Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

143 files changed, 35981 insertions, 20947 deletions

diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig
index 0a75be027afa..d1b23067619f 100644
--- a/drivers/net/wireless/ath/Kconfig
+++ b/drivers/net/wireless/ath/Kconfig
@@ -24,6 +24,6 @@ config ATH_DEBUG
 
 source "drivers/net/wireless/ath/ath5k/Kconfig"
 source "drivers/net/wireless/ath/ath9k/Kconfig"
-source "drivers/net/wireless/ath/ar9170/Kconfig"
+source "drivers/net/wireless/ath/carl9170/Kconfig"
 
 endif
diff --git a/drivers/net/wireless/ath/Makefile b/drivers/net/wireless/ath/Makefile
index 8113a5042afa..0e8f528c81c0 100644
--- a/drivers/net/wireless/ath/Makefile
+++ b/drivers/net/wireless/ath/Makefile
@@ -1,11 +1,12 @@
 obj-$(CONFIG_ATH5K)             += ath5k/
 obj-$(CONFIG_ATH9K_HW)          += ath9k/
-obj-$(CONFIG_AR9170_USB)        += ar9170/
+obj-$(CONFIG_CARL9170)          += carl9170/
 
 obj-$(CONFIG_ATH_COMMON)        += ath.o
 
 ath-objs :=     main.o \
                 regd.o \
-                hw.o
+                hw.o \
+                key.o
 
 ath-$(CONFIG_ATH_DEBUG) += debug.o
diff --git a/drivers/net/wireless/ath/ar9170/Kconfig b/drivers/net/wireless/ath/ar9170/Kconfig
deleted file mode 100644
index d7a4799d20fb..000000000000
--- a/drivers/net/wireless/ath/ar9170/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-config AR9170_USB
-        tristate "Atheros AR9170 802.11n USB support"
-        depends on USB && MAC80211
-        select FW_LOADER
-        help
-          This is a driver for the Atheros "otus" 802.11n USB devices.
-
-          These devices require additional firmware (2 files).
-          For now, these files can be downloaded from here:
-
-          http://wireless.kernel.org/en/users/Drivers/ar9170
-
-          If you choose to build a module, it'll be called ar9170usb.
-
-config AR9170_LEDS
-        bool
-        depends on AR9170_USB && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = AR9170_USB)
-        default y
diff --git a/drivers/net/wireless/ath/ar9170/Makefile b/drivers/net/wireless/ath/ar9170/Makefile
deleted file mode 100644
index 8d91c7ee3215..000000000000
--- a/drivers/net/wireless/ath/ar9170/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-ar9170usb-objs := usb.o main.o cmd.o mac.o phy.o led.o
-
-obj-$(CONFIG_AR9170_USB) += ar9170usb.o
diff --git a/drivers/net/wireless/ath/ar9170/ar9170.h b/drivers/net/wireless/ath/ar9170/ar9170.h
deleted file mode 100644
index 4f845f80c098..000000000000
--- a/drivers/net/wireless/ath/ar9170/ar9170.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * Driver specific definitions
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#ifndef __AR9170_H
-#define __AR9170_H
-
-#include <linux/completion.h>
-#include <linux/spinlock.h>
-#include <net/cfg80211.h>
-#include <net/mac80211.h>
-#ifdef CONFIG_AR9170_LEDS
-#include <linux/leds.h>
-#endif /* CONFIG_AR9170_LEDS */
-#include "eeprom.h"
-#include "hw.h"
-
-#include "../regd.h"
-
-#define PAYLOAD_MAX     (AR9170_MAX_CMD_LEN/4 - 1)
-
-enum ar9170_bw {
-        AR9170_BW_20,
-        AR9170_BW_40_BELOW,
-        AR9170_BW_40_ABOVE,
-
-        __AR9170_NUM_BW,
-};
-
-static inline enum ar9170_bw nl80211_to_ar9170(enum nl80211_channel_type type)
-{
-        switch (type) {
-        case NL80211_CHAN_NO_HT:
-        case NL80211_CHAN_HT20:
-                return AR9170_BW_20;
-        case NL80211_CHAN_HT40MINUS:
-                return AR9170_BW_40_BELOW;
-        case NL80211_CHAN_HT40PLUS:
-                return AR9170_BW_40_ABOVE;
-        default:
-                BUG();
-        }
-}
-
-enum ar9170_rf_init_mode {
-        AR9170_RFI_NONE,
-        AR9170_RFI_WARM,
-        AR9170_RFI_COLD,
-};
-
-#define AR9170_MAX_RX_BUFFER_SIZE               8192
-
-#ifdef CONFIG_AR9170_LEDS
-struct ar9170;
-
-struct ar9170_led {
-        struct ar9170 *ar;
-        struct led_classdev l;
-        char name[32];
-        unsigned int toggled;
-        bool last_state;
-        bool registered;
-};
-
-#endif /* CONFIG_AR9170_LEDS */
-
-enum ar9170_device_state {
-        AR9170_UNKNOWN_STATE,
-        AR9170_STOPPED,
-        AR9170_IDLE,
-        AR9170_STARTED,
-};
-
-struct ar9170_rxstream_mpdu_merge {
-        struct ar9170_rx_head plcp;
-        bool has_plcp;
-};
-
-struct ar9170_tx_queue_stats {
-        unsigned int len;
-        unsigned int limit;
-        unsigned int count;
-};
-
-#define AR9170_QUEUE_TIMEOUT            64
-#define AR9170_TX_TIMEOUT               8
-#define AR9170_JANITOR_DELAY            128
-#define AR9170_TX_INVALID_RATE          0xffffffff
-
-#define AR9170_NUM_TX_LIMIT_HARD        AR9170_TXQ_DEPTH
-#define AR9170_NUM_TX_LIMIT_SOFT        (AR9170_TXQ_DEPTH - 10)
-
-struct ar9170 {
-        struct ieee80211_hw *hw;
-        struct ath_common common;
-        struct mutex mutex;
-        enum ar9170_device_state state;
-        bool registered;
-        unsigned long bad_hw_nagger;
-
-        int (*open)(struct ar9170 *);
-        void (*stop)(struct ar9170 *);
-        int (*tx)(struct ar9170 *, struct sk_buff *);
-        int (*exec_cmd)(struct ar9170 *, enum ar9170_cmd, u32 ,
-                        void *, u32 , void *);
-        void (*callback_cmd)(struct ar9170 *, u32 , void *);
-        int (*flush)(struct ar9170 *);
-
-        /* interface mode settings */
-        struct ieee80211_vif *vif;
-
-        /* beaconing */
-        struct sk_buff *beacon;
-        struct work_struct beacon_work;
-        bool enable_beacon;
-
-        /* cryptographic engine */
-        u64 usedkeys;
-        bool rx_software_decryption;
-        bool disable_offload;
-
-        /* filter settings */
-        u64 cur_mc_hash;
-        u32 cur_filter;
-        unsigned int filter_state;
-        bool sniffer_enabled;
-
-        /* PHY */
-        struct ieee80211_channel *channel;
-        int noise[4];
-
-        /* power calibration data */
-        u8 power_5G_leg[4];
-        u8 power_2G_cck[4];
-        u8 power_2G_ofdm[4];
-        u8 power_5G_ht20[8];
-        u8 power_5G_ht40[8];
-        u8 power_2G_ht20[8];
-        u8 power_2G_ht40[8];
-
-        u8 phy_heavy_clip;
-
-#ifdef CONFIG_AR9170_LEDS
-        struct delayed_work led_work;
-        struct ar9170_led leds[AR9170_NUM_LEDS];
-#endif /* CONFIG_AR9170_LEDS */
-
-        /* qos queue settings */
-        spinlock_t tx_stats_lock;
-        struct ar9170_tx_queue_stats tx_stats[5];
-        struct ieee80211_tx_queue_params edcf[5];
-
-        spinlock_t cmdlock;
-        __le32 cmdbuf[PAYLOAD_MAX + 1];
-
-        /* MAC statistics */
-        struct ieee80211_low_level_stats stats;
-
-        /* EEPROM */
-        struct ar9170_eeprom eeprom;
-
-        /* tx queues - as seen by hw - */
-        struct sk_buff_head tx_pending[__AR9170_NUM_TXQ];
-        struct sk_buff_head tx_status[__AR9170_NUM_TXQ];
-        struct delayed_work tx_janitor;
-
-        /* rxstream mpdu merge */
-        struct ar9170_rxstream_mpdu_merge rx_mpdu;
-        struct sk_buff *rx_failover;
-        int rx_failover_missing;
-
-        /* (cached) HW A-MPDU settings */
-        u8 global_ampdu_density;
-        u8 global_ampdu_factor;
-};
-
-struct ar9170_tx_info {
-        unsigned long timeout;
-};
-
-#define IS_STARTED(a)           (((struct ar9170 *)a)->state >= AR9170_STARTED)
-#define IS_ACCEPTING_CMD(a)     (((struct ar9170 *)a)->state >= AR9170_IDLE)
-
-/* exported interface */
-void *ar9170_alloc(size_t priv_size);
-int ar9170_register(struct ar9170 *ar, struct device *pdev);
-void ar9170_rx(struct ar9170 *ar, struct sk_buff *skb);
-void ar9170_unregister(struct ar9170 *ar);
-void ar9170_tx_callback(struct ar9170 *ar, struct sk_buff *skb);
-void ar9170_handle_command_response(struct ar9170 *ar, void *buf, u32 len);
-int ar9170_nag_limiter(struct ar9170 *ar);
-
-/* MAC */
-int ar9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
-int ar9170_init_mac(struct ar9170 *ar);
-int ar9170_set_qos(struct ar9170 *ar);
-int ar9170_update_multicast(struct ar9170 *ar, const u64 mc_hast);
-int ar9170_update_frame_filter(struct ar9170 *ar, const u32 filter);
-int ar9170_set_operating_mode(struct ar9170 *ar);
-int ar9170_set_beacon_timers(struct ar9170 *ar);
-int ar9170_set_dyn_sifs_ack(struct ar9170 *ar);
-int ar9170_set_slot_time(struct ar9170 *ar);
-int ar9170_set_basic_rates(struct ar9170 *ar);
-int ar9170_set_hwretry_limit(struct ar9170 *ar, u32 max_retry);
-int ar9170_update_beacon(struct ar9170 *ar);
-void ar9170_new_beacon(struct work_struct *work);
-int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
-                      u8 keyidx, u8 *keydata, int keylen);
-int ar9170_disable_key(struct ar9170 *ar, u8 id);
-
-/* LEDs */
-#ifdef CONFIG_AR9170_LEDS
-int ar9170_register_leds(struct ar9170 *ar);
-void ar9170_unregister_leds(struct ar9170 *ar);
-#endif /* CONFIG_AR9170_LEDS */
-int ar9170_init_leds(struct ar9170 *ar);
-int ar9170_set_leds_state(struct ar9170 *ar, u32 led_state);
-
-/* PHY / RF */
-int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band);
-int ar9170_init_rf(struct ar9170 *ar);
-int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
-                       enum ar9170_rf_init_mode rfi, enum ar9170_bw bw);
-
-#endif /* __AR9170_H */
diff --git a/drivers/net/wireless/ath/ar9170/cmd.c b/drivers/net/wireless/ath/ar9170/cmd.c
deleted file mode 100644
index 4604de09a8b2..000000000000
--- a/drivers/net/wireless/ath/ar9170/cmd.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * Basic HW register/memory/command access functions
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "ar9170.h"
-#include "cmd.h"
-
-int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len)
-{
-        int err;
-
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return 0;
-
-        err = ar->exec_cmd(ar, AR9170_CMD_WMEM, len, (u8 *) data, 0, NULL);
-        if (err)
-                wiphy_debug(ar->hw->wiphy, "writing memory failed\n");
-        return err;
-}
-
-int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
-{
-        __le32 buf[2] = {
-                cpu_to_le32(reg),
-                cpu_to_le32(val),
-        };
-        int err;
-
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return 0;
-
-        err = ar->exec_cmd(ar, AR9170_CMD_WREG, sizeof(buf),
-                           (u8 *) buf, 0, NULL);
-        if (err)
-                wiphy_debug(ar->hw->wiphy, "writing reg %#x (val %#x) failed\n",
-                            reg, val);
-        return err;
-}
-
-int ar9170_read_mreg(struct ar9170 *ar, int nregs, const u32 *regs, u32 *out)
-{
-        int i, err;
-        __le32 *offs, *res;
-
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return 0;
-
-        /* abuse "out" for the register offsets, must be same length */
-        offs = (__le32 *)out;
-        for (i = 0; i < nregs; i++)
-                offs[i] = cpu_to_le32(regs[i]);
-
-        /* also use the same buffer for the input */
-        res = (__le32 *)out;
-
-        err = ar->exec_cmd(ar, AR9170_CMD_RREG,
-                           4 * nregs, (u8 *)offs,
-                           4 * nregs, (u8 *)res);
-        if (err)
-                return err;
-
-        /* convert result to cpu endian */
-        for (i = 0; i < nregs; i++)
-                out[i] = le32_to_cpu(res[i]);
-
-        return 0;
-}
-
-int ar9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val)
-{
-        return ar9170_read_mreg(ar, 1, &reg, val);
-}
-
-int ar9170_echo_test(struct ar9170 *ar, u32 v)
-{
-        __le32 echobuf = cpu_to_le32(v);
-        __le32 echores;
-        int err;
-
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return -ENODEV;
-
-        err = ar->exec_cmd(ar, AR9170_CMD_ECHO,
-                           4, (u8 *)&echobuf,
-                           4, (u8 *)&echores);
-        if (err)
-                return err;
-
-        if (echobuf != echores)
-                return -EINVAL;
-
-        return 0;
-}
diff --git a/drivers/net/wireless/ath/ar9170/cmd.h b/drivers/net/wireless/ath/ar9170/cmd.h
deleted file mode 100644
index ec8134b4b949..000000000000
--- a/drivers/net/wireless/ath/ar9170/cmd.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * Basic HW register/memory/command access functions
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#ifndef __CMD_H
-#define __CMD_H
-
-#include "ar9170.h"
-
-/* basic HW access */
-int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len);
-int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val);
-int ar9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val);
-int ar9170_read_mreg(struct ar9170 *ar, int nregs, const u32 *regs, u32 *out);
-int ar9170_echo_test(struct ar9170 *ar, u32 v);
-
-/*
- * Macros to facilitate writing multiple registers in a single
- * write-combining USB command. Note that when the first group
- * fails the whole thing will fail without any others attempted,
- * but you won't know which write in the group failed.
- */
-#define ar9170_regwrite_begin(ar)                                       \
-do {                                                                    \
-        int __nreg = 0, __err = 0;                                      \
-        struct ar9170 *__ar = ar;
-
-#define ar9170_regwrite(r, v) do {                                      \
-        __ar->cmdbuf[2 * __nreg + 1] = cpu_to_le32(r);                  \
-        __ar->cmdbuf[2 * __nreg + 2] = cpu_to_le32(v);                  \
-        __nreg++;                                                       \
-        if ((__nreg >= PAYLOAD_MAX/2)) {                                \
-                if (IS_ACCEPTING_CMD(__ar))                             \
-                        __err = ar->exec_cmd(__ar, AR9170_CMD_WREG,     \
-                                             8 * __nreg,                \
-                                             (u8 *) &__ar->cmdbuf[1],   \
-                                             0, NULL);                  \
-                __nreg = 0;                                             \
-                if (__err)                                              \
-                        goto __regwrite_out;                            \
-        }                                                               \
-} while (0)
-
-#define ar9170_regwrite_finish()                                        \
-__regwrite_out :                                                        \
-        if (__nreg) {                                                   \
-                if (IS_ACCEPTING_CMD(__ar))                             \
-                        __err = ar->exec_cmd(__ar, AR9170_CMD_WREG,     \
-                                             8 * __nreg,                \
-                                             (u8 *) &__ar->cmdbuf[1],   \
-                                             0, NULL);                  \
-                __nreg = 0;                                             \
-        }
-
-#define ar9170_regwrite_result()                                        \
-        __err;                                                          \
-} while (0);
-
-#endif /* __CMD_H */
diff --git a/drivers/net/wireless/ath/ar9170/hw.h b/drivers/net/wireless/ath/ar9170/hw.h
deleted file mode 100644
index 06f1f3c951a4..000000000000
--- a/drivers/net/wireless/ath/ar9170/hw.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * Hardware-specific definitions
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#ifndef __AR9170_HW_H
-#define __AR9170_HW_H
-
-#define AR9170_MAX_CMD_LEN      64
-
-enum ar9170_cmd {
-        AR9170_CMD_RREG         = 0x00,
-        AR9170_CMD_WREG         = 0x01,
-        AR9170_CMD_RMEM         = 0x02,
-        AR9170_CMD_WMEM         = 0x03,
-        AR9170_CMD_BITAND       = 0x04,
-        AR9170_CMD_BITOR        = 0x05,
-        AR9170_CMD_EKEY         = 0x28,
-        AR9170_CMD_DKEY         = 0x29,
-        AR9170_CMD_FREQUENCY    = 0x30,
-        AR9170_CMD_RF_INIT      = 0x31,
-        AR9170_CMD_SYNTH        = 0x32,
-        AR9170_CMD_FREQ_START   = 0x33,
-        AR9170_CMD_ECHO         = 0x80,
-        AR9170_CMD_TALLY        = 0x81,
-        AR9170_CMD_TALLY_APD    = 0x82,
-        AR9170_CMD_CONFIG       = 0x83,
-        AR9170_CMD_RESET        = 0x90,
-        AR9170_CMD_DKRESET      = 0x91,
-        AR9170_CMD_DKTX_STATUS  = 0x92,
-        AR9170_CMD_FDC          = 0xA0,
-        AR9170_CMD_WREEPROM     = 0xB0,
-        AR9170_CMD_WFLASH       = 0xB0,
-        AR9170_CMD_FLASH_ERASE  = 0xB1,
-        AR9170_CMD_FLASH_PROG   = 0xB2,
-        AR9170_CMD_FLASH_CHKSUM = 0xB3,
-        AR9170_CMD_FLASH_READ   = 0xB4,
-        AR9170_CMD_FW_DL_INIT   = 0xB5,
-        AR9170_CMD_MEM_WREEPROM = 0xBB,
-};
-
-/* endpoints */
-#define AR9170_EP_TX                            1
-#define AR9170_EP_RX                            2
-#define AR9170_EP_IRQ                           3
-#define AR9170_EP_CMD                           4
-
-#define AR9170_EEPROM_START                     0x1600
-
-#define AR9170_GPIO_REG_BASE                    0x1d0100
-#define AR9170_GPIO_REG_PORT_TYPE               AR9170_GPIO_REG_BASE
-#define AR9170_GPIO_REG_DATA                    (AR9170_GPIO_REG_BASE + 4)
-#define AR9170_NUM_LEDS                         2
-
-
-#define AR9170_USB_REG_BASE                     0x1e1000
-#define AR9170_USB_REG_DMA_CTL                  (AR9170_USB_REG_BASE + 0x108)
-#define         AR9170_DMA_CTL_ENABLE_TO_DEVICE         0x1
-#define         AR9170_DMA_CTL_ENABLE_FROM_DEVICE       0x2
-#define         AR9170_DMA_CTL_HIGH_SPEED               0x4
-#define         AR9170_DMA_CTL_PACKET_MODE              0x8
-
-#define AR9170_USB_REG_MAX_AGG_UPLOAD           (AR9170_USB_REG_BASE + 0x110)
-#define AR9170_USB_REG_UPLOAD_TIME_CTL          (AR9170_USB_REG_BASE + 0x114)
-
-
-
-#define AR9170_MAC_REG_BASE                     0x1c3000
-
-#define AR9170_MAC_REG_TSF_L                    (AR9170_MAC_REG_BASE + 0x514)
-#define AR9170_MAC_REG_TSF_H                    (AR9170_MAC_REG_BASE + 0x518)
-
-#define AR9170_MAC_REG_ATIM_WINDOW              (AR9170_MAC_REG_BASE + 0x51C)
-#define AR9170_MAC_REG_BCN_PERIOD               (AR9170_MAC_REG_BASE + 0x520)
-#define AR9170_MAC_REG_PRETBTT                  (AR9170_MAC_REG_BASE + 0x524)
-
-#define AR9170_MAC_REG_MAC_ADDR_L               (AR9170_MAC_REG_BASE + 0x610)
-#define AR9170_MAC_REG_MAC_ADDR_H               (AR9170_MAC_REG_BASE + 0x614)
-#define AR9170_MAC_REG_BSSID_L                  (AR9170_MAC_REG_BASE + 0x618)
-#define AR9170_MAC_REG_BSSID_H                  (AR9170_MAC_REG_BASE + 0x61c)
-
-#define AR9170_MAC_REG_GROUP_HASH_TBL_L         (AR9170_MAC_REG_BASE + 0x624)
-#define AR9170_MAC_REG_GROUP_HASH_TBL_H         (AR9170_MAC_REG_BASE + 0x628)
-
-#define AR9170_MAC_REG_RX_TIMEOUT               (AR9170_MAC_REG_BASE + 0x62C)
-
-#define AR9170_MAC_REG_BASIC_RATE               (AR9170_MAC_REG_BASE + 0x630)
-#define AR9170_MAC_REG_MANDATORY_RATE           (AR9170_MAC_REG_BASE + 0x634)
-#define AR9170_MAC_REG_RTS_CTS_RATE             (AR9170_MAC_REG_BASE + 0x638)
-#define AR9170_MAC_REG_BACKOFF_PROTECT          (AR9170_MAC_REG_BASE + 0x63c)
-#define AR9170_MAC_REG_RX_THRESHOLD             (AR9170_MAC_REG_BASE + 0x640)
-#define AR9170_MAC_REG_RX_PE_DELAY              (AR9170_MAC_REG_BASE + 0x64C)
-
-#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK         (AR9170_MAC_REG_BASE + 0x658)
-#define AR9170_MAC_REG_SNIFFER                  (AR9170_MAC_REG_BASE + 0x674)
-#define         AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC   BIT(0)
-#define         AR9170_MAC_REG_SNIFFER_DEFAULTS         0x02000000
-#define AR9170_MAC_REG_ENCRYPTION               (AR9170_MAC_REG_BASE + 0x678)
-#define         AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE   BIT(3)
-#define         AR9170_MAC_REG_ENCRYPTION_DEFAULTS      0x70
-
-#define AR9170_MAC_REG_MISC_680                 (AR9170_MAC_REG_BASE + 0x680)
-#define AR9170_MAC_REG_TX_UNDERRUN              (AR9170_MAC_REG_BASE + 0x688)
-
-#define AR9170_MAC_REG_FRAMETYPE_FILTER         (AR9170_MAC_REG_BASE + 0x68c)
-#define         AR9170_MAC_REG_FTF_ASSOC_REQ            BIT(0)
-#define         AR9170_MAC_REG_FTF_ASSOC_RESP           BIT(1)
-#define         AR9170_MAC_REG_FTF_REASSOC_REQ          BIT(2)
-#define         AR9170_MAC_REG_FTF_REASSOC_RESP         BIT(3)
-#define         AR9170_MAC_REG_FTF_PRB_REQ              BIT(4)
-#define         AR9170_MAC_REG_FTF_PRB_RESP             BIT(5)
-#define         AR9170_MAC_REG_FTF_BIT6                 BIT(6)
-#define         AR9170_MAC_REG_FTF_BIT7                 BIT(7)
-#define         AR9170_MAC_REG_FTF_BEACON               BIT(8)
-#define         AR9170_MAC_REG_FTF_ATIM                 BIT(9)
-#define         AR9170_MAC_REG_FTF_DEASSOC              BIT(10)
-#define         AR9170_MAC_REG_FTF_AUTH                 BIT(11)
-#define         AR9170_MAC_REG_FTF_DEAUTH               BIT(12)
-#define         AR9170_MAC_REG_FTF_BIT13                BIT(13)
-#define         AR9170_MAC_REG_FTF_BIT14                BIT(14)
-#define         AR9170_MAC_REG_FTF_BIT15                BIT(15)
-#define         AR9170_MAC_REG_FTF_BAR                  BIT(24)
-#define         AR9170_MAC_REG_FTF_BA                   BIT(25)
-#define         AR9170_MAC_REG_FTF_PSPOLL               BIT(26)
-#define         AR9170_MAC_REG_FTF_RTS                  BIT(27)
-#define         AR9170_MAC_REG_FTF_CTS                  BIT(28)
-#define         AR9170_MAC_REG_FTF_ACK                  BIT(29)
-#define         AR9170_MAC_REG_FTF_CFE                  BIT(30)
-#define         AR9170_MAC_REG_FTF_CFE_ACK              BIT(31)
-#define         AR9170_MAC_REG_FTF_DEFAULTS             0x0700ffff
-#define         AR9170_MAC_REG_FTF_MONITOR              0xfd00ffff
-
-#define AR9170_MAC_REG_RX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6A0)
-#define AR9170_MAC_REG_RX_CRC32                 (AR9170_MAC_REG_BASE + 0x6A4)
-#define AR9170_MAC_REG_RX_CRC16                 (AR9170_MAC_REG_BASE + 0x6A8)
-#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI    (AR9170_MAC_REG_BASE + 0x6AC)
-#define AR9170_MAC_REG_RX_OVERRUN               (AR9170_MAC_REG_BASE + 0x6B0)
-#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL    (AR9170_MAC_REG_BASE + 0x6BC)
-#define AR9170_MAC_REG_TX_RETRY                 (AR9170_MAC_REG_BASE + 0x6CC)
-#define AR9170_MAC_REG_TX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6F4)
-
-
-#define AR9170_MAC_REG_ACK_EXTENSION            (AR9170_MAC_REG_BASE + 0x690)
-#define AR9170_MAC_REG_EIFS_AND_SIFS            (AR9170_MAC_REG_BASE + 0x698)
-
-#define AR9170_MAC_REG_SLOT_TIME                (AR9170_MAC_REG_BASE + 0x6F0)
-
-#define AR9170_MAC_REG_POWERMANAGEMENT          (AR9170_MAC_REG_BASE + 0x700)
-#define         AR9170_MAC_REG_POWERMGT_IBSS            0xe0
-#define         AR9170_MAC_REG_POWERMGT_AP              0xa1
-#define         AR9170_MAC_REG_POWERMGT_STA             0x2
-#define         AR9170_MAC_REG_POWERMGT_AP_WDS          0x3
-#define         AR9170_MAC_REG_POWERMGT_DEFAULTS        (0xf << 24)
-
-#define AR9170_MAC_REG_ROLL_CALL_TBL_L          (AR9170_MAC_REG_BASE + 0x704)
-#define AR9170_MAC_REG_ROLL_CALL_TBL_H          (AR9170_MAC_REG_BASE + 0x708)
-
-#define AR9170_MAC_REG_AC0_CW                   (AR9170_MAC_REG_BASE + 0xB00)
-#define AR9170_MAC_REG_AC1_CW                   (AR9170_MAC_REG_BASE + 0xB04)
-#define AR9170_MAC_REG_AC2_CW                   (AR9170_MAC_REG_BASE + 0xB08)
-#define AR9170_MAC_REG_AC3_CW                   (AR9170_MAC_REG_BASE + 0xB0C)
-#define AR9170_MAC_REG_AC4_CW                   (AR9170_MAC_REG_BASE + 0xB10)
-#define AR9170_MAC_REG_AC1_AC0_AIFS             (AR9170_MAC_REG_BASE + 0xB14)
-#define AR9170_MAC_REG_AC3_AC2_AIFS             (AR9170_MAC_REG_BASE + 0xB18)
-
-#define AR9170_MAC_REG_RETRY_MAX                (AR9170_MAC_REG_BASE + 0xB28)
-
-#define AR9170_MAC_REG_FCS_SELECT               (AR9170_MAC_REG_BASE + 0xBB0)
-#define         AR9170_MAC_FCS_SWFCS            0x1
-#define         AR9170_MAC_FCS_FIFO_PROT        0x4
-
-
-#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND      (AR9170_MAC_REG_BASE + 0xB30)
-
-#define AR9170_MAC_REG_AC1_AC0_TXOP             (AR9170_MAC_REG_BASE + 0xB44)
-#define AR9170_MAC_REG_AC3_AC2_TXOP             (AR9170_MAC_REG_BASE + 0xB48)
-
-#define AR9170_MAC_REG_AMPDU_FACTOR             (AR9170_MAC_REG_BASE + 0xB9C)
-#define AR9170_MAC_REG_AMPDU_DENSITY            (AR9170_MAC_REG_BASE + 0xBA0)
-
-#define AR9170_MAC_REG_ACK_TABLE                (AR9170_MAC_REG_BASE + 0xC00)
-#define AR9170_MAC_REG_AMPDU_RX_THRESH          (AR9170_MAC_REG_BASE + 0xC50)
-
-#define AR9170_MAC_REG_TXRX_MPI                 (AR9170_MAC_REG_BASE + 0xD7C)
-#define         AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
-#define         AR9170_MAC_TXRX_MPI_TX_TO_MASK  0x0000fff0
-#define         AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000
-#define         AR9170_MAC_TXRX_MPI_RX_TO_MASK  0xfff00000
-
-#define AR9170_MAC_REG_BCN_ADDR                 (AR9170_MAC_REG_BASE + 0xD84)
-#define AR9170_MAC_REG_BCN_LENGTH               (AR9170_MAC_REG_BASE + 0xD88)
-#define AR9170_MAC_REG_BCN_PLCP                 (AR9170_MAC_REG_BASE + 0xD90)
-#define AR9170_MAC_REG_BCN_CTRL                 (AR9170_MAC_REG_BASE + 0xD94)
-#define AR9170_MAC_REG_BCN_HT1                  (AR9170_MAC_REG_BASE + 0xDA0)
-#define AR9170_MAC_REG_BCN_HT2                  (AR9170_MAC_REG_BASE + 0xDA4)
-
-
-#define AR9170_PWR_REG_BASE                     0x1D4000
-
-#define AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
-#define         AR9170_PWR_CLK_AHB_40MHZ        0
-#define         AR9170_PWR_CLK_AHB_20_22MHZ     1
-#define         AR9170_PWR_CLK_AHB_40_44MHZ     2
-#define         AR9170_PWR_CLK_AHB_80_88MHZ     3
-#define         AR9170_PWR_CLK_DAC_160_INV_DLY  0x70
-
-
-/* put beacon here in memory */
-#define AR9170_BEACON_BUFFER_ADDRESS            0x117900
-
-
-struct ar9170_tx_control {
-        __le16 length;
-        __le16 mac_control;
-        __le32 phy_control;
-        u8 frame_data[0];
-} __packed;
-
-/* these are either-or */
-#define AR9170_TX_MAC_PROT_RTS                  0x0001
-#define AR9170_TX_MAC_PROT_CTS                  0x0002
-
-#define AR9170_TX_MAC_NO_ACK                    0x0004
-/* if unset, MAC will only do SIFS space before frame */
-#define AR9170_TX_MAC_BACKOFF                   0x0008
-#define AR9170_TX_MAC_BURST                     0x0010
-#define AR9170_TX_MAC_AGGR                      0x0020
-
-/* encryption is a two-bit field */
-#define AR9170_TX_MAC_ENCR_NONE                 0x0000
-#define AR9170_TX_MAC_ENCR_RC4                  0x0040
-#define AR9170_TX_MAC_ENCR_CENC                 0x0080
-#define AR9170_TX_MAC_ENCR_AES                  0x00c0
-
-#define AR9170_TX_MAC_MMIC                      0x0100
-#define AR9170_TX_MAC_HW_DURATION               0x0200
-#define AR9170_TX_MAC_QOS_SHIFT                 10
-#define AR9170_TX_MAC_QOS_MASK                  (3 << AR9170_TX_MAC_QOS_SHIFT)
-#define AR9170_TX_MAC_AGGR_QOS_BIT1             0x0400
-#define AR9170_TX_MAC_AGGR_QOS_BIT2             0x0800
-#define AR9170_TX_MAC_DISABLE_TXOP              0x1000
-#define AR9170_TX_MAC_TXOP_RIFS                 0x2000
-#define AR9170_TX_MAC_IMM_AMPDU                 0x4000
-#define AR9170_TX_MAC_RATE_PROBE                0x8000
-
-/* either-or */
-#define AR9170_TX_PHY_MOD_MASK                  0x00000003
-#define AR9170_TX_PHY_MOD_CCK                   0x00000000
-#define AR9170_TX_PHY_MOD_OFDM                  0x00000001
-#define AR9170_TX_PHY_MOD_HT                    0x00000002
-
-/* depends on modulation */
-#define AR9170_TX_PHY_SHORT_PREAMBLE            0x00000004
-#define AR9170_TX_PHY_GREENFIELD                0x00000004
-
-#define AR9170_TX_PHY_BW_SHIFT                  3
-#define AR9170_TX_PHY_BW_MASK                   (3 << AR9170_TX_PHY_BW_SHIFT)
-#define AR9170_TX_PHY_BW_20MHZ                  0
-#define AR9170_TX_PHY_BW_40MHZ                  2
-#define AR9170_TX_PHY_BW_40MHZ_DUP              3
-
-#define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT       6
-#define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK        (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT)
-
-#define AR9170_TX_PHY_TX_PWR_SHIFT              9
-#define AR9170_TX_PHY_TX_PWR_MASK               (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT)
-
-/* not part of the hw-spec */
-#define AR9170_TX_PHY_QOS_SHIFT                 25
-#define AR9170_TX_PHY_QOS_MASK                  (3 << AR9170_TX_PHY_QOS_SHIFT)
-
-#define AR9170_TX_PHY_TXCHAIN_SHIFT             15
-#define AR9170_TX_PHY_TXCHAIN_MASK              (7 << AR9170_TX_PHY_TXCHAIN_SHIFT)
-#define AR9170_TX_PHY_TXCHAIN_1                 1
-/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
-#define AR9170_TX_PHY_TXCHAIN_2                 5
-
-#define AR9170_TX_PHY_MCS_SHIFT                 18
-#define AR9170_TX_PHY_MCS_MASK                  (0x7f << AR9170_TX_PHY_MCS_SHIFT)
-
-#define AR9170_TX_PHY_SHORT_GI                  0x80000000
-
-#define AR5416_MAX_RATE_POWER                   63
-
-struct ar9170_rx_head {
-        u8 plcp[12];
-} __packed;
-
-struct ar9170_rx_phystatus {
-        union {
-                struct {
-                        u8 rssi_ant0, rssi_ant1, rssi_ant2,
-                           rssi_ant0x, rssi_ant1x, rssi_ant2x,
-                           rssi_combined;
-                } __packed;
-                u8 rssi[7];
-        } __packed;
-
-        u8 evm_stream0[6], evm_stream1[6];
-        u8 phy_err;
-} __packed;
-
-struct ar9170_rx_macstatus {
-        u8 SAidx, DAidx;
-        u8 error;
-        u8 status;
-} __packed;
-
-#define AR9170_ENC_ALG_NONE                     0x0
-#define AR9170_ENC_ALG_WEP64                    0x1
-#define AR9170_ENC_ALG_TKIP                     0x2
-#define AR9170_ENC_ALG_AESCCMP                  0x4
-#define AR9170_ENC_ALG_WEP128                   0x5
-#define AR9170_ENC_ALG_WEP256                   0x6
-#define AR9170_ENC_ALG_CENC                     0x7
-
-#define AR9170_RX_ENC_SOFTWARE                  0x8
-
-static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
-{
-        return (t->SAidx & 0xc0) >> 4 |
-               (t->DAidx & 0xc0) >> 6;
-}
-
-#define AR9170_RX_STATUS_MODULATION_MASK        0x03
-#define AR9170_RX_STATUS_MODULATION_CCK         0x00
-#define AR9170_RX_STATUS_MODULATION_OFDM        0x01
-#define AR9170_RX_STATUS_MODULATION_HT          0x02
-#define AR9170_RX_STATUS_MODULATION_DUPOFDM     0x03
-
-/* depends on modulation */
-#define AR9170_RX_STATUS_SHORT_PREAMBLE         0x08
-#define AR9170_RX_STATUS_GREENFIELD             0x08
-
-#define AR9170_RX_STATUS_MPDU_MASK              0x30
-#define AR9170_RX_STATUS_MPDU_SINGLE            0x00
-#define AR9170_RX_STATUS_MPDU_FIRST             0x20
-#define AR9170_RX_STATUS_MPDU_MIDDLE            0x30
-#define AR9170_RX_STATUS_MPDU_LAST              0x10
-
-#define AR9170_RX_ERROR_RXTO                    0x01
-#define AR9170_RX_ERROR_OVERRUN                 0x02
-#define AR9170_RX_ERROR_DECRYPT                 0x04
-#define AR9170_RX_ERROR_FCS                     0x08
-#define AR9170_RX_ERROR_WRONG_RA                0x10
-#define AR9170_RX_ERROR_PLCP                    0x20
-#define AR9170_RX_ERROR_MMIC                    0x40
-#define AR9170_RX_ERROR_FATAL                   0x80
-
-struct ar9170_cmd_tx_status {
-        u8 dst[ETH_ALEN];
-        __le32 rate;
-        __le16 status;
-} __packed;
-
-#define AR9170_TX_STATUS_COMPLETE               0x00
-#define AR9170_TX_STATUS_RETRY                  0x01
-#define AR9170_TX_STATUS_FAILED                 0x02
-
-struct ar9170_cmd_ba_failed_count {
-        __le16 failed;
-        __le16 rate;
-} __packed;
-
-struct ar9170_cmd_response {
-        u8 flag;
-        u8 type;
-        __le16 padding;
-
-        union {
-                struct ar9170_cmd_tx_status             tx_status;
-                struct ar9170_cmd_ba_failed_count       ba_fail_cnt;
-                u8 data[0];
-        };
-} __packed;
-
-/* QoS */
-
-/* mac80211 queue to HW/FW map */
-static const u8 ar9170_qos_hwmap[4] = { 3, 2, 0, 1 };
-
-/* HW/FW queue to mac80211 map */
-static const u8 ar9170_qos_mac80211map[4] = { 2, 3, 1, 0 };
-
-enum ar9170_txq {
-        AR9170_TXQ_BE,
-        AR9170_TXQ_BK,
-        AR9170_TXQ_VI,
-        AR9170_TXQ_VO,
-
-        __AR9170_NUM_TXQ,
-};
-
-#define AR9170_TXQ_DEPTH        32
-#define AR9170_TX_MAX_PENDING   128
-#define AR9170_RX_STREAM_MAX_SIZE 65535
-
-#endif /* __AR9170_HW_H */
diff --git a/drivers/net/wireless/ath/ar9170/mac.c b/drivers/net/wireless/ath/ar9170/mac.c
deleted file mode 100644
index 857e86104295..000000000000
--- a/drivers/net/wireless/ath/ar9170/mac.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * MAC programming
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <asm/unaligned.h>
-
-#include "ar9170.h"
-#include "cmd.h"
-
-int ar9170_set_dyn_sifs_ack(struct ar9170 *ar)
-{
-        u32 val;
-
-        if (conf_is_ht40(&ar->hw->conf))
-                val = 0x010a;
-        else {
-                if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
-                        val = 0x105;
-                else
-                        val = 0x104;
-        }
-
-        return ar9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val);
-}
-
-int ar9170_set_slot_time(struct ar9170 *ar)
-{
-        u32 slottime = 20;
-
-        if (!ar->vif)
-                return 0;
-
-        if ((ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ) ||
-            ar->vif->bss_conf.use_short_slot)
-                slottime = 9;
-
-        return ar9170_write_reg(ar, AR9170_MAC_REG_SLOT_TIME, slottime << 10);
-}
-
-int ar9170_set_basic_rates(struct ar9170 *ar)
-{
-        u8 cck, ofdm;
-
-        if (!ar->vif)
-                return 0;
-
-        ofdm = ar->vif->bss_conf.basic_rates >> 4;
-
-        /* FIXME: is still necessary? */
-        if (ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ)
-                cck = 0;
-        else
-                cck = ar->vif->bss_conf.basic_rates & 0xf;
-
-        return ar9170_write_reg(ar, AR9170_MAC_REG_BASIC_RATE,
-                                ofdm << 8 | cck);
-}
-
-int ar9170_set_qos(struct ar9170 *ar)
-{
-        ar9170_regwrite_begin(ar);
-
-        ar9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
-                        (ar->edcf[0].cw_max << 16));
-        ar9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
-                        (ar->edcf[1].cw_max << 16));
-        ar9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
-                        (ar->edcf[2].cw_max << 16));
-        ar9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
-                        (ar->edcf[3].cw_max << 16));
-        ar9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
-                        (ar->edcf[4].cw_max << 16));
-
-        ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_AIFS,
-                        ((ar->edcf[0].aifs * 9 + 10)) |
-                        ((ar->edcf[1].aifs * 9 + 10) << 12) |
-                        ((ar->edcf[2].aifs * 9 + 10) << 24));
-        ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_AIFS,
-                        ((ar->edcf[2].aifs * 9 + 10) >> 8) |
-                        ((ar->edcf[3].aifs * 9 + 10) << 4) |
-                        ((ar->edcf[4].aifs * 9 + 10) << 16));
-
-        ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
-                        ar->edcf[0].txop | ar->edcf[1].txop << 16);
-        ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
-                        ar->edcf[2].txop | ar->edcf[3].txop << 16);
-
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
-}
-
-static int ar9170_set_ampdu_density(struct ar9170 *ar, u8 mpdudensity)
-{
-        u32 val;
-
-        /* don't allow AMPDU density > 8us */
-        if (mpdudensity > 6)
-                return -EINVAL;
-
-        /* Watch out! Otus uses slightly different density values. */
-        val = 0x140a00 | (mpdudensity ? (mpdudensity + 1) : 0);
-
-        ar9170_regwrite_begin(ar);
-        ar9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, val);
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
-}
-
-int ar9170_init_mac(struct ar9170 *ar)
-{
-        ar9170_regwrite_begin(ar);
-
-        ar9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
-
-        ar9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0);
-
-        /* enable MMIC */
-        ar9170_regwrite(AR9170_MAC_REG_SNIFFER,
-                        AR9170_MAC_REG_SNIFFER_DEFAULTS);
-
-        ar9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
-
-        ar9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
-        ar9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
-        ar9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
-
-        /* CF-END mode */
-        ar9170_regwrite(0x1c3b2c, 0x19000000);
-
-        /* NAV protects ACK only (in TXOP) */
-        ar9170_regwrite(0x1c3b38, 0x201);
-
-        /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
-        /* OTUS set AM to 0x1 */
-        ar9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
-
-        ar9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
-
-        /* AGG test code*/
-        /* Aggregation MAX number and timeout */
-        ar9170_regwrite(0x1c3b9c, 0x10000a);
-
-        ar9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
-                        AR9170_MAC_REG_FTF_DEFAULTS);
-
-        /* Enable deaggregator, response in sniffer mode */
-        ar9170_regwrite(0x1c3c40, 0x1 | 1<<30);
-
-        /* rate sets */
-        ar9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
-        ar9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
-        ar9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
-
-        /* MIMO response control */
-        ar9170_regwrite(0x1c3694, 0x4003C1E);/* bit 26~28  otus-AM */
-
-        /* switch MAC to OTUS interface */
-        ar9170_regwrite(0x1c3600, 0x3);
-
-        ar9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
-
-        /* set PHY register read timeout (??) */
-        ar9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
-
-        /* Disable Rx TimeOut, workaround for BB. */
-        ar9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
-
-        /* Set CPU clock frequency to 88/80MHz */
-        ar9170_regwrite(AR9170_PWR_REG_CLOCK_SEL,
-                        AR9170_PWR_CLK_AHB_80_88MHZ |
-                        AR9170_PWR_CLK_DAC_160_INV_DLY);
-
-        /* Set WLAN DMA interrupt mode: generate int per packet */
-        ar9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
-
-        ar9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
-                        AR9170_MAC_FCS_FIFO_PROT);
-
-        /* Disables the CF_END frame, undocumented register */
-        ar9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
-                        0x141E0F48);
-
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
-}
-
-static int ar9170_set_mac_reg(struct ar9170 *ar, const u32 reg, const u8 *mac)
-{
-        static const u8 zero[ETH_ALEN] = { 0 };
-
-        if (!mac)
-                mac = zero;
-
-        ar9170_regwrite_begin(ar);
-
-        ar9170_regwrite(reg, get_unaligned_le32(mac));
-        ar9170_regwrite(reg + 4, get_unaligned_le16(mac + 4));
-
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
-}
-
-int ar9170_update_multicast(struct ar9170 *ar, const u64 mc_hash)
-{
-        int err;
-
-        ar9170_regwrite_begin(ar);
-        ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, mc_hash >> 32);
-        ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, mc_hash);
-        ar9170_regwrite_finish();
-        err = ar9170_regwrite_result();
-        if (err)
-                return err;
-
-        ar->cur_mc_hash = mc_hash;
-        return 0;
-}
-
-int ar9170_update_frame_filter(struct ar9170 *ar, const u32 filter)
-{
-        int err;
-
-        err = ar9170_write_reg(ar, AR9170_MAC_REG_FRAMETYPE_FILTER, filter);
-        if (err)
-                return err;
-
-        ar->cur_filter = filter;
-        return 0;
-}
-
-static int ar9170_set_promiscouous(struct ar9170 *ar)
-{
-        u32 encr_mode, sniffer;
-        int err;
-
-        err = ar9170_read_reg(ar, AR9170_MAC_REG_SNIFFER, &sniffer);
-        if (err)
-                return err;
-
-        err = ar9170_read_reg(ar, AR9170_MAC_REG_ENCRYPTION, &encr_mode);
-        if (err)
-                return err;
-
-        if (ar->sniffer_enabled) {
-                sniffer |= AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
-
-                /*
-                 * Rx decryption works in place.
-                 *
-                 * If we don't disable it, the hardware will render all
-                 * encrypted frames which are encrypted with an unknown
-                 * key useless.
-                 */
-
-                encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
-                ar->sniffer_enabled = true;
-        } else {
-                sniffer &= ~AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
-
-                if (ar->rx_software_decryption)
-                        encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
-                else
-                        encr_mode &= ~AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
-        }
-
-        ar9170_regwrite_begin(ar);
-        ar9170_regwrite(AR9170_MAC_REG_ENCRYPTION, encr_mode);
-        ar9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
-}
-
-int ar9170_set_operating_mode(struct ar9170 *ar)
-{
-        struct ath_common *common = &ar->common;
-        u32 pm_mode = AR9170_MAC_REG_POWERMGT_DEFAULTS;
-        u8 *mac_addr, *bssid;
-        int err;
-
-        if (ar->vif) {
-                mac_addr = common->macaddr;
-                bssid = common->curbssid;
-
-                switch (ar->vif->type) {
-                case NL80211_IFTYPE_MESH_POINT:
-                case NL80211_IFTYPE_ADHOC:
-                        pm_mode |= AR9170_MAC_REG_POWERMGT_IBSS;
-                        break;
-                case NL80211_IFTYPE_AP:
-                        pm_mode |= AR9170_MAC_REG_POWERMGT_AP;
-                        break;
-                case NL80211_IFTYPE_WDS:
-                        pm_mode |= AR9170_MAC_REG_POWERMGT_AP_WDS;
-                        break;
-                case NL80211_IFTYPE_MONITOR:
-                        ar->sniffer_enabled = true;
-                        ar->rx_software_decryption = true;
-                        break;
-                default:
-                        pm_mode |= AR9170_MAC_REG_POWERMGT_STA;
-                        break;
-                }
-        } else {
-                mac_addr = NULL;
-                bssid = NULL;
-        }
-
-        err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr);
-        if (err)
-                return err;
-
-        err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid);
-        if (err)
-                return err;
-
-        err = ar9170_set_promiscouous(ar);
-        if (err)
-                return err;
-
-        /* set AMPDU density to 8us. */
-        err = ar9170_set_ampdu_density(ar, 6);
-        if (err)
-                return err;
-
-        ar9170_regwrite_begin(ar);
-
-        ar9170_regwrite(AR9170_MAC_REG_POWERMANAGEMENT, pm_mode);
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
-}
-
-int ar9170_set_hwretry_limit(struct ar9170 *ar, unsigned int max_retry)
-{
-        u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111);
-
-        return ar9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
-}
-
-int ar9170_set_beacon_timers(struct ar9170 *ar)
-{
-        u32 v = 0;
-        u32 pretbtt = 0;
-
-        if (ar->vif) {
-                v |= ar->vif->bss_conf.beacon_int;
-
-                if (ar->enable_beacon) {
-                        switch (ar->vif->type) {
-                        case NL80211_IFTYPE_MESH_POINT:
-                        case NL80211_IFTYPE_ADHOC:
-                                v |= BIT(25);
-                                break;
-                        case NL80211_IFTYPE_AP:
-                                v |= BIT(24);
-                                pretbtt = (ar->vif->bss_conf.beacon_int - 6) <<
-                                          16;
-                                break;
-                        default:
-                        break;
-                        }
-                }
-
-                v |= ar->vif->bss_conf.dtim_period << 16;
-        }
-
-        ar9170_regwrite_begin(ar);
-        ar9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
-        ar9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
-        ar9170_regwrite_finish();
-        return ar9170_regwrite_result();
-}
-
-int ar9170_update_beacon(struct ar9170 *ar)
-{
-        struct sk_buff *skb;
-        __le32 *data, *old = NULL;
-        u32 word;
-        int i;
-
-        skb = ieee80211_beacon_get(ar->hw, ar->vif);
-        if (!skb)
-                return -ENOMEM;
-
-        data = (__le32 *)skb->data;
-        if (ar->beacon)
-                old = (__le32 *)ar->beacon->data;
-
-        ar9170_regwrite_begin(ar);
-        for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
-                /*
-                 * XXX: This accesses beyond skb data for up
-                 *      to the last 3 bytes!!
-                 */
-
-                if (old && (data[i] == old[i]))
-                        continue;
-
-                word = le32_to_cpu(data[i]);
-                ar9170_regwrite(AR9170_BEACON_BUFFER_ADDRESS + 4 * i, word);
-        }
-
-        /* XXX: use skb->cb info */
-        if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
-                ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
-                                ((skb->len + 4) << (3 + 16)) + 0x0400);
-        else
-                ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
-                                ((skb->len + 4) << 16) + 0x001b);
-
-        ar9170_regwrite(AR9170_MAC_REG_BCN_LENGTH, skb->len + 4);
-        ar9170_regwrite(AR9170_MAC_REG_BCN_ADDR, AR9170_BEACON_BUFFER_ADDRESS);
-        ar9170_regwrite(AR9170_MAC_REG_BCN_CTRL, 1);
-
-        ar9170_regwrite_finish();
-
-        dev_kfree_skb(ar->beacon);
-        ar->beacon = skb;
-
-        return ar9170_regwrite_result();
-}
-
-void ar9170_new_beacon(struct work_struct *work)
-{
-        struct ar9170 *ar = container_of(work, struct ar9170,
-                                         beacon_work);
-        struct sk_buff *skb;
-
-        if (unlikely(!IS_STARTED(ar)))
-                return ;
-
-        mutex_lock(&ar->mutex);
-
-        if (!ar->vif)
-                goto out;
-
-        ar9170_update_beacon(ar);
-
-        rcu_read_lock();
-        while ((skb = ieee80211_get_buffered_bc(ar->hw, ar->vif)))
-                ar9170_op_tx(ar->hw, skb);
-
-        rcu_read_unlock();
-
- out:
-        mutex_unlock(&ar->mutex);
-}
-
-int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
-                      u8 keyidx, u8 *keydata, int keylen)
-{
-        __le32 vals[7];
-        static const u8 bcast[ETH_ALEN] =
-                { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-        u8 dummy;
-
-        mac = mac ? : bcast;
-
-        vals[0] = cpu_to_le32((keyidx << 16) + id);
-        vals[1] = cpu_to_le32(mac[1] << 24 | mac[0] << 16 | ktype);
-        vals[2] = cpu_to_le32(mac[5] << 24 | mac[4] << 16 |
-                              mac[3] << 8 | mac[2]);
-        memset(&vals[3], 0, 16);
-        if (keydata)
-                memcpy(&vals[3], keydata, keylen);
-
-        return ar->exec_cmd(ar, AR9170_CMD_EKEY,
-                            sizeof(vals), (u8 *)vals,
-                            1, &dummy);
-}
-
-int ar9170_disable_key(struct ar9170 *ar, u8 id)
-{
-        __le32 val = cpu_to_le32(id);
-        u8 dummy;
-
-        return ar->exec_cmd(ar, AR9170_CMD_EKEY,
-                            sizeof(val), (u8 *)&val,
-                            1, &dummy);
-}
diff --git a/drivers/net/wireless/ath/ar9170/main.c b/drivers/net/wireless/ath/ar9170/main.c
deleted file mode 100644
index debfb0fbc7c5..000000000000
--- a/drivers/net/wireless/ath/ar9170/main.c
+++ /dev/null
@@ -1,2191 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * mac80211 interaction code
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- * Copyright 2009, Christian Lamparter <chunkeey@web.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/etherdevice.h>
-#include <net/mac80211.h>
-#include "ar9170.h"
-#include "hw.h"
-#include "cmd.h"
-
-static int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
-MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
-
-#define RATE(_bitrate, _hw_rate, _txpidx, _flags) {     \
-        .bitrate        = (_bitrate),                   \
-        .flags          = (_flags),                     \
-        .hw_value       = (_hw_rate) | (_txpidx) << 4,  \
-}
-
-static struct ieee80211_rate __ar9170_ratetable[] = {
-        RATE(10, 0, 0, 0),
-        RATE(20, 1, 1, IEEE80211_RATE_SHORT_PREAMBLE),
-        RATE(55, 2, 2, IEEE80211_RATE_SHORT_PREAMBLE),
-        RATE(110, 3, 3, IEEE80211_RATE_SHORT_PREAMBLE),
-        RATE(60, 0xb, 0, 0),
-        RATE(90, 0xf, 0, 0),
-        RATE(120, 0xa, 0, 0),
-        RATE(180, 0xe, 0, 0),
-        RATE(240, 0x9, 0, 0),
-        RATE(360, 0xd, 1, 0),
-        RATE(480, 0x8, 2, 0),
-        RATE(540, 0xc, 3, 0),
-};
-#undef RATE
-
-#define ar9170_g_ratetable      (__ar9170_ratetable + 0)
-#define ar9170_g_ratetable_size 12
-#define ar9170_a_ratetable      (__ar9170_ratetable + 4)
-#define ar9170_a_ratetable_size 8
-
-/*
- * NB: The hw_value is used as an index into the ar9170_phy_freq_params
- *     array in phy.c so that we don't have to do frequency lookups!
- */
-#define CHAN(_freq, _idx) {             \
-        .center_freq    = (_freq),      \
-        .hw_value       = (_idx),       \
-        .max_power      = 18, /* XXX */ \
-}
-
-static struct ieee80211_channel ar9170_2ghz_chantable[] = {
-        CHAN(2412,  0),
-        CHAN(2417,  1),
-        CHAN(2422,  2),
-        CHAN(2427,  3),
-        CHAN(2432,  4),
-        CHAN(2437,  5),
-        CHAN(2442,  6),
-        CHAN(2447,  7),
-        CHAN(2452,  8),
-        CHAN(2457,  9),
-        CHAN(2462, 10),
-        CHAN(2467, 11),
-        CHAN(2472, 12),
-        CHAN(2484, 13),
-};
-
-static struct ieee80211_channel ar9170_5ghz_chantable[] = {
-        CHAN(4920, 14),
-        CHAN(4940, 15),
-        CHAN(4960, 16),
-        CHAN(4980, 17),
-        CHAN(5040, 18),
-        CHAN(5060, 19),
-        CHAN(5080, 20),
-        CHAN(5180, 21),
-        CHAN(5200, 22),
-        CHAN(5220, 23),
-        CHAN(5240, 24),
-        CHAN(5260, 25),
-        CHAN(5280, 26),
-        CHAN(5300, 27),
-        CHAN(5320, 28),
-        CHAN(5500, 29),
-        CHAN(5520, 30),
-        CHAN(5540, 31),
-        CHAN(5560, 32),
-        CHAN(5580, 33),
-        CHAN(5600, 34),
-        CHAN(5620, 35),
-        CHAN(5640, 36),
-        CHAN(5660, 37),
-        CHAN(5680, 38),
-        CHAN(5700, 39),
-        CHAN(5745, 40),
-        CHAN(5765, 41),
-        CHAN(5785, 42),
-        CHAN(5805, 43),
-        CHAN(5825, 44),
-        CHAN(5170, 45),
-        CHAN(5190, 46),
-        CHAN(5210, 47),
-        CHAN(5230, 48),
-};
-#undef CHAN
-
-#define AR9170_HT_CAP                                                   \
-{                                                                       \
-        .ht_supported   = true,                                         \
-        .cap            = IEEE80211_HT_CAP_MAX_AMSDU |                  \
-                          IEEE80211_HT_CAP_SUP_WIDTH_20_40 |            \
-                          IEEE80211_HT_CAP_SGI_40 |                     \
-                          IEEE80211_HT_CAP_GRN_FLD |                    \
-                          IEEE80211_HT_CAP_DSSSCCK40 |                  \
-                          IEEE80211_HT_CAP_SM_PS,                       \
-        .ampdu_factor   = 3,                                            \
-        .ampdu_density  = 6,                                            \
-        .mcs            = {                                             \
-                .rx_mask = { 0xff, 0xff, 0, 0, 0x1, 0, 0, 0, 0, 0, },   \
-                .rx_highest = cpu_to_le16(300),                         \
-                .tx_params = IEEE80211_HT_MCS_TX_DEFINED,               \
-        },                                                              \
-}
-
-static struct ieee80211_supported_band ar9170_band_2GHz = {
-        .channels       = ar9170_2ghz_chantable,
-        .n_channels     = ARRAY_SIZE(ar9170_2ghz_chantable),
-        .bitrates       = ar9170_g_ratetable,
-        .n_bitrates     = ar9170_g_ratetable_size,
-        .ht_cap         = AR9170_HT_CAP,
-};
-
-static struct ieee80211_supported_band ar9170_band_5GHz = {
-        .channels       = ar9170_5ghz_chantable,
-        .n_channels     = ARRAY_SIZE(ar9170_5ghz_chantable),
-        .bitrates       = ar9170_a_ratetable,
-        .n_bitrates     = ar9170_a_ratetable_size,
-        .ht_cap         = AR9170_HT_CAP,
-};
-
-static void ar9170_tx(struct ar9170 *ar);
-
-static inline u16 ar9170_get_seq_h(struct ieee80211_hdr *hdr)
-{
-        return le16_to_cpu(hdr->seq_ctrl) >> 4;
-}
-
-static inline u16 ar9170_get_seq(struct sk_buff *skb)
-{
-        struct ar9170_tx_control *txc = (void *) skb->data;
-        return ar9170_get_seq_h((void *) txc->frame_data);
-}
-
-#ifdef AR9170_QUEUE_DEBUG
-static void ar9170_print_txheader(struct ar9170 *ar, struct sk_buff *skb)
-{
-        struct ar9170_tx_control *txc = (void *) skb->data;
-        struct ieee80211_tx_info *txinfo = IEEE80211_SKB_CB(skb);
-        struct ar9170_tx_info *arinfo = (void *) txinfo->rate_driver_data;
-        struct ieee80211_hdr *hdr = (void *) txc->frame_data;
-
-        wiphy_debug(ar->hw->wiphy,
-                    "=> FRAME [skb:%p, q:%d, DA:[%pM] s:%d "
-                    "mac_ctrl:%04x, phy_ctrl:%08x, timeout:[%d ms]]\n",
-                    skb, skb_get_queue_mapping(skb),
-                    ieee80211_get_DA(hdr), ar9170_get_seq_h(hdr),
-                    le16_to_cpu(txc->mac_control), le32_to_cpu(txc->phy_control),
-                    jiffies_to_msecs(arinfo->timeout - jiffies));
-}
-
-static void __ar9170_dump_txqueue(struct ar9170 *ar,
-                                struct sk_buff_head *queue)
-{
-        struct sk_buff *skb;
-        int i = 0;
-
-        printk(KERN_DEBUG "---[ cut here ]---\n");
-        wiphy_debug(ar->hw->wiphy, "%d entries in queue.\n",
-                    skb_queue_len(queue));
-
-        skb_queue_walk(queue, skb) {
-                printk(KERN_DEBUG "index:%d =>\n", i++);
-                ar9170_print_txheader(ar, skb);
-        }
-        if (i != skb_queue_len(queue))
-                printk(KERN_DEBUG "WARNING: queue frame counter "
-                       "mismatch %d != %d\n", skb_queue_len(queue), i);
-        printk(KERN_DEBUG "---[ end ]---\n");
-}
-#endif /* AR9170_QUEUE_DEBUG */
-
-#ifdef AR9170_QUEUE_DEBUG
-static void ar9170_dump_txqueue(struct ar9170 *ar,
-                                struct sk_buff_head *queue)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&queue->lock, flags);
-        __ar9170_dump_txqueue(ar, queue);
-        spin_unlock_irqrestore(&queue->lock, flags);
-}
-#endif /* AR9170_QUEUE_DEBUG */
-
-#ifdef AR9170_QUEUE_STOP_DEBUG
-static void __ar9170_dump_txstats(struct ar9170 *ar)
-{
-        int i;
-
-        wiphy_debug(ar->hw->wiphy, "QoS queue stats\n");
-
-        for (i = 0; i < __AR9170_NUM_TXQ; i++)
-                wiphy_debug(ar->hw->wiphy,
-                            "queue:%d limit:%d len:%d waitack:%d stopped:%d\n",
-                            i, ar->tx_stats[i].limit, ar->tx_stats[i].len,
-                            skb_queue_len(&ar->tx_status[i]),
-                            ieee80211_queue_stopped(ar->hw, i));
-}
-#endif /* AR9170_QUEUE_STOP_DEBUG */
-
-/* caller must guarantee exclusive access for _bin_ queue. */
-static void ar9170_recycle_expired(struct ar9170 *ar,
-                                   struct sk_buff_head *queue,
-                                   struct sk_buff_head *bin)
-{
-        struct sk_buff *skb, *old = NULL;
-        unsigned long flags;
-
-        spin_lock_irqsave(&queue->lock, flags);
-        while ((skb = skb_peek(queue))) {
-                struct ieee80211_tx_info *txinfo;
-                struct ar9170_tx_info *arinfo;
-
-                txinfo = IEEE80211_SKB_CB(skb);
-                arinfo = (void *) txinfo->rate_driver_data;
-
-                if (time_is_before_jiffies(arinfo->timeout)) {
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy,
-                                    "[%ld > %ld] frame expired => recycle\n",
-                                    jiffies, arinfo->timeout);
-                        ar9170_print_txheader(ar, skb);
-#endif /* AR9170_QUEUE_DEBUG */
-                        __skb_unlink(skb, queue);
-                        __skb_queue_tail(bin, skb);
-                } else {
-                        break;
-                }
-
-                if (unlikely(old == skb)) {
-                        /* bail out - queue is shot. */
-
-                        WARN_ON(1);
-                        break;
-                }
-                old = skb;
-        }
-        spin_unlock_irqrestore(&queue->lock, flags);
-}
-
-static void ar9170_tx_status(struct ar9170 *ar, struct sk_buff *skb,
-                                    u16 tx_status)
-{
-        struct ieee80211_tx_info *txinfo;
-        unsigned int retries = 0;
-
-        txinfo = IEEE80211_SKB_CB(skb);
-        ieee80211_tx_info_clear_status(txinfo);
-
-        switch (tx_status) {
-        case AR9170_TX_STATUS_RETRY:
-                retries = 2;
-        case AR9170_TX_STATUS_COMPLETE:
-                txinfo->flags |= IEEE80211_TX_STAT_ACK;
-                break;
-
-        case AR9170_TX_STATUS_FAILED:
-                retries = ar->hw->conf.long_frame_max_tx_count;
-                break;
-
-        default:
-                wiphy_err(ar->hw->wiphy,
-                          "invalid tx_status response (%x)\n", tx_status);
-                break;
-        }
-
-        txinfo->status.rates[0].count = retries + 1;
-        skb_pull(skb, sizeof(struct ar9170_tx_control));
-        ieee80211_tx_status_irqsafe(ar->hw, skb);
-}
-
-void ar9170_tx_callback(struct ar9170 *ar, struct sk_buff *skb)
-{
-        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-        struct ar9170_tx_info *arinfo = (void *) info->rate_driver_data;
-        unsigned int queue = skb_get_queue_mapping(skb);
-        unsigned long flags;
-
-        spin_lock_irqsave(&ar->tx_stats_lock, flags);
-        ar->tx_stats[queue].len--;
-
-        if (ar->tx_stats[queue].len < AR9170_NUM_TX_LIMIT_SOFT) {
-#ifdef AR9170_QUEUE_STOP_DEBUG
-                wiphy_debug(ar->hw->wiphy, "wake queue %d\n", queue);
-                __ar9170_dump_txstats(ar);
-#endif /* AR9170_QUEUE_STOP_DEBUG */
-                ieee80211_wake_queue(ar->hw, queue);
-        }
-        spin_unlock_irqrestore(&ar->tx_stats_lock, flags);
-
-        if (info->flags & IEEE80211_TX_CTL_NO_ACK) {
-                ar9170_tx_status(ar, skb, AR9170_TX_STATUS_FAILED);
-        } else {
-                arinfo->timeout = jiffies +
-                          msecs_to_jiffies(AR9170_TX_TIMEOUT);
-
-                skb_queue_tail(&ar->tx_status[queue], skb);
-        }
-
-        if (!ar->tx_stats[queue].len &&
-            !skb_queue_empty(&ar->tx_pending[queue])) {
-                ar9170_tx(ar);
-        }
-}
-
-static struct sk_buff *ar9170_get_queued_skb(struct ar9170 *ar,
-                                             const u8 *mac,
-                                             struct sk_buff_head *queue,
-                                             const u32 rate)
-{
-        unsigned long flags;
-        struct sk_buff *skb;
-
-        /*
-         * Unfortunately, the firmware does not tell to which (queued) frame
-         * this transmission status report belongs to.
-         *
-         * So we have to make risky guesses - with the scarce information
-         * the firmware provided (-> destination MAC, and phy_control) -
-         * and hope that we picked the right one...
-         */
-
-        spin_lock_irqsave(&queue->lock, flags);
-        skb_queue_walk(queue, skb) {
-                struct ar9170_tx_control *txc = (void *) skb->data;
-                struct ieee80211_hdr *hdr = (void *) txc->frame_data;
-                u32 r;
-
-                if (mac && compare_ether_addr(ieee80211_get_DA(hdr), mac)) {
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy,
-                                    "skip frame => DA %pM != %pM\n",
-                                    mac, ieee80211_get_DA(hdr));
-                        ar9170_print_txheader(ar, skb);
-#endif /* AR9170_QUEUE_DEBUG */
-                        continue;
-                }
-
-                r = (le32_to_cpu(txc->phy_control) & AR9170_TX_PHY_MCS_MASK) >>
-                    AR9170_TX_PHY_MCS_SHIFT;
-
-                if ((rate != AR9170_TX_INVALID_RATE) && (r != rate)) {
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy,
-                                    "skip frame => rate %d != %d\n", rate, r);
-                        ar9170_print_txheader(ar, skb);
-#endif /* AR9170_QUEUE_DEBUG */
-                        continue;
-                }
-
-                __skb_unlink(skb, queue);
-                spin_unlock_irqrestore(&queue->lock, flags);
-                return skb;
-        }
-
-#ifdef AR9170_QUEUE_DEBUG
-        wiphy_err(ar->hw->wiphy,
-                  "ESS:[%pM] does not have any outstanding frames in queue.\n",
-                  mac);
-        __ar9170_dump_txqueue(ar, queue);
-#endif /* AR9170_QUEUE_DEBUG */
-        spin_unlock_irqrestore(&queue->lock, flags);
-
-        return NULL;
-}
-
-/*
- * This worker tries to keeps an maintain tx_status queues.
- * So we can guarantee that incoming tx_status reports are
- * actually for a pending frame.
- */
-
-static void ar9170_tx_janitor(struct work_struct *work)
-{
-        struct ar9170 *ar = container_of(work, struct ar9170,
-                                         tx_janitor.work);
-        struct sk_buff_head waste;
-        unsigned int i;
-        bool resched = false;
-
-        if (unlikely(!IS_STARTED(ar)))
-                return ;
-
-        skb_queue_head_init(&waste);
-
-        for (i = 0; i < __AR9170_NUM_TXQ; i++) {
-#ifdef AR9170_QUEUE_DEBUG
-                wiphy_debug(ar->hw->wiphy, "garbage collector scans queue:%d\n",
-                            i);
-                ar9170_dump_txqueue(ar, &ar->tx_pending[i]);
-                ar9170_dump_txqueue(ar, &ar->tx_status[i]);
-#endif /* AR9170_QUEUE_DEBUG */
-
-                ar9170_recycle_expired(ar, &ar->tx_status[i], &waste);
-                ar9170_recycle_expired(ar, &ar->tx_pending[i], &waste);
-                skb_queue_purge(&waste);
-
-                if (!skb_queue_empty(&ar->tx_status[i]) ||
-                    !skb_queue_empty(&ar->tx_pending[i]))
-                        resched = true;
-        }
-
-        if (!resched)
-                return;
-
-        ieee80211_queue_delayed_work(ar->hw,
-                                     &ar->tx_janitor,
-                                     msecs_to_jiffies(AR9170_JANITOR_DELAY));
-}
-
-void ar9170_handle_command_response(struct ar9170 *ar, void *buf, u32 len)
-{
-        struct ar9170_cmd_response *cmd = (void *) buf;
-
-        if ((cmd->type & 0xc0) != 0xc0) {
-                ar->callback_cmd(ar, len, buf);
-                return;
-        }
-
-        /* hardware event handlers */
-        switch (cmd->type) {
-        case 0xc1: {
-                /*
-                 * TX status notification:
-                 * bytes: 0c c1 XX YY M1 M2 M3 M4 M5 M6 R4 R3 R2 R1 S2 S1
-                 *
-                 * XX always 81
-                 * YY always 00
-                 * M1-M6 is the MAC address
-                 * R1-R4 is the transmit rate
-                 * S1-S2 is the transmit status
-                 */
-
-                struct sk_buff *skb;
-                u32 phy = le32_to_cpu(cmd->tx_status.rate);
-                u32 q = (phy & AR9170_TX_PHY_QOS_MASK) >>
-                        AR9170_TX_PHY_QOS_SHIFT;
-#ifdef AR9170_QUEUE_DEBUG
-                wiphy_debug(ar->hw->wiphy,
-                            "recv tx_status for %pm, p:%08x, q:%d\n",
-                            cmd->tx_status.dst, phy, q);
-#endif /* AR9170_QUEUE_DEBUG */
-
-                skb = ar9170_get_queued_skb(ar, cmd->tx_status.dst,
-                                            &ar->tx_status[q],
-                                            AR9170_TX_INVALID_RATE);
-                if (unlikely(!skb))
-                        return ;
-
-                ar9170_tx_status(ar, skb, le16_to_cpu(cmd->tx_status.status));
-                break;
-                }
-
-        case 0xc0:
-                /*
-                 * pre-TBTT event
-                 */
-                if (ar->vif && ar->vif->type == NL80211_IFTYPE_AP)
-                        ieee80211_queue_work(ar->hw, &ar->beacon_work);
-                break;
-
-        case 0xc2:
-                /*
-                 * (IBSS) beacon send notification
-                 * bytes: 04 c2 XX YY B4 B3 B2 B1
-                 *
-                 * XX always 80
-                 * YY always 00
-                 * B1-B4 "should" be the number of send out beacons.
-                 */
-                break;
-
-        case 0xc3:
-                /* End of Atim Window */
-                break;
-
-        case 0xc4:
-                /* BlockACK bitmap */
-                break;
-
-        case 0xc5:
-                /* BlockACK events */
-                break;
-
-        case 0xc6:
-                /* Watchdog Interrupt */
-                break;
-
-        case 0xc9:
-                /* retransmission issue / SIFS/EIFS collision ?! */
-                break;
-
-        /* firmware debug */
-        case 0xca:
-                printk(KERN_DEBUG "ar9170 FW: %.*s\n", len - 4,
-                                (char *)buf + 4);
-                break;
-        case 0xcb:
-                len -= 4;
-
-                switch (len) {
-                case 1:
-                        printk(KERN_DEBUG "ar9170 FW: u8: %#.2x\n",
-                                *((char *)buf + 4));
-                        break;
-                case 2:
-                        printk(KERN_DEBUG "ar9170 FW: u8: %#.4x\n",
-                                le16_to_cpup((__le16 *)((char *)buf + 4)));
-                        break;
-                case 4:
-                        printk(KERN_DEBUG "ar9170 FW: u8: %#.8x\n",
-                                le32_to_cpup((__le32 *)((char *)buf + 4)));
-                        break;
-                case 8:
-                        printk(KERN_DEBUG "ar9170 FW: u8: %#.16lx\n",
-                                (unsigned long)le64_to_cpup(
-                                                (__le64 *)((char *)buf + 4)));
-                        break;
-                }
-                break;
-        case 0xcc:
-                print_hex_dump_bytes("ar9170 FW:", DUMP_PREFIX_NONE,
-                                     (char *)buf + 4, len - 4);
-                break;
-
-        default:
-                pr_info("received unhandled event %x\n", cmd->type);
-                print_hex_dump_bytes("dump:", DUMP_PREFIX_NONE, buf, len);
-                break;
-        }
-}
-
-static void ar9170_rx_reset_rx_mpdu(struct ar9170 *ar)
-{
-        memset(&ar->rx_mpdu.plcp, 0, sizeof(struct ar9170_rx_head));
-        ar->rx_mpdu.has_plcp = false;
-}
-
-int ar9170_nag_limiter(struct ar9170 *ar)
-{
-        bool print_message;
-
-        /*
-         * we expect all sorts of errors in promiscuous mode.
-         * don't bother with it, it's OK!
-         */
-        if (ar->sniffer_enabled)
-                return false;
-
-        /*
-         * only go for frequent errors! The hardware tends to
-         * do some stupid thing once in a while under load, in
-         * noisy environments or just for fun!
-         */
-        if (time_before(jiffies, ar->bad_hw_nagger) && net_ratelimit())
-                print_message = true;
-        else
-                print_message = false;
-
-        /* reset threshold for "once in a while" */
-        ar->bad_hw_nagger = jiffies + HZ / 4;
-        return print_message;
-}
-
-static int ar9170_rx_mac_status(struct ar9170 *ar,
-                                struct ar9170_rx_head *head,
-                                struct ar9170_rx_macstatus *mac,
-                                struct ieee80211_rx_status *status)
-{
-        u8 error, decrypt;
-
-        BUILD_BUG_ON(sizeof(struct ar9170_rx_head) != 12);
-        BUILD_BUG_ON(sizeof(struct ar9170_rx_macstatus) != 4);
-
-        error = mac->error;
-        if (error & AR9170_RX_ERROR_MMIC) {
-                status->flag |= RX_FLAG_MMIC_ERROR;
-                error &= ~AR9170_RX_ERROR_MMIC;
-        }
-
-        if (error & AR9170_RX_ERROR_PLCP) {
-                status->flag |= RX_FLAG_FAILED_PLCP_CRC;
-                error &= ~AR9170_RX_ERROR_PLCP;
-
-                if (!(ar->filter_state & FIF_PLCPFAIL))
-                        return -EINVAL;
-        }
-
-        if (error & AR9170_RX_ERROR_FCS) {
-                status->flag |= RX_FLAG_FAILED_FCS_CRC;
-                error &= ~AR9170_RX_ERROR_FCS;
-
-                if (!(ar->filter_state & FIF_FCSFAIL))
-                        return -EINVAL;
-        }
-
-        decrypt = ar9170_get_decrypt_type(mac);
-        if (!(decrypt & AR9170_RX_ENC_SOFTWARE) &&
-            decrypt != AR9170_ENC_ALG_NONE)
-                status->flag |= RX_FLAG_DECRYPTED;
-
-        /* ignore wrong RA errors */
-        error &= ~AR9170_RX_ERROR_WRONG_RA;
-
-        if (error & AR9170_RX_ERROR_DECRYPT) {
-                error &= ~AR9170_RX_ERROR_DECRYPT;
-                /*
-                 * Rx decryption is done in place,
-                 * the original data is lost anyway.
-                 */
-
-                return -EINVAL;
-        }
-
-        /* drop any other error frames */
-        if (unlikely(error)) {
-                /* TODO: update netdevice's RX dropped/errors statistics */
-
-                if (ar9170_nag_limiter(ar))
-                        wiphy_debug(ar->hw->wiphy,
-                                    "received frame with suspicious error code (%#x).\n",
-                                    error);
-
-                return -EINVAL;
-        }
-
-        status->band = ar->channel->band;
-        status->freq = ar->channel->center_freq;
-
-        switch (mac->status & AR9170_RX_STATUS_MODULATION_MASK) {
-        case AR9170_RX_STATUS_MODULATION_CCK:
-                if (mac->status & AR9170_RX_STATUS_SHORT_PREAMBLE)
-                        status->flag |= RX_FLAG_SHORTPRE;
-                switch (head->plcp[0]) {
-                case 0x0a:
-                        status->rate_idx = 0;
-                        break;
-                case 0x14:
-                        status->rate_idx = 1;
-                        break;
-                case 0x37:
-                        status->rate_idx = 2;
-                        break;
-                case 0x6e:
-                        status->rate_idx = 3;
-                        break;
-                default:
-                        if (ar9170_nag_limiter(ar))
-                                wiphy_err(ar->hw->wiphy,
-                                          "invalid plcp cck rate (%x).\n",
-                                          head->plcp[0]);
-                        return -EINVAL;
-                }
-                break;
-
-        case AR9170_RX_STATUS_MODULATION_DUPOFDM:
-        case AR9170_RX_STATUS_MODULATION_OFDM:
-                switch (head->plcp[0] & 0xf) {
-                case 0xb:
-                        status->rate_idx = 0;
-                        break;
-                case 0xf:
-                        status->rate_idx = 1;
-                        break;
-                case 0xa:
-                        status->rate_idx = 2;
-                        break;
-                case 0xe:
-                        status->rate_idx = 3;
-                        break;
-                case 0x9:
-                        status->rate_idx = 4;
-                        break;
-                case 0xd:
-                        status->rate_idx = 5;
-                        break;
-                case 0x8:
-                        status->rate_idx = 6;
-                        break;
-                case 0xc:
-                        status->rate_idx = 7;
-                        break;
-                default:
-                        if (ar9170_nag_limiter(ar))
-                                wiphy_err(ar->hw->wiphy,
-                                          "invalid plcp ofdm rate (%x).\n",
-                                          head->plcp[0]);
-                        return -EINVAL;
-                }
-                if (status->band == IEEE80211_BAND_2GHZ)
-                        status->rate_idx += 4;
-                break;
-
-        case AR9170_RX_STATUS_MODULATION_HT:
-                if (head->plcp[3] & 0x80)
-                        status->flag |= RX_FLAG_40MHZ;
-                if (head->plcp[6] & 0x80)
-                        status->flag |= RX_FLAG_SHORT_GI;
-
-                status->rate_idx = clamp(0, 75, head->plcp[6] & 0x7f);
-                status->flag |= RX_FLAG_HT;
-                break;
-
-        default:
-                if (ar9170_nag_limiter(ar))
-                        wiphy_err(ar->hw->wiphy, "invalid modulation\n");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static void ar9170_rx_phy_status(struct ar9170 *ar,
-                                 struct ar9170_rx_phystatus *phy,
-                                 struct ieee80211_rx_status *status)
-{
-        int i;
-
-        BUILD_BUG_ON(sizeof(struct ar9170_rx_phystatus) != 20);
-
-        for (i = 0; i < 3; i++)
-                if (phy->rssi[i] != 0x80)
-                        status->antenna |= BIT(i);
-
-        /* post-process RSSI */
-        for (i = 0; i < 7; i++)
-                if (phy->rssi[i] & 0x80)
-                        phy->rssi[i] = ((phy->rssi[i] & 0x7f) + 1) & 0x7f;
-
-        /* TODO: we could do something with phy_errors */
-        status->signal = ar->noise[0] + phy->rssi_combined;
-}
-
-static struct sk_buff *ar9170_rx_copy_data(u8 *buf, int len)
-{
-        struct sk_buff *skb;
-        int reserved = 0;
-        struct ieee80211_hdr *hdr = (void *) buf;
-
-        if (ieee80211_is_data_qos(hdr->frame_control)) {
-                u8 *qc = ieee80211_get_qos_ctl(hdr);
-                reserved += NET_IP_ALIGN;
-
-                if (*qc & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
-                        reserved += NET_IP_ALIGN;
-        }
-
-        if (ieee80211_has_a4(hdr->frame_control))
-                reserved += NET_IP_ALIGN;
-
-        reserved = 32 + (reserved & NET_IP_ALIGN);
-
-        skb = dev_alloc_skb(len + reserved);
-        if (likely(skb)) {
-                skb_reserve(skb, reserved);
-                memcpy(skb_put(skb, len), buf, len);
-        }
-
-        return skb;
-}
-
-/*
- * If the frame alignment is right (or the kernel has
- * CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS), and there
- * is only a single MPDU in the USB frame, then we could
- * submit to mac80211 the SKB directly. However, since
- * there may be multiple packets in one SKB in stream
- * mode, and we need to observe the proper ordering,
- * this is non-trivial.
- */
-
-static void ar9170_handle_mpdu(struct ar9170 *ar, u8 *buf, int len)
-{
-        struct ar9170_rx_head *head;
-        struct ar9170_rx_macstatus *mac;
-        struct ar9170_rx_phystatus *phy = NULL;
-        struct ieee80211_rx_status status;
-        struct sk_buff *skb;
-        int mpdu_len;
-
-        if (unlikely(!IS_STARTED(ar) || len < (sizeof(*mac))))
-                return ;
-
-        /* Received MPDU */
-        mpdu_len = len - sizeof(*mac);
-
-        mac = (void *)(buf + mpdu_len);
-        if (unlikely(mac->error & AR9170_RX_ERROR_FATAL)) {
-                /* this frame is too damaged and can't be used - drop it */
-
-                return ;
-        }
-
-        switch (mac->status & AR9170_RX_STATUS_MPDU_MASK) {
-        case AR9170_RX_STATUS_MPDU_FIRST:
-                /* first mpdu packet has the plcp header */
-                if (likely(mpdu_len >= sizeof(struct ar9170_rx_head))) {
-                        head = (void *) buf;
-                        memcpy(&ar->rx_mpdu.plcp, (void *) buf,
-                               sizeof(struct ar9170_rx_head));
-
-                        mpdu_len -= sizeof(struct ar9170_rx_head);
-                        buf += sizeof(struct ar9170_rx_head);
-                        ar->rx_mpdu.has_plcp = true;
-                } else {
-                        if (ar9170_nag_limiter(ar))
-                                wiphy_err(ar->hw->wiphy,
-                                          "plcp info is clipped.\n");
-                        return ;
-                }
-                break;
-
-        case AR9170_RX_STATUS_MPDU_LAST:
-                /* last mpdu has a extra tail with phy status information */
-
-                if (likely(mpdu_len >= sizeof(struct ar9170_rx_phystatus))) {
-                        mpdu_len -= sizeof(struct ar9170_rx_phystatus);
-                        phy = (void *)(buf + mpdu_len);
-                } else {
-                        if (ar9170_nag_limiter(ar))
-                                wiphy_err(ar->hw->wiphy,
-                                          "frame tail is clipped.\n");
-                        return ;
-                }
-
-        case AR9170_RX_STATUS_MPDU_MIDDLE:
-                /* middle mpdus are just data */
-                if (unlikely(!ar->rx_mpdu.has_plcp)) {
-                        if (!ar9170_nag_limiter(ar))
-                                return ;
-
-                        wiphy_err(ar->hw->wiphy,
-                                  "rx stream did not start with a first_mpdu frame tag.\n");
-
-                        return ;
-                }
-
-                head = &ar->rx_mpdu.plcp;
-                break;
-
-        case AR9170_RX_STATUS_MPDU_SINGLE:
-                /* single mpdu - has plcp (head) and phy status (tail) */
-                head = (void *) buf;
-
-                mpdu_len -= sizeof(struct ar9170_rx_head);
-                mpdu_len -= sizeof(struct ar9170_rx_phystatus);
-
-                buf += sizeof(struct ar9170_rx_head);
-                phy = (void *)(buf + mpdu_len);
-                break;
-
-        default:
-                BUG_ON(1);
-                break;
-        }
-
-        if (unlikely(mpdu_len < FCS_LEN))
-                return ;
-
-        memset(&status, 0, sizeof(status));
-        if (unlikely(ar9170_rx_mac_status(ar, head, mac, &status)))
-                return ;
-
-        if (phy)
-                ar9170_rx_phy_status(ar, phy, &status);
-
-        skb = ar9170_rx_copy_data(buf, mpdu_len);
-        if (likely(skb)) {
-                memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
-                ieee80211_rx_irqsafe(ar->hw, skb);
-        }
-}
-
-void ar9170_rx(struct ar9170 *ar, struct sk_buff *skb)
-{
-        unsigned int i, tlen, resplen, wlen = 0, clen = 0;
-        u8 *tbuf, *respbuf;
-
-        tbuf = skb->data;
-        tlen = skb->len;
-
-        while (tlen >= 4) {
-                clen = tbuf[1] << 8 | tbuf[0];
-                wlen = ALIGN(clen, 4);
-
-                /* check if this is stream has a valid tag.*/
-                if (tbuf[2] != 0 || tbuf[3] != 0x4e) {
-                        /*
-                         * TODO: handle the highly unlikely event that the
-                         * corrupted stream has the TAG at the right position.
-                         */
-
-                        /* check if the frame can be repaired. */
-                        if (!ar->rx_failover_missing) {
-                                /* this is no "short read". */
-                                if (ar9170_nag_limiter(ar)) {
-                                        wiphy_err(ar->hw->wiphy,
-                                                  "missing tag!\n");
-                                        goto err_telluser;
-                                } else
-                                        goto err_silent;
-                        }
-
-                        if (ar->rx_failover_missing > tlen) {
-                                if (ar9170_nag_limiter(ar)) {
-                                        wiphy_err(ar->hw->wiphy,
-                                                  "possible multi stream corruption!\n");
-                                        goto err_telluser;
-                                } else
-                                        goto err_silent;
-                        }
-
-                        memcpy(skb_put(ar->rx_failover, tlen), tbuf, tlen);
-                        ar->rx_failover_missing -= tlen;
-
-                        if (ar->rx_failover_missing <= 0) {
-                                /*
-                                 * nested ar9170_rx call!
-                                 * termination is guranteed, even when the
-                                 * combined frame also have a element with
-                                 * a bad tag.
-                                 */
-
-                                ar->rx_failover_missing = 0;
-                                ar9170_rx(ar, ar->rx_failover);
-
-                                skb_reset_tail_pointer(ar->rx_failover);
-                                skb_trim(ar->rx_failover, 0);
-                        }
-
-                        return ;
-                }
-
-                /* check if stream is clipped */
-                if (wlen > tlen - 4) {
-                        if (ar->rx_failover_missing) {
-                                /* TODO: handle double stream corruption. */
-                                if (ar9170_nag_limiter(ar)) {
-                                        wiphy_err(ar->hw->wiphy,
-                                                  "double rx stream corruption!\n");
-                                        goto err_telluser;
-                                } else
-                                        goto err_silent;
-                        }
-
-                        /*
-                         * save incomplete data set.
-                         * the firmware will resend the missing bits when
-                         * the rx - descriptor comes round again.
-                         */
-
-                        memcpy(skb_put(ar->rx_failover, tlen), tbuf, tlen);
-                        ar->rx_failover_missing = clen - tlen;
-                        return ;
-                }
-                resplen = clen;
-                respbuf = tbuf + 4;
-                tbuf += wlen + 4;
-                tlen -= wlen + 4;
-
-                i = 0;
-
-                /* weird thing, but this is the same in the original driver */
-                while (resplen > 2 && i < 12 &&
-                       respbuf[0] == 0xff && respbuf[1] == 0xff) {
-                        i += 2;
-                        resplen -= 2;
-                        respbuf += 2;
-                }
-
-                if (resplen < 4)
-                        continue;
-
-                /* found the 6 * 0xffff marker? */
-                if (i == 12)
-                        ar9170_handle_command_response(ar, respbuf, resplen);
-                else
-                        ar9170_handle_mpdu(ar, respbuf, clen);
-        }
-
-        if (tlen) {
-                if (net_ratelimit())
-                        wiphy_err(ar->hw->wiphy,
-                                  "%d bytes of unprocessed data left in rx stream!\n",
-                                  tlen);
-
-                goto err_telluser;
-        }
-
-        return ;
-
-err_telluser:
-        wiphy_err(ar->hw->wiphy,
-                  "damaged RX stream data [want:%d, data:%d, rx:%d, pending:%d ]\n",
-                  clen, wlen, tlen, ar->rx_failover_missing);
-
-        if (ar->rx_failover_missing)
-                print_hex_dump_bytes("rxbuf:", DUMP_PREFIX_OFFSET,
-                                     ar->rx_failover->data,
-                                     ar->rx_failover->len);
-
-        print_hex_dump_bytes("stream:", DUMP_PREFIX_OFFSET,
-                             skb->data, skb->len);
-
-        wiphy_err(ar->hw->wiphy,
-                  "If you see this message frequently, please check your hardware and cables.\n");
-
-err_silent:
-        if (ar->rx_failover_missing) {
-                skb_reset_tail_pointer(ar->rx_failover);
-                skb_trim(ar->rx_failover, 0);
-                ar->rx_failover_missing = 0;
-        }
-}
-
-#define AR9170_FILL_QUEUE(queue, ai_fs, cwmin, cwmax, _txop)            \
-do {                                                                    \
-        queue.aifs = ai_fs;                                             \
-        queue.cw_min = cwmin;                                           \
-        queue.cw_max = cwmax;                                           \
-        queue.txop = _txop;                                             \
-} while (0)
-
-static int ar9170_op_start(struct ieee80211_hw *hw)
-{
-        struct ar9170 *ar = hw->priv;
-        int err, i;
-
-        mutex_lock(&ar->mutex);
-
-        /* reinitialize queues statistics */
-        memset(&ar->tx_stats, 0, sizeof(ar->tx_stats));
-        for (i = 0; i < __AR9170_NUM_TXQ; i++)
-                ar->tx_stats[i].limit = AR9170_TXQ_DEPTH;
-
-        /* reset QoS defaults */
-        AR9170_FILL_QUEUE(ar->edcf[0], 3, 15, 1023,  0); /* BEST EFFORT*/
-        AR9170_FILL_QUEUE(ar->edcf[1], 7, 15, 1023,  0); /* BACKGROUND */
-        AR9170_FILL_QUEUE(ar->edcf[2], 2, 7,    15, 94); /* VIDEO */
-        AR9170_FILL_QUEUE(ar->edcf[3], 2, 3,     7, 47); /* VOICE */
-        AR9170_FILL_QUEUE(ar->edcf[4], 2, 3,     7,  0); /* SPECIAL */
-
-        /* set sane AMPDU defaults */
-        ar->global_ampdu_density = 6;
-        ar->global_ampdu_factor = 3;
-
-        ar->bad_hw_nagger = jiffies;
-
-        err = ar->open(ar);
-        if (err)
-                goto out;
-
-        err = ar9170_init_mac(ar);
-        if (err)
-                goto out;
-
-        err = ar9170_set_qos(ar);
-        if (err)
-                goto out;
-
-        err = ar9170_init_phy(ar, IEEE80211_BAND_2GHZ);
-        if (err)
-                goto out;
-
-        err = ar9170_init_rf(ar);
-        if (err)
-                goto out;
-
-        /* start DMA */
-        err = ar9170_write_reg(ar, 0x1c3d30, 0x100);
-        if (err)
-                goto out;
-
-        ar->state = AR9170_STARTED;
-
-out:
-        mutex_unlock(&ar->mutex);
-        return err;
-}
-
-static void ar9170_op_stop(struct ieee80211_hw *hw)
-{
-        struct ar9170 *ar = hw->priv;
-        unsigned int i;
-
-        if (IS_STARTED(ar))
-                ar->state = AR9170_IDLE;
-
-        cancel_delayed_work_sync(&ar->tx_janitor);
-#ifdef CONFIG_AR9170_LEDS
-        cancel_delayed_work_sync(&ar->led_work);
-#endif
-        cancel_work_sync(&ar->beacon_work);
-
-        mutex_lock(&ar->mutex);
-
-        if (IS_ACCEPTING_CMD(ar)) {
-                ar9170_set_leds_state(ar, 0);
-
-                /* stop DMA */
-                ar9170_write_reg(ar, 0x1c3d30, 0);
-                ar->stop(ar);
-        }
-
-        for (i = 0; i < __AR9170_NUM_TXQ; i++) {
-                skb_queue_purge(&ar->tx_pending[i]);
-                skb_queue_purge(&ar->tx_status[i]);
-        }
-
-        mutex_unlock(&ar->mutex);
-}
-
-static int ar9170_tx_prepare(struct ar9170 *ar, struct sk_buff *skb)
-{
-        struct ieee80211_hdr *hdr;
-        struct ar9170_tx_control *txc;
-        struct ieee80211_tx_info *info;
-        struct ieee80211_tx_rate *txrate;
-        struct ar9170_tx_info *arinfo;
-        unsigned int queue = skb_get_queue_mapping(skb);
-        u16 keytype = 0;
-        u16 len, icv = 0;
-
-        BUILD_BUG_ON(sizeof(*arinfo) > sizeof(info->rate_driver_data));
-
-        hdr = (void *)skb->data;
-        info = IEEE80211_SKB_CB(skb);
-        len = skb->len;
-
-        txc = (void *)skb_push(skb, sizeof(*txc));
-
-        if (info->control.hw_key) {
-                icv = info->control.hw_key->icv_len;
-
-                switch (info->control.hw_key->alg) {
-                case ALG_WEP:
-                        keytype = AR9170_TX_MAC_ENCR_RC4;
-                        break;
-                case ALG_TKIP:
-                        keytype = AR9170_TX_MAC_ENCR_RC4;
-                        break;
-                case ALG_CCMP:
-                        keytype = AR9170_TX_MAC_ENCR_AES;
-                        break;
-                default:
-                        WARN_ON(1);
-                        goto err_out;
-                }
-        }
-
-        /* Length */
-        txc->length = cpu_to_le16(len + icv + 4);
-
-        txc->mac_control = cpu_to_le16(AR9170_TX_MAC_HW_DURATION |
-                                       AR9170_TX_MAC_BACKOFF);
-        txc->mac_control |= cpu_to_le16(ar9170_qos_hwmap[queue] <<
-                                        AR9170_TX_MAC_QOS_SHIFT);
-        txc->mac_control |= cpu_to_le16(keytype);
-        txc->phy_control = cpu_to_le32(0);
-
-        if (info->flags & IEEE80211_TX_CTL_NO_ACK)
-                txc->mac_control |= cpu_to_le16(AR9170_TX_MAC_NO_ACK);
-
-        txrate = &info->control.rates[0];
-        if (txrate->flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
-                txc->mac_control |= cpu_to_le16(AR9170_TX_MAC_PROT_CTS);
-        else if (txrate->flags & IEEE80211_TX_RC_USE_RTS_CTS)
-                txc->mac_control |= cpu_to_le16(AR9170_TX_MAC_PROT_RTS);
-
-        arinfo = (void *)info->rate_driver_data;
-        arinfo->timeout = jiffies + msecs_to_jiffies(AR9170_QUEUE_TIMEOUT);
-
-        if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
-             (is_valid_ether_addr(ieee80211_get_DA(hdr)))) {
-                /*
-                 * WARNING:
-                 * Putting the QoS queue bits into an unexplored territory is
-                 * certainly not elegant.
-                 *
-                 * In my defense: This idea provides a reasonable way to
-                 * smuggle valuable information to the tx_status callback.
-                 * Also, the idea behind this bit-abuse came straight from
-                 * the original driver code.
-                 */
-
-                txc->phy_control |=
-                        cpu_to_le32(queue << AR9170_TX_PHY_QOS_SHIFT);
-
-                txc->mac_control |= cpu_to_le16(AR9170_TX_MAC_RATE_PROBE);
-        }
-
-        return 0;
-
-err_out:
-        skb_pull(skb, sizeof(*txc));
-        return -EINVAL;
-}
-
-static void ar9170_tx_prepare_phy(struct ar9170 *ar, struct sk_buff *skb)
-{
-        struct ar9170_tx_control *txc;
-        struct ieee80211_tx_info *info;
-        struct ieee80211_rate *rate = NULL;
-        struct ieee80211_tx_rate *txrate;
-        u32 power, chains;
-
-        txc = (void *) skb->data;
-        info = IEEE80211_SKB_CB(skb);
-        txrate = &info->control.rates[0];
-
-        if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
-                txc->phy_control |= cpu_to_le32(AR9170_TX_PHY_GREENFIELD);
-
-        if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
-                txc->phy_control |= cpu_to_le32(AR9170_TX_PHY_SHORT_PREAMBLE);
-
-        if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
-                txc->phy_control |= cpu_to_le32(AR9170_TX_PHY_BW_40MHZ);
-        /* this works because 40 MHz is 2 and dup is 3 */
-        if (txrate->flags & IEEE80211_TX_RC_DUP_DATA)
-                txc->phy_control |= cpu_to_le32(AR9170_TX_PHY_BW_40MHZ_DUP);
-
-        if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
-                txc->phy_control |= cpu_to_le32(AR9170_TX_PHY_SHORT_GI);
-
-        if (txrate->flags & IEEE80211_TX_RC_MCS) {
-                u32 r = txrate->idx;
-                u8 *txpower;
-
-                /* heavy clip control */
-                txc->phy_control |= cpu_to_le32((r & 0x7) << 7);
-
-                r <<= AR9170_TX_PHY_MCS_SHIFT;
-                BUG_ON(r & ~AR9170_TX_PHY_MCS_MASK);
-
-                txc->phy_control |= cpu_to_le32(r & AR9170_TX_PHY_MCS_MASK);
-                txc->phy_control |= cpu_to_le32(AR9170_TX_PHY_MOD_HT);
-
-                if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
-                        if (info->band == IEEE80211_BAND_5GHZ)
-                                txpower = ar->power_5G_ht40;
-                        else
-                                txpower = ar->power_2G_ht40;
-                } else {
-                        if (info->band == IEEE80211_BAND_5GHZ)
-                                txpower = ar->power_5G_ht20;
-                        else
-                                txpower = ar->power_2G_ht20;
-                }
-
-                power = txpower[(txrate->idx) & 7];
-        } else {
-                u8 *txpower;
-                u32 mod;
-                u32 phyrate;
-                u8 idx = txrate->idx;
-
-                if (info->band != IEEE80211_BAND_2GHZ) {
-                        idx += 4;
-                        txpower = ar->power_5G_leg;
-                        mod = AR9170_TX_PHY_MOD_OFDM;
-                } else {
-                        if (idx < 4) {
-                                txpower = ar->power_2G_cck;
-                                mod = AR9170_TX_PHY_MOD_CCK;
-                        } else {
-                                mod = AR9170_TX_PHY_MOD_OFDM;
-                                txpower = ar->power_2G_ofdm;
-                        }
-                }
-
-                rate = &__ar9170_ratetable[idx];
-
-                phyrate = rate->hw_value & 0xF;
-                power = txpower[(rate->hw_value & 0x30) >> 4];
-                phyrate <<= AR9170_TX_PHY_MCS_SHIFT;
-
-                txc->phy_control |= cpu_to_le32(mod);
-                txc->phy_control |= cpu_to_le32(phyrate);
-        }
-
-        power <<= AR9170_TX_PHY_TX_PWR_SHIFT;
-        power &= AR9170_TX_PHY_TX_PWR_MASK;
-        txc->phy_control |= cpu_to_le32(power);
-
-        /* set TX chains */
-        if (ar->eeprom.tx_mask == 1) {
-                chains = AR9170_TX_PHY_TXCHAIN_1;
-        } else {
-                chains = AR9170_TX_PHY_TXCHAIN_2;
-
-                /* >= 36M legacy OFDM - use only one chain */
-                if (rate && rate->bitrate >= 360)
-                        chains = AR9170_TX_PHY_TXCHAIN_1;
-        }
-        txc->phy_control |= cpu_to_le32(chains << AR9170_TX_PHY_TXCHAIN_SHIFT);
-}
-
-static void ar9170_tx(struct ar9170 *ar)
-{
-        struct sk_buff *skb;
-        unsigned long flags;
-        struct ieee80211_tx_info *info;
-        struct ar9170_tx_info *arinfo;
-        unsigned int i, frames, frames_failed, remaining_space;
-        int err;
-        bool schedule_garbagecollector = false;
-
-        BUILD_BUG_ON(sizeof(*arinfo) > sizeof(info->rate_driver_data));
-
-        if (unlikely(!IS_STARTED(ar)))
-                return ;
-
-        remaining_space = AR9170_TX_MAX_PENDING;
-
-        for (i = 0; i < __AR9170_NUM_TXQ; i++) {
-                spin_lock_irqsave(&ar->tx_stats_lock, flags);
-                frames = min(ar->tx_stats[i].limit - ar->tx_stats[i].len,
-                             skb_queue_len(&ar->tx_pending[i]));
-
-                if (remaining_space < frames) {
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy,
-                                    "tx quota reached queue:%d, "
-                                    "remaining slots:%d, needed:%d\n",
-                                    i, remaining_space, frames);
-#endif /* AR9170_QUEUE_DEBUG */
-                        frames = remaining_space;
-                }
-
-                ar->tx_stats[i].len += frames;
-                ar->tx_stats[i].count += frames;
-                if (ar->tx_stats[i].len >= ar->tx_stats[i].limit) {
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy, "queue %d full\n", i);
-                        wiphy_debug(ar->hw->wiphy, "stuck frames: ===>\n");
-                        ar9170_dump_txqueue(ar, &ar->tx_pending[i]);
-                        ar9170_dump_txqueue(ar, &ar->tx_status[i]);
-#endif /* AR9170_QUEUE_DEBUG */
-
-#ifdef AR9170_QUEUE_STOP_DEBUG
-                        wiphy_debug(ar->hw->wiphy, "stop queue %d\n", i);
-                        __ar9170_dump_txstats(ar);
-#endif /* AR9170_QUEUE_STOP_DEBUG */
-                        ieee80211_stop_queue(ar->hw, i);
-                }
-
-                spin_unlock_irqrestore(&ar->tx_stats_lock, flags);
-
-                if (!frames)
-                        continue;
-
-                frames_failed = 0;
-                while (frames) {
-                        skb = skb_dequeue(&ar->tx_pending[i]);
-                        if (unlikely(!skb)) {
-                                frames_failed += frames;
-                                frames = 0;
-                                break;
-                        }
-
-                        info = IEEE80211_SKB_CB(skb);
-                        arinfo = (void *) info->rate_driver_data;
-
-                        /* TODO: cancel stuck frames */
-                        arinfo->timeout = jiffies +
-                                          msecs_to_jiffies(AR9170_TX_TIMEOUT);
-
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy, "send frame q:%d =>\n", i);
-                        ar9170_print_txheader(ar, skb);
-#endif /* AR9170_QUEUE_DEBUG */
-
-                        err = ar->tx(ar, skb);
-                        if (unlikely(err)) {
-                                frames_failed++;
-                                dev_kfree_skb_any(skb);
-                        } else {
-                                remaining_space--;
-                                schedule_garbagecollector = true;
-                        }
-
-                        frames--;
-                }
-
-#ifdef AR9170_QUEUE_DEBUG
-                wiphy_debug(ar->hw->wiphy,
-                            "ar9170_tx report for queue %d\n", i);
-
-                wiphy_debug(ar->hw->wiphy,
-                            "unprocessed pending frames left:\n");
-                ar9170_dump_txqueue(ar, &ar->tx_pending[i]);
-#endif /* AR9170_QUEUE_DEBUG */
-
-                if (unlikely(frames_failed)) {
-#ifdef AR9170_QUEUE_DEBUG
-                        wiphy_debug(ar->hw->wiphy,
-                                    "frames failed %d =>\n", frames_failed);
-#endif /* AR9170_QUEUE_DEBUG */
-
-                        spin_lock_irqsave(&ar->tx_stats_lock, flags);
-                        ar->tx_stats[i].len -= frames_failed;
-                        ar->tx_stats[i].count -= frames_failed;
-#ifdef AR9170_QUEUE_STOP_DEBUG
-                        wiphy_debug(ar->hw->wiphy, "wake queue %d\n", i);
-                        __ar9170_dump_txstats(ar);
-#endif /* AR9170_QUEUE_STOP_DEBUG */
-                        ieee80211_wake_queue(ar->hw, i);
-                        spin_unlock_irqrestore(&ar->tx_stats_lock, flags);
-                }
-        }
-
-        if (!schedule_garbagecollector)
-                return;
-
-        ieee80211_queue_delayed_work(ar->hw,
-                                     &ar->tx_janitor,
-                                     msecs_to_jiffies(AR9170_JANITOR_DELAY));
-}
-
-int ar9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
-        struct ar9170 *ar = hw->priv;
-        struct ieee80211_tx_info *info;
-        unsigned int queue;
-
-        if (unlikely(!IS_STARTED(ar)))
-                goto err_free;
-
-        if (unlikely(ar9170_tx_prepare(ar, skb)))
-                goto err_free;
-
-        queue = skb_get_queue_mapping(skb);
-        info = IEEE80211_SKB_CB(skb);
-        ar9170_tx_prepare_phy(ar, skb);
-        skb_queue_tail(&ar->tx_pending[queue], skb);
-
-        ar9170_tx(ar);
-        return NETDEV_TX_OK;
-
-err_free:
-        dev_kfree_skb_any(skb);
-        return NETDEV_TX_OK;
-}
-
-static int ar9170_op_add_interface(struct ieee80211_hw *hw,
-                                   struct ieee80211_vif *vif)
-{
-        struct ar9170 *ar = hw->priv;
-        struct ath_common *common = &ar->common;
-        int err = 0;
-
-        mutex_lock(&ar->mutex);
-
-        if (ar->vif) {
-                err = -EBUSY;
-                goto unlock;
-        }
-
-        ar->vif = vif;
-        memcpy(common->macaddr, vif->addr, ETH_ALEN);
-
-        if (modparam_nohwcrypt || (ar->vif->type != NL80211_IFTYPE_STATION)) {
-                ar->rx_software_decryption = true;
-                ar->disable_offload = true;
-        }
-
-        ar->cur_filter = 0;
-        err = ar9170_update_frame_filter(ar, AR9170_MAC_REG_FTF_DEFAULTS);
-        if (err)
-                goto unlock;
-
-        err = ar9170_set_operating_mode(ar);
-
-unlock:
-        mutex_unlock(&ar->mutex);
-        return err;
-}
-
-static void ar9170_op_remove_interface(struct ieee80211_hw *hw,
-                                       struct ieee80211_vif *vif)
-{
-        struct ar9170 *ar = hw->priv;
-
-        mutex_lock(&ar->mutex);
-        ar->vif = NULL;
-        ar9170_update_frame_filter(ar, 0);
-        ar9170_set_beacon_timers(ar);
-        dev_kfree_skb(ar->beacon);
-        ar->beacon = NULL;
-        ar->sniffer_enabled = false;
-        ar->rx_software_decryption = false;
-        ar9170_set_operating_mode(ar);
-        mutex_unlock(&ar->mutex);
-}
-
-static int ar9170_op_config(struct ieee80211_hw *hw, u32 changed)
-{
-        struct ar9170 *ar = hw->priv;
-        int err = 0;
-
-        mutex_lock(&ar->mutex);
-
-        if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {
-                /* TODO */
-                err = 0;
-        }
-
-        if (changed & IEEE80211_CONF_CHANGE_PS) {
-                /* TODO */
-                err = 0;
-        }
-
-        if (changed & IEEE80211_CONF_CHANGE_POWER) {
-                /* TODO */
-                err = 0;
-        }
-
-        if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
-                /*
-                 * is it long_frame_max_tx_count or short_frame_max_tx_count?
-                 */
-
-                err = ar9170_set_hwretry_limit(ar,
-                        ar->hw->conf.long_frame_max_tx_count);
-                if (err)
-                        goto out;
-        }
-
-        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
-
-                /* adjust slot time for 5 GHz */
-                err = ar9170_set_slot_time(ar);
-                if (err)
-                        goto out;
-
-                err = ar9170_set_dyn_sifs_ack(ar);
-                if (err)
-                        goto out;
-
-                err = ar9170_set_channel(ar, hw->conf.channel,
-                                AR9170_RFI_NONE,
-                                nl80211_to_ar9170(hw->conf.channel_type));
-                if (err)
-                        goto out;
-        }
-
-out:
-        mutex_unlock(&ar->mutex);
-        return err;
-}
-
-static u64 ar9170_op_prepare_multicast(struct ieee80211_hw *hw,
-                                       struct netdev_hw_addr_list *mc_list)
-{
-        u64 mchash;
-        struct netdev_hw_addr *ha;
-
-        /* always get broadcast frames */
-        mchash = 1ULL << (0xff >> 2);
-
-        netdev_hw_addr_list_for_each(ha, mc_list)
-                mchash |= 1ULL << (ha->addr[5] >> 2);
-
-        return mchash;
-}
-
-static void ar9170_op_configure_filter(struct ieee80211_hw *hw,
-                                       unsigned int changed_flags,
-                                       unsigned int *new_flags,
-                                       u64 multicast)
-{
-        struct ar9170 *ar = hw->priv;
-
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return ;
-
-        mutex_lock(&ar->mutex);
-
-        /* mask supported flags */
-        *new_flags &= FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC |
-                      FIF_PROMISC_IN_BSS | FIF_FCSFAIL | FIF_PLCPFAIL;
-        ar->filter_state = *new_flags;
-        /*
-         * We can support more by setting the sniffer bit and
-         * then checking the error flags, later.
-         */
-
-        if (changed_flags & FIF_ALLMULTI && *new_flags & FIF_ALLMULTI)
-                multicast = ~0ULL;
-
-        if (multicast != ar->cur_mc_hash)
-                ar9170_update_multicast(ar, multicast);
-
-        if (changed_flags & FIF_CONTROL) {
-                u32 filter = AR9170_MAC_REG_FTF_PSPOLL |
-                             AR9170_MAC_REG_FTF_RTS |
-                             AR9170_MAC_REG_FTF_CTS |
-                             AR9170_MAC_REG_FTF_ACK |
-                             AR9170_MAC_REG_FTF_CFE |
-                             AR9170_MAC_REG_FTF_CFE_ACK;
-
-                if (*new_flags & FIF_CONTROL)
-                        filter |= ar->cur_filter;
-                else
-                        filter &= (~ar->cur_filter);
-
-                ar9170_update_frame_filter(ar, filter);
-        }
-
-        if (changed_flags & FIF_PROMISC_IN_BSS) {
-                ar->sniffer_enabled = ((*new_flags) & FIF_PROMISC_IN_BSS) != 0;
-                ar9170_set_operating_mode(ar);
-        }
-
-        mutex_unlock(&ar->mutex);
-}
-
-
-static void ar9170_op_bss_info_changed(struct ieee80211_hw *hw,
-                                       struct ieee80211_vif *vif,
-                                       struct ieee80211_bss_conf *bss_conf,
-                                       u32 changed)
-{
-        struct ar9170 *ar = hw->priv;
-        struct ath_common *common = &ar->common;
-        int err = 0;
-
-        mutex_lock(&ar->mutex);
-
-        if (changed & BSS_CHANGED_BSSID) {
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                err = ar9170_set_operating_mode(ar);
-                if (err)
-                        goto out;
-        }
-
-        if (changed & BSS_CHANGED_BEACON_ENABLED)
-                ar->enable_beacon = bss_conf->enable_beacon;
-
-        if (changed & BSS_CHANGED_BEACON) {
-                err = ar9170_update_beacon(ar);
-                if (err)
-                        goto out;
-        }
-
-        if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON |
-                       BSS_CHANGED_BEACON_INT)) {
-                err = ar9170_set_beacon_timers(ar);
-                if (err)
-                        goto out;
-        }
-
-        if (changed & BSS_CHANGED_ASSOC) {
-#ifndef CONFIG_AR9170_LEDS
-                /* enable assoc LED. */
-                err = ar9170_set_leds_state(ar, bss_conf->assoc ? 2 : 0);
-#endif /* CONFIG_AR9170_LEDS */
-        }
-
-        if (changed & BSS_CHANGED_HT) {
-                /* TODO */
-                err = 0;
-        }
-
-        if (changed & BSS_CHANGED_ERP_SLOT) {
-                err = ar9170_set_slot_time(ar);
-                if (err)
-                        goto out;
-        }
-
-        if (changed & BSS_CHANGED_BASIC_RATES) {
-                err = ar9170_set_basic_rates(ar);
-                if (err)
-                        goto out;
-        }
-
-out:
-        mutex_unlock(&ar->mutex);
-}
-
-static u64 ar9170_op_get_tsf(struct ieee80211_hw *hw)
-{
-        struct ar9170 *ar = hw->priv;
-        int err;
-        u64 tsf;
-#define NR 3
-        static const u32 addr[NR] = { AR9170_MAC_REG_TSF_H,
-                                    AR9170_MAC_REG_TSF_L,
-                                    AR9170_MAC_REG_TSF_H };
-        u32 val[NR];
-        int loops = 0;
-
-        mutex_lock(&ar->mutex);
-
-        while (loops++ < 10) {
-                err = ar9170_read_mreg(ar, NR, addr, val);
-                if (err || val[0] == val[2])
-                        break;
-        }
-
-        mutex_unlock(&ar->mutex);
-
-        if (WARN_ON(err))
-                return 0;
-        tsf = val[0];
-        tsf = (tsf << 32) | val[1];
-        return tsf;
-#undef NR
-}
-
-static int ar9170_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
-                          struct ieee80211_vif *vif, struct ieee80211_sta *sta,
-                          struct ieee80211_key_conf *key)
-{
-        struct ar9170 *ar = hw->priv;
-        int err = 0, i;
-        u8 ktype;
-
-        if ((!ar->vif) || (ar->disable_offload))
-                return -EOPNOTSUPP;
-
-        switch (key->alg) {
-        case ALG_WEP:
-                if (key->keylen == WLAN_KEY_LEN_WEP40)
-                        ktype = AR9170_ENC_ALG_WEP64;
-                else
-                        ktype = AR9170_ENC_ALG_WEP128;
-                break;
-        case ALG_TKIP:
-                ktype = AR9170_ENC_ALG_TKIP;
-                break;
-        case ALG_CCMP:
-                ktype = AR9170_ENC_ALG_AESCCMP;
-                break;
-        default:
-                return -EOPNOTSUPP;
-        }
-
-        mutex_lock(&ar->mutex);
-        if (cmd == SET_KEY) {
-                if (unlikely(!IS_STARTED(ar))) {
-                        err = -EOPNOTSUPP;
-                        goto out;
-                }
-
-                /* group keys need all-zeroes address */
-                if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
-                        sta = NULL;
-
-                if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
-                        for (i = 0; i < 64; i++)
-                                if (!(ar->usedkeys & BIT(i)))
-                                        break;
-                        if (i == 64) {
-                                ar->rx_software_decryption = true;
-                                ar9170_set_operating_mode(ar);
-                                err = -ENOSPC;
-                                goto out;
-                        }
-                } else {
-                        i = 64 + key->keyidx;
-                }
-
-                key->hw_key_idx = i;
-
-                err = ar9170_upload_key(ar, i, sta ? sta->addr : NULL, ktype, 0,
-                                        key->key, min_t(u8, 16, key->keylen));
-                if (err)
-                        goto out;
-
-                if (key->alg == ALG_TKIP) {
-                        err = ar9170_upload_key(ar, i, sta ? sta->addr : NULL,
-                                                ktype, 1, key->key + 16, 16);
-                        if (err)
-                                goto out;
-
-                        /*
-                         * hardware is not capable generating the MMIC
-                         * for fragmented frames!
-                         */
-                        key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
-                }
-
-                if (i < 64)
-                        ar->usedkeys |= BIT(i);
-
-                key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
-        } else {
-                if (unlikely(!IS_STARTED(ar))) {
-                        /* The device is gone... together with the key ;-) */
-                        err = 0;
-                        goto out;
-                }
-
-                err = ar9170_disable_key(ar, key->hw_key_idx);
-                if (err)
-                        goto out;
-
-                if (key->hw_key_idx < 64) {
-                        ar->usedkeys &= ~BIT(key->hw_key_idx);
-                } else {
-                        err = ar9170_upload_key(ar, key->hw_key_idx, NULL,
-                                                AR9170_ENC_ALG_NONE, 0,
-                                                NULL, 0);
-                        if (err)
-                                goto out;
-
-                        if (key->alg == ALG_TKIP) {
-                                err = ar9170_upload_key(ar, key->hw_key_idx,
-                                                        NULL,
-                                                        AR9170_ENC_ALG_NONE, 1,
-                                                        NULL, 0);
-                                if (err)
-                                        goto out;
-                        }
-
-                }
-        }
-
-        ar9170_regwrite_begin(ar);
-        ar9170_regwrite(AR9170_MAC_REG_ROLL_CALL_TBL_L, ar->usedkeys);
-        ar9170_regwrite(AR9170_MAC_REG_ROLL_CALL_TBL_H, ar->usedkeys >> 32);
-        ar9170_regwrite_finish();
-        err = ar9170_regwrite_result();
-
-out:
-        mutex_unlock(&ar->mutex);
-
-        return err;
-}
-
-static int ar9170_get_stats(struct ieee80211_hw *hw,
-                            struct ieee80211_low_level_stats *stats)
-{
-        struct ar9170 *ar = hw->priv;
-        u32 val;
-        int err;
-
-        mutex_lock(&ar->mutex);
-        err = ar9170_read_reg(ar, AR9170_MAC_REG_TX_RETRY, &val);
-        ar->stats.dot11ACKFailureCount += val;
-
-        memcpy(stats, &ar->stats, sizeof(*stats));
-        mutex_unlock(&ar->mutex);
-
-        return 0;
-}
-
-static int ar9170_get_survey(struct ieee80211_hw *hw, int idx,
-                                struct survey_info *survey)
-{
-        struct ar9170 *ar = hw->priv;
-        struct ieee80211_conf *conf = &hw->conf;
-
-        if (idx != 0)
-                return -ENOENT;
-
-        /* TODO: update noise value, e.g. call ar9170_set_channel */
-
-        survey->channel = conf->channel;
-        survey->filled = SURVEY_INFO_NOISE_DBM;
-        survey->noise = ar->noise[0];
-
-        return 0;
-}
-
-static int ar9170_conf_tx(struct ieee80211_hw *hw, u16 queue,
-                          const struct ieee80211_tx_queue_params *param)
-{
-        struct ar9170 *ar = hw->priv;
-        int ret;
-
-        mutex_lock(&ar->mutex);
-        if (queue < __AR9170_NUM_TXQ) {
-                memcpy(&ar->edcf[ar9170_qos_hwmap[queue]],
-                       param, sizeof(*param));
-
-                ret = ar9170_set_qos(ar);
-        } else {
-                ret = -EINVAL;
-        }
-
-        mutex_unlock(&ar->mutex);
-        return ret;
-}
-
-static int ar9170_ampdu_action(struct ieee80211_hw *hw,
-                               struct ieee80211_vif *vif,
-                               enum ieee80211_ampdu_mlme_action action,
-                               struct ieee80211_sta *sta, u16 tid, u16 *ssn)
-{
-        switch (action) {
-        case IEEE80211_AMPDU_RX_START:
-        case IEEE80211_AMPDU_RX_STOP:
-                /* Handled by firmware */
-                break;
-
-        default:
-                return -EOPNOTSUPP;
-        }
-
-        return 0;
-}
-
-static const struct ieee80211_ops ar9170_ops = {
-        .start                  = ar9170_op_start,
-        .stop                   = ar9170_op_stop,
-        .tx                     = ar9170_op_tx,
-        .add_interface          = ar9170_op_add_interface,
-        .remove_interface       = ar9170_op_remove_interface,
-        .config                 = ar9170_op_config,
-        .prepare_multicast      = ar9170_op_prepare_multicast,
-        .configure_filter       = ar9170_op_configure_filter,
-        .conf_tx                = ar9170_conf_tx,
-        .bss_info_changed       = ar9170_op_bss_info_changed,
-        .get_tsf                = ar9170_op_get_tsf,
-        .set_key                = ar9170_set_key,
-        .get_stats              = ar9170_get_stats,
-        .get_survey             = ar9170_get_survey,
-        .ampdu_action           = ar9170_ampdu_action,
-};
-
-void *ar9170_alloc(size_t priv_size)
-{
-        struct ieee80211_hw *hw;
-        struct ar9170 *ar;
-        struct sk_buff *skb;
-        int i;
-
-        /*
-         * this buffer is used for rx stream reconstruction.
-         * Under heavy load this device (or the transport layer?)
-         * tends to split the streams into separate rx descriptors.
-         */
-
-        skb = __dev_alloc_skb(AR9170_RX_STREAM_MAX_SIZE, GFP_KERNEL);
-        if (!skb)
-                goto err_nomem;
-
-        hw = ieee80211_alloc_hw(priv_size, &ar9170_ops);
-        if (!hw)
-                goto err_nomem;
-
-        ar = hw->priv;
-        ar->hw = hw;
-        ar->rx_failover = skb;
-
-        mutex_init(&ar->mutex);
-        spin_lock_init(&ar->cmdlock);
-        spin_lock_init(&ar->tx_stats_lock);
-        for (i = 0; i < __AR9170_NUM_TXQ; i++) {
-                skb_queue_head_init(&ar->tx_status[i]);
-                skb_queue_head_init(&ar->tx_pending[i]);
-        }
-        ar9170_rx_reset_rx_mpdu(ar);
-        INIT_WORK(&ar->beacon_work, ar9170_new_beacon);
-        INIT_DELAYED_WORK(&ar->tx_janitor, ar9170_tx_janitor);
-
-        /* all hw supports 2.4 GHz, so set channel to 1 by default */
-        ar->channel = &ar9170_2ghz_chantable[0];
-
-        /* first part of wiphy init */
-        ar->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
-                                         BIT(NL80211_IFTYPE_WDS) |
-                                         BIT(NL80211_IFTYPE_ADHOC);
-        ar->hw->flags |= IEEE80211_HW_RX_INCLUDES_FCS |
-                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
-                         IEEE80211_HW_SIGNAL_DBM;
-
-        ar->hw->queues = __AR9170_NUM_TXQ;
-        ar->hw->extra_tx_headroom = 8;
-
-        ar->hw->max_rates = 1;
-        ar->hw->max_rate_tries = 3;
-
-        for (i = 0; i < ARRAY_SIZE(ar->noise); i++)
-                ar->noise[i] = -95; /* ATH_DEFAULT_NOISE_FLOOR */
-
-        return ar;
-
-err_nomem:
-        kfree_skb(skb);
-        return ERR_PTR(-ENOMEM);
-}
-
-static int ar9170_read_eeprom(struct ar9170 *ar)
-{
-#define RW      8       /* number of words to read at once */
-#define RB      (sizeof(u32) * RW)
-        struct ath_regulatory *regulatory = &ar->common.regulatory;
-        u8 *eeprom = (void *)&ar->eeprom;
-        u8 *addr = ar->eeprom.mac_address;
-        __le32 offsets[RW];
-        unsigned int rx_streams, tx_streams, tx_params = 0;
-        int i, j, err, bands = 0;
-
-        BUILD_BUG_ON(sizeof(ar->eeprom) & 3);
-
-        BUILD_BUG_ON(RB > AR9170_MAX_CMD_LEN - 4);
-#ifndef __CHECKER__
-        /* don't want to handle trailing remains */
-        BUILD_BUG_ON(sizeof(ar->eeprom) % RB);
-#endif
-
-        for (i = 0; i < sizeof(ar->eeprom)/RB; i++) {
-                for (j = 0; j < RW; j++)
-                        offsets[j] = cpu_to_le32(AR9170_EEPROM_START +
-                                                 RB * i + 4 * j);
-
-                err = ar->exec_cmd(ar, AR9170_CMD_RREG,
-                                   RB, (u8 *) &offsets,
-                                   RB, eeprom + RB * i);
-                if (err)
-                        return err;
-        }
-
-#undef RW
-#undef RB
-
-        if (ar->eeprom.length == cpu_to_le16(0xFFFF))
-                return -ENODATA;
-
-        if (ar->eeprom.operating_flags & AR9170_OPFLAG_2GHZ) {
-                ar->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &ar9170_band_2GHz;
-                bands++;
-        }
-        if (ar->eeprom.operating_flags & AR9170_OPFLAG_5GHZ) {
-                ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &ar9170_band_5GHz;
-                bands++;
-        }
-
-        rx_streams = hweight8(ar->eeprom.rx_mask);
-        tx_streams = hweight8(ar->eeprom.tx_mask);
-
-        if (rx_streams != tx_streams)
-                tx_params = IEEE80211_HT_MCS_TX_RX_DIFF;
-
-        if (tx_streams >= 1 && tx_streams <= IEEE80211_HT_MCS_TX_MAX_STREAMS)
-                tx_params = (tx_streams - 1) <<
-                            IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
-
-        ar9170_band_2GHz.ht_cap.mcs.tx_params |= tx_params;
-        ar9170_band_5GHz.ht_cap.mcs.tx_params |= tx_params;
-
-        /*
-         * I measured this, a bandswitch takes roughly
-         * 135 ms and a frequency switch about 80.
-         *
-         * FIXME: measure these values again once EEPROM settings
-         *        are used, that will influence them!
-         */
-        if (bands == 2)
-                ar->hw->channel_change_time = 135 * 1000;
-        else
-                ar->hw->channel_change_time = 80 * 1000;
-
-        regulatory->current_rd = le16_to_cpu(ar->eeprom.reg_domain[0]);
-        regulatory->current_rd_ext = le16_to_cpu(ar->eeprom.reg_domain[1]);
-
-        /* second part of wiphy init */
-        SET_IEEE80211_PERM_ADDR(ar->hw, addr);
-
-        return bands ? 0 : -EINVAL;
-}
-
-static int ar9170_reg_notifier(struct wiphy *wiphy,
-                        struct regulatory_request *request)
-{
-        struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
-        struct ar9170 *ar = hw->priv;
-
-        return ath_reg_notifier_apply(wiphy, request, &ar->common.regulatory);
-}
-
-int ar9170_register(struct ar9170 *ar, struct device *pdev)
-{
-        struct ath_regulatory *regulatory = &ar->common.regulatory;
-        int err;
-
-        /* try to read EEPROM, init MAC addr */
-        err = ar9170_read_eeprom(ar);
-        if (err)
-                goto err_out;
-
-        err = ath_regd_init(regulatory, ar->hw->wiphy,
-                            ar9170_reg_notifier);
-        if (err)
-                goto err_out;
-
-        err = ieee80211_register_hw(ar->hw);
-        if (err)
-                goto err_out;
-
-        if (!ath_is_world_regd(regulatory))
-                regulatory_hint(ar->hw->wiphy, regulatory->alpha2);
-
-        err = ar9170_init_leds(ar);
-        if (err)
-                goto err_unreg;
-
-#ifdef CONFIG_AR9170_LEDS
-        err = ar9170_register_leds(ar);
-        if (err)
-                goto err_unreg;
-#endif /* CONFIG_AR9170_LEDS */
-
-        dev_info(pdev, "Atheros AR9170 is registered as '%s'\n",
-                 wiphy_name(ar->hw->wiphy));
-
-        ar->registered = true;
-        return 0;
-
-err_unreg:
-        ieee80211_unregister_hw(ar->hw);
-
-err_out:
-        return err;
-}
-
-void ar9170_unregister(struct ar9170 *ar)
-{
-        if (ar->registered) {
-#ifdef CONFIG_AR9170_LEDS
-                ar9170_unregister_leds(ar);
-#endif /* CONFIG_AR9170_LEDS */
-
-        ieee80211_unregister_hw(ar->hw);
-        }
-
-        kfree_skb(ar->rx_failover);
-        mutex_destroy(&ar->mutex);
-}
diff --git a/drivers/net/wireless/ath/ar9170/usb.c b/drivers/net/wireless/ath/ar9170/usb.c
deleted file mode 100644
index a93dc18a45c3..000000000000
--- a/drivers/net/wireless/ath/ar9170/usb.c
+++ /dev/null
@@ -1,1012 +0,0 @@
-/*
- * Atheros AR9170 driver
- *
- * USB - frontend
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- * Copyright 2009, Christian Lamparter <chunkeey@web.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/usb.h>
-#include <linux/firmware.h>
-#include <linux/etherdevice.h>
-#include <linux/device.h>
-#include <net/mac80211.h>
-#include "ar9170.h"
-#include "cmd.h"
-#include "hw.h"
-#include "usb.h"
-
-MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
-MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Atheros AR9170 802.11n USB wireless");
-MODULE_FIRMWARE("ar9170.fw");
-MODULE_FIRMWARE("ar9170-1.fw");
-MODULE_FIRMWARE("ar9170-2.fw");
-
-enum ar9170_requirements {
-        AR9170_REQ_FW1_ONLY = 1,
-};
-
-static struct usb_device_id ar9170_usb_ids[] = {
-        /* Atheros 9170 */
-        { USB_DEVICE(0x0cf3, 0x9170) },
-        /* Atheros TG121N */
-        { USB_DEVICE(0x0cf3, 0x1001) },
-        /* TP-Link TL-WN821N v2 */
-        { USB_DEVICE(0x0cf3, 0x1002) },
-        /* 3Com Dual Band 802.11n USB Adapter */
-        { USB_DEVICE(0x0cf3, 0x1010) },
-        /* H3C Dual Band 802.11n USB Adapter */
-        { USB_DEVICE(0x0cf3, 0x1011) },
-        /* Cace Airpcap NX */
-        { USB_DEVICE(0xcace, 0x0300) },
-        /* D-Link DWA 160 A1 */
-        { USB_DEVICE(0x07d1, 0x3c10) },
-        /* D-Link DWA 160 A2 */
-        { USB_DEVICE(0x07d1, 0x3a09) },
-        /* Netgear WNA1000 */
-        { USB_DEVICE(0x0846, 0x9040) },
-        /* Netgear WNDA3100 */
-        { USB_DEVICE(0x0846, 0x9010) },
-        /* Netgear WN111 v2 */
-        { USB_DEVICE(0x0846, 0x9001) },
-        /* Zydas ZD1221 */
-        { USB_DEVICE(0x0ace, 0x1221) },
-        /* Proxim ORiNOCO 802.11n USB */
-        { USB_DEVICE(0x1435, 0x0804) },
-        /* WNC Generic 11n USB Dongle */
-        { USB_DEVICE(0x1435, 0x0326) },
-        /* ZyXEL NWD271N */
-        { USB_DEVICE(0x0586, 0x3417) },
-        /* Z-Com UB81 BG */
-        { USB_DEVICE(0x0cde, 0x0023) },
-        /* Z-Com UB82 ABG */
-        { USB_DEVICE(0x0cde, 0x0026) },
-        /* Sphairon Homelink 1202 */
-        { USB_DEVICE(0x0cde, 0x0027) },
-        /* Arcadyan WN7512 */
-        { USB_DEVICE(0x083a, 0xf522) },
-        /* Planex GWUS300 */
-        { USB_DEVICE(0x2019, 0x5304) },
-        /* IO-Data WNGDNUS2 */
-        { USB_DEVICE(0x04bb, 0x093f) },
-        /* AVM FRITZ!WLAN USB Stick N */
-        { USB_DEVICE(0x057C, 0x8401) },
-        /* NEC WL300NU-G */
-        { USB_DEVICE(0x0409, 0x0249) },
-        /* AVM FRITZ!WLAN USB Stick N 2.4 */
-        { USB_DEVICE(0x057C, 0x8402), .driver_info = AR9170_REQ_FW1_ONLY },
-        /* Qwest/Actiontec 802AIN Wireless N USB Network Adapter */
-        { USB_DEVICE(0x1668, 0x1200) },
-
-        /* terminate */
-        {}
-};
-MODULE_DEVICE_TABLE(usb, ar9170_usb_ids);
-
-static void ar9170_usb_submit_urb(struct ar9170_usb *aru)
-{
-        struct urb *urb;
-        unsigned long flags;
-        int err;
-
-        if (unlikely(!IS_STARTED(&aru->common)))
-                return ;
-
-        spin_lock_irqsave(&aru->tx_urb_lock, flags);
-        if (atomic_read(&aru->tx_submitted_urbs) >= AR9170_NUM_TX_URBS) {
-                spin_unlock_irqrestore(&aru->tx_urb_lock, flags);
-                return ;
-        }
-        atomic_inc(&aru->tx_submitted_urbs);
-
-        urb = usb_get_from_anchor(&aru->tx_pending);
-        if (!urb) {
-                atomic_dec(&aru->tx_submitted_urbs);
-                spin_unlock_irqrestore(&aru->tx_urb_lock, flags);
-
-                return ;
-        }
-        spin_unlock_irqrestore(&aru->tx_urb_lock, flags);
-
-        aru->tx_pending_urbs--;
-        usb_anchor_urb(urb, &aru->tx_submitted);
-
-        err = usb_submit_urb(urb, GFP_ATOMIC);
-        if (unlikely(err)) {
-                if (ar9170_nag_limiter(&aru->common))
-                        dev_err(&aru->udev->dev, "submit_urb failed (%d).\n",
-                                err);
-
-                usb_unanchor_urb(urb);
-                atomic_dec(&aru->tx_submitted_urbs);
-                ar9170_tx_callback(&aru->common, urb->context);
-        }
-
-        usb_free_urb(urb);
-}
-
-static void ar9170_usb_tx_urb_complete_frame(struct urb *urb)
-{
-        struct sk_buff *skb = urb->context;
-        struct ar9170_usb *aru = (struct ar9170_usb *)
-              usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
-
-        if (unlikely(!aru)) {
-                dev_kfree_skb_irq(skb);
-                return ;
-        }
-
-        atomic_dec(&aru->tx_submitted_urbs);
-
-        ar9170_tx_callback(&aru->common, skb);
-
-        ar9170_usb_submit_urb(aru);
-}
-
-static void ar9170_usb_tx_urb_complete(struct urb *urb)
-{
-}
-
-static void ar9170_usb_irq_completed(struct urb *urb)
-{
-        struct ar9170_usb *aru = urb->context;
-
-        switch (urb->status) {
-        /* everything is fine */
-        case 0:
-                break;
-
-        /* disconnect */
-        case -ENOENT:
-        case -ECONNRESET:
-        case -ENODEV:
-        case -ESHUTDOWN:
-                goto free;
-
-        default:
-                goto resubmit;
-        }
-
-        ar9170_handle_command_response(&aru->common, urb->transfer_buffer,
-                                       urb->actual_length);
-
-resubmit:
-        usb_anchor_urb(urb, &aru->rx_submitted);
-        if (usb_submit_urb(urb, GFP_ATOMIC)) {
-                usb_unanchor_urb(urb);
-                goto free;
-        }
-
-        return;
-
-free:
-        usb_free_coherent(aru->udev, 64, urb->transfer_buffer, urb->transfer_dma);
-}
-
-static void ar9170_usb_rx_completed(struct urb *urb)
-{
-        struct sk_buff *skb = urb->context;
-        struct ar9170_usb *aru = (struct ar9170_usb *)
-                usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
-        int err;
-
-        if (!aru)
-                goto free;
-
-        switch (urb->status) {
-        /* everything is fine */
-        case 0:
-                break;
-
-        /* disconnect */
-        case -ENOENT:
-        case -ECONNRESET:
-        case -ENODEV:
-        case -ESHUTDOWN:
-                goto free;
-
-        default:
-                goto resubmit;
-        }
-
-        skb_put(skb, urb->actual_length);
-        ar9170_rx(&aru->common, skb);
-
-resubmit:
-        skb_reset_tail_pointer(skb);
-        skb_trim(skb, 0);
-
-        usb_anchor_urb(urb, &aru->rx_submitted);
-        err = usb_submit_urb(urb, GFP_ATOMIC);
-        if (unlikely(err)) {
-                usb_unanchor_urb(urb);
-                goto free;
-        }
-
-        return ;
-
-free:
-        dev_kfree_skb_irq(skb);
-}
-
-static int ar9170_usb_prep_rx_urb(struct ar9170_usb *aru,
-                                  struct urb *urb, gfp_t gfp)
-{
-        struct sk_buff *skb;
-
-        skb = __dev_alloc_skb(AR9170_MAX_RX_BUFFER_SIZE + 32, gfp);
-        if (!skb)
-                return -ENOMEM;
-
-        /* reserve some space for mac80211's radiotap */
-        skb_reserve(skb, 32);
-
-        usb_fill_bulk_urb(urb, aru->udev,
-                          usb_rcvbulkpipe(aru->udev, AR9170_EP_RX),
-                          skb->data, min(skb_tailroom(skb),
-                          AR9170_MAX_RX_BUFFER_SIZE),
-                          ar9170_usb_rx_completed, skb);
-
-        return 0;
-}
-
-static int ar9170_usb_alloc_rx_irq_urb(struct ar9170_usb *aru)
-{
-        struct urb *urb = NULL;
-        void *ibuf;
-        int err = -ENOMEM;
-
-        /* initialize interrupt endpoint */
-        urb = usb_alloc_urb(0, GFP_KERNEL);
-        if (!urb)
-                goto out;
-
-        ibuf = usb_alloc_coherent(aru->udev, 64, GFP_KERNEL, &urb->transfer_dma);
-        if (!ibuf)
-                goto out;
-
-        usb_fill_int_urb(urb, aru->udev,
-                         usb_rcvintpipe(aru->udev, AR9170_EP_IRQ), ibuf,
-                         64, ar9170_usb_irq_completed, aru, 1);
-        urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
-
-        usb_anchor_urb(urb, &aru->rx_submitted);
-        err = usb_submit_urb(urb, GFP_KERNEL);
-        if (err) {
-                usb_unanchor_urb(urb);
-                usb_free_coherent(aru->udev, 64, urb->transfer_buffer,
-                                  urb->transfer_dma);
-        }
-
-out:
-        usb_free_urb(urb);
-        return err;
-}
-
-static int ar9170_usb_alloc_rx_bulk_urbs(struct ar9170_usb *aru)
-{
-        struct urb *urb;
-        int i;
-        int err = -EINVAL;
-
-        for (i = 0; i < AR9170_NUM_RX_URBS; i++) {
-                err = -ENOMEM;
-                urb = usb_alloc_urb(0, GFP_KERNEL);
-                if (!urb)
-                        goto err_out;
-
-                err = ar9170_usb_prep_rx_urb(aru, urb, GFP_KERNEL);
-                if (err) {
-                        usb_free_urb(urb);
-                        goto err_out;
-                }
-
-                usb_anchor_urb(urb, &aru->rx_submitted);
-                err = usb_submit_urb(urb, GFP_KERNEL);
-                if (err) {
-                        usb_unanchor_urb(urb);
-                        dev_kfree_skb_any((void *) urb->transfer_buffer);
-                        usb_free_urb(urb);
-                        goto err_out;
-                }
-                usb_free_urb(urb);
-        }
-
-        /* the device now waiting for a firmware. */
-        aru->common.state = AR9170_IDLE;
-        return 0;
-
-err_out:
-
-        usb_kill_anchored_urbs(&aru->rx_submitted);
-        return err;
-}
-
-static int ar9170_usb_flush(struct ar9170 *ar)
-{
-        struct ar9170_usb *aru = (void *) ar;
-        struct urb *urb;
-        int ret, err = 0;
-
-        if (IS_STARTED(ar))
-                aru->common.state = AR9170_IDLE;
-
-        usb_wait_anchor_empty_timeout(&aru->tx_pending,
-                                            msecs_to_jiffies(800));
-        while ((urb = usb_get_from_anchor(&aru->tx_pending))) {
-                ar9170_tx_callback(&aru->common, (void *) urb->context);
-                usb_free_urb(urb);
-        }
-
-        /* lets wait a while until the tx - queues are dried out */
-        ret = usb_wait_anchor_empty_timeout(&aru->tx_submitted,
-                                            msecs_to_jiffies(100));
-        if (ret == 0)
-                err = -ETIMEDOUT;
-
-        usb_kill_anchored_urbs(&aru->tx_submitted);
-
-        if (IS_ACCEPTING_CMD(ar))
-                aru->common.state = AR9170_STARTED;
-
-        return err;
-}
-
-static void ar9170_usb_cancel_urbs(struct ar9170_usb *aru)
-{
-        int err;
-
-        aru->common.state = AR9170_UNKNOWN_STATE;
-
-        err = ar9170_usb_flush(&aru->common);
-        if (err)
-                dev_err(&aru->udev->dev, "stuck tx urbs!\n");
-
-        usb_poison_anchored_urbs(&aru->tx_submitted);
-        usb_poison_anchored_urbs(&aru->rx_submitted);
-}
-
-static int ar9170_usb_exec_cmd(struct ar9170 *ar, enum ar9170_cmd cmd,
-                               unsigned int plen, void *payload,
-                               unsigned int outlen, void *out)
-{
-        struct ar9170_usb *aru = (void *) ar;
-        struct urb *urb = NULL;
-        unsigned long flags;
-        int err = -ENOMEM;
-
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return -EPERM;
-
-        if (WARN_ON(plen > AR9170_MAX_CMD_LEN - 4))
-                return -EINVAL;
-
-        urb = usb_alloc_urb(0, GFP_ATOMIC);
-        if (unlikely(!urb))
-                goto err_free;
-
-        ar->cmdbuf[0] = cpu_to_le32(plen);
-        ar->cmdbuf[0] |= cpu_to_le32(cmd << 8);
-        /* writing multiple regs fills this buffer already */
-        if (plen && payload != (u8 *)(&ar->cmdbuf[1]))
-                memcpy(&ar->cmdbuf[1], payload, plen);
-
-        spin_lock_irqsave(&aru->common.cmdlock, flags);
-        aru->readbuf = (u8 *)out;
-        aru->readlen = outlen;
-        spin_unlock_irqrestore(&aru->common.cmdlock, flags);
-
-        usb_fill_int_urb(urb, aru->udev,
-                         usb_sndintpipe(aru->udev, AR9170_EP_CMD),
-                         aru->common.cmdbuf, plen + 4,
-                         ar9170_usb_tx_urb_complete, NULL, 1);
-
-        usb_anchor_urb(urb, &aru->tx_submitted);
-        err = usb_submit_urb(urb, GFP_ATOMIC);
-        if (unlikely(err)) {
-                usb_unanchor_urb(urb);
-                usb_free_urb(urb);
-                goto err_unbuf;
-        }
-        usb_free_urb(urb);
-
-        err = wait_for_completion_timeout(&aru->cmd_wait, HZ);
-        if (err == 0) {
-                err = -ETIMEDOUT;
-                goto err_unbuf;
-        }
-
-        if (aru->readlen != outlen) {
-                err = -EMSGSIZE;
-                goto err_unbuf;
-        }
-
-        return 0;
-
-err_unbuf:
-        /* Maybe the device was removed in the second we were waiting? */
-        if (IS_STARTED(ar)) {
-                dev_err(&aru->udev->dev, "no command feedback "
-                                         "received (%d).\n", err);
-
-                /* provide some maybe useful debug information */
-                print_hex_dump_bytes("ar9170 cmd: ", DUMP_PREFIX_NONE,
-                                     aru->common.cmdbuf, plen + 4);
-                dump_stack();
-        }
-
-        /* invalidate to avoid completing the next prematurely */
-        spin_lock_irqsave(&aru->common.cmdlock, flags);
-        aru->readbuf = NULL;
-        aru->readlen = 0;
-        spin_unlock_irqrestore(&aru->common.cmdlock, flags);
-
-err_free:
-
-        return err;
-}
-
-static int ar9170_usb_tx(struct ar9170 *ar, struct sk_buff *skb)
-{
-        struct ar9170_usb *aru = (struct ar9170_usb *) ar;
-        struct urb *urb;
-
-        if (unlikely(!IS_STARTED(ar))) {
-                /* Seriously, what were you drink... err... thinking!? */
-                return -EPERM;
-        }
-
-        urb = usb_alloc_urb(0, GFP_ATOMIC);
-        if (unlikely(!urb))
-                return -ENOMEM;
-
-        usb_fill_bulk_urb(urb, aru->udev,
-                          usb_sndbulkpipe(aru->udev, AR9170_EP_TX),
-                          skb->data, skb->len,
-                          ar9170_usb_tx_urb_complete_frame, skb);
-        urb->transfer_flags |= URB_ZERO_PACKET;
-
-        usb_anchor_urb(urb, &aru->tx_pending);
-        aru->tx_pending_urbs++;
-
-        usb_free_urb(urb);
-
-        ar9170_usb_submit_urb(aru);
-        return 0;
-}
-
-static void ar9170_usb_callback_cmd(struct ar9170 *ar, u32 len , void *buffer)
-{
-        struct ar9170_usb *aru = (void *) ar;
-        unsigned long flags;
-        u32 in, out;
-
-        if (unlikely(!buffer))
-                return ;
-
-        in = le32_to_cpup((__le32 *)buffer);
-        out = le32_to_cpu(ar->cmdbuf[0]);
-
-        /* mask off length byte */
-        out &= ~0xFF;
-
-        if (aru->readlen >= 0) {
-                /* add expected length */
-                out |= aru->readlen;
-        } else {
-                /* add obtained length */
-                out |= in & 0xFF;
-        }
-
-        /*
-         * Some commands (e.g: AR9170_CMD_FREQUENCY) have a variable response
-         * length and we cannot predict the correct length in advance.
-         * So we only check if we provided enough space for the data.
-         */
-        if (unlikely(out < in)) {
-                dev_warn(&aru->udev->dev, "received invalid command response "
-                                          "got %d bytes, instead of %d bytes "
-                                          "and the resp length is %d bytes\n",
-                         in, out, len);
-                print_hex_dump_bytes("ar9170 invalid resp: ",
-                                     DUMP_PREFIX_OFFSET, buffer, len);
-                /*
-                 * Do not complete, then the command times out,
-                 * and we get a stack trace from there.
-                 */
-                return ;
-        }
-
-        spin_lock_irqsave(&aru->common.cmdlock, flags);
-        if (aru->readbuf && len > 0) {
-                memcpy(aru->readbuf, buffer + 4, len - 4);
-                aru->readbuf = NULL;
-        }
-        complete(&aru->cmd_wait);
-        spin_unlock_irqrestore(&aru->common.cmdlock, flags);
-}
-
-static int ar9170_usb_upload(struct ar9170_usb *aru, const void *data,
-                             size_t len, u32 addr, bool complete)
-{
-        int transfer, err;
-        u8 *buf = kmalloc(4096, GFP_KERNEL);
-
-        if (!buf)
-                return -ENOMEM;
-
-        while (len) {
-                transfer = min_t(int, len, 4096);
-                memcpy(buf, data, transfer);
-
-                err = usb_control_msg(aru->udev, usb_sndctrlpipe(aru->udev, 0),
-                                      0x30 /* FW DL */, 0x40 | USB_DIR_OUT,
-                                      addr >> 8, 0, buf, transfer, 1000);
-
-                if (err < 0) {
-                        kfree(buf);
-                        return err;
-                }
-
-                len -= transfer;
-                data += transfer;
-                addr += transfer;
-        }
-        kfree(buf);
-
-        if (complete) {
-                err = usb_control_msg(aru->udev, usb_sndctrlpipe(aru->udev, 0),
-                                      0x31 /* FW DL COMPLETE */,
-                                      0x40 | USB_DIR_OUT, 0, 0, NULL, 0, 5000);
-        }
-
-        return 0;
-}
-
-static int ar9170_usb_reset(struct ar9170_usb *aru)
-{
-        int ret, lock = (aru->intf->condition != USB_INTERFACE_BINDING);
-
-        if (lock) {
-                ret = usb_lock_device_for_reset(aru->udev, aru->intf);
-                if (ret < 0) {
-                        dev_err(&aru->udev->dev, "unable to lock device "
-                                "for reset (%d).\n", ret);
-                        return ret;
-                }
-        }
-
-        ret = usb_reset_device(aru->udev);
-        if (lock)
-                usb_unlock_device(aru->udev);
-
-        /* let it rest - for a second - */
-        msleep(1000);
-
-        return ret;
-}
-
-static int ar9170_usb_upload_firmware(struct ar9170_usb *aru)
-{
-        int err;
-
-        if (!aru->init_values)
-                goto upload_fw_start;
-
-        /* First, upload initial values to device RAM */
-        err = ar9170_usb_upload(aru, aru->init_values->data,
-                                aru->init_values->size, 0x102800, false);
-        if (err) {
-                dev_err(&aru->udev->dev, "firmware part 1 "
-                        "upload failed (%d).\n", err);
-                return err;
-        }
-
-upload_fw_start:
-
-        /* Then, upload the firmware itself and start it */
-        return ar9170_usb_upload(aru, aru->firmware->data, aru->firmware->size,
-                                0x200000, true);
-}
-
-static int ar9170_usb_init_transport(struct ar9170_usb *aru)
-{
-        struct ar9170 *ar = (void *) &aru->common;
-        int err;
-
-        ar9170_regwrite_begin(ar);
-
-        /* Set USB Rx stream mode MAX packet number to 2 */
-        ar9170_regwrite(AR9170_USB_REG_MAX_AGG_UPLOAD, 0x4);
-
-        /* Set USB Rx stream mode timeout to 10us */
-        ar9170_regwrite(AR9170_USB_REG_UPLOAD_TIME_CTL, 0x80);
-
-        ar9170_regwrite_finish();
-
-        err = ar9170_regwrite_result();
-        if (err)
-                dev_err(&aru->udev->dev, "USB setup failed (%d).\n", err);
-
-        return err;
-}
-
-static void ar9170_usb_stop(struct ar9170 *ar)
-{
-        struct ar9170_usb *aru = (void *) ar;
-        int ret;
-
-        if (IS_ACCEPTING_CMD(ar))
-                aru->common.state = AR9170_STOPPED;
-
-        ret = ar9170_usb_flush(ar);
-        if (ret)
-                dev_err(&aru->udev->dev, "kill pending tx urbs.\n");
-
-        usb_poison_anchored_urbs(&aru->tx_submitted);
-
-        /*
-         * Note:
-         * So far we freed all tx urbs, but we won't dare to touch any rx urbs.
-         * Else we would end up with a unresponsive device...
-         */
-}
-
-static int ar9170_usb_open(struct ar9170 *ar)
-{
-        struct ar9170_usb *aru = (void *) ar;
-        int err;
-
-        usb_unpoison_anchored_urbs(&aru->tx_submitted);
-        err = ar9170_usb_init_transport(aru);
-        if (err) {
-                usb_poison_anchored_urbs(&aru->tx_submitted);
-                return err;
-        }
-
-        aru->common.state = AR9170_IDLE;
-        return 0;
-}
-
-static int ar9170_usb_init_device(struct ar9170_usb *aru)
-{
-        int err;
-
-        err = ar9170_usb_alloc_rx_irq_urb(aru);
-        if (err)
-                goto err_out;
-
-        err = ar9170_usb_alloc_rx_bulk_urbs(aru);
-        if (err)
-                goto err_unrx;
-
-        err = ar9170_usb_upload_firmware(aru);
-        if (err) {
-                err = ar9170_echo_test(&aru->common, 0x60d43110);
-                if (err) {
-                        /* force user invention, by disabling the device */
-                        err = usb_driver_set_configuration(aru->udev, -1);
-                        dev_err(&aru->udev->dev, "device is in a bad state. "
-                                                 "please reconnect it!\n");
-                        goto err_unrx;
-                }
-        }
-
-        return 0;
-
-err_unrx:
-        ar9170_usb_cancel_urbs(aru);
-
-err_out:
-        return err;
-}
-
-static void ar9170_usb_firmware_failed(struct ar9170_usb *aru)
-{
-        struct device *parent = aru->udev->dev.parent;
-        struct usb_device *udev;
-
-        /*
-         * Store a copy of the usb_device pointer locally.
-         * This is because device_release_driver initiates
-         * ar9170_usb_disconnect, which in turn frees our
-         * driver context (aru).
-         */
-        udev = aru->udev;
-
-        complete(&aru->firmware_loading_complete);
-
-        /* unbind anything failed */
-        if (parent)
-                device_lock(parent);
-
-        device_release_driver(&udev->dev);
-        if (parent)
-                device_unlock(parent);
-
-        usb_put_dev(udev);
-}
-
-static void ar9170_usb_firmware_finish(const struct firmware *fw, void *context)
-{
-        struct ar9170_usb *aru = context;
-        int err;
-
-        aru->firmware = fw;
-
-        if (!fw) {
-                dev_err(&aru->udev->dev, "firmware file not found.\n");
-                goto err_freefw;
-        }
-
-        err = ar9170_usb_init_device(aru);
-        if (err)
-                goto err_freefw;
-
-        err = ar9170_usb_open(&aru->common);
-        if (err)
-                goto err_unrx;
-
-        err = ar9170_register(&aru->common, &aru->udev->dev);
-
-        ar9170_usb_stop(&aru->common);
-        if (err)
-                goto err_unrx;
-
-        complete(&aru->firmware_loading_complete);
-        usb_put_dev(aru->udev);
-        return;
-
- err_unrx:
-        ar9170_usb_cancel_urbs(aru);
-
- err_freefw:
-        ar9170_usb_firmware_failed(aru);
-}
-
-static void ar9170_usb_firmware_inits(const struct firmware *fw,
-                                      void *context)
-{
-        struct ar9170_usb *aru = context;
-        int err;
-
-        if (!fw) {
-                dev_err(&aru->udev->dev, "file with init values not found.\n");
-                ar9170_usb_firmware_failed(aru);
-                return;
-        }
-
-        aru->init_values = fw;
-
-        /* ok so we have the init values -- get code for two-stage */
-
-        err = request_firmware_nowait(THIS_MODULE, 1, "ar9170-2.fw",
-                                      &aru->udev->dev, GFP_KERNEL, aru,
-                                      ar9170_usb_firmware_finish);
-        if (err)
-                ar9170_usb_firmware_failed(aru);
-}
-
-static void ar9170_usb_firmware_step2(const struct firmware *fw, void *context)
-{
-        struct ar9170_usb *aru = context;
-        int err;
-
-        if (fw) {
-                ar9170_usb_firmware_finish(fw, context);
-                return;
-        }
-
-        if (aru->req_one_stage_fw) {
-                dev_err(&aru->udev->dev, "ar9170.fw firmware file "
-                        "not found and is required for this device\n");
-                ar9170_usb_firmware_failed(aru);
-                return;
-        }
-
-        dev_err(&aru->udev->dev, "ar9170.fw firmware file "
-                "not found, trying old firmware...\n");
-
-        err = request_firmware_nowait(THIS_MODULE, 1, "ar9170-1.fw",
-                                      &aru->udev->dev, GFP_KERNEL, aru,
-                                      ar9170_usb_firmware_inits);
-        if (err)
-                ar9170_usb_firmware_failed(aru);
-}
-
-static bool ar9170_requires_one_stage(const struct usb_device_id *id)
-{
-        if (!id->driver_info)
-                return false;
-        if (id->driver_info == AR9170_REQ_FW1_ONLY)
-                return true;
-        return false;
-}
-
-static int ar9170_usb_probe(struct usb_interface *intf,
-                        const struct usb_device_id *id)
-{
-        struct ar9170_usb *aru;
-        struct ar9170 *ar;
-        struct usb_device *udev;
-        int err;
-
-        aru = ar9170_alloc(sizeof(*aru));
-        if (IS_ERR(aru)) {
-                err = PTR_ERR(aru);
-                goto out;
-        }
-
-        udev = interface_to_usbdev(intf);
-        usb_get_dev(udev);
-        aru->udev = udev;
-        aru->intf = intf;
-        ar = &aru->common;
-
-        aru->req_one_stage_fw = ar9170_requires_one_stage(id);
-
-        usb_set_intfdata(intf, aru);
-        SET_IEEE80211_DEV(ar->hw, &intf->dev);
-
-        init_usb_anchor(&aru->rx_submitted);
-        init_usb_anchor(&aru->tx_pending);
-        init_usb_anchor(&aru->tx_submitted);
-        init_completion(&aru->cmd_wait);
-        init_completion(&aru->firmware_loading_complete);
-        spin_lock_init(&aru->tx_urb_lock);
-
-        aru->tx_pending_urbs = 0;
-        atomic_set(&aru->tx_submitted_urbs, 0);
-
-        aru->common.stop = ar9170_usb_stop;
-        aru->common.flush = ar9170_usb_flush;
-        aru->common.open = ar9170_usb_open;
-        aru->common.tx = ar9170_usb_tx;
-        aru->common.exec_cmd = ar9170_usb_exec_cmd;
-        aru->common.callback_cmd = ar9170_usb_callback_cmd;
-
-#ifdef CONFIG_PM
-        udev->reset_resume = 1;
-#endif /* CONFIG_PM */
-        err = ar9170_usb_reset(aru);
-        if (err)
-                goto err_freehw;
-
-        usb_get_dev(aru->udev);
-        return request_firmware_nowait(THIS_MODULE, 1, "ar9170.fw",
-                                       &aru->udev->dev, GFP_KERNEL, aru,
-                                       ar9170_usb_firmware_step2);
-err_freehw:
-        usb_set_intfdata(intf, NULL);
-        usb_put_dev(udev);
-        ieee80211_free_hw(ar->hw);
-out:
-        return err;
-}
-
-static void ar9170_usb_disconnect(struct usb_interface *intf)
-{
-        struct ar9170_usb *aru = usb_get_intfdata(intf);
-
-        if (!aru)
-                return;
-
-        aru->common.state = AR9170_IDLE;
-
-        wait_for_completion(&aru->firmware_loading_complete);
-
-        ar9170_unregister(&aru->common);
-        ar9170_usb_cancel_urbs(aru);
-
-        usb_put_dev(aru->udev);
-        usb_set_intfdata(intf, NULL);
-        ieee80211_free_hw(aru->common.hw);
-
-        release_firmware(aru->init_values);
-        release_firmware(aru->firmware);
-}
-
-#ifdef CONFIG_PM
-static int ar9170_suspend(struct usb_interface *intf,
-                          pm_message_t  message)
-{
-        struct ar9170_usb *aru = usb_get_intfdata(intf);
-
-        if (!aru)
-                return -ENODEV;
-
-        aru->common.state = AR9170_IDLE;
-        ar9170_usb_cancel_urbs(aru);
-
-        return 0;
-}
-
-static int ar9170_resume(struct usb_interface *intf)
-{
-        struct ar9170_usb *aru = usb_get_intfdata(intf);
-        int err;
-
-        if (!aru)
-                return -ENODEV;
-
-        usb_unpoison_anchored_urbs(&aru->rx_submitted);
-        usb_unpoison_anchored_urbs(&aru->tx_submitted);
-
-        err = ar9170_usb_init_device(aru);
-        if (err)
-                goto err_unrx;
-
-        err = ar9170_usb_open(&aru->common);
-        if (err)
-                goto err_unrx;
-
-        return 0;
-
-err_unrx:
-        aru->common.state = AR9170_IDLE;
-        ar9170_usb_cancel_urbs(aru);
-
-        return err;
-}
-#endif /* CONFIG_PM */
-
-static struct usb_driver ar9170_driver = {
-        .name = "ar9170usb",
-        .probe = ar9170_usb_probe,
-        .disconnect = ar9170_usb_disconnect,
-        .id_table = ar9170_usb_ids,
-        .soft_unbind = 1,
-#ifdef CONFIG_PM
-        .suspend = ar9170_suspend,
-        .resume = ar9170_resume,
-        .reset_resume = ar9170_resume,
-#endif /* CONFIG_PM */
-};
-
-static int __init ar9170_init(void)
-{
-        return usb_register(&ar9170_driver);
-}
-
-static void __exit ar9170_exit(void)
-{
-        usb_deregister(&ar9170_driver);
-}
-
-module_init(ar9170_init);
-module_exit(ar9170_exit);
diff --git a/drivers/net/wireless/ath/ar9170/usb.h b/drivers/net/wireless/ath/ar9170/usb.h
deleted file mode 100644
index 919b06046eb3..000000000000
--- a/drivers/net/wireless/ath/ar9170/usb.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Atheros AR9170 USB driver
- *
- * Driver specific definitions
- *
- * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
- * Copyright 2009, Christian Lamparter <chunkeey@web.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, see
- * http://www.gnu.org/licenses/.
- *
- * This file incorporates work covered by the following copyright and
- * permission notice:
- *    Copyright (c) 2007-2008 Atheros Communications, Inc.
- *
- *    Permission to use, copy, modify, and/or distribute this software for any
- *    purpose with or without fee is hereby granted, provided that the above
- *    copyright notice and this permission notice appear in all copies.
- *
- *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#ifndef __USB_H
-#define __USB_H
-
-#include <linux/usb.h>
-#include <linux/completion.h>
-#include <linux/spinlock.h>
-#include <linux/leds.h>
-#include <net/cfg80211.h>
-#include <net/mac80211.h>
-#include <linux/firmware.h>
-#include "eeprom.h"
-#include "hw.h"
-#include "ar9170.h"
-
-#define AR9170_NUM_RX_URBS                      16
-#define AR9170_NUM_TX_URBS                      8
-
-struct firmware;
-
-struct ar9170_usb {
-        struct ar9170 common;
-        struct usb_device *udev;
-        struct usb_interface *intf;
-
-        struct usb_anchor rx_submitted;
-        struct usb_anchor tx_pending;
-        struct usb_anchor tx_submitted;
-
-        bool req_one_stage_fw;
-
-        spinlock_t tx_urb_lock;
-        atomic_t tx_submitted_urbs;
-        unsigned int tx_pending_urbs;
-
-        struct completion cmd_wait;
-        struct completion firmware_loading_complete;
-        int readlen;
-        u8 *readbuf;
-
-        const struct firmware *init_values;
-        const struct firmware *firmware;
-};
-
-#endif /* __USB_H */
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index d32f2828b098..7cf4317a2a84 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -19,6 +19,7 @@
 
 #include <linux/skbuff.h>
 #include <linux/if_ether.h>
+#include <linux/spinlock.h>
 #include <net/mac80211.h>
 
 /*
@@ -35,7 +36,6 @@ static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 
 struct ath_ani {
         bool caldone;
-        int16_t noise_floor;
         unsigned int longcal_timer;
         unsigned int shortcal_timer;
         unsigned int resetcal_timer;
@@ -43,6 +43,13 @@ struct ath_ani {
         struct timer_list timer;
 };
 
+struct ath_cycle_counters {
+        u32 cycles;
+        u32 rx_busy;
+        u32 rx_frame;
+        u32 tx_frame;
+};
+
 enum ath_device_state {
         ATH_HW_UNAVAILABLE,
         ATH_HW_INITIALIZED,
@@ -71,31 +78,52 @@ struct ath_regulatory {
         struct reg_dmn_pair_mapping *regpair;
 };
 
+enum ath_crypt_caps {
+        ATH_CRYPT_CAP_CIPHER_AESCCM             = BIT(0),
+        ATH_CRYPT_CAP_MIC_COMBINED              = BIT(1),
+};
+
+struct ath_keyval {
+        u8 kv_type;
+        u8 kv_pad;
+        u16 kv_len;
+        u8 kv_val[16]; /* TK */
+        u8 kv_mic[8]; /* Michael MIC key */
+        u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
+                         * supports both MIC keys in the same key cache entry;
+                         * in that case, kv_mic is the RX key) */
+};
+
+enum ath_cipher {
+        ATH_CIPHER_WEP = 0,
+        ATH_CIPHER_AES_OCB = 1,
+        ATH_CIPHER_AES_CCM = 2,
+        ATH_CIPHER_CKIP = 3,
+        ATH_CIPHER_TKIP = 4,
+        ATH_CIPHER_CLR = 5,
+        ATH_CIPHER_MIC = 127
+};
+
 /**
  * struct ath_ops - Register read/write operations
  *
  * @read: Register read
+ * @multi_read: Multiple register read
  * @write: Register write
  * @enable_write_buffer: Enable multiple register writes
- * @disable_write_buffer: Disable multiple register writes
- * @write_flush: Flush buffered register writes
+ * @write_flush: flush buffered register writes and disable buffering
  */
 struct ath_ops {
         unsigned int (*read)(void *, u32 reg_offset);
+        void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
         void (*write)(void *, u32 val, u32 reg_offset);
         void (*enable_write_buffer)(void *);
-        void (*disable_write_buffer)(void *);
         void (*write_flush) (void *);
+        u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
 };
 
 struct ath_common;
-
-struct ath_bus_ops {
-        enum ath_bus_type ath_bus_type;
-        void (*read_cachesize)(struct ath_common *common, int *csz);
-        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
-        void (*bt_coex_prep)(struct ath_common *common);
-};
+struct ath_bus_ops;
 
 struct ath_common {
         void *ah;
@@ -119,11 +147,20 @@ struct ath_common {
 
         u32 keymax;
         DECLARE_BITMAP(keymap, ATH_KEYMAX);
-        u8 splitmic;
+        DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
+        enum ath_crypt_caps crypt_caps;
+
+        unsigned int clockrate;
+
+        spinlock_t cc_lock;
+        struct ath_cycle_counters cc_ani;
+        struct ath_cycle_counters cc_survey;
 
         struct ath_regulatory regulatory;
         const struct ath_ops *ops;
         const struct ath_bus_ops *bus_ops;
+
+        bool btcoex_enabled;
 };
 
 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
@@ -131,5 +168,121 @@ struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
                                 gfp_t gfp_mask);
 
 void ath_hw_setbssidmask(struct ath_common *common);
+void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
+int ath_key_config(struct ath_common *common,
+                          struct ieee80211_vif *vif,
+                          struct ieee80211_sta *sta,
+                          struct ieee80211_key_conf *key);
+bool ath_hw_keyreset(struct ath_common *common, u16 entry);
+void ath_hw_cycle_counters_update(struct ath_common *common);
+int32_t ath_hw_get_listen_time(struct ath_common *common);
+
+extern __attribute__ ((format (printf, 3, 4))) int
+ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
+
+#define ath_emerg(common, fmt, ...)                             \
+        ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
+#define ath_alert(common, fmt, ...)                             \
+        ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
+#define ath_crit(common, fmt, ...)                              \
+        ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
+#define ath_err(common, fmt, ...)                               \
+        ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
+#define ath_warn(common, fmt, ...)                              \
+        ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
+#define ath_notice(common, fmt, ...)                            \
+        ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
+#define ath_info(common, fmt, ...)                              \
+        ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
+
+/**
+ * enum ath_debug_level - atheros wireless debug level
+ *
+ * @ATH_DBG_RESET: reset processing
+ * @ATH_DBG_QUEUE: hardware queue management
+ * @ATH_DBG_EEPROM: eeprom processing
+ * @ATH_DBG_CALIBRATE: periodic calibration
+ * @ATH_DBG_INTERRUPT: interrupt processing
+ * @ATH_DBG_REGULATORY: regulatory processing
+ * @ATH_DBG_ANI: adaptive noise immunitive processing
+ * @ATH_DBG_XMIT: basic xmit operation
+ * @ATH_DBG_BEACON: beacon handling
+ * @ATH_DBG_CONFIG: configuration of the hardware
+ * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
+ * @ATH_DBG_PS: power save processing
+ * @ATH_DBG_HWTIMER: hardware timer handling
+ * @ATH_DBG_BTCOEX: bluetooth coexistance
+ * @ATH_DBG_BSTUCK: stuck beacons
+ * @ATH_DBG_ANY: enable all debugging
+ *
+ * The debug level is used to control the amount and type of debugging output
+ * we want to see. Each driver has its own method for enabling debugging and
+ * modifying debug level states -- but this is typically done through a
+ * module parameter 'debug' along with a respective 'debug' debugfs file
+ * entry.
+ */
+enum ATH_DEBUG {
+        ATH_DBG_RESET           = 0x00000001,
+        ATH_DBG_QUEUE           = 0x00000002,
+        ATH_DBG_EEPROM          = 0x00000004,
+        ATH_DBG_CALIBRATE       = 0x00000008,
+        ATH_DBG_INTERRUPT       = 0x00000010,
+        ATH_DBG_REGULATORY      = 0x00000020,
+        ATH_DBG_ANI             = 0x00000040,
+        ATH_DBG_XMIT            = 0x00000080,
+        ATH_DBG_BEACON          = 0x00000100,
+        ATH_DBG_CONFIG          = 0x00000200,
+        ATH_DBG_FATAL           = 0x00000400,
+        ATH_DBG_PS              = 0x00000800,
+        ATH_DBG_HWTIMER         = 0x00001000,
+        ATH_DBG_BTCOEX          = 0x00002000,
+        ATH_DBG_WMI             = 0x00004000,
+        ATH_DBG_BSTUCK          = 0x00008000,
+        ATH_DBG_ANY             = 0xffffffff
+};
+
+#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
+
+#ifdef CONFIG_ATH_DEBUG
+
+#define ath_dbg(common, dbg_mask, fmt, ...)                     \
+({                                                              \
+        int rtn;                                                \
+        if ((common)->debug_mask & dbg_mask)                    \
+                rtn = ath_printk(KERN_DEBUG, common, fmt,       \
+                                 ##__VA_ARGS__);                \
+        else                                                    \
+                rtn = 0;                                        \
+                                                                \
+        rtn;                                                    \
+})
+#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
+#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
+
+#else
+
+static inline  __attribute__ ((format (printf, 3, 4))) int
+ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
+        const char *fmt, ...)
+{
+        return 0;
+}
+#define ATH_DBG_WARN(foo, arg...) do {} while (0)
+#define ATH_DBG_WARN_ON_ONCE(foo) ({                            \
+        int __ret_warn_once = !!(foo);                          \
+        unlikely(__ret_warn_once);                              \
+})
+
+#endif /* CONFIG_ATH_DEBUG */
+
+/** Returns string describing opmode, or NULL if unknown mode. */
+#ifdef CONFIG_ATH_DEBUG
+const char *ath_opmode_to_string(enum nl80211_iftype opmode);
+#else
+static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
+{
+        return "UNKNOWN";
+}
+#endif
 
 #endif /* ATH_H */
diff --git a/drivers/net/wireless/ath/ath5k/Kconfig b/drivers/net/wireless/ath/ath5k/Kconfig
index eb83b7b4d0e3..e18a9aa7b6ca 100644
--- a/drivers/net/wireless/ath/ath5k/Kconfig
+++ b/drivers/net/wireless/ath/ath5k/Kconfig
@@ -1,9 +1,12 @@
 config ATH5K
         tristate "Atheros 5xxx wireless cards support"
-        depends on PCI && MAC80211
+        depends on (PCI || ATHEROS_AR231X) && MAC80211
         select MAC80211_LEDS
         select LEDS_CLASS
         select NEW_LEDS
+        select AVERAGE
+        select ATH5K_AHB if (ATHEROS_AR231X && !PCI)
+        select ATH5K_PCI if (!ATHEROS_AR231X && PCI)
         ---help---
           This module adds support for wireless adapters based on
           Atheros 5xxx chipset.
@@ -37,3 +40,27 @@ config ATH5K_DEBUG
 
           modprobe ath5k debug=0x00000400
 
+config ATH5K_TRACER
+        bool "Atheros 5xxx tracer"
+        depends on ATH5K
+        depends on EVENT_TRACING
+        ---help---
+          Say Y here to enable tracepoints for the ath5k driver
+          using the kernel tracing infrastructure.  Select this
+          option if you are interested in debugging the driver.
+
+          If unsure, say N.
+
+config ATH5K_AHB
+        bool "Atheros 5xxx AHB bus support"
+        depends on (ATHEROS_AR231X && !PCI)
+        ---help---
+          This adds support for WiSoC type chipsets of the 5xxx Atheros
+          family.
+
+config ATH5K_PCI
+        bool "Atheros 5xxx PCI bus support"
+        depends on (!ATHEROS_AR231X && PCI)
+        ---help---
+          This adds support for PCI type chipsets of the 5xxx Atheros
+          family.
diff --git a/drivers/net/wireless/ath/ath5k/Makefile b/drivers/net/wireless/ath/ath5k/Makefile
index 2242a140e4fe..f60b3899afc4 100644
--- a/drivers/net/wireless/ath/ath5k/Makefile
+++ b/drivers/net/wireless/ath/ath5k/Makefile
@@ -14,5 +14,8 @@ ath5k-y				+= led.o
 ath5k-y                         += rfkill.o
 ath5k-y                         += ani.o
 ath5k-y                         += sysfs.o
+ath5k-y                         += mac80211-ops.o
 ath5k-$(CONFIG_ATH5K_DEBUG)     += debug.o
+ath5k-$(CONFIG_ATH5K_AHB)       += ahb.o
+ath5k-$(CONFIG_ATH5K_PCI)       += pci.o
 obj-$(CONFIG_ATH5K)             += ath5k.o
diff --git a/drivers/net/wireless/ath/ath5k/ahb.c b/drivers/net/wireless/ath/ath5k/ahb.c
new file mode 100644
index 000000000000..ea9982781559
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/ahb.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/platform_device.h>
+#include <linux/etherdevice.h>
+#include <ar231x_platform.h>
+#include "ath5k.h"
+#include "debug.h"
+#include "base.h"
+#include "reg.h"
+#include "debug.h"
+
+/* return bus cachesize in 4B word units */
+static void ath5k_ahb_read_cachesize(struct ath_common *common, int *csz)
+{
+        *csz = L1_CACHE_BYTES >> 2;
+}
+
+static bool
+ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
+{
+        struct ath5k_softc *sc = common->priv;
+        struct platform_device *pdev = to_platform_device(sc->dev);
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        u16 *eeprom, *eeprom_end;
+
+
+
+        bcfg = pdev->dev.platform_data;
+        eeprom = (u16 *) bcfg->radio;
+        eeprom_end = ((void *) bcfg->config) + BOARD_CONFIG_BUFSZ;
+
+        eeprom += off;
+        if (eeprom > eeprom_end)
+                return false;
+
+        *data = *eeprom;
+        return true;
+}
+
+int ath5k_hw_read_srev(struct ath5k_hw *ah)
+{
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct platform_device *pdev = to_platform_device(sc->dev);
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        ah->ah_mac_srev = bcfg->devid;
+        return 0;
+}
+
+static int ath5k_ahb_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
+{
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct platform_device *pdev = to_platform_device(sc->dev);
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        u8 *cfg_mac;
+
+        if (to_platform_device(sc->dev)->id == 0)
+                cfg_mac = bcfg->config->wlan0_mac;
+        else
+                cfg_mac = bcfg->config->wlan1_mac;
+
+        memcpy(mac, cfg_mac, ETH_ALEN);
+        return 0;
+}
+
+static const struct ath_bus_ops ath_ahb_bus_ops = {
+        .ath_bus_type = ATH_AHB,
+        .read_cachesize = ath5k_ahb_read_cachesize,
+        .eeprom_read = ath5k_ahb_eeprom_read,
+        .eeprom_read_mac = ath5k_ahb_eeprom_read_mac,
+};
+
+/*Initialization*/
+static int ath_ahb_probe(struct platform_device *pdev)
+{
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        struct ath5k_softc *sc;
+        struct ieee80211_hw *hw;
+        struct resource *res;
+        void __iomem *mem;
+        int irq;
+        int ret = 0;
+        u32 reg;
+
+        if (!pdev->dev.platform_data) {
+                dev_err(&pdev->dev, "no platform data specified\n");
+                ret = -EINVAL;
+                goto err_out;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no memory resource found\n");
+                ret = -ENXIO;
+                goto err_out;
+        }
+
+        mem = ioremap_nocache(res->start, resource_size(res));
+        if (mem == NULL) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err_out;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no IRQ resource found\n");
+                ret = -ENXIO;
+                goto err_out;
+        }
+
+        irq = res->start;
+
+        hw = ieee80211_alloc_hw(sizeof(struct ath5k_softc), &ath5k_hw_ops);
+        if (hw == NULL) {
+                dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
+                ret = -ENOMEM;
+                goto err_out;
+        }
+
+        sc = hw->priv;
+        sc->hw = hw;
+        sc->dev = &pdev->dev;
+        sc->iobase = mem;
+        sc->irq = irq;
+        sc->devid = bcfg->devid;
+
+        if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
+                /* Enable WMAC AHB arbitration */
+                reg = __raw_readl((void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+                reg |= AR5K_AR2315_AHB_ARB_CTL_WLAN;
+                __raw_writel(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+
+                /* Enable global WMAC swapping */
+                reg = __raw_readl((void __iomem *) AR5K_AR2315_BYTESWAP);
+                reg |= AR5K_AR2315_BYTESWAP_WMAC;
+                __raw_writel(reg, (void __iomem *) AR5K_AR2315_BYTESWAP);
+        } else {
+                /* Enable WMAC DMA access (assuming 5312 or 231x*/
+                /* TODO: check other platforms */
+                reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
+                if (to_platform_device(sc->dev)->id == 0)
+                        reg |= AR5K_AR5312_ENABLE_WLAN0;
+                else
+                        reg |= AR5K_AR5312_ENABLE_WLAN1;
+                __raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE);
+
+                /*
+                 * On a dual-band AR5312, the multiband radio is only
+                 * used as pass-through. Disable 2 GHz support in the
+                 * driver for it
+                 */
+                if (to_platform_device(sc->dev)->id == 0 &&
+                    (bcfg->config->flags & (BD_WLAN0|BD_WLAN1)) ==
+                     (BD_WLAN1|BD_WLAN0))
+                        __set_bit(ATH_STAT_2G_DISABLED, sc->status);
+        }
+
+        ret = ath5k_init_softc(sc, &ath_ahb_bus_ops);
+        if (ret != 0) {
+                dev_err(&pdev->dev, "failed to attach device, err=%d\n", ret);
+                ret = -ENODEV;
+                goto err_free_hw;
+        }
+
+        platform_set_drvdata(pdev, hw);
+
+        return 0;
+
+ err_free_hw:
+        ieee80211_free_hw(hw);
+        platform_set_drvdata(pdev, NULL);
+ err_out:
+        return ret;
+}
+
+static int ath_ahb_remove(struct platform_device *pdev)
+{
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        struct ieee80211_hw *hw = platform_get_drvdata(pdev);
+        struct ath5k_softc *sc;
+        u32 reg;
+
+        if (!hw)
+                return 0;
+
+        sc = hw->priv;
+
+        if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
+                /* Disable WMAC AHB arbitration */
+                reg = __raw_readl((void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+                reg &= ~AR5K_AR2315_AHB_ARB_CTL_WLAN;
+                __raw_writel(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+        } else {
+                /*Stop DMA access */
+                reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
+                if (to_platform_device(sc->dev)->id == 0)
+                        reg &= ~AR5K_AR5312_ENABLE_WLAN0;
+                else
+                        reg &= ~AR5K_AR5312_ENABLE_WLAN1;
+                __raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE);
+        }
+
+        ath5k_deinit_softc(sc);
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_driver ath_ahb_driver = {
+        .probe      = ath_ahb_probe,
+        .remove     = ath_ahb_remove,
+        .driver         = {
+                .name   = "ar231x-wmac",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init
+ath5k_ahb_init(void)
+{
+        return platform_driver_register(&ath_ahb_driver);
+}
+
+static void __exit
+ath5k_ahb_exit(void)
+{
+        platform_driver_unregister(&ath_ahb_driver);
+}
+
+module_init(ath5k_ahb_init);
+module_exit(ath5k_ahb_exit);
diff --git a/drivers/net/wireless/ath/ath5k/ani.c b/drivers/net/wireless/ath/ath5k/ani.c
index 26dbe65fedb0..f915f404302d 100644
--- a/drivers/net/wireless/ath/ath5k/ani.c
+++ b/drivers/net/wireless/ath/ath5k/ani.c
@@ -58,20 +58,20 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
 {
         /* TODO:
          * ANI documents suggest the following five levels to use, but the HAL
-         * and ath9k use only use the last two levels, making this
+         * and ath9k use only the last two levels, making this
          * essentially an on/off option. There *may* be a reason for this (???),
          * so i stick with the HAL version for now...
          */
 #if 0
-        const s8 hi[] = { -18, -18, -16, -14, -12 };
-        const s8 lo[] = { -52, -56, -60, -64, -70 };
-        const s8 sz[] = { -34, -41, -48, -55, -62 };
-        const s8 fr[] = { -70, -72, -75, -78, -80 };
+        static const s8 lo[] = { -52, -56, -60, -64, -70 };
+        static const s8 hi[] = { -18, -18, -16, -14, -12 };
+        static const s8 sz[] = { -34, -41, -48, -55, -62 };
+        static const s8 fr[] = { -70, -72, -75, -78, -80 };
 #else
-        const s8 sz[] = { -55, -62 };
-        const s8 lo[] = { -64, -70 };
-        const s8 hi[] = { -14, -12 };
-        const s8 fr[] = { -78, -80 };
+        static const s8 lo[] = { -64, -70 };
+        static const s8 hi[] = { -14, -12 };
+        static const s8 sz[] = { -55, -62 };
+        static const s8 fr[] = { -78, -80 };
 #endif
         if (level < 0 || level >= ARRAY_SIZE(sz)) {
                 ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range",
@@ -102,7 +102,7 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
 void
 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
 {
-        const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
+        static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
 
         if (level < 0 || level >= ARRAY_SIZE(val) ||
             level > ah->ah_sc->ani_state.max_spur_level) {
@@ -127,7 +127,7 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
 void
 ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
 {
-        const int val[] = { 0, 4, 8 };
+        static const int val[] = { 0, 4, 8 };
 
         if (level < 0 || level >= ARRAY_SIZE(val)) {
                 ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level);
@@ -151,12 +151,12 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
 void
 ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
 {
-        const int m1l[] = { 127, 50 };
-        const int m2l[] = { 127, 40 };
-        const int m1[] = { 127, 0x4d };
-        const int m2[] = { 127, 0x40 };
-        const int m2cnt[] = { 31, 16 };
-        const int m2lcnt[] = { 63, 48 };
+        static const int m1l[] = { 127, 50 };
+        static const int m2l[] = { 127, 40 };
+        static const int m1[] = { 127, 0x4d };
+        static const int m2[] = { 127, 0x40 };
+        static const int m2cnt[] = { 31, 16 };
+        static const int m2lcnt[] = { 63, 48 };
 
         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
                                 AR5K_PHY_WEAK_OFDM_LOW_THR_M1, m1l[on]);
@@ -192,7 +192,7 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
 void
 ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
 {
-        const int val[] = { 8, 6 };
+        static const int val[] = { 8, 6 };
         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
                                 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
         ah->ah_sc->ani_state.cck_weak_sig = on;
@@ -216,7 +216,7 @@ static void
 ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
                          bool ofdm_trigger)
 {
-        int rssi = ah->ah_beacon_rssi_avg.avg;
+        int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
 
         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)",
                 ofdm_trigger ? "ODFM" : "CCK");
@@ -301,7 +301,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
 static void
 ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
 {
-        int rssi = ah->ah_beacon_rssi_avg.avg;
+        int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
 
         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity");
 
@@ -355,41 +355,28 @@ ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
 
 
 /**
- * ath5k_hw_ani_get_listen_time() - Calculate time spent listening
+ * ath5k_hw_ani_get_listen_time() - Update counters and return listening time
  *
  * Return an approximation of the time spent "listening" in milliseconds (ms)
- * since the last call of this function by deducting the cycles spent
- * transmitting and receiving from the total cycle count.
- * Save profile count values for debugging/statistics and because we might want
- * to use them later.
- *
- * We assume no one else clears these registers!
+ * since the last call of this function.
+ * Save a snapshot of the counter values for debugging/statistics.
  */
 static int
 ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
 {
+        struct ath_common *common = ath5k_hw_common(ah);
         int listen;
 
-        /* freeze */
-        ath5k_hw_reg_write(ah, AR5K_MIBC_FMC, AR5K_MIBC);
-        /* read */
-        as->pfc_cycles = ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE);
-        as->pfc_busy = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR);
-        as->pfc_tx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX);
-        as->pfc_rx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX);
-        /* clear */
-        ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
-        ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
-        ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
-        ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
-        /* un-freeze */
-        ath5k_hw_reg_write(ah, 0, AR5K_MIBC);
-
-        /* TODO: where does 44000 come from? (11g clock rate?) */
-        listen = (as->pfc_cycles - as->pfc_rx - as->pfc_tx) / 44000;
-
-        if (as->pfc_cycles == 0 || listen < 0)
-                return 0;
+        spin_lock_bh(&common->cc_lock);
+
+        ath_hw_cycle_counters_update(common);
+        memcpy(&as->last_cc, &common->cc_ani, sizeof(as->last_cc));
+
+        /* clears common->cc_ani */
+        listen = ath_hw_get_listen_time(common);
+
+        spin_unlock_bh(&common->cc_lock);
+
         return listen;
 }
 
@@ -552,9 +539,9 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
         if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO)
                 return;
 
-        /* if one of the errors triggered, we can get a superfluous second
-         * interrupt, even though we have already reset the register. the
-         * function detects that so we can return early */
+        /* If one of the errors triggered, we can get a superfluous second
+         * interrupt, even though we have already reset the register. The
+         * function detects that so we can return early. */
         if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0)
                 return;
 
diff --git a/drivers/net/wireless/ath/ath5k/ani.h b/drivers/net/wireless/ath/ath5k/ani.h
index 55cf26d8522c..034015397093 100644
--- a/drivers/net/wireless/ath/ath5k/ani.h
+++ b/drivers/net/wireless/ath/ath5k/ani.h
@@ -27,7 +27,7 @@
 #define ATH5K_ANI_RSSI_THR_HIGH         40
 #define ATH5K_ANI_RSSI_THR_LOW          7
 
-/* maximum availabe levels */
+/* maximum available levels */
 #define ATH5K_ANI_MAX_FIRSTEP_LVL       2
 #define ATH5K_ANI_MAX_NOISE_IMM_LVL     1
 
@@ -75,10 +75,7 @@ struct ath5k_ani_state {
         unsigned int            cck_errors;
 
         /* debug/statistics only: numbers from last ANI calibration */
-        unsigned int            pfc_tx;
-        unsigned int            pfc_rx;
-        unsigned int            pfc_busy;
-        unsigned int            pfc_cycles;
+        struct ath_cycle_counters last_cc;
         unsigned int            last_listen;
         unsigned int            last_ofdm_errors;
         unsigned int            last_cck_errors;
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index ea6362a8988d..bb50700436fe 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -25,6 +25,7 @@
 
 #include <linux/io.h>
 #include <linux/types.h>
+#include <linux/average.h>
 #include <net/mac80211.h>
 
 /* RX/TX descriptor hw structs
@@ -153,19 +154,6 @@
                 udelay(1);                                              \
 } while (0)
 
-/* Register dumps are done per operation mode */
-#define AR5K_INI_RFGAIN_5GHZ            0
-#define AR5K_INI_RFGAIN_2GHZ            1
-
-/* TODO: Clean this up */
-#define AR5K_INI_VAL_11A                0
-#define AR5K_INI_VAL_11A_TURBO          1
-#define AR5K_INI_VAL_11B                2
-#define AR5K_INI_VAL_11G                3
-#define AR5K_INI_VAL_11G_TURBO          4
-#define AR5K_INI_VAL_XR                 0
-#define AR5K_INI_VAL_MAX                5
-
 /*
  * Some tuneable values (these should be changeable by the user)
  * TODO: Make use of them and add more options OR use debug/configfs
@@ -175,7 +163,7 @@
 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
 #define AR5K_TUNE_RADAR_ALERT                   false
 #define AR5K_TUNE_MIN_TX_FIFO_THRES             1
-#define AR5K_TUNE_MAX_TX_FIFO_THRES             ((IEEE80211_MAX_LEN / 64) + 1)
+#define AR5K_TUNE_MAX_TX_FIFO_THRES     ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
 #define AR5K_TUNE_REGISTER_TIMEOUT              20000
 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
  * be the max value. */
@@ -206,6 +194,8 @@
 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI     1000    /* 1 sec */
 #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF      60000   /* 60 sec */
 
+#define ATH5K_TX_COMPLETE_POLL_INT              3000    /* 3 sec */
+
 #define AR5K_INIT_CARR_SENSE_EN                 1
 
 /*Swap RX/TX Descriptor for big endian archs*/
@@ -219,45 +209,61 @@
 
 /* Initial values */
 #define AR5K_INIT_CYCRSSI_THR1                  2
-#define AR5K_INIT_TX_LATENCY                    502
-#define AR5K_INIT_USEC                          39
-#define AR5K_INIT_USEC_TURBO                    79
-#define AR5K_INIT_USEC_32                       31
-#define AR5K_INIT_SLOT_TIME                     396
-#define AR5K_INIT_SLOT_TIME_TURBO               480
-#define AR5K_INIT_ACK_CTS_TIMEOUT               1024
-#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO         0x08000800
-#define AR5K_INIT_PROG_IFS                      920
-#define AR5K_INIT_PROG_IFS_TURBO                960
-#define AR5K_INIT_EIFS                          3440
-#define AR5K_INIT_EIFS_TURBO                    6880
-#define AR5K_INIT_SIFS                          560
-#define AR5K_INIT_SIFS_TURBO                    480
-#define AR5K_INIT_SH_RETRY                      10
-#define AR5K_INIT_LG_RETRY                      AR5K_INIT_SH_RETRY
-#define AR5K_INIT_SSH_RETRY                     32
-#define AR5K_INIT_SLG_RETRY                     AR5K_INIT_SSH_RETRY
-#define AR5K_INIT_TX_RETRY                      10
-
-#define AR5K_INIT_TRANSMIT_LATENCY              (                       \
-        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
-        (AR5K_INIT_USEC)                                                \
-)
-#define AR5K_INIT_TRANSMIT_LATENCY_TURBO        (                       \
-        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
-        (AR5K_INIT_USEC_TURBO)                                          \
-)
-#define AR5K_INIT_PROTO_TIME_CNTRL              (                       \
-        (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) |      \
-        (AR5K_INIT_PROG_IFS)                                            \
-)
-#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO        (                       \
-        (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
-        (AR5K_INIT_PROG_IFS_TURBO)                                      \
-)
 
-/* token to use for aifs, cwmin, cwmax in MadWiFi */
-#define AR5K_TXQ_USEDEFAULT     ((u32) -1)
+/* Tx retry limit defaults from standard */
+#define AR5K_INIT_RETRY_SHORT                   7
+#define AR5K_INIT_RETRY_LONG                    4
+
+/* Slot time */
+#define AR5K_INIT_SLOT_TIME_TURBO               6
+#define AR5K_INIT_SLOT_TIME_DEFAULT             9
+#define AR5K_INIT_SLOT_TIME_HALF_RATE           13
+#define AR5K_INIT_SLOT_TIME_QUARTER_RATE        21
+#define AR5K_INIT_SLOT_TIME_B                   20
+#define AR5K_SLOT_TIME_MAX                      0xffff
+
+/* SIFS */
+#define AR5K_INIT_SIFS_TURBO                    6
+#define AR5K_INIT_SIFS_DEFAULT_BG               10
+#define AR5K_INIT_SIFS_DEFAULT_A                16
+#define AR5K_INIT_SIFS_HALF_RATE                32
+#define AR5K_INIT_SIFS_QUARTER_RATE             64
+
+/* Used to calculate tx time for non 5/10/40MHz
+ * operation */
+/* It's preamble time + signal time (16 + 4) */
+#define AR5K_INIT_OFDM_PREAMPLE_TIME            20
+/* Preamble time for 40MHz (turbo) operation (min ?) */
+#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN        14
+#define AR5K_INIT_OFDM_SYMBOL_TIME              4
+#define AR5K_INIT_OFDM_PLCP_BITS                22
+
+/* Rx latency for 5 and 10MHz operation (max ?) */
+#define AR5K_INIT_RX_LAT_MAX                    63
+/* Tx latencies from initvals (5212 only but no problem
+ * because we only tweak them on 5212) */
+#define AR5K_INIT_TX_LAT_A                      54
+#define AR5K_INIT_TX_LAT_BG                     384
+/* Tx latency for 40MHz (turbo) operation (min ?) */
+#define AR5K_INIT_TX_LAT_MIN                    32
+/* Default Tx/Rx latencies (same for 5211)*/
+#define AR5K_INIT_TX_LATENCY_5210               54
+#define AR5K_INIT_RX_LATENCY_5210               29
+
+/* Tx frame to Tx data start delay */
+#define AR5K_INIT_TXF2TXD_START_DEFAULT         14
+#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ     12
+#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ      13
+
+/* We need to increase PHY switch and agc settling time
+ * on turbo mode */
+#define AR5K_SWITCH_SETTLING                    5760
+#define AR5K_SWITCH_SETTLING_TURBO              7168
+
+#define AR5K_AGC_SETTLING                       28
+/* 38 on 5210 but shouldn't matter */
+#define AR5K_AGC_SETTLING_TURBO                 37
+
 
 /* GENERIC CHIPSET DEFINITIONS */
 
@@ -303,12 +309,19 @@ struct ath5k_srev_name {
 #define AR5K_SREV_AR5311B       0x30 /* Spirit */
 #define AR5K_SREV_AR5211        0x40 /* Oahu */
 #define AR5K_SREV_AR5212        0x50 /* Venice */
+#define AR5K_SREV_AR5312_R2     0x52 /* AP31 */
 #define AR5K_SREV_AR5212_V4     0x54 /* ??? */
 #define AR5K_SREV_AR5213        0x55 /* ??? */
+#define AR5K_SREV_AR5312_R7     0x57 /* AP30 */
+#define AR5K_SREV_AR2313_R8     0x58 /* AP43 */
 #define AR5K_SREV_AR5213A       0x59 /* Hainan */
 #define AR5K_SREV_AR2413        0x78 /* Griffin lite */
 #define AR5K_SREV_AR2414        0x70 /* Griffin */
+#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
+#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
 #define AR5K_SREV_AR5424        0x90 /* Condor */
+#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
+#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
 #define AR5K_SREV_AR5413        0xa4 /* Eagle lite */
 #define AR5K_SREV_AR5414        0xa0 /* Eagle */
 #define AR5K_SREV_AR2415        0xb0 /* Talon */
@@ -343,15 +356,12 @@ struct ath5k_srev_name {
 #define AR5K_SREV_PHY_5413      0x61
 #define AR5K_SREV_PHY_2425      0x70
 
-/* IEEE defs */
-#define IEEE80211_MAX_LEN       2500
-
 /* TODO add support to mac80211 for vendor-specific rates and modes */
 
 /*
  * Some of this information is based on Documentation from:
  *
- * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
+ * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 
  *
  * Modulation for Atheros' eXtended Range - range enhancing extension that is
  * supposed to double the distance an Atheros client device can keep a
@@ -407,12 +417,10 @@ struct ath5k_srev_name {
 
 enum ath5k_driver_mode {
         AR5K_MODE_11A           =       0,
-        AR5K_MODE_11A_TURBO     =       1,
-        AR5K_MODE_11B           =       2,
-        AR5K_MODE_11G           =       3,
-        AR5K_MODE_11G_TURBO     =       4,
+        AR5K_MODE_11B           =       1,
+        AR5K_MODE_11G           =       2,
         AR5K_MODE_XR            =       0,
-        AR5K_MODE_MAX           =       5
+        AR5K_MODE_MAX           =       3
 };
 
 enum ath5k_ant_mode {
@@ -426,6 +434,12 @@ enum ath5k_ant_mode {
         AR5K_ANTMODE_MAX,
 };
 
+enum ath5k_bw_mode {
+        AR5K_BWMODE_DEFAULT     = 0,    /* 20MHz, default operation */
+        AR5K_BWMODE_5MHZ        = 1,    /* Quarter rate */
+        AR5K_BWMODE_10MHZ       = 2,    /* Half rate */
+        AR5K_BWMODE_40MHZ       = 3     /* Turbo */
+};
 
 /****************\
   TX DEFINITIONS
@@ -438,12 +452,10 @@ struct ath5k_tx_status {
         u16     ts_seqnum;
         u16     ts_tstamp;
         u8      ts_status;
-        u8      ts_rate[4];
-        u8      ts_retry[4];
         u8      ts_final_idx;
+        u8      ts_final_retry;
         s8      ts_rssi;
         u8      ts_shortretry;
-        u8      ts_longretry;
         u8      ts_virtcol;
         u8      ts_antenna;
 };
@@ -498,7 +510,7 @@ enum ath5k_tx_queue_id {
         AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
         AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
         AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
-        AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
+        AR5K_TX_QUEUE_ID_DATA_MAX       = 3, /*IEEE80211_TX_QUEUE_DATA3*/
         AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
         AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
         AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
@@ -531,9 +543,9 @@ struct ath5k_txq_info {
         enum ath5k_tx_queue tqi_type;
         enum ath5k_tx_queue_subtype tqi_subtype;
         u16     tqi_flags;      /* Tx queue flags (see above) */
-        u32     tqi_aifs;       /* Arbitrated Interframe Space */
-        s32     tqi_cw_min;     /* Minimum Contention Window */
-        s32     tqi_cw_max;     /* Maximum Contention Window */
+        u8      tqi_aifs;       /* Arbitrated Interframe Space */
+        u16     tqi_cw_min;     /* Minimum Contention Window */
+        u16     tqi_cw_max;     /* Maximum Contention Window */
         u32     tqi_cbr_period; /* Constant bit rate period */
         u32     tqi_cbr_overflow_limit;
         u32     tqi_burst_time;
@@ -658,7 +670,6 @@ struct ath5k_gain {
 
 /* channel_flags */
 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
-#define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 #define CHANNEL_CCK     0x0020  /* CCK channel */
 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
@@ -670,16 +681,10 @@ struct ath5k_gain {
 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
-#define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_108A    CHANNEL_T
-#define CHANNEL_108G    CHANNEL_TG
 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 
-#define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
-                CHANNEL_TURBO)
+#define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ)
 
-#define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
 #define CHANNEL_MODES           CHANNEL_ALL
 
 /*
@@ -867,6 +872,19 @@ enum ath5k_int {
         AR5K_INT_QTRIG  =       0x40000000, /* Non common */
         AR5K_INT_GLOBAL =       0x80000000,
 
+        AR5K_INT_TX_ALL = AR5K_INT_TXOK
+                | AR5K_INT_TXDESC
+                | AR5K_INT_TXERR
+                | AR5K_INT_TXEOL
+                | AR5K_INT_TXURN,
+
+        AR5K_INT_RX_ALL = AR5K_INT_RXOK
+                | AR5K_INT_RXDESC
+                | AR5K_INT_RXERR
+                | AR5K_INT_RXNOFRM
+                | AR5K_INT_RXEOL
+                | AR5K_INT_RXORN,
+
         AR5K_INT_COMMON  = AR5K_INT_RXOK
                 | AR5K_INT_RXDESC
                 | AR5K_INT_RXERR
@@ -1028,17 +1046,15 @@ struct ath5k_hw {
         enum ath5k_int          ah_imr;
 
         struct ieee80211_channel *ah_current_channel;
-        bool                    ah_turbo;
         bool                    ah_calibration;
         bool                    ah_single_chip;
-        bool                    ah_aes_support;
-        bool                    ah_combined_mic;
 
         enum ath5k_version      ah_version;
         enum ath5k_radio        ah_radio;
         u32                     ah_phy;
         u32                     ah_mac_srev;
         u16                     ah_mac_version;
+        u16                     ah_mac_revision;
         u16                     ah_phy_revision;
         u16                     ah_radio_5ghz_revision;
         u16                     ah_radio_2ghz_revision;
@@ -1046,19 +1062,19 @@ struct ath5k_hw {
 #define ah_modes                ah_capabilities.cap_mode
 #define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
 
-        u32                     ah_atim_window;
-        u32                     ah_aifs;
-        u32                     ah_cw_min;
-        u32                     ah_cw_max;
-        u32                     ah_limit_tx_retries;
+        u8                      ah_retry_long;
+        u8                      ah_retry_short;
+
         u8                      ah_coverage_class;
+        bool                    ah_ack_bitrate_high;
+        u8                      ah_bwmode;
+        bool                    ah_short_slot;
 
         /* Antenna Control */
         u32                     ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
         u8                      ah_ant_mode;
         u8                      ah_tx_ant;
         u8                      ah_def_ant;
-        bool                    ah_software_retry;
 
         struct ath5k_capabilities ah_capabilities;
 
@@ -1094,12 +1110,14 @@ struct ath5k_hw {
                 /* Values in 0.25dB units */
                 s16             txp_min_pwr;
                 s16             txp_max_pwr;
+                s16             txp_cur_pwr;
                 /* Values in 0.5dB units */
                 s16             txp_offset;
                 s16             txp_ofdm;
                 s16             txp_cck_ofdm_gainf_delta;
                 /* Value in dB units */
                 s16             txp_cck_ofdm_pwr_delta;
+                bool            txp_setup;
         } ah_txpower;
 
         struct {
@@ -1111,7 +1129,7 @@ struct ath5k_hw {
         struct ath5k_nfcal_hist ah_nfcal_hist;
 
         /* average beacon RSSI in our BSS (used by ANI) */
-        struct ath5k_avg_val    ah_beacon_rssi_avg;
+        struct ewma             ah_beacon_rssi_avg;
 
         /* noise floor from last periodic calibration */
         s32                     ah_noise_floor;
@@ -1137,39 +1155,80 @@ struct ath5k_hw {
                 struct ath5k_rx_status *);
 };
 
+struct ath_bus_ops {
+        enum ath_bus_type ath_bus_type;
+        void (*read_cachesize)(struct ath_common *common, int *csz);
+        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
+        int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
+};
+
 /*
  * Prototypes
  */
+extern const struct ieee80211_ops ath5k_hw_ops;
 
-/* Attach/Detach Functions */
-int ath5k_hw_attach(struct ath5k_softc *sc);
-void ath5k_hw_detach(struct ath5k_hw *ah);
+/* Initialization and detach functions */
+int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops);
+void ath5k_deinit_softc(struct ath5k_softc *sc);
+int ath5k_hw_init(struct ath5k_softc *sc);
+void ath5k_hw_deinit(struct ath5k_hw *ah);
 
 int ath5k_sysfs_register(struct ath5k_softc *sc);
 void ath5k_sysfs_unregister(struct ath5k_softc *sc);
 
+/* base.c */
+struct ath5k_buf;
+struct ath5k_txq;
+
+void set_beacon_filter(struct ieee80211_hw *hw, bool enable);
+bool ath_any_vif_assoc(struct ath5k_softc *sc);
+void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
+                    struct ath5k_txq *txq);
+int ath5k_init_hw(struct ath5k_softc *sc);
+int ath5k_stop_hw(struct ath5k_softc *sc);
+void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif);
+void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
+                                        struct ieee80211_vif *vif);
+int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan);
+void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
+int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
+void ath5k_beacon_config(struct ath5k_softc *sc);
+void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
+void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
+
+/*Chip id helper functions */
+const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
+int ath5k_hw_read_srev(struct ath5k_hw *ah);
+
 /* LED functions */
 int ath5k_init_leds(struct ath5k_softc *sc);
 void ath5k_led_enable(struct ath5k_softc *sc);
 void ath5k_led_off(struct ath5k_softc *sc);
 void ath5k_unregister_leds(struct ath5k_softc *sc);
 
+
 /* Reset Functions */
 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
 int ath5k_hw_on_hold(struct ath5k_hw *ah);
 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
-                   struct ieee80211_channel *channel, bool change_channel);
+           struct ieee80211_channel *channel, bool fast, bool skip_pcu);
 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
                               bool is_set);
 /* Power management functions */
 
+
+/* Clock rate related functions */
+unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
+unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
+void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
+
+
 /* DMA Related Functions */
 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
-int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
-void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
+int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
-int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
+int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
                                 u32 phys_addr);
@@ -1179,42 +1238,42 @@ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
+/* Init/Stop functions */
+void ath5k_hw_dma_init(struct ath5k_hw *ah);
+int ath5k_hw_dma_stop(struct ath5k_hw *ah);
 
 /* EEPROM access functions */
 int ath5k_eeprom_init(struct ath5k_hw *ah);
 void ath5k_eeprom_detach(struct ath5k_hw *ah);
-int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
+
 
 /* Protocol Control Unit Functions */
+/* Helpers */
+int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
+                int len, struct ieee80211_rate *rate, bool shortpre);
+unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
+unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
-/* BSSID Functions */
+/* RX filter control*/
 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
-void ath5k_hw_set_associd(struct ath5k_hw *ah);
+void ath5k_hw_set_bssid(struct ath5k_hw *ah);
 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
-/* Receive start/stop functions */
-void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
-void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
-/* RX Filter functions */
 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
+/* Receive (DRU) start/stop functions */
+void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
+void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
 /* Beacon control functions */
 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
-/* ACK bit rate */
-void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
-/* Clock rate related functions */
-unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
-unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
-unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
-/* Key table (WEP) functions */
-int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
-int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
-                     const struct ieee80211_key_conf *key, const u8 *mac);
-int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
+bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
+/* Init function */
+void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
+                                                                u8 mode);
 
 /* Queue Control Unit, DFS Control Unit Functions */
 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
@@ -1224,10 +1283,14 @@ int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
                             enum ath5k_tx_queue queue_type,
                             struct ath5k_txq_info *queue_info);
+void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
+                                  unsigned int queue);
 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
-int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
+int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
+/* Init function */
+int ath5k_hw_init_queues(struct ath5k_hw *ah);
 
 /* Hardware Descriptor Functions */
 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
@@ -1237,6 +1300,7 @@ int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
         u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
 
+
 /* GPIO Functions */
 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
@@ -1246,11 +1310,13 @@ int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
                             u32 interrupt_level);
 
-/* rfkill Functions */
+
+/* RFkill Functions */
 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
 
-/* Misc functions */
+
+/* Misc functions TODO: Cleanup */
 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
 int ath5k_hw_get_capability(struct ath5k_hw *ah,
                             enum ath5k_capability_type cap_type, u32 capability,
@@ -1258,19 +1324,20 @@ int ath5k_hw_get_capability(struct ath5k_hw *ah,
 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
 
+
 /* Initial register settings functions */
 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
 
-/* Initialize RF */
-int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
-                         struct ieee80211_channel *channel,
-                         unsigned int mode);
-int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
+
+/* PHY functions */
+/* Misc PHY functions */
+u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
+int ath5k_hw_phy_disable(struct ath5k_hw *ah);
+/* Gain_F optimization */
 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
 /* PHY/RF channel functions */
 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
-int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
 /* PHY calibration */
 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
@@ -1279,18 +1346,14 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
 /* Spur mitigation */
 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
                                   struct ieee80211_channel *channel);
-void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
-                                         struct ieee80211_channel *channel);
-/* Misc PHY functions */
-u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
-int ath5k_hw_phy_disable(struct ath5k_hw *ah);
 /* Antenna control */
 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
 /* TX power setup */
-int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
-                     u8 ee_mode, u8 txpower);
 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
+/* Init function */
+int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
+                                u8 mode, bool fast);
 
 /*
  * Functions used internaly
@@ -1306,6 +1369,32 @@ static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
         return &(ath5k_hw_common(ah)->regulatory);
 }
 
+#ifdef CONFIG_ATHEROS_AR231X
+#define AR5K_AR2315_PCI_BASE    ((void __iomem *)0xb0100000)
+
+static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
+{
+        /* On AR2315 and AR2317 the PCI clock domain registers
+         * are outside of the WMAC register space */
+        if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
+                (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
+                return AR5K_AR2315_PCI_BASE + reg;
+
+        return ah->ah_iobase + reg;
+}
+
+static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
+{
+        return __raw_readl(ath5k_ahb_reg(ah, reg));
+}
+
+static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
+{
+        __raw_writel(val, ath5k_ahb_reg(ah, reg));
+}
+
+#else
+
 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
 {
         return ioread32(ah->ah_iobase + reg);
@@ -1316,6 +1405,24 @@ static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
         iowrite32(val, ah->ah_iobase + reg);
 }
 
+#endif
+
+static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
+{
+        return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
+}
+
+static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
+{
+        common->bus_ops->read_cachesize(common, csz);
+}
+
+static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        return common->bus_ops->eeprom_read(common, off, data);
+}
+
 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
 {
         u32 retval = 0, bit, i;
@@ -1328,27 +1435,4 @@ static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
         return retval;
 }
 
-#define AVG_SAMPLES     8
-#define AVG_FACTOR      1000
-
-/**
- * ath5k_moving_average -  Exponentially weighted moving average
- * @avg: average structure
- * @val: current value
- *
- * This implementation make use of a struct ath5k_avg_val to prevent rounding
- * errors.
- */
-static inline struct ath5k_avg_val
-ath5k_moving_average(const struct ath5k_avg_val avg, const int val)
-{
-        struct ath5k_avg_val new;
-        new.avg_weight = avg.avg_weight  ?
-                (((avg.avg_weight * ((AVG_SAMPLES) - 1)) +
-                        (val * (AVG_FACTOR))) / (AVG_SAMPLES)) :
-                (val * (AVG_FACTOR));
-        new.avg = new.avg_weight / (AVG_FACTOR);
-        return new;
-}
-
 #endif
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index b32e28caeee2..1588401de3c4 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -93,16 +93,16 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_attach - Check if hw is supported and init the needed structs
+ * ath5k_hw_init - Check if hw is supported and init the needed structs
  *
- * @sc: The &struct ath5k_softc we got from the driver's attach function
+ * @sc: The &struct ath5k_softc we got from the driver's init_softc function
  *
  * Check if the device is supported, perform a POST and initialize the needed
  * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  * -ENODEV if the device is not supported or prints an error msg if something
  * else went wrong.
  */
-int ath5k_hw_attach(struct ath5k_softc *sc)
+int ath5k_hw_init(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
         struct ath_common *common = ath5k_hw_common(ah);
@@ -115,14 +115,11 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
          * HW information
          */
         ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
-        ah->ah_turbo = false;
+        ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
         ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
         ah->ah_imr = 0;
-        ah->ah_atim_window = 0;
-        ah->ah_aifs = AR5K_TUNE_AIFS;
-        ah->ah_cw_min = AR5K_TUNE_CWMIN;
-        ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
-        ah->ah_software_retry = false;
+        ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
+        ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
         ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
         ah->ah_noise_floor = -95;       /* until first NF calibration is run */
         sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
@@ -131,7 +128,8 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         /*
          * Find the mac version
          */
-        srev = ath5k_hw_reg_read(ah, AR5K_SREV);
+        ath5k_hw_read_srev(ah);
+        srev = ah->ah_mac_srev;
         if (srev < AR5K_SREV_AR5311)
                 ah->ah_version = AR5K_AR5210;
         else if (srev < AR5K_SREV_AR5212)
@@ -139,26 +137,28 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         else
                 ah->ah_version = AR5K_AR5212;
 
-        /*Fill the ath5k_hw struct with the needed functions*/
+        /* Get the MAC revision */
+        ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+        ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
+
+        /* Fill the ath5k_hw struct with the needed functions */
         ret = ath5k_hw_init_desc_functions(ah);
         if (ret)
-                goto err_free;
+                goto err;
 
-        /* Bring device out of sleep and reset it's units */
+        /* Bring device out of sleep and reset its units */
         ret = ath5k_hw_nic_wakeup(ah, 0, true);
         if (ret)
-                goto err_free;
+                goto err;
 
-        /* Get MAC, PHY and RADIO revisions */
-        ah->ah_mac_srev = srev;
-        ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+        /* Get PHY and RADIO revisions */
         ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
                         0xffffffff;
         ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
                         CHANNEL_5GHZ);
         ah->ah_phy = AR5K_PHY(0);
 
-        /* Try to identify radio chip based on it's srev */
+        /* Try to identify radio chip based on its srev */
         switch (ah->ah_radio_5ghz_revision & 0xf0) {
         case AR5K_SREV_RAD_5111:
                 ah->ah_radio = AR5K_RF5111;
@@ -220,7 +220,8 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
                         ah->ah_radio = AR5K_RF5112;
                         ah->ah_single_chip = false;
                         ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
-                } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
+                } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
+                        ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
                         ah->ah_radio = AR5K_RF2316;
                         ah->ah_single_chip = true;
                         ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
@@ -237,7 +238,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
                 } else {
                         ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
                         ret = -ENODEV;
-                        goto err_free;
+                        goto err;
                 }
         }
 
@@ -247,7 +248,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         (srev < AR5K_SREV_AR2425)) {
                 ATH5K_ERR(sc, "Device not yet supported.\n");
                 ret = -ENODEV;
-                goto err_free;
+                goto err;
         }
 
         /*
@@ -255,7 +256,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
          */
         ret = ath5k_hw_post(ah);
         if (ret)
-                goto err_free;
+                goto err;
 
         /* Enable pci core retry fix on Hainan (5213A) and later chips */
         if (srev >= AR5K_SREV_AR5213A)
@@ -268,7 +269,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         ret = ath5k_eeprom_init(ah);
         if (ret) {
                 ATH5K_ERR(sc, "unable to init EEPROM\n");
-                goto err_free;
+                goto err;
         }
 
         ee = &ah->ah_capabilities.cap_eeprom;
@@ -276,7 +277,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         /*
          * Write PCI-E power save settings
          */
-        if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
+        if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
                 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
                 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
 
@@ -308,18 +309,26 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         /* Get misc capabilities */
         ret = ath5k_hw_set_capabilities(ah);
         if (ret) {
-                ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
-                        sc->pdev->device);
-                goto err_free;
+                ATH5K_ERR(sc, "unable to get device capabilities\n");
+                goto err;
+        }
+
+        if (test_bit(ATH_STAT_2G_DISABLED, sc->status)) {
+                __clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode);
+                __clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode);
         }
 
         /* Crypto settings */
-        ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
-                (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
-                 !AR5K_EEPROM_AES_DIS(ee->ee_misc5));
+        common->keymax = (sc->ah->ah_version == AR5K_AR5210 ?
+                          AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
+
+        if (srev >= AR5K_SREV_AR5212_V4 &&
+            (ee->ee_version < AR5K_EEPROM_VERSION_5_0 ||
+            !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
+                common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
 
         if (srev >= AR5K_SREV_AR2414) {
-                ah->ah_combined_mic = true;
+                common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
                 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
                         AR5K_MISC_MODE_COMBINED_MIC);
         }
@@ -329,7 +338,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
 
         /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
         memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
-        ath5k_hw_set_associd(ah);
+        ath5k_hw_set_bssid(ah);
         ath5k_hw_set_opmode(ah, sc->opmode);
 
         ath5k_hw_rfgain_opt_init(ah);
@@ -340,17 +349,16 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
 
         return 0;
-err_free:
-        kfree(ah);
+err:
         return ret;
 }
 
 /**
- * ath5k_hw_detach - Free the ath5k_hw struct
+ * ath5k_hw_deinit - Free the ath5k_hw struct
  *
  * @ah: The &struct ath5k_hw
  */
-void ath5k_hw_detach(struct ath5k_hw *ah)
+void ath5k_hw_deinit(struct ath5k_hw *ah)
 {
         __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
 
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index d77ce9906b6c..b6c5d3715b96 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -47,11 +47,10 @@
 #include <linux/io.h>
 #include <linux/netdevice.h>
 #include <linux/cache.h>
-#include <linux/pci.h>
-#include <linux/pci-aspm.h>
 #include <linux/ethtool.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
+#include <linux/etherdevice.h>
 
 #include <net/ieee80211_radiotap.h>
 
@@ -62,18 +61,21 @@
 #include "debug.h"
 #include "ani.h"
 
-static int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
+#define CREATE_TRACE_POINTS
+#include "trace.h"
+
+int ath5k_modparam_nohwcrypt;
+module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
 
 static int modparam_all_channels;
 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
 
+static int modparam_fastchanswitch;
+module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
+MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
 
-/******************\
-* Internal defines *
-\******************/
 
 /* Module info */
 MODULE_AUTHOR("Jiri Slaby");
@@ -81,35 +83,24 @@ MODULE_AUTHOR("Nick Kossifidis");
 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
 MODULE_LICENSE("Dual BSD/GPL");
-MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
-
-
-/* Known PCI ids */
-static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
-        { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
-        { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
-        { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
-        { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
-        { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
-        { PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
-        { PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
-        { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
-        { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
-        { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
-        { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
-        { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
-        { 0 }
-};
-MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
+
+static int ath5k_init(struct ieee80211_hw *hw);
+static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
+                                                                bool skip_pcu);
+int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
+void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 
 /* Known SREVs */
 static const struct ath5k_srev_name srev_names[] = {
+#ifdef CONFIG_ATHEROS_AR231X
+        { "5312",       AR5K_VERSION_MAC,       AR5K_SREV_AR5312_R2 },
+        { "5312",       AR5K_VERSION_MAC,       AR5K_SREV_AR5312_R7 },
+        { "2313",       AR5K_VERSION_MAC,       AR5K_SREV_AR2313_R8 },
+        { "2315",       AR5K_VERSION_MAC,       AR5K_SREV_AR2315_R6 },
+        { "2315",       AR5K_VERSION_MAC,       AR5K_SREV_AR2315_R7 },
+        { "2317",       AR5K_VERSION_MAC,       AR5K_SREV_AR2317_R1 },
+        { "2317",       AR5K_VERSION_MAC,       AR5K_SREV_AR2317_R2 },
+#else
         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
@@ -128,6 +119,7 @@ static const struct ath5k_srev_name srev_names[] = {
         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
+#endif
         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
@@ -141,10 +133,12 @@ static const struct ath5k_srev_name srev_names[] = {
         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
-        { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
-        { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
+#ifdef CONFIG_ATHEROS_AR231X
+        { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
+        { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
+#endif
         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 };
 
@@ -190,190 +184,6 @@ static const struct ieee80211_rate ath5k_rates[] = {
         /* XR missing */
 };
 
-/*
- * Prototypes - PCI stack related functions
- */
-static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
-                                const struct pci_device_id *id);
-static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
-#ifdef CONFIG_PM_SLEEP
-static int              ath5k_pci_suspend(struct device *dev);
-static int              ath5k_pci_resume(struct device *dev);
-
-static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
-#define ATH5K_PM_OPS    (&ath5k_pm_ops)
-#else
-#define ATH5K_PM_OPS    NULL
-#endif /* CONFIG_PM_SLEEP */
-
-static struct pci_driver ath5k_pci_driver = {
-        .name           = KBUILD_MODNAME,
-        .id_table       = ath5k_pci_id_table,
-        .probe          = ath5k_pci_probe,
-        .remove         = __devexit_p(ath5k_pci_remove),
-        .driver.pm      = ATH5K_PM_OPS,
-};
-
-
-
-/*
- * Prototypes - MAC 802.11 stack related functions
- */
-static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
-static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
-                struct ath5k_txq *txq);
-static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
-static int ath5k_start(struct ieee80211_hw *hw);
-static void ath5k_stop(struct ieee80211_hw *hw);
-static int ath5k_add_interface(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif);
-static void ath5k_remove_interface(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif);
-static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
-static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
-                                   struct netdev_hw_addr_list *mc_list);
-static void ath5k_configure_filter(struct ieee80211_hw *hw,
-                unsigned int changed_flags,
-                unsigned int *new_flags,
-                u64 multicast);
-static int ath5k_set_key(struct ieee80211_hw *hw,
-                enum set_key_cmd cmd,
-                struct ieee80211_vif *vif, struct ieee80211_sta *sta,
-                struct ieee80211_key_conf *key);
-static int ath5k_get_stats(struct ieee80211_hw *hw,
-                struct ieee80211_low_level_stats *stats);
-static int ath5k_get_survey(struct ieee80211_hw *hw,
-                int idx, struct survey_info *survey);
-static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
-static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
-static void ath5k_reset_tsf(struct ieee80211_hw *hw);
-static int ath5k_beacon_update(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif);
-static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif,
-                struct ieee80211_bss_conf *bss_conf,
-                u32 changes);
-static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
-static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
-static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
-                u8 coverage_class);
-
-static const struct ieee80211_ops ath5k_hw_ops = {
-        .tx             = ath5k_tx,
-        .start          = ath5k_start,
-        .stop           = ath5k_stop,
-        .add_interface  = ath5k_add_interface,
-        .remove_interface = ath5k_remove_interface,
-        .config         = ath5k_config,
-        .prepare_multicast = ath5k_prepare_multicast,
-        .configure_filter = ath5k_configure_filter,
-        .set_key        = ath5k_set_key,
-        .get_stats      = ath5k_get_stats,
-        .get_survey     = ath5k_get_survey,
-        .conf_tx        = NULL,
-        .get_tsf        = ath5k_get_tsf,
-        .set_tsf        = ath5k_set_tsf,
-        .reset_tsf      = ath5k_reset_tsf,
-        .bss_info_changed = ath5k_bss_info_changed,
-        .sw_scan_start  = ath5k_sw_scan_start,
-        .sw_scan_complete = ath5k_sw_scan_complete,
-        .set_coverage_class = ath5k_set_coverage_class,
-};
-
-/*
- * Prototypes - Internal functions
- */
-/* Attach detach */
-static int      ath5k_attach(struct pci_dev *pdev,
-                        struct ieee80211_hw *hw);
-static void     ath5k_detach(struct pci_dev *pdev,
-                        struct ieee80211_hw *hw);
-/* Channel/mode setup */
-static inline short ath5k_ieee2mhz(short chan);
-static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
-                                struct ieee80211_channel *channels,
-                                unsigned int mode,
-                                unsigned int max);
-static int      ath5k_setup_bands(struct ieee80211_hw *hw);
-static int      ath5k_chan_set(struct ath5k_softc *sc,
-                                struct ieee80211_channel *chan);
-static void     ath5k_setcurmode(struct ath5k_softc *sc,
-                                unsigned int mode);
-static void     ath5k_mode_setup(struct ath5k_softc *sc);
-
-/* Descriptor setup */
-static int      ath5k_desc_alloc(struct ath5k_softc *sc,
-                                struct pci_dev *pdev);
-static void     ath5k_desc_free(struct ath5k_softc *sc,
-                                struct pci_dev *pdev);
-/* Buffers setup */
-static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
-                                struct ath5k_buf *bf);
-static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
-                                struct ath5k_buf *bf,
-                                struct ath5k_txq *txq, int padsize);
-
-static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
-                                struct ath5k_buf *bf)
-{
-        BUG_ON(!bf);
-        if (!bf->skb)
-                return;
-        pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
-                        PCI_DMA_TODEVICE);
-        dev_kfree_skb_any(bf->skb);
-        bf->skb = NULL;
-        bf->skbaddr = 0;
-        bf->desc->ds_data = 0;
-}
-
-static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
-                                struct ath5k_buf *bf)
-{
-        struct ath5k_hw *ah = sc->ah;
-        struct ath_common *common = ath5k_hw_common(ah);
-
-        BUG_ON(!bf);
-        if (!bf->skb)
-                return;
-        pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
-                        PCI_DMA_FROMDEVICE);
-        dev_kfree_skb_any(bf->skb);
-        bf->skb = NULL;
-        bf->skbaddr = 0;
-        bf->desc->ds_data = 0;
-}
-
-
-/* Queues setup */
-static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
-                                int qtype, int subtype);
-static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
-static int      ath5k_beaconq_config(struct ath5k_softc *sc);
-static void     ath5k_txq_drainq(struct ath5k_softc *sc,
-                                struct ath5k_txq *txq);
-static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
-static void     ath5k_txq_release(struct ath5k_softc *sc);
-/* Rx handling */
-static int      ath5k_rx_start(struct ath5k_softc *sc);
-static void     ath5k_rx_stop(struct ath5k_softc *sc);
-static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
-                                        struct sk_buff *skb,
-                                        struct ath5k_rx_status *rs);
-static void     ath5k_tasklet_rx(unsigned long data);
-/* Tx handling */
-static void     ath5k_tx_processq(struct ath5k_softc *sc,
-                                struct ath5k_txq *txq);
-static void     ath5k_tasklet_tx(unsigned long data);
-/* Beacon handling */
-static int      ath5k_beacon_setup(struct ath5k_softc *sc,
-                                        struct ath5k_buf *bf);
-static void     ath5k_beacon_send(struct ath5k_softc *sc);
-static void     ath5k_beacon_config(struct ath5k_softc *sc);
-static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
-static void     ath5k_tasklet_beacon(unsigned long data);
-static void     ath5k_tasklet_ani(unsigned long data);
-
 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 {
         u64 tsf = ath5k_hw_get_tsf64(ah);
@@ -384,51 +194,7 @@ static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
         return (tsf & ~0x7fff) | rstamp;
 }
 
-/* Interrupt handling */
-static int      ath5k_init(struct ath5k_softc *sc);
-static int      ath5k_stop_locked(struct ath5k_softc *sc);
-static int      ath5k_stop_hw(struct ath5k_softc *sc);
-static irqreturn_t ath5k_intr(int irq, void *dev_id);
-static void ath5k_reset_work(struct work_struct *work);
-
-static void     ath5k_tasklet_calibrate(unsigned long data);
-
-/*
- * Module init/exit functions
- */
-static int __init
-init_ath5k_pci(void)
-{
-        int ret;
-
-        ath5k_debug_init();
-
-        ret = pci_register_driver(&ath5k_pci_driver);
-        if (ret) {
-                printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
-                return ret;
-        }
-
-        return 0;
-}
-
-static void __exit
-exit_ath5k_pci(void)
-{
-        pci_unregister_driver(&ath5k_pci_driver);
-
-        ath5k_debug_finish();
-}
-
-module_init(init_ath5k_pci);
-module_exit(exit_ath5k_pci);
-
-
-/********************\
-* PCI Initialization *
-\********************/
-
-static const char *
+const char *
 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 {
         const char *name = "xxxxx";
@@ -466,299 +232,6 @@ static const struct ath_ops ath5k_common_ops = {
         .write = ath5k_iowrite32,
 };
 
-static int __devinit
-ath5k_pci_probe(struct pci_dev *pdev,
-                const struct pci_device_id *id)
-{
-        void __iomem *mem;
-        struct ath5k_softc *sc;
-        struct ath_common *common;
-        struct ieee80211_hw *hw;
-        int ret;
-        u8 csz;
-
-        /*
-         * L0s needs to be disabled on all ath5k cards.
-         *
-         * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
-         * by default in the future in 2.6.36) this will also mean both L1 and
-         * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
-         * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
-         * though but cannot currently undue the effect of a blacklist, for
-         * details you can read pcie_aspm_sanity_check() and see how it adjusts
-         * the device link capability.
-         *
-         * It may be possible in the future to implement some PCI API to allow
-         * drivers to override blacklists for pre 1.1 PCIe but for now it is
-         * best to accept that both L0s and L1 will be disabled completely for
-         * distributions shipping with CONFIG_PCIEASPM rather than having this
-         * issue present. Motivation for adding this new API will be to help
-         * with power consumption for some of these devices.
-         */
-        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
-
-        ret = pci_enable_device(pdev);
-        if (ret) {
-                dev_err(&pdev->dev, "can't enable device\n");
-                goto err;
-        }
-
-        /* XXX 32-bit addressing only */
-        ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
-        if (ret) {
-                dev_err(&pdev->dev, "32-bit DMA not available\n");
-                goto err_dis;
-        }
-
-        /*
-         * Cache line size is used to size and align various
-         * structures used to communicate with the hardware.
-         */
-        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
-        if (csz == 0) {
-                /*
-                 * Linux 2.4.18 (at least) writes the cache line size
-                 * register as a 16-bit wide register which is wrong.
-                 * We must have this setup properly for rx buffer
-                 * DMA to work so force a reasonable value here if it
-                 * comes up zero.
-                 */
-                csz = L1_CACHE_BYTES >> 2;
-                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
-        }
-        /*
-         * The default setting of latency timer yields poor results,
-         * set it to the value used by other systems.  It may be worth
-         * tweaking this setting more.
-         */
-        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
-
-        /* Enable bus mastering */
-        pci_set_master(pdev);
-
-        /*
-         * Disable the RETRY_TIMEOUT register (0x41) to keep
-         * PCI Tx retries from interfering with C3 CPU state.
-         */
-        pci_write_config_byte(pdev, 0x41, 0);
-
-        ret = pci_request_region(pdev, 0, "ath5k");
-        if (ret) {
-                dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
-                goto err_dis;
-        }
-
-        mem = pci_iomap(pdev, 0, 0);
-        if (!mem) {
-                dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
-                ret = -EIO;
-                goto err_reg;
-        }
-
-        /*
-         * Allocate hw (mac80211 main struct)
-         * and hw->priv (driver private data)
-         */
-        hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
-        if (hw == NULL) {
-                dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
-                ret = -ENOMEM;
-                goto err_map;
-        }
-
-        dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
-
-        /* Initialize driver private data */
-        SET_IEEE80211_DEV(hw, &pdev->dev);
-        hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
-                    IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
-                    IEEE80211_HW_SIGNAL_DBM;
-
-        hw->wiphy->interface_modes =
-                BIT(NL80211_IFTYPE_AP) |
-                BIT(NL80211_IFTYPE_STATION) |
-                BIT(NL80211_IFTYPE_ADHOC) |
-                BIT(NL80211_IFTYPE_MESH_POINT);
-
-        hw->extra_tx_headroom = 2;
-        hw->channel_change_time = 5000;
-        sc = hw->priv;
-        sc->hw = hw;
-        sc->pdev = pdev;
-
-        ath5k_debug_init_device(sc);
-
-        /*
-         * Mark the device as detached to avoid processing
-         * interrupts until setup is complete.
-         */
-        __set_bit(ATH_STAT_INVALID, sc->status);
-
-        sc->iobase = mem; /* So we can unmap it on detach */
-        sc->opmode = NL80211_IFTYPE_STATION;
-        sc->bintval = 1000;
-        mutex_init(&sc->lock);
-        spin_lock_init(&sc->rxbuflock);
-        spin_lock_init(&sc->txbuflock);
-        spin_lock_init(&sc->block);
-
-        /* Set private data */
-        pci_set_drvdata(pdev, sc);
-
-        /* Setup interrupt handler */
-        ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
-        if (ret) {
-                ATH5K_ERR(sc, "request_irq failed\n");
-                goto err_free;
-        }
-
-        /*If we passed the test malloc a ath5k_hw struct*/
-        sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
-        if (!sc->ah) {
-                ret = -ENOMEM;
-                ATH5K_ERR(sc, "out of memory\n");
-                goto err_irq;
-        }
-
-        sc->ah->ah_sc = sc;
-        sc->ah->ah_iobase = sc->iobase;
-        common = ath5k_hw_common(sc->ah);
-        common->ops = &ath5k_common_ops;
-        common->ah = sc->ah;
-        common->hw = hw;
-        common->cachelsz = csz << 2; /* convert to bytes */
-
-        /* Initialize device */
-        ret = ath5k_hw_attach(sc);
-        if (ret) {
-                goto err_free_ah;
-        }
-
-        /* set up multi-rate retry capabilities */
-        if (sc->ah->ah_version == AR5K_AR5212) {
-                hw->max_rates = 4;
-                hw->max_rate_tries = 11;
-        }
-
-        /* Finish private driver data initialization */
-        ret = ath5k_attach(pdev, hw);
-        if (ret)
-                goto err_ah;
-
-        ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
-                        ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
-                                        sc->ah->ah_mac_srev,
-                                        sc->ah->ah_phy_revision);
-
-        if (!sc->ah->ah_single_chip) {
-                /* Single chip radio (!RF5111) */
-                if (sc->ah->ah_radio_5ghz_revision &&
-                        !sc->ah->ah_radio_2ghz_revision) {
-                        /* No 5GHz support -> report 2GHz radio */
-                        if (!test_bit(AR5K_MODE_11A,
-                                sc->ah->ah_capabilities.cap_mode)) {
-                                ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
-                                        ath5k_chip_name(AR5K_VERSION_RAD,
-                                                sc->ah->ah_radio_5ghz_revision),
-                                                sc->ah->ah_radio_5ghz_revision);
-                        /* No 2GHz support (5110 and some
-                         * 5Ghz only cards) -> report 5Ghz radio */
-                        } else if (!test_bit(AR5K_MODE_11B,
-                                sc->ah->ah_capabilities.cap_mode)) {
-                                ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
-                                        ath5k_chip_name(AR5K_VERSION_RAD,
-                                                sc->ah->ah_radio_5ghz_revision),
-                                                sc->ah->ah_radio_5ghz_revision);
-                        /* Multiband radio */
-                        } else {
-                                ATH5K_INFO(sc, "RF%s multiband radio found"
-                                        " (0x%x)\n",
-                                        ath5k_chip_name(AR5K_VERSION_RAD,
-                                                sc->ah->ah_radio_5ghz_revision),
-                                                sc->ah->ah_radio_5ghz_revision);
-                        }
-                }
-                /* Multi chip radio (RF5111 - RF2111) ->
-                 * report both 2GHz/5GHz radios */
-                else if (sc->ah->ah_radio_5ghz_revision &&
-                                sc->ah->ah_radio_2ghz_revision){
-                        ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
-                                ath5k_chip_name(AR5K_VERSION_RAD,
-                                        sc->ah->ah_radio_5ghz_revision),
-                                        sc->ah->ah_radio_5ghz_revision);
-                        ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
-                                ath5k_chip_name(AR5K_VERSION_RAD,
-                                        sc->ah->ah_radio_2ghz_revision),
-                                        sc->ah->ah_radio_2ghz_revision);
-                }
-        }
-
-
-        /* ready to process interrupts */
-        __clear_bit(ATH_STAT_INVALID, sc->status);
-
-        return 0;
-err_ah:
-        ath5k_hw_detach(sc->ah);
-err_irq:
-        free_irq(pdev->irq, sc);
-err_free_ah:
-        kfree(sc->ah);
-err_free:
-        ieee80211_free_hw(hw);
-err_map:
-        pci_iounmap(pdev, mem);
-err_reg:
-        pci_release_region(pdev, 0);
-err_dis:
-        pci_disable_device(pdev);
-err:
-        return ret;
-}
-
-static void __devexit
-ath5k_pci_remove(struct pci_dev *pdev)
-{
-        struct ath5k_softc *sc = pci_get_drvdata(pdev);
-
-        ath5k_debug_finish_device(sc);
-        ath5k_detach(pdev, sc->hw);
-        ath5k_hw_detach(sc->ah);
-        kfree(sc->ah);
-        free_irq(pdev->irq, sc);
-        pci_iounmap(pdev, sc->iobase);
-        pci_release_region(pdev, 0);
-        pci_disable_device(pdev);
-        ieee80211_free_hw(sc->hw);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int ath5k_pci_suspend(struct device *dev)
-{
-        struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
-
-        ath5k_led_off(sc);
-        return 0;
-}
-
-static int ath5k_pci_resume(struct device *dev)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        struct ath5k_softc *sc = pci_get_drvdata(pdev);
-
-        /*
-         * Suspend/Resume resets the PCI configuration space, so we have to
-         * re-disable the RETRY_TIMEOUT register (0x41) to keep
-         * PCI Tx retries from interfering with C3 CPU state
-         */
-        pci_write_config_byte(pdev, 0x41, 0);
-
-        ath5k_led_enable(sc);
-        return 0;
-}
-#endif /* CONFIG_PM_SLEEP */
-
-
 /***********************\
 * Driver Initialization *
 \***********************/
@@ -772,260 +245,83 @@ static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *re
         return ath_reg_notifier_apply(wiphy, request, regulatory);
 }
 
-static int
-ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
-        u8 mac[ETH_ALEN] = {};
-        int ret;
-
-        ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
-
-        /*
-         * Check if the MAC has multi-rate retry support.
-         * We do this by trying to setup a fake extended
-         * descriptor.  MAC's that don't have support will
-         * return false w/o doing anything.  MAC's that do
-         * support it will return true w/o doing anything.
-         */
-        ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
-
-        if (ret < 0)
-                goto err;
-        if (ret > 0)
-                __set_bit(ATH_STAT_MRRETRY, sc->status);
-
-        /*
-         * Collect the channel list.  The 802.11 layer
-         * is resposible for filtering this list based
-         * on settings like the phy mode and regulatory
-         * domain restrictions.
-         */
-        ret = ath5k_setup_bands(hw);
-        if (ret) {
-                ATH5K_ERR(sc, "can't get channels\n");
-                goto err;
-        }
-
-        /* NB: setup here so ath5k_rate_update is happy */
-        if (test_bit(AR5K_MODE_11A, ah->ah_modes))
-                ath5k_setcurmode(sc, AR5K_MODE_11A);
-        else
-                ath5k_setcurmode(sc, AR5K_MODE_11B);
-
-        /*
-         * Allocate tx+rx descriptors and populate the lists.
-         */
-        ret = ath5k_desc_alloc(sc, pdev);
-        if (ret) {
-                ATH5K_ERR(sc, "can't allocate descriptors\n");
-                goto err;
-        }
-
-        /*
-         * Allocate hardware transmit queues: one queue for
-         * beacon frames and one data queue for each QoS
-         * priority.  Note that hw functions handle reseting
-         * these queues at the needed time.
-         */
-        ret = ath5k_beaconq_setup(ah);
-        if (ret < 0) {
-                ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
-                goto err_desc;
-        }
-        sc->bhalq = ret;
-        sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
-        if (IS_ERR(sc->cabq)) {
-                ATH5K_ERR(sc, "can't setup cab queue\n");
-                ret = PTR_ERR(sc->cabq);
-                goto err_bhal;
-        }
-
-        sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
-        if (IS_ERR(sc->txq)) {
-                ATH5K_ERR(sc, "can't setup xmit queue\n");
-                ret = PTR_ERR(sc->txq);
-                goto err_queues;
-        }
-
-        tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
-        tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
-        tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
-        tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
-        tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
-
-        INIT_WORK(&sc->reset_work, ath5k_reset_work);
-
-        ret = ath5k_eeprom_read_mac(ah, mac);
-        if (ret) {
-                ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
-                        sc->pdev->device);
-                goto err_queues;
-        }
-
-        SET_IEEE80211_PERM_ADDR(hw, mac);
-        /* All MAC address bits matter for ACKs */
-        memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
-        ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
-
-        regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
-        ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
-        if (ret) {
-                ATH5K_ERR(sc, "can't initialize regulatory system\n");
-                goto err_queues;
-        }
-
-        ret = ieee80211_register_hw(hw);
-        if (ret) {
-                ATH5K_ERR(sc, "can't register ieee80211 hw\n");
-                goto err_queues;
-        }
-
-        if (!ath_is_world_regd(regulatory))
-                regulatory_hint(hw->wiphy, regulatory->alpha2);
-
-        ath5k_init_leds(sc);
-
-        ath5k_sysfs_register(sc);
-
-        return 0;
-err_queues:
-        ath5k_txq_release(sc);
-err_bhal:
-        ath5k_hw_release_tx_queue(ah, sc->bhalq);
-err_desc:
-        ath5k_desc_free(sc, pdev);
-err:
-        return ret;
-}
-
-static void
-ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        /*
-         * NB: the order of these is important:
-         * o call the 802.11 layer before detaching ath5k_hw to
-         *   insure callbacks into the driver to delete global
-         *   key cache entries can be handled
-         * o reclaim the tx queue data structures after calling
-         *   the 802.11 layer as we'll get called back to reclaim
-         *   node state and potentially want to use them
-         * o to cleanup the tx queues the hal is called, so detach
-         *   it last
-         * XXX: ??? detach ath5k_hw ???
-         * Other than that, it's straightforward...
-         */
-        ieee80211_unregister_hw(hw);
-        ath5k_desc_free(sc, pdev);
-        ath5k_txq_release(sc);
-        ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
-        ath5k_unregister_leds(sc);
-
-        ath5k_sysfs_unregister(sc);
-        /*
-         * NB: can't reclaim these until after ieee80211_ifdetach
-         * returns because we'll get called back to reclaim node
-         * state and potentially want to use them.
-         */
-}
-
-
-
-
 /********************\
 * Channel/mode setup *
 \********************/
 
 /*
- * Convert IEEE channel number to MHz frequency.
- */
-static inline short
-ath5k_ieee2mhz(short chan)
-{
-        if (chan <= 14 || chan >= 27)
-                return ieee80211chan2mhz(chan);
-        else
-                return 2212 + chan * 20;
-}
-
-/*
  * Returns true for the channel numbers used without all_channels modparam.
  */
-static bool ath5k_is_standard_channel(short chan)
+static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
 {
-        return ((chan <= 14) ||
-                /* UNII 1,2 */
-                ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
+        if (band == IEEE80211_BAND_2GHZ && chan <= 14)
+                return true;
+
+        return  /* UNII 1,2 */
+                (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
                 /* midband */
                 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
                 /* UNII-3 */
-                ((chan & 3) == 1 && chan >= 149 && chan <= 165));
+                ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
+                /* 802.11j 5.030-5.080 GHz (20MHz) */
+                (chan == 8 || chan == 12 || chan == 16) ||
+                /* 802.11j 4.9GHz (20MHz) */
+                (chan == 184 || chan == 188 || chan == 192 || chan == 196));
 }
 
 static unsigned int
-ath5k_copy_channels(struct ath5k_hw *ah,
-                struct ieee80211_channel *channels,
-                unsigned int mode,
-                unsigned int max)
+ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
+                unsigned int mode, unsigned int max)
 {
-        unsigned int i, count, size, chfreq, freq, ch;
-
-        if (!test_bit(mode, ah->ah_modes))
-                return 0;
+        unsigned int count, size, chfreq, freq, ch;
+        enum ieee80211_band band;
 
         switch (mode) {
         case AR5K_MODE_11A:
-        case AR5K_MODE_11A_TURBO:
                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
-                size = 220 ;
+                size = 220;
                 chfreq = CHANNEL_5GHZ;
+                band = IEEE80211_BAND_5GHZ;
                 break;
         case AR5K_MODE_11B:
         case AR5K_MODE_11G:
-        case AR5K_MODE_11G_TURBO:
                 size = 26;
                 chfreq = CHANNEL_2GHZ;
+                band = IEEE80211_BAND_2GHZ;
                 break;
         default:
                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
                 return 0;
         }
 
-        for (i = 0, count = 0; i < size && max > 0; i++) {
-                ch = i + 1 ;
-                freq = ath5k_ieee2mhz(ch);
+        count = 0;
+        for (ch = 1; ch <= size && count < max; ch++) {
+                freq = ieee80211_channel_to_frequency(ch, band);
+
+                if (freq == 0) /* mapping failed - not a standard channel */
+                        continue;
 
                 /* Check if channel is supported by the chipset */
                 if (!ath5k_channel_ok(ah, freq, chfreq))
                         continue;
 
-                if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
+                if (!modparam_all_channels &&
+                    !ath5k_is_standard_channel(ch, band))
                         continue;
 
                 /* Write channel info and increment counter */
                 channels[count].center_freq = freq;
-                channels[count].band = (chfreq == CHANNEL_2GHZ) ?
-                        IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
+                channels[count].band = band;
                 switch (mode) {
                 case AR5K_MODE_11A:
                 case AR5K_MODE_11G:
                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
                         break;
-                case AR5K_MODE_11A_TURBO:
-                case AR5K_MODE_11G_TURBO:
-                        channels[count].hw_value = chfreq |
-                                CHANNEL_OFDM | CHANNEL_TURBO;
-                        break;
                 case AR5K_MODE_11B:
                         channels[count].hw_value = CHANNEL_B;
                 }
 
                 count++;
-                max--;
         }
 
         return count;
@@ -1070,7 +366,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
                 sband->n_bitrates = 12;
 
                 sband->channels = sc->channels;
-                sband->n_channels = ath5k_copy_channels(ah, sband->channels,
+                sband->n_channels = ath5k_setup_channels(ah, sband->channels,
                                         AR5K_MODE_11G, max_c);
 
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
@@ -1096,7 +392,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
                 }
 
                 sband->channels = sc->channels;
-                sband->n_channels = ath5k_copy_channels(ah, sband->channels,
+                sband->n_channels = ath5k_setup_channels(ah, sband->channels,
                                         AR5K_MODE_11B, max_c);
 
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
@@ -1116,7 +412,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
                 sband->n_bitrates = 8;
 
                 sband->channels = &sc->channels[count_c];
-                sband->n_channels = ath5k_copy_channels(ah, sband->channels,
+                sband->n_channels = ath5k_setup_channels(ah, sband->channels,
                                         AR5K_MODE_11A, max_c);
 
                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
@@ -1135,7 +431,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
  *
  * Called with sc->lock.
  */
-static int
+int
 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
 {
         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
@@ -1148,38 +444,102 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
          * hardware at the new frequency, and then re-enable
          * the relevant bits of the h/w.
          */
-        return ath5k_reset(sc, chan);
+        return ath5k_reset(sc, chan, true);
 }
 
-static void
-ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
+void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
 {
-        sc->curmode = mode;
+        struct ath5k_vif_iter_data *iter_data = data;
+        int i;
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
 
-        if (mode == AR5K_MODE_11A) {
-                sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
-        } else {
-                sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
+        if (iter_data->hw_macaddr)
+                for (i = 0; i < ETH_ALEN; i++)
+                        iter_data->mask[i] &=
+                                ~(iter_data->hw_macaddr[i] ^ mac[i]);
+
+        if (!iter_data->found_active) {
+                iter_data->found_active = true;
+                memcpy(iter_data->active_mac, mac, ETH_ALEN);
+        }
+
+        if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
+                if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
+                        iter_data->need_set_hw_addr = false;
+
+        if (!iter_data->any_assoc) {
+                if (avf->assoc)
+                        iter_data->any_assoc = true;
+        }
+
+        /* Calculate combined mode - when APs are active, operate in AP mode.
+         * Otherwise use the mode of the new interface. This can currently
+         * only deal with combinations of APs and STAs. Only one ad-hoc
+         * interfaces is allowed.
+         */
+        if (avf->opmode == NL80211_IFTYPE_AP)
+                iter_data->opmode = NL80211_IFTYPE_AP;
+        else {
+                if (avf->opmode == NL80211_IFTYPE_STATION)
+                        iter_data->n_stas++;
+                if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
+                        iter_data->opmode = avf->opmode;
         }
 }
 
-static void
-ath5k_mode_setup(struct ath5k_softc *sc)
+void
+ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
+                                   struct ieee80211_vif *vif)
 {
-        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(sc->ah);
+        struct ath5k_vif_iter_data iter_data;
         u32 rfilt;
 
-        /* configure rx filter */
-        rfilt = sc->filter_flags;
-        ath5k_hw_set_rx_filter(ah, rfilt);
-
-        if (ath5k_hw_hasbssidmask(ah))
-                ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
-
-        /* configure operational mode */
-        ath5k_hw_set_opmode(ah, sc->opmode);
+        /*
+         * Use the hardware MAC address as reference, the hardware uses it
+         * together with the BSSID mask when matching addresses.
+         */
+        iter_data.hw_macaddr = common->macaddr;
+        memset(&iter_data.mask, 0xff, ETH_ALEN);
+        iter_data.found_active = false;
+        iter_data.need_set_hw_addr = true;
+        iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
+        iter_data.n_stas = 0;
+
+        if (vif)
+                ath5k_vif_iter(&iter_data, vif->addr, vif);
+
+        /* Get list of all active MAC addresses */
+        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
+                                                   &iter_data);
+        memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
+
+        sc->opmode = iter_data.opmode;
+        if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
+                /* Nothing active, default to station mode */
+                sc->opmode = NL80211_IFTYPE_STATION;
+
+        ath5k_hw_set_opmode(sc->ah, sc->opmode);
+        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
+                  sc->opmode, ath_opmode_to_string(sc->opmode));
+
+        if (iter_data.need_set_hw_addr && iter_data.found_active)
+                ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
+
+        if (ath5k_hw_hasbssidmask(sc->ah))
+                ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
+
+        /* Set up RX Filter */
+        if (iter_data.n_stas > 1) {
+                /* If you have multiple STA interfaces connected to
+                 * different APs, ARPs are not received (most of the time?)
+                 * Enabling PROMISC appears to fix that probem.
+                 */
+                sc->filter_flags |= AR5K_RX_FILTER_PROM;
+        }
 
-        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
+        rfilt = sc->filter_flags;
+        ath5k_hw_set_rx_filter(sc->ah, rfilt);
         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
 }
 
@@ -1193,7 +553,7 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
                         "hw_rix out of bounds: %x\n", hw_rix))
                 return 0;
 
-        rix = sc->rate_idx[sc->curband->band][hw_rix];
+        rix = sc->rate_idx[sc->curchan->band][hw_rix];
         if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
                 rix = 0;
 
@@ -1224,10 +584,11 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
                 return NULL;
         }
 
-        *skb_addr = pci_map_single(sc->pdev,
+        *skb_addr = dma_map_single(sc->dev,
                                    skb->data, common->rx_bufsize,
-                                   PCI_DMA_FROMDEVICE);
-        if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
+                                   DMA_FROM_DEVICE);
+
+        if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
                 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
                 dev_kfree_skb(skb);
                 return NULL;
@@ -1323,8 +684,8 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
 
         /* XXX endianness */
-        bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
-                        PCI_DMA_TODEVICE);
+        bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
+                        DMA_TO_DEVICE);
 
         rate = ieee80211_get_tx_rate(sc->hw, info);
         if (!rate) {
@@ -1352,13 +713,13 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
                 flags |= AR5K_TXDESC_RTSENA;
                 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
                 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
-                        sc->vif, pktlen, info));
+                        info->control.vif, pktlen, info));
         }
         if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
                 flags |= AR5K_TXDESC_CTSENA;
                 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
                 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
-                        sc->vif, pktlen, info));
+                        info->control.vif, pktlen, info));
         }
         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
                 ieee80211_get_hdrlen_from_skb(skb), padsize,
@@ -1391,6 +752,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
 
         spin_lock_bh(&txq->lock);
         list_add_tail(&bf->list, &txq->q);
+        txq->txq_len++;
         if (txq->link == NULL) /* is this first packet? */
                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
         else /* no, so only link it */
@@ -1403,7 +765,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
 
         return 0;
 err_unmap:
-        pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
+        dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
         return ret;
 }
 
@@ -1412,7 +774,7 @@ err_unmap:
 \*******************/
 
 static int
-ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
+ath5k_desc_alloc(struct ath5k_softc *sc)
 {
         struct ath5k_desc *ds;
         struct ath5k_buf *bf;
@@ -1423,7 +785,9 @@ ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
         /* allocate descriptors */
         sc->desc_len = sizeof(struct ath5k_desc) *
                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
-        sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
+
+        sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
+                                &sc->desc_daddr, GFP_KERNEL);
         if (sc->desc == NULL) {
                 ATH5K_ERR(sc, "can't allocate descriptors\n");
                 ret = -ENOMEM;
@@ -1459,44 +823,75 @@ ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
                 list_add_tail(&bf->list, &sc->txbuf);
         }
 
-        /* beacon buffer */
-        bf->desc = ds;
-        bf->daddr = da;
-        sc->bbuf = bf;
+        /* beacon buffers */
+        INIT_LIST_HEAD(&sc->bcbuf);
+        for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
+                bf->desc = ds;
+                bf->daddr = da;
+                list_add_tail(&bf->list, &sc->bcbuf);
+        }
 
         return 0;
 err_free:
-        pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
+        dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
 err:
         sc->desc = NULL;
         return ret;
 }
 
+void
+ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
+{
+        BUG_ON(!bf);
+        if (!bf->skb)
+                return;
+        dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
+                        DMA_TO_DEVICE);
+        dev_kfree_skb_any(bf->skb);
+        bf->skb = NULL;
+        bf->skbaddr = 0;
+        bf->desc->ds_data = 0;
+}
+
+void
+ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
+{
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+
+        BUG_ON(!bf);
+        if (!bf->skb)
+                return;
+        dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
+                        DMA_FROM_DEVICE);
+        dev_kfree_skb_any(bf->skb);
+        bf->skb = NULL;
+        bf->skbaddr = 0;
+        bf->desc->ds_data = 0;
+}
+
 static void
-ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
+ath5k_desc_free(struct ath5k_softc *sc)
 {
         struct ath5k_buf *bf;
 
-        ath5k_txbuf_free_skb(sc, sc->bbuf);
         list_for_each_entry(bf, &sc->txbuf, list)
                 ath5k_txbuf_free_skb(sc, bf);
         list_for_each_entry(bf, &sc->rxbuf, list)
                 ath5k_rxbuf_free_skb(sc, bf);
+        list_for_each_entry(bf, &sc->bcbuf, list)
+                ath5k_txbuf_free_skb(sc, bf);
 
         /* Free memory associated with all descriptors */
-        pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
+        dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
         sc->desc = NULL;
         sc->desc_daddr = 0;
 
         kfree(sc->bufptr);
         sc->bufptr = NULL;
-        sc->bbuf = NULL;
 }
 
 
-
-
-
 /**************\
 * Queues setup *
 \**************/
@@ -1509,16 +904,18 @@ ath5k_txq_setup(struct ath5k_softc *sc,
         struct ath5k_txq *txq;
         struct ath5k_txq_info qi = {
                 .tqi_subtype = subtype,
-                .tqi_aifs = AR5K_TXQ_USEDEFAULT,
-                .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
-                .tqi_cw_max = AR5K_TXQ_USEDEFAULT
+                /* XXX: default values not correct for B and XR channels,
+                 * but who cares? */
+                .tqi_aifs = AR5K_TUNE_AIFS,
+                .tqi_cw_min = AR5K_TUNE_CWMIN,
+                .tqi_cw_max = AR5K_TUNE_CWMAX
         };
         int qnum;
 
         /*
          * Enable interrupts only for EOL and DESC conditions.
          * We mark tx descriptors to receive a DESC interrupt
-         * when a tx queue gets deep; otherwise waiting for the
+         * when a tx queue gets deep; otherwise we wait for the
          * EOL to reap descriptors.  Note that this is done to
          * reduce interrupt load and this only defers reaping
          * descriptors, never transmitting frames.  Aside from
@@ -1550,6 +947,10 @@ ath5k_txq_setup(struct ath5k_softc *sc,
                 INIT_LIST_HEAD(&txq->q);
                 spin_lock_init(&txq->lock);
                 txq->setup = true;
+                txq->txq_len = 0;
+                txq->txq_max = ATH5K_TXQ_LEN_MAX;
+                txq->txq_poll_mark = false;
+                txq->txq_stuck = 0;
         }
         return &sc->txqs[qnum];
 }
@@ -1558,9 +959,11 @@ static int
 ath5k_beaconq_setup(struct ath5k_hw *ah)
 {
         struct ath5k_txq_info qi = {
-                .tqi_aifs = AR5K_TXQ_USEDEFAULT,
-                .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
-                .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
+                /* XXX: default values not correct for B and XR channels,
+                 * but who cares? */
+                .tqi_aifs = AR5K_TUNE_AIFS,
+                .tqi_cw_min = AR5K_TUNE_CWMIN,
+                .tqi_cw_max = AR5K_TUNE_CWMAX,
                 /* NB: for dynamic turbo, don't enable any other interrupts */
                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
         };
@@ -1594,7 +997,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
                  */
                 qi.tqi_aifs = 0;
                 qi.tqi_cw_min = 0;
-                qi.tqi_cw_max = 2 * ah->ah_cw_min;
+                qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
         }
 
         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
@@ -1626,60 +1029,44 @@ err:
         return ret;
 }
 
+/**
+ * ath5k_drain_tx_buffs - Empty tx buffers
+ *
+ * @sc The &struct ath5k_softc
+ *
+ * Empty tx buffers from all queues in preparation
+ * of a reset or during shutdown.
+ *
+ * NB:  this assumes output has been stopped and
+ *      we do not need to block ath5k_tx_tasklet
+ */
 static void
-ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
+ath5k_drain_tx_buffs(struct ath5k_softc *sc)
 {
+        struct ath5k_txq *txq;
         struct ath5k_buf *bf, *bf0;
+        int i;
 
-        /*
-         * NB: this assumes output has been stopped and
-         *     we do not need to block ath5k_tx_tasklet
-         */
-        spin_lock_bh(&txq->lock);
-        list_for_each_entry_safe(bf, bf0, &txq->q, list) {
-                ath5k_debug_printtxbuf(sc, bf);
-
-                ath5k_txbuf_free_skb(sc, bf);
-
-                spin_lock_bh(&sc->txbuflock);
-                list_move_tail(&bf->list, &sc->txbuf);
-                sc->txbuf_len++;
-                spin_unlock_bh(&sc->txbuflock);
-        }
-        txq->link = NULL;
-        spin_unlock_bh(&txq->lock);
-}
+        for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
+                if (sc->txqs[i].setup) {
+                        txq = &sc->txqs[i];
+                        spin_lock_bh(&txq->lock);
+                        list_for_each_entry_safe(bf, bf0, &txq->q, list) {
+                                ath5k_debug_printtxbuf(sc, bf);
 
-/*
- * Drain the transmit queues and reclaim resources.
- */
-static void
-ath5k_txq_cleanup(struct ath5k_softc *sc)
-{
-        struct ath5k_hw *ah = sc->ah;
-        unsigned int i;
+                                ath5k_txbuf_free_skb(sc, bf);
 
-        /* XXX return value */
-        if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
-                /* don't touch the hardware if marked invalid */
-                ath5k_hw_stop_tx_dma(ah, sc->bhalq);
-                ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
-                        ath5k_hw_get_txdp(ah, sc->bhalq));
-                for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
-                        if (sc->txqs[i].setup) {
-                                ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
-                                ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
-                                        "link %p\n",
-                                        sc->txqs[i].qnum,
-                                        ath5k_hw_get_txdp(ah,
-                                                        sc->txqs[i].qnum),
-                                        sc->txqs[i].link);
+                                spin_lock_bh(&sc->txbuflock);
+                                list_move_tail(&bf->list, &sc->txbuf);
+                                sc->txbuf_len++;
+                                txq->txq_len--;
+                                spin_unlock_bh(&sc->txbuflock);
                         }
+                        txq->link = NULL;
+                        txq->txq_poll_mark = false;
+                        spin_unlock_bh(&txq->lock);
+                }
         }
-
-        for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
-                if (sc->txqs[i].setup)
-                        ath5k_txq_drainq(sc, &sc->txqs[i]);
 }
 
 static void
@@ -1696,8 +1083,6 @@ ath5k_txq_release(struct ath5k_softc *sc)
 }
 
 
-
-
 /*************\
 * RX Handling *
 \*************/
@@ -1713,7 +1098,7 @@ ath5k_rx_start(struct ath5k_softc *sc)
         struct ath5k_buf *bf;
         int ret;
 
-        common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
+        common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
 
         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
                   common->cachelsz, common->rx_bufsize);
@@ -1732,7 +1117,7 @@ ath5k_rx_start(struct ath5k_softc *sc)
         spin_unlock_bh(&sc->rxbuflock);
 
         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
-        ath5k_mode_setup(sc);           /* set filters, etc. */
+        ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
 
         return 0;
@@ -1741,16 +1126,19 @@ err:
 }
 
 /*
- * Disable the receive h/w in preparation for a reset.
+ * Disable the receive logic on PCU (DRU)
+ * In preparation for a shutdown.
+ *
+ * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
+ * does.
  */
 static void
 ath5k_rx_stop(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
 
-        ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
-        ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
+        ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
 
         ath5k_debug_printrxbuffs(sc, ah);
 }
@@ -1840,6 +1228,15 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
                  */
                 if (hw_tu >= sc->nexttbtt)
                         ath5k_beacon_update_timers(sc, bc_tstamp);
+
+                /* Check if the beacon timers are still correct, because a TSF
+                 * update might have created a window between them - for a
+                 * longer description see the comment of this function: */
+                if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
+                        ath5k_beacon_update_timers(sc, bc_tstamp);
+                        ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
+                                "fixed beacon timers after beacon receive\n");
+                }
         }
 }
 
@@ -1855,15 +1252,14 @@ ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
             memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
                 return;
 
-        ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
-                                                      rssi);
+        ewma_add(&ah->ah_beacon_rssi_avg, rssi);
 
         /* in IBSS mode we should keep RSSI statistics per neighbour */
         /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
 }
 
 /*
- * Compute padding position. skb must contains an IEEE 802.11 frame
+ * Compute padding position. skb must contain an IEEE 802.11 frame
  */
 static int ath5k_common_padpos(struct sk_buff *skb)
 {
@@ -1882,10 +1278,9 @@ static int ath5k_common_padpos(struct sk_buff *skb)
 }
 
 /*
- * This function expects a 802.11 frame and returns the number of
- * bytes added, or -1 if we don't have enought header room.
+ * This function expects an 802.11 frame and returns the number of
+ * bytes added, or -1 if we don't have enough header room.
  */
-
 static int ath5k_add_padding(struct sk_buff *skb)
 {
         int padpos = ath5k_common_padpos(skb);
@@ -1905,10 +1300,18 @@ static int ath5k_add_padding(struct sk_buff *skb)
 }
 
 /*
- * This function expects a 802.11 frame and returns the number of
- * bytes removed
+ * The MAC header is padded to have 32-bit boundary if the
+ * packet payload is non-zero. The general calculation for
+ * padsize would take into account odd header lengths:
+ * padsize = 4 - (hdrlen & 3); however, since only
+ * even-length headers are used, padding can only be 0 or 2
+ * bytes and we can optimize this a bit.  We must not try to
+ * remove padding from short control frames that do not have a
+ * payload.
+ *
+ * This function expects an 802.11 frame and returns the number of
+ * bytes removed.
  */
-
 static int ath5k_remove_padding(struct sk_buff *skb)
 {
         int padpos = ath5k_common_padpos(skb);
@@ -1929,14 +1332,6 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
 {
         struct ieee80211_rx_status *rxs;
 
-        /* The MAC header is padded to have 32-bit boundary if the
-         * packet payload is non-zero. The general calculation for
-         * padsize would take into account odd header lengths:
-         * padsize = (4 - hdrlen % 4) % 4; However, since only
-         * even-length headers are used, padding can only be 0 or 2
-         * bytes and we can optimize this a bit. In addition, we must
-         * not try to remove padding from short control frames that do
-         * not have payload. */
         ath5k_remove_padding(skb);
 
         rxs = IEEE80211_SKB_RXCB(skb);
@@ -1966,10 +1361,10 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
          * right now, so it's not too bad...
          */
         rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
-        rxs->flag |= RX_FLAG_TSFT;
+        rxs->flag |= RX_FLAG_MACTIME_MPDU;
 
         rxs->freq = sc->curchan->center_freq;
-        rxs->band = sc->curband->band;
+        rxs->band = sc->curchan->band;
 
         rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
 
@@ -1984,10 +1379,10 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
         rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
 
         if (rxs->rate_idx >= 0 && rs->rs_rate ==
-            sc->curband->bitrates[rxs->rate_idx].hw_value_short)
+            sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
                 rxs->flag |= RX_FLAG_SHORTPRE;
 
-        ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
+        trace_ath5k_rx(sc, skb);
 
         ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
 
@@ -2007,6 +1402,7 @@ static bool
 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
 {
         sc->stats.rx_all_count++;
+        sc->stats.rx_bytes_count += rs->rs_datalen;
 
         if (unlikely(rs->rs_status)) {
                 if (rs->rs_status & AR5K_RXERR_CRC)
@@ -2040,9 +1436,8 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
                         return true;
                 }
 
-                /* let crypto-error packets fall through in MNTR */
-                if ((rs->rs_status & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
-                    sc->opmode != NL80211_IFTYPE_MONITOR)
+                /* reject any frames with non-crypto errors */
+                if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
                         return false;
         }
 
@@ -2054,6 +1449,21 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
 }
 
 static void
+ath5k_set_current_imask(struct ath5k_softc *sc)
+{
+        enum ath5k_int imask = sc->imask;
+        unsigned long flags;
+
+        spin_lock_irqsave(&sc->irqlock, flags);
+        if (sc->rx_pending)
+                imask &= ~AR5K_INT_RX_ALL;
+        if (sc->tx_pending)
+                imask &= ~AR5K_INT_TX_ALL;
+        ath5k_hw_set_imr(sc->ah, imask);
+        spin_unlock_irqrestore(&sc->irqlock, flags);
+}
+
+static void
 ath5k_tasklet_rx(unsigned long data)
 {
         struct ath5k_rx_status rs = {};
@@ -2100,9 +1510,9 @@ ath5k_tasklet_rx(unsigned long data)
                         if (!next_skb)
                                 goto next;
 
-                        pci_unmap_single(sc->pdev, bf->skbaddr,
+                        dma_unmap_single(sc->dev, bf->skbaddr,
                                          common->rx_bufsize,
-                                         PCI_DMA_FROMDEVICE);
+                                         DMA_FROM_DEVICE);
 
                         skb_put(skb, rs.rs_datalen);
 
@@ -2116,6 +1526,8 @@ next:
         } while (ath5k_rxbuf_setup(sc, bf) == 0);
 unlock:
         spin_unlock(&sc->rxbuflock);
+        sc->rx_pending = false;
+        ath5k_set_current_imask(sc);
 }
 
 
@@ -2123,6 +1535,122 @@ unlock:
 * TX Handling *
 \*************/
 
+void
+ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
+               struct ath5k_txq *txq)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_buf *bf;
+        unsigned long flags;
+        int padsize;
+
+        trace_ath5k_tx(sc, skb, txq);
+
+        /*
+         * The hardware expects the header padded to 4 byte boundaries.
+         * If this is not the case, we add the padding after the header.
+         */
+        padsize = ath5k_add_padding(skb);
+        if (padsize < 0) {
+                ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
+                          " headroom to pad");
+                goto drop_packet;
+        }
+
+        if (txq->txq_len >= txq->txq_max)
+                ieee80211_stop_queue(hw, txq->qnum);
+
+        spin_lock_irqsave(&sc->txbuflock, flags);
+        if (list_empty(&sc->txbuf)) {
+                ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
+                spin_unlock_irqrestore(&sc->txbuflock, flags);
+                ieee80211_stop_queues(hw);
+                goto drop_packet;
+        }
+        bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
+        list_del(&bf->list);
+        sc->txbuf_len--;
+        if (list_empty(&sc->txbuf))
+                ieee80211_stop_queues(hw);
+        spin_unlock_irqrestore(&sc->txbuflock, flags);
+
+        bf->skb = skb;
+
+        if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
+                bf->skb = NULL;
+                spin_lock_irqsave(&sc->txbuflock, flags);
+                list_add_tail(&bf->list, &sc->txbuf);
+                sc->txbuf_len++;
+                spin_unlock_irqrestore(&sc->txbuflock, flags);
+                goto drop_packet;
+        }
+        return;
+
+drop_packet:
+        dev_kfree_skb_any(skb);
+}
+
+static void
+ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
+                         struct ath5k_txq *txq, struct ath5k_tx_status *ts)
+{
+        struct ieee80211_tx_info *info;
+        u8 tries[3];
+        int i;
+
+        sc->stats.tx_all_count++;
+        sc->stats.tx_bytes_count += skb->len;
+        info = IEEE80211_SKB_CB(skb);
+
+        tries[0] = info->status.rates[0].count;
+        tries[1] = info->status.rates[1].count;
+        tries[2] = info->status.rates[2].count;
+
+        ieee80211_tx_info_clear_status(info);
+
+        for (i = 0; i < ts->ts_final_idx; i++) {
+                struct ieee80211_tx_rate *r =
+                        &info->status.rates[i];
+
+                r->count = tries[i];
+        }
+
+        info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
+        info->status.rates[ts->ts_final_idx + 1].idx = -1;
+
+        if (unlikely(ts->ts_status)) {
+                sc->stats.ack_fail++;
+                if (ts->ts_status & AR5K_TXERR_FILT) {
+                        info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
+                        sc->stats.txerr_filt++;
+                }
+                if (ts->ts_status & AR5K_TXERR_XRETRY)
+                        sc->stats.txerr_retry++;
+                if (ts->ts_status & AR5K_TXERR_FIFO)
+                        sc->stats.txerr_fifo++;
+        } else {
+                info->flags |= IEEE80211_TX_STAT_ACK;
+                info->status.ack_signal = ts->ts_rssi;
+
+                /* count the successful attempt as well */
+                info->status.rates[ts->ts_final_idx].count++;
+        }
+
+        /*
+        * Remove MAC header padding before giving the frame
+        * back to mac80211.
+        */
+        ath5k_remove_padding(skb);
+
+        if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
+                sc->stats.antenna_tx[ts->ts_antenna]++;
+        else
+                sc->stats.antenna_tx[0]++; /* invalid */
+
+        trace_ath5k_tx_complete(sc, skb, txq, ts);
+        ieee80211_tx_status(sc->hw, skb);
+}
+
 static void
 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
 {
@@ -2130,96 +1658,52 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
         struct ath5k_buf *bf, *bf0;
         struct ath5k_desc *ds;
         struct sk_buff *skb;
-        struct ieee80211_tx_info *info;
-        int i, ret;
+        int ret;
 
         spin_lock(&txq->lock);
         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
-                ds = bf->desc;
-
-                /*
-                 * It's possible that the hardware can say the buffer is
-                 * completed when it hasn't yet loaded the ds_link from
-                 * host memory and moved on.  If there are more TX
-                 * descriptors in the queue, wait for TXDP to change
-                 * before processing this one.
-                 */
-                if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
-                    !list_is_last(&bf->list, &txq->q))
-                        break;
-
-                ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
-                if (unlikely(ret == -EINPROGRESS))
-                        break;
-                else if (unlikely(ret)) {
-                        ATH5K_ERR(sc, "error %d while processing queue %u\n",
-                                ret, txq->qnum);
-                        break;
-                }
-
-                sc->stats.tx_all_count++;
-                skb = bf->skb;
-                info = IEEE80211_SKB_CB(skb);
-                bf->skb = NULL;
 
-                pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
-                                PCI_DMA_TODEVICE);
+                txq->txq_poll_mark = false;
 
-                ieee80211_tx_info_clear_status(info);
-                for (i = 0; i < 4; i++) {
-                        struct ieee80211_tx_rate *r =
-                                &info->status.rates[i];
+                /* skb might already have been processed last time. */
+                if (bf->skb != NULL) {
+                        ds = bf->desc;
 
-                        if (ts.ts_rate[i]) {
-                                r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
-                                r->count = ts.ts_retry[i];
-                        } else {
-                                r->idx = -1;
-                                r->count = 0;
+                        ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
+                        if (unlikely(ret == -EINPROGRESS))
+                                break;
+                        else if (unlikely(ret)) {
+                                ATH5K_ERR(sc,
+                                        "error %d while processing "
+                                        "queue %u\n", ret, txq->qnum);
+                                break;
                         }
-                }
 
-                /* count the successful attempt as well */
-                info->status.rates[ts.ts_final_idx].count++;
+                        skb = bf->skb;
+                        bf->skb = NULL;
 
-                if (unlikely(ts.ts_status)) {
-                        sc->stats.ack_fail++;
-                        if (ts.ts_status & AR5K_TXERR_FILT) {
-                                info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
-                                sc->stats.txerr_filt++;
-                        }
-                        if (ts.ts_status & AR5K_TXERR_XRETRY)
-                                sc->stats.txerr_retry++;
-                        if (ts.ts_status & AR5K_TXERR_FIFO)
-                                sc->stats.txerr_fifo++;
-                } else {
-                        info->flags |= IEEE80211_TX_STAT_ACK;
-                        info->status.ack_signal = ts.ts_rssi;
+                        dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
+                                        DMA_TO_DEVICE);
+                        ath5k_tx_frame_completed(sc, skb, txq, &ts);
                 }
 
                 /*
-                 * Remove MAC header padding before giving the frame
-                 * back to mac80211.
+                 * It's possible that the hardware can say the buffer is
+                 * completed when it hasn't yet loaded the ds_link from
+                 * host memory and moved on.
+                 * Always keep the last descriptor to avoid HW races...
                  */
-                ath5k_remove_padding(skb);
-
-                if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
-                        sc->stats.antenna_tx[ts.ts_antenna]++;
-                else
-                        sc->stats.antenna_tx[0]++; /* invalid */
-
-                ieee80211_tx_status(sc->hw, skb);
-
-                spin_lock(&sc->txbuflock);
-                list_move_tail(&bf->list, &sc->txbuf);
-                sc->txbuf_len++;
-                spin_unlock(&sc->txbuflock);
+                if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
+                        spin_lock(&sc->txbuflock);
+                        list_move_tail(&bf->list, &sc->txbuf);
+                        sc->txbuf_len++;
+                        txq->txq_len--;
+                        spin_unlock(&sc->txbuflock);
+                }
         }
-        if (likely(list_empty(&txq->q)))
-                txq->link = NULL;
         spin_unlock(&txq->lock);
-        if (sc->txbuf_len > ATH_TXBUF / 5)
-                ieee80211_wake_queues(sc->hw);
+        if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
+                ieee80211_wake_queue(sc->hw, txq->qnum);
 }
 
 static void
@@ -2231,6 +1715,9 @@ ath5k_tasklet_tx(unsigned long data)
         for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
                 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
                         ath5k_tx_processq(sc, &sc->txqs[i]);
+
+        sc->tx_pending = false;
+        ath5k_set_current_imask(sc);
 }
 
 
@@ -2253,12 +1740,13 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
         u32 flags;
         const int padsize = 0;
 
-        bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
-                        PCI_DMA_TODEVICE);
+        bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
+                        DMA_TO_DEVICE);
         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
                         "skbaddr %llx\n", skb, skb->data, skb->len,
                         (unsigned long long)bf->skbaddr);
-        if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
+
+        if (dma_mapping_error(sc->dev, bf->skbaddr)) {
                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
                 return -EIO;
         }
@@ -2285,10 +1773,11 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
          * default antenna which is supposed to be an omni.
          *
          * Note2: On sectored scenarios it's possible to have
-         * multiple antennas (1omni -the default- and 14 sectors)
-         * so if we choose to actually support this mode we need
-         * to allow user to set how many antennas we have and tweak
-         * the code below to send beacons on all of them.
+         * multiple antennas (1 omni -- the default -- and 14
+         * sectors), so if we choose to actually support this
+         * mode, we need to allow the user to set how many antennas
+         * we have and tweak the code below to send beacons
+         * on all of them.
          */
         if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
                 antenna = sc->bsent & 4 ? 2 : 1;
@@ -2309,7 +1798,43 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
 
         return 0;
 err_unmap:
-        pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
+        dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
+        return ret;
+}
+
+/*
+ * Updates the beacon that is sent by ath5k_beacon_send.  For adhoc,
+ * this is called only once at config_bss time, for AP we do it every
+ * SWBA interrupt so that the TIM will reflect buffered frames.
+ *
+ * Called with the beacon lock.
+ */
+int
+ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+        int ret;
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+        struct sk_buff *skb;
+
+        if (WARN_ON(!vif)) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+        skb = ieee80211_beacon_get(hw, vif);
+
+        if (!skb) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        ath5k_txbuf_free_skb(sc, avf->bbuf);
+        avf->bbuf->skb = skb;
+        ret = ath5k_beacon_setup(sc, avf->bbuf);
+        if (ret)
+                avf->bbuf->skb = NULL;
+out:
         return ret;
 }
 
@@ -2324,20 +1849,17 @@ err_unmap:
 static void
 ath5k_beacon_send(struct ath5k_softc *sc)
 {
-        struct ath5k_buf *bf = sc->bbuf;
         struct ath5k_hw *ah = sc->ah;
+        struct ieee80211_vif *vif;
+        struct ath5k_vif *avf;
+        struct ath5k_buf *bf;
         struct sk_buff *skb;
 
         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
 
-        if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
-                        sc->opmode == NL80211_IFTYPE_MONITOR)) {
-                ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
-                return;
-        }
         /*
          * Check if the previous beacon has gone out.  If
-         * not don't don't try to post another, skip this
+         * not, don't don't try to post another: skip this
          * period and wait for the next.  Missed beacons
          * indicate a problem and should not occur.  If we
          * miss too many consecutive beacons reset the device.
@@ -2363,35 +1885,60 @@ ath5k_beacon_send(struct ath5k_softc *sc)
                 sc->bmisscount = 0;
         }
 
+        if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
+                        sc->opmode == NL80211_IFTYPE_MESH_POINT) {
+                u64 tsf = ath5k_hw_get_tsf64(ah);
+                u32 tsftu = TSF_TO_TU(tsf);
+                int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
+                vif = sc->bslot[(slot + 1) % ATH_BCBUF];
+                ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
+                        "tsf %llx tsftu %x intval %u slot %u vif %p\n",
+                        (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
+        } else /* only one interface */
+                vif = sc->bslot[0];
+
+        if (!vif)
+                return;
+
+        avf = (void *)vif->drv_priv;
+        bf = avf->bbuf;
+        if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
+                        sc->opmode == NL80211_IFTYPE_MONITOR)) {
+                ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
+                return;
+        }
+
         /*
          * Stop any current dma and put the new frame on the queue.
          * This should never fail since we check above that no frames
          * are still pending on the queue.
          */
-        if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
+        if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
                 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
                 /* NB: hw still stops DMA, so proceed */
         }
 
-        /* refresh the beacon for AP mode */
-        if (sc->opmode == NL80211_IFTYPE_AP)
-                ath5k_beacon_update(sc->hw, sc->vif);
+        /* refresh the beacon for AP or MESH mode */
+        if (sc->opmode == NL80211_IFTYPE_AP ||
+                        sc->opmode == NL80211_IFTYPE_MESH_POINT)
+                ath5k_beacon_update(sc->hw, vif);
+
+        trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
 
         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
         ath5k_hw_start_tx_dma(ah, sc->bhalq);
         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
 
-        skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
+        skb = ieee80211_get_buffered_bc(sc->hw, vif);
         while (skb) {
                 ath5k_tx_queue(sc->hw, skb, sc->cabq);
-                skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
+                skb = ieee80211_get_buffered_bc(sc->hw, vif);
         }
 
         sc->bsent++;
 }
 
-
 /**
  * ath5k_beacon_update_timers - update beacon timers
  *
@@ -2408,7 +1955,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
  * when we otherwise know we have to update the timers, but we keep it in this
  * function to have it all together in one place.
  */
-static void
+void
 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
 {
         struct ath5k_hw *ah = sc->ah;
@@ -2416,6 +1963,12 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
         u64 hw_tsf;
 
         intval = sc->bintval & AR5K_BEACON_PERIOD;
+        if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
+                intval /= ATH_BCBUF;    /* staggered multi-bss beacons */
+                if (intval < 15)
+                        ATH5K_WARN(sc, "intval %u is too low, min 15\n",
+                                   intval);
+        }
         if (WARN_ON(!intval))
                 return;
 
@@ -2426,8 +1979,11 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
         hw_tsf = ath5k_hw_get_tsf64(ah);
         hw_tu = TSF_TO_TU(hw_tsf);
 
-#define FUDGE 3
-        /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
+#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
+        /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
+         * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
+         * configuration we need to make sure it is bigger than that. */
+
         if (bc_tsf == -1) {
                 /*
                  * no beacons received, called internally.
@@ -2443,7 +1999,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
                 intval |= AR5K_BEACON_RESET_TSF;
         } else if (bc_tsf > hw_tsf) {
                 /*
-                 * beacon received, SW merge happend but HW TSF not yet updated.
+                 * beacon received, SW merge happened but HW TSF not yet updated.
                  * not possible to reconfigure timers yet, but next time we
                  * receive a beacon with the same BSSID, the hardware will
                  * automatically update the TSF and then we need to reconfigure
@@ -2493,7 +2049,6 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
 }
 
-
 /**
  * ath5k_beacon_config - Configure the beacon queues and interrupts
  *
@@ -2502,7 +2057,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
  * interrupts to detect TSF updates only.
  */
-static void
+void
 ath5k_beacon_config(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
@@ -2530,7 +2085,7 @@ ath5k_beacon_config(struct ath5k_softc *sc)
                 } else
                         ath5k_beacon_update_timers(sc, -1);
         } else {
-                ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
+                ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
         }
 
         ath5k_hw_set_imr(ah, sc->imask);
@@ -2572,155 +2127,6 @@ static void ath5k_tasklet_beacon(unsigned long data)
 * Interrupt handling *
 \********************/
 
-static int
-ath5k_init(struct ath5k_softc *sc)
-{
-        struct ath5k_hw *ah = sc->ah;
-        int ret, i;
-
-        mutex_lock(&sc->lock);
-
-        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
-
-        /*
-         * Stop anything previously setup.  This is safe
-         * no matter this is the first time through or not.
-         */
-        ath5k_stop_locked(sc);
-
-        /*
-         * The basic interface to setting the hardware in a good
-         * state is ``reset''.  On return the hardware is known to
-         * be powered up and with interrupts disabled.  This must
-         * be followed by initialization of the appropriate bits
-         * and then setup of the interrupt mask.
-         */
-        sc->curchan = sc->hw->conf.channel;
-        sc->curband = &sc->sbands[sc->curchan->band];
-        sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
-                AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
-                AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
-
-        ret = ath5k_reset(sc, NULL);
-        if (ret)
-                goto done;
-
-        ath5k_rfkill_hw_start(ah);
-
-        /*
-         * Reset the key cache since some parts do not reset the
-         * contents on initial power up or resume from suspend.
-         */
-        for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
-                ath5k_hw_reset_key(ah, i);
-
-        ath5k_hw_set_ack_bitrate_high(ah, true);
-        ret = 0;
-done:
-        mmiowb();
-        mutex_unlock(&sc->lock);
-        return ret;
-}
-
-static int
-ath5k_stop_locked(struct ath5k_softc *sc)
-{
-        struct ath5k_hw *ah = sc->ah;
-
-        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
-                        test_bit(ATH_STAT_INVALID, sc->status));
-
-        /*
-         * Shutdown the hardware and driver:
-         *    stop output from above
-         *    disable interrupts
-         *    turn off timers
-         *    turn off the radio
-         *    clear transmit machinery
-         *    clear receive machinery
-         *    drain and release tx queues
-         *    reclaim beacon resources
-         *    power down hardware
-         *
-         * Note that some of this work is not possible if the
-         * hardware is gone (invalid).
-         */
-        ieee80211_stop_queues(sc->hw);
-
-        if (!test_bit(ATH_STAT_INVALID, sc->status)) {
-                ath5k_led_off(sc);
-                ath5k_hw_set_imr(ah, 0);
-                synchronize_irq(sc->pdev->irq);
-        }
-        ath5k_txq_cleanup(sc);
-        if (!test_bit(ATH_STAT_INVALID, sc->status)) {
-                ath5k_rx_stop(sc);
-                ath5k_hw_phy_disable(ah);
-        }
-
-        return 0;
-}
-
-static void stop_tasklets(struct ath5k_softc *sc)
-{
-        tasklet_kill(&sc->rxtq);
-        tasklet_kill(&sc->txtq);
-        tasklet_kill(&sc->calib);
-        tasklet_kill(&sc->beacontq);
-        tasklet_kill(&sc->ani_tasklet);
-}
-
-/*
- * Stop the device, grabbing the top-level lock to protect
- * against concurrent entry through ath5k_init (which can happen
- * if another thread does a system call and the thread doing the
- * stop is preempted).
- */
-static int
-ath5k_stop_hw(struct ath5k_softc *sc)
-{
-        int ret;
-
-        mutex_lock(&sc->lock);
-        ret = ath5k_stop_locked(sc);
-        if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
-                /*
-                 * Don't set the card in full sleep mode!
-                 *
-                 * a) When the device is in this state it must be carefully
-                 * woken up or references to registers in the PCI clock
-                 * domain may freeze the bus (and system).  This varies
-                 * by chip and is mostly an issue with newer parts
-                 * (madwifi sources mentioned srev >= 0x78) that go to
-                 * sleep more quickly.
-                 *
-                 * b) On older chips full sleep results a weird behaviour
-                 * during wakeup. I tested various cards with srev < 0x78
-                 * and they don't wake up after module reload, a second
-                 * module reload is needed to bring the card up again.
-                 *
-                 * Until we figure out what's going on don't enable
-                 * full chip reset on any chip (this is what Legacy HAL
-                 * and Sam's HAL do anyway). Instead Perform a full reset
-                 * on the device (same as initial state after attach) and
-                 * leave it idle (keep MAC/BB on warm reset) */
-                ret = ath5k_hw_on_hold(sc->ah);
-
-                ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
-                                "putting device to sleep\n");
-        }
-        ath5k_txbuf_free_skb(sc, sc->bbuf);
-
-        mmiowb();
-        mutex_unlock(&sc->lock);
-
-        stop_tasklets(sc);
-
-        ath5k_rfkill_hw_stop(sc->ah);
-
-        return ret;
-}
-
 static void
 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
 {
@@ -2741,7 +2147,21 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
          * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
 }
 
-static irqreturn_t
+static void
+ath5k_schedule_rx(struct ath5k_softc *sc)
+{
+        sc->rx_pending = true;
+        tasklet_schedule(&sc->rxtq);
+}
+
+static void
+ath5k_schedule_tx(struct ath5k_softc *sc)
+{
+        sc->tx_pending = true;
+        tasklet_schedule(&sc->txtq);
+}
+
+irqreturn_t
 ath5k_intr(int irq, void *dev_id)
 {
         struct ath5k_softc *sc = dev_id;
@@ -2750,7 +2170,8 @@ ath5k_intr(int irq, void *dev_id)
         unsigned int counter = 1000;
 
         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
-                                !ath5k_hw_is_intr_pending(ah)))
+                ((ath5k_get_bus_type(ah) != ATH_AHB) &&
+                                !ath5k_hw_is_intr_pending(ah))))
                 return IRQ_NONE;
 
         do {
@@ -2782,7 +2203,7 @@ ath5k_intr(int irq, void *dev_id)
                                 ieee80211_queue_work(sc->hw, &sc->reset_work);
                         }
                         else
-                                tasklet_schedule(&sc->rxtq);
+                                ath5k_schedule_rx(sc);
                 } else {
                         if (status & AR5K_INT_SWBA) {
                                 tasklet_hi_schedule(&sc->beacontq);
@@ -2800,10 +2221,10 @@ ath5k_intr(int irq, void *dev_id)
                                 ath5k_hw_update_tx_triglevel(ah, true);
                         }
                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
-                                tasklet_schedule(&sc->rxtq);
+                                ath5k_schedule_rx(sc);
                         if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
                                         | AR5K_INT_TXERR | AR5K_INT_TXEOL))
-                                tasklet_schedule(&sc->txtq);
+                                ath5k_schedule_tx(sc);
                         if (status & AR5K_INT_BMISS) {
                                 /* TODO */
                         }
@@ -2816,8 +2237,15 @@ ath5k_intr(int irq, void *dev_id)
                                 tasklet_schedule(&sc->rf_kill.toggleq);
 
                 }
+
+                if (ath5k_get_bus_type(ah) == ATH_AHB)
+                        break;
+
         } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
 
+        if (sc->rx_pending || sc->tx_pending)
+                ath5k_set_current_imask(sc);
+
         if (unlikely(!counter))
                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
 
@@ -2857,14 +2285,13 @@ ath5k_tasklet_calibrate(unsigned long data)
                                 sc->curchan->center_freq));
 
         /* Noise floor calibration interrupts rx/tx path while I/Q calibration
-         * doesn't. We stop the queues so that calibration doesn't interfere
-         * with TX and don't run it as often */
+         * doesn't.
+         * TODO: We should stop TX here, so that it doesn't interfere.
+         * Note that stopping the queues is not enough to stop TX! */
         if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
                 ah->ah_cal_next_nf = jiffies +
                         msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
-                ieee80211_stop_queues(sc->hw);
                 ath5k_hw_update_noise_floor(ah);
-                ieee80211_wake_queues(sc->hw);
         }
 
         ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
@@ -2883,570 +2310,676 @@ ath5k_tasklet_ani(unsigned long data)
 }
 
 
-/********************\
-* Mac80211 functions *
-\********************/
-
-static int
-ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        return ath5k_tx_queue(hw, skb, sc->txq);
-}
-
-static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
-                          struct ath5k_txq *txq)
+static void
+ath5k_tx_complete_poll_work(struct work_struct *work)
 {
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_buf *bf;
-        unsigned long flags;
-        int padsize;
-
-        ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
+        struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
+                        tx_complete_work.work);
+        struct ath5k_txq *txq;
+        int i;
+        bool needreset = false;
 
-        if (sc->opmode == NL80211_IFTYPE_MONITOR)
-                ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
+        mutex_lock(&sc->lock);
 
-        /*
-         * the hardware expects the header padded to 4 byte boundaries
-         * if this is not the case we add the padding after the header
-         */
-        padsize = ath5k_add_padding(skb);
-        if (padsize < 0) {
-                ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
-                          " headroom to pad");
-                goto drop_packet;
+        for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
+                if (sc->txqs[i].setup) {
+                        txq = &sc->txqs[i];
+                        spin_lock_bh(&txq->lock);
+                        if (txq->txq_len > 1) {
+                                if (txq->txq_poll_mark) {
+                                        ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
+                                                  "TX queue stuck %d\n",
+                                                  txq->qnum);
+                                        needreset = true;
+                                        txq->txq_stuck++;
+                                        spin_unlock_bh(&txq->lock);
+                                        break;
+                                } else {
+                                        txq->txq_poll_mark = true;
+                                }
+                        }
+                        spin_unlock_bh(&txq->lock);
+                }
         }
 
-        spin_lock_irqsave(&sc->txbuflock, flags);
-        if (list_empty(&sc->txbuf)) {
-                ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
-                spin_unlock_irqrestore(&sc->txbuflock, flags);
-                ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
-                goto drop_packet;
+        if (needreset) {
+                ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
+                          "TX queues stuck, resetting\n");
+                ath5k_reset(sc, NULL, true);
         }
-        bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
-        list_del(&bf->list);
-        sc->txbuf_len--;
-        if (list_empty(&sc->txbuf))
-                ieee80211_stop_queues(hw);
-        spin_unlock_irqrestore(&sc->txbuflock, flags);
-
-        bf->skb = skb;
 
-        if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
-                bf->skb = NULL;
-                spin_lock_irqsave(&sc->txbuflock, flags);
-                list_add_tail(&bf->list, &sc->txbuf);
-                sc->txbuf_len++;
-                spin_unlock_irqrestore(&sc->txbuflock, flags);
-                goto drop_packet;
-        }
-        return NETDEV_TX_OK;
+        mutex_unlock(&sc->lock);
 
-drop_packet:
-        dev_kfree_skb_any(skb);
-        return NETDEV_TX_OK;
+        ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
+                msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
 }
 
-/*
- * Reset the hardware.  If chan is not NULL, then also pause rx/tx
- * and change to the given channel.
- *
- * This should be called with sc->lock.
- */
-static int
-ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
+
+/*************************\
+* Initialization routines *
+\*************************/
+
+int
+ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
 {
-        struct ath5k_hw *ah = sc->ah;
+        struct ieee80211_hw *hw = sc->hw;
+        struct ath_common *common;
         int ret;
+        int csz;
 
-        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
+        /* Initialize driver private data */
+        SET_IEEE80211_DEV(hw, sc->dev);
+        hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
+                        IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
+                        IEEE80211_HW_SIGNAL_DBM |
+                        IEEE80211_HW_REPORTS_TX_ACK_STATUS;
 
-        ath5k_hw_set_imr(ah, 0);
-        synchronize_irq(sc->pdev->irq);
-        stop_tasklets(sc);
+        hw->wiphy->interface_modes =
+                BIT(NL80211_IFTYPE_AP) |
+                BIT(NL80211_IFTYPE_STATION) |
+                BIT(NL80211_IFTYPE_ADHOC) |
+                BIT(NL80211_IFTYPE_MESH_POINT);
 
-        if (chan) {
-                ath5k_txq_cleanup(sc);
-                ath5k_rx_stop(sc);
+        /* both antennas can be configured as RX or TX */
+        hw->wiphy->available_antennas_tx = 0x3;
+        hw->wiphy->available_antennas_rx = 0x3;
 
-                sc->curchan = chan;
-                sc->curband = &sc->sbands[chan->band];
-        }
-        ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
-        if (ret) {
-                ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
-                goto err;
-        }
+        hw->extra_tx_headroom = 2;
+        hw->channel_change_time = 5000;
 
-        ret = ath5k_rx_start(sc);
+        /*
+         * Mark the device as detached to avoid processing
+         * interrupts until setup is complete.
+         */
+        __set_bit(ATH_STAT_INVALID, sc->status);
+
+        sc->opmode = NL80211_IFTYPE_STATION;
+        sc->bintval = 1000;
+        mutex_init(&sc->lock);
+        spin_lock_init(&sc->rxbuflock);
+        spin_lock_init(&sc->txbuflock);
+        spin_lock_init(&sc->block);
+        spin_lock_init(&sc->irqlock);
+
+        /* Setup interrupt handler */
+        ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
         if (ret) {
-                ATH5K_ERR(sc, "can't start recv logic\n");
+                ATH5K_ERR(sc, "request_irq failed\n");
                 goto err;
         }
 
-        ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
+        /* If we passed the test, malloc an ath5k_hw struct */
+        sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
+        if (!sc->ah) {
+                ret = -ENOMEM;
+                ATH5K_ERR(sc, "out of memory\n");
+                goto err_irq;
+        }
 
-        ah->ah_cal_next_full = jiffies;
-        ah->ah_cal_next_ani = jiffies;
-        ah->ah_cal_next_nf = jiffies;
+        sc->ah->ah_sc = sc;
+        sc->ah->ah_iobase = sc->iobase;
+        common = ath5k_hw_common(sc->ah);
+        common->ops = &ath5k_common_ops;
+        common->bus_ops = bus_ops;
+        common->ah = sc->ah;
+        common->hw = hw;
+        common->priv = sc;
 
         /*
-         * Change channels and update the h/w rate map if we're switching;
-         * e.g. 11a to 11b/g.
-         *
-         * We may be doing a reset in response to an ioctl that changes the
-         * channel so update any state that might change as a result.
-         *
-         * XXX needed?
+         * Cache line size is used to size and align various
+         * structures used to communicate with the hardware.
          */
-/*      ath5k_chan_change(sc, c); */
+        ath5k_read_cachesize(common, &csz);
+        common->cachelsz = csz << 2; /* convert to bytes */
 
-        ath5k_beacon_config(sc);
-        /* intrs are enabled by ath5k_beacon_config */
+        spin_lock_init(&common->cc_lock);
 
-        ieee80211_wake_queues(sc->hw);
+        /* Initialize device */
+        ret = ath5k_hw_init(sc);
+        if (ret)
+                goto err_free_ah;
+
+        /* set up multi-rate retry capabilities */
+        if (sc->ah->ah_version == AR5K_AR5212) {
+                hw->max_rates = 4;
+                hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
+                                         AR5K_INIT_RETRY_LONG);
+        }
+
+        hw->vif_data_size = sizeof(struct ath5k_vif);
+
+        /* Finish private driver data initialization */
+        ret = ath5k_init(hw);
+        if (ret)
+                goto err_ah;
+
+        ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
+                        ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
+                                        sc->ah->ah_mac_srev,
+                                        sc->ah->ah_phy_revision);
+
+        if (!sc->ah->ah_single_chip) {
+                /* Single chip radio (!RF5111) */
+                if (sc->ah->ah_radio_5ghz_revision &&
+                        !sc->ah->ah_radio_2ghz_revision) {
+                        /* No 5GHz support -> report 2GHz radio */
+                        if (!test_bit(AR5K_MODE_11A,
+                                sc->ah->ah_capabilities.cap_mode)) {
+                                ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
+                                        ath5k_chip_name(AR5K_VERSION_RAD,
+                                                sc->ah->ah_radio_5ghz_revision),
+                                                sc->ah->ah_radio_5ghz_revision);
+                        /* No 2GHz support (5110 and some
+                         * 5Ghz only cards) -> report 5Ghz radio */
+                        } else if (!test_bit(AR5K_MODE_11B,
+                                sc->ah->ah_capabilities.cap_mode)) {
+                                ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
+                                        ath5k_chip_name(AR5K_VERSION_RAD,
+                                                sc->ah->ah_radio_5ghz_revision),
+                                                sc->ah->ah_radio_5ghz_revision);
+                        /* Multiband radio */
+                        } else {
+                                ATH5K_INFO(sc, "RF%s multiband radio found"
+                                        " (0x%x)\n",
+                                        ath5k_chip_name(AR5K_VERSION_RAD,
+                                                sc->ah->ah_radio_5ghz_revision),
+                                                sc->ah->ah_radio_5ghz_revision);
+                        }
+                }
+                /* Multi chip radio (RF5111 - RF2111) ->
+                 * report both 2GHz/5GHz radios */
+                else if (sc->ah->ah_radio_5ghz_revision &&
+                                sc->ah->ah_radio_2ghz_revision){
+                        ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
+                                ath5k_chip_name(AR5K_VERSION_RAD,
+                                        sc->ah->ah_radio_5ghz_revision),
+                                        sc->ah->ah_radio_5ghz_revision);
+                        ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
+                                ath5k_chip_name(AR5K_VERSION_RAD,
+                                        sc->ah->ah_radio_2ghz_revision),
+                                        sc->ah->ah_radio_2ghz_revision);
+                }
+        }
+
+        ath5k_debug_init_device(sc);
+
+        /* ready to process interrupts */
+        __clear_bit(ATH_STAT_INVALID, sc->status);
 
         return 0;
+err_ah:
+        ath5k_hw_deinit(sc->ah);
+err_free_ah:
+        kfree(sc->ah);
+err_irq:
+        free_irq(sc->irq, sc);
 err:
         return ret;
 }
 
-static void ath5k_reset_work(struct work_struct *work)
+static int
+ath5k_stop_locked(struct ath5k_softc *sc)
 {
-        struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
-                reset_work);
+        struct ath5k_hw *ah = sc->ah;
 
-        mutex_lock(&sc->lock);
-        ath5k_reset(sc, sc->curchan);
-        mutex_unlock(&sc->lock);
-}
+        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
+                        test_bit(ATH_STAT_INVALID, sc->status));
 
-static int ath5k_start(struct ieee80211_hw *hw)
-{
-        return ath5k_init(hw->priv);
-}
+        /*
+         * Shutdown the hardware and driver:
+         *    stop output from above
+         *    disable interrupts
+         *    turn off timers
+         *    turn off the radio
+         *    clear transmit machinery
+         *    clear receive machinery
+         *    drain and release tx queues
+         *    reclaim beacon resources
+         *    power down hardware
+         *
+         * Note that some of this work is not possible if the
+         * hardware is gone (invalid).
+         */
+        ieee80211_stop_queues(sc->hw);
 
-static void ath5k_stop(struct ieee80211_hw *hw)
-{
-        ath5k_stop_hw(hw->priv);
+        if (!test_bit(ATH_STAT_INVALID, sc->status)) {
+                ath5k_led_off(sc);
+                ath5k_hw_set_imr(ah, 0);
+                synchronize_irq(sc->irq);
+                ath5k_rx_stop(sc);
+                ath5k_hw_dma_stop(ah);
+                ath5k_drain_tx_buffs(sc);
+                ath5k_hw_phy_disable(ah);
+        }
+
+        return 0;
 }
 
-static int ath5k_add_interface(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif)
+int
+ath5k_init_hw(struct ath5k_softc *sc)
 {
-        struct ath5k_softc *sc = hw->priv;
-        int ret;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+        int ret, i;
 
         mutex_lock(&sc->lock);
-        if (sc->vif) {
-                ret = 0;
-                goto end;
-        }
 
-        sc->vif = vif;
+        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
 
-        switch (vif->type) {
-        case NL80211_IFTYPE_AP:
-        case NL80211_IFTYPE_STATION:
-        case NL80211_IFTYPE_ADHOC:
-        case NL80211_IFTYPE_MESH_POINT:
-        case NL80211_IFTYPE_MONITOR:
-                sc->opmode = vif->type;
-                break;
-        default:
-                ret = -EOPNOTSUPP;
-                goto end;
-        }
+        /*
+         * Stop anything previously setup.  This is safe
+         * no matter this is the first time through or not.
+         */
+        ath5k_stop_locked(sc);
+
+        /*
+         * The basic interface to setting the hardware in a good
+         * state is ``reset''.  On return the hardware is known to
+         * be powered up and with interrupts disabled.  This must
+         * be followed by initialization of the appropriate bits
+         * and then setup of the interrupt mask.
+         */
+        sc->curchan = sc->hw->conf.channel;
+        sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
+                AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
+                AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
 
-        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
+        ret = ath5k_reset(sc, NULL, false);
+        if (ret)
+                goto done;
 
-        ath5k_hw_set_lladdr(sc->ah, vif->addr);
-        ath5k_mode_setup(sc);
+        ath5k_rfkill_hw_start(ah);
+
+        /*
+         * Reset the key cache since some parts do not reset the
+         * contents on initial power up or resume from suspend.
+         */
+        for (i = 0; i < common->keymax; i++)
+                ath_hw_keyreset(common, (u16) i);
+
+        /* Use higher rates for acks instead of base
+         * rate */
+        ah->ah_ack_bitrate_high = true;
+
+        for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
+                sc->bslot[i] = NULL;
 
         ret = 0;
-end:
+done:
+        mmiowb();
         mutex_unlock(&sc->lock);
+
+        ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
+                        msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
+
         return ret;
 }
 
-static void
-ath5k_remove_interface(struct ieee80211_hw *hw,
-                        struct ieee80211_vif *vif)
+static void stop_tasklets(struct ath5k_softc *sc)
 {
-        struct ath5k_softc *sc = hw->priv;
-        u8 mac[ETH_ALEN] = {};
-
-        mutex_lock(&sc->lock);
-        if (sc->vif != vif)
-                goto end;
-
-        ath5k_hw_set_lladdr(sc->ah, mac);
-        sc->vif = NULL;
-end:
-        mutex_unlock(&sc->lock);
+        sc->rx_pending = false;
+        sc->tx_pending = false;
+        tasklet_kill(&sc->rxtq);
+        tasklet_kill(&sc->txtq);
+        tasklet_kill(&sc->calib);
+        tasklet_kill(&sc->beacontq);
+        tasklet_kill(&sc->ani_tasklet);
 }
 
 /*
- * TODO: Phy disable/diversity etc
+ * Stop the device, grabbing the top-level lock to protect
+ * against concurrent entry through ath5k_init (which can happen
+ * if another thread does a system call and the thread doing the
+ * stop is preempted).
  */
-static int
-ath5k_config(struct ieee80211_hw *hw, u32 changed)
+int
+ath5k_stop_hw(struct ath5k_softc *sc)
 {
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ieee80211_conf *conf = &hw->conf;
-        int ret = 0;
+        int ret;
 
         mutex_lock(&sc->lock);
+        ret = ath5k_stop_locked(sc);
+        if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
+                /*
+                 * Don't set the card in full sleep mode!
+                 *
+                 * a) When the device is in this state it must be carefully
+                 * woken up or references to registers in the PCI clock
+                 * domain may freeze the bus (and system).  This varies
+                 * by chip and is mostly an issue with newer parts
+                 * (madwifi sources mentioned srev >= 0x78) that go to
+                 * sleep more quickly.
+                 *
+                 * b) On older chips full sleep results a weird behaviour
+                 * during wakeup. I tested various cards with srev < 0x78
+                 * and they don't wake up after module reload, a second
+                 * module reload is needed to bring the card up again.
+                 *
+                 * Until we figure out what's going on don't enable
+                 * full chip reset on any chip (this is what Legacy HAL
+                 * and Sam's HAL do anyway). Instead Perform a full reset
+                 * on the device (same as initial state after attach) and
+                 * leave it idle (keep MAC/BB on warm reset) */
+                ret = ath5k_hw_on_hold(sc->ah);
 
-        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
-                ret = ath5k_chan_set(sc, conf->channel);
-                if (ret < 0)
-                        goto unlock;
-        }
-
-        if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
-        (sc->power_level != conf->power_level)) {
-                sc->power_level = conf->power_level;
-
-                /* Half dB steps */
-                ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
+                ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
+                                "putting device to sleep\n");
         }
 
-        /* TODO:
-         * 1) Move this on config_interface and handle each case
-         * separately eg. when we have only one STA vif, use
-         * AR5K_ANTMODE_SINGLE_AP
-         *
-         * 2) Allow the user to change antenna mode eg. when only
-         * one antenna is present
-         *
-         * 3) Allow the user to set default/tx antenna when possible
-         *
-         * 4) Default mode should handle 90% of the cases, together
-         * with fixed a/b and single AP modes we should be able to
-         * handle 99%. Sectored modes are extreme cases and i still
-         * haven't found a usage for them. If we decide to support them,
-         * then we must allow the user to set how many tx antennas we
-         * have available
-         */
-        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
-
-unlock:
+        mmiowb();
         mutex_unlock(&sc->lock);
-        return ret;
-}
 
-static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
-                                   struct netdev_hw_addr_list *mc_list)
-{
-        u32 mfilt[2], val;
-        u8 pos;
-        struct netdev_hw_addr *ha;
+        stop_tasklets(sc);
 
-        mfilt[0] = 0;
-        mfilt[1] = 1;
+        cancel_delayed_work_sync(&sc->tx_complete_work);
 
-        netdev_hw_addr_list_for_each(ha, mc_list) {
-                /* calculate XOR of eight 6-bit values */
-                val = get_unaligned_le32(ha->addr + 0);
-                pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
-                val = get_unaligned_le32(ha->addr + 3);
-                pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
-                pos &= 0x3f;
-                mfilt[pos / 32] |= (1 << (pos % 32));
-                /* XXX: we might be able to just do this instead,
-                * but not sure, needs testing, if we do use this we'd
-                * neet to inform below to not reset the mcast */
-                /* ath5k_hw_set_mcast_filterindex(ah,
-                 *      ha->addr[5]); */
-        }
+        ath5k_rfkill_hw_stop(sc->ah);
 
-        return ((u64)(mfilt[1]) << 32) | mfilt[0];
+        return ret;
 }
 
-#define SUPPORTED_FIF_FLAGS \
-        FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
-        FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
-        FIF_BCN_PRBRESP_PROMISC
 /*
- * o always accept unicast, broadcast, and multicast traffic
- * o multicast traffic for all BSSIDs will be enabled if mac80211
- *   says it should be
- * o maintain current state of phy ofdm or phy cck error reception.
- *   If the hardware detects any of these type of errors then
- *   ath5k_hw_get_rx_filter() will pass to us the respective
- *   hardware filters to be able to receive these type of frames.
- * o probe request frames are accepted only when operating in
- *   hostap, adhoc, or monitor modes
- * o enable promiscuous mode according to the interface state
- * o accept beacons:
- *   - when operating in adhoc mode so the 802.11 layer creates
- *     node table entries for peers,
- *   - when operating in station mode for collecting rssi data when
- *     the station is otherwise quiet, or
- *   - when scanning
+ * Reset the hardware.  If chan is not NULL, then also pause rx/tx
+ * and change to the given channel.
+ *
+ * This should be called with sc->lock.
  */
-static void ath5k_configure_filter(struct ieee80211_hw *hw,
-                unsigned int changed_flags,
-                unsigned int *new_flags,
-                u64 multicast)
+static int
+ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
+                                                        bool skip_pcu)
 {
-        struct ath5k_softc *sc = hw->priv;
         struct ath5k_hw *ah = sc->ah;
-        u32 mfilt[2], rfilt;
+        struct ath_common *common = ath5k_hw_common(ah);
+        int ret, ani_mode;
+        bool fast;
 
-        mutex_lock(&sc->lock);
+        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
 
-        mfilt[0] = multicast;
-        mfilt[1] = multicast >> 32;
+        ath5k_hw_set_imr(ah, 0);
+        synchronize_irq(sc->irq);
+        stop_tasklets(sc);
 
-        /* Only deal with supported flags */
-        changed_flags &= SUPPORTED_FIF_FLAGS;
-        *new_flags &= SUPPORTED_FIF_FLAGS;
+        /* Save ani mode and disable ANI during
+         * reset. If we don't we might get false
+         * PHY error interrupts. */
+        ani_mode = ah->ah_sc->ani_state.ani_mode;
+        ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
+
+        /* We are going to empty hw queues
+         * so we should also free any remaining
+         * tx buffers */
+        ath5k_drain_tx_buffs(sc);
+        if (chan)
+                sc->curchan = chan;
 
-        /* If HW detects any phy or radar errors, leave those filters on.
-         * Also, always enable Unicast, Broadcasts and Multicast
-         * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
-        rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
-                (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
-                AR5K_RX_FILTER_MCAST);
+        fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
 
-        if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
-                if (*new_flags & FIF_PROMISC_IN_BSS) {
-                        __set_bit(ATH_STAT_PROMISC, sc->status);
-                } else {
-                        __clear_bit(ATH_STAT_PROMISC, sc->status);
-                }
+        ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast,
+                                                                skip_pcu);
+        if (ret) {
+                ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
+                goto err;
         }
 
-        if (test_bit(ATH_STAT_PROMISC, sc->status))
-                rfilt |= AR5K_RX_FILTER_PROM;
-
-        /* Note, AR5K_RX_FILTER_MCAST is already enabled */
-        if (*new_flags & FIF_ALLMULTI) {
-                mfilt[0] =  ~0;
-                mfilt[1] =  ~0;
+        ret = ath5k_rx_start(sc);
+        if (ret) {
+                ATH5K_ERR(sc, "can't start recv logic\n");
+                goto err;
         }
 
-        /* This is the best we can do */
-        if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
-                rfilt |= AR5K_RX_FILTER_PHYERR;
+        ath5k_ani_init(ah, ani_mode);
 
-        /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
-        * and probes for any BSSID, this needs testing */
-        if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
-                rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
+        ah->ah_cal_next_full = jiffies;
+        ah->ah_cal_next_ani = jiffies;
+        ah->ah_cal_next_nf = jiffies;
+        ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
 
-        /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
-         * set we should only pass on control frames for this
-         * station. This needs testing. I believe right now this
-         * enables *all* control frames, which is OK.. but
-         * but we should see if we can improve on granularity */
-        if (*new_flags & FIF_CONTROL)
-                rfilt |= AR5K_RX_FILTER_CONTROL;
+        /* clear survey data and cycle counters */
+        memset(&sc->survey, 0, sizeof(sc->survey));
+        spin_lock_bh(&common->cc_lock);
+        ath_hw_cycle_counters_update(common);
+        memset(&common->cc_survey, 0, sizeof(common->cc_survey));
+        memset(&common->cc_ani, 0, sizeof(common->cc_ani));
+        spin_unlock_bh(&common->cc_lock);
 
-        /* Additional settings per mode -- this is per ath5k */
+        /*
+         * Change channels and update the h/w rate map if we're switching;
+         * e.g. 11a to 11b/g.
+         *
+         * We may be doing a reset in response to an ioctl that changes the
+         * channel so update any state that might change as a result.
+         *
+         * XXX needed?
+         */
+/*      ath5k_chan_change(sc, c); */
 
-        /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
+        ath5k_beacon_config(sc);
+        /* intrs are enabled by ath5k_beacon_config */
 
-        switch (sc->opmode) {
-        case NL80211_IFTYPE_MESH_POINT:
-        case NL80211_IFTYPE_MONITOR:
-                rfilt |= AR5K_RX_FILTER_CONTROL |
-                         AR5K_RX_FILTER_BEACON |
-                         AR5K_RX_FILTER_PROBEREQ |
-                         AR5K_RX_FILTER_PROM;
-                break;
-        case NL80211_IFTYPE_AP:
-        case NL80211_IFTYPE_ADHOC:
-                rfilt |= AR5K_RX_FILTER_PROBEREQ |
-                         AR5K_RX_FILTER_BEACON;
-                break;
-        case NL80211_IFTYPE_STATION:
-                if (sc->assoc)
-                        rfilt |= AR5K_RX_FILTER_BEACON;
-        default:
-                break;
-        }
+        ieee80211_wake_queues(sc->hw);
 
-        /* Set filters */
-        ath5k_hw_set_rx_filter(ah, rfilt);
+        return 0;
+err:
+        return ret;
+}
 
-        /* Set multicast bits */
-        ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
-        /* Set the cached hw filter flags, this will alter actually
-         * be set in HW */
-        sc->filter_flags = rfilt;
+static void ath5k_reset_work(struct work_struct *work)
+{
+        struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
+                reset_work);
 
+        mutex_lock(&sc->lock);
+        ath5k_reset(sc, NULL, true);
         mutex_unlock(&sc->lock);
 }
 
 static int
-ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
-              struct ieee80211_vif *vif, struct ieee80211_sta *sta,
-              struct ieee80211_key_conf *key)
+ath5k_init(struct ieee80211_hw *hw)
 {
+
         struct ath5k_softc *sc = hw->priv;
         struct ath5k_hw *ah = sc->ah;
-        struct ath_common *common = ath5k_hw_common(ah);
-        int ret = 0;
+        struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
+        struct ath5k_txq *txq;
+        u8 mac[ETH_ALEN] = {};
+        int ret;
 
-        if (modparam_nohwcrypt)
-                return -EOPNOTSUPP;
 
-        if (sc->opmode == NL80211_IFTYPE_AP)
-                return -EOPNOTSUPP;
+        /*
+         * Check if the MAC has multi-rate retry support.
+         * We do this by trying to setup a fake extended
+         * descriptor.  MACs that don't have support will
+         * return false w/o doing anything.  MACs that do
+         * support it will return true w/o doing anything.
+         */
+        ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 
-        switch (key->alg) {
-        case ALG_WEP:
-        case ALG_TKIP:
-                break;
-        case ALG_CCMP:
-                if (sc->ah->ah_aes_support)
-                        break;
+        if (ret < 0)
+                goto err;
+        if (ret > 0)
+                __set_bit(ATH_STAT_MRRETRY, sc->status);
 
-                return -EOPNOTSUPP;
-        default:
-                WARN_ON(1);
-                return -EINVAL;
+        /*
+         * Collect the channel list.  The 802.11 layer
+         * is resposible for filtering this list based
+         * on settings like the phy mode and regulatory
+         * domain restrictions.
+         */
+        ret = ath5k_setup_bands(hw);
+        if (ret) {
+                ATH5K_ERR(sc, "can't get channels\n");
+                goto err;
         }
 
-        mutex_lock(&sc->lock);
+        /*
+         * Allocate tx+rx descriptors and populate the lists.
+         */
+        ret = ath5k_desc_alloc(sc);
+        if (ret) {
+                ATH5K_ERR(sc, "can't allocate descriptors\n");
+                goto err;
+        }
 
-        switch (cmd) {
-        case SET_KEY:
-                ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
-                                       sta ? sta->addr : NULL);
-                if (ret) {
-                        ATH5K_ERR(sc, "can't set the key\n");
-                        goto unlock;
-                }
-                __set_bit(key->keyidx, common->keymap);
-                key->hw_key_idx = key->keyidx;
-                key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
-                               IEEE80211_KEY_FLAG_GENERATE_MMIC);
-                break;
-        case DISABLE_KEY:
-                ath5k_hw_reset_key(sc->ah, key->keyidx);
-                __clear_bit(key->keyidx, common->keymap);
-                break;
-        default:
-                ret = -EINVAL;
-                goto unlock;
+        /*
+         * Allocate hardware transmit queues: one queue for
+         * beacon frames and one data queue for each QoS
+         * priority.  Note that hw functions handle resetting
+         * these queues at the needed time.
+         */
+        ret = ath5k_beaconq_setup(ah);
+        if (ret < 0) {
+                ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
+                goto err_desc;
+        }
+        sc->bhalq = ret;
+        sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
+        if (IS_ERR(sc->cabq)) {
+                ATH5K_ERR(sc, "can't setup cab queue\n");
+                ret = PTR_ERR(sc->cabq);
+                goto err_bhal;
         }
 
-unlock:
-        mmiowb();
-        mutex_unlock(&sc->lock);
-        return ret;
-}
+        /* 5211 and 5212 usually support 10 queues but we better rely on the
+         * capability information */
+        if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
+                /* This order matches mac80211's queue priority, so we can
+                * directly use the mac80211 queue number without any mapping */
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                hw->queues = 4;
+        } else {
+                /* older hardware (5210) can only support one data queue */
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                hw->queues = 1;
+        }
 
-static int
-ath5k_get_stats(struct ieee80211_hw *hw,
-                struct ieee80211_low_level_stats *stats)
-{
-        struct ath5k_softc *sc = hw->priv;
+        tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
+        tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
+        tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
+        tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
+        tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
 
-        /* Force update */
-        ath5k_hw_update_mib_counters(sc->ah);
+        INIT_WORK(&sc->reset_work, ath5k_reset_work);
+        INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
 
-        stats->dot11ACKFailureCount = sc->stats.ack_fail;
-        stats->dot11RTSFailureCount = sc->stats.rts_fail;
-        stats->dot11RTSSuccessCount = sc->stats.rts_ok;
-        stats->dot11FCSErrorCount = sc->stats.fcs_error;
+        ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
+        if (ret) {
+                ATH5K_ERR(sc, "unable to read address from EEPROM\n");
+                goto err_queues;
+        }
 
-        return 0;
-}
+        SET_IEEE80211_PERM_ADDR(hw, mac);
+        memcpy(&sc->lladdr, mac, ETH_ALEN);
+        /* All MAC address bits matter for ACKs */
+        ath5k_update_bssid_mask_and_opmode(sc, NULL);
 
-static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
-                struct survey_info *survey)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ieee80211_conf *conf = &hw->conf;
+        regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
+        ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
+        if (ret) {
+                ATH5K_ERR(sc, "can't initialize regulatory system\n");
+                goto err_queues;
+        }
 
-         if (idx != 0)
-                return -ENOENT;
+        ret = ieee80211_register_hw(hw);
+        if (ret) {
+                ATH5K_ERR(sc, "can't register ieee80211 hw\n");
+                goto err_queues;
+        }
 
-        survey->channel = conf->channel;
-        survey->filled = SURVEY_INFO_NOISE_DBM;
-        survey->noise = sc->ah->ah_noise_floor;
+        if (!ath_is_world_regd(regulatory))
+                regulatory_hint(hw->wiphy, regulatory->alpha2);
 
-        return 0;
-}
+        ath5k_init_leds(sc);
 
-static u64
-ath5k_get_tsf(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
+        ath5k_sysfs_register(sc);
 
-        return ath5k_hw_get_tsf64(sc->ah);
+        return 0;
+err_queues:
+        ath5k_txq_release(sc);
+err_bhal:
+        ath5k_hw_release_tx_queue(ah, sc->bhalq);
+err_desc:
+        ath5k_desc_free(sc);
+err:
+        return ret;
 }
 
-static void
-ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
+void
+ath5k_deinit_softc(struct ath5k_softc *sc)
 {
-        struct ath5k_softc *sc = hw->priv;
+        struct ieee80211_hw *hw = sc->hw;
 
-        ath5k_hw_set_tsf64(sc->ah, tsf);
-}
-
-static void
-ath5k_reset_tsf(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
+        /*
+         * NB: the order of these is important:
+         * o call the 802.11 layer before detaching ath5k_hw to
+         *   ensure callbacks into the driver to delete global
+         *   key cache entries can be handled
+         * o reclaim the tx queue data structures after calling
+         *   the 802.11 layer as we'll get called back to reclaim
+         *   node state and potentially want to use them
+         * o to cleanup the tx queues the hal is called, so detach
+         *   it last
+         * XXX: ??? detach ath5k_hw ???
+         * Other than that, it's straightforward...
+         */
+        ieee80211_unregister_hw(hw);
+        ath5k_desc_free(sc);
+        ath5k_txq_release(sc);
+        ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
+        ath5k_unregister_leds(sc);
 
+        ath5k_sysfs_unregister(sc);
         /*
-         * in IBSS mode we need to update the beacon timers too.
-         * this will also reset the TSF if we call it with 0
+         * NB: can't reclaim these until after ieee80211_ifdetach
+         * returns because we'll get called back to reclaim node
+         * state and potentially want to use them.
          */
-        if (sc->opmode == NL80211_IFTYPE_ADHOC)
-                ath5k_beacon_update_timers(sc, 0);
-        else
-                ath5k_hw_reset_tsf(sc->ah);
+        ath5k_hw_deinit(sc->ah);
+        free_irq(sc->irq, sc);
 }
 
-/*
- * Updates the beacon that is sent by ath5k_beacon_send.  For adhoc,
- * this is called only once at config_bss time, for AP we do it every
- * SWBA interrupt so that the TIM will reflect buffered frames.
- *
- * Called with the beacon lock.
- */
-static int
-ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+bool
+ath_any_vif_assoc(struct ath5k_softc *sc)
 {
-        int ret;
-        struct ath5k_softc *sc = hw->priv;
-        struct sk_buff *skb;
+        struct ath5k_vif_iter_data iter_data;
+        iter_data.hw_macaddr = NULL;
+        iter_data.any_assoc = false;
+        iter_data.need_set_hw_addr = false;
+        iter_data.found_active = true;
 
-        if (WARN_ON(!vif)) {
-                ret = -EINVAL;
-                goto out;
-        }
-
-        skb = ieee80211_beacon_get(hw, vif);
-
-        if (!skb) {
-                ret = -ENOMEM;
-                goto out;
-        }
-
-        ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
-
-        ath5k_txbuf_free_skb(sc, sc->bbuf);
-        sc->bbuf->skb = skb;
-        ret = ath5k_beacon_setup(sc, sc->bbuf);
-        if (ret)
-                sc->bbuf->skb = NULL;
-out:
-        return ret;
+        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
+                                                   &iter_data);
+        return iter_data.any_assoc;
 }
 
-static void
+void
 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
 {
         struct ath5k_softc *sc = hw->priv;
@@ -3460,94 +2993,3 @@ set_beacon_filter(struct ieee80211_hw *hw, bool enable)
         ath5k_hw_set_rx_filter(ah, rfilt);
         sc->filter_flags = rfilt;
 }
-
-static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
-                                    struct ieee80211_vif *vif,
-                                    struct ieee80211_bss_conf *bss_conf,
-                                    u32 changes)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ath_common *common = ath5k_hw_common(ah);
-        unsigned long flags;
-
-        mutex_lock(&sc->lock);
-        if (WARN_ON(sc->vif != vif))
-                goto unlock;
-
-        if (changes & BSS_CHANGED_BSSID) {
-                /* Cache for later use during resets */
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                common->curaid = 0;
-                ath5k_hw_set_associd(ah);
-                mmiowb();
-        }
-
-        if (changes & BSS_CHANGED_BEACON_INT)
-                sc->bintval = bss_conf->beacon_int;
-
-        if (changes & BSS_CHANGED_ASSOC) {
-                sc->assoc = bss_conf->assoc;
-                if (sc->opmode == NL80211_IFTYPE_STATION)
-                        set_beacon_filter(hw, sc->assoc);
-                ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
-                        AR5K_LED_ASSOC : AR5K_LED_INIT);
-                if (bss_conf->assoc) {
-                        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
-                                  "Bss Info ASSOC %d, bssid: %pM\n",
-                                  bss_conf->aid, common->curbssid);
-                        common->curaid = bss_conf->aid;
-                        ath5k_hw_set_associd(ah);
-                        /* Once ANI is available you would start it here */
-                }
-        }
-
-        if (changes & BSS_CHANGED_BEACON) {
-                spin_lock_irqsave(&sc->block, flags);
-                ath5k_beacon_update(hw, vif);
-                spin_unlock_irqrestore(&sc->block, flags);
-        }
-
-        if (changes & BSS_CHANGED_BEACON_ENABLED)
-                sc->enable_beacon = bss_conf->enable_beacon;
-
-        if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
-                       BSS_CHANGED_BEACON_INT))
-                ath5k_beacon_config(sc);
-
- unlock:
-        mutex_unlock(&sc->lock);
-}
-
-static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-        if (!sc->assoc)
-                ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
-}
-
-static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-        ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
-                AR5K_LED_ASSOC : AR5K_LED_INIT);
-}
-
-/**
- * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
- *
- * @hw: struct ieee80211_hw pointer
- * @coverage_class: IEEE 802.11 coverage class number
- *
- * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
- * coverage class. The values are persistent, they are restored after device
- * reset.
- */
-static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        mutex_lock(&sc->lock);
-        ath5k_hw_set_coverage_class(sc->ah, coverage_class);
-        mutex_unlock(&sc->lock);
-}
diff --git a/drivers/net/wireless/ath/ath5k/base.h b/drivers/net/wireless/ath/ath5k/base.h
index dc1241f9c4e8..b294f3305011 100644
--- a/drivers/net/wireless/ath/ath5k/base.h
+++ b/drivers/net/wireless/ath/ath5k/base.h
@@ -58,7 +58,9 @@
 
 #define ATH_RXBUF       40              /* number of RX buffers */
 #define ATH_TXBUF       200             /* number of TX buffers */
-#define ATH_BCBUF       1               /* number of beacon buffers */
+#define ATH_BCBUF       4               /* number of beacon buffers */
+#define ATH5K_TXQ_LEN_MAX       (ATH_TXBUF / 4)         /* bufs per queue */
+#define ATH5K_TXQ_LEN_LOW       (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
 
 struct ath5k_buf {
         struct list_head        list;
@@ -83,6 +85,10 @@ struct ath5k_txq {
         struct list_head        q;      /* transmit queue */
         spinlock_t              lock;   /* lock on q and link */
         bool                    setup;
+        int                     txq_len; /* number of queued buffers */
+        int                     txq_max; /* max allowed num of queued buffers */
+        bool                    txq_poll_mark;
+        unsigned int            txq_stuck;      /* informational counter */
 };
 
 #define ATH5K_LED_MAX_NAME_LEN 31
@@ -116,6 +122,13 @@ struct ath5k_statistics {
         /* frame errors */
         unsigned int rx_all_count;      /* all RX frames, including errors */
         unsigned int tx_all_count;      /* all TX frames, including errors */
+        unsigned int rx_bytes_count;    /* all RX bytes, including errored pks
+                                         * and the MAC headers for each packet
+                                         */
+        unsigned int tx_bytes_count;    /* all TX bytes, including errored pkts
+                                         * and the MAC headers and padding for
+                                         * each packet.
+                                         */
         unsigned int rxerr_crc;
         unsigned int rxerr_phy;
         unsigned int rxerr_phy_code[32];
@@ -146,10 +159,21 @@ struct ath5k_statistics {
 #define ATH_CHAN_MAX    (14+14+14+252+20)
 #endif
 
+struct ath5k_vif {
+        bool                    assoc; /* are we associated or not */
+        enum nl80211_iftype     opmode;
+        int                     bslot;
+        struct ath5k_buf        *bbuf; /* beacon buffer */
+        u8                      lladdr[ETH_ALEN];
+};
+
 /* Software Carrier, keeps track of the driver state
  * associated with an instance of a device */
 struct ath5k_softc {
-        struct pci_dev          *pdev;          /* for dma mapping */
+        struct pci_dev          *pdev;
+        struct device           *dev;           /* for dma mapping */
+        int irq;
+        u16 devid;
         void __iomem            *iobase;        /* address of the device */
         struct mutex            lock;           /* dev-level lock */
         struct ieee80211_hw     *hw;            /* IEEE 802.11 common */
@@ -160,8 +184,6 @@ struct ath5k_softc {
         enum nl80211_iftype     opmode;
         struct ath5k_hw         *ah;            /* Atheros HW */
 
-        struct ieee80211_supported_band         *curband;
-
 #ifdef CONFIG_ATH5K_DEBUG
         struct ath5k_dbg_info   debug;          /* debug info */
 #endif /* CONFIG_ATH5K_DEBUG */
@@ -171,21 +193,26 @@ struct ath5k_softc {
         dma_addr_t              desc_daddr;     /* DMA (physical) address */
         size_t                  desc_len;       /* size of TX/RX descriptors */
 
-        DECLARE_BITMAP(status, 5);
+        DECLARE_BITMAP(status, 6);
 #define ATH_STAT_INVALID        0               /* disable hardware accesses */
 #define ATH_STAT_MRRETRY        1               /* multi-rate retry support */
 #define ATH_STAT_PROMISC        2
 #define ATH_STAT_LEDSOFT        3               /* enable LED gpio status */
 #define ATH_STAT_STARTED        4               /* opened & irqs enabled */
+#define ATH_STAT_2G_DISABLED    5               /* multiband radio without 2G */
 
         unsigned int            filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
-        unsigned int            curmode;        /* current phy mode */
         struct ieee80211_channel *curchan;      /* current h/w channel */
 
-        struct ieee80211_vif *vif;
+        u16                     nvifs;
 
         enum ath5k_int          imask;          /* interrupt mask copy */
 
+        spinlock_t              irqlock;
+        bool                    rx_pending;     /* rx tasklet pending */
+        bool                    tx_pending;     /* tx tasklet pending */
+
+        u8                      lladdr[ETH_ALEN];
         u8                      bssidmask[ETH_ALEN];
 
         unsigned int            led_pin,        /* GPIO pin for driving LED */
@@ -204,7 +231,6 @@ struct ath5k_softc {
         spinlock_t              txbuflock;
         unsigned int            txbuf_len;      /* buf count in txbuf list */
         struct ath5k_txq        txqs[AR5K_NUM_TX_QUEUES];       /* tx queues */
-        struct ath5k_txq        *txq;           /* main tx queue */
         struct tasklet_struct   txtq;           /* tx intr tasklet */
         struct ath5k_led        tx_led;         /* tx led */
 
@@ -214,7 +240,10 @@ struct ath5k_softc {
 
         spinlock_t              block;          /* protects beacon */
         struct tasklet_struct   beacontq;       /* beacon intr tasklet */
-        struct ath5k_buf        *bbuf;          /* beacon buffer */
+        struct list_head        bcbuf;          /* beacon buffer */
+        struct ieee80211_vif    *bslot[ATH_BCBUF];
+        u16                     num_ap_vifs;
+        u16                     num_adhoc_vifs;
         unsigned int            bhalq,          /* SW q for outgoing beacons */
                                 bmisscount,     /* missed beacon transmits */
                                 bintval,        /* beacon interval in TU */
@@ -230,8 +259,25 @@ struct ath5k_softc {
 
         struct ath5k_ani_state  ani_state;
         struct tasklet_struct   ani_tasklet;    /* ANI calibration */
+
+        struct delayed_work     tx_complete_work;
+
+        struct survey_info      survey;         /* collected survey info */
 };
 
+struct ath5k_vif_iter_data {
+        const u8        *hw_macaddr;
+        u8              mask[ETH_ALEN];
+        u8              active_mac[ETH_ALEN]; /* first active MAC */
+        bool            need_set_hw_addr;
+        bool            found_active;
+        bool            any_assoc;
+        enum nl80211_iftype opmode;
+        int n_stas;
+};
+void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif);
+
+
 #define ath5k_hw_hasbssidmask(_ah) \
         (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
 #define ath5k_hw_hasveol(_ah) \
diff --git a/drivers/net/wireless/ath/ath5k/caps.c b/drivers/net/wireless/ath/ath5k/caps.c
index beae519aa735..7dd88e1c3ff8 100644
--- a/drivers/net/wireless/ath/ath5k/caps.c
+++ b/drivers/net/wireless/ath/ath5k/caps.c
@@ -32,24 +32,24 @@
  */
 int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
 {
+        struct ath5k_capabilities *caps = &ah->ah_capabilities;
         u16 ee_header;
 
         /* Capabilities stored in the EEPROM */
-        ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
+        ee_header = caps->cap_eeprom.ee_header;
 
         if (ah->ah_version == AR5K_AR5210) {
                 /*
                  * Set radio capabilities
                  * (The AR5110 only supports the middle 5GHz band)
                  */
-                ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
-                ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
-                ah->ah_capabilities.cap_range.range_2ghz_min = 0;
-                ah->ah_capabilities.cap_range.range_2ghz_max = 0;
+                caps->cap_range.range_5ghz_min = 5120;
+                caps->cap_range.range_5ghz_max = 5430;
+                caps->cap_range.range_2ghz_min = 0;
+                caps->cap_range.range_2ghz_max = 0;
 
                 /* Set supported modes */
-                __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
-                __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
+                __set_bit(AR5K_MODE_11A, caps->cap_mode);
         } else {
                 /*
                  * XXX The tranceiver supports frequencies from 4920 to 6100GHz
@@ -57,9 +57,8 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
                  * XXX current ieee80211 implementation because the IEEE
                  * XXX channel mapping does not support negative channel
                  * XXX numbers (2312MHz is channel -19). Of course, this
-                 * XXX doesn't matter because these channels are out of range
-                 * XXX but some regulation domains like MKK (Japan) will
-                 * XXX support frequencies somewhere around 4.8GHz.
+                 * XXX doesn't matter because these channels are out of the
+                 * XXX legal range.
                  */
 
                 /*
@@ -67,18 +66,14 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
                  */
 
                 if (AR5K_EEPROM_HDR_11A(ee_header)) {
-                        /* 4920 */
-                        ah->ah_capabilities.cap_range.range_5ghz_min = 5005;
-                        ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
+                        if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain))
+                                caps->cap_range.range_5ghz_min = 4920;
+                        else
+                                caps->cap_range.range_5ghz_min = 5005;
+                        caps->cap_range.range_5ghz_max = 6100;
 
                         /* Set supported modes */
-                        __set_bit(AR5K_MODE_11A,
-                                        ah->ah_capabilities.cap_mode);
-                        __set_bit(AR5K_MODE_11A_TURBO,
-                                        ah->ah_capabilities.cap_mode);
-                        if (ah->ah_version == AR5K_AR5212)
-                                __set_bit(AR5K_MODE_11G_TURBO,
-                                                ah->ah_capabilities.cap_mode);
+                        __set_bit(AR5K_MODE_11A, caps->cap_mode);
                 }
 
                 /* Enable  802.11b if a 2GHz capable radio (2111/5112) is
@@ -87,32 +82,32 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
                     (AR5K_EEPROM_HDR_11G(ee_header) &&
                      ah->ah_version != AR5K_AR5211)) {
                         /* 2312 */
-                        ah->ah_capabilities.cap_range.range_2ghz_min = 2412;
-                        ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
+                        caps->cap_range.range_2ghz_min = 2412;
+                        caps->cap_range.range_2ghz_max = 2732;
 
                         if (AR5K_EEPROM_HDR_11B(ee_header))
-                                __set_bit(AR5K_MODE_11B,
-                                                ah->ah_capabilities.cap_mode);
+                                __set_bit(AR5K_MODE_11B, caps->cap_mode);
 
                         if (AR5K_EEPROM_HDR_11G(ee_header) &&
                             ah->ah_version != AR5K_AR5211)
-                                __set_bit(AR5K_MODE_11G,
-                                                ah->ah_capabilities.cap_mode);
+                                __set_bit(AR5K_MODE_11G, caps->cap_mode);
                 }
         }
 
+        if ((ah->ah_radio_5ghz_revision & 0xf0) == AR5K_SREV_RAD_2112)
+                __clear_bit(AR5K_MODE_11A, caps->cap_mode);
+
         /* Set number of supported TX queues */
         if (ah->ah_version == AR5K_AR5210)
-                ah->ah_capabilities.cap_queues.q_tx_num =
-                        AR5K_NUM_TX_QUEUES_NOQCU;
+                caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
         else
-                ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
+                caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
 
         /* newer hardware has PHY error counters */
         if (ah->ah_mac_srev >= AR5K_SREV_AR5213A)
-                ah->ah_capabilities.cap_has_phyerr_counters = true;
+                caps->cap_has_phyerr_counters = true;
         else
-                ah->ah_capabilities.cap_has_phyerr_counters = false;
+                caps->cap_has_phyerr_counters = false;
 
         return 0;
 }
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c
index 4cccc29964f6..0bf7313b8a17 100644
--- a/drivers/net/wireless/ath/ath5k/debug.c
+++ b/drivers/net/wireless/ath/ath5k/debug.c
@@ -71,8 +71,6 @@ module_param_named(debug, ath5k_debug, uint, 0);
 #include "reg.h"
 #include "ani.h"
 
-static struct dentry *ath5k_global_debugfs;
-
 static int ath5k_debugfs_open(struct inode *inode, struct file *file)
 {
         file->private_data = inode->i_private;
@@ -271,6 +269,7 @@ static const struct file_operations fops_beacon = {
         .write = write_file_beacon,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -290,6 +289,7 @@ static const struct file_operations fops_reset = {
         .write = write_file_reset,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = noop_llseek,
 };
 
 
@@ -308,10 +308,10 @@ static const struct {
         { ATH5K_DEBUG_CALIBRATE, "calib",       "periodic calibration" },
         { ATH5K_DEBUG_TXPOWER,  "txpower",      "transmit power setting" },
         { ATH5K_DEBUG_LED,      "led",          "LED management" },
-        { ATH5K_DEBUG_DUMP_RX,  "dumprx",       "print received skb content" },
-        { ATH5K_DEBUG_DUMP_TX,  "dumptx",       "print transmit skb content" },
         { ATH5K_DEBUG_DUMPBANDS, "dumpbands",   "dump bands" },
+        { ATH5K_DEBUG_DMA,      "dma",          "dma start/stop" },
         { ATH5K_DEBUG_ANI,      "ani",          "adaptive noise immunity" },
+        { ATH5K_DEBUG_DESC,     "desc",         "descriptor chains" },
         { ATH5K_DEBUG_ANY,      "all",          "show all debug levels" },
 };
 
@@ -369,6 +369,7 @@ static const struct file_operations fops_debug = {
         .write = write_file_debug,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -480,6 +481,61 @@ static const struct file_operations fops_antenna = {
         .write = write_file_antenna,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+/* debugfs: misc */
+
+static ssize_t read_file_misc(struct file *file, char __user *user_buf,
+                                   size_t count, loff_t *ppos)
+{
+        struct ath5k_softc *sc = file->private_data;
+        char buf[700];
+        unsigned int len = 0;
+        u32 filt = ath5k_hw_get_rx_filter(sc->ah);
+
+        len += snprintf(buf+len, sizeof(buf)-len, "bssid-mask: %pM\n",
+                        sc->bssidmask);
+        len += snprintf(buf+len, sizeof(buf)-len, "filter-flags: 0x%x ",
+                        filt);
+        if (filt & AR5K_RX_FILTER_UCAST)
+                len += snprintf(buf+len, sizeof(buf)-len, " UCAST");
+        if (filt & AR5K_RX_FILTER_MCAST)
+                len += snprintf(buf+len, sizeof(buf)-len, " MCAST");
+        if (filt & AR5K_RX_FILTER_BCAST)
+                len += snprintf(buf+len, sizeof(buf)-len, " BCAST");
+        if (filt & AR5K_RX_FILTER_CONTROL)
+                len += snprintf(buf+len, sizeof(buf)-len, " CONTROL");
+        if (filt & AR5K_RX_FILTER_BEACON)
+                len += snprintf(buf+len, sizeof(buf)-len, " BEACON");
+        if (filt & AR5K_RX_FILTER_PROM)
+                len += snprintf(buf+len, sizeof(buf)-len, " PROM");
+        if (filt & AR5K_RX_FILTER_XRPOLL)
+                len += snprintf(buf+len, sizeof(buf)-len, " XRPOLL");
+        if (filt & AR5K_RX_FILTER_PROBEREQ)
+                len += snprintf(buf+len, sizeof(buf)-len, " PROBEREQ");
+        if (filt & AR5K_RX_FILTER_PHYERR_5212)
+                len += snprintf(buf+len, sizeof(buf)-len, " PHYERR-5212");
+        if (filt & AR5K_RX_FILTER_RADARERR_5212)
+                len += snprintf(buf+len, sizeof(buf)-len, " RADARERR-5212");
+        if (filt & AR5K_RX_FILTER_PHYERR_5211)
+                snprintf(buf+len, sizeof(buf)-len, " PHYERR-5211");
+        if (filt & AR5K_RX_FILTER_RADARERR_5211)
+                len += snprintf(buf+len, sizeof(buf)-len, " RADARERR-5211");
+
+        len += snprintf(buf+len, sizeof(buf)-len, "\nopmode: %s (%d)\n",
+                        ath_opmode_to_string(sc->opmode), sc->opmode);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_misc = {
+        .read = read_file_misc,
+        .open = ath5k_debugfs_open,
+        .owner = THIS_MODULE,
 };
 
 
@@ -496,60 +552,64 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
 
         len += snprintf(buf+len, sizeof(buf)-len,
                         "RX\n---------------------\n");
-        len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%u\t(%u%%)\n",
                         st->rxerr_crc,
                         st->rx_all_count > 0 ?
                                 st->rxerr_crc*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%u\t(%u%%)\n",
                         st->rxerr_phy,
                         st->rx_all_count > 0 ?
                                 st->rxerr_phy*100/st->rx_all_count : 0);
         for (i = 0; i < 32; i++) {
                 if (st->rxerr_phy_code[i])
                         len += snprintf(buf+len, sizeof(buf)-len,
-                                " phy_err[%d]\t%d\n",
+                                " phy_err[%u]\t%u\n",
                                 i, st->rxerr_phy_code[i]);
         }
 
-        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n",
                         st->rxerr_fifo,
                         st->rx_all_count > 0 ?
                                 st->rxerr_fifo*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%u\t(%u%%)\n",
                         st->rxerr_decrypt,
                         st->rx_all_count > 0 ?
                                 st->rxerr_decrypt*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%u\t(%u%%)\n",
                         st->rxerr_mic,
                         st->rx_all_count > 0 ?
                                 st->rxerr_mic*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "process\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "process\t%u\t(%u%%)\n",
                         st->rxerr_proc,
                         st->rx_all_count > 0 ?
                                 st->rxerr_proc*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%u\t(%u%%)\n",
                         st->rxerr_jumbo,
                         st->rx_all_count > 0 ?
                                 st->rxerr_jumbo*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%d]\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%u]\n",
                         st->rx_all_count);
+        len += snprintf(buf+len, sizeof(buf)-len, "RX-all-bytes\t%u\n",
+                        st->rx_bytes_count);
 
         len += snprintf(buf+len, sizeof(buf)-len,
                         "\nTX\n---------------------\n");
-        len += snprintf(buf+len, sizeof(buf)-len, "retry\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "retry\t%u\t(%u%%)\n",
                         st->txerr_retry,
                         st->tx_all_count > 0 ?
                                 st->txerr_retry*100/st->tx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n",
                         st->txerr_fifo,
                         st->tx_all_count > 0 ?
                                 st->txerr_fifo*100/st->tx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "filter\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "filter\t%u\t(%u%%)\n",
                         st->txerr_filt,
                         st->tx_all_count > 0 ?
                                 st->txerr_filt*100/st->tx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%d]\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%u]\n",
                         st->tx_all_count);
+        len += snprintf(buf+len, sizeof(buf)-len, "TX-all-bytes\t%u\n",
+                        st->tx_bytes_count);
 
         if (len > sizeof(buf))
                 len = sizeof(buf);
@@ -591,6 +651,7 @@ static const struct file_operations fops_frameerrors = {
         .write = write_file_frameerrors,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -656,21 +717,22 @@ static ssize_t read_file_ani(struct file *file, char __user *user_buf,
                         st->mib_intr);
         len += snprintf(buf+len, sizeof(buf)-len,
                         "beacon RSSI average:\t%d\n",
-                        sc->ah->ah_beacon_rssi_avg.avg);
+                        (int)ewma_read(&sc->ah->ah_beacon_rssi_avg));
+
+#define CC_PRINT(_struct, _field) \
+        _struct._field, \
+        _struct.cycles > 0 ? \
+        _struct._field*100/_struct.cycles : 0
+
         len += snprintf(buf+len, sizeof(buf)-len, "profcnt tx\t\t%u\t(%d%%)\n",
-                        as->pfc_tx,
-                        as->pfc_cycles > 0 ?
-                        as->pfc_tx*100/as->pfc_cycles : 0);
+                        CC_PRINT(as->last_cc, tx_frame));
         len += snprintf(buf+len, sizeof(buf)-len, "profcnt rx\t\t%u\t(%d%%)\n",
-                        as->pfc_rx,
-                        as->pfc_cycles > 0 ?
-                        as->pfc_rx*100/as->pfc_cycles : 0);
+                        CC_PRINT(as->last_cc, rx_frame));
         len += snprintf(buf+len, sizeof(buf)-len, "profcnt busy\t\t%u\t(%d%%)\n",
-                        as->pfc_busy,
-                        as->pfc_cycles > 0 ?
-                        as->pfc_busy*100/as->pfc_cycles : 0);
+                        CC_PRINT(as->last_cc, rx_busy));
+#undef CC_PRINT
         len += snprintf(buf+len, sizeof(buf)-len, "profcnt cycles\t\t%u\n",
-                        as->pfc_cycles);
+                        as->last_cc.cycles);
         len += snprintf(buf+len, sizeof(buf)-len,
                         "listen time\t\t%d\tlast: %d\n",
                         as->listen_time, as->last_listen);
@@ -748,6 +810,7 @@ static const struct file_operations fops_ani = {
         .write = write_file_ani,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -762,7 +825,7 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
 
         struct ath5k_txq *txq;
         struct ath5k_buf *bf, *bf0;
-        int i, n = 0;
+        int i, n;
 
         len += snprintf(buf+len, sizeof(buf)-len,
                         "available txbuffers: %d\n", sc->txbuf_len);
@@ -776,9 +839,16 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
                 if (!txq->setup)
                         continue;
 
+                n = 0;
+                spin_lock_bh(&txq->lock);
                 list_for_each_entry_safe(bf, bf0, &txq->q, list)
                         n++;
-                len += snprintf(buf+len, sizeof(buf)-len, "  len: %d\n", n);
+                spin_unlock_bh(&txq->lock);
+
+                len += snprintf(buf+len, sizeof(buf)-len,
+                                "  len: %d bufs: %d\n", txq->txq_len, n);
+                len += snprintf(buf+len, sizeof(buf)-len,
+                                "  stuck: %d\n", txq->txq_stuck);
         }
 
         if (len > sizeof(buf))
@@ -811,80 +881,45 @@ static const struct file_operations fops_queue = {
         .write = write_file_queue,
         .open = ath5k_debugfs_open,
         .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
-/* init */
-
-void
-ath5k_debug_init(void)
-{
-        ath5k_global_debugfs = debugfs_create_dir("ath5k", NULL);
-}
-
 void
 ath5k_debug_init_device(struct ath5k_softc *sc)
 {
+        struct dentry *phydir;
+
         sc->debug.level = ath5k_debug;
 
-        sc->debug.debugfs_phydir = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
-                                ath5k_global_debugfs);
+        phydir = debugfs_create_dir("ath5k", sc->hw->wiphy->debugfsdir);
+        if (!phydir)
+            return;
 
-        sc->debug.debugfs_debug = debugfs_create_file("debug",
-                                S_IWUSR | S_IRUSR,
-                                sc->debug.debugfs_phydir, sc, &fops_debug);
+        debugfs_create_file("debug", S_IWUSR | S_IRUSR, phydir, sc,
+                            &fops_debug);
 
-        sc->debug.debugfs_registers = debugfs_create_file("registers", S_IRUSR,
-                                sc->debug.debugfs_phydir, sc, &fops_registers);
+        debugfs_create_file("registers", S_IRUSR, phydir, sc, &fops_registers);
 
-        sc->debug.debugfs_beacon = debugfs_create_file("beacon",
-                                S_IWUSR | S_IRUSR,
-                                sc->debug.debugfs_phydir, sc, &fops_beacon);
+        debugfs_create_file("beacon", S_IWUSR | S_IRUSR, phydir, sc,
+                            &fops_beacon);
 
-        sc->debug.debugfs_reset = debugfs_create_file("reset", S_IWUSR,
-                                sc->debug.debugfs_phydir, sc, &fops_reset);
+        debugfs_create_file("reset", S_IWUSR, phydir, sc, &fops_reset);
 
-        sc->debug.debugfs_antenna = debugfs_create_file("antenna",
-                                S_IWUSR | S_IRUSR,
-                                sc->debug.debugfs_phydir, sc, &fops_antenna);
+        debugfs_create_file("antenna", S_IWUSR | S_IRUSR, phydir, sc,
+                            &fops_antenna);
 
-        sc->debug.debugfs_frameerrors = debugfs_create_file("frameerrors",
-                                S_IWUSR | S_IRUSR,
-                                sc->debug.debugfs_phydir, sc,
-                                &fops_frameerrors);
+        debugfs_create_file("misc", S_IRUSR, phydir, sc, &fops_misc);
 
-        sc->debug.debugfs_ani = debugfs_create_file("ani",
-                                S_IWUSR | S_IRUSR,
-                                sc->debug.debugfs_phydir, sc,
-                                &fops_ani);
+        debugfs_create_file("frameerrors", S_IWUSR | S_IRUSR, phydir, sc,
+                            &fops_frameerrors);
 
-        sc->debug.debugfs_queue = debugfs_create_file("queue",
-                                S_IWUSR | S_IRUSR,
-                                sc->debug.debugfs_phydir, sc,
-                                &fops_queue);
-}
+        debugfs_create_file("ani", S_IWUSR | S_IRUSR, phydir, sc, &fops_ani);
 
-void
-ath5k_debug_finish(void)
-{
-        debugfs_remove(ath5k_global_debugfs);
+        debugfs_create_file("queue", S_IWUSR | S_IRUSR, phydir, sc,
+                            &fops_queue);
 }
 
-void
-ath5k_debug_finish_device(struct ath5k_softc *sc)
-{
-        debugfs_remove(sc->debug.debugfs_debug);
-        debugfs_remove(sc->debug.debugfs_registers);
-        debugfs_remove(sc->debug.debugfs_beacon);
-        debugfs_remove(sc->debug.debugfs_reset);
-        debugfs_remove(sc->debug.debugfs_antenna);
-        debugfs_remove(sc->debug.debugfs_frameerrors);
-        debugfs_remove(sc->debug.debugfs_ani);
-        debugfs_remove(sc->debug.debugfs_queue);
-        debugfs_remove(sc->debug.debugfs_phydir);
-}
-
-
 /* functions used in other places */
 
 void
@@ -955,7 +990,7 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
         struct ath5k_rx_status rs = {};
         int status;
 
-        if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
+        if (likely(!(sc->debug.level & ATH5K_DEBUG_DESC)))
                 return;
 
         printk(KERN_DEBUG "rxdp %x, rxlink %p\n",
@@ -972,24 +1007,6 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
 }
 
 void
-ath5k_debug_dump_skb(struct ath5k_softc *sc,
-                        struct sk_buff *skb, const char *prefix, int tx)
-{
-        char buf[16];
-
-        if (likely(!((tx && (sc->debug.level & ATH5K_DEBUG_DUMP_TX)) ||
-                     (!tx && (sc->debug.level & ATH5K_DEBUG_DUMP_RX)))))
-                return;
-
-        snprintf(buf, sizeof(buf), "%s %s", wiphy_name(sc->hw->wiphy), prefix);
-
-        print_hex_dump_bytes(buf, DUMP_PREFIX_NONE, skb->data,
-                min(200U, skb->len));
-
-        printk(KERN_DEBUG "\n");
-}
-
-void
 ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf)
 {
         struct ath5k_desc *ds = bf->desc;
@@ -997,7 +1014,7 @@ ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf)
         struct ath5k_tx_status ts = {};
         int done;
 
-        if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
+        if (likely(!(sc->debug.level & ATH5K_DEBUG_DESC)))
                 return;
 
         done = sc->ah->ah_proc_tx_desc(sc->ah, bf->desc, &ts);
diff --git a/drivers/net/wireless/ath/ath5k/debug.h b/drivers/net/wireless/ath/ath5k/debug.h
index 606ae94a9157..193dd2d4ea3c 100644
--- a/drivers/net/wireless/ath/ath5k/debug.h
+++ b/drivers/net/wireless/ath/ath5k/debug.h
@@ -68,16 +68,6 @@ struct ath5k_buf;
 
 struct ath5k_dbg_info {
         unsigned int            level;          /* debug level */
-        /* debugfs entries */
-        struct dentry           *debugfs_phydir;
-        struct dentry           *debugfs_debug;
-        struct dentry           *debugfs_registers;
-        struct dentry           *debugfs_beacon;
-        struct dentry           *debugfs_reset;
-        struct dentry           *debugfs_antenna;
-        struct dentry           *debugfs_frameerrors;
-        struct dentry           *debugfs_ani;
-        struct dentry           *debugfs_queue;
 };
 
 /**
@@ -94,7 +84,9 @@ struct ath5k_dbg_info {
  * @ATH5K_DEBUG_DUMP_RX: print received skb content
  * @ATH5K_DEBUG_DUMP_TX: print transmit skb content
  * @ATH5K_DEBUG_DUMPBANDS: dump bands
+ * @ATH5K_DEBUG_DMA: debug dma start/stop
  * @ATH5K_DEBUG_TRACE: trace function calls
+ * @ATH5K_DEBUG_DESC: descriptor setup
  * @ATH5K_DEBUG_ANY: show at any debug level
  *
  * The debug level is used to control the amount and type of debugging output
@@ -113,10 +105,10 @@ enum ath5k_debug_level {
         ATH5K_DEBUG_CALIBRATE   = 0x00000020,
         ATH5K_DEBUG_TXPOWER     = 0x00000040,
         ATH5K_DEBUG_LED         = 0x00000080,
-        ATH5K_DEBUG_DUMP_RX     = 0x00000100,
-        ATH5K_DEBUG_DUMP_TX     = 0x00000200,
         ATH5K_DEBUG_DUMPBANDS   = 0x00000400,
+        ATH5K_DEBUG_DMA         = 0x00000800,
         ATH5K_DEBUG_ANI         = 0x00002000,
+        ATH5K_DEBUG_DESC        = 0x00004000,
         ATH5K_DEBUG_ANY         = 0xffffffff
 };
 
@@ -135,28 +127,15 @@ enum ath5k_debug_level {
         } while (0)
 
 void
-ath5k_debug_init(void);
-
-void
 ath5k_debug_init_device(struct ath5k_softc *sc);
 
 void
-ath5k_debug_finish(void);
-
-void
-ath5k_debug_finish_device(struct ath5k_softc *sc);
-
-void
 ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah);
 
 void
 ath5k_debug_dump_bands(struct ath5k_softc *sc);
 
 void
-ath5k_debug_dump_skb(struct ath5k_softc *sc,
-                        struct sk_buff *skb, const char *prefix, int tx);
-
-void
 ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf);
 
 #else /* no debugging */
@@ -171,28 +150,15 @@ ATH5K_DBG_UNLIMIT(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...)
 {}
 
 static inline void
-ath5k_debug_init(void) {}
-
-static inline void
 ath5k_debug_init_device(struct ath5k_softc *sc) {}
 
 static inline void
-ath5k_debug_finish(void) {}
-
-static inline void
-ath5k_debug_finish_device(struct ath5k_softc *sc) {}
-
-static inline void
 ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) {}
 
 static inline void
 ath5k_debug_dump_bands(struct ath5k_softc *sc) {}
 
 static inline void
-ath5k_debug_dump_skb(struct ath5k_softc *sc,
-                        struct sk_buff *skb, const char *prefix, int tx) {}
-
-static inline void
 ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) {}
 
 #endif /* ifdef CONFIG_ATH5K_DEBUG */
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index 43244382f213..f82383b3ed30 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -26,9 +26,10 @@
 #include "debug.h"
 #include "base.h"
 
-/*
- * TX Descriptors
- */
+
+/************************\
+* TX Control descriptors *
+\************************/
 
 /*
  * Initialize the 2-word tx control descriptor on 5210/5211
@@ -50,7 +51,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         /*
          * Validate input
          * - Zero retries don't make sense.
-         * - A zero rate will put the HW into a mode where it continously sends
+         * - A zero rate will put the HW into a mode where it continuously sends
          *   noise on the channel, so it is important to avoid this.
          */
         if (unlikely(tx_tries0 == 0)) {
@@ -106,10 +107,13 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
                 case AR5K_PKT_TYPE_BEACON:
                 case AR5K_PKT_TYPE_PROBE_RESP:
                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
+                        break;
                 case AR5K_PKT_TYPE_PIFS:
                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
+                        break;
                 default:
                         frame_type = type;
+                        break;
                 }
 
                 tx_ctl->tx_control_0 |=
@@ -184,12 +188,18 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
         struct ath5k_hw_4w_tx_ctl *tx_ctl;
         unsigned int frame_len;
 
+        /*
+         * Use local variables for these to reduce load/store access on
+         * uncached memory
+         */
+        u32 txctl0 = 0, txctl1 = 0, txctl2 = 0, txctl3 = 0;
+
         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 
         /*
          * Validate input
          * - Zero retries don't make sense.
-         * - A zero rate will put the HW into a mode where it continously sends
+         * - A zero rate will put the HW into a mode where it continuously sends
          *   noise on the channel, so it is important to avoid this.
          */
         if (unlikely(tx_tries0 == 0)) {
@@ -207,8 +217,9 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
         if (tx_power > AR5K_TUNE_MAX_TXPOWER)
                 tx_power = AR5K_TUNE_MAX_TXPOWER;
 
-        /* Clear descriptor */
-        memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
+        /* Clear descriptor status area */
+        memset(&desc->ud.ds_tx5212.tx_stat, 0,
+               sizeof(desc->ud.ds_tx5212.tx_stat));
 
         /* Setup control descriptor */
 
@@ -220,7 +231,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
         if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
                 return -EINVAL;
 
-        tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
+        txctl0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
 
         /* Verify and set buffer length */
 
@@ -231,21 +242,17 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
         if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
                 return -EINVAL;
 
-        tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
+        txctl1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
 
-        tx_ctl->tx_control_0 |=
-                AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
-                AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
-        tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
-                                        AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
-        tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
-                                        AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
-        tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
+        txctl0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
+                  AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
+        txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
+        txctl2 = AR5K_REG_SM(tx_tries0, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
+        txctl3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
 
 #define _TX_FLAGS(_c, _flag)                                    \
         if (flags & AR5K_TXDESC_##_flag) {                      \
-                tx_ctl->tx_control_##_c |=                      \
-                        AR5K_4W_TX_DESC_CTL##_c##_##_flag;      \
+                txctl##_c |= AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
         }
 
         _TX_FLAGS(0, CLRDMASK);
@@ -261,8 +268,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
          * WEP crap
          */
         if (key_index != AR5K_TXKEYIX_INVALID) {
-                tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
-                tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
+                txctl0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
+                txctl1 |= AR5K_REG_SM(key_index,
                                 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
         }
 
@@ -273,12 +280,16 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
                 if ((flags & AR5K_TXDESC_RTSENA) &&
                                 (flags & AR5K_TXDESC_CTSENA))
                         return -EINVAL;
-                tx_ctl->tx_control_2 |= rtscts_duration &
-                                AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
-                tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
+                txctl2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
+                txctl3 |= AR5K_REG_SM(rtscts_rate,
                                 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
         }
 
+        tx_ctl->tx_control_0 = txctl0;
+        tx_ctl->tx_control_1 = txctl1;
+        tx_ctl->tx_control_2 = txctl2;
+        tx_ctl->tx_control_3 = txctl3;
+
         return 0;
 }
 
@@ -299,7 +310,7 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         /*
          * Rates can be 0 as long as the retry count is 0 too.
          * A zero rate and nonzero retry count will put the HW into a mode where
-         * it continously sends noise on the channel, so it is important to
+         * it continuously sends noise on the channel, so it is important to
          * avoid this.
          */
         if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
@@ -335,8 +346,13 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         return 0;
 }
 
+
+/***********************\
+* TX Status descriptors *
+\***********************/
+
 /*
- * Proccess the tx status descriptor on 5210/5211
+ * Process the tx status descriptor on 5210/5211
  */
 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
@@ -358,7 +374,7 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
-        ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
+        ts->ts_final_retry = AR5K_REG_MS(tx_status->tx_status_0,
                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
         /*TODO: ts->ts_virtcol + test*/
         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
@@ -367,9 +383,6 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
         ts->ts_antenna = 1;
         ts->ts_status = 0;
-        ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
-                AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
-        ts->ts_retry[0] = ts->ts_longretry;
         ts->ts_final_idx = 0;
 
         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
@@ -388,97 +401,65 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
 }
 
 /*
- * Proccess a tx status descriptor on 5212
+ * Process a tx status descriptor on 5212
  */
 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 {
         struct ath5k_hw_4w_tx_ctl *tx_ctl;
         struct ath5k_hw_tx_status *tx_status;
+        u32 txstat0, txstat1;
 
         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
         tx_status = &desc->ud.ds_tx5212.tx_stat;
 
+        txstat1 = ACCESS_ONCE(tx_status->tx_status_1);
+
         /* No frame has been send or error */
-        if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
+        if (unlikely(!(txstat1 & AR5K_DESC_TX_STATUS1_DONE)))
                 return -EINPROGRESS;
 
+        txstat0 = ACCESS_ONCE(tx_status->tx_status_0);
+
         /*
          * Get descriptor status
          */
-        ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
+        ts->ts_tstamp = AR5K_REG_MS(txstat0,
                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
-        ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
+        ts->ts_shortretry = AR5K_REG_MS(txstat0,
                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
-        ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
+        ts->ts_final_retry = AR5K_REG_MS(txstat0,
                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
-        ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
+        ts->ts_seqnum = AR5K_REG_MS(txstat1,
                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
-        ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
+        ts->ts_rssi = AR5K_REG_MS(txstat1,
                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
-        ts->ts_antenna = (tx_status->tx_status_1 &
+        ts->ts_antenna = (txstat1 &
                 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1;
         ts->ts_status = 0;
 
-        ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
+        ts->ts_final_idx = AR5K_REG_MS(txstat1,
                         AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212);
 
-        /* The longretry counter has the number of un-acked retries
-         * for the final rate. To get the total number of retries
-         * we have to add the retry counters for the other rates
-         * as well
-         */
-        ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
-        switch (ts->ts_final_idx) {
-        case 3:
-                ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
-                        AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
-
-                ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
-                        AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
-                ts->ts_longretry += ts->ts_retry[2];
-                /* fall through */
-        case 2:
-                ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
-                        AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
-
-                ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
-                        AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
-                ts->ts_longretry += ts->ts_retry[1];
-                /* fall through */
-        case 1:
-                ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
-                        AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
-
-                ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
-                        AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
-                ts->ts_longretry += ts->ts_retry[0];
-                /* fall through */
-        case 0:
-                ts->ts_rate[0] = tx_ctl->tx_control_3 &
-                        AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
-                break;
-        }
-
         /* TX error */
-        if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
-                if (tx_status->tx_status_0 &
-                                AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
+        if (!(txstat0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
+                if (txstat0 & AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
                         ts->ts_status |= AR5K_TXERR_XRETRY;
 
-                if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
+                if (txstat0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
                         ts->ts_status |= AR5K_TXERR_FIFO;
 
-                if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
+                if (txstat0 & AR5K_DESC_TX_STATUS0_FILTERED)
                         ts->ts_status |= AR5K_TXERR_FILT;
         }
 
         return 0;
 }
 
-/*
- * RX Descriptors
- */
+
+/****************\
+* RX Descriptors *
+\****************/
 
 /*
  * Initialize an rx control descriptor
@@ -512,7 +493,7 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
 }
 
 /*
- * Proccess the rx status descriptor on 5210/5211
+ * Process the rx status descriptor on 5210/5211
  */
 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
                 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
@@ -595,44 +576,44 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
 }
 
 /*
- * Proccess the rx status descriptor on 5212
+ * Process the rx status descriptor on 5212
  */
 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
                                         struct ath5k_desc *desc,
                                         struct ath5k_rx_status *rs)
 {
         struct ath5k_hw_rx_status *rx_status;
+        u32 rxstat0, rxstat1;
 
         rx_status = &desc->ud.ds_rx.rx_stat;
+        rxstat1 = ACCESS_ONCE(rx_status->rx_status_1);
 
         /* No frame received / not ready */
-        if (unlikely(!(rx_status->rx_status_1 &
-                                AR5K_5212_RX_DESC_STATUS1_DONE)))
+        if (unlikely(!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_DONE)))
                 return -EINPROGRESS;
 
         memset(rs, 0, sizeof(struct ath5k_rx_status));
+        rxstat0 = ACCESS_ONCE(rx_status->rx_status_0);
 
         /*
          * Frame receive status
          */
-        rs->rs_datalen = rx_status->rx_status_0 &
-                AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
-        rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
+        rs->rs_datalen = rxstat0 & AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
+        rs->rs_rssi = AR5K_REG_MS(rxstat0,
                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
-        rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
+        rs->rs_rate = AR5K_REG_MS(rxstat0,
                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
-        rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
+        rs->rs_antenna = AR5K_REG_MS(rxstat0,
                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
-        rs->rs_more = !!(rx_status->rx_status_0 &
-                AR5K_5212_RX_DESC_STATUS0_MORE);
-        rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
+        rs->rs_more = !!(rxstat0 & AR5K_5212_RX_DESC_STATUS0_MORE);
+        rs->rs_tstamp = AR5K_REG_MS(rxstat1,
                 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 
         /*
          * Key table status
          */
-        if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
-                rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
+        if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
+                rs->rs_keyix = AR5K_REG_MS(rxstat1,
                                            AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
         else
                 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
@@ -640,32 +621,32 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
         /*
          * Receive/descriptor errors
          */
-        if (!(rx_status->rx_status_1 &
-            AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
-                if (rx_status->rx_status_1 &
-                                AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
+        if (!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
+                if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
                         rs->rs_status |= AR5K_RXERR_CRC;
 
-                if (rx_status->rx_status_1 &
-                                AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
+                if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
                         rs->rs_status |= AR5K_RXERR_PHY;
-                        rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
+                        rs->rs_phyerr = AR5K_REG_MS(rxstat1,
                                 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE);
                         if (!ah->ah_capabilities.cap_has_phyerr_counters)
                                 ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
                 }
 
-                if (rx_status->rx_status_1 &
-                                AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
+                if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
                         rs->rs_status |= AR5K_RXERR_DECRYPT;
 
-                if (rx_status->rx_status_1 &
-                                AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
+                if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
                         rs->rs_status |= AR5K_RXERR_MIC;
         }
         return 0;
 }
 
+
+/********\
+* Attach *
+\********/
+
 /*
  * Init function pointers inside ath5k_hw struct
  */
diff --git a/drivers/net/wireless/ath/ath5k/desc.h b/drivers/net/wireless/ath/ath5k/desc.h
index b2adb2a281c2..2509d0bf037d 100644
--- a/drivers/net/wireless/ath/ath5k/desc.h
+++ b/drivers/net/wireless/ath/ath5k/desc.h
@@ -26,7 +26,7 @@
 struct ath5k_hw_rx_ctl {
         u32     rx_control_0; /* RX control word 0 */
         u32     rx_control_1; /* RX control word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* RX control word 1 fields/flags */
 #define AR5K_DESC_RX_CTL1_BUF_LEN               0x00000fff /* data buffer length */
@@ -39,7 +39,7 @@ struct ath5k_hw_rx_ctl {
 struct ath5k_hw_rx_status {
         u32     rx_status_0; /* RX status word 0 */
         u32     rx_status_1; /* RX status word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* 5210/5211 */
 /* RX status word 0 fields/flags */
@@ -129,7 +129,7 @@ enum ath5k_phy_error_code {
 struct ath5k_hw_2w_tx_ctl {
         u32     tx_control_0; /* TX control word 0 */
         u32     tx_control_1; /* TX control word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* TX control word 0 fields/flags */
 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN          0x00000fff /* frame length */
@@ -185,7 +185,7 @@ struct ath5k_hw_4w_tx_ctl {
         u32     tx_control_1; /* TX control word 1 */
         u32     tx_control_2; /* TX control word 2 */
         u32     tx_control_3; /* TX control word 3 */
-} __packed;
+} __packed __aligned(4);
 
 /* TX control word 0 fields/flags */
 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN          0x00000fff /* frame length */
@@ -244,7 +244,7 @@ struct ath5k_hw_4w_tx_ctl {
 struct ath5k_hw_tx_status {
         u32     tx_status_0; /* TX status word 0 */
         u32     tx_status_1; /* TX status word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* TX status word 0 fields/flags */
 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK      0x00000001 /* TX success */
@@ -282,7 +282,7 @@ struct ath5k_hw_tx_status {
 struct ath5k_hw_5210_tx_desc {
         struct ath5k_hw_2w_tx_ctl       tx_ctl;
         struct ath5k_hw_tx_status       tx_stat;
-} __packed;
+} __packed __aligned(4);
 
 /*
  * 5212 hardware TX descriptor
@@ -290,7 +290,7 @@ struct ath5k_hw_5210_tx_desc {
 struct ath5k_hw_5212_tx_desc {
         struct ath5k_hw_4w_tx_ctl       tx_ctl;
         struct ath5k_hw_tx_status       tx_stat;
-} __packed;
+} __packed __aligned(4);
 
 /*
  * Common hardware RX descriptor
@@ -298,7 +298,7 @@ struct ath5k_hw_5212_tx_desc {
 struct ath5k_hw_all_rx_desc {
         struct ath5k_hw_rx_ctl          rx_ctl;
         struct ath5k_hw_rx_status       rx_stat;
-} __packed;
+} __packed __aligned(4);
 
 /*
  * Atheros hardware DMA descriptor
@@ -313,7 +313,7 @@ struct ath5k_desc {
                 struct ath5k_hw_5212_tx_desc    ds_tx5212;
                 struct ath5k_hw_all_rx_desc     ds_rx;
         } ud;
-} __packed;
+} __packed __aligned(4);
 
 #define AR5K_RXDESC_INTREQ      0x0020
 
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 484f31870ba8..21091c26a9a5 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -37,6 +37,7 @@
 #include "debug.h"
 #include "base.h"
 
+
 /*********\
 * Receive *
 \*********/
@@ -57,7 +58,7 @@ void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
  *
  * @ah: The &struct ath5k_hw
  */
-int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
+static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
 {
         unsigned int i;
 
@@ -69,7 +70,11 @@ int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
         for (i = 1000; i > 0 &&
                         (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
                         i--)
-                udelay(10);
+                udelay(100);
+
+        if (!i)
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "failed to stop RX DMA !\n");
 
         return i ? 0 : -EBUSY;
 }
@@ -90,11 +95,18 @@ u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
  * @ah: The &struct ath5k_hw
  * @phys_addr: RX descriptor address
  *
- * XXX: Should we check if rx is enabled before setting rxdp ?
+ * Returns -EIO if rx is active
  */
-void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
+int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
 {
+        if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "tried to set RXDP while rx was active !\n");
+                return -EIO;
+        }
+
         ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
+        return 0;
 }
 
 
@@ -125,7 +137,7 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 
         /* Return if queue is declared inactive */
         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return -EIO;
+                return -EINVAL;
 
         if (ah->ah_version == AR5K_AR5210) {
                 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
@@ -173,10 +185,10 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
  *
  * Stop DMA transmit on a specific hw queue and drain queue so we don't
  * have any pending frames. Returns -EBUSY if we still have pending frames,
- * -EINVAL if queue number is out of range.
+ * -EINVAL if queue number is out of range or inactive.
  *
  */
-int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
+static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 {
         unsigned int i = 40;
         u32 tx_queue, pending;
@@ -185,7 +197,7 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 
         /* Return if queue is declared inactive */
         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return -EIO;
+                return -EINVAL;
 
         if (ah->ah_version == AR5K_AR5210) {
                 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
@@ -211,12 +223,31 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
                 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
                 ath5k_hw_reg_read(ah, AR5K_CR);
         } else {
+
+                /*
+                 * Enable DCU early termination to quickly
+                 * flush any pending frames from QCU
+                 */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_DCU_EARLY);
+
                 /*
                  * Schedule TX disable and wait until queue is empty
                  */
                 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
 
-                /*Check for pending frames*/
+                /* Wait for queue to stop */
+                for (i = 1000; i > 0 &&
+                (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);
+                i--)
+                        udelay(100);
+
+                if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "queue %i didn't stop !\n", queue);
+
+                /* Check for pending frames */
+                i = 1000;
                 do {
                         pending = ath5k_hw_reg_read(ah,
                                 AR5K_QUEUE_STATUS(queue)) &
@@ -244,15 +275,15 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 
                         /* Force channel idle high */
                         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
-                                        AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
+                                        AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
 
                         /* Wait a while and disable mechanism */
-                        udelay(200);
+                        udelay(400);
                         AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
                                                 AR5K_QUIET_CTL1_QT_EN);
 
                         /* Re-check for pending frames */
-                        i = 40;
+                        i = 100;
                         do {
                                 pending = ath5k_hw_reg_read(ah,
                                         AR5K_QUEUE_STATUS(queue)) &
@@ -261,13 +292,28 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
                         } while (--i && pending);
 
                         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
-                                        AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
+                                        AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
+
+                        if (pending)
+                                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                        "quiet mechanism didn't work q:%i !\n",
+                                        queue);
                 }
 
+                /*
+                 * Disable DCU early termination
+                 */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_DCU_EARLY);
+
                 /* Clear register */
                 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
-                if (pending)
+                if (pending) {
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                        "tx dma didn't stop (q:%i, frm:%i) !\n",
+                                        queue, pending);
                         return -EBUSY;
+                }
         }
 
         /* TODO: Check for success on 5210 else return error */
@@ -275,6 +321,26 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 }
 
 /**
+ * ath5k_hw_stop_beacon_queue - Stop beacon queue
+ *
+ * @ah The &struct ath5k_hw
+ * @queue The queue number
+ *
+ * Returns -EIO if queue didn't stop
+ */
+int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
+{
+        int ret;
+        ret = ath5k_hw_stop_tx_dma(ah, queue);
+        if (ret) {
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "beacon queue didn't stop !\n");
+                return -EIO;
+        }
+        return 0;
+}
+
+/**
  * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
  *
  * @ah: The &struct ath5k_hw
@@ -377,11 +443,11 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
  *
  * This function increases/decreases the tx trigger level for the tx fifo
  * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
- * the buffer and transmits it's data. Lowering this results sending small
+ * the buffer and transmits its data. Lowering this results sending small
  * frames more quickly but can lead to tx underruns, raising it a lot can
  * result other problems (i think bmiss is related). Right now we start with
  * the lowest possible (64Bytes) and if we get tx underrun we increase it using
- * the increase flag. Returns -EIO if we have have reached maximum/minimum.
+ * the increase flag. Returns -EIO if we have reached maximum/minimum.
  *
  * XXX: Link this with tx DMA size ?
  * XXX: Use it to save interrupts ?
@@ -427,6 +493,7 @@ done:
         return ret;
 }
 
+
 /*******************\
 * Interrupt masking *
 \*******************/
@@ -688,3 +755,92 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
         return old_mask;
 }
 
+
+/********************\
+ Init/Stop functions
+\********************/
+
+/**
+ * ath5k_hw_dma_init - Initialize DMA unit
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Set DMA size and pre-enable interrupts
+ * (driver handles tx/rx buffer setup and
+ * dma start/stop)
+ *
+ * XXX: Save/restore RXDP/TXDP registers ?
+ */
+void ath5k_hw_dma_init(struct ath5k_hw *ah)
+{
+        /*
+         * Set Rx/Tx DMA Configuration
+         *
+         * Set standard DMA size (128). Note that
+         * a DMA size of 512 causes rx overruns and tx errors
+         * on pci-e cards (tested on 5424 but since rx overruns
+         * also occur on 5416/5418 with madwifi we set 128
+         * for all PCI-E cards to be safe).
+         *
+         * XXX: need to check 5210 for this
+         * TODO: Check out tx triger level, it's always 64 on dumps but I
+         * guess we can tweak it and see how it goes ;-)
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
+                        AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
+                AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
+                        AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
+        }
+
+        /* Pre-enable interrupts on 5211/5212*/
+        if (ah->ah_version != AR5K_AR5210)
+                ath5k_hw_set_imr(ah, ah->ah_imr);
+
+}
+
+/**
+ * ath5k_hw_dma_stop - stop DMA unit
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Stop tx/rx DMA and interrupts. Returns
+ * -EBUSY if tx or rx dma failed to stop.
+ *
+ * XXX: Sometimes DMA unit hangs and we have
+ * stuck frames on tx queues, only a reset
+ * can fix that.
+ */
+int ath5k_hw_dma_stop(struct ath5k_hw *ah)
+{
+        int i, qmax, err;
+        err = 0;
+
+        /* Disable interrupts */
+        ath5k_hw_set_imr(ah, 0);
+
+        /* Stop rx dma */
+        err = ath5k_hw_stop_rx_dma(ah);
+        if (err)
+                return err;
+
+        /* Clear any pending interrupts
+         * and disable tx dma */
+        if (ah->ah_version != AR5K_AR5210) {
+                ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
+                qmax = AR5K_NUM_TX_QUEUES;
+        } else {
+                /* PISR/SISR Not available on 5210 */
+                ath5k_hw_reg_read(ah, AR5K_ISR);
+                qmax = AR5K_NUM_TX_QUEUES_NOQCU;
+        }
+
+        for (i = 0; i < qmax; i++) {
+                err = ath5k_hw_stop_tx_dma(ah, i);
+                /* -EINVAL -> queue inactive */
+                if (err && err != -EINVAL)
+                        return err;
+        }
+
+        return 0;
+}
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c
index ae316fec4a6a..392771f93759 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -28,45 +28,16 @@
 #include "debug.h"
 #include "base.h"
 
-/*
- * Read from eeprom
- */
-static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
-{
-        u32 status, timeout;
-
-        /*
-         * Initialize EEPROM access
-         */
-        if (ah->ah_version == AR5K_AR5210) {
-                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
-                (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
-        } else {
-                ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
-                AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
-                                AR5K_EEPROM_CMD_READ);
-        }
-
-        for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
-                status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
-                if (status & AR5K_EEPROM_STAT_RDDONE) {
-                        if (status & AR5K_EEPROM_STAT_RDERR)
-                                return -EIO;
-                        *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
-                                        0xffff);
-                        return 0;
-                }
-                udelay(15);
-        }
 
-        return -ETIMEDOUT;
-}
+/******************\
+* Helper functions *
+\******************/
 
 /*
  * Translate binary channel representation in EEPROM to frequency
  */
 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
-                                 unsigned int mode)
+                                                        unsigned int mode)
 {
         u16 val;
 
@@ -89,6 +60,11 @@ static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
         return val;
 }
 
+
+/*********\
+* Parsers *
+\*********/
+
 /*
  * Initialize eeprom & capabilities structs
  */
@@ -96,7 +72,6 @@ static int
 ath5k_eeprom_init_header(struct ath5k_hw *ah)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-        int ret;
         u16 val;
         u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
 
@@ -198,7 +173,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
          *
          * XXX: Serdes values seem to be fixed so
          * no need to read them here, we write them
-         * during ath5k_hw_attach */
+         * during ath5k_hw_init */
         AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
         ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
                                                         true : false;
@@ -216,7 +191,7 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         u32 o = *offset;
         u16 val;
-        int ret, i = 0;
+        int i = 0;
 
         AR5K_EEPROM_READ(o++, val);
         ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
@@ -276,7 +251,6 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         u32 o = *offset;
         u16 val;
-        int ret;
 
         ee->ee_n_piers[mode] = 0;
         AR5K_EEPROM_READ(o++, val);
@@ -539,7 +513,6 @@ ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
         int o = *offset;
         int i = 0;
         u8 freq1, freq2;
-        int ret;
         u16 val;
 
         ee->ee_n_piers[mode] = 0;
@@ -575,7 +548,7 @@ ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
-        int i, ret;
+        int i;
         u16 val;
         u8 mask;
 
@@ -647,6 +620,7 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
         return 0;
 }
 
+
 /*
  * Read power calibration for RF5111 chips
  *
@@ -661,7 +635,7 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
  * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
  * steps that match with the power values we read from eeprom. On
  * older eeprom versions (< 3.2) these steps are equaly spaced at
- * 10% of the pcdac curve -until the curve reaches it's maximum-
+ * 10% of the pcdac curve -until the curve reaches its maximum-
  * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
  * these 11 steps are spaced in a different way. This function returns
  * the pcdac steps based on eeprom version and curve min/max so that we
@@ -686,6 +660,51 @@ ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
                 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
 }
 
+static int
+ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
+{
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+        struct ath5k_chan_pcal_info *chinfo;
+        u8 pier, pdg;
+
+        switch (mode) {
+        case AR5K_EEPROM_MODE_11A:
+                if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
+                        return 0;
+                chinfo = ee->ee_pwr_cal_a;
+                break;
+        case AR5K_EEPROM_MODE_11B:
+                if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
+                        return 0;
+                chinfo = ee->ee_pwr_cal_b;
+                break;
+        case AR5K_EEPROM_MODE_11G:
+                if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
+                        return 0;
+                chinfo = ee->ee_pwr_cal_g;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
+                if (!chinfo[pier].pd_curves)
+                        continue;
+
+                for (pdg = 0; pdg < AR5K_EEPROM_N_PD_CURVES; pdg++) {
+                        struct ath5k_pdgain_info *pd =
+                                        &chinfo[pier].pd_curves[pdg];
+
+                        kfree(pd->pd_step);
+                        kfree(pd->pd_pwr);
+                }
+
+                kfree(chinfo[pier].pd_curves);
+        }
+
+        return 0;
+}
+
 /* Convert RF5111 specific data to generic raw data
  * used by interpolation code */
 static int
@@ -710,7 +729,7 @@ ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
                                 GFP_KERNEL);
 
                 if (!chinfo[pier].pd_curves)
-                        return -ENOMEM;
+                        goto err_out;
 
                 /* Only one curve for RF5111
                  * find out which one and place
@@ -734,12 +753,12 @@ ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
                 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
                                         sizeof(u8), GFP_KERNEL);
                 if (!pd->pd_step)
-                        return -ENOMEM;
+                        goto err_out;
 
                 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
                                         sizeof(s16), GFP_KERNEL);
                 if (!pd->pd_pwr)
-                        return -ENOMEM;
+                        goto err_out;
 
                 /* Fill raw dataset
                  * (convert power to 0.25dB units
@@ -760,6 +779,10 @@ ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
         }
 
         return 0;
+
+err_out:
+        ath5k_eeprom_free_pcal_info(ah, mode);
+        return -ENOMEM;
 }
 
 /* Parse EEPROM data */
@@ -893,7 +916,7 @@ ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
                                         GFP_KERNEL);
 
                 if (!chinfo[pier].pd_curves)
-                        return -ENOMEM;
+                        goto err_out;
 
                 /* Fill pd_curves */
                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
@@ -912,14 +935,13 @@ ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
                                                 sizeof(u8), GFP_KERNEL);
 
                                 if (!pd->pd_step)
-                                        return -ENOMEM;
+                                        goto err_out;
 
                                 pd->pd_pwr = kcalloc(pd->pd_points,
                                                 sizeof(s16), GFP_KERNEL);
 
                                 if (!pd->pd_pwr)
-                                        return -ENOMEM;
-
+                                        goto err_out;
 
                                 /* Fill raw dataset
                                  * (all power levels are in 0.25dB units) */
@@ -951,13 +973,13 @@ ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
                                                 sizeof(u8), GFP_KERNEL);
 
                                 if (!pd->pd_step)
-                                        return -ENOMEM;
+                                        goto err_out;
 
                                 pd->pd_pwr = kcalloc(pd->pd_points,
                                                 sizeof(s16), GFP_KERNEL);
 
                                 if (!pd->pd_pwr)
-                                        return -ENOMEM;
+                                        goto err_out;
 
                                 /* Fill raw dataset
                                  * (all power levels are in 0.25dB units) */
@@ -980,6 +1002,10 @@ ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
         }
 
         return 0;
+
+err_out:
+        ath5k_eeprom_free_pcal_info(ah, mode);
+        return -ENOMEM;
 }
 
 /* Parse EEPROM data */
@@ -993,7 +1019,6 @@ ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
         u32 offset;
         u8 i, c;
         u16 val;
-        int ret;
         u8 pd_gains = 0;
 
         /* Count how many curves we have and
@@ -1107,13 +1132,13 @@ ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
  *
  * To recreate the curves we read here the points and interpolate
  * later. Note that in most cases only 2 (higher and lower) curves are
- * used (like RF5112) but vendors have the oportunity to include all
+ * used (like RF5112) but vendors have the opportunity to include all
  * 4 curves on eeprom. The final curve (higher power) has an extra
  * point for better accuracy like RF5112.
  */
 
 /* For RF2413 power calibration data doesn't start on a fixed location and
- * if a mode is not supported, it's section is missing -not zeroed-.
+ * if a mode is not supported, its section is missing -not zeroed-.
  * So we need to calculate the starting offset for each section by using
  * these two functions */
 
@@ -1183,7 +1208,7 @@ ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
                                         GFP_KERNEL);
 
                 if (!chinfo[pier].pd_curves)
-                        return -ENOMEM;
+                        goto err_out;
 
                 /* Fill pd_curves */
                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
@@ -1204,13 +1229,13 @@ ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
                                         sizeof(u8), GFP_KERNEL);
 
                         if (!pd->pd_step)
-                                return -ENOMEM;
+                                goto err_out;
 
                         pd->pd_pwr = kcalloc(pd->pd_points,
                                         sizeof(s16), GFP_KERNEL);
 
                         if (!pd->pd_pwr)
-                                return -ENOMEM;
+                                goto err_out;
 
                         /* Fill raw dataset
                          * convert all pwr levels to
@@ -1240,6 +1265,10 @@ ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
         }
 
         return 0;
+
+err_out:
+        ath5k_eeprom_free_pcal_info(ah, mode);
+        return -ENOMEM;
 }
 
 /* Parse EEPROM data */
@@ -1251,7 +1280,7 @@ ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
         struct ath5k_chan_pcal_info *chinfo;
         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
         u32 offset;
-        int idx, i, ret;
+        int idx, i;
         u16 val;
         u8 pd_gains = 0;
 
@@ -1329,7 +1358,7 @@ ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
                         /*
                          * Pd gain 0 is not the last pd gain
                          * so it only has 2 pd points.
-                         * Continue wih pd gain 1.
+                         * Continue with pd gain 1.
                          */
                         pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
 
@@ -1442,7 +1471,7 @@ ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
         u8 *rate_target_pwr_num;
         u32 offset;
         u16 val;
-        int ret, i;
+        int i;
 
         offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
         rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
@@ -1514,6 +1543,7 @@ ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
         return 0;
 }
 
+
 /*
  * Read per channel calibration info from EEPROM
  *
@@ -1560,62 +1590,6 @@ ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
         return 0;
 }
 
-static int
-ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
-{
-        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-        struct ath5k_chan_pcal_info *chinfo;
-        u8 pier, pdg;
-
-        switch (mode) {
-        case AR5K_EEPROM_MODE_11A:
-                if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
-                        return 0;
-                chinfo = ee->ee_pwr_cal_a;
-                break;
-        case AR5K_EEPROM_MODE_11B:
-                if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
-                        return 0;
-                chinfo = ee->ee_pwr_cal_b;
-                break;
-        case AR5K_EEPROM_MODE_11G:
-                if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
-                        return 0;
-                chinfo = ee->ee_pwr_cal_g;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
-                if (!chinfo[pier].pd_curves)
-                        continue;
-
-                for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
-                        struct ath5k_pdgain_info *pd =
-                                        &chinfo[pier].pd_curves[pdg];
-
-                        if (pd != NULL) {
-                                kfree(pd->pd_step);
-                                kfree(pd->pd_pwr);
-                        }
-                }
-
-                kfree(chinfo[pier].pd_curves);
-        }
-
-        return 0;
-}
-
-void
-ath5k_eeprom_detach(struct ath5k_hw *ah)
-{
-        u8 mode;
-
-        for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
-                ath5k_eeprom_free_pcal_info(ah, mode);
-}
-
 /* Read conformance test limits used for regulatory control */
 static int
 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
@@ -1624,7 +1598,7 @@ ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
         struct ath5k_edge_power *rep;
         unsigned int fmask, pmask;
         unsigned int ctl_mode;
-        int ret, i, j;
+        int i, j;
         u32 offset;
         u16 val;
 
@@ -1756,6 +1730,11 @@ ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
         return ret;
 }
 
+
+/***********************\
+* Init/Detach functions *
+\***********************/
+
 /*
  * Initialize eeprom data structure
  */
@@ -1787,35 +1766,27 @@ ath5k_eeprom_init(struct ath5k_hw *ah)
         return 0;
 }
 
-/*
- * Read the MAC address from eeprom
- */
-int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
+void
+ath5k_eeprom_detach(struct ath5k_hw *ah)
 {
-        u8 mac_d[ETH_ALEN] = {};
-        u32 total, offset;
-        u16 data;
-        int octet, ret;
-
-        ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
-        if (ret)
-                return ret;
+        u8 mode;
 
-        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
-                ret = ath5k_hw_eeprom_read(ah, offset, &data);
-                if (ret)
-                        return ret;
+        for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
+                ath5k_eeprom_free_pcal_info(ah, mode);
+}
 
-                total += data;
-                mac_d[octet + 1] = data & 0xff;
-                mac_d[octet] = data >> 8;
-                octet += 2;
+int
+ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel)
+{
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+        case CHANNEL_XR:
+                return AR5K_EEPROM_MODE_11A;
+        case CHANNEL_G:
+                return AR5K_EEPROM_MODE_11G;
+        case CHANNEL_B:
+                return AR5K_EEPROM_MODE_11B;
+        default:
+                return -1;
         }
-
-        if (!total || total == 3 * 0xffff)
-                return -EINVAL;
-
-        memcpy(mac, mac_d, ETH_ALEN);
-
-        return 0;
 }
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h
index c4a6d5f26af4..6511c27d938e 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -241,9 +241,8 @@ enum ath5k_eeprom_freq_bands{
 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
 
 #define AR5K_EEPROM_READ(_o, _v) do {                   \
-        ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
-        if (ret)                                        \
-                return ret;                             \
+        if (!ath5k_hw_nvram_read(ah, (_o), &(_v)))      \
+                return -EIO;                            \
 } while (0)
 
 #define AR5K_EEPROM_READ_HDR(_o, _v)                                    \
@@ -269,29 +268,6 @@ enum ath5k_ctl_mode {
         AR5K_CTL_MODE_M = 15,
 };
 
-/* Default CTL ids for the 3 main reg domains.
- * Atheros only uses these by default but vendors
- * can have up to 32 different CTLs for different
- * scenarios. Note that theese values are ORed with
- * the mode id (above) so we can have up to 24 CTL
- * datasets out of these 3 main regdomains. That leaves
- * 8 ids that can be used by vendors and since 0x20 is
- * missing from HAL sources i guess this is the set of
- * custom CTLs vendors can use. */
-#define AR5K_CTL_FCC    0x10
-#define AR5K_CTL_CUSTOM 0x20
-#define AR5K_CTL_ETSI   0x30
-#define AR5K_CTL_MKK    0x40
-
-/* Indicates a CTL with only mode set and
- * no reg domain mapping, such CTLs are used
- * for world roaming domains or simply when
- * a reg domain is not set */
-#define AR5K_CTL_NO_REGDOMAIN   0xf0
-
-/* Indicates an empty (invalid) CTL */
-#define AR5K_CTL_NO_CTL         0xff
-
 /* Per channel calibration data, used for power table setup */
 struct ath5k_chan_pcal_info_rf5111 {
         /* Power levels in half dbm units
@@ -517,3 +493,5 @@ struct ath5k_eeprom_info {
         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 };
 
+int
+ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel);
diff --git a/drivers/net/wireless/ath/ath5k/initvals.c b/drivers/net/wireless/ath/ath5k/initvals.c
index 8fa439308828..e49340d18df4 100644
--- a/drivers/net/wireless/ath/ath5k/initvals.c
+++ b/drivers/net/wireless/ath/ath5k/initvals.c
@@ -44,7 +44,7 @@ struct ath5k_ini {
 
 struct ath5k_ini_mode {
         u16     mode_register;
-        u32     mode_value[5];
+        u32     mode_value[3];
 };
 
 /* Initial register settings for AR5210 */
@@ -391,76 +391,74 @@ static const struct ath5k_ini ar5211_ini[] = {
  */
 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
         { AR5K_TXCFG,
-        /*        a         aTurbo        b       g (OFDM)    */
-           { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x0000001d, 0x00000015 } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_DCU_GBL_IFS_SLOT,
-           { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
+           { 0x00000168, 0x000001b8, 0x00000168 } },
         { AR5K_DCU_GBL_IFS_SIFS,
-           { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
+           { 0x00000230, 0x000000b0, 0x00000230 } },
         { AR5K_DCU_GBL_IFS_EIFS,
-           { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
+           { 0x00000d98, 0x00001f48, 0x00000d98 } },
         { AR5K_DCU_GBL_IFS_MISC,
-           { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
+           { 0x0000a0e0, 0x00005880, 0x0000a0e0 } },
         { AR5K_TIME_OUT,
-           { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
+           { 0x04000400, 0x20003000, 0x04000400 } },
         { AR5K_USEC_5211,
-           { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
-        { AR5K_PHY_TURBO,
-           { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
+           { 0x0e8d8fa7, 0x01608f95, 0x0e8d8fa7 } },
         { AR5K_PHY(8),
-           { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
-        { AR5K_PHY(9),
-           { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
-        { AR5K_PHY(10),
-           { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
-        { AR5K_PHY(13),
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
-        { AR5K_PHY(14),
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
-        { AR5K_PHY(17),
-           { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
-        { AR5K_PHY(18),
-           { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
-        { AR5K_PHY(20),
-           { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
+           { 0x02020200, 0x02010200, 0x02020200 } },
+        { AR5K_PHY_RF_CTL2,
+           { 0x00000e0e, 0x00000707, 0x00000e0e } },
+        { AR5K_PHY_RF_CTL3,
+           { 0x0a020001, 0x05010000, 0x0a020001 } },
+        { AR5K_PHY_RF_CTL4,
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+        { AR5K_PHY_PA_CTL,
+           { 0x00000007, 0x0000000b, 0x0000000b } },
+        { AR5K_PHY_SETTLING,
+           { 0x1372169c, 0x137216a8, 0x1372169c } },
+        { AR5K_PHY_GAIN,
+           { 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
+        { AR5K_PHY_DESIRED_SIZE,
+           { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
+           { 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
         { AR5K_PHY_AGCCTL,
-           { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
+           { 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
         { AR5K_PHY_NF,
-           { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
+           { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
+           { 0x00002710, 0x0000157c, 0x00002710 } },
         { AR5K_PHY(70),
-           { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
+           { 0x00000190, 0x00000084, 0x00000190 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
+           { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
         { AR5K_PHY_PCDAC_TXPOWER_BASE,
-           { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
+           { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
         { AR5K_RF_BUFFER_CONTROL_4,
-           { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
+           { 0x00000010, 0x00000010, 0x00000010 } },
 };
 
 /* Initial register settings for AR5212 */
@@ -677,89 +675,87 @@ static const struct ath5k_ini ar5212_ini_common_start[] = {
 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+        /*      A/XR          B           G       */
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_DCU_GBL_IFS_SIFS,
-           { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
+           { 0x00000230, 0x000000b0, 0x00000160 } },
         { AR5K_DCU_GBL_IFS_SLOT,
-           { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
+           { 0x00000168, 0x000001b8, 0x0000018c } },
         { AR5K_DCU_GBL_IFS_EIFS,
-           { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
+           { 0x00000e60, 0x00001f1c, 0x00003e38 } },
         { AR5K_DCU_GBL_IFS_MISC,
-           { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
+           { 0x0000a0e0, 0x00005880, 0x0000b0e0 } },
         { AR5K_TIME_OUT,
-           { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
-        { AR5K_PHY_TURBO,
-           { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
+           { 0x03e803e8, 0x04200420, 0x08400840 } },
         { AR5K_PHY(8),
-           { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
+           { 0x02020200, 0x02010200, 0x02020200 } },
         { AR5K_PHY_RF_CTL2,
-           { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000707, 0x00000e0e } },
         { AR5K_PHY_SETTLING,
-           { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
+           { 0x1372161c, 0x13721722, 0x137216a2 } },
         { AR5K_PHY_AGCCTL,
-           { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
+           { 0x00009d10, 0x00009d18, 0x00009d18 } },
         { AR5K_PHY_NF,
-           { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
+           { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
         { AR5K_PHY_WEAK_OFDM_HIGH_THR,
-           { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
+           { 0x409a4190, 0x409a4190, 0x409a4190 } },
         { AR5K_PHY(70),
-           { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
+           { 0x000001b8, 0x00000084, 0x00000108 } },
         { AR5K_PHY_OFDM_SELFCORR,
-           { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
+           { 0x10058a05, 0x10058a05, 0x10058a05 } },
         { 0xa230,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000108 } },
 };
 
 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
+        /*      A/XR          B           G       */
+           { 0x00008015, 0x00008015, 0x00008015 } },
         { AR5K_USEC_5211,
-           { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
+           { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05010100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000007, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_GAIN,
-           { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
+           { 0x0018da5a, 0x0018ca69, 0x0018ca69 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
+           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
+           { 0x3137665e, 0x3137665e, 0x3137665e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
+           { 0x050cb081, 0x050cb081, 0x050cb080 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
+           { 0x00002710, 0x0000157c, 0x00002af8 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
+           { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
+           { 0x642c416a, 0x6440416a, 0x6440416a } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1873800a, 0x1883800a } },
 };
 
 static const struct ath5k_ini rf5111_ini_common_end[] = {
@@ -782,38 +778,38 @@ static const struct ath5k_ini rf5111_ini_common_end[] = {
 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
+        /*      A/XR          B           G       */
+           { 0x00008015, 0x00008015, 0x00008015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000007, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_GAIN,
-           { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
+           { 0x0018da6d, 0x0018ca75, 0x0018ca75 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
+           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
+           { 0x3137665e, 0x3137665e, 0x3137665e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
+           { 0xf7b81020, 0xf7b80d10, 0xf7b81010 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
+           { 0x00000000, 0x00000008, 0x00000008 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
+           { 0x642c0140, 0x6442c160, 0x6442c160 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1873800a, 0x1883800a } },
 };
 
 static const struct ath5k_ini rf5112_ini_common_end[] = {
@@ -833,66 +829,66 @@ static const struct ath5k_ini rf5112_ini_common_end[] = {
 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x00000015, 0x00000015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000007, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_GAIN,
-           { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
+           { 0x0018fa61, 0x001a1a63, 0x001a1a63 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
+           { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
         { AR5K_PHY_SIG,
-           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
+           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
+           { 0x3139605e, 0x3139605e, 0x3139605e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+           { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000000 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
+           { 0x002ec1e0, 0x002ac120, 0x002ac120 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1863800a, 0x1883800a } },
         { 0xa300,
-           { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
+           { 0x18010000, 0x18010000, 0x18010000 } },
         { 0xa304,
-           { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
+           { 0x30032602, 0x30032602, 0x30032602 } },
         { 0xa308,
-           { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
+           { 0x48073e06, 0x48073e06, 0x48073e06 } },
         { 0xa30c,
-           { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
+           { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
         { 0xa310,
-           { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
+           { 0x641a600f, 0x641a600f, 0x641a600f } },
         { 0xa314,
-           { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
+           { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
         { 0xa318,
-           { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
+           { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
         { 0xa31c,
-           { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
+           { 0x90cf865b, 0x8ecf865b, 0x8ecf865b } },
         { 0xa320,
-           { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
+           { 0x9d4f970f, 0x9b4f970f, 0x9b4f970f } },
         { 0xa324,
-           { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
+           { 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f } },
         { 0xa328,
-           { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
+           { 0xb55faf1f, 0xb35faf1f, 0xb35faf1f } },
         { 0xa32c,
-           { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
+           { 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f } },
         { 0xa330,
-           { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
+           { 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f } },
         { 0xa334,
-           { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
+           { 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
 };
 
 static const struct ath5k_ini rf5413_ini_common_end[] = {
@@ -972,38 +968,38 @@ static const struct ath5k_ini rf5413_ini_common_end[] = {
 /* XXX: a mode ? */
 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x00000015, 0x00000015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020000, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
+           { 0x00000e00, 0x00000e00, 0x00000e00 } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
+           { 0x00000002, 0x0000000a, 0x0000000a } },
         { AR5K_PHY_GAIN,
-           { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
+           { 0x0018da6d, 0x001a6a64, 0x001a6a64 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
+           { 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
+           { 0x3137665e, 0x3137665e, 0x3139605e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+           { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000000 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
+           { 0x002c0140, 0x0042c140, 0x0042c140 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1863800a, 0x1883800a } },
 };
 
 static const struct ath5k_ini rf2413_ini_common_end[] = {
@@ -1094,52 +1090,50 @@ static const struct ath5k_ini rf2413_ini_common_end[] = {
 /* XXX: a mode ? */
 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x00000015, 0x00000015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
-        { AR5K_PHY_TURBO,
-           { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000003, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_SETTLING,
-           { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
+           { 0x1372161c, 0x13721722, 0x13721422 } },
         { AR5K_PHY_GAIN,
-           { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
+           { 0x0018fa61, 0x00199a65, 0x00199a65 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
+           { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
         { AR5K_PHY_SIG,
-           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
+           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
+           { 0x3139605e, 0x3139605e, 0x3139605e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+           { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000000 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
+           { 0x00000140, 0x0052c140, 0x0052c140 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1863800a, 0x1883800a } },
         { 0xa324,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa328,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa32c,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa330,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa334,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
 };
 
 static const struct ath5k_ini rf2425_ini_common_end[] = {
@@ -1368,15 +1362,15 @@ static const struct ath5k_ini rf5112_ini_bbgain[] = {
  * Write initial register dump
  */
 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
-                const struct ath5k_ini *ini_regs, bool change_channel)
+                const struct ath5k_ini *ini_regs, bool skip_pcu)
 {
         unsigned int i;
 
         /* Write initial registers */
         for (i = 0; i < size; i++) {
-                /* On channel change there is
-                 * no need to mess with PCU */
-                if (change_channel &&
+                /* Skip PCU registers if
+                 * requested */
+                if (skip_pcu &&
                                 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
                                 ini_regs[i].ini_register <= AR5K_PCU_MAX)
                         continue;
@@ -1409,7 +1403,7 @@ static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
 
 }
 
-int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
+int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
 {
         /*
          * Write initial register settings
@@ -1427,7 +1421,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
                  * Write initial settings common for all modes
                  */
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
-                                ar5212_ini_common_start, change_channel);
+                                ar5212_ini_common_start, skip_pcu);
 
                 /* Second set of mode-specific settings */
                 switch (ah->ah_radio) {
@@ -1439,12 +1433,12 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5111_ini_common_end),
-                                        rf5111_ini_common_end, change_channel);
+                                        rf5111_ini_common_end, skip_pcu);
 
                         /* Baseband gain table */
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5111_ini_bbgain),
-                                        rf5111_ini_bbgain, change_channel);
+                                        rf5111_ini_bbgain, skip_pcu);
 
                         break;
                 case AR5K_RF5112:
@@ -1455,11 +1449,11 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_common_end),
-                                        rf5112_ini_common_end, change_channel);
+                                        rf5112_ini_common_end, skip_pcu);
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
 
                         break;
                 case AR5K_RF5413:
@@ -1470,11 +1464,11 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5413_ini_common_end),
-                                        rf5413_ini_common_end, change_channel);
+                                        rf5413_ini_common_end, skip_pcu);
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
 
                         break;
                 case AR5K_RF2316:
@@ -1486,7 +1480,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf2413_ini_common_end),
-                                        rf2413_ini_common_end, change_channel);
+                                        rf2413_ini_common_end, skip_pcu);
 
                         /* Override settings from rf2413_ini_common_end */
                         if (ah->ah_radio == AR5K_RF2316) {
@@ -1498,9 +1492,32 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
                         break;
                 case AR5K_RF2317:
+
+                        ath5k_hw_ini_mode_registers(ah,
+                                        ARRAY_SIZE(rf2413_ini_mode_end),
+                                        rf2413_ini_mode_end, mode);
+
+                        ath5k_hw_ini_registers(ah,
+                                        ARRAY_SIZE(rf2425_ini_common_end),
+                                        rf2425_ini_common_end, skip_pcu);
+
+                        /* Override settings from rf2413_ini_mode_end */
+                        ath5k_hw_reg_write(ah, 0x00180a65, AR5K_PHY_GAIN);
+
+                        /* Override settings from rf2413_ini_common_end */
+                        ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC);
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TPC_RG5,
+                                AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP, 0xa);
+                        ath5k_hw_reg_write(ah, 0x800000a8, 0x8140);
+                        ath5k_hw_reg_write(ah, 0x000000ff, 0x9958);
+
+                        ath5k_hw_ini_registers(ah,
+                                        ARRAY_SIZE(rf5112_ini_bbgain),
+                                        rf5112_ini_bbgain, skip_pcu);
+                        break;
                 case AR5K_RF2425:
 
                         ath5k_hw_ini_mode_registers(ah,
@@ -1509,11 +1526,11 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf2425_ini_common_end),
-                                        rf2425_ini_common_end, change_channel);
+                                        rf2425_ini_common_end, skip_pcu);
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
                         break;
                 default:
                         return -EINVAL;
@@ -1538,17 +1555,17 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
                  * Write initial settings common for all modes
                  */
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
-                                ar5211_ini, change_channel);
+                                ar5211_ini, skip_pcu);
 
                 /* AR5211 only comes with 5111 */
 
                 /* Baseband gain table */
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
-                                rf5111_ini_bbgain, change_channel);
+                                rf5111_ini_bbgain, skip_pcu);
         /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
         } else if (ah->ah_version == AR5K_AR5210) {
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
-                                ar5210_ini, change_channel);
+                                ar5210_ini, skip_pcu);
         }
 
         return 0;
diff --git a/drivers/net/wireless/ath/ath5k/led.c b/drivers/net/wireless/ath/ath5k/led.c
index 67aa52e9bf94..576edf2965dc 100644
--- a/drivers/net/wireless/ath/ath5k/led.c
+++ b/drivers/net/wireless/ath/ath5k/led.c
@@ -133,7 +133,7 @@ ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
         led->led_dev.default_trigger = trigger;
         led->led_dev.brightness_set = ath5k_led_brightness_set;
 
-        err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
+        err = led_classdev_register(sc->dev, &led->led_dev);
         if (err) {
                 ATH5K_WARN(sc, "could not register LED %s\n", name);
                 led->sc = NULL;
@@ -161,11 +161,20 @@ int ath5k_init_leds(struct ath5k_softc *sc)
 {
         int ret = 0;
         struct ieee80211_hw *hw = sc->hw;
+#ifndef CONFIG_ATHEROS_AR231X
         struct pci_dev *pdev = sc->pdev;
+#endif
         char name[ATH5K_LED_MAX_NAME_LEN + 1];
         const struct pci_device_id *match;
 
+        if (!sc->pdev)
+                return 0;
+
+#ifdef CONFIG_ATHEROS_AR231X
+        match = NULL;
+#else
         match = pci_match_id(&ath5k_led_devices[0], pdev);
+#endif
         if (match) {
                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
                 sc->led_pin = ATH_PIN(match->driver_data);
diff --git a/drivers/net/wireless/ath/ath5k/mac80211-ops.c b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
new file mode 100644
index 000000000000..807bd6440169
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
@@ -0,0 +1,833 @@
+/*-
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * Copyright (c) 2004-2005 Atheros Communications, Inc.
+ * Copyright (c) 2006 Devicescape Software, Inc.
+ * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
+ * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
+ * Copyright (c) 2010 Bruno Randolf <br1@einfach.org>
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ *    of any contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ */
+
+#include <asm/unaligned.h>
+
+#include "base.h"
+#include "reg.h"
+
+extern int ath5k_modparam_nohwcrypt;
+
+/********************\
+* Mac80211 functions *
+\********************/
+
+static void
+ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct ath5k_softc *sc = hw->priv;
+        u16 qnum = skb_get_queue_mapping(skb);
+
+        if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
+                dev_kfree_skb_any(skb);
+                return;
+        }
+
+        ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
+}
+
+
+static int
+ath5k_start(struct ieee80211_hw *hw)
+{
+        return ath5k_init_hw(hw->priv);
+}
+
+
+static void
+ath5k_stop(struct ieee80211_hw *hw)
+{
+        ath5k_stop_hw(hw->priv);
+}
+
+
+static int
+ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+        struct ath5k_softc *sc = hw->priv;
+        int ret;
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+
+        mutex_lock(&sc->lock);
+
+        if ((vif->type == NL80211_IFTYPE_AP ||
+             vif->type == NL80211_IFTYPE_ADHOC)
+            && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
+                ret = -ELNRNG;
+                goto end;
+        }
+
+        /* Don't allow other interfaces if one ad-hoc is configured.
+         * TODO: Fix the problems with ad-hoc and multiple other interfaces.
+         * We would need to operate the HW in ad-hoc mode to allow TSF updates
+         * for the IBSS, but this breaks with additional AP or STA interfaces
+         * at the moment. */
+        if (sc->num_adhoc_vifs ||
+            (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
+                ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
+                ret = -ELNRNG;
+                goto end;
+        }
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_STATION:
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_MESH_POINT:
+                avf->opmode = vif->type;
+                break;
+        default:
+                ret = -EOPNOTSUPP;
+                goto end;
+        }
+
+        sc->nvifs++;
+        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
+
+        /* Assign the vap/adhoc to a beacon xmit slot. */
+        if ((avf->opmode == NL80211_IFTYPE_AP) ||
+            (avf->opmode == NL80211_IFTYPE_ADHOC) ||
+            (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
+                int slot;
+
+                WARN_ON(list_empty(&sc->bcbuf));
+                avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
+                                             list);
+                list_del(&avf->bbuf->list);
+
+                avf->bslot = 0;
+                for (slot = 0; slot < ATH_BCBUF; slot++) {
+                        if (!sc->bslot[slot]) {
+                                avf->bslot = slot;
+                                break;
+                        }
+                }
+                BUG_ON(sc->bslot[avf->bslot] != NULL);
+                sc->bslot[avf->bslot] = vif;
+                if (avf->opmode == NL80211_IFTYPE_AP)
+                        sc->num_ap_vifs++;
+                else if (avf->opmode == NL80211_IFTYPE_ADHOC)
+                        sc->num_adhoc_vifs++;
+        }
+
+        /* Any MAC address is fine, all others are included through the
+         * filter.
+         */
+        memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
+        ath5k_hw_set_lladdr(sc->ah, vif->addr);
+
+        memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
+
+        ath5k_update_bssid_mask_and_opmode(sc, vif);
+        ret = 0;
+end:
+        mutex_unlock(&sc->lock);
+        return ret;
+}
+
+
+static void
+ath5k_remove_interface(struct ieee80211_hw *hw,
+                       struct ieee80211_vif *vif)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+        unsigned int i;
+
+        mutex_lock(&sc->lock);
+        sc->nvifs--;
+
+        if (avf->bbuf) {
+                ath5k_txbuf_free_skb(sc, avf->bbuf);
+                list_add_tail(&avf->bbuf->list, &sc->bcbuf);
+                for (i = 0; i < ATH_BCBUF; i++) {
+                        if (sc->bslot[i] == vif) {
+                                sc->bslot[i] = NULL;
+                                break;
+                        }
+                }
+                avf->bbuf = NULL;
+        }
+        if (avf->opmode == NL80211_IFTYPE_AP)
+                sc->num_ap_vifs--;
+        else if (avf->opmode == NL80211_IFTYPE_ADHOC)
+                sc->num_adhoc_vifs--;
+
+        ath5k_update_bssid_mask_and_opmode(sc, NULL);
+        mutex_unlock(&sc->lock);
+}
+
+
+/*
+ * TODO: Phy disable/diversity etc
+ */
+static int
+ath5k_config(struct ieee80211_hw *hw, u32 changed)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ieee80211_conf *conf = &hw->conf;
+        int ret = 0;
+        int i;
+
+        mutex_lock(&sc->lock);
+
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+                ret = ath5k_chan_set(sc, conf->channel);
+                if (ret < 0)
+                        goto unlock;
+        }
+
+        if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
+        (sc->power_level != conf->power_level)) {
+                sc->power_level = conf->power_level;
+
+                /* Half dB steps */
+                ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
+                ah->ah_retry_long = conf->long_frame_max_tx_count;
+                ah->ah_retry_short = conf->short_frame_max_tx_count;
+
+                for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++)
+                        ath5k_hw_set_tx_retry_limits(ah, i);
+        }
+
+        /* TODO:
+         * 1) Move this on config_interface and handle each case
+         * separately eg. when we have only one STA vif, use
+         * AR5K_ANTMODE_SINGLE_AP
+         *
+         * 2) Allow the user to change antenna mode eg. when only
+         * one antenna is present
+         *
+         * 3) Allow the user to set default/tx antenna when possible
+         *
+         * 4) Default mode should handle 90% of the cases, together
+         * with fixed a/b and single AP modes we should be able to
+         * handle 99%. Sectored modes are extreme cases and i still
+         * haven't found a usage for them. If we decide to support them,
+         * then we must allow the user to set how many tx antennas we
+         * have available
+         */
+        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
+
+unlock:
+        mutex_unlock(&sc->lock);
+        return ret;
+}
+
+
+static void
+ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+                       struct ieee80211_bss_conf *bss_conf, u32 changes)
+{
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+        unsigned long flags;
+
+        mutex_lock(&sc->lock);
+
+        if (changes & BSS_CHANGED_BSSID) {
+                /* Cache for later use during resets */
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                common->curaid = 0;
+                ath5k_hw_set_bssid(ah);
+                mmiowb();
+        }
+
+        if (changes & BSS_CHANGED_BEACON_INT)
+                sc->bintval = bss_conf->beacon_int;
+
+        if (changes & BSS_CHANGED_ERP_SLOT) {
+                int slot_time;
+
+                ah->ah_short_slot = bss_conf->use_short_slot;
+                slot_time = ath5k_hw_get_default_slottime(ah) +
+                            3 * ah->ah_coverage_class;
+                ath5k_hw_set_ifs_intervals(ah, slot_time);
+        }
+
+        if (changes & BSS_CHANGED_ASSOC) {
+                avf->assoc = bss_conf->assoc;
+                if (bss_conf->assoc)
+                        sc->assoc = bss_conf->assoc;
+                else
+                        sc->assoc = ath_any_vif_assoc(sc);
+
+                if (sc->opmode == NL80211_IFTYPE_STATION)
+                        set_beacon_filter(hw, sc->assoc);
+                ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
+                        AR5K_LED_ASSOC : AR5K_LED_INIT);
+                if (bss_conf->assoc) {
+                        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
+                                  "Bss Info ASSOC %d, bssid: %pM\n",
+                                  bss_conf->aid, common->curbssid);
+                        common->curaid = bss_conf->aid;
+                        ath5k_hw_set_bssid(ah);
+                        /* Once ANI is available you would start it here */
+                }
+        }
+
+        if (changes & BSS_CHANGED_BEACON) {
+                spin_lock_irqsave(&sc->block, flags);
+                ath5k_beacon_update(hw, vif);
+                spin_unlock_irqrestore(&sc->block, flags);
+        }
+
+        if (changes & BSS_CHANGED_BEACON_ENABLED)
+                sc->enable_beacon = bss_conf->enable_beacon;
+
+        if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
+                       BSS_CHANGED_BEACON_INT))
+                ath5k_beacon_config(sc);
+
+        mutex_unlock(&sc->lock);
+}
+
+
+static u64
+ath5k_prepare_multicast(struct ieee80211_hw *hw,
+                        struct netdev_hw_addr_list *mc_list)
+{
+        u32 mfilt[2], val;
+        u8 pos;
+        struct netdev_hw_addr *ha;
+
+        mfilt[0] = 0;
+        mfilt[1] = 1;
+
+        netdev_hw_addr_list_for_each(ha, mc_list) {
+                /* calculate XOR of eight 6-bit values */
+                val = get_unaligned_le32(ha->addr + 0);
+                pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+                val = get_unaligned_le32(ha->addr + 3);
+                pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+                pos &= 0x3f;
+                mfilt[pos / 32] |= (1 << (pos % 32));
+                /* XXX: we might be able to just do this instead,
+                * but not sure, needs testing, if we do use this we'd
+                * neet to inform below to not reset the mcast */
+                /* ath5k_hw_set_mcast_filterindex(ah,
+                 *      ha->addr[5]); */
+        }
+
+        return ((u64)(mfilt[1]) << 32) | mfilt[0];
+}
+
+
+/*
+ * o always accept unicast, broadcast, and multicast traffic
+ * o multicast traffic for all BSSIDs will be enabled if mac80211
+ *   says it should be
+ * o maintain current state of phy ofdm or phy cck error reception.
+ *   If the hardware detects any of these type of errors then
+ *   ath5k_hw_get_rx_filter() will pass to us the respective
+ *   hardware filters to be able to receive these type of frames.
+ * o probe request frames are accepted only when operating in
+ *   hostap, adhoc, or monitor modes
+ * o enable promiscuous mode according to the interface state
+ * o accept beacons:
+ *   - when operating in adhoc mode so the 802.11 layer creates
+ *     node table entries for peers,
+ *   - when operating in station mode for collecting rssi data when
+ *     the station is otherwise quiet, or
+ *   - when scanning
+ */
+static void
+ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
+                       unsigned int *new_flags, u64 multicast)
+{
+#define SUPPORTED_FIF_FLAGS \
+        (FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
+        FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
+        FIF_BCN_PRBRESP_PROMISC)
+
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        u32 mfilt[2], rfilt;
+        struct ath5k_vif_iter_data iter_data; /* to count STA interfaces */
+
+        mutex_lock(&sc->lock);
+
+        mfilt[0] = multicast;
+        mfilt[1] = multicast >> 32;
+
+        /* Only deal with supported flags */
+        changed_flags &= SUPPORTED_FIF_FLAGS;
+        *new_flags &= SUPPORTED_FIF_FLAGS;
+
+        /* If HW detects any phy or radar errors, leave those filters on.
+         * Also, always enable Unicast, Broadcasts and Multicast
+         * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
+        rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
+                (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
+                AR5K_RX_FILTER_MCAST);
+
+        if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
+                if (*new_flags & FIF_PROMISC_IN_BSS)
+                        __set_bit(ATH_STAT_PROMISC, sc->status);
+                else
+                        __clear_bit(ATH_STAT_PROMISC, sc->status);
+        }
+
+        if (test_bit(ATH_STAT_PROMISC, sc->status))
+                rfilt |= AR5K_RX_FILTER_PROM;
+
+        /* Note, AR5K_RX_FILTER_MCAST is already enabled */
+        if (*new_flags & FIF_ALLMULTI) {
+                mfilt[0] =  ~0;
+                mfilt[1] =  ~0;
+        }
+
+        /* This is the best we can do */
+        if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
+                rfilt |= AR5K_RX_FILTER_PHYERR;
+
+        /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
+        * and probes for any BSSID */
+        if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
+                rfilt |= AR5K_RX_FILTER_BEACON;
+
+        /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
+         * set we should only pass on control frames for this
+         * station. This needs testing. I believe right now this
+         * enables *all* control frames, which is OK.. but
+         * but we should see if we can improve on granularity */
+        if (*new_flags & FIF_CONTROL)
+                rfilt |= AR5K_RX_FILTER_CONTROL;
+
+        /* Additional settings per mode -- this is per ath5k */
+
+        /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
+
+        switch (sc->opmode) {
+        case NL80211_IFTYPE_MESH_POINT:
+                rfilt |= AR5K_RX_FILTER_CONTROL |
+                         AR5K_RX_FILTER_BEACON |
+                         AR5K_RX_FILTER_PROBEREQ |
+                         AR5K_RX_FILTER_PROM;
+                break;
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_ADHOC:
+                rfilt |= AR5K_RX_FILTER_PROBEREQ |
+                         AR5K_RX_FILTER_BEACON;
+                break;
+        case NL80211_IFTYPE_STATION:
+                if (sc->assoc)
+                        rfilt |= AR5K_RX_FILTER_BEACON;
+        default:
+                break;
+        }
+
+        iter_data.hw_macaddr = NULL;
+        iter_data.n_stas = 0;
+        iter_data.need_set_hw_addr = false;
+        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
+                                                   &iter_data);
+
+        /* Set up RX Filter */
+        if (iter_data.n_stas > 1) {
+                /* If you have multiple STA interfaces connected to
+                 * different APs, ARPs are not received (most of the time?)
+                 * Enabling PROMISC appears to fix that probem.
+                 */
+                rfilt |= AR5K_RX_FILTER_PROM;
+        }
+
+        /* Set filters */
+        ath5k_hw_set_rx_filter(ah, rfilt);
+
+        /* Set multicast bits */
+        ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
+        /* Set the cached hw filter flags, this will later actually
+         * be set in HW */
+        sc->filter_flags = rfilt;
+
+        mutex_unlock(&sc->lock);
+}
+
+
+static int
+ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+              struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+              struct ieee80211_key_conf *key)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+        int ret = 0;
+
+        if (ath5k_modparam_nohwcrypt)
+                return -EOPNOTSUPP;
+
+        switch (key->cipher) {
+        case WLAN_CIPHER_SUITE_WEP40:
+        case WLAN_CIPHER_SUITE_WEP104:
+        case WLAN_CIPHER_SUITE_TKIP:
+                break;
+        case WLAN_CIPHER_SUITE_CCMP:
+                if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
+                        break;
+                return -EOPNOTSUPP;
+        default:
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        mutex_lock(&sc->lock);
+
+        switch (cmd) {
+        case SET_KEY:
+                ret = ath_key_config(common, vif, sta, key);
+                if (ret >= 0) {
+                        key->hw_key_idx = ret;
+                        /* push IV and Michael MIC generation to stack */
+                        key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
+                                key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+                        if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
+                                key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
+                        ret = 0;
+                }
+                break;
+        case DISABLE_KEY:
+                ath_key_delete(common, key);
+                break;
+        default:
+                ret = -EINVAL;
+        }
+
+        mmiowb();
+        mutex_unlock(&sc->lock);
+        return ret;
+}
+
+
+static void
+ath5k_sw_scan_start(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+        if (!sc->assoc)
+                ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
+}
+
+
+static void
+ath5k_sw_scan_complete(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+        ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
+                AR5K_LED_ASSOC : AR5K_LED_INIT);
+}
+
+
+static int
+ath5k_get_stats(struct ieee80211_hw *hw,
+                struct ieee80211_low_level_stats *stats)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        /* Force update */
+        ath5k_hw_update_mib_counters(sc->ah);
+
+        stats->dot11ACKFailureCount = sc->stats.ack_fail;
+        stats->dot11RTSFailureCount = sc->stats.rts_fail;
+        stats->dot11RTSSuccessCount = sc->stats.rts_ok;
+        stats->dot11FCSErrorCount = sc->stats.fcs_error;
+
+        return 0;
+}
+
+
+static int
+ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
+              const struct ieee80211_tx_queue_params *params)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath5k_txq_info qi;
+        int ret = 0;
+
+        if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
+                return 0;
+
+        mutex_lock(&sc->lock);
+
+        ath5k_hw_get_tx_queueprops(ah, queue, &qi);
+
+        qi.tqi_aifs = params->aifs;
+        qi.tqi_cw_min = params->cw_min;
+        qi.tqi_cw_max = params->cw_max;
+        qi.tqi_burst_time = params->txop;
+
+        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
+                  "Configure tx [queue %d],  "
+                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                  queue, params->aifs, params->cw_min,
+                  params->cw_max, params->txop);
+
+        if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
+                ATH5K_ERR(sc,
+                          "Unable to update hardware queue %u!\n", queue);
+                ret = -EIO;
+        } else
+                ath5k_hw_reset_tx_queue(ah, queue);
+
+        mutex_unlock(&sc->lock);
+
+        return ret;
+}
+
+
+static u64
+ath5k_get_tsf(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        return ath5k_hw_get_tsf64(sc->ah);
+}
+
+
+static void
+ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        ath5k_hw_set_tsf64(sc->ah, tsf);
+}
+
+
+static void
+ath5k_reset_tsf(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        /*
+         * in IBSS mode we need to update the beacon timers too.
+         * this will also reset the TSF if we call it with 0
+         */
+        if (sc->opmode == NL80211_IFTYPE_ADHOC)
+                ath5k_beacon_update_timers(sc, 0);
+        else
+                ath5k_hw_reset_tsf(sc->ah);
+}
+
+
+static int
+ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ieee80211_conf *conf = &hw->conf;
+        struct ath_common *common = ath5k_hw_common(sc->ah);
+        struct ath_cycle_counters *cc = &common->cc_survey;
+        unsigned int div = common->clockrate * 1000;
+
+        if (idx != 0)
+                return -ENOENT;
+
+        spin_lock_bh(&common->cc_lock);
+        ath_hw_cycle_counters_update(common);
+        if (cc->cycles > 0) {
+                sc->survey.channel_time += cc->cycles / div;
+                sc->survey.channel_time_busy += cc->rx_busy / div;
+                sc->survey.channel_time_rx += cc->rx_frame / div;
+                sc->survey.channel_time_tx += cc->tx_frame / div;
+        }
+        memset(cc, 0, sizeof(*cc));
+        spin_unlock_bh(&common->cc_lock);
+
+        memcpy(survey, &sc->survey, sizeof(*survey));
+
+        survey->channel = conf->channel;
+        survey->noise = sc->ah->ah_noise_floor;
+        survey->filled = SURVEY_INFO_NOISE_DBM |
+                        SURVEY_INFO_CHANNEL_TIME |
+                        SURVEY_INFO_CHANNEL_TIME_BUSY |
+                        SURVEY_INFO_CHANNEL_TIME_RX |
+                        SURVEY_INFO_CHANNEL_TIME_TX;
+
+        return 0;
+}
+
+
+/**
+ * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
+ *
+ * @hw: struct ieee80211_hw pointer
+ * @coverage_class: IEEE 802.11 coverage class number
+ *
+ * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
+ * coverage class. The values are persistent, they are restored after device
+ * reset.
+ */
+static void
+ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        mutex_lock(&sc->lock);
+        ath5k_hw_set_coverage_class(sc->ah, coverage_class);
+        mutex_unlock(&sc->lock);
+}
+
+
+static int
+ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        if (tx_ant == 1 && rx_ant == 1)
+                ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
+        else if (tx_ant == 2 && rx_ant == 2)
+                ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
+        else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
+                ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
+        else
+                return -EINVAL;
+        return 0;
+}
+
+
+static int
+ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        switch (sc->ah->ah_ant_mode) {
+        case AR5K_ANTMODE_FIXED_A:
+                *tx_ant = 1; *rx_ant = 1; break;
+        case AR5K_ANTMODE_FIXED_B:
+                *tx_ant = 2; *rx_ant = 2; break;
+        case AR5K_ANTMODE_DEFAULT:
+                *tx_ant = 3; *rx_ant = 3; break;
+        }
+        return 0;
+}
+
+
+static void ath5k_get_ringparam(struct ieee80211_hw *hw,
+                                u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        *tx = sc->txqs[AR5K_TX_QUEUE_ID_DATA_MIN].txq_max;
+
+        *tx_max = ATH5K_TXQ_LEN_MAX;
+        *rx = *rx_max = ATH_RXBUF;
+}
+
+
+static int ath5k_set_ringparam(struct ieee80211_hw *hw, u32 tx, u32 rx)
+{
+        struct ath5k_softc *sc = hw->priv;
+        u16 qnum;
+
+        /* only support setting tx ring size for now */
+        if (rx != ATH_RXBUF)
+                return -EINVAL;
+
+        /* restrict tx ring size min/max */
+        if (!tx || tx > ATH5K_TXQ_LEN_MAX)
+                return -EINVAL;
+
+        for (qnum = 0; qnum < ARRAY_SIZE(sc->txqs); qnum++) {
+                if (!sc->txqs[qnum].setup)
+                        continue;
+                if (sc->txqs[qnum].qnum < AR5K_TX_QUEUE_ID_DATA_MIN ||
+                    sc->txqs[qnum].qnum > AR5K_TX_QUEUE_ID_DATA_MAX)
+                        continue;
+
+                sc->txqs[qnum].txq_max = tx;
+                if (sc->txqs[qnum].txq_len >= sc->txqs[qnum].txq_max)
+                        ieee80211_stop_queue(hw, sc->txqs[qnum].qnum);
+        }
+
+        return 0;
+}
+
+
+const struct ieee80211_ops ath5k_hw_ops = {
+        .tx                     = ath5k_tx,
+        .start                  = ath5k_start,
+        .stop                   = ath5k_stop,
+        .add_interface          = ath5k_add_interface,
+        /* .change_interface    = not implemented */
+        .remove_interface       = ath5k_remove_interface,
+        .config                 = ath5k_config,
+        .bss_info_changed       = ath5k_bss_info_changed,
+        .prepare_multicast      = ath5k_prepare_multicast,
+        .configure_filter       = ath5k_configure_filter,
+        /* .set_tim             = not implemented */
+        .set_key                = ath5k_set_key,
+        /* .update_tkip_key     = not implemented */
+        /* .hw_scan             = not implemented */
+        .sw_scan_start          = ath5k_sw_scan_start,
+        .sw_scan_complete       = ath5k_sw_scan_complete,
+        .get_stats              = ath5k_get_stats,
+        /* .get_tkip_seq        = not implemented */
+        /* .set_frag_threshold  = not implemented */
+        /* .set_rts_threshold   = not implemented */
+        /* .sta_add             = not implemented */
+        /* .sta_remove          = not implemented */
+        /* .sta_notify          = not implemented */
+        .conf_tx                = ath5k_conf_tx,
+        .get_tsf                = ath5k_get_tsf,
+        .set_tsf                = ath5k_set_tsf,
+        .reset_tsf              = ath5k_reset_tsf,
+        /* .tx_last_beacon      = not implemented */
+        /* .ampdu_action        = not needed */
+        .get_survey             = ath5k_get_survey,
+        .set_coverage_class     = ath5k_set_coverage_class,
+        /* .rfkill_poll         = not implemented */
+        /* .flush               = not implemented */
+        /* .channel_switch      = not implemented */
+        /* .napi_poll           = not implemented */
+        .set_antenna            = ath5k_set_antenna,
+        .get_antenna            = ath5k_get_antenna,
+        .set_ringparam          = ath5k_set_ringparam,
+        .get_ringparam          = ath5k_get_ringparam,
+};
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c
new file mode 100644
index 000000000000..f2c0c236392f
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/pci.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/pci.h>
+#include <linux/pci-aspm.h>
+#include <linux/etherdevice.h>
+#include "../ath.h"
+#include "ath5k.h"
+#include "debug.h"
+#include "base.h"
+#include "reg.h"
+
+/* Known PCI ids */
+static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
+        { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
+        { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
+        { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
+        { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
+        { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
+        { PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
+        { PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
+        { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
+        { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
+        { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
+        { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
+        { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
+        { 0 }
+};
+MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
+
+/* return bus cachesize in 4B word units */
+static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
+{
+        struct ath5k_softc *sc = (struct ath5k_softc *) common->priv;
+        u8 u8tmp;
+
+        pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
+        *csz = (int)u8tmp;
+
+        /*
+         * This check was put in to avoid "unpleasant" consequences if
+         * the bootrom has not fully initialized all PCI devices.
+         * Sometimes the cache line size register is not set
+         */
+
+        if (*csz == 0)
+                *csz = L1_CACHE_BYTES >> 2;   /* Use the default size */
+}
+
+/*
+ * Read from eeprom
+ */
+static bool
+ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
+{
+        struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
+        u32 status, timeout;
+
+        /*
+         * Initialize EEPROM access
+         */
+        if (ah->ah_version == AR5K_AR5210) {
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
+                (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
+        } else {
+                ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
+                AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
+                                AR5K_EEPROM_CMD_READ);
+        }
+
+        for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
+                status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
+                if (status & AR5K_EEPROM_STAT_RDDONE) {
+                        if (status & AR5K_EEPROM_STAT_RDERR)
+                                return false;
+                        *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
+                                        0xffff);
+                        return true;
+                }
+                udelay(15);
+        }
+
+        return false;
+}
+
+int ath5k_hw_read_srev(struct ath5k_hw *ah)
+{
+        ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
+        return 0;
+}
+
+/*
+ * Read the MAC address from eeprom or platform_data
+ */
+static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
+{
+        u8 mac_d[ETH_ALEN] = {};
+        u32 total, offset;
+        u16 data;
+        int octet;
+
+        AR5K_EEPROM_READ(0x20, data);
+
+        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
+                AR5K_EEPROM_READ(offset, data);
+
+                total += data;
+                mac_d[octet + 1] = data & 0xff;
+                mac_d[octet] = data >> 8;
+                octet += 2;
+        }
+
+        if (!total || total == 3 * 0xffff)
+                return -EINVAL;
+
+        memcpy(mac, mac_d, ETH_ALEN);
+
+        return 0;
+}
+
+
+/* Common ath_bus_opts structure */
+static const struct ath_bus_ops ath_pci_bus_ops = {
+        .ath_bus_type = ATH_PCI,
+        .read_cachesize = ath5k_pci_read_cachesize,
+        .eeprom_read = ath5k_pci_eeprom_read,
+        .eeprom_read_mac = ath5k_pci_eeprom_read_mac,
+};
+
+/********************\
+* PCI Initialization *
+\********************/
+
+static int __devinit
+ath5k_pci_probe(struct pci_dev *pdev,
+                const struct pci_device_id *id)
+{
+        void __iomem *mem;
+        struct ath5k_softc *sc;
+        struct ieee80211_hw *hw;
+        int ret;
+        u8 csz;
+
+        /*
+         * L0s needs to be disabled on all ath5k cards.
+         *
+         * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
+         * by default in the future in 2.6.36) this will also mean both L1 and
+         * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
+         * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
+         * though but cannot currently undue the effect of a blacklist, for
+         * details you can read pcie_aspm_sanity_check() and see how it adjusts
+         * the device link capability.
+         *
+         * It may be possible in the future to implement some PCI API to allow
+         * drivers to override blacklists for pre 1.1 PCIe but for now it is
+         * best to accept that both L0s and L1 will be disabled completely for
+         * distributions shipping with CONFIG_PCIEASPM rather than having this
+         * issue present. Motivation for adding this new API will be to help
+         * with power consumption for some of these devices.
+         */
+        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
+
+        ret = pci_enable_device(pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "can't enable device\n");
+                goto err;
+        }
+
+        /* XXX 32-bit addressing only */
+        ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+        if (ret) {
+                dev_err(&pdev->dev, "32-bit DMA not available\n");
+                goto err_dis;
+        }
+
+        /*
+         * Cache line size is used to size and align various
+         * structures used to communicate with the hardware.
+         */
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
+        if (csz == 0) {
+                /*
+                 * Linux 2.4.18 (at least) writes the cache line size
+                 * register as a 16-bit wide register which is wrong.
+                 * We must have this setup properly for rx buffer
+                 * DMA to work so force a reasonable value here if it
+                 * comes up zero.
+                 */
+                csz = L1_CACHE_BYTES >> 2;
+                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
+        }
+        /*
+         * The default setting of latency timer yields poor results,
+         * set it to the value used by other systems.  It may be worth
+         * tweaking this setting more.
+         */
+        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
+
+        /* Enable bus mastering */
+        pci_set_master(pdev);
+
+        /*
+         * Disable the RETRY_TIMEOUT register (0x41) to keep
+         * PCI Tx retries from interfering with C3 CPU state.
+         */
+        pci_write_config_byte(pdev, 0x41, 0);
+
+        ret = pci_request_region(pdev, 0, "ath5k");
+        if (ret) {
+                dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
+                goto err_dis;
+        }
+
+        mem = pci_iomap(pdev, 0, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
+                ret = -EIO;
+                goto err_reg;
+        }
+
+        /*
+         * Allocate hw (mac80211 main struct)
+         * and hw->priv (driver private data)
+         */
+        hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
+        if (hw == NULL) {
+                dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
+                ret = -ENOMEM;
+                goto err_map;
+        }
+
+        dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
+
+        sc = hw->priv;
+        sc->hw = hw;
+        sc->pdev = pdev;
+        sc->dev = &pdev->dev;
+        sc->irq = pdev->irq;
+        sc->devid = id->device;
+        sc->iobase = mem; /* So we can unmap it on detach */
+
+        /* Initialize */
+        ret = ath5k_init_softc(sc, &ath_pci_bus_ops);
+        if (ret)
+                goto err_free;
+
+        /* Set private data */
+        pci_set_drvdata(pdev, hw);
+
+        return 0;
+err_free:
+        ieee80211_free_hw(hw);
+err_map:
+        pci_iounmap(pdev, mem);
+err_reg:
+        pci_release_region(pdev, 0);
+err_dis:
+        pci_disable_device(pdev);
+err:
+        return ret;
+}
+
+static void __devexit
+ath5k_pci_remove(struct pci_dev *pdev)
+{
+        struct ieee80211_hw *hw = pci_get_drvdata(pdev);
+        struct ath5k_softc *sc = hw->priv;
+
+        ath5k_deinit_softc(sc);
+        pci_iounmap(pdev, sc->iobase);
+        pci_release_region(pdev, 0);
+        pci_disable_device(pdev);
+        ieee80211_free_hw(hw);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int ath5k_pci_suspend(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct ieee80211_hw *hw = pci_get_drvdata(pdev);
+        struct ath5k_softc *sc = hw->priv;
+
+        ath5k_led_off(sc);
+        return 0;
+}
+
+static int ath5k_pci_resume(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct ieee80211_hw *hw = pci_get_drvdata(pdev);
+        struct ath5k_softc *sc = hw->priv;
+
+        /*
+         * Suspend/Resume resets the PCI configuration space, so we have to
+         * re-disable the RETRY_TIMEOUT register (0x41) to keep
+         * PCI Tx retries from interfering with C3 CPU state
+         */
+        pci_write_config_byte(pdev, 0x41, 0);
+
+        ath5k_led_enable(sc);
+        return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
+#define ATH5K_PM_OPS    (&ath5k_pm_ops)
+#else
+#define ATH5K_PM_OPS    NULL
+#endif /* CONFIG_PM_SLEEP */
+
+static struct pci_driver ath5k_pci_driver = {
+        .name           = KBUILD_MODNAME,
+        .id_table       = ath5k_pci_id_table,
+        .probe          = ath5k_pci_probe,
+        .remove         = __devexit_p(ath5k_pci_remove),
+        .driver.pm      = ATH5K_PM_OPS,
+};
+
+/*
+ * Module init/exit functions
+ */
+static int __init
+init_ath5k_pci(void)
+{
+        int ret;
+
+        ret = pci_register_driver(&ath5k_pci_driver);
+        if (ret) {
+                printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static void __exit
+exit_ath5k_pci(void)
+{
+        pci_unregister_driver(&ath5k_pci_driver);
+}
+
+module_init(init_ath5k_pci);
+module_exit(exit_ath5k_pci);
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index 86fdb6ddfaaa..712a9ac4000e 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -31,87 +31,169 @@
 #include "debug.h"
 #include "base.h"
 
+/*
+ * AR5212+ can use higher rates for ack transmition
+ * based on current tx rate instead of the base rate.
+ * It does this to better utilize channel usage.
+ * This is a mapping between G rates (that cover both
+ * CCK and OFDM) and ack rates that we use when setting
+ * rate -> duration table. This mapping is hw-based so
+ * don't change anything.
+ *
+ * To enable this functionality we must set
+ * ah->ah_ack_bitrate_high to true else base rate is
+ * used (1Mb for CCK, 6Mb for OFDM).
+ */
+static const unsigned int ack_rates_high[] =
+/* Tx   -> ACK  */
+/* 1Mb  -> 1Mb  */      { 0,
+/* 2MB  -> 2Mb  */      1,
+/* 5.5Mb -> 2Mb */      1,
+/* 11Mb -> 2Mb  */      1,
+/* 6Mb  -> 6Mb  */      4,
+/* 9Mb  -> 6Mb  */      4,
+/* 12Mb -> 12Mb */      6,
+/* 18Mb -> 12Mb */      6,
+/* 24Mb -> 24Mb */      8,
+/* 36Mb -> 24Mb */      8,
+/* 48Mb -> 24Mb */      8,
+/* 54Mb -> 24Mb */      8 };
+
 /*******************\
-* Generic functions *
+* Helper functions *
 \*******************/
 
 /**
- * ath5k_hw_set_opmode - Set PCU operating mode
+ * ath5k_hw_get_frame_duration - Get tx time of a frame
  *
  * @ah: The &struct ath5k_hw
- * @op_mode: &enum nl80211_iftype operating mode
+ * @len: Frame's length in bytes
+ * @rate: The @struct ieee80211_rate
  *
- * Initialize PCU for the various operating modes (AP/STA etc)
+ * Calculate tx duration of a frame given it's rate and length
+ * It extends ieee80211_generic_frame_duration for non standard
+ * bwmodes.
  */
-int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
+int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
+                int len, struct ieee80211_rate *rate, bool shortpre)
 {
-        struct ath_common *common = ath5k_hw_common(ah);
-        u32 pcu_reg, beacon_reg, low_id, high_id;
+        struct ath5k_softc *sc = ah->ah_sc;
+        int sifs, preamble, plcp_bits, sym_time;
+        int bitrate, bits, symbols, symbol_bits;
+        int dur;
+
+        /* Fallback */
+        if (!ah->ah_bwmode) {
+                __le16 raw_dur = ieee80211_generic_frame_duration(sc->hw,
+                                        NULL, len, rate);
+
+                /* subtract difference between long and short preamble */
+                dur = le16_to_cpu(raw_dur);
+                if (shortpre)
+                        dur -= 96;
+
+                return dur;
+        }
 
-        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
+        bitrate = rate->bitrate;
+        preamble = AR5K_INIT_OFDM_PREAMPLE_TIME;
+        plcp_bits = AR5K_INIT_OFDM_PLCP_BITS;
+        sym_time = AR5K_INIT_OFDM_SYMBOL_TIME;
 
-        /* Preserve rest settings */
-        pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
-        pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
-                        | AR5K_STA_ID1_KEYSRCH_MODE
-                        | (ah->ah_version == AR5K_AR5210 ?
-                        (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                sifs = AR5K_INIT_SIFS_TURBO;
+                preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                sifs = AR5K_INIT_SIFS_HALF_RATE;
+                preamble *= 2;
+                sym_time *= 2;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                sifs = AR5K_INIT_SIFS_QUARTER_RATE;
+                preamble *= 4;
+                sym_time *= 4;
+                break;
+        default:
+                sifs = AR5K_INIT_SIFS_DEFAULT_BG;
+                break;
+        }
 
-        beacon_reg = 0;
+        bits = plcp_bits + (len << 3);
+        /* Bit rate is in 100Kbits */
+        symbol_bits = bitrate * sym_time;
+        symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
 
-        switch (op_mode) {
-        case NL80211_IFTYPE_ADHOC:
-                pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
-                beacon_reg |= AR5K_BCR_ADHOC;
-                if (ah->ah_version == AR5K_AR5210)
-                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
-                else
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
-                break;
+        dur = sifs + preamble + (sym_time * symbols);
 
-        case NL80211_IFTYPE_AP:
-        case NL80211_IFTYPE_MESH_POINT:
-                pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
-                beacon_reg |= AR5K_BCR_AP;
-                if (ah->ah_version == AR5K_AR5210)
-                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
-                else
-                        AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
-                break;
+        return dur;
+}
 
-        case NL80211_IFTYPE_STATION:
-                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
-                        | (ah->ah_version == AR5K_AR5210 ?
-                                AR5K_STA_ID1_PWR_SV : 0);
-        case NL80211_IFTYPE_MONITOR:
-                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
-                        | (ah->ah_version == AR5K_AR5210 ?
-                                AR5K_STA_ID1_NO_PSPOLL : 0);
-                break;
+/**
+ * ath5k_hw_get_default_slottime - Get the default slot time for current mode
+ *
+ * @ah: The &struct ath5k_hw
+ */
+unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
+{
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        unsigned int slot_time;
 
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                slot_time = AR5K_INIT_SLOT_TIME_TURBO;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE;
+                break;
+        case AR5K_BWMODE_DEFAULT:
         default:
-                return -EINVAL;
+                slot_time = AR5K_INIT_SLOT_TIME_DEFAULT;
+                if ((channel->hw_value & CHANNEL_CCK) && !ah->ah_short_slot)
+                        slot_time = AR5K_INIT_SLOT_TIME_B;
+                break;
         }
 
-        /*
-         * Set PCU registers
-         */
-        low_id = get_unaligned_le32(common->macaddr);
-        high_id = get_unaligned_le16(common->macaddr + 4);
-        ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
-        ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
+        return slot_time;
+}
 
-        /*
-         * Set Beacon Control Register on 5210
-         */
-        if (ah->ah_version == AR5K_AR5210)
-                ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
+/**
+ * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
+ *
+ * @ah: The &struct ath5k_hw
+ */
+unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
+{
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        unsigned int sifs;
 
-        return 0;
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                sifs = AR5K_INIT_SIFS_TURBO;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                sifs = AR5K_INIT_SIFS_HALF_RATE;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                sifs = AR5K_INIT_SIFS_QUARTER_RATE;
+                break;
+        case AR5K_BWMODE_DEFAULT:
+                sifs = AR5K_INIT_SIFS_DEFAULT_BG;
+        default:
+                if (channel->hw_value & CHANNEL_5GHZ)
+                        sifs = AR5K_INIT_SIFS_DEFAULT_A;
+                break;
+        }
+
+        return sifs;
 }
 
 /**
- * ath5k_hw_update - Update MIB counters (mac layer statistics)
+ * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics)
  *
  * @ah: The &struct ath5k_hw
  *
@@ -133,35 +215,72 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
         stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
 }
 
+
+/******************\
+* ACK/CTS Timeouts *
+\******************/
+
 /**
- * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
+ * ath5k_hw_write_rate_duration - fill rate code to duration table
  *
- * @ah: The &struct ath5k_hw
- * @high: Flag to determine if we want to use high transmition rate
- * for ACKs or not
+ * @ah: the &struct ath5k_hw
+ * @mode: one of enum ath5k_driver_mode
+ *
+ * Write the rate code to duration table upon hw reset. This is a helper for
+ * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
+ * the hardware, based on current mode, for each rate. The rates which are
+ * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
+ * different rate code so we write their value twice (one for long preamble
+ * and one for short).
+ *
+ * Note: Band doesn't matter here, if we set the values for OFDM it works
+ * on both a and g modes. So all we have to do is set values for all g rates
+ * that include all OFDM and CCK rates.
  *
- * If high flag is set, we tell hw to use a set of control rates based on
- * the current transmition rate (check out control_rates array inside reset.c).
- * If not hw just uses the lowest rate available for the current modulation
- * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
  */
-void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
+static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
 {
-        if (ah->ah_version != AR5K_AR5212)
-                return;
-        else {
-                u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
-                if (high)
-                        AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct ieee80211_rate *rate;
+        unsigned int i;
+        /* 802.11g covers both OFDM and CCK */
+        u8 band = IEEE80211_BAND_2GHZ;
+
+        /* Write rate duration table */
+        for (i = 0; i < sc->sbands[band].n_bitrates; i++) {
+                u32 reg;
+                u16 tx_time;
+
+                if (ah->ah_ack_bitrate_high)
+                        rate = &sc->sbands[band].bitrates[ack_rates_high[i]];
+                /* CCK -> 1Mb */
+                else if (i < 4)
+                        rate = &sc->sbands[band].bitrates[0];
+                /* OFDM -> 6Mb */
                 else
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
-        }
-}
+                        rate = &sc->sbands[band].bitrates[4];
 
+                /* Set ACK timeout */
+                reg = AR5K_RATE_DUR(rate->hw_value);
 
-/******************\
-* ACK/CTS Timeouts *
-\******************/
+                /* An ACK frame consists of 10 bytes. If you add the FCS,
+                 * which ieee80211_generic_frame_duration() adds,
+                 * its 14 bytes. Note we use the control rate and not the
+                 * actual rate for this rate. See mac80211 tx.c
+                 * ieee80211_duration() for a brief description of
+                 * what rate we should choose to TX ACKs. */
+                tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false);
+
+                ath5k_hw_reg_write(ah, tx_time, reg);
+
+                if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
+                        continue;
+
+                tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true);
+                ath5k_hw_reg_write(ah, tx_time,
+                        reg + (AR5K_SET_SHORT_PREAMBLE << 2));
+        }
+}
 
 /**
  * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
@@ -199,85 +318,10 @@ static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
         return 0;
 }
 
-/**
- * ath5k_hw_htoclock - Translate usec to hw clock units
- *
- * @ah: The &struct ath5k_hw
- * @usec: value in microseconds
- */
-unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
-{
-        return usec * ath5k_hw_get_clockrate(ah);
-}
-
-/**
- * ath5k_hw_clocktoh - Translate hw clock units to usec
- * @clock: value in hw clock units
- */
-unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
-{
-        return clock / ath5k_hw_get_clockrate(ah);
-}
-
-/**
- * ath5k_hw_get_clockrate - Get the clock rate for current mode
- *
- * @ah: The &struct ath5k_hw
- */
-unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
-{
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-        int clock;
-
-        if (channel->hw_value & CHANNEL_5GHZ)
-                clock = 40; /* 802.11a */
-        else if (channel->hw_value & CHANNEL_CCK)
-                clock = 22; /* 802.11b */
-        else
-                clock = 44; /* 802.11g */
-
-        /* Clock rate in turbo modes is twice the normal rate */
-        if (channel->hw_value & CHANNEL_TURBO)
-                clock *= 2;
-
-        return clock;
-}
 
-/**
- * ath5k_hw_get_default_slottime - Get the default slot time for current mode
- *
- * @ah: The &struct ath5k_hw
- */
-static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
-{
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-
-        if (channel->hw_value & CHANNEL_TURBO)
-                return 6; /* both turbo modes */
-
-        if (channel->hw_value & CHANNEL_CCK)
-                return 20; /* 802.11b */
-
-        return 9; /* 802.11 a/g */
-}
-
-/**
- * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
- *
- * @ah: The &struct ath5k_hw
- */
-static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
-{
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-
-        if (channel->hw_value & CHANNEL_TURBO)
-                return 8; /* both turbo modes */
-
-        if (channel->hw_value & CHANNEL_5GHZ)
-                return 16; /* 802.11a */
-
-        return 10; /* 802.11 b/g */
-}
+/*******************\
+* RX filter Control *
+\*******************/
 
 /**
  * ath5k_hw_set_lladdr - Set station id
@@ -308,27 +352,26 @@ int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
 }
 
 /**
- * ath5k_hw_set_associd - Set BSSID for association
+ * ath5k_hw_set_bssid - Set current BSSID on hw
  *
  * @ah: The &struct ath5k_hw
- * @bssid: BSSID
- * @assoc_id: Assoc id
  *
- * Sets the BSSID which trigers the "SME Join" operation
+ * Sets the current BSSID and BSSID mask we have from the
+ * common struct into the hardware
  */
-void ath5k_hw_set_associd(struct ath5k_hw *ah)
+void ath5k_hw_set_bssid(struct ath5k_hw *ah)
 {
         struct ath_common *common = ath5k_hw_common(ah);
         u16 tim_offset = 0;
 
         /*
-         * Set simple BSSID mask on 5212
+         * Set BSSID mask on 5212
          */
         if (ah->ah_version == AR5K_AR5212)
                 ath_hw_setbssidmask(common);
 
         /*
-         * Set BSSID which triggers the "SME Join" operation
+         * Set BSSID
          */
         ath5k_hw_reg_write(ah,
                            get_unaligned_le32(common->curbssid),
@@ -360,39 +403,6 @@ void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
                 ath_hw_setbssidmask(common);
 }
 
-/************\
-* RX Control *
-\************/
-
-/**
- * ath5k_hw_start_rx_pcu - Start RX engine
- *
- * @ah: The &struct ath5k_hw
- *
- * Starts RX engine on PCU so that hw can process RXed frames
- * (ACK etc).
- *
- * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
- */
-void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
-{
-        AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
-}
-
-/**
- * at5k_hw_stop_rx_pcu - Stop RX engine
- *
- * @ah: The &struct ath5k_hw
- *
- * Stops RX engine on PCU
- *
- * TODO: Detach ANI here
- */
-void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
-{
-        AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
-}
-
 /*
  * Set multicast filter
  */
@@ -455,7 +465,7 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
         }
 
         /*
-         * The AR5210 uses promiscous mode to detect radar activity
+         * The AR5210 uses promiscuous mode to detect radar activity
          */
         if (ah->ah_version == AR5K_AR5210 &&
                         (filter & AR5K_RX_FILTER_RADARERR)) {
@@ -496,6 +506,10 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
 {
         u32 tsf_lower, tsf_upper1, tsf_upper2;
         int i;
+        unsigned long flags;
+
+        /* This code is time critical - we don't want to be interrupted here */
+        local_irq_save(flags);
 
         /*
          * While reading TSF upper and then lower part, the clock is still
@@ -518,6 +532,8 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
                 tsf_upper1 = tsf_upper2;
         }
 
+        local_irq_restore(flags);
+
         WARN_ON( i == ATH5K_MAX_TSF_READ );
 
         return (((u64)tsf_upper1 << 32) | tsf_lower);
@@ -601,7 +617,7 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
         /* Timer3 marks the end of our ATIM window
          * a zero length window is not allowed because
          * we 'll get no beacons */
-        timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
+        timer3 = next_beacon + 1;
 
         /*
          * Set the beacon register and enable all timers.
@@ -641,218 +657,281 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
 
 }
 
+/**
+ * ath5k_check_timer_win - Check if timer B is timer A + window
+ *
+ * @a: timer a (before b)
+ * @b: timer b (after a)
+ * @window: difference between a and b
+ * @intval: timers are increased by this interval
+ *
+ * This helper function checks if timer B is timer A + window and covers
+ * cases where timer A or B might have already been updated or wrapped
+ * around (Timers are 16 bit).
+ *
+ * Returns true if O.K.
+ */
+static inline bool
+ath5k_check_timer_win(int a, int b, int window, int intval)
+{
+        /*
+         * 1.) usually B should be A + window
+         * 2.) A already updated, B not updated yet
+         * 3.) A already updated and has wrapped around
+         * 4.) B has wrapped around
+         */
+        if ((b - a == window) ||                                /* 1.) */
+            (a - b == intval - window) ||                       /* 2.) */
+            ((a | 0x10000) - b == intval - window) ||           /* 3.) */
+            ((b | 0x10000) - a == window))                      /* 4.) */
+                return true; /* O.K. */
+        return false;
+}
 
-/*********************\
-* Key table functions *
-\*********************/
-
-/*
- * Reset a key entry on the table
+/**
+ * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct
+ *
+ * @ah: The &struct ath5k_hw
+ * @intval: beacon interval
+ *
+ * This is a workaround for IBSS mode:
+ *
+ * The need for this function arises from the fact that we have 4 separate
+ * HW timer registers (TIMER0 - TIMER3), which are closely related to the
+ * next beacon target time (NBTT), and that the HW updates these timers
+ * separately based on the current TSF value. The hardware increments each
+ * timer by the beacon interval, when the local TSF converted to TU is equal
+ * to the value stored in the timer.
+ *
+ * The reception of a beacon with the same BSSID can update the local HW TSF
+ * at any time - this is something we can't avoid. If the TSF jumps to a
+ * time which is later than the time stored in a timer, this timer will not
+ * be updated until the TSF in TU wraps around at 16 bit (the size of the
+ * timers) and reaches the time which is stored in the timer.
+ *
+ * The problem is that these timers are closely related to TIMER0 (NBTT) and
+ * that they define a time "window". When the TSF jumps between two timers
+ * (e.g. ATIM and NBTT), the one in the past will be left behind (not
+ * updated), while the one in the future will be updated every beacon
+ * interval. This causes the window to get larger, until the TSF wraps
+ * around as described above and the timer which was left behind gets
+ * updated again. But - because the beacon interval is usually not an exact
+ * divisor of the size of the timers (16 bit), an unwanted "window" between
+ * these timers has developed!
+ *
+ * This is especially important with the ATIM window, because during
+ * the ATIM window only ATIM frames and no data frames are allowed to be
+ * sent, which creates transmission pauses after each beacon. This symptom
+ * has been described as "ramping ping" because ping times increase linearly
+ * for some time and then drop down again. A wrong window on the DMA beacon
+ * timer has the same effect, so we check for these two conditions.
+ *
+ * Returns true if O.K.
  */
-int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
+bool
+ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
 {
-        unsigned int i, type;
-        u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
+        unsigned int nbtt, atim, dma;
 
-        AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
+        nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
+        atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
+        dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
 
-        type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
+        /* NOTE: SWBA is different. Having a wrong window there does not
+         * stop us from sending data and this condition is catched thru
+         * other means (SWBA interrupt) */
 
-        for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
-                ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
+        if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
+            ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
+                                  intval))
+                return true; /* O.K. */
+        return false;
+}
 
-        /* Reset associated MIC entry if TKIP
-         * is enabled located at offset (entry + 64) */
-        if (type == AR5K_KEYTABLE_TYPE_TKIP) {
-                AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE);
-                for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
-                        ath5k_hw_reg_write(ah, 0,
-                                AR5K_KEYTABLE_OFF(micentry, i));
-        }
+/**
+ * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
+ *
+ * @ah: The &struct ath5k_hw
+ * @coverage_class: IEEE 802.11 coverage class number
+ *
+ * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
+ */
+void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
+{
+        /* As defined by IEEE 802.11-2007 17.3.8.6 */
+        int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
+        int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
+        int cts_timeout = ack_timeout;
 
-        /*
-         * Set NULL encryption on AR5212+
-         *
-         * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
-         *       AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
-         *
-         * Note2: Windows driver (ndiswrapper) sets this to
-         *        0x00000714 instead of 0x00000007
-         */
-        if (ah->ah_version >= AR5K_AR5211) {
-                ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
-                                AR5K_KEYTABLE_TYPE(entry));
+        ath5k_hw_set_ifs_intervals(ah, slot_time);
+        ath5k_hw_set_ack_timeout(ah, ack_timeout);
+        ath5k_hw_set_cts_timeout(ah, cts_timeout);
 
-                if (type == AR5K_KEYTABLE_TYPE_TKIP) {
-                        ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
-                                AR5K_KEYTABLE_TYPE(micentry));
-                }
-        }
+        ah->ah_coverage_class = coverage_class;
+}
 
-        return 0;
+/***************************\
+* Init/Start/Stop functions *
+\***************************/
+
+/**
+ * ath5k_hw_start_rx_pcu - Start RX engine
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Starts RX engine on PCU so that hw can process RXed frames
+ * (ACK etc).
+ *
+ * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
+ */
+void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
+{
+        AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
 }
 
-static
-int ath5k_keycache_type(const struct ieee80211_key_conf *key)
+/**
+ * at5k_hw_stop_rx_pcu - Stop RX engine
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Stops RX engine on PCU
+ */
+void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
 {
-        switch (key->alg) {
-        case ALG_TKIP:
-                return AR5K_KEYTABLE_TYPE_TKIP;
-        case ALG_CCMP:
-                return AR5K_KEYTABLE_TYPE_CCM;
-        case ALG_WEP:
-                if (key->keylen == WLAN_KEY_LEN_WEP40)
-                        return AR5K_KEYTABLE_TYPE_40;
-                else if (key->keylen == WLAN_KEY_LEN_WEP104)
-                        return AR5K_KEYTABLE_TYPE_104;
-                return -EINVAL;
-        default:
-                return -EINVAL;
-        }
-        return -EINVAL;
+        AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
 }
 
-/*
- * Set a key entry on the table
+/**
+ * ath5k_hw_set_opmode - Set PCU operating mode
+ *
+ * @ah: The &struct ath5k_hw
+ * @op_mode: &enum nl80211_iftype operating mode
+ *
+ * Configure PCU for the various operating modes (AP/STA etc)
  */
-int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
-                const struct ieee80211_key_conf *key, const u8 *mac)
+int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
 {
-        unsigned int i;
-        int keylen;
-        __le32 key_v[5] = {};
-        __le32 key0 = 0, key1 = 0;
-        __le32 *rxmic, *txmic;
-        int keytype;
-        u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
-        bool is_tkip;
-        const u8 *key_ptr;
+        struct ath_common *common = ath5k_hw_common(ah);
+        u32 pcu_reg, beacon_reg, low_id, high_id;
 
-        is_tkip = (key->alg == ALG_TKIP);
+        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
 
-        /*
-         * key->keylen comes in from mac80211 in bytes.
-         * TKIP is 128 bit + 128 bit mic
-         */
-        keylen = (is_tkip) ? (128 / 8) : key->keylen;
+        /* Preserve rest settings */
+        pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
+        pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
+                        | AR5K_STA_ID1_KEYSRCH_MODE
+                        | (ah->ah_version == AR5K_AR5210 ?
+                        (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
 
-        if (entry > AR5K_KEYTABLE_SIZE ||
-                (is_tkip && micentry > AR5K_KEYTABLE_SIZE))
-                return -EOPNOTSUPP;
+        beacon_reg = 0;
 
-        if (unlikely(keylen > 16))
-                return -EOPNOTSUPP;
+        switch (op_mode) {
+        case NL80211_IFTYPE_ADHOC:
+                pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
+                beacon_reg |= AR5K_BCR_ADHOC;
+                if (ah->ah_version == AR5K_AR5210)
+                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
+                else
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
+                break;
 
-        keytype = ath5k_keycache_type(key);
-        if (keytype < 0)
-                return keytype;
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_MESH_POINT:
+                pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
+                beacon_reg |= AR5K_BCR_AP;
+                if (ah->ah_version == AR5K_AR5210)
+                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
+                else
+                        AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
+                break;
 
-        /*
-         * each key block is 6 bytes wide, written as pairs of
-         * alternating 32 and 16 bit le values.
-         */
-        key_ptr = key->key;
-        for (i = 0; keylen >= 6; keylen -= 6) {
-                memcpy(&key_v[i], key_ptr, 6);
-                i += 2;
-                key_ptr += 6;
-        }
-        if (keylen)
-                memcpy(&key_v[i], key_ptr, keylen);
+        case NL80211_IFTYPE_STATION:
+                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
+                        | (ah->ah_version == AR5K_AR5210 ?
+                                AR5K_STA_ID1_PWR_SV : 0);
+        case NL80211_IFTYPE_MONITOR:
+                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
+                        | (ah->ah_version == AR5K_AR5210 ?
+                                AR5K_STA_ID1_NO_PSPOLL : 0);
+                break;
 
-        /* intentionally corrupt key until mic is installed */
-        if (is_tkip) {
-                key0 = key_v[0] = ~key_v[0];
-                key1 = key_v[1] = ~key_v[1];
+        default:
+                return -EINVAL;
         }
 
-        for (i = 0; i < ARRAY_SIZE(key_v); i++)
-                ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
-                                AR5K_KEYTABLE_OFF(entry, i));
-
-        ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
-
-        if (is_tkip) {
-                /* Install rx/tx MIC */
-                rxmic = (__le32 *) &key->key[16];
-                txmic = (__le32 *) &key->key[24];
+        /*
+         * Set PCU registers
+         */
+        low_id = get_unaligned_le32(common->macaddr);
+        high_id = get_unaligned_le16(common->macaddr + 4);
+        ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
+        ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
 
-                if (ah->ah_combined_mic) {
-                        key_v[0] = rxmic[0];
-                        key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16);
-                        key_v[2] = rxmic[1];
-                        key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff);
-                        key_v[4] = txmic[1];
-                } else {
-                        key_v[0] = rxmic[0];
-                        key_v[1] = 0;
-                        key_v[2] = rxmic[1];
-                        key_v[3] = 0;
-                        key_v[4] = 0;
-                }
-                for (i = 0; i < ARRAY_SIZE(key_v); i++)
-                        ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
-                                AR5K_KEYTABLE_OFF(micentry, i));
-
-                ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
-                        AR5K_KEYTABLE_TYPE(micentry));
-                ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry));
-                ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry));
-
-                /* restore first 2 words of key */
-                ath5k_hw_reg_write(ah, le32_to_cpu(~key0),
-                        AR5K_KEYTABLE_OFF(entry, 0));
-                ath5k_hw_reg_write(ah, le32_to_cpu(~key1),
-                        AR5K_KEYTABLE_OFF(entry, 1));
-        }
+        /*
+         * Set Beacon Control Register on 5210
+         */
+        if (ah->ah_version == AR5K_AR5210)
+                ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
 
-        return ath5k_hw_set_key_lladdr(ah, entry, mac);
+        return 0;
 }
 
-int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
+void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
+                                                                u8 mode)
 {
-        u32 low_id, high_id;
-
-         /* Invalid entry (key table overflow) */
-        AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
+        /* Set bssid and bssid mask */
+        ath5k_hw_set_bssid(ah);
 
-        /*
-         * MAC may be NULL if it's a broadcast key. In this case no need to
-         * to compute get_unaligned_le32 and get_unaligned_le16 as we
-         * already know it.
-         */
-        if (!mac) {
-                low_id = 0xffffffff;
-                high_id = 0xffff | AR5K_KEYTABLE_VALID;
-        } else {
-                low_id = get_unaligned_le32(mac);
-                high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID;
-        }
+        /* Set PCU config */
+        ath5k_hw_set_opmode(ah, op_mode);
 
-        ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
-        ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
+        /* Write rate duration table only on AR5212 and if
+         * virtual interface has already been brought up
+         * XXX: rethink this after new mode changes to
+         * mac80211 are integrated */
+        if (ah->ah_version == AR5K_AR5212 &&
+                ah->ah_sc->nvifs)
+                ath5k_hw_write_rate_duration(ah);
 
-        return 0;
-}
+        /* Set RSSI/BRSSI thresholds
+         *
+         * Note: If we decide to set this value
+         * dynamicaly, have in mind that when AR5K_RSSI_THR
+         * register is read it might return 0x40 if we haven't
+         * wrote anything to it plus BMISS RSSI threshold is zeroed.
+         * So doing a save/restore procedure here isn't the right
+         * choice. Instead store it on ath5k_hw */
+        ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
+                                AR5K_TUNE_BMISS_THRES <<
+                                AR5K_RSSI_THR_BMISS_S),
+                                AR5K_RSSI_THR);
+
+        /* MIC QoS support */
+        if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
+                ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
+                ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
+        }
 
-/**
- * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
- *
- * @ah: The &struct ath5k_hw
- * @coverage_class: IEEE 802.11 coverage class number
- *
- * Sets slot time, ACK timeout and CTS timeout for given coverage class.
- */
-void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
-{
-        /* As defined by IEEE 802.11-2007 17.3.8.6 */
-        int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
-        int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
-        int cts_timeout = ack_timeout;
+        /* QoS NOACK Policy */
+        if (ah->ah_version == AR5K_AR5212) {
+                ath5k_hw_reg_write(ah,
+                        AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
+                        AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
+                        AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
+                        AR5K_QOS_NOACK);
+        }
 
-        ath5k_hw_set_slot_time(ah, slot_time);
-        ath5k_hw_set_ack_timeout(ah, ack_timeout);
-        ath5k_hw_set_cts_timeout(ah, cts_timeout);
+        /* Restore slot time and ACK timeouts */
+        if (ah->ah_coverage_class > 0)
+                ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
 
-        ah->ah_coverage_class = coverage_class;
+        /* Set ACK bitrate mode (see ack_rates_high) */
+        if (ah->ah_version == AR5K_AR5212) {
+                u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
+                if (ah->ah_ack_bitrate_high)
+                        AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
+                else
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
+        }
+        return;
 }
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 6284c389ba18..55441913344d 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -29,6 +29,95 @@
 #include "rfbuffer.h"
 #include "rfgain.h"
 
+
+/******************\
+* Helper functions *
+\******************/
+
+/*
+ * Get the PHY Chip revision
+ */
+u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
+{
+        unsigned int i;
+        u32 srev;
+        u16 ret;
+
+        /*
+         * Set the radio chip access register
+         */
+        switch (chan) {
+        case CHANNEL_2GHZ:
+                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
+                break;
+        case CHANNEL_5GHZ:
+                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+                break;
+        default:
+                return 0;
+        }
+
+        mdelay(2);
+
+        /* ...wait until PHY is ready and read the selected radio revision */
+        ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
+
+        for (i = 0; i < 8; i++)
+                ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
+
+        if (ah->ah_version == AR5K_AR5210) {
+                srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
+                ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
+        } else {
+                srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
+                ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
+                                ((srev & 0x0f) << 4), 8);
+        }
+
+        /* Reset to the 5GHz mode */
+        ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+
+        return ret;
+}
+
+/*
+ * Check if a channel is supported
+ */
+bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
+{
+        /* Check if the channel is in our supported range */
+        if (flags & CHANNEL_2GHZ) {
+                if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
+                    (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
+                        return true;
+        } else if (flags & CHANNEL_5GHZ)
+                if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
+                    (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
+                        return true;
+
+        return false;
+}
+
+bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
+{
+        u8 refclk_freq;
+
+        if ((ah->ah_radio == AR5K_RF5112) ||
+        (ah->ah_radio == AR5K_RF5413) ||
+        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                refclk_freq = 40;
+        else
+                refclk_freq = 32;
+
+        if ((channel->center_freq % refclk_freq != 0) &&
+        ((channel->center_freq % refclk_freq < 10) ||
+        (channel->center_freq % refclk_freq > 22)))
+                return true;
+        else
+                return false;
+}
+
 /*
  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  */
@@ -110,12 +199,124 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
         return data;
 }
 
+/**
+ * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
+ *
+ * @ah: the &struct ath5k_hw
+ * @channel: the currently set channel upon reset
+ *
+ * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
+ * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
+ *
+ * Since delta slope is floating point we split it on its exponent and
+ * mantissa and provide these values on hw.
+ *
+ * For more infos i think this patent is related
+ * http://www.freepatentsonline.com/7184495.html
+ */
+static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
+        struct ieee80211_channel *channel)
+{
+        /* Get exponent and mantissa and set it */
+        u32 coef_scaled, coef_exp, coef_man,
+                ds_coef_exp, ds_coef_man, clock;
+
+        BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
+                !(channel->hw_value & CHANNEL_OFDM));
+
+        /* Get coefficient
+         * ALGO: coef = (5 * clock / carrier_freq) / 2
+         * we scale coef by shifting clock value by 24 for
+         * better precision since we use integers */
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                clock = 40 * 2;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                clock = 40 / 2;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                clock = 40 / 4;
+                break;
+        default:
+                clock = 40;
+                break;
+        }
+        coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
+
+        /* Get exponent
+         * ALGO: coef_exp = 14 - highest set bit position */
+        coef_exp = ilog2(coef_scaled);
+
+        /* Doesn't make sense if it's zero*/
+        if (!coef_scaled || !coef_exp)
+                return -EINVAL;
+
+        /* Note: we've shifted coef_scaled by 24 */
+        coef_exp = 14 - (coef_exp - 24);
+
+
+        /* Get mantissa (significant digits)
+         * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
+        coef_man = coef_scaled +
+                (1 << (24 - coef_exp - 1));
+
+        /* Calculate delta slope coefficient exponent
+         * and mantissa (remove scaling) and set them on hw */
+        ds_coef_man = coef_man >> (24 - coef_exp);
+        ds_coef_exp = coef_exp - 16;
+
+        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
+                AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
+        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
+                AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
+
+        return 0;
+}
+
+int ath5k_hw_phy_disable(struct ath5k_hw *ah)
+{
+        /*Just a try M.F.*/
+        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+
+        return 0;
+}
+
+/*
+ * Wait for synth to settle
+ */
+static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
+                        struct ieee80211_channel *channel)
+{
+        /*
+         * On 5211+ read activation -> rx delay
+         * and use it (100ns steps).
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                u32 delay;
+                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
+                        AR5K_PHY_RX_DELAY_M;
+                delay = (channel->hw_value & CHANNEL_CCK) ?
+                        ((delay << 2) / 22) : (delay / 10);
+                if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
+                        delay = delay << 1;
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
+                        delay = delay << 2;
+                /* XXX: /2 on turbo ? Let's be safe
+                 * for now */
+                udelay(100 + delay);
+        } else {
+                mdelay(1);
+        }
+}
+
+
 /**********************\
 * RF Gain optimization *
 \**********************/
 
 /*
- * This code is used to optimize rf gain on different environments
+ * This code is used to optimize RF gain on different environments
  * (temperature mostly) based on feedback from a power detector.
  *
  * It's only used on RF5111 and RF5112, later RF chips seem to have
@@ -134,11 +335,11 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  * http://madwifi-project.org/ticket/1659
  * with various measurements and diagrams
  *
- * TODO: Deal with power drops due to probes by setting an apropriate
+ * TODO: Deal with power drops due to probes by setting an appropriate
  * tx power on the probe packets ! Make this part of the calibration process.
  */
 
-/* Initialize ah_gain durring attach */
+/* Initialize ah_gain during attach */
 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
 {
         /* Initialize the gain optimization values */
@@ -302,7 +503,7 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
 }
 
 /* Perform gain_F adjustment by choosing the right set
- * of parameters from rf gain optimization ladder */
+ * of parameters from RF gain optimization ladder */
 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
 {
         const struct ath5k_gain_opt *go;
@@ -367,7 +568,7 @@ done:
         return ret;
 }
 
-/* Main callback for thermal rf gain calibration engine
+/* Main callback for thermal RF gain calibration engine
  * Check for a new gain reading and schedule an adjustment
  * if needed.
  *
@@ -433,13 +634,13 @@ done:
         return ah->ah_gain.g_state;
 }
 
-/* Write initial rf gain table to set the RF sensitivity
+/* Write initial RF gain table to set the RF sensitivity
  * this one works on all RF chips and has nothing to do
  * with gain_F calibration */
-int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
+static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
 {
         const struct ath5k_ini_rfgain *ath5k_rfg;
-        unsigned int i, size;
+        unsigned int i, size, index;
 
         switch (ah->ah_radio) {
         case AR5K_RF5111:
@@ -471,17 +672,11 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
                 return -EINVAL;
         }
 
-        switch (freq) {
-        case AR5K_INI_RFGAIN_2GHZ:
-        case AR5K_INI_RFGAIN_5GHZ:
-                break;
-        default:
-                return -EINVAL;
-        }
+        index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
 
         for (i = 0; i < size; i++) {
                 AR5K_REG_WAIT(i);
-                ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
+                ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
                         (u32)ath5k_rfg[i].rfg_register);
         }
 
@@ -494,12 +689,11 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
 * RF Registers setup *
 \********************/
 
-
 /*
- * Setup RF registers by writing rf buffer on hw
+ * Setup RF registers by writing RF buffer on hw
  */
-int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
-                unsigned int mode)
+static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
+        struct ieee80211_channel *channel, unsigned int mode)
 {
         const struct ath5k_rf_reg *rf_regs;
         const struct ath5k_ini_rfbuffer *ini_rfb;
@@ -571,7 +765,7 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 return -EINVAL;
         }
 
-        /* If it's the first time we set rf buffer, allocate
+        /* If it's the first time we set RF buffer, allocate
          * ah->ah_rf_banks based on ah->ah_rf_banks_size
          * we set above */
         if (ah->ah_rf_banks == NULL) {
@@ -652,6 +846,11 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 
         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 
+        /* Set turbo mode (N/A on RF5413) */
+        if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
+        (ah->ah_radio != AR5K_RF5413))
+                ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
+
         /* Bank Modifications (chip-specific) */
         if (ah->ah_radio == AR5K_RF5111) {
 
@@ -691,7 +890,23 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
                                                 AR5K_RF_PLO_SEL, true);
 
-                /* TODO: Half/quarter channel support */
+                /* Tweak power detectors for half/quarter rate support */
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
+                ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
+                        u8 wait_i;
+
+                        ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
+                                                AR5K_RF_WAIT_S, true);
+
+                        wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
+                                                        0x1f : 0x10;
+
+                        ath5k_hw_rfb_op(ah, rf_regs, wait_i,
+                                                AR5K_RF_WAIT_I, true);
+                        ath5k_hw_rfb_op(ah, rf_regs, 3,
+                                                AR5K_RF_MAX_TIME, true);
+
+                }
         }
 
         if (ah->ah_radio == AR5K_RF5112) {
@@ -789,8 +1004,20 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
                                                 AR5K_RF_GAIN_I, true);
 
-                /* TODO: Half/quarter channel support */
+                /* Tweak power detector for half/quarter rates */
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
+                ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
+                        u8 pd_delay;
+
+                        pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
+                                                        0xf : 0x8;
+
+                        ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
+                                                AR5K_RF_PD_PERIOD_A, true);
+                        ath5k_hw_rfb_op(ah, rf_regs, 0xf,
+                                                AR5K_RF_PD_DELAY_A, true);
 
+                }
         }
 
         if (ah->ah_radio == AR5K_RF5413 &&
@@ -822,25 +1049,7 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 \**************************/
 
 /*
- * Check if a channel is supported
- */
-bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
-{
-        /* Check if the channel is in our supported range */
-        if (flags & CHANNEL_2GHZ) {
-                if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
-                    (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
-                        return true;
-        } else if (flags & CHANNEL_5GHZ)
-                if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
-                    (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
-                        return true;
-
-        return false;
-}
-
-/*
- * Convertion needed for RF5110
+ * Conversion needed for RF5110
  */
 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 {
@@ -879,7 +1088,7 @@ static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
 }
 
 /*
- * Convertion needed for 5111
+ * Conversion needed for 5111
  */
 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
                 struct ath5k_athchan_2ghz *athchan)
@@ -1045,7 +1254,8 @@ static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
 /*
  * Set a channel on the radio chip
  */
-int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
+static int ath5k_hw_channel(struct ath5k_hw *ah,
+                struct ieee80211_channel *channel)
 {
         int ret;
         /*
@@ -1071,6 +1281,7 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
         case AR5K_RF5111:
                 ret = ath5k_hw_rf5111_channel(ah, channel);
                 break;
+        case AR5K_RF2317:
         case AR5K_RF2425:
                 ret = ath5k_hw_rf2425_channel(ah, channel);
                 break;
@@ -1092,7 +1303,6 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
         }
 
         ah->ah_current_channel = channel;
-        ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
 
         return 0;
 }
@@ -1101,18 +1311,12 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
   PHY calibration
 \*****************/
 
-static int sign_extend(int val, const int nbits)
-{
-        int order = BIT(nbits-1);
-        return (val ^ order) - order;
-}
-
 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
 {
         s32 val;
 
         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
-        return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
+        return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
 }
 
 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
@@ -1180,22 +1384,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
                 return;
         }
 
-        switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
-        case CHANNEL_A:
-        case CHANNEL_T:
-        case CHANNEL_XR:
-                ee_mode = AR5K_EEPROM_MODE_11A;
-                break;
-        case CHANNEL_G:
-        case CHANNEL_TG:
-                ee_mode = AR5K_EEPROM_MODE_11G;
-                break;
-        default:
-        case CHANNEL_B:
-                ee_mode = AR5K_EEPROM_MODE_11B;
-                break;
-        }
-
+        ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
 
         /* completed NF calibration, test threshold */
         nf = ath5k_hw_read_measured_noise_floor(ah);
@@ -1257,7 +1446,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
          * Disable beacons and RX/TX queues, wait
          */
         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
-                AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
+                AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
 
@@ -1336,7 +1525,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
          * Re-enable RX/TX and beacons
          */
         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
-                AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
+                AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
 
         return 0;
@@ -1377,7 +1566,7 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
 
         /* protect against divide by 0 and loss of sign bits */
         if (i_coffd == 0 || q_coffd < 2)
-                return -1;
+                return 0;
 
         i_coff = (-iq_corr) / i_coffd;
         i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
@@ -1424,31 +1613,12 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
         return ret;
 }
 
+
 /***************************\
 * Spur mitigation functions *
 \***************************/
 
-bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
-                                struct ieee80211_channel *channel)
-{
-        u8 refclk_freq;
-
-        if ((ah->ah_radio == AR5K_RF5112) ||
-        (ah->ah_radio == AR5K_RF5413) ||
-        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                refclk_freq = 40;
-        else
-                refclk_freq = 32;
-
-        if ((channel->center_freq % refclk_freq != 0) &&
-        ((channel->center_freq % refclk_freq < 10) ||
-        (channel->center_freq % refclk_freq > 22)))
-                return true;
-        else
-                return false;
-}
-
-void
+static void
 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
                                 struct ieee80211_channel *channel)
 {
@@ -1477,7 +1647,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
         spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
         spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
         /* XXX: Half/Quarter channels ?*/
-        if (channel->hw_value & CHANNEL_TURBO)
+        if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
                 spur_detection_window *= 2;
 
         for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
@@ -1506,32 +1676,43 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
                  * Calculate deltas:
                  * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
                  * spur_delta_phase -> spur_offset / chip_freq << 11
-                 * Note: Both values have 100KHz resolution
+                 * Note: Both values have 100Hz resolution
                  */
-                /* XXX: Half/Quarter rate channels ? */
-                switch (channel->hw_value) {
-                case CHANNEL_A:
-                        /* Both sample_freq and chip_freq are 40MHz */
-                        spur_delta_phase = (spur_offset << 17) / 25;
-                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
-                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
-                        break;
-                case CHANNEL_G:
-                        /* sample_freq -> 40MHz chip_freq -> 44MHz
-                         * (for b compatibility) */
-                        spur_freq_sigma_delta = (spur_offset << 8) / 55;
-                        spur_delta_phase = (spur_offset << 17) / 25;
-                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
-                        break;
-                case CHANNEL_T:
-                case CHANNEL_TG:
+                switch (ah->ah_bwmode) {
+                case AR5K_BWMODE_40MHZ:
                         /* Both sample_freq and chip_freq are 80MHz */
                         spur_delta_phase = (spur_offset << 16) / 25;
                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
-                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
                         break;
+                case AR5K_BWMODE_10MHZ:
+                        /* Both sample_freq and chip_freq are 20MHz (?) */
+                        spur_delta_phase = (spur_offset << 18) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
+                case AR5K_BWMODE_5MHZ:
+                        /* Both sample_freq and chip_freq are 10MHz (?) */
+                        spur_delta_phase = (spur_offset << 19) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
                 default:
-                        return;
+                        if (channel->hw_value == CHANNEL_A) {
+                                /* Both sample_freq and chip_freq are 40MHz */
+                                spur_delta_phase = (spur_offset << 17) / 25;
+                                spur_freq_sigma_delta =
+                                                (spur_delta_phase >> 10);
+                                symbol_width =
+                                        AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        } else {
+                                /* sample_freq -> 40MHz chip_freq -> 44MHz
+                                 * (for b compatibility) */
+                                spur_delta_phase = (spur_offset << 17) / 25;
+                                spur_freq_sigma_delta =
+                                                (spur_offset << 8) / 55;
+                                symbol_width =
+                                        AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        }
+                        break;
                 }
 
                 /* Calculate pilot and magnitude masks */
@@ -1582,7 +1763,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
                         else if (curr_sym_off >= 31 && curr_sym_off <= 46)
                                 mag_mask[2] |=
                                         plt_mag_map << (curr_sym_off - 31) * 2;
-                        else if (curr_sym_off >= 46 && curr_sym_off <= 53)
+                        else if (curr_sym_off >= 47 && curr_sym_off <= 53)
                                 mag_mask[3] |=
                                         plt_mag_map << (curr_sym_off - 47) * 2;
 
@@ -1671,63 +1852,6 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
         }
 }
 
-/********************\
-  Misc PHY functions
-\********************/
-
-int ath5k_hw_phy_disable(struct ath5k_hw *ah)
-{
-        /*Just a try M.F.*/
-        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
-
-        return 0;
-}
-
-/*
- * Get the PHY Chip revision
- */
-u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
-{
-        unsigned int i;
-        u32 srev;
-        u16 ret;
-
-        /*
-         * Set the radio chip access register
-         */
-        switch (chan) {
-        case CHANNEL_2GHZ:
-                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
-                break;
-        case CHANNEL_5GHZ:
-                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
-                break;
-        default:
-                return 0;
-        }
-
-        mdelay(2);
-
-        /* ...wait until PHY is ready and read the selected radio revision */
-        ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
-
-        for (i = 0; i < 8; i++)
-                ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
-
-        if (ah->ah_version == AR5K_AR5210) {
-                srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
-                ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
-        } else {
-                srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
-                ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
-                                ((srev & 0x0f) << 4), 8);
-        }
-
-        /* Reset to the 5GHz mode */
-        ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
-
-        return ret;
-}
 
 /*****************\
 * Antenna control *
@@ -1821,7 +1945,8 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
         struct ieee80211_channel *channel = ah->ah_current_channel;
         bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
         bool use_def_for_sg;
-        u8 def_ant, tx_ant, ee_mode;
+        int ee_mode;
+        u8 def_ant, tx_ant;
         u32 sta_id1 = 0;
 
         /* if channel is not initialized yet we can't set the antennas
@@ -1833,20 +1958,8 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
 
         def_ant = ah->ah_def_ant;
 
-        switch (channel->hw_value & CHANNEL_MODES) {
-        case CHANNEL_A:
-        case CHANNEL_T:
-        case CHANNEL_XR:
-                ee_mode = AR5K_EEPROM_MODE_11A;
-                break;
-        case CHANNEL_G:
-        case CHANNEL_TG:
-                ee_mode = AR5K_EEPROM_MODE_11G;
-                break;
-        case CHANNEL_B:
-                ee_mode = AR5K_EEPROM_MODE_11B;
-                break;
-        default:
+        ee_mode = ath5k_eeprom_mode_from_channel(channel);
+        if (ee_mode < 0) {
                 ATH5K_ERR(ah->ah_sc,
                         "invalid channel: %d\n", channel->center_freq);
                 return;
@@ -2088,7 +2201,7 @@ ath5k_create_power_curve(s16 pmin, s16 pmax,
 /*
  * Get the surrounding per-channel power calibration piers
  * for a given frequency so that we can interpolate between
- * them and come up with an apropriate dataset for our current
+ * them and come up with an appropriate dataset for our current
  * channel.
  */
 static void
@@ -2274,20 +2387,20 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
 
         switch (channel->hw_value & CHANNEL_MODES) {
         case CHANNEL_A:
-                ctl_mode |= AR5K_CTL_11A;
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
+                        ctl_mode |= AR5K_CTL_TURBO;
+                else
+                        ctl_mode |= AR5K_CTL_11A;
                 break;
         case CHANNEL_G:
-                ctl_mode |= AR5K_CTL_11G;
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
+                        ctl_mode |= AR5K_CTL_TURBOG;
+                else
+                        ctl_mode |= AR5K_CTL_11G;
                 break;
         case CHANNEL_B:
                 ctl_mode |= AR5K_CTL_11B;
                 break;
-        case CHANNEL_T:
-                ctl_mode |= AR5K_CTL_TURBO;
-                break;
-        case CHANNEL_TG:
-                ctl_mode |= AR5K_CTL_TURBOG;
-                break;
         case CHANNEL_XR:
                 /* Fall through */
         default:
@@ -2481,7 +2594,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
 
 /* Write PCDAC values on hw */
 static void
-ath5k_setup_pcdac_table(struct ath5k_hw *ah)
+ath5k_write_pcdac_table(struct ath5k_hw *ah)
 {
         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
         int     i;
@@ -2505,7 +2618,7 @@ ath5k_setup_pcdac_table(struct ath5k_hw *ah)
 /*
  * Set the gain boundaries and create final Power to PDADC table
  *
- * We can have up to 4 pd curves, we need to do a simmilar process
+ * We can have up to 4 pd curves, we need to do a similar process
  * as we do for RF5112. This time we don't have an edge_flag but we
  * set the gain boundaries on a separate register.
  */
@@ -2630,10 +2743,12 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
 
 /* Write PDADC values on hw */
 static void
-ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
-                        u8 pdcurves, u8 *pdg_to_idx)
+ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
 {
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
+        u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
+        u8 pdcurves = ee->ee_pd_gains[ee_mode];
         u32 reg;
         u8 i;
 
@@ -2711,13 +2826,13 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
         u32 target = channel->center_freq;
         int pdg, i;
 
-        /* Get surounding freq piers for this channel */
+        /* Get surrounding freq piers for this channel */
         ath5k_get_chan_pcal_surrounding_piers(ah, channel,
                                                 &pcinfo_L,
                                                 &pcinfo_R);
 
         /* Loop over pd gain curves on
-         * surounding freq piers by index */
+         * surrounding freq piers by index */
         for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
 
                 /* Fill curves in reverse order
@@ -2808,7 +2923,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 }
 
                 /* Interpolate between curves
-                 * of surounding freq piers to
+                 * of surrounding freq piers to
                  * get the final curve for this
                  * pd gain. Re-use tmpL for interpolation
                  * output */
@@ -2832,7 +2947,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
 
         /* Fill min and max power levels for this
          * channel by interpolating the values on
-         * surounding channels to complete the dataset */
+         * surrounding channels to complete the dataset */
         ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
                                         (s16) pcinfo_L->freq,
                                         (s16) pcinfo_R->freq,
@@ -2843,8 +2958,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                                         (s16) pcinfo_R->freq,
                                         pcinfo_L->max_pwr, pcinfo_R->max_pwr);
 
-        /* We are ready to go, fill PCDAC/PDADC
-         * table and write settings on hardware */
+        /* Fill PCDAC/PDADC table */
         switch (type) {
         case AR5K_PWRTABLE_LINEAR_PCDAC:
                 /* For RF5112 we can have one or two curves
@@ -2857,9 +2971,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                  * match max power value with max
                  * table index */
                 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
-
-                /* Write settings on hw */
-                ath5k_setup_pcdac_table(ah);
                 break;
         case AR5K_PWRTABLE_PWR_TO_PCDAC:
                 /* We are done for RF5111 since it has only
@@ -2869,9 +2980,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 /* No rate powertable adjustment for RF5111 */
                 ah->ah_txpower.txp_min_idx = 0;
                 ah->ah_txpower.txp_offset = 0;
-
-                /* Write settings on hw */
-                ath5k_setup_pcdac_table(ah);
                 break;
         case AR5K_PWRTABLE_PWR_TO_PDADC:
                 /* Set PDADC boundaries and fill
@@ -2879,9 +2987,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
                                                 ee->ee_pd_gains[ee_mode]);
 
-                /* Write settings on hw */
-                ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
-
                 /* Set txp.offset, note that table_min
                  * can be negative */
                 ah->ah_txpower.txp_offset = table_min[0];
@@ -2890,9 +2995,20 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 return -EINVAL;
         }
 
+        ah->ah_txpower.txp_setup = true;
+
         return 0;
 }
 
+/* Write power table for current channel to hw */
+static void
+ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
+{
+        if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
+                ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
+        else
+                ath5k_write_pcdac_table(ah);
+}
 
 /*
  * Per-rate tx power setting
@@ -2981,19 +3097,21 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
 
         /* Min/max in 0.25dB units */
         ah->ah_txpower.txp_min_pwr = 2 * rates[7];
-        ah->ah_txpower.txp_max_pwr = 2 * rates[0];
+        ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
         ah->ah_txpower.txp_ofdm = rates[7];
 }
 
 
 /*
- * Set transmition power
+ * Set transmission power
  */
-int
+static int
 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
-                u8 ee_mode, u8 txpower)
+                 u8 txpower)
 {
         struct ath5k_rate_pcal_info rate_info;
+        struct ieee80211_channel *curr_channel = ah->ah_current_channel;
+        int ee_mode;
         u8 type;
         int ret;
 
@@ -3002,14 +3120,18 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 return -EINVAL;
         }
 
-        /* Reset TX power values */
-        memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
-        ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
-        ah->ah_txpower.txp_min_pwr = 0;
-        ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
+        ee_mode = ath5k_eeprom_mode_from_channel(channel);
+        if (ee_mode < 0) {
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return -EINVAL;
+        }
 
         /* Initialize TX power table */
         switch (ah->ah_radio) {
+        case AR5K_RF5110:
+                /* TODO */
+                return 0;
         case AR5K_RF5111:
                 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
                 break;
@@ -3027,24 +3149,37 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 return -EINVAL;
         }
 
-        /* FIXME: Only on channel/mode change */
-        ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
-        if (ret)
-                return ret;
+        /*
+         * If we don't change channel/mode skip tx powertable calculation
+         * and use the cached one.
+         */
+        if (!ah->ah_txpower.txp_setup ||
+            (channel->hw_value != curr_channel->hw_value) ||
+            (channel->center_freq != curr_channel->center_freq)) {
+                /* Reset TX power values */
+                memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
+                ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
+
+                /* Calculate the powertable */
+                ret = ath5k_setup_channel_powertable(ah, channel,
+                                                        ee_mode, type);
+                if (ret)
+                        return ret;
+        }
+
+        /* Write table on hw */
+        ath5k_write_channel_powertable(ah, ee_mode, type);
 
         /* Limit max power if we have a CTL available */
         ath5k_get_max_ctl_power(ah, channel);
 
-        /* FIXME: Tx power limit for this regdomain
-         * XXX: Mac80211/CRDA will do that anyway ? */
-
         /* FIXME: Antenna reduction stuff */
 
         /* FIXME: Limit power on turbo modes */
 
         /* FIXME: TPC scale reduction */
 
-        /* Get surounding channels for per-rate power table
+        /* Get surrounding channels for per-rate power table
          * calibration */
         ath5k_get_rate_pcal_data(ah, channel, &rate_info);
 
@@ -3088,31 +3223,223 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 
 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
 {
-        /*Just a try M.F.*/
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-        u8 ee_mode;
+        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
+                "changing txpower to %d\n", txpower);
 
-        switch (channel->hw_value & CHANNEL_MODES) {
-        case CHANNEL_A:
-        case CHANNEL_T:
-        case CHANNEL_XR:
-                ee_mode = AR5K_EEPROM_MODE_11A;
-                break;
-        case CHANNEL_G:
-        case CHANNEL_TG:
-                ee_mode = AR5K_EEPROM_MODE_11G;
-                break;
-        case CHANNEL_B:
-                ee_mode = AR5K_EEPROM_MODE_11B;
-                break;
-        default:
-                ATH5K_ERR(ah->ah_sc,
-                        "invalid channel: %d\n", channel->center_freq);
+        return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
+}
+
+/*************\
+ Init function
+\*************/
+
+int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
+                      u8 mode, bool fast)
+{
+        struct ieee80211_channel *curr_channel;
+        int ret, i;
+        u32 phy_tst1;
+        ret = 0;
+
+        /*
+         * Sanity check for fast flag
+         * Don't try fast channel change when changing modulation
+         * mode/band. We check for chip compatibility on
+         * ath5k_hw_reset.
+         */
+        curr_channel = ah->ah_current_channel;
+        if (fast && (channel->hw_value != curr_channel->hw_value))
                 return -EINVAL;
+
+        /*
+         * On fast channel change we only set the synth parameters
+         * while PHY is running, enable calibration and skip the rest.
+         */
+        if (fast) {
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
+                                    AR5K_PHY_RFBUS_REQ_REQUEST);
+                for (i = 0; i < 100; i++) {
+                        if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
+                                break;
+                        udelay(5);
+                }
+                /* Failed */
+                if (i >= 100)
+                        return -EIO;
+
+                /* Set channel and wait for synth */
+                ret = ath5k_hw_channel(ah, channel);
+                if (ret)
+                        return ret;
+
+                ath5k_hw_wait_for_synth(ah, channel);
         }
 
-        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
-                "changing txpower to %d\n", txpower);
+        /*
+         * Set TX power
+         *
+         * Note: We need to do that before we set
+         * RF buffer settings on 5211/5212+ so that we
+         * properly set curve indices.
+         */
+        ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
+                        ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
+        if (ret)
+                return ret;
+
+        /* Write OFDM timings on 5212*/
+        if (ah->ah_version == AR5K_AR5212 &&
+                channel->hw_value & CHANNEL_OFDM) {
+
+                ret = ath5k_hw_write_ofdm_timings(ah, channel);
+                if (ret)
+                        return ret;
+
+                /* Spur info is available only from EEPROM versions
+                 * greater than 5.3, but the EEPROM routines will use
+                 * static values for older versions */
+                if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
+                        ath5k_hw_set_spur_mitigation_filter(ah,
+                                                            channel);
+        }
+
+        /* If we used fast channel switching
+         * we are done, release RF bus and
+         * fire up NF calibration.
+         *
+         * Note: Only NF calibration due to
+         * channel change, not AGC calibration
+         * since AGC is still running !
+         */
+        if (fast) {
+                /*
+                 * Release RF Bus grant
+                 */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
+                                    AR5K_PHY_RFBUS_REQ_REQUEST);
+
+                /*
+                 * Start NF calibration
+                 */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_NF);
 
-        return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
+                return ret;
+        }
+
+        /*
+         * For 5210 we do all initialization using
+         * initvals, so we don't have to modify
+         * any settings (5210 also only supports
+         * a/aturbo modes)
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+
+                /*
+                 * Write initial RF gain settings
+                 * This should work for both 5111/5112
+                 */
+                ret = ath5k_hw_rfgain_init(ah, channel->band);
+                if (ret)
+                        return ret;
+
+                mdelay(1);
+
+                /*
+                 * Write RF buffer
+                 */
+                ret = ath5k_hw_rfregs_init(ah, channel, mode);
+                if (ret)
+                        return ret;
+
+                /*Enable/disable 802.11b mode on 5111
+                (enable 2111 frequency converter + CCK)*/
+                if (ah->ah_radio == AR5K_RF5111) {
+                        if (mode == AR5K_MODE_11B)
+                                AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
+                                    AR5K_TXCFG_B_MODE);
+                        else
+                                AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
+                                    AR5K_TXCFG_B_MODE);
+                }
+
+        } else if (ah->ah_version == AR5K_AR5210) {
+                mdelay(1);
+                /* Disable phy and wait */
+                ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+                mdelay(1);
+        }
+
+        /* Set channel on PHY */
+        ret = ath5k_hw_channel(ah, channel);
+        if (ret)
+                return ret;
+
+        /*
+         * Enable the PHY and wait until completion
+         * This includes BaseBand and Synthesizer
+         * activation.
+         */
+        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
+
+        ath5k_hw_wait_for_synth(ah, channel);
+
+        /*
+         * Perform ADC test to see if baseband is ready
+         * Set tx hold and check adc test register
+         */
+        phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
+        ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
+        for (i = 0; i <= 20; i++) {
+                if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
+                        break;
+                udelay(200);
+        }
+        ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
+
+        /*
+         * Start automatic gain control calibration
+         *
+         * During AGC calibration RX path is re-routed to
+         * a power detector so we don't receive anything.
+         *
+         * This method is used to calibrate some static offsets
+         * used together with on-the fly I/Q calibration (the
+         * one performed via ath5k_hw_phy_calibrate), which doesn't
+         * interrupt rx path.
+         *
+         * While rx path is re-routed to the power detector we also
+         * start a noise floor calibration to measure the
+         * card's noise floor (the noise we measure when we are not
+         * transmitting or receiving anything).
+         *
+         * If we are in a noisy environment, AGC calibration may time
+         * out and/or noise floor calibration might timeout.
+         */
+        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
+
+        /* At the same time start I/Q calibration for QAM constellation
+         * -no need for CCK- */
+        ah->ah_calibration = false;
+        if (!(mode == AR5K_MODE_11B)) {
+                ah->ah_calibration = true;
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
+                                AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
+                                AR5K_PHY_IQ_RUN);
+        }
+
+        /* Wait for gain calibration to finish (we check for I/Q calibration
+         * during ath5k_phy_calibrate) */
+        if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
+                        AR5K_PHY_AGCCTL_CAL, 0, false)) {
+                ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
+                        channel->center_freq);
+        }
+
+        /* Restore antenna mode */
+        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
+
+        return ret;
 }
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 4186ff4c6e9c..b18c5021aac3 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -25,6 +25,68 @@ Queue Control Unit, DFS Control Unit Functions
 #include "debug.h"
 #include "base.h"
 
+
+/******************\
+* Helper functions *
+\******************/
+
+/*
+ * Get number of pending frames
+ * for a specific queue [5211+]
+ */
+u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
+{
+        u32 pending;
+        AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
+
+        /* Return if queue is declared inactive */
+        if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
+                return false;
+
+        /* XXX: How about AR5K_CFG_TXCNT ? */
+        if (ah->ah_version == AR5K_AR5210)
+                return false;
+
+        pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
+        pending &= AR5K_QCU_STS_FRMPENDCNT;
+
+        /* It's possible to have no frames pending even if TXE
+         * is set. To indicate that q has not stopped return
+         * true */
+        if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
+                return true;
+
+        return pending;
+}
+
+/*
+ * Set a transmit queue inactive
+ */
+void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+{
+        if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
+                return;
+
+        /* This queue will be skipped in further operations */
+        ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
+        /*For SIMR setup*/
+        AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
+}
+
+/*
+ * Make sure cw is a power of 2 minus 1 and smaller than 1024
+ */
+static u16 ath5k_cw_validate(u16 cw_req)
+{
+        u32 cw = 1;
+        cw_req = min(cw_req, (u16)1023);
+
+        while (cw < cw_req)
+                cw = (cw << 1) | 1;
+
+        return cw;
+}
+
 /*
  * Get properties for a transmit queue
  */
@@ -39,21 +101,41 @@ int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
  * Set properties for a transmit queue
  */
 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
-                                const struct ath5k_txq_info *queue_info)
+                                const struct ath5k_txq_info *qinfo)
 {
+        struct ath5k_txq_info *qi;
+
         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 
-        if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
+        qi = &ah->ah_txq[queue];
+
+        if (qi->tqi_type == AR5K_TX_QUEUE_INACTIVE)
                 return -EIO;
 
-        memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
+        /* copy and validate values */
+        qi->tqi_type = qinfo->tqi_type;
+        qi->tqi_subtype = qinfo->tqi_subtype;
+        qi->tqi_flags = qinfo->tqi_flags;
+        /*
+         * According to the docs: Although the AIFS field is 8 bit wide,
+         * the maximum supported value is 0xFC. Setting it higher than that
+         * will cause the DCU to hang.
+         */
+        qi->tqi_aifs = min(qinfo->tqi_aifs, (u8)0xFC);
+        qi->tqi_cw_min = ath5k_cw_validate(qinfo->tqi_cw_min);
+        qi->tqi_cw_max = ath5k_cw_validate(qinfo->tqi_cw_max);
+        qi->tqi_cbr_period = qinfo->tqi_cbr_period;
+        qi->tqi_cbr_overflow_limit = qinfo->tqi_cbr_overflow_limit;
+        qi->tqi_burst_time = qinfo->tqi_burst_time;
+        qi->tqi_ready_time = qinfo->tqi_ready_time;
 
         /*XXX: Is this supported on 5210 ?*/
-        if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
-                        ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
-                        (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
-                        queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
-                ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
+        /*XXX: Is this correct for AR5K_WME_AC_VI,VO ???*/
+        if ((qinfo->tqi_type == AR5K_TX_QUEUE_DATA &&
+                ((qinfo->tqi_subtype == AR5K_WME_AC_VI) ||
+                 (qinfo->tqi_subtype == AR5K_WME_AC_VO))) ||
+             qinfo->tqi_type == AR5K_TX_QUEUE_UAPSD)
+                qi->tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
 
         return 0;
 }
@@ -70,8 +152,8 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
         /*
          * Get queue by type
          */
-        /*5210 only has 2 queues*/
-        if (ah->ah_version == AR5K_AR5210) {
+        /* 5210 only has 2 queues */
+        if (ah->ah_capabilities.cap_queues.q_tx_num == 2) {
                 switch (queue_type) {
                 case AR5K_TX_QUEUE_DATA:
                         queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
@@ -138,392 +220,431 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
         return queue;
 }
 
-/*
- * Get number of pending frames
- * for a specific queue [5211+]
- */
-u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
-{
-        u32 pending;
-        AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
-
-        /* Return if queue is declared inactive */
-        if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return false;
-
-        /* XXX: How about AR5K_CFG_TXCNT ? */
-        if (ah->ah_version == AR5K_AR5210)
-                return false;
-
-        pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
-        pending &= AR5K_QCU_STS_FRMPENDCNT;
-
-        /* It's possible to have no frames pending even if TXE
-         * is set. To indicate that q has not stopped return
-         * true */
-        if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
-                return true;
 
-        return pending;
-}
+/*******************************\
+* Single QCU/DCU initialization *
+\*******************************/
 
 /*
- * Set a transmit queue inactive
+ * Set tx retry limits on DCU
  */
-void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
+                                  unsigned int queue)
 {
-        if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
-                return;
+        /* Single data queue on AR5210 */
+        if (ah->ah_version == AR5K_AR5210) {
+                struct ath5k_txq_info *tq = &ah->ah_txq[queue];
 
-        /* This queue will be skipped in further operations */
-        ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
-        /*For SIMR setup*/
-        AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
+                if (queue > 0)
+                        return;
+
+                ath5k_hw_reg_write(ah,
+                        (tq->tqi_cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
+                        | AR5K_REG_SM(ah->ah_retry_long,
+                                      AR5K_NODCU_RETRY_LMT_SLG_RETRY)
+                        | AR5K_REG_SM(ah->ah_retry_short,
+                                      AR5K_NODCU_RETRY_LMT_SSH_RETRY)
+                        | AR5K_REG_SM(ah->ah_retry_long,
+                                      AR5K_NODCU_RETRY_LMT_LG_RETRY)
+                        | AR5K_REG_SM(ah->ah_retry_short,
+                                      AR5K_NODCU_RETRY_LMT_SH_RETRY),
+                        AR5K_NODCU_RETRY_LMT);
+        /* DCU on AR5211+ */
+        } else {
+                ath5k_hw_reg_write(ah,
+                        AR5K_REG_SM(ah->ah_retry_long,
+                                    AR5K_DCU_RETRY_LMT_RTS)
+                        | AR5K_REG_SM(ah->ah_retry_long,
+                                      AR5K_DCU_RETRY_LMT_STA_RTS)
+                        | AR5K_REG_SM(max(ah->ah_retry_long, ah->ah_retry_short),
+                                      AR5K_DCU_RETRY_LMT_STA_DATA),
+                        AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
+        }
 }
 
-/*
- * Set DFS properties for a transmit queue on DCU
+/**
+ * ath5k_hw_reset_tx_queue - Initialize a single hw queue
+ *
+ * @ah The &struct ath5k_hw
+ * @queue The hw queue number
+ *
+ * Set DFS properties for the given transmit queue on DCU
+ * and configures all queue-specific parameters.
  */
 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
 {
-        u32 cw_min, cw_max, retry_lg, retry_sh;
         struct ath5k_txq_info *tq = &ah->ah_txq[queue];
 
         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 
         tq = &ah->ah_txq[queue];
 
-        if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
+        /* Skip if queue inactive or if we are on AR5210
+         * that doesn't have QCU/DCU */
+        if ((ah->ah_version == AR5K_AR5210) ||
+        (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE))
                 return 0;
 
-        if (ah->ah_version == AR5K_AR5210) {
-                /* Only handle data queues, others will be ignored */
-                if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
-                        return 0;
-
-                /* Set Slot time */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
-                        AR5K_SLOT_TIME);
-                /* Set ACK_CTS timeout */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
-                        AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
-                /* Set Transmit Latency */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_TRANSMIT_LATENCY_TURBO :
-                        AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
-
-                /* Set IFS0 */
-                if (ah->ah_turbo) {
-                         ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
-                                (ah->ah_aifs + tq->tqi_aifs) *
-                                AR5K_INIT_SLOT_TIME_TURBO) <<
-                                AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
-                                AR5K_IFS0);
-                } else {
-                        ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
-                                (ah->ah_aifs + tq->tqi_aifs) *
-                                AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
-                                AR5K_INIT_SIFS, AR5K_IFS0);
-                }
-
-                /* Set IFS1 */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
-                        AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
-                /* Set AR5K_PHY_SETTLING */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
-                        | 0x38 :
-                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
-                        | 0x1C,
-                        AR5K_PHY_SETTLING);
-                /* Set Frame Control Register */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
-                        AR5K_PHY_TURBO_SHORT | 0x2020) :
-                        (AR5K_PHY_FRAME_CTL_INI | 0x1020),
-                        AR5K_PHY_FRAME_CTL_5210);
-        }
-
         /*
-         * Calculate cwmin/max by channel mode
+         * Set contention window (cw_min/cw_max)
+         * and arbitrated interframe space (aifs)...
          */
-        cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
-        cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
-        ah->ah_aifs = AR5K_TUNE_AIFS;
-        /*XR is only supported on 5212*/
-        if (IS_CHAN_XR(ah->ah_current_channel) &&
-                        ah->ah_version == AR5K_AR5212) {
-                cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
-                cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
-                ah->ah_aifs = AR5K_TUNE_AIFS_XR;
-        /*B mode is not supported on 5210*/
-        } else if (IS_CHAN_B(ah->ah_current_channel) &&
-                        ah->ah_version != AR5K_AR5210) {
-                cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
-                cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
-                ah->ah_aifs = AR5K_TUNE_AIFS_11B;
-        }
+        ath5k_hw_reg_write(ah,
+                AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
+                AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
+                AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),
+                AR5K_QUEUE_DFS_LOCAL_IFS(queue));
 
-        cw_min = 1;
-        while (cw_min < ah->ah_cw_min)
-                cw_min = (cw_min << 1) | 1;
+        /*
+         * Set tx retry limits for this queue
+         */
+        ath5k_hw_set_tx_retry_limits(ah, queue);
 
-        cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
-                ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
-        cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
-                ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
 
         /*
-         * Calculate and set retry limits
+         * Set misc registers
          */
-        if (ah->ah_software_retry) {
-                /* XXX Need to test this */
-                retry_lg = ah->ah_limit_tx_retries;
-                retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
-                        AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
-        } else {
-                retry_lg = AR5K_INIT_LG_RETRY;
-                retry_sh = AR5K_INIT_SH_RETRY;
-        }
 
-        /*No QCU/DCU [5210]*/
-        if (ah->ah_version == AR5K_AR5210) {
-                ath5k_hw_reg_write(ah,
-                        (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
-                        | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
-                                AR5K_NODCU_RETRY_LMT_SLG_RETRY)
-                        | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
-                                AR5K_NODCU_RETRY_LMT_SSH_RETRY)
-                        | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
-                        | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
-                        AR5K_NODCU_RETRY_LMT);
-        } else {
-                /*QCU/DCU [5211+]*/
-                ath5k_hw_reg_write(ah,
-                        AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
-                                AR5K_DCU_RETRY_LMT_SLG_RETRY) |
-                        AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
-                                AR5K_DCU_RETRY_LMT_SSH_RETRY) |
-                        AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
-                        AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
-                        AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
+        /* Enable DCU to wait for next fragment from QCU */
+        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                                AR5K_DCU_MISC_FRAG_WAIT);
 
-        /*===Rest is also for QCU/DCU only [5211+]===*/
+        /* On Maui and Spirit use the global seqnum on DCU */
+        if (ah->ah_mac_version < AR5K_SREV_AR5211)
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                                        AR5K_DCU_MISC_SEQNUM_CTL);
+
+        /* Constant bit rate period */
+        if (tq->tqi_cbr_period) {
+                ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
+                                        AR5K_QCU_CBRCFG_INTVAL) |
+                                        AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
+                                        AR5K_QCU_CBRCFG_ORN_THRES),
+                                        AR5K_QUEUE_CBRCFG(queue));
 
-                /*
-                 * Set initial content window (cw_min/cw_max)
-                 * and arbitrated interframe space (aifs)...
-                 */
-                ath5k_hw_reg_write(ah,
-                        AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
-                        AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
-                        AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
-                                AR5K_DCU_LCL_IFS_AIFS),
-                        AR5K_QUEUE_DFS_LOCAL_IFS(queue));
-
-                /*
-                 * Set misc registers
-                 */
-                /* Enable DCU early termination for this queue */
                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                        AR5K_QCU_MISC_DCU_EARLY);
+                                        AR5K_QCU_MISC_FRSHED_CBR);
 
-                /* Enable DCU to wait for next fragment from QCU */
-                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
-                                        AR5K_DCU_MISC_FRAG_WAIT);
-
-                /* On Maui and Spirit use the global seqnum on DCU */
-                if (ah->ah_mac_version < AR5K_SREV_AR5211)
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
-                                                AR5K_DCU_MISC_SEQNUM_CTL);
-
-                if (tq->tqi_cbr_period) {
-                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
-                                AR5K_QCU_CBRCFG_INTVAL) |
-                                AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
-                                AR5K_QCU_CBRCFG_ORN_THRES),
-                                AR5K_QUEUE_CBRCFG(queue));
+                if (tq->tqi_cbr_overflow_limit)
                         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_FRSHED_CBR);
-                        if (tq->tqi_cbr_overflow_limit)
-                                AR5K_REG_ENABLE_BITS(ah,
-                                        AR5K_QUEUE_MISC(queue),
                                         AR5K_QCU_MISC_CBR_THRES_ENABLE);
-                }
+        }
 
-                if (tq->tqi_ready_time &&
-                (tq->tqi_type != AR5K_TX_QUEUE_CAB))
-                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
-                                AR5K_QCU_RDYTIMECFG_INTVAL) |
-                                AR5K_QCU_RDYTIMECFG_ENABLE,
-                                AR5K_QUEUE_RDYTIMECFG(queue));
-
-                if (tq->tqi_burst_time) {
-                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
-                                AR5K_DCU_CHAN_TIME_DUR) |
-                                AR5K_DCU_CHAN_TIME_ENABLE,
-                                AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
-
-                        if (tq->tqi_flags
-                        & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
-                                AR5K_REG_ENABLE_BITS(ah,
-                                        AR5K_QUEUE_MISC(queue),
+        /* Ready time interval */
+        if (tq->tqi_ready_time && (tq->tqi_type != AR5K_TX_QUEUE_CAB))
+                ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
+                                        AR5K_QCU_RDYTIMECFG_INTVAL) |
+                                        AR5K_QCU_RDYTIMECFG_ENABLE,
+                                        AR5K_QUEUE_RDYTIMECFG(queue));
+
+        if (tq->tqi_burst_time) {
+                ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
+                                        AR5K_DCU_CHAN_TIME_DUR) |
+                                        AR5K_DCU_CHAN_TIME_ENABLE,
+                                        AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
+
+                if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                         AR5K_QCU_MISC_RDY_VEOL_POLICY);
-                }
+        }
 
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
-                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
-                                AR5K_QUEUE_DFS_MISC(queue));
+        /* Enable/disable Post frame backoff */
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
+                ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
+                                        AR5K_QUEUE_DFS_MISC(queue));
 
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
-                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
-                                AR5K_QUEUE_DFS_MISC(queue));
+        /* Enable/disable fragmentation burst backoff */
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
+                ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
+                                        AR5K_QUEUE_DFS_MISC(queue));
 
-                /*
-                 * Set registers by queue type
-                 */
-                switch (tq->tqi_type) {
-                case AR5K_TX_QUEUE_BEACON:
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+        /*
+         * Set registers by queue type
+         */
+        switch (tq->tqi_type) {
+        case AR5K_TX_QUEUE_BEACON:
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                 AR5K_QCU_MISC_FRSHED_DBA_GT |
                                 AR5K_QCU_MISC_CBREXP_BCN_DIS |
                                 AR5K_QCU_MISC_BCN_ENABLE);
 
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
                                 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
                                 AR5K_DCU_MISC_ARBLOCK_IGNORE |
                                 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
                                 AR5K_DCU_MISC_BCN_ENABLE);
-                        break;
+                break;
 
-                case AR5K_TX_QUEUE_CAB:
-                        /* XXX: use BCN_SENT_GT, if we can figure out how */
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_FRSHED_DBA_GT |
-                                AR5K_QCU_MISC_CBREXP_DIS |
-                                AR5K_QCU_MISC_CBREXP_BCN_DIS);
+        case AR5K_TX_QUEUE_CAB:
+                /* XXX: use BCN_SENT_GT, if we can figure out how */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_FRSHED_DBA_GT |
+                                        AR5K_QCU_MISC_CBREXP_DIS |
+                                        AR5K_QCU_MISC_CBREXP_BCN_DIS);
 
-                        ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -
-                                (AR5K_TUNE_SW_BEACON_RESP -
-                                AR5K_TUNE_DMA_BEACON_RESP) -
+                ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -
+                                        (AR5K_TUNE_SW_BEACON_RESP -
+                                        AR5K_TUNE_DMA_BEACON_RESP) -
                                 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
-                                AR5K_QCU_RDYTIMECFG_ENABLE,
-                                AR5K_QUEUE_RDYTIMECFG(queue));
+                                        AR5K_QCU_RDYTIMECFG_ENABLE,
+                                        AR5K_QUEUE_RDYTIMECFG(queue));
 
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
-                                (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
-                                AR5K_DCU_MISC_ARBLOCK_CTL_S));
-                        break;
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                                        (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
+                                        AR5K_DCU_MISC_ARBLOCK_CTL_S));
+                break;
 
-                case AR5K_TX_QUEUE_UAPSD:
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_CBREXP_DIS);
-                        break;
+        case AR5K_TX_QUEUE_UAPSD:
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_CBREXP_DIS);
+                break;
 
-                case AR5K_TX_QUEUE_DATA:
-                default:
+        case AR5K_TX_QUEUE_DATA:
+        default:
                         break;
-                }
-
-                /* TODO: Handle frame compression */
-
-                /*
-                 * Enable interrupts for this tx queue
-                 * in the secondary interrupt mask registers
-                 */
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
-
-                /* Update secondary interrupt mask registers */
-
-                /* Filter out inactive queues */
-                ah->ah_txq_imr_txok &= ah->ah_txq_status;
-                ah->ah_txq_imr_txerr &= ah->ah_txq_status;
-                ah->ah_txq_imr_txurn &= ah->ah_txq_status;
-                ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
-                ah->ah_txq_imr_txeol &= ah->ah_txq_status;
-                ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
-                ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
-                ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
-                ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
-
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
-                        AR5K_SIMR0_QCU_TXOK) |
-                        AR5K_REG_SM(ah->ah_txq_imr_txdesc,
-                        AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
-                        AR5K_SIMR1_QCU_TXERR) |
-                        AR5K_REG_SM(ah->ah_txq_imr_txeol,
-                        AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
-                /* Update simr2 but don't overwrite rest simr2 settings */
-                AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
-                AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
-                        AR5K_REG_SM(ah->ah_txq_imr_txurn,
-                        AR5K_SIMR2_QCU_TXURN));
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
-                        AR5K_SIMR3_QCBRORN) |
-                        AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
-                        AR5K_SIMR3_QCBRURN), AR5K_SIMR3);
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
-                        AR5K_SIMR4_QTRIG), AR5K_SIMR4);
-                /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
-                        AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
-                /* No queue has TXNOFRM enabled, disable the interrupt
-                 * by setting AR5K_TXNOFRM to zero */
-                if (ah->ah_txq_imr_nofrm == 0)
-                        ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
-
-                /* Set QCU mask for this DCU to save power */
-                AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
         }
 
+        /* TODO: Handle frame compression */
+
+        /*
+         * Enable interrupts for this tx queue
+         * in the secondary interrupt mask registers
+         */
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
+
+        /* Update secondary interrupt mask registers */
+
+        /* Filter out inactive queues */
+        ah->ah_txq_imr_txok &= ah->ah_txq_status;
+        ah->ah_txq_imr_txerr &= ah->ah_txq_status;
+        ah->ah_txq_imr_txurn &= ah->ah_txq_status;
+        ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
+        ah->ah_txq_imr_txeol &= ah->ah_txq_status;
+        ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
+        ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
+        ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
+        ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
+                                        AR5K_SIMR0_QCU_TXOK) |
+                                        AR5K_REG_SM(ah->ah_txq_imr_txdesc,
+                                        AR5K_SIMR0_QCU_TXDESC),
+                                        AR5K_SIMR0);
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
+                                        AR5K_SIMR1_QCU_TXERR) |
+                                        AR5K_REG_SM(ah->ah_txq_imr_txeol,
+                                        AR5K_SIMR1_QCU_TXEOL),
+                                        AR5K_SIMR1);
+
+        /* Update SIMR2 but don't overwrite rest simr2 settings */
+        AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
+        AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
+                                AR5K_REG_SM(ah->ah_txq_imr_txurn,
+                                AR5K_SIMR2_QCU_TXURN));
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
+                                AR5K_SIMR3_QCBRORN) |
+                                AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
+                                AR5K_SIMR3_QCBRURN),
+                                AR5K_SIMR3);
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
+                                AR5K_SIMR4_QTRIG), AR5K_SIMR4);
+
+        /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
+                                AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
+
+        /* No queue has TXNOFRM enabled, disable the interrupt
+         * by setting AR5K_TXNOFRM to zero */
+        if (ah->ah_txq_imr_nofrm == 0)
+                ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
+
+        /* Set QCU mask for this DCU to save power */
+        AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
+
         return 0;
 }
 
-/*
- * Set slot time on DCU
+
+/**************************\
+* Global QCU/DCU functions *
+\**************************/
+
+/**
+ * ath5k_hw_set_ifs_intervals  - Set global inter-frame spaces on DCU
+ *
+ * @ah The &struct ath5k_hw
+ * @slot_time Slot time in us
+ *
+ * Sets the global IFS intervals on DCU (also works on AR5210) for
+ * the given slot time and the current bwmode.
  */
-int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
+int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
 {
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct ieee80211_rate *rate;
+        u32 ack_tx_time, eifs, eifs_clock, sifs, sifs_clock;
         u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);
 
         if (slot_time < 6 || slot_time_clock > AR5K_SLOT_TIME_MAX)
                 return -EINVAL;
 
-        if (ah->ah_version == AR5K_AR5210)
-                ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);
+        sifs = ath5k_hw_get_default_sifs(ah);
+        sifs_clock = ath5k_hw_htoclock(ah, sifs - 2);
+
+        /* EIFS
+         * Txtime of ack at lowest rate + SIFS + DIFS
+         * (DIFS = SIFS + 2 * Slot time)
+         *
+         * Note: HAL has some predefined values for EIFS
+         * Turbo:   (37 + 2 * 6)
+         * Default: (74 + 2 * 9)
+         * Half:    (149 + 2 * 13)
+         * Quarter: (298 + 2 * 21)
+         *
+         * (74 + 2 * 6) for AR5210 default and turbo !
+         *
+         * According to the formula we have
+         * ack_tx_time = 25 for turbo and
+         * ack_tx_time = 42.5 * clock multiplier
+         * for default/half/quarter.
+         *
+         * This can't be right, 42 is what we would get
+         * from ath5k_hw_get_frame_dur_for_bwmode or
+         * ieee80211_generic_frame_duration for zero frame
+         * length and without SIFS !
+         *
+         * Also we have different lowest rate for 802.11a
+         */
+        if (channel->hw_value & CHANNEL_5GHZ)
+                rate = &sc->sbands[IEEE80211_BAND_5GHZ].bitrates[0];
         else
-                ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);
+                rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[0];
+
+        ack_tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false);
+
+        /* ack_tx_time includes an SIFS already */
+        eifs = ack_tx_time + sifs + 2 * slot_time;
+        eifs_clock = ath5k_hw_htoclock(ah, eifs);
+
+        /* Set IFS settings on AR5210 */
+        if (ah->ah_version == AR5K_AR5210) {
+                u32 pifs, pifs_clock, difs, difs_clock;
+
+                /* Set slot time */
+                ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);
+
+                /* Set EIFS */
+                eifs_clock = AR5K_REG_SM(eifs_clock, AR5K_IFS1_EIFS);
+
+                /* PIFS = Slot time + SIFS */
+                pifs = slot_time + sifs;
+                pifs_clock = ath5k_hw_htoclock(ah, pifs);
+                pifs_clock = AR5K_REG_SM(pifs_clock, AR5K_IFS1_PIFS);
+
+                /* DIFS = SIFS + 2 * Slot time */
+                difs = sifs + 2 * slot_time;
+                difs_clock = ath5k_hw_htoclock(ah, difs);
+
+                /* Set SIFS/DIFS */
+                ath5k_hw_reg_write(ah, (difs_clock <<
+                                AR5K_IFS0_DIFS_S) | sifs_clock,
+                                AR5K_IFS0);
+
+                /* Set PIFS/EIFS and preserve AR5K_INIT_CARR_SENSE_EN */
+                ath5k_hw_reg_write(ah, pifs_clock | eifs_clock |
+                                (AR5K_INIT_CARR_SENSE_EN << AR5K_IFS1_CS_EN_S),
+                                AR5K_IFS1);
+
+                return 0;
+        }
+
+        /* Set IFS slot time */
+        ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);
+
+        /* Set EIFS interval */
+        ath5k_hw_reg_write(ah, eifs_clock, AR5K_DCU_GBL_IFS_EIFS);
+
+        /* Set SIFS interval in usecs */
+        AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
+                                AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC,
+                                sifs);
+
+        /* Set SIFS interval in clock cycles */
+        ath5k_hw_reg_write(ah, sifs_clock, AR5K_DCU_GBL_IFS_SIFS);
 
         return 0;
 }
 
+
+int ath5k_hw_init_queues(struct ath5k_hw *ah)
+{
+        int i, ret;
+
+        /* TODO: HW Compression support for data queues */
+        /* TODO: Burst prefetch for data queues */
+
+        /*
+         * Reset queues and start beacon timers at the end of the reset routine
+         * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
+         * Note: If we want we can assign multiple qcus on one dcu.
+         */
+        if (ah->ah_version != AR5K_AR5210)
+                for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
+                        ret = ath5k_hw_reset_tx_queue(ah, i);
+                        if (ret) {
+                                ATH5K_ERR(ah->ah_sc,
+                                        "failed to reset TX queue #%d\n", i);
+                                return ret;
+                        }
+                }
+        else
+                /* No QCU/DCU on AR5210, just set tx
+                 * retry limits. We set IFS parameters
+                 * on ath5k_hw_set_ifs_intervals */
+                ath5k_hw_set_tx_retry_limits(ah, 0);
+
+        /* Set the turbo flag when operating on 40MHz */
+        if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
+                AR5K_REG_ENABLE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
+                                AR5K_DCU_GBL_IFS_MISC_TURBO_MODE);
+
+        /* If we didn't set IFS timings through
+         * ath5k_hw_set_coverage_class make sure
+         * we set them here */
+        if (!ah->ah_coverage_class) {
+                unsigned int slot_time = ath5k_hw_get_default_slottime(ah);
+                ath5k_hw_set_ifs_intervals(ah, slot_time);
+        }
+
+        return 0;
+}
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index 55b4ac6d236f..d12b827033c1 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -26,7 +26,6 @@
  * Atheros presentations and papers like these:
  *
  * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
- *        http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
  *
  * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
  *
@@ -133,8 +132,8 @@
  * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
  * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
  * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
- * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i
- * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what
+ * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
+ * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what
  * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
  */
 #define AR5K_BSR                0x002c                  /* Register Address */
@@ -284,7 +283,7 @@
  */
 #define AR5K_ISR                0x001c                  /* Register Address [5210] */
 #define AR5K_PISR               0x0080                  /* Register Address [5211+] */
-#define AR5K_ISR_RXOK           0x00000001      /* Frame successfuly recieved */
+#define AR5K_ISR_RXOK           0x00000001      /* Frame successfuly received */
 #define AR5K_ISR_RXDESC         0x00000002      /* RX descriptor request */
 #define AR5K_ISR_RXERR          0x00000004      /* Receive error */
 #define AR5K_ISR_RXNOFRM        0x00000008      /* No frame received (receive timeout) */
@@ -373,12 +372,12 @@
 /*
  * Interrupt Mask Registers
  *
- * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
+ * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
  * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
  */
 #define AR5K_IMR                0x0020                  /* Register Address [5210] */
 #define AR5K_PIMR               0x00a0                  /* Register Address [5211+] */
-#define AR5K_IMR_RXOK           0x00000001      /* Frame successfuly recieved*/
+#define AR5K_IMR_RXOK           0x00000001      /* Frame successfuly received*/
 #define AR5K_IMR_RXDESC         0x00000002      /* RX descriptor request*/
 #define AR5K_IMR_RXERR          0x00000004      /* Receive error*/
 #define AR5K_IMR_RXNOFRM        0x00000008      /* No frame received (receive timeout)*/
@@ -687,16 +686,15 @@
 
 /*
  * DCU retry limit registers
+ * all these fields don't allow zero values
  */
 #define AR5K_DCU_RETRY_LMT_BASE         0x1080                  /* Register Address -Queue0 DCU_RETRY_LMT */
-#define AR5K_DCU_RETRY_LMT_SH_RETRY     0x0000000f      /* Short retry limit mask */
-#define AR5K_DCU_RETRY_LMT_SH_RETRY_S   0
-#define AR5K_DCU_RETRY_LMT_LG_RETRY     0x000000f0      /* Long retry limit mask */
-#define AR5K_DCU_RETRY_LMT_LG_RETRY_S   4
-#define AR5K_DCU_RETRY_LMT_SSH_RETRY    0x00003f00      /* Station short retry limit mask (?) */
-#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S  8
-#define AR5K_DCU_RETRY_LMT_SLG_RETRY    0x000fc000      /* Station long retry limit mask (?) */
-#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S  14
+#define AR5K_DCU_RETRY_LMT_RTS          0x0000000f      /* RTS failure limit. Transmission fails if no CTS is received for this number of times */
+#define AR5K_DCU_RETRY_LMT_RTS_S        0
+#define AR5K_DCU_RETRY_LMT_STA_RTS      0x00003f00      /* STA RTS failure limit. If exceeded CW reset */
+#define AR5K_DCU_RETRY_LMT_STA_RTS_S    8
+#define AR5K_DCU_RETRY_LMT_STA_DATA     0x000fc000      /* STA data failure limit. If exceeded CW reset. */
+#define AR5K_DCU_RETRY_LMT_STA_DATA_S   14
 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)  AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
 
 /*
@@ -788,6 +786,7 @@
 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE        0x00000007      /* LFSR Slice Select */
 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE        0x00000008      /* Turbo mode */
 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC     0x000003f0      /* SIFS Duration mask */
+#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S   4
 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR          0x000ffc00      /* USEC Duration mask */
 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S        10
 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY     0x00300000      /* DCU Arbiter delay mask */
@@ -896,7 +895,7 @@
 #define AR5K_PCICFG_SL_INTEN            0x00000800      /* Enable interrupts when asleep */
 #define AR5K_PCICFG_LED_BCTL            0x00001000      /* Led blink (?) [5210] */
 #define AR5K_PCICFG_RETRY_FIX           0x00001000      /* Enable pci core retry fix */
-#define AR5K_PCICFG_SL_INPEN            0x00002000      /* Sleep even whith pending interrupts*/
+#define AR5K_PCICFG_SL_INPEN            0x00002000      /* Sleep even with pending interrupts*/
 #define AR5K_PCICFG_SPWR_DN             0x00010000      /* Mask for power status */
 #define AR5K_PCICFG_LEDMODE             0x000e0000      /* Ledmode [5211+] */
 #define AR5K_PCICFG_LEDMODE_PROP        0x00000000      /* Blink on standard traffic [5211+] */
@@ -1064,7 +1063,7 @@
 /*
  * EEPROM command register
  */
-#define AR5K_EEPROM_CMD         0x6008                  /* Register Addres */
+#define AR5K_EEPROM_CMD         0x6008                  /* Register Address */
 #define AR5K_EEPROM_CMD_READ    0x00000001      /* EEPROM read */
 #define AR5K_EEPROM_CMD_WRITE   0x00000002      /* EEPROM write */
 #define AR5K_EEPROM_CMD_RESET   0x00000004      /* EEPROM reset */
@@ -1084,7 +1083,7 @@
 /*
  * EEPROM config register
  */
-#define AR5K_EEPROM_CFG                 0x6010                  /* Register Addres */
+#define AR5K_EEPROM_CFG                 0x6010                  /* Register Address */
 #define AR5K_EEPROM_CFG_SIZE            0x00000003              /* Size determination override */
 #define AR5K_EEPROM_CFG_SIZE_AUTO       0
 #define AR5K_EEPROM_CFG_SIZE_4KBIT      1
@@ -1126,7 +1125,7 @@
  * Second station id register (Upper 16 bits of MAC address + PCU settings)
  */
 #define AR5K_STA_ID1                    0x8004                  /* Register Address */
-#define AR5K_STA_ID1_ADDR_U16           0x0000ffff      /* Upper 16 bits of MAC addres */
+#define AR5K_STA_ID1_ADDR_U16           0x0000ffff      /* Upper 16 bits of MAC address */
 #define AR5K_STA_ID1_AP                 0x00010000      /* Set AP mode */
 #define AR5K_STA_ID1_ADHOC              0x00020000      /* Set Ad-Hoc mode */
 #define AR5K_STA_ID1_PWR_SV             0x00040000      /* Power save reporting */
@@ -1312,7 +1311,7 @@
 #define AR5K_IFS1_EIFS          0x03fff000
 #define AR5K_IFS1_EIFS_S        12
 #define AR5K_IFS1_CS_EN         0x04000000
-
+#define AR5K_IFS1_CS_EN_S       26
 
 /*
  * CFP duration register
@@ -1387,10 +1386,9 @@
 
 
 /*
- * PCU control register
+ * PCU Diagnostic register
  *
- * Only DIS_RX is used in the code, the rest i guess are
- * for tweaking/diagnostics.
+ * Used for tweaking/diagnostics.
  */
 #define AR5K_DIAG_SW_5210               0x8068                  /* Register Address [5210] */
 #define AR5K_DIAG_SW_5211               0x8048                  /* Register Address [5211+] */
@@ -1399,22 +1397,22 @@
 #define AR5K_DIAG_SW_DIS_WEP_ACK        0x00000001      /* Disable ACKs if WEP key is invalid */
 #define AR5K_DIAG_SW_DIS_ACK            0x00000002      /* Disable ACKs */
 #define AR5K_DIAG_SW_DIS_CTS            0x00000004      /* Disable CTSs */
-#define AR5K_DIAG_SW_DIS_ENC            0x00000008      /* Disable encryption */
-#define AR5K_DIAG_SW_DIS_DEC            0x00000010      /* Disable decryption */
-#define AR5K_DIAG_SW_DIS_TX             0x00000020      /* Disable transmit [5210] */
-#define AR5K_DIAG_SW_DIS_RX_5210        0x00000040      /* Disable recieve */
+#define AR5K_DIAG_SW_DIS_ENC            0x00000008      /* Disable HW encryption */
+#define AR5K_DIAG_SW_DIS_DEC            0x00000010      /* Disable HW decryption */
+#define AR5K_DIAG_SW_DIS_TX_5210        0x00000020      /* Disable transmit [5210] */
+#define AR5K_DIAG_SW_DIS_RX_5210        0x00000040      /* Disable receive */
 #define AR5K_DIAG_SW_DIS_RX_5211        0x00000020
 #define AR5K_DIAG_SW_DIS_RX             (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
-#define AR5K_DIAG_SW_LOOP_BACK_5210     0x00000080      /* Loopback (i guess it goes with DIS_TX) [5210] */
+#define AR5K_DIAG_SW_LOOP_BACK_5210     0x00000080      /* TX Data Loopback (i guess it goes with DIS_TX) [5210] */
 #define AR5K_DIAG_SW_LOOP_BACK_5211     0x00000040
 #define AR5K_DIAG_SW_LOOP_BACK          (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
-#define AR5K_DIAG_SW_CORR_FCS_5210      0x00000100      /* Corrupted FCS */
+#define AR5K_DIAG_SW_CORR_FCS_5210      0x00000100      /* Generate invalid TX FCS */
 #define AR5K_DIAG_SW_CORR_FCS_5211      0x00000080
 #define AR5K_DIAG_SW_CORR_FCS           (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
-#define AR5K_DIAG_SW_CHAN_INFO_5210     0x00000200      /* Dump channel info */
+#define AR5K_DIAG_SW_CHAN_INFO_5210     0x00000200      /* Add 56 bytes of channel info before the frame data in the RX buffer */
 #define AR5K_DIAG_SW_CHAN_INFO_5211     0x00000100
 #define AR5K_DIAG_SW_CHAN_INFO          (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
@@ -1426,17 +1424,17 @@
 #define AR5K_DIAG_SW_SCVRAM_SEED        0x0003f800      /* [5210] */
 #define AR5K_DIAG_SW_SCRAM_SEED_M       0x0001fc00      /* Scrambler seed mask */
 #define AR5K_DIAG_SW_SCRAM_SEED_S       10
-#define AR5K_DIAG_SW_DIS_SEQ_INC        0x00040000      /* Disable seqnum increment (?)[5210] */
+#define AR5K_DIAG_SW_DIS_SEQ_INC_5210   0x00040000      /* Disable seqnum increment (?)[5210] */
 #define AR5K_DIAG_SW_FRAME_NV0_5210     0x00080000
 #define AR5K_DIAG_SW_FRAME_NV0_5211     0x00020000      /* Accept frames of non-zero protocol number */
 #define AR5K_DIAG_SW_FRAME_NV0          (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
 #define AR5K_DIAG_SW_OBSPT_M            0x000c0000      /* Observation point select (?) */
 #define AR5K_DIAG_SW_OBSPT_S            18
-#define AR5K_DIAG_SW_RX_CLEAR_HIGH      0x0010000       /* Force RX Clear high */
-#define AR5K_DIAG_SW_IGNORE_CARR_SENSE  0x0020000       /* Ignore virtual carrier sense */
-#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH   0x0040000       /* Force channel idle high */
-#define AR5K_DIAG_SW_PHEAR_ME           0x0080000       /* ??? */
+#define AR5K_DIAG_SW_RX_CLEAR_HIGH      0x00100000      /* Ignore carrier sense */
+#define AR5K_DIAG_SW_IGNORE_CARR_SENSE  0x00200000      /* Ignore virtual carrier sense */
+#define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH  0x00400000      /* Force channel idle high */
+#define AR5K_DIAG_SW_PHEAR_ME           0x00800000      /* ??? */
 
 /*
  * TSF (clock) register (lower 32 bits)
@@ -1822,50 +1820,8 @@
 
 /*===5212 end===*/
 
-/*
- * Key table (WEP) register
- */
-#define AR5K_KEYTABLE_0_5210            0x9000
-#define AR5K_KEYTABLE_0_5211            0x8800
-#define AR5K_KEYTABLE_5210(_n)          (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
-#define AR5K_KEYTABLE_5211(_n)          (AR5K_KEYTABLE_0_5211 + ((_n) << 5))
-#define AR5K_KEYTABLE(_n)               (ah->ah_version == AR5K_AR5210 ? \
-                                        AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
-#define AR5K_KEYTABLE_OFF(_n, x)        (AR5K_KEYTABLE(_n) + (x << 2))
-#define AR5K_KEYTABLE_TYPE(_n)          AR5K_KEYTABLE_OFF(_n, 5)
-#define AR5K_KEYTABLE_TYPE_40           0x00000000
-#define AR5K_KEYTABLE_TYPE_104          0x00000001
-#define AR5K_KEYTABLE_TYPE_128          0x00000003
-#define AR5K_KEYTABLE_TYPE_TKIP         0x00000004      /* [5212+] */
-#define AR5K_KEYTABLE_TYPE_AES          0x00000005      /* [5211+] */
-#define AR5K_KEYTABLE_TYPE_CCM          0x00000006      /* [5212+] */
-#define AR5K_KEYTABLE_TYPE_NULL         0x00000007      /* [5211+] */
-#define AR5K_KEYTABLE_ANTENNA           0x00000008      /* [5212+] */
-#define AR5K_KEYTABLE_MAC0(_n)          AR5K_KEYTABLE_OFF(_n, 6)
-#define AR5K_KEYTABLE_MAC1(_n)          AR5K_KEYTABLE_OFF(_n, 7)
-#define AR5K_KEYTABLE_VALID             0x00008000
-
-/* If key type is TKIP and MIC is enabled
- * MIC key goes in offset entry + 64 */
-#define AR5K_KEYTABLE_MIC_OFFSET        64
-
-/* WEP 40-bit   = 40-bit  entered key + 24 bit IV = 64-bit
- * WEP 104-bit  = 104-bit entered key + 24-bit IV = 128-bit
- * WEP 128-bit  = 128-bit entered key + 24 bit IV = 152-bit
- *
- * Some vendors have introduced bigger WEP keys to address
- * security vulnerabilities in WEP. This includes:
- *
- * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit
- *
- * We can expand this if we find ar5k Atheros cards with a larger
- * key table size.
- */
 #define AR5K_KEYTABLE_SIZE_5210         64
 #define AR5K_KEYTABLE_SIZE_5211         128
-#define AR5K_KEYTABLE_SIZE              (ah->ah_version == AR5K_AR5210 ? \
-                                        AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
-
 
 /*===PHY REGISTERS===*/
 
@@ -1911,7 +1867,7 @@
 #define AR5K_PHY_TURBO                  0x9804                  /* Register Address */
 #define AR5K_PHY_TURBO_MODE             0x00000001      /* Enable turbo mode */
 #define AR5K_PHY_TURBO_SHORT            0x00000002      /* Set short symbols to turbo mode */
-#define AR5K_PHY_TURBO_MIMO             0x00000004      /* Set turbo for mimo mimo */
+#define AR5K_PHY_TURBO_MIMO             0x00000004      /* Set turbo for mimo */
 
 /*
  * PHY agility command register
@@ -2102,6 +2058,7 @@
 
 #define AR5K_PHY_SCAL                   0x9878
 #define AR5K_PHY_SCAL_32MHZ             0x0000000e
+#define AR5K_PHY_SCAL_32MHZ_5311        0x00000008
 #define AR5K_PHY_SCAL_32MHZ_2417        0x0000000a
 #define AR5K_PHY_SCAL_32MHZ_HB63        0x00000032
 
@@ -2288,6 +2245,8 @@
 #define AR5K_PHY_FRAME_CTL              (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
 /*---[5111+]---*/
+#define AR5K_PHY_FRAME_CTL_WIN_LEN      0x00000003      /* Force window length (?) */
+#define AR5K_PHY_FRAME_CTL_WIN_LEN_S    0
 #define AR5K_PHY_FRAME_CTL_TX_CLIP      0x00000038      /* Mask for tx clip (?) */
 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S    3
 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO  0x00010000      /* Prepend chan info */
@@ -2602,3 +2561,28 @@
  */
 #define AR5K_PHY_PDADC_TXPOWER_BASE     0xa280
 #define AR5K_PHY_PDADC_TXPOWER(_n)      (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
+
+/*
+ * Platform registers for WiSoC
+ */
+#define AR5K_AR5312_RESET               0xbc003020
+#define AR5K_AR5312_RESET_BB0_COLD      0x00000004
+#define AR5K_AR5312_RESET_BB1_COLD      0x00000200
+#define AR5K_AR5312_RESET_WMAC0         0x00002000
+#define AR5K_AR5312_RESET_BB0_WARM      0x00004000
+#define AR5K_AR5312_RESET_WMAC1         0x00020000
+#define AR5K_AR5312_RESET_BB1_WARM      0x00040000
+
+#define AR5K_AR5312_ENABLE              0xbc003080
+#define AR5K_AR5312_ENABLE_WLAN0    0x00000001
+#define AR5K_AR5312_ENABLE_WLAN1    0x00000008
+
+#define AR5K_AR2315_RESET               0xb1000004
+#define AR5K_AR2315_RESET_WMAC          0x00000001
+#define AR5K_AR2315_RESET_BB_WARM       0x00000002
+
+#define AR5K_AR2315_AHB_ARB_CTL         0xb1000008
+#define AR5K_AR2315_AHB_ARB_CTL_WLAN    0x00000002
+
+#define AR5K_AR2315_BYTESWAP    0xb100000c
+#define AR5K_AR2315_BYTESWAP_WMAC       0x00000002
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 498aa28ea9e6..126a4eab35f3 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -27,11 +27,17 @@
 
 #include <linux/pci.h>          /* To determine if a card is pci-e */
 #include <linux/log2.h>
+#include <linux/platform_device.h>
 #include "ath5k.h"
 #include "reg.h"
 #include "base.h"
 #include "debug.h"
 
+
+/******************\
+* Helper functions *
+\******************/
+
 /*
  * Check if a register write has been completed
  */
@@ -53,146 +59,272 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
         return (i <= 0) ? -EAGAIN : 0;
 }
 
+
+/*************************\
+* Clock related functions *
+\*************************/
+
 /**
- * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
+ * ath5k_hw_htoclock - Translate usec to hw clock units
  *
- * @ah: the &struct ath5k_hw
- * @channel: the currently set channel upon reset
- *
- * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
- * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
+ * @ah: The &struct ath5k_hw
+ * @usec: value in microseconds
+ */
+unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        return usec * common->clockrate;
+}
+
+/**
+ * ath5k_hw_clocktoh - Translate hw clock units to usec
+ * @clock: value in hw clock units
+ */
+unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        return clock / common->clockrate;
+}
+
+/**
+ * ath5k_hw_init_core_clock - Initialize core clock
  *
- * Since delta slope is floating point we split it on its exponent and
- * mantissa and provide these values on hw.
+ * @ah The &struct ath5k_hw
  *
- * For more infos i think this patent is related
- * http://www.freepatentsonline.com/7184495.html
+ * Initialize core clock parameters (usec, usec32, latencies etc).
  */
-static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
-        struct ieee80211_channel *channel)
+static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
 {
-        /* Get exponent and mantissa and set it */
-        u32 coef_scaled, coef_exp, coef_man,
-                ds_coef_exp, ds_coef_man, clock;
-
-        BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
-                !(channel->hw_value & CHANNEL_OFDM));
-
-        /* Get coefficient
-         * ALGO: coef = (5 * clock / carrier_freq) / 2
-         * we scale coef by shifting clock value by 24 for
-         * better precision since we use integers */
-        /* TODO: Half/quarter rate */
-        clock =  (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
-        coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
-
-        /* Get exponent
-         * ALGO: coef_exp = 14 - highest set bit position */
-        coef_exp = ilog2(coef_scaled);
-
-        /* Doesn't make sense if it's zero*/
-        if (!coef_scaled || !coef_exp)
-                return -EINVAL;
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        struct ath_common *common = ath5k_hw_common(ah);
+        u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
 
-        /* Note: we've shifted coef_scaled by 24 */
-        coef_exp = 14 - (coef_exp - 24);
+        /*
+         * Set core clock frequency
+         */
+        if (channel->hw_value & CHANNEL_5GHZ)
+                clock = 40; /* 802.11a */
+        else if (channel->hw_value & CHANNEL_CCK)
+                clock = 22; /* 802.11b */
+        else
+                clock = 44; /* 802.11g */
 
+        /* Use clock multiplier for non-default
+         * bwmode */
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                clock *= 2;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                clock /= 2;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                clock /= 4;
+                break;
+        default:
+                break;
+        }
+
+        common->clockrate = clock;
 
-        /* Get mantissa (significant digits)
-         * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
-        coef_man = coef_scaled +
-                (1 << (24 - coef_exp - 1));
+        /*
+         * Set USEC parameters
+         */
+        /* Set USEC counter on PCU*/
+        usec = clock - 1;
+        usec = AR5K_REG_SM(usec, AR5K_USEC_1);
 
-        /* Calculate delta slope coefficient exponent
-         * and mantissa (remove scaling) and set them on hw */
-        ds_coef_man = coef_man >> (24 - coef_exp);
-        ds_coef_exp = coef_exp - 16;
+        /* Set usec duration on DCU */
+        if (ah->ah_version != AR5K_AR5210)
+                AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
+                                        AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
+                                        clock);
 
-        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
-                AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
-        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
-                AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
+        /* Set 32MHz USEC counter */
+        if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_radio == AR5K_RF2316) ||
+                (ah->ah_radio == AR5K_RF2317))
+        /* Remain on 40MHz clock ? */
+                sclock = 40 - 1;
+        else
+                sclock = 32 - 1;
+        sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
 
-        return 0;
-}
+        /*
+         * Set tx/rx latencies
+         */
+        usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
+        txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
+        rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
 
+        /*
+         * Set default Tx frame to Tx data start delay
+         */
+        txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
 
-/*
- * index into rates for control rates, we can set it up like this because
- * this is only used for AR5212 and we know it supports G mode
- */
-static const unsigned int control_rates[] =
-        { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
+        /*
+         * 5210 initvals don't include usec settings
+         * so we need to use magic values here for
+         * tx/rx latencies
+         */
+        if (ah->ah_version == AR5K_AR5210) {
+                /* same for turbo */
+                txlat = AR5K_INIT_TX_LATENCY_5210;
+                rxlat = AR5K_INIT_RX_LATENCY_5210;
+        }
 
-/**
- * ath5k_hw_write_rate_duration - fill rate code to duration table
- *
- * @ah: the &struct ath5k_hw
- * @mode: one of enum ath5k_driver_mode
- *
- * Write the rate code to duration table upon hw reset. This is a helper for
- * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
- * the hardware, based on current mode, for each rate. The rates which are
- * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
- * different rate code so we write their value twice (one for long preample
- * and one for short).
+        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
+                /* 5311 has different tx/rx latency masks
+                 * from 5211, since we deal 5311 the same
+                 * as 5211 when setting initvals, shift
+                 * values here to their proper locations
+                 *
+                 * Note: Initvals indicate tx/rx/ latencies
+                 * are the same for turbo mode */
+                txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
+                rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
+        } else
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_10MHZ:
+                txlat = AR5K_REG_SM(txlat * 2,
+                                AR5K_USEC_TX_LATENCY_5211);
+                rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
+                                AR5K_USEC_RX_LATENCY_5211);
+                txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                txlat = AR5K_REG_SM(txlat * 4,
+                                AR5K_USEC_TX_LATENCY_5211);
+                rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
+                                AR5K_USEC_RX_LATENCY_5211);
+                txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
+                break;
+        case AR5K_BWMODE_40MHZ:
+                txlat = AR5K_INIT_TX_LAT_MIN;
+                rxlat = AR5K_REG_SM(rxlat / 2,
+                                AR5K_USEC_RX_LATENCY_5211);
+                txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
+                break;
+        default:
+                break;
+        }
+
+        usec_reg = (usec | sclock | txlat | rxlat);
+        ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
+
+        /* On 5112 set tx frane to tx data start delay */
+        if (ah->ah_radio == AR5K_RF5112) {
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
+                                        AR5K_PHY_RF_CTL2_TXF2TXD_START,
+                                        txf2txs);
+        }
+}
+
+/*
+ * If there is an external 32KHz crystal available, use it
+ * as ref. clock instead of 32/40MHz clock and baseband clocks
+ * to save power during sleep or restore normal 32/40MHz
+ * operation.
  *
- * Note: Band doesn't matter here, if we set the values for OFDM it works
- * on both a and g modes. So all we have to do is set values for all g rates
- * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
- * quarter rate mode, we need to use another set of bitrates (that's why we
- * need the mode parameter) but we don't handle these proprietary modes yet.
+ * XXX: When operating on 32KHz certain PHY registers (27 - 31,
+ *      123 - 127) require delay on access.
  */
-static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
-       unsigned int mode)
+static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 {
-        struct ath5k_softc *sc = ah->ah_sc;
-        struct ieee80211_rate *rate;
-        unsigned int i;
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+        u32 scal, spending;
+
+        /* Only set 32KHz settings if we have an external
+         * 32KHz crystal present */
+        if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
+        AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
+        enable) {
 
-        /* Write rate duration table */
-        for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
-                u32 reg;
-                u16 tx_time;
+                /* 1 usec/cycle */
+                AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
+                /* Set up tsf increment on each cycle */
+                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
 
-                rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
+                /* Set baseband sleep control registers
+                 * and sleep control rate */
+                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 
-                /* Set ACK timeout */
-                reg = AR5K_RATE_DUR(rate->hw_value);
+                if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_radio == AR5K_RF2316) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                        spending = 0x14;
+                else
+                        spending = 0x18;
+                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 
-                /* An ACK frame consists of 10 bytes. If you add the FCS,
-                 * which ieee80211_generic_frame_duration() adds,
-                 * its 14 bytes. Note we use the control rate and not the
-                 * actual rate for this rate. See mac80211 tx.c
-                 * ieee80211_duration() for a brief description of
-                 * what rate we should choose to TX ACKs. */
-                tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
-                                                        sc->vif, 10, rate));
+                if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
+                        ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
+                        ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
+                        ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
+                        ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
+                } else {
+                        ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
+                        ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
+                        ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
+                        ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
+                }
 
-                ath5k_hw_reg_write(ah, tx_time, reg);
+                /* Enable sleep clock operation */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_EN);
 
-                if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
-                        continue;
+        } else {
 
-                /*
-                 * We're not distinguishing short preamble here,
-                 * This is true, all we'll get is a longer value here
-                 * which is not necessarilly bad. We could use
-                 * export ieee80211_frame_duration() but that needs to be
-                 * fixed first to be properly used by mac802111 drivers:
-                 *
-                 *  - remove erp stuff and let the routine figure ofdm
-                 *    erp rates
-                 *  - remove passing argument ieee80211_local as
-                 *    drivers don't have access to it
-                 *  - move drivers using ieee80211_generic_frame_duration()
-                 *    to this
-                 */
-                ath5k_hw_reg_write(ah, tx_time,
-                        reg + (AR5K_SET_SHORT_PREAMBLE << 2));
+                /* Disable sleep clock operation and
+                 * restore default parameters */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_EN);
+
+                AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
+
+                /* Set DAC/ADC delays */
+                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
+                ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
+
+                if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
+                        scal = AR5K_PHY_SCAL_32MHZ_2417;
+                else if (ee->ee_is_hb63)
+                        scal = AR5K_PHY_SCAL_32MHZ_HB63;
+                else
+                        scal = AR5K_PHY_SCAL_32MHZ;
+                ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
+
+                ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
+                ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
+
+                if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_radio == AR5K_RF2316) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                        spending = 0x14;
+                else
+                        spending = 0x18;
+                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
+
+                /* Set up tsf increment on each cycle */
+                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
         }
 }
 
+
+/*********************\
+* Reset/Sleep control *
+\*********************/
+
 /*
  * Reset chipset
  */
@@ -236,6 +368,64 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 }
 
 /*
+ * Reset AHB chipset
+ * AR5K_RESET_CTL_PCU flag resets WMAC
+ * AR5K_RESET_CTL_BASEBAND flag resets WBB
+ */
+static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
+{
+        u32 mask = flags ? flags : ~0U;
+        volatile u32 *reg;
+        u32 regval;
+        u32 val = 0;
+
+        /* ah->ah_mac_srev is not available at this point yet */
+        if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
+                reg = (u32 *) AR5K_AR2315_RESET;
+                if (mask & AR5K_RESET_CTL_PCU)
+                        val |= AR5K_AR2315_RESET_WMAC;
+                if (mask & AR5K_RESET_CTL_BASEBAND)
+                        val |= AR5K_AR2315_RESET_BB_WARM;
+        } else {
+                reg = (u32 *) AR5K_AR5312_RESET;
+                if (to_platform_device(ah->ah_sc->dev)->id == 0) {
+                        if (mask & AR5K_RESET_CTL_PCU)
+                                val |= AR5K_AR5312_RESET_WMAC0;
+                        if (mask & AR5K_RESET_CTL_BASEBAND)
+                                val |= AR5K_AR5312_RESET_BB0_COLD |
+                                       AR5K_AR5312_RESET_BB0_WARM;
+                } else {
+                        if (mask & AR5K_RESET_CTL_PCU)
+                                val |= AR5K_AR5312_RESET_WMAC1;
+                        if (mask & AR5K_RESET_CTL_BASEBAND)
+                                val |= AR5K_AR5312_RESET_BB1_COLD |
+                                       AR5K_AR5312_RESET_BB1_WARM;
+                }
+        }
+
+        /* Put BB/MAC into reset */
+        regval = __raw_readl(reg);
+        __raw_writel(regval | val, reg);
+        regval = __raw_readl(reg);
+        udelay(100);
+
+        /* Bring BB/MAC out of reset */
+        __raw_writel(regval & ~val, reg);
+        regval = __raw_readl(reg);
+
+        /*
+         * Reset configuration register (for hw byte-swap). Note that this
+         * is only set for big endian. We do the necessary magic in
+         * AR5K_INIT_CFG.
+         */
+        if ((flags & AR5K_RESET_CTL_PCU) == 0)
+                ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
+
+        return 0;
+}
+
+
+/*
  * Sleep control
  */
 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
@@ -326,7 +516,7 @@ commit:
  * register). After this MAC and Baseband are
  * disabled and a full reset is needed to come
  * back. This way we save as much power as possible
- * without puting the card on full sleep.
+ * without putting the card on full sleep.
  */
 int ath5k_hw_on_hold(struct ath5k_hw *ah)
 {
@@ -334,6 +524,9 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
         u32 bus_flags;
         int ret;
 
+        if (ath5k_get_bus_type(ah) == ATH_AHB)
+                return 0;
+
         /* Make sure device is awake */
         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
         if (ret) {
@@ -344,12 +537,12 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
         /*
          * Put chipset on warm reset...
          *
-         * Note: puting PCI core on warm reset on PCI-E cards
+         * Note: putting PCI core on warm reset on PCI-E cards
          * results card to hang and always return 0xffff... so
          * we ingore that flag for PCI-E cards. On PCI cards
          * this flag gets cleared after 64 PCI clocks.
          */
-        bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
+        bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 
         if (ah->ah_version == AR5K_AR5210) {
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
@@ -378,7 +571,6 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
 
 /*
  * Bring up MAC + PHY Chips and program PLL
- * TODO: Half/Quarter rate support
  */
 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 {
@@ -390,22 +582,24 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
         mode = 0;
         clock = 0;
 
-        /* Wakeup the device */
-        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
-        if (ret) {
-                ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
-                return ret;
+        if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
+                /* Wakeup the device */
+                ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+                if (ret) {
+                        ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
+                        return ret;
+                }
         }
 
         /*
          * Put chipset on warm reset...
          *
-         * Note: puting PCI core on warm reset on PCI-E cards
+         * Note: putting PCI core on warm reset on PCI-E cards
          * results card to hang and always return 0xffff... so
          * we ingore that flag for PCI-E cards. On PCI cards
          * this flag gets cleared after 64 PCI clocks.
          */
-        bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
+        bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 
         if (ah->ah_version == AR5K_AR5210) {
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
@@ -413,8 +607,12 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
                         mdelay(2);
         } else {
-                ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
-                        AR5K_RESET_CTL_BASEBAND | bus_flags);
+                if (ath5k_get_bus_type(ah) == ATH_AHB)
+                        ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
+                                AR5K_RESET_CTL_BASEBAND);
+                else
+                        ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+                                AR5K_RESET_CTL_BASEBAND | bus_flags);
         }
 
         if (ret) {
@@ -429,9 +627,15 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                 return ret;
         }
 
-        /* ...clear reset control register and pull device out of
-         * warm reset */
-        if (ath5k_hw_nic_reset(ah, 0)) {
+        /* ...reset configuration regiter on Wisoc ...
+         * ...clear reset control register and pull device out of
+         * warm reset on others */
+        if (ath5k_get_bus_type(ah) == ATH_AHB)
+                ret = ath5k_hw_wisoc_reset(ah, 0);
+        else
+                ret = ath5k_hw_nic_reset(ah, 0);
+
+        if (ret) {
                 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
                 return -EIO;
         }
@@ -466,7 +670,8 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                                  * CCK headers) operation. We need to test
                                  * this, 5211 might support ofdm-only g after
                                  * all, there are also initial register values
-                                 * in the code for g mode (see initvals.c). */
+                                 * in the code for g mode (see initvals.c).
+                                 */
                                 if (ah->ah_version == AR5K_AR5211)
                                         mode |= AR5K_PHY_MODE_MOD_OFDM;
                                 else
@@ -479,6 +684,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                 } else if (flags & CHANNEL_5GHZ) {
                         mode |= AR5K_PHY_MODE_FREQ_5GHZ;
 
+                        /* Different PLL setting for 5413 */
                         if (ah->ah_radio == AR5K_RF5413)
                                 clock = AR5K_PHY_PLL_40MHZ_5413;
                         else
@@ -496,12 +702,29 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                         return -EINVAL;
                 }
 
-                if (flags & CHANNEL_TURBO)
-                        turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
+                /*XXX: Can bwmode be used with dynamic mode ?
+                 * (I don't think it supports 44MHz) */
+                /* On 2425 initvals TURBO_SHORT is not pressent */
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
+                        turbo = AR5K_PHY_TURBO_MODE |
+                                (ah->ah_radio == AR5K_RF2425) ? 0 :
+                                AR5K_PHY_TURBO_SHORT;
+                } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
+                        if (ah->ah_radio == AR5K_RF5413) {
+                                mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
+                                        AR5K_PHY_MODE_HALF_RATE :
+                                        AR5K_PHY_MODE_QUARTER_RATE;
+                        } else if (ah->ah_version == AR5K_AR5212) {
+                                clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
+                                        AR5K_PHY_PLL_HALF_RATE :
+                                        AR5K_PHY_PLL_QUARTER_RATE;
+                        }
+                }
+
         } else { /* Reset the device */
 
                 /* ...enable Atheros turbo mode if requested */
-                if (flags & CHANNEL_TURBO)
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
                         ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
                                         AR5K_PHY_TURBO);
         }
@@ -522,107 +745,10 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
         return 0;
 }
 
-/*
- * If there is an external 32KHz crystal available, use it
- * as ref. clock instead of 32/40MHz clock and baseband clocks
- * to save power during sleep or restore normal 32/40MHz
- * operation.
- *
- * XXX: When operating on 32KHz certain PHY registers (27 - 31,
- *      123 - 127) require delay on access.
- */
-static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
-{
-        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-        u32 scal, spending, usec32;
-
-        /* Only set 32KHz settings if we have an external
-         * 32KHz crystal present */
-        if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
-        AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
-        enable) {
-
-                /* 1 usec/cycle */
-                AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
-                /* Set up tsf increment on each cycle */
-                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
-
-                /* Set baseband sleep control registers
-                 * and sleep control rate */
-                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413) ||
-                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                        spending = 0x14;
-                else
-                        spending = 0x18;
-                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413) ||
-                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
-                        ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
-                        ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
-                        ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
-                        ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
-                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
-                } else {
-                        ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
-                        ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
-                        ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
-                        ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
-                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
-                }
-
-                /* Enable sleep clock operation */
-                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_EN);
-
-        } else {
-
-                /* Disable sleep clock operation and
-                 * restore default parameters */
-                AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_EN);
-
-                AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
-
-                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
-                ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
-
-                if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
-                        scal = AR5K_PHY_SCAL_32MHZ_2417;
-                else if (ee->ee_is_hb63)
-                        scal = AR5K_PHY_SCAL_32MHZ_HB63;
-                else
-                        scal = AR5K_PHY_SCAL_32MHZ;
-                ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
-
-                ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
-                ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
 
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413) ||
-                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                        spending = 0x14;
-                else
-                        spending = 0x18;
-                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413))
-                        usec32 = 39;
-                else
-                        usec32 = 31;
-                AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
-
-                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
-        }
-}
+/**************************************\
+* Post-initvals register modifications *
+\**************************************/
 
 /* TODO: Half/Quarter rate */
 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
@@ -663,22 +789,10 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
                                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
 
-        /* Set DAC/ADC delays */
-        if (ah->ah_version == AR5K_AR5212) {
-                u32 scal;
-                struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-                if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
-                        scal = AR5K_PHY_SCAL_32MHZ_2417;
-                else if (ee->ee_is_hb63)
-                        scal = AR5K_PHY_SCAL_32MHZ_HB63;
-                else
-                        scal = AR5K_PHY_SCAL_32MHZ;
-                ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
-        }
-
         /* Set fast ADC */
         if ((ah->ah_radio == AR5K_RF5413) ||
-        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
+                (ah->ah_radio == AR5K_RF2317) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
                 u32 fast_adc = true;
 
                 if (channel->center_freq == 2462 ||
@@ -706,33 +820,68 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
         }
 
         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
-                u32 usec_reg;
-                /* 5311 has different tx/rx latency masks
-                 * from 5211, since we deal 5311 the same
-                 * as 5211 when setting initvals, shift
-                 * values here to their proper locations */
-                usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
-                ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
-                                AR5K_USEC_32 |
-                                AR5K_USEC_TX_LATENCY_5211 |
-                                AR5K_REG_SM(29,
-                                AR5K_USEC_RX_LATENCY_5210)),
-                                AR5K_USEC_5211);
                 /* Clear QCU/DCU clock gating register */
                 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
                 /* Set DAC/ADC delays */
-                ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
+                ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
+                                                AR5K_PHY_SCAL);
                 /* Enable PCU FIFO corruption ECO */
                 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
                                         AR5K_DIAG_SW_ECO_ENABLE);
         }
+
+        if (ah->ah_bwmode) {
+                /* Increase PHY switch and AGC settling time
+                 * on turbo mode (ath5k_hw_commit_eeprom_settings
+                 * will override settling time if available) */
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
+
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
+                                                AR5K_PHY_SETTLING_AGC,
+                                                AR5K_AGC_SETTLING_TURBO);
+
+                        /* XXX: Initvals indicate we only increase
+                         * switch time on AR5212, 5211 and 5210
+                         * only change agc time (bug?) */
+                        if (ah->ah_version == AR5K_AR5212)
+                                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
+                                                AR5K_PHY_SETTLING_SWITCH,
+                                                AR5K_SWITCH_SETTLING_TURBO);
+
+                        if (ah->ah_version == AR5K_AR5210) {
+                                /* Set Frame Control Register */
+                                ath5k_hw_reg_write(ah,
+                                        (AR5K_PHY_FRAME_CTL_INI |
+                                        AR5K_PHY_TURBO_MODE |
+                                        AR5K_PHY_TURBO_SHORT | 0x2020),
+                                        AR5K_PHY_FRAME_CTL_5210);
+                        }
+                /* On 5413 PHY force window length for half/quarter rate*/
+                } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
+                (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
+                                                AR5K_PHY_FRAME_CTL_WIN_LEN,
+                                                3);
+                }
+        } else if (ah->ah_version == AR5K_AR5210) {
+                /* Set Frame Control Register for normal operation */
+                ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
+                                                AR5K_PHY_FRAME_CTL_5210);
+        }
 }
 
 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
-                struct ieee80211_channel *channel, u8 ee_mode)
+                struct ieee80211_channel *channel)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         s16 cck_ofdm_pwr_delta;
+        u8 ee_mode;
+
+        /* TODO: Add support for AR5210 EEPROM */
+        if (ah->ah_version == AR5K_AR5210)
+                return;
+
+        ee_mode = ath5k_eeprom_mode_from_channel(channel);
 
         /* Adjust power delta for channel 14 */
         if (channel->center_freq == 2484)
@@ -772,7 +921,7 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
                 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
                 AR5K_PHY_NFTHRES);
 
-        if ((channel->hw_value & CHANNEL_TURBO) &&
+        if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
         (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
                 /* Switch settling time (Turbo) */
                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
@@ -870,143 +1019,175 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
 }
 
-/*
- * Main reset function
- */
+
+/*********************\
+* Main reset function *
+\*********************/
+
 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
-        struct ieee80211_channel *channel, bool change_channel)
+                struct ieee80211_channel *channel, bool fast, bool skip_pcu)
 {
-        struct ath_common *common = ath5k_hw_common(ah);
-        u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
-        u32 phy_tst1;
-        u8 mode, freq, ee_mode;
+        u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
+        u8 mode;
         int i, ret;
 
-        ee_mode = 0;
-        staid1_flags = 0;
         tsf_up = 0;
         tsf_lo = 0;
-        freq = 0;
         mode = 0;
 
         /*
-         * Save some registers before a reset
+         * Sanity check for fast flag
+         * Fast channel change only available
+         * on AR2413/AR5413.
          */
-        /*DCU/Antenna selection not available on 5210*/
-        if (ah->ah_version != AR5K_AR5210) {
+        if (fast && (ah->ah_radio != AR5K_RF2413) &&
+        (ah->ah_radio != AR5K_RF5413))
+                fast = 0;
 
-                switch (channel->hw_value & CHANNEL_MODES) {
-                case CHANNEL_A:
-                        mode = AR5K_MODE_11A;
-                        freq = AR5K_INI_RFGAIN_5GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11A;
-                        break;
-                case CHANNEL_G:
-                        mode = AR5K_MODE_11G;
-                        freq = AR5K_INI_RFGAIN_2GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11G;
-                        break;
-                case CHANNEL_B:
-                        mode = AR5K_MODE_11B;
-                        freq = AR5K_INI_RFGAIN_2GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11B;
-                        break;
-                case CHANNEL_T:
-                        mode = AR5K_MODE_11A_TURBO;
-                        freq = AR5K_INI_RFGAIN_5GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11A;
-                        break;
-                case CHANNEL_TG:
-                        if (ah->ah_version == AR5K_AR5211) {
-                                ATH5K_ERR(ah->ah_sc,
-                                        "TurboG mode not available on 5211");
-                                return -EINVAL;
-                        }
-                        mode = AR5K_MODE_11G_TURBO;
-                        freq = AR5K_INI_RFGAIN_2GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11G;
-                        break;
-                case CHANNEL_XR:
-                        if (ah->ah_version == AR5K_AR5211) {
-                                ATH5K_ERR(ah->ah_sc,
-                                        "XR mode not available on 5211");
-                                return -EINVAL;
-                        }
-                        mode = AR5K_MODE_XR;
-                        freq = AR5K_INI_RFGAIN_5GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11A;
-                        break;
-                default:
+        /* Disable sleep clock operation
+         * to avoid register access delay on certain
+         * PHY registers */
+        if (ah->ah_version == AR5K_AR5212)
+                ath5k_hw_set_sleep_clock(ah, false);
+
+        /*
+         * Stop PCU
+         */
+        ath5k_hw_stop_rx_pcu(ah);
+
+        /*
+         * Stop DMA
+         *
+         * Note: If DMA didn't stop continue
+         * since only a reset will fix it.
+         */
+        ret = ath5k_hw_dma_stop(ah);
+
+        /* RF Bus grant won't work if we have pending
+         * frames */
+        if (ret && fast) {
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
+                        "DMA didn't stop, falling back to normal reset\n");
+                fast = 0;
+                /* Non fatal, just continue with
+                 * normal reset */
+                ret = 0;
+        }
+
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+                mode = AR5K_MODE_11A;
+                break;
+        case CHANNEL_G:
+
+                if (ah->ah_version <= AR5K_AR5211) {
                         ATH5K_ERR(ah->ah_sc,
-                                "invalid channel: %d\n", channel->center_freq);
+                                "G mode not available on 5210/5211");
                         return -EINVAL;
                 }
 
-                if (change_channel) {
-                        /*
-                         * Save frame sequence count
-                         * For revs. after Oahu, only save
-                         * seq num for DCU 0 (Global seq num)
-                         */
-                        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
+                mode = AR5K_MODE_11G;
+                break;
+        case CHANNEL_B:
 
-                                for (i = 0; i < 10; i++)
-                                        s_seq[i] = ath5k_hw_reg_read(ah,
-                                                AR5K_QUEUE_DCU_SEQNUM(i));
+                if (ah->ah_version < AR5K_AR5211) {
+                        ATH5K_ERR(ah->ah_sc,
+                                "B mode not available on 5210");
+                        return -EINVAL;
+                }
 
-                        } else {
-                                s_seq[0] = ath5k_hw_reg_read(ah,
-                                                AR5K_QUEUE_DCU_SEQNUM(0));
-                        }
+                mode = AR5K_MODE_11B;
+                break;
+        case CHANNEL_XR:
+                if (ah->ah_version == AR5K_AR5211) {
+                        ATH5K_ERR(ah->ah_sc,
+                                "XR mode not available on 5211");
+                        return -EINVAL;
+                }
+                mode = AR5K_MODE_XR;
+                break;
+        default:
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return -EINVAL;
+        }
 
-                        /* TSF accelerates on AR5211 durring reset
-                         * As a workaround save it here and restore
-                         * it later so that it's back in time after
-                         * reset. This way it'll get re-synced on the
-                         * next beacon without breaking ad-hoc.
-                         *
-                         * On AR5212 TSF is almost preserved across a
-                         * reset so it stays back in time anyway and
-                         * we don't have to save/restore it.
-                         *
-                         * XXX: Since this breaks power saving we have
-                         * to disable power saving until we receive the
-                         * next beacon, so we can resync beacon timers */
-                        if (ah->ah_version == AR5K_AR5211) {
-                                tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
-                                tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
-                        }
+        /*
+         * If driver requested fast channel change and DMA has stopped
+         * go on. If it fails continue with a normal reset.
+         */
+        if (fast) {
+                ret = ath5k_hw_phy_init(ah, channel, mode, true);
+                if (ret) {
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
+                                "fast chan change failed, falling back to normal reset\n");
+                        /* Non fatal, can happen eg.
+                         * on mode change */
+                        ret = 0;
+                } else {
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
+                                "fast chan change successful\n");
+                        return 0;
                 }
+        }
+
+        /*
+         * Save some registers before a reset
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                /*
+                 * Save frame sequence count
+                 * For revs. after Oahu, only save
+                 * seq num for DCU 0 (Global seq num)
+                 */
+                if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 
-                if (ah->ah_version == AR5K_AR5212) {
-                        /* Restore normal 32/40MHz clock operation
-                         * to avoid register access delay on certain
-                         * PHY registers */
-                        ath5k_hw_set_sleep_clock(ah, false);
+                        for (i = 0; i < 10; i++)
+                                s_seq[i] = ath5k_hw_reg_read(ah,
+                                        AR5K_QUEUE_DCU_SEQNUM(i));
 
-                        /* Since we are going to write rf buffer
-                         * check if we have any pending gain_F
-                         * optimization settings */
-                        if (change_channel && ah->ah_rf_banks != NULL)
-                                ath5k_hw_gainf_calibrate(ah);
+                } else {
+                        s_seq[0] = ath5k_hw_reg_read(ah,
+                                        AR5K_QUEUE_DCU_SEQNUM(0));
+                }
+
+                /* TSF accelerates on AR5211 during reset
+                 * As a workaround save it here and restore
+                 * it later so that it's back in time after
+                 * reset. This way it'll get re-synced on the
+                 * next beacon without breaking ad-hoc.
+                 *
+                 * On AR5212 TSF is almost preserved across a
+                 * reset so it stays back in time anyway and
+                 * we don't have to save/restore it.
+                 *
+                 * XXX: Since this breaks power saving we have
+                 * to disable power saving until we receive the
+                 * next beacon, so we can resync beacon timers */
+                if (ah->ah_version == AR5K_AR5211) {
+                        tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
+                        tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
                 }
         }
 
+
         /*GPIOs*/
         s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
                                         AR5K_PCICFG_LEDSTATE;
         s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
         s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
 
-        /* AR5K_STA_ID1 flags, only preserve antenna
-         * settings and ack/cts rate mode */
-        staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
-                        (AR5K_STA_ID1_DEFAULT_ANTENNA |
-                        AR5K_STA_ID1_DESC_ANTENNA |
-                        AR5K_STA_ID1_RTS_DEF_ANTENNA |
-                        AR5K_STA_ID1_ACKCTS_6MB |
-                        AR5K_STA_ID1_BASE_RATE_11B |
-                        AR5K_STA_ID1_SELFGEN_DEF_ANT);
+
+        /*
+         * Since we are going to write rf buffer
+         * check if we have any pending gain_F
+         * optimization settings
+         */
+        if (ah->ah_version == AR5K_AR5212 &&
+        (ah->ah_radio <= AR5K_RF5112)) {
+                if (!fast && ah->ah_rf_banks != NULL)
+                                ath5k_hw_gainf_calibrate(ah);
+        }
 
         /* Wakeup the device */
         ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
@@ -1021,121 +1202,42 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                                                         AR5K_PHY(0));
 
         /* Write initial settings */
-        ret = ath5k_hw_write_initvals(ah, mode, change_channel);
+        ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
         if (ret)
                 return ret;
 
+        /* Initialize core clock settings */
+        ath5k_hw_init_core_clock(ah);
+
         /*
-         * 5211/5212 Specific
+         * Tweak initval settings for revised
+         * chipsets and add some more config
+         * bits
          */
-        if (ah->ah_version != AR5K_AR5210) {
-
-                /*
-                 * Write initial RF gain settings
-                 * This should work for both 5111/5112
-                 */
-                ret = ath5k_hw_rfgain_init(ah, freq);
-                if (ret)
-                        return ret;
-
-                mdelay(1);
-
-                /*
-                 * Tweak initval settings for revised
-                 * chipsets and add some more config
-                 * bits
-                 */
-                ath5k_hw_tweak_initval_settings(ah, channel);
-
-                /*
-                 * Set TX power
-                 */
-                ret = ath5k_hw_txpower(ah, channel, ee_mode,
-                                        ah->ah_txpower.txp_max_pwr / 2);
-                if (ret)
-                        return ret;
-
-                /* Write rate duration table only on AR5212 and if
-                 * virtual interface has already been brought up
-                 * XXX: rethink this after new mode changes to
-                 * mac80211 are integrated */
-                if (ah->ah_version == AR5K_AR5212 &&
-                        ah->ah_sc->vif != NULL)
-                        ath5k_hw_write_rate_duration(ah, mode);
-
-                /*
-                 * Write RF buffer
-                 */
-                ret = ath5k_hw_rfregs_init(ah, channel, mode);
-                if (ret)
-                        return ret;
-
-
-                /* Write OFDM timings on 5212*/
-                if (ah->ah_version == AR5K_AR5212 &&
-                        channel->hw_value & CHANNEL_OFDM) {
+        ath5k_hw_tweak_initval_settings(ah, channel);
 
-                        ret = ath5k_hw_write_ofdm_timings(ah, channel);
-                        if (ret)
-                                return ret;
+        /* Commit values from EEPROM */
+        ath5k_hw_commit_eeprom_settings(ah, channel);
 
-                        /* Spur info is available only from EEPROM versions
-                         * bigger than 5.3 but but the EEPOM routines will use
-                         * static values for older versions */
-                        if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
-                                ath5k_hw_set_spur_mitigation_filter(ah,
-                                                                    channel);
-                }
-
-                /*Enable/disable 802.11b mode on 5111
-                (enable 2111 frequency converter + CCK)*/
-                if (ah->ah_radio == AR5K_RF5111) {
-                        if (mode == AR5K_MODE_11B)
-                                AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
-                                    AR5K_TXCFG_B_MODE);
-                        else
-                                AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
-                                    AR5K_TXCFG_B_MODE);
-                }
-
-                /* Commit values from EEPROM */
-                ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
-
-        } else {
-                /*
-                 * For 5210 we do all initialization using
-                 * initvals, so we don't have to modify
-                 * any settings (5210 also only supports
-                 * a/aturbo modes)
-                 */
-                mdelay(1);
-                /* Disable phy and wait */
-                ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
-                mdelay(1);
-        }
 
         /*
          * Restore saved values
          */
 
-        /*DCU/Antenna selection not available on 5210*/
+        /* Seqnum, TSF */
         if (ah->ah_version != AR5K_AR5210) {
+                if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
+                        for (i = 0; i < 10; i++)
+                                ath5k_hw_reg_write(ah, s_seq[i],
+                                        AR5K_QUEUE_DCU_SEQNUM(i));
+                } else {
+                        ath5k_hw_reg_write(ah, s_seq[0],
+                                AR5K_QUEUE_DCU_SEQNUM(0));
+                }
 
-                if (change_channel) {
-                        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
-                                for (i = 0; i < 10; i++)
-                                        ath5k_hw_reg_write(ah, s_seq[i],
-                                                AR5K_QUEUE_DCU_SEQNUM(i));
-                        } else {
-                                ath5k_hw_reg_write(ah, s_seq[0],
-                                        AR5K_QUEUE_DCU_SEQNUM(0));
-                        }
-
-
-                        if (ah->ah_version == AR5K_AR5211) {
-                                ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
-                                ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
-                        }
+                if (ah->ah_version == AR5K_AR5211) {
+                        ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
+                        ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
                 }
         }
 
@@ -1146,203 +1248,34 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
         ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
         ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
 
-        /* Restore sta_id flags and preserve our mac address*/
-        ath5k_hw_reg_write(ah,
-                           get_unaligned_le32(common->macaddr),
-                           AR5K_STA_ID0);
-        ath5k_hw_reg_write(ah,
-                           staid1_flags | get_unaligned_le16(common->macaddr + 4),
-                           AR5K_STA_ID1);
-
-
         /*
-         * Configure PCU
+         * Initialize PCU
          */
-
-        /* Restore bssid and bssid mask */
-        ath5k_hw_set_associd(ah);
-
-        /* Set PCU config */
-        ath5k_hw_set_opmode(ah, op_mode);
-
-        /* Clear any pending interrupts
-         * PISR/SISR Not available on 5210 */
-        if (ah->ah_version != AR5K_AR5210)
-                ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
-
-        /* Set RSSI/BRSSI thresholds
-         *
-         * Note: If we decide to set this value
-         * dynamicaly, have in mind that when AR5K_RSSI_THR
-         * register is read it might return 0x40 if we haven't
-         * wrote anything to it plus BMISS RSSI threshold is zeroed.
-         * So doing a save/restore procedure here isn't the right
-         * choice. Instead store it on ath5k_hw */
-        ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
-                                AR5K_TUNE_BMISS_THRES <<
-                                AR5K_RSSI_THR_BMISS_S),
-                                AR5K_RSSI_THR);
-
-        /* MIC QoS support */
-        if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
-                ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
-                ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
-        }
-
-        /* QoS NOACK Policy */
-        if (ah->ah_version == AR5K_AR5212) {
-                ath5k_hw_reg_write(ah,
-                        AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
-                        AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
-                        AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
-                        AR5K_QOS_NOACK);
-        }
-
+        ath5k_hw_pcu_init(ah, op_mode, mode);
 
         /*
-         * Configure PHY
+         * Initialize PHY
          */
-
-        /* Set channel on PHY */
-        ret = ath5k_hw_channel(ah, channel);
-        if (ret)
+        ret = ath5k_hw_phy_init(ah, channel, mode, false);
+        if (ret) {
+                ATH5K_ERR(ah->ah_sc,
+                        "failed to initialize PHY (%i) !\n", ret);
                 return ret;
-
-        /*
-         * Enable the PHY and wait until completion
-         * This includes BaseBand and Synthesizer
-         * activation.
-         */
-        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
-
-        /*
-         * On 5211+ read activation -> rx delay
-         * and use it.
-         *
-         * TODO: Half/quarter rate support
-         */
-        if (ah->ah_version != AR5K_AR5210) {
-                u32 delay;
-                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
-                        AR5K_PHY_RX_DELAY_M;
-                delay = (channel->hw_value & CHANNEL_CCK) ?
-                        ((delay << 2) / 22) : (delay / 10);
-
-                udelay(100 + (2 * delay));
-        } else {
-                mdelay(1);
-        }
-
-        /*
-         * Perform ADC test to see if baseband is ready
-         * Set tx hold and check adc test register
-         */
-        phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
-        ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
-        for (i = 0; i <= 20; i++) {
-                if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
-                        break;
-                udelay(200);
-        }
-        ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
-
-        /*
-         * Start automatic gain control calibration
-         *
-         * During AGC calibration RX path is re-routed to
-         * a power detector so we don't receive anything.
-         *
-         * This method is used to calibrate some static offsets
-         * used together with on-the fly I/Q calibration (the
-         * one performed via ath5k_hw_phy_calibrate), that doesn't
-         * interrupt rx path.
-         *
-         * While rx path is re-routed to the power detector we also
-         * start a noise floor calibration, to measure the
-         * card's noise floor (the noise we measure when we are not
-         * transmiting or receiving anything).
-         *
-         * If we are in a noisy environment AGC calibration may time
-         * out and/or noise floor calibration might timeout.
-         */
-        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
-                                AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
-
-        /* At the same time start I/Q calibration for QAM constellation
-         * -no need for CCK- */
-        ah->ah_calibration = false;
-        if (!(mode == AR5K_MODE_11B)) {
-                ah->ah_calibration = true;
-                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
-                                AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
-                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
-                                AR5K_PHY_IQ_RUN);
         }
 
-        /* Wait for gain calibration to finish (we check for I/Q calibration
-         * during ath5k_phy_calibrate) */
-        if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
-                        AR5K_PHY_AGCCTL_CAL, 0, false)) {
-                ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
-                        channel->center_freq);
-        }
-
-        /* Restore antenna mode */
-        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
-
-        /* Restore slot time and ACK timeouts */
-        if (ah->ah_coverage_class > 0)
-                ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
-
         /*
          * Configure QCUs/DCUs
          */
-
-        /* TODO: HW Compression support for data queues */
-        /* TODO: Burst prefetch for data queues */
-
-        /*
-         * Reset queues and start beacon timers at the end of the reset routine
-         * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
-         * Note: If we want we can assign multiple qcus on one dcu.
-         */
-        for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
-                ret = ath5k_hw_reset_tx_queue(ah, i);
-                if (ret) {
-                        ATH5K_ERR(ah->ah_sc,
-                                "failed to reset TX queue #%d\n", i);
-                        return ret;
-                }
-        }
+        ret = ath5k_hw_init_queues(ah);
+        if (ret)
+                return ret;
 
 
         /*
-         * Configure DMA/Interrupts
+         * Initialize DMA/Interrupts
          */
+        ath5k_hw_dma_init(ah);
 
-        /*
-         * Set Rx/Tx DMA Configuration
-         *
-         * Set standard DMA size (128). Note that
-         * a DMA size of 512 causes rx overruns and tx errors
-         * on pci-e cards (tested on 5424 but since rx overruns
-         * also occur on 5416/5418 with madwifi we set 128
-         * for all PCI-E cards to be safe).
-         *
-         * XXX: need to check 5210 for this
-         * TODO: Check out tx triger level, it's always 64 on dumps but I
-         * guess we can tweak it and see how it goes ;-)
-         */
-        if (ah->ah_version != AR5K_AR5210) {
-                AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
-                        AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
-                AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
-                        AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
-        }
-
-        /* Pre-enable interrupts on 5211/5212*/
-        if (ah->ah_version != AR5K_AR5210)
-                ath5k_hw_set_imr(ah, ah->ah_imr);
 
         /* Enable 32KHz clock function for AR5212+ chips
          * Set clocks to 32KHz operation and use an
diff --git a/drivers/net/wireless/ath/ath5k/rfbuffer.h b/drivers/net/wireless/ath/ath5k/rfbuffer.h
index e50baff66175..16b67e84906d 100644
--- a/drivers/net/wireless/ath/ath5k/rfbuffer.h
+++ b/drivers/net/wireless/ath/ath5k/rfbuffer.h
@@ -25,10 +25,10 @@
  *
  * We don't write on those registers directly but
  * we send a data packet on the chip, using a special register,
- * that holds all the settings we need. After we 've sent the
+ * that holds all the settings we need. After we've sent the
  * data packet, we write on another special register to notify hw
  * to apply the settings. This is done so that control registers
- * can be dynamicaly programmed during operation and the settings
+ * can be dynamically programmed during operation and the settings
  * are applied faster on the hw.
  *
  * We call each data packet an "RF Bank" and all the data we write
@@ -51,7 +51,7 @@
 struct ath5k_ini_rfbuffer {
         u8      rfb_bank;               /* RF Bank number */
         u16     rfb_ctrl_register;      /* RF Buffer control register */
-        u32     rfb_mode_data[5];       /* RF Buffer data for each mode */
+        u32     rfb_mode_data[3];       /* RF Buffer data for each mode */
 };
 
 /*
@@ -79,8 +79,10 @@ struct ath5k_rf_reg {
  * life easier by using an index for each register
  * instead of a full rfb_field */
 enum ath5k_rf_regs_idx {
+        /* BANK 2 */
+        AR5K_RF_TURBO = 0,
         /* BANK 6 */
-        AR5K_RF_OB_2GHZ = 0,
+        AR5K_RF_OB_2GHZ,
         AR5K_RF_OB_5GHZ,
         AR5K_RF_DB_2GHZ,
         AR5K_RF_DB_5GHZ,
@@ -134,6 +136,9 @@ enum ath5k_rf_regs_idx {
 * RF5111 (Sombrero) *
 \*******************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF5111_RF_TURBO            { 1, 3,   0 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF5111_OB_2GHZ             { 3, 119, 0 }
 #define AR5K_RF5111_DB_2GHZ             { 3, 122, 0 }
@@ -158,6 +163,7 @@ enum ath5k_rf_regs_idx {
 #define AR5K_RF5111_MAX_TIME            { 2, 49,  0 }
 
 static const struct ath5k_rf_reg rf_regs_5111[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF5111_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5111_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5111_DB_2GHZ},
         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5111_OB_5GHZ},
@@ -177,97 +183,52 @@ static const struct ath5k_rf_reg rf_regs_5111[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5111[] = {
-        { 0, 0x989c,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
-        { 0, 0x989c,
-            { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
-        { 0, 0x98d4,
-            { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
-        { 1, 0x98d4,
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d4,
-            { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
-        { 3, 0x98d8,
-            { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
-        { 6, 0x989c,
-            { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
-        { 6, 0x989c,
-            { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
-        { 6, 0x989c,
-            { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
-        { 6, 0x989c,
-            { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
-        { 6, 0x98d4,
-            { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
-        { 7, 0x989c,
-            { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
-        { 7, 0x989c,
-            { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
-        { 7, 0x989c,
-            { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
-        { 7, 0x989c,
-            { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
-        { 7, 0x989c,
-            { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
-        { 7, 0x989c,
-            { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
-        { 7, 0x989c,
-            { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00380000, 0x00380000, 0x00380000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x000000c0, 0x00000080 } },
+        { 0, 0x989c, { 0x000400f9, 0x000400ff, 0x000400fd } },
+        { 0, 0x98d4, { 0x00000000, 0x00000004, 0x00000004 } },
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d4, { 0x00000010, 0x00000010, 0x00000010 } },
+        { 3, 0x98d8, { 0x00601068, 0x00601068, 0x00601068 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x04000000, 0x04000000, 0x04000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x0a000000, 0x00000000 } },
+        { 6, 0x989c, { 0x003800c0, 0x023800c0, 0x003800c0 } },
+        { 6, 0x989c, { 0x00020006, 0x00000006, 0x00020006 } },
+        { 6, 0x989c, { 0x00000089, 0x00000089, 0x00000089 } },
+        { 6, 0x989c, { 0x000000a0, 0x000000a0, 0x000000a0 } },
+        { 6, 0x989c, { 0x00040007, 0x00040007, 0x00040007 } },
+        { 6, 0x98d4, { 0x0000001a, 0x0000001a, 0x0000001a } },
+        { 7, 0x989c, { 0x00000040, 0x00000040, 0x00000040 } },
+        { 7, 0x989c, { 0x00000010, 0x00000010, 0x00000010 } },
+        { 7, 0x989c, { 0x00000008, 0x00000008, 0x00000008 } },
+        { 7, 0x989c, { 0x0000004f, 0x0000004f, 0x0000004f } },
+        { 7, 0x989c, { 0x000000f1, 0x00000061, 0x000000f1 } },
+        { 7, 0x989c, { 0x0000904f, 0x0000904c, 0x0000904f } },
+        { 7, 0x989c, { 0x0000125a, 0x0000129a, 0x0000125a } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000f, 0x0000000e } },
 };
 
 
@@ -276,6 +237,9 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = {
 * RF5112/RF2112 (Derby) *
 \***********************/
 
+/* BANK 2 (Common)                      len  pos col */
+#define AR5K_RF5112X_RF_TURBO           { 1, 1,   2 }
+
 /* BANK 7 (Common)                      len  pos col */
 #define AR5K_RF5112X_GAIN_I             { 6, 14,  0 }
 #define AR5K_RF5112X_MIXVGA_OVR         { 1, 36,  0 }
@@ -307,6 +271,7 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = {
 #define AR5K_RF5112_PWD(_n)             { 1, (302 - _n), 3 }
 
 static const struct ath5k_rf_reg rf_regs_5112[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF5112X_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5112_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5112_DB_2GHZ},
         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5112_OB_5GHZ},
@@ -335,115 +300,61 @@ static const struct ath5k_rf_reg rf_regs_5112[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5112[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
-        { 3, 0x98dc,
-            { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
-        { 6, 0x989c,
-            { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
-        { 6, 0x989c,
-            { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
-        { 6, 0x989c,
-            { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
-        { 6, 0x989c,
-            { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
-        { 6, 0x989c,
-            { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
-        { 6, 0x989c,
-            { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
-        { 6, 0x989c,
-            { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
-        { 6, 0x989c,
-            { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
-        { 6, 0x989c,
-            { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
-        { 6, 0x989c,
-            { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
-        { 6, 0x989c,
-            { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
-        { 6, 0x989c,
-            { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
-        { 6, 0x989c,
-            { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
-        { 6, 0x989c,
-            { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
-        { 6, 0x989c,
-            { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
-        { 6, 0x989c,
-            { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
-        { 6, 0x989c,
-            { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
-        { 6, 0x989c,
-            { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
-        { 6, 0x989c,
-            { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
-        { 6, 0x989c,
-            { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
-        { 6, 0x989c,
-            { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
-        { 6, 0x989c,
-            { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
-        { 6, 0x989c,
-            { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
-        { 6, 0x989c,
-            { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
-        { 6, 0x989c,
-            { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
-        { 6, 0x989c,
-            { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
-        { 6, 0x989c,
-            { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
-        { 6, 0x989c,
-            { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
-        { 6, 0x98d0,
-            { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
-        { 7, 0x989c,
-            { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
-        { 7, 0x989c,
-            { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
-        { 7, 0x989c,
-            { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
-        { 7, 0x989c,
-            { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
-        { 7, 0x989c,
-            { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
-        { 7, 0x989c,
-            { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
-        { 7, 0x989c,
-            { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
-        { 7, 0x989c,
-            { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
-        { 7, 0x989c,
-            { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
-        { 7, 0x989c,
-            { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
-        { 7, 0x989c,
-            { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
-        { 7, 0x989c,
-            { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
-        { 7, 0x98c4,
-            { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
+        { 3, 0x98dc, { 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
+        { 6, 0x989c, { 0x00a00000, 0x00a00000, 0x00a00000 } },
+        { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00660000, 0x00660000, 0x00660000 } },
+        { 6, 0x989c, { 0x00db0000, 0x00db0000, 0x00db0000 } },
+        { 6, 0x989c, { 0x00f10000, 0x00f10000, 0x00f10000 } },
+        { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
+        { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x008b0000, 0x008b0000, 0x008b0000 } },
+        { 6, 0x989c, { 0x00600000, 0x00600000, 0x00600000 } },
+        { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
+        { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
+        { 6, 0x989c, { 0x00640000, 0x00640000, 0x00640000 } },
+        { 6, 0x989c, { 0x00200000, 0x00200000, 0x00200000 } },
+        { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
+        { 6, 0x989c, { 0x00250000, 0x00250000, 0x00250000 } },
+        { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
+        { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
+        { 6, 0x989c, { 0x00510000, 0x00510000, 0x00510000 } },
+        { 6, 0x989c, { 0x1c040000, 0x1c040000, 0x1c040000 } },
+        { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
+        { 6, 0x989c, { 0x00a10000, 0x00a10000, 0x00a10000 } },
+        { 6, 0x989c, { 0x00400000, 0x00400000, 0x00400000 } },
+        { 6, 0x989c, { 0x03090000, 0x03090000, 0x03090000 } },
+        { 6, 0x989c, { 0x06000000, 0x06000000, 0x06000000 } },
+        { 6, 0x989c, { 0x000000b0, 0x000000a8, 0x000000a8 } },
+        { 6, 0x989c, { 0x0000002e, 0x0000002e, 0x0000002e } },
+        { 6, 0x989c, { 0x006c4a41, 0x006c4af1, 0x006c4a61 } },
+        { 6, 0x989c, { 0x0050892a, 0x0050892b, 0x0050892b } },
+        { 6, 0x989c, { 0x00842400, 0x00842400, 0x00842400 } },
+        { 6, 0x989c, { 0x00c69200, 0x00c69200, 0x00c69200 } },
+        { 6, 0x98d0, { 0x0002000c, 0x0002000c, 0x0002000c } },
+        { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
+        { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
+        { 7, 0x989c, { 0x0000000a, 0x00000012, 0x00000012 } },
+        { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
+        { 7, 0x989c, { 0x000000c1, 0x000000c1, 0x000000c1 } },
+        { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
+        { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
+        { 7, 0x989c, { 0x00000022, 0x00000022, 0x00000022 } },
+        { 7, 0x989c, { 0x00000092, 0x00000092, 0x00000092 } },
+        { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
+        { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
+        { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
+        { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
 };
 
 /* RFX112A (Derby 2) */
@@ -477,6 +388,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112[] = {
 #define AR5K_RF5112A_XB5_LVL            { 2, 3,   3 }
 
 static const struct ath5k_rf_reg rf_regs_5112a[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF5112X_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5112A_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5112A_DB_2GHZ},
         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5112A_OB_5GHZ},
@@ -515,119 +427,63 @@ static const struct ath5k_rf_reg rf_regs_5112a[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
-        { 6, 0x989c,
-            { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
-        { 6, 0x989c,
-            { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
-        { 6, 0x989c,
-            { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
-        { 6, 0x989c,
-            { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
-        { 6, 0x989c,
-            { 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000 } },
-        { 6, 0x989c,
-            { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
-        { 6, 0x989c,
-            { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
-        { 6, 0x989c,
-            { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } },
-        { 6, 0x989c,
-            { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
-        { 6, 0x989c,
-            { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
-        { 6, 0x989c,
-            { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
-        { 6, 0x989c,
-            { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
-        { 6, 0x989c,
-            { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
-        { 6, 0x989c,
-            { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
-        { 6, 0x989c,
-            { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
-        { 6, 0x989c,
-            { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
-        { 6, 0x989c,
-            { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
-        { 6, 0x989c,
-            { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } },
-        { 6, 0x989c,
-            { 0x00270019, 0x00270019, 0x00270019, 0x00270019, 0x00270019 } },
-        { 6, 0x989c,
-            { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
-        { 6, 0x989c,
-            { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
-        { 6, 0x989c,
-            { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
-        { 6, 0x989c,
-            { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
-        { 6, 0x989c,
-            { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
-        { 6, 0x98d8,
-            { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
-        { 7, 0x989c,
-            { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
-        { 7, 0x989c,
-            { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
-        { 7, 0x989c,
-            { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
-        { 7, 0x989c,
-            { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
-        { 7, 0x989c,
-            { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
-        { 7, 0x989c,
-            { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
-        { 7, 0x989c,
-            { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
-        { 7, 0x989c,
-            { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
-        { 7, 0x989c,
-            { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
-        { 7, 0x989c,
-            { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
-        { 7, 0x989c,
-            { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
-        { 7, 0x989c,
-            { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
-        { 7, 0x98c4,
-            { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00800000, 0x00800000, 0x00800000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00010000, 0x00010000, 0x00010000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00180000, 0x00180000, 0x00180000 } },
+        { 6, 0x989c, { 0x00600000, 0x006e0000, 0x006e0000 } },
+        { 6, 0x989c, { 0x00c70000, 0x00c70000, 0x00c70000 } },
+        { 6, 0x989c, { 0x004b0000, 0x004b0000, 0x004b0000 } },
+        { 6, 0x989c, { 0x04480000, 0x04480000, 0x04480000 } },
+        { 6, 0x989c, { 0x004c0000, 0x004c0000, 0x004c0000 } },
+        { 6, 0x989c, { 0x00e40000, 0x00e40000, 0x00e40000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x043f0000, 0x043f0000, 0x043f0000 } },
+        { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
+        { 6, 0x989c, { 0x02190000, 0x02190000, 0x02190000 } },
+        { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
+        { 6, 0x989c, { 0x00b40000, 0x00b40000, 0x00b40000 } },
+        { 6, 0x989c, { 0x00990000, 0x00990000, 0x00990000 } },
+        { 6, 0x989c, { 0x00500000, 0x00500000, 0x00500000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
+        { 6, 0x989c, { 0xc0320000, 0xc0320000, 0xc0320000 } },
+        { 6, 0x989c, { 0x01740000, 0x01740000, 0x01740000 } },
+        { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
+        { 6, 0x989c, { 0x86280000, 0x86280000, 0x86280000 } },
+        { 6, 0x989c, { 0x31840000, 0x31840000, 0x31840000 } },
+        { 6, 0x989c, { 0x00f20080, 0x00f20080, 0x00f20080 } },
+        { 6, 0x989c, { 0x00270019, 0x00270019, 0x00270019 } },
+        { 6, 0x989c, { 0x00000003, 0x00000003, 0x00000003 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x000000b2, 0x000000b2, 0x000000b2 } },
+        { 6, 0x989c, { 0x00b02084, 0x00b02084, 0x00b02084 } },
+        { 6, 0x989c, { 0x004125a4, 0x004125a4, 0x004125a4 } },
+        { 6, 0x989c, { 0x00119220, 0x00119220, 0x00119220 } },
+        { 6, 0x989c, { 0x001a4800, 0x001a4800, 0x001a4800 } },
+        { 6, 0x98d8, { 0x000b0230, 0x000b0230, 0x000b0230 } },
+        { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
+        { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
+        { 7, 0x989c, { 0x00000012, 0x00000012, 0x00000012 } },
+        { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
+        { 7, 0x989c, { 0x000000d9, 0x000000d9, 0x000000d9 } },
+        { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
+        { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
+        { 7, 0x989c, { 0x000000a2, 0x000000a2, 0x000000a2 } },
+        { 7, 0x989c, { 0x00000052, 0x00000052, 0x00000052 } },
+        { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
+        { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
+        { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
+        { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
 };
 
 
@@ -636,11 +492,15 @@ static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
 * RF2413 (Griffin) *
 \******************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF2413_RF_TURBO            { 1, 1,   2 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF2413_OB_2GHZ             { 3, 168, 0 }
 #define AR5K_RF2413_DB_2GHZ             { 3, 165, 0 }
 
 static const struct ath5k_rf_reg rf_regs_2413[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF2413_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2413_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2413_DB_2GHZ},
 };
@@ -649,73 +509,40 @@ static const struct ath5k_rf_reg rf_regs_2413[] = {
  * XXX: a/aTurbo ???
  */
 static const struct ath5k_ini_rfbuffer rfb_2413[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x03000000, 0x03000000, 0x03000000, 0x03000000, 0x03000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x40400000, 0x40400000, 0x40400000, 0x40400000, 0x40400000 } },
-        { 6, 0x989c,
-            { 0x65050000, 0x65050000, 0x65050000, 0x65050000, 0x65050000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00420000, 0x00420000, 0x00420000, 0x00420000, 0x00420000 } },
-        { 6, 0x989c,
-            { 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000 } },
-        { 6, 0x989c,
-            { 0x00030000, 0x00030000, 0x00030000, 0x00030000, 0x00030000 } },
-        { 6, 0x989c,
-            { 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000 } },
-        { 6, 0x989c,
-            { 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000 } },
-        { 6, 0x989c,
-            { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
-        { 6, 0x989c,
-            { 0x04220000, 0x04220000, 0x04220000, 0x04220000, 0x04220000 } },
-        { 6, 0x989c,
-            { 0x00230018, 0x00230018, 0x00230018, 0x00230018, 0x00230018 } },
-        { 6, 0x989c,
-            { 0x00280000, 0x00280000, 0x00280060, 0x00280060, 0x00280060 } },
-        { 6, 0x989c,
-            { 0x005000c0, 0x005000c0, 0x005000c3, 0x005000c3, 0x005000c3 } },
-        { 6, 0x989c,
-            { 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f } },
-        { 6, 0x989c,
-            { 0x00000458, 0x00000458, 0x00000458, 0x00000458, 0x00000458 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000 } },
-        { 6, 0x98d8,
-            { 0x00400230, 0x00400230, 0x00400230, 0x00400230, 0x00400230 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0xf0000000, 0xf0000000, 0xf0000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x03000000, 0x03000000, 0x03000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x40400000, 0x40400000, 0x40400000 } },
+        { 6, 0x989c, { 0x65050000, 0x65050000, 0x65050000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00420000, 0x00420000, 0x00420000 } },
+        { 6, 0x989c, { 0x00b50000, 0x00b50000, 0x00b50000 } },
+        { 6, 0x989c, { 0x00030000, 0x00030000, 0x00030000 } },
+        { 6, 0x989c, { 0x00f70000, 0x00f70000, 0x00f70000 } },
+        { 6, 0x989c, { 0x009d0000, 0x009d0000, 0x009d0000 } },
+        { 6, 0x989c, { 0x00220000, 0x00220000, 0x00220000 } },
+        { 6, 0x989c, { 0x04220000, 0x04220000, 0x04220000 } },
+        { 6, 0x989c, { 0x00230018, 0x00230018, 0x00230018 } },
+        { 6, 0x989c, { 0x00280000, 0x00280060, 0x00280060 } },
+        { 6, 0x989c, { 0x005000c0, 0x005000c3, 0x005000c3 } },
+        { 6, 0x989c, { 0x0004007f, 0x0004007f, 0x0004007f } },
+        { 6, 0x989c, { 0x00000458, 0x00000458, 0x00000458 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x0000c000, 0x0000c000, 0x0000c000 } },
+        { 6, 0x98d8, { 0x00400230, 0x00400230, 0x00400230 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 
@@ -724,88 +551,57 @@ static const struct ath5k_ini_rfbuffer rfb_2413[] = {
 * RF2315/RF2316 (Cobra SoC) *
 \***************************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF2316_RF_TURBO            { 1, 1,   2 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF2316_OB_2GHZ             { 3, 178, 0 }
 #define AR5K_RF2316_DB_2GHZ             { 3, 175, 0 }
 
 static const struct ath5k_rf_reg rf_regs_2316[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF2316_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2316_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2316_DB_2GHZ},
 };
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_2316[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000 } },
-        { 6, 0x989c,
-            { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
-        { 6, 0x989c,
-            { 0x02000000, 0x02000000, 0x02000000, 0x02000000, 0x02000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x95150000, 0x95150000, 0x95150000, 0x95150000, 0x95150000 } },
-        { 6, 0x989c,
-            { 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00080000, 0x00080000, 0x00080000, 0x00080000, 0x00080000 } },
-        { 6, 0x989c,
-            { 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000 } },
-        { 6, 0x989c,
-            { 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000 } },
-        { 6, 0x989c,
-            { 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
-        { 6, 0x989c,
-            { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
-        { 6, 0x989c,
-            { 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000 } },
-        { 6, 0x989c,
-            { 0x10880000, 0x10880000, 0x10880000, 0x10880000, 0x10880000 } },
-        { 6, 0x989c,
-            { 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060 } },
-        { 6, 0x989c,
-            { 0x00a00000, 0x00a00000, 0x00a00080, 0x00a00080, 0x00a00080 } },
-        { 6, 0x989c,
-            { 0x00400000, 0x00400000, 0x0040000d, 0x0040000d, 0x0040000d } },
-        { 6, 0x989c,
-            { 0x00110400, 0x00110400, 0x00110400, 0x00110400, 0x00110400 } },
-        { 6, 0x989c,
-            { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
-        { 6, 0x989c,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 6, 0x989c,
-            { 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00 } },
-        { 6, 0x989c,
-            { 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8 } },
-        { 6, 0x98c0,
-            { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0xc0000000, 0xc0000000, 0xc0000000 } },
+        { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
+        { 6, 0x989c, { 0x02000000, 0x02000000, 0x02000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0xf8000000, 0xf8000000, 0xf8000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x95150000, 0x95150000, 0x95150000 } },
+        { 6, 0x989c, { 0xc1000000, 0xc1000000, 0xc1000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00080000, 0x00080000, 0x00080000 } },
+        { 6, 0x989c, { 0x00d50000, 0x00d50000, 0x00d50000 } },
+        { 6, 0x989c, { 0x000e0000, 0x000e0000, 0x000e0000 } },
+        { 6, 0x989c, { 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
+        { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
+        { 6, 0x989c, { 0x008a0000, 0x008a0000, 0x008a0000 } },
+        { 6, 0x989c, { 0x10880000, 0x10880000, 0x10880000 } },
+        { 6, 0x989c, { 0x008c0060, 0x008c0060, 0x008c0060 } },
+        { 6, 0x989c, { 0x00a00000, 0x00a00080, 0x00a00080 } },
+        { 6, 0x989c, { 0x00400000, 0x0040000d, 0x0040000d } },
+        { 6, 0x989c, { 0x00110400, 0x00110400, 0x00110400 } },
+        { 6, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
+        { 6, 0x989c, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 6, 0x989c, { 0x00000b00, 0x00000b00, 0x00000b00 } },
+        { 6, 0x989c, { 0x00000be8, 0x00000be8, 0x00000be8 } },
+        { 6, 0x98c0, { 0x00010000, 0x00010000, 0x00010000 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 
@@ -835,93 +631,50 @@ static const struct ath5k_rf_reg rf_regs_5413[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5413[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
-        { 3, 0x98dc,
-            { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
-        { 6, 0x989c,
-            { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
-        { 6, 0x989c,
-            { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
-        { 6, 0x989c,
-            { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
-        { 6, 0x989c,
-            { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
-        { 6, 0x989c,
-            { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
-        { 6, 0x989c,
-            { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
-        { 6, 0x989c,
-            { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
-        { 6, 0x989c,
-            { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
-        { 6, 0x989c,
-            { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
-        { 6, 0x989c,
-            { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
-        { 6, 0x989c,
-            { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
-        { 6, 0x989c,
-            { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
-        { 6, 0x989c,
-            { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
-        { 6, 0x989c,
-            { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
-        { 6, 0x989c,
-            { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
-        { 6, 0x989c,
-            { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
-        { 6, 0x989c,
-            { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
-        { 6, 0x989c,
-            { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
-        { 6, 0x989c,
-            { 0x00510040, 0x00510040, 0x00510040, 0x00510040, 0x00510040 } },
-        { 6, 0x989c,
-            { 0x005000da, 0x005000da, 0x005000da, 0x005000da, 0x005000da } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
-        { 6, 0x989c,
-            { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00002c00 } },
-        { 6, 0x98c8,
-            { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x00000008, 0x00000008, 0x00000008 } },
+        { 3, 0x98dc, { 0x00a000c0, 0x00e000c0, 0x00e000c0 } },
+        { 6, 0x989c, { 0x33000000, 0x33000000, 0x33000000 } },
+        { 6, 0x989c, { 0x01000000, 0x01000000, 0x01000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x1f000000, 0x1f000000, 0x1f000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00b80000, 0x00b80000, 0x00b80000 } },
+        { 6, 0x989c, { 0x00b70000, 0x00b70000, 0x00b70000 } },
+        { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
+        { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
+        { 6, 0x989c, { 0x00c00000, 0x00c00000, 0x00c00000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00d70000, 0x00d70000, 0x00d70000 } },
+        { 6, 0x989c, { 0x00610000, 0x00610000, 0x00610000 } },
+        { 6, 0x989c, { 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
+        { 6, 0x989c, { 0x00de0000, 0x00de0000, 0x00de0000 } },
+        { 6, 0x989c, { 0x007f0000, 0x007f0000, 0x007f0000 } },
+        { 6, 0x989c, { 0x043d0000, 0x043d0000, 0x043d0000 } },
+        { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
+        { 6, 0x989c, { 0x00440000, 0x00440000, 0x00440000 } },
+        { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
+        { 6, 0x989c, { 0x00100080, 0x00100080, 0x00100080 } },
+        { 6, 0x989c, { 0x0005c034, 0x0005c034, 0x0005c034 } },
+        { 6, 0x989c, { 0x003100f0, 0x003100f0, 0x003100f0 } },
+        { 6, 0x989c, { 0x000c011f, 0x000c011f, 0x000c011f } },
+        { 6, 0x989c, { 0x00510040, 0x00510040, 0x00510040 } },
+        { 6, 0x989c, { 0x005000da, 0x005000da, 0x005000da } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00004044, 0x00004044, 0x00004044 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x000060c0, 0x000060c0, 0x000060c0 } },
+        { 6, 0x989c, { 0x00002c00, 0x00003600, 0x00003600 } },
+        { 6, 0x98c8, { 0x00000403, 0x00040403, 0x00040403 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 
@@ -931,92 +684,59 @@ static const struct ath5k_ini_rfbuffer rfb_5413[] = {
 * AR2317 (Spider SoC)       *
 \***************************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF2425_RF_TURBO            { 1, 1,   2 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF2425_OB_2GHZ             { 3, 193, 0 }
 #define AR5K_RF2425_DB_2GHZ             { 3, 190, 0 }
 
 static const struct ath5k_rf_reg rf_regs_2425[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF2425_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2425_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2425_DB_2GHZ},
 };
 
 /* Default mode specific settings
- * XXX: a/aTurbo ?
  */
 static const struct ath5k_ini_rfbuffer rfb_2425[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
-        { 6, 0x989c,
-            { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
-        { 6, 0x989c,
-            { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
-        { 6, 0x989c,
-            { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
-        { 6, 0x989c,
-            { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
-        { 6, 0x989c,
-            { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
-        { 6, 0x989c,
-            { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
-        { 6, 0x989c,
-            { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
-        { 6, 0x989c,
-            { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
-        { 6, 0x989c,
-            { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
-        { 6, 0x98c4,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
+        { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
+        { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
+        { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
+        { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
+        { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
+        { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
+        { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
+        { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
+        { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
+        { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 /*
@@ -1024,158 +744,85 @@ static const struct ath5k_ini_rfbuffer rfb_2425[] = {
  * bank modification and get rid of this
  */
 static const struct ath5k_ini_rfbuffer rfb_2317[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
-        { 6, 0x989c,
-            { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
-        { 6, 0x989c,
-            { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
-        { 6, 0x989c,
-            { 0x00140100, 0x00140100, 0x00140100, 0x00140100, 0x00140100 } },
-        { 6, 0x989c,
-            { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
-        { 6, 0x989c,
-            { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
-        { 6, 0x989c,
-            { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
-        { 6, 0x989c,
-            { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
-        { 6, 0x989c,
-            { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
-        { 6, 0x989c,
-            { 0x00009688, 0x00009688, 0x00009688, 0x00009688, 0x00009688 } },
-        { 6, 0x98c4,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
+        { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
+        { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
+        { 6, 0x989c, { 0x00140100, 0x00140100, 0x00140100 } },
+        { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
+        { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
+        { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
+        { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
+        { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
+        { 6, 0x989c, { 0x00009688, 0x00009688, 0x00009688 } },
+        { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 /*
  * TODO: Handle the few differences with swan during
  * bank modification and get rid of this
- * XXX: a/aTurbo ?
  */
 static const struct ath5k_ini_rfbuffer rfb_2417[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
-        { 6, 0x989c,
-            { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
-        { 6, 0x989c,
-            { 0x00e70000, 0x00e70000, 0x80e70000, 0x80e70000, 0x00e70000 } },
-        { 6, 0x989c,
-            { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
-        { 6, 0x989c,
-            { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
-        { 6, 0x989c,
-            { 0x0007001a, 0x0007001a, 0x0207001a, 0x0207001a, 0x0007001a } },
-        { 6, 0x989c,
-            { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
-        { 6, 0x989c,
-            { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
-        { 6, 0x989c,
-            { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
-        { 6, 0x989c,
-            { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
-        { 6, 0x98c4,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
+        { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
+        { 6, 0x989c, { 0x00e70000, 0x80e70000, 0x80e70000 } },
+        { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
+        { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
+        { 6, 0x989c, { 0x0007001a, 0x0207001a, 0x0207001a } },
+        { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
+        { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
+        { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
+        { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
+        { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
diff --git a/drivers/net/wireless/ath/ath5k/sysfs.c b/drivers/net/wireless/ath/ath5k/sysfs.c
index 90757de7bf59..a073cdce1f15 100644
--- a/drivers/net/wireless/ath/ath5k/sysfs.c
+++ b/drivers/net/wireless/ath/ath5k/sysfs.c
@@ -10,7 +10,8 @@ static ssize_t ath5k_attr_show_##name(struct device *dev,		\
                         struct device_attribute *attr,                  \
                         char *buf)                                      \
 {                                                                       \
-        struct ath5k_softc *sc = dev_get_drvdata(dev);                  \
+        struct ieee80211_hw *hw = dev_get_drvdata(dev);                 \
+        struct ath5k_softc *sc = hw->priv;                              \
         return snprintf(buf, PAGE_SIZE, "%d\n", get);                   \
 }                                                                       \
                                                                         \
@@ -18,7 +19,8 @@ static ssize_t ath5k_attr_store_##name(struct device *dev,		\
                         struct device_attribute *attr,                  \
                         const char *buf, size_t count)                  \
 {                                                                       \
-        struct ath5k_softc *sc = dev_get_drvdata(dev);                  \
+        struct ieee80211_hw *hw = dev_get_drvdata(dev);                 \
+        struct ath5k_softc *sc = hw->priv;                              \
         int val;                                                        \
                                                                         \
         val = (int)simple_strtoul(buf, NULL, 10);                       \
@@ -33,7 +35,8 @@ static ssize_t ath5k_attr_show_##name(struct device *dev,		\
                         struct device_attribute *attr,                  \
                         char *buf)                                      \
 {                                                                       \
-        struct ath5k_softc *sc = dev_get_drvdata(dev);                  \
+        struct ieee80211_hw *hw = dev_get_drvdata(dev);                 \
+        struct ath5k_softc *sc = hw->priv;                              \
         return snprintf(buf, PAGE_SIZE, "%d\n", get);                   \
 }                                                                       \
 static DEVICE_ATTR(name, S_IRUGO, ath5k_attr_show_##name, NULL)
@@ -95,7 +98,7 @@ static struct attribute_group ath5k_attribute_group_ani = {
 int
 ath5k_sysfs_register(struct ath5k_softc *sc)
 {
-        struct device *dev = &sc->pdev->dev;
+        struct device *dev = sc->dev;
         int err;
 
         err = sysfs_create_group(&dev->kobj, &ath5k_attribute_group_ani);
@@ -110,7 +113,7 @@ ath5k_sysfs_register(struct ath5k_softc *sc)
 void
 ath5k_sysfs_unregister(struct ath5k_softc *sc)
 {
-        struct device *dev = &sc->pdev->dev;
+        struct device *dev = sc->dev;
 
         sysfs_remove_group(&dev->kobj, &ath5k_attribute_group_ani);
 }
diff --git a/drivers/net/wireless/ath/ath5k/trace.h b/drivers/net/wireless/ath/ath5k/trace.h
new file mode 100644
index 000000000000..2de68adb6240
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/trace.h
@@ -0,0 +1,107 @@
+#if !defined(__TRACE_ATH5K_H) || defined(TRACE_HEADER_MULTI_READ)
+#define __TRACE_ATH5K_H
+
+#include <linux/tracepoint.h>
+#include "base.h"
+
+#ifndef CONFIG_ATH5K_TRACER
+#undef TRACE_EVENT
+#define TRACE_EVENT(name, proto, ...) \
+static inline void trace_ ## name(proto) {}
+#endif
+
+struct sk_buff;
+
+#define PRIV_ENTRY  __field(struct ath5k_softc *, priv)
+#define PRIV_ASSIGN __entry->priv = priv
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM ath5k
+
+TRACE_EVENT(ath5k_rx,
+        TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb),
+        TP_ARGS(priv, skb),
+        TP_STRUCT__entry(
+                PRIV_ENTRY
+                __field(unsigned long, skbaddr)
+                __dynamic_array(u8, frame, skb->len)
+        ),
+        TP_fast_assign(
+                PRIV_ASSIGN;
+                __entry->skbaddr = (unsigned long) skb;
+                memcpy(__get_dynamic_array(frame), skb->data, skb->len);
+        ),
+        TP_printk(
+                "[%p] RX skb=%lx", __entry->priv, __entry->skbaddr
+        )
+);
+
+TRACE_EVENT(ath5k_tx,
+        TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb,
+                 struct ath5k_txq *q),
+
+        TP_ARGS(priv, skb, q),
+
+        TP_STRUCT__entry(
+                PRIV_ENTRY
+                __field(unsigned long, skbaddr)
+                __field(u8, qnum)
+                __dynamic_array(u8, frame, skb->len)
+        ),
+
+        TP_fast_assign(
+                PRIV_ASSIGN;
+                __entry->skbaddr = (unsigned long) skb;
+                __entry->qnum = (u8) q->qnum;
+                memcpy(__get_dynamic_array(frame), skb->data, skb->len);
+        ),
+
+        TP_printk(
+                "[%p] TX skb=%lx q=%d", __entry->priv, __entry->skbaddr,
+                __entry->qnum
+        )
+);
+
+TRACE_EVENT(ath5k_tx_complete,
+        TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb,
+                 struct ath5k_txq *q, struct ath5k_tx_status *ts),
+
+        TP_ARGS(priv, skb, q, ts),
+
+        TP_STRUCT__entry(
+                PRIV_ENTRY
+                __field(unsigned long, skbaddr)
+                __field(u8, qnum)
+                __field(u8, ts_status)
+                __field(s8, ts_rssi)
+                __field(u8, ts_antenna)
+        ),
+
+        TP_fast_assign(
+                PRIV_ASSIGN;
+                __entry->skbaddr = (unsigned long) skb;
+                __entry->qnum = (u8) q->qnum;
+                __entry->ts_status = ts->ts_status;
+                __entry->ts_rssi =  ts->ts_rssi;
+                __entry->ts_antenna = ts->ts_antenna;
+        ),
+
+        TP_printk(
+                "[%p] TX end skb=%lx q=%d stat=%x rssi=%d ant=%x",
+                __entry->priv, __entry->skbaddr, __entry->qnum,
+                __entry->ts_status, __entry->ts_rssi, __entry->ts_antenna
+        )
+);
+
+#endif /* __TRACE_ATH5K_H */
+
+#ifdef CONFIG_ATH5K_TRACER
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH ../../drivers/net/wireless/ath/ath5k
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE trace
+
+#include <trace/define_trace.h>
+
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index 35f23bdc442f..d9c08c619a3a 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -5,7 +5,7 @@ config ATH9K_COMMON
 
 config ATH9K
         tristate "Atheros 802.11n wireless cards support"
-        depends on PCI && MAC80211
+        depends on MAC80211
         select ATH9K_HW
         select MAC80211_LEDS
         select LEDS_CLASS
@@ -23,6 +23,24 @@ config ATH9K
 
           If you choose to build a module, it'll be called ath9k.
 
+config ATH9K_PCI
+        bool "Atheros ath9k PCI/PCIe bus support"
+        depends on ATH9K && PCI
+        ---help---
+          This option enables the PCI bus support in ath9k.
+
+          Say Y, if you have a compatible PCI/PCIe wireless card.
+
+config ATH9K_AHB
+        bool "Atheros ath9k AHB bus support"
+        depends on ATH9K
+        default n
+        ---help---
+          This option enables the AHB bus support in ath9k.
+
+          Say Y, if you have a SoC with a compatible built-in
+          wireless MAC. Say N if unsure.
+
 config ATH9K_DEBUGFS
         bool "Atheros ath9k debugging"
         depends on ATH9K && DEBUG_FS
@@ -32,6 +50,14 @@ config ATH9K_DEBUGFS
 
           Also required for changing debug message flags at run time.
 
+config ATH9K_RATE_CONTROL
+        bool "Atheros ath9k rate control"
+        depends on ATH9K
+        default y
+        ---help---
+          Say Y, if you want to use the ath9k specific rate control
+          module instead of minstrel_ht.
+
 config ATH9K_HTC
        tristate "Atheros HTC based wireless cards support"
        depends on USB && MAC80211
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 973ae4f49f35..05a6fade7b1c 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -4,11 +4,10 @@ ath9k-y +=	beacon.o \
                 main.o \
                 recv.o \
                 xmit.o \
-                virtual.o \
-                rc.o
 
-ath9k-$(CONFIG_PCI) += pci.o
-ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o
+ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
+ath9k-$(CONFIG_ATH9K_PCI) += pci.o
+ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
 
 obj-$(CONFIG_ATH9K) += ath9k.o
@@ -46,6 +45,9 @@ ath9k_htc-y +=	htc_hst.o \
                 htc_drv_txrx.o \
                 htc_drv_main.o \
                 htc_drv_beacon.o \
-                htc_drv_init.o
+                htc_drv_init.o \
+                htc_drv_gpio.o
+
+ath9k_htc-$(CONFIG_ATH9K_HTC_DEBUGFS) += htc_drv_debug.o
 
 obj-$(CONFIG_ATH9K_HTC) += ath9k_htc.o
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 1a984b02e9e5..5b49cd03bfdf 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
  * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
  *
@@ -21,6 +21,18 @@
 #include <linux/ath9k_platform.h>
 #include "ath9k.h"
 
+static const struct platform_device_id ath9k_platform_id_table[] = {
+        {
+                .name = "ath9k",
+                .driver_data = AR5416_AR9100_DEVID,
+        },
+        {
+                .name = "ar934x_wmac",
+                .driver_data = AR9300_DEVID_AR9340,
+        },
+        {},
+};
+
 /* return bus cachesize in 4B word units */
 static void ath_ahb_read_cachesize(struct ath_common *common, int *csz)
 {
@@ -35,10 +47,9 @@ static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 
         pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
         if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "%s: flash read failed, offset %08x "
-                          "is out of range\n",
-                          __func__, off);
+                ath_err(common,
+                        "%s: flash read failed, offset %08x is out of range\n",
+                        __func__, off);
                 return false;
         }
 
@@ -55,10 +66,10 @@ static struct ath_bus_ops ath_ahb_bus_ops  = {
 static int ath_ahb_probe(struct platform_device *pdev)
 {
         void __iomem *mem;
-        struct ath_wiphy *aphy;
         struct ath_softc *sc;
         struct ieee80211_hw *hw;
         struct resource *res;
+        const struct platform_device_id *id = platform_get_device_id(pdev);
         int irq;
         int ret = 0;
         struct ath_hw *ah;
@@ -77,7 +88,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
                 goto err_out;
         }
 
-        mem = ioremap_nocache(res->start, res->end - res->start + 1);
+        mem = ioremap_nocache(res->start, resource_size(res));
         if (mem == NULL) {
                 dev_err(&pdev->dev, "ioremap failed\n");
                 ret = -ENOMEM;
@@ -93,8 +104,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
 
         irq = res->start;
 
-        hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
-                                sizeof(struct ath_softc), &ath9k_ops);
+        hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
         if (hw == NULL) {
                 dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
                 ret = -ENOMEM;
@@ -104,11 +114,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
         SET_IEEE80211_DEV(hw, &pdev->dev);
         platform_set_drvdata(pdev, hw);
 
-        aphy = hw->priv;
-        sc = (struct ath_softc *) (aphy + 1);
-        aphy->sc = sc;
-        aphy->hw = hw;
-        sc->pri_wiphy = aphy;
+        sc = hw->priv;
         sc->hw = hw;
         sc->dev = &pdev->dev;
         sc->mem = mem;
@@ -123,7 +129,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
                 goto err_free_hw;
         }
 
-        ret = ath9k_init_device(AR5416_AR9100_DEVID, sc, 0x0, &ath_ahb_bus_ops);
+        ret = ath9k_init_device(id->driver_data, sc, 0x0, &ath_ahb_bus_ops);
         if (ret) {
                 dev_err(&pdev->dev, "failed to initialize device\n");
                 goto err_irq;
@@ -152,8 +158,7 @@ static int ath_ahb_remove(struct platform_device *pdev)
         struct ieee80211_hw *hw = platform_get_drvdata(pdev);
 
         if (hw) {
-                struct ath_wiphy *aphy = hw->priv;
-                struct ath_softc *sc = aphy->sc;
+                struct ath_softc *sc = hw->priv;
                 void __iomem *mem = sc->mem;
 
                 ath9k_deinit_device(sc);
@@ -173,8 +178,11 @@ static struct platform_driver ath_ahb_driver = {
                 .name   = "ath9k",
                 .owner  = THIS_MODULE,
         },
+        .id_table    = ath9k_platform_id_table,
 };
 
+MODULE_DEVICE_TABLE(platform, ath9k_platform_id_table);
+
 int ath_ahb_init(void)
 {
         return platform_driver_register(&ath_ahb_driver);
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index a3d95cca8f0c..bfb6481f01f9 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/kernel.h>
 #include "hw.h"
 #include "hw-ops.h"
 
@@ -48,7 +49,7 @@ static const struct ani_ofdm_level_entry ofdm_level_table[] = {
         {  7,  8,  0  }  /* lvl 9 */
 };
 #define ATH9K_ANI_OFDM_NUM_LEVEL \
-        (sizeof(ofdm_level_table)/sizeof(ofdm_level_table[0]))
+        ARRAY_SIZE(ofdm_level_table)
 #define ATH9K_ANI_OFDM_MAX_LEVEL \
         (ATH9K_ANI_OFDM_NUM_LEVEL-1)
 #define ATH9K_ANI_OFDM_DEF_LEVEL \
@@ -94,7 +95,7 @@ static const struct ani_cck_level_entry cck_level_table[] = {
 };
 
 #define ATH9K_ANI_CCK_NUM_LEVEL \
-        (sizeof(cck_level_table)/sizeof(cck_level_table[0]))
+        ARRAY_SIZE(cck_level_table)
 #define ATH9K_ANI_CCK_MAX_LEVEL \
         (ATH9K_ANI_CCK_NUM_LEVEL-1)
 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
@@ -102,31 +103,9 @@ static const struct ani_cck_level_entry cck_level_table[] = {
 #define ATH9K_ANI_CCK_DEF_LEVEL \
         2 /* default level - matches the INI settings */
 
-/* Private to ani.c */
-static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
+static bool use_new_ani(struct ath_hw *ah)
 {
-        ath9k_hw_private_ops(ah)->ani_lower_immunity(ah);
-}
-
-int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
-                                 struct ath9k_channel *chan)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
-                if (ah->ani[i].c &&
-                    ah->ani[i].c->channel == chan->channel)
-                        return i;
-                if (ah->ani[i].c == NULL) {
-                        ah->ani[i].c = chan;
-                        return i;
-                }
-        }
-
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
-                  "No more channel states left. Using channel 0\n");
-
-        return 0;
+        return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
 }
 
 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
@@ -139,82 +118,34 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
 }
 
-static void ath9k_ani_restart_old(struct ath_hw *ah)
+static void ath9k_ani_restart(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
+        u32 ofdm_base = 0, cck_base = 0;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
         aniState->listenTime = 0;
 
-        if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
-                aniState->ofdmPhyErrBase = 0;
-                ath_print(common, ATH_DBG_ANI,
-                          "OFDM Trigger is too high for hw counters\n");
-        } else {
-                aniState->ofdmPhyErrBase =
-                        AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
-        }
-        if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
-                aniState->cckPhyErrBase = 0;
-                ath_print(common, ATH_DBG_ANI,
-                          "CCK Trigger is too high for hw counters\n");
-        } else {
-                aniState->cckPhyErrBase =
-                        AR_PHY_COUNTMAX - aniState->cckTrigHigh;
+        if (!use_new_ani(ah)) {
+                ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
+                cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
         }
-        ath_print(common, ATH_DBG_ANI,
-                  "Writing ofdmbase=%u   cckbase=%u\n",
-                  aniState->ofdmPhyErrBase,
-                  aniState->cckPhyErrBase);
-
-        ENABLE_REGWRITE_BUFFER(ah);
-
-        REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
-        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
-
-        REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
-
-        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
-
-        aniState->ofdmPhyErrCount = 0;
-        aniState->cckPhyErrCount = 0;
-}
 
-static void ath9k_ani_restart_new(struct ath_hw *ah)
-{
-        struct ar5416AniState *aniState;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
-        aniState->listenTime = 0;
-
-        aniState->ofdmPhyErrBase = 0;
-        aniState->cckPhyErrBase = 0;
-
-        ath_print(common, ATH_DBG_ANI,
-                  "Writing ofdmbase=%08x   cckbase=%08x\n",
-                  aniState->ofdmPhyErrBase,
-                  aniState->cckPhyErrBase);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Writing ofdmbase=%u   cckbase=%u\n", ofdm_base, cck_base);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
-        REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
+        REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
+        REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -228,10 +159,7 @@ static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
         struct ar5416AniState *aniState;
         int32_t rssi;
 
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
 
         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
@@ -300,10 +228,7 @@ static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
         struct ar5416AniState *aniState;
         int32_t rssi;
 
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
                                          aniState->noiseImmunityLevel + 1)) {
@@ -335,18 +260,18 @@ static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
 /* Adjust the OFDM Noise Immunity Level */
 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath_common *common = ath9k_hw_common(ah);
         const struct ani_ofdm_level_entry *entry_ofdm;
         const struct ani_cck_level_entry *entry_cck;
 
         aniState->noiseFloor = BEACON_RSSI(ah);
 
-        ath_print(common, ATH_DBG_ANI,
-                  "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
-                  aniState->ofdmNoiseImmunityLevel,
-                  immunityLevel, aniState->noiseFloor,
-                  aniState->rssiThrLow, aniState->rssiThrHigh);
+        ath_dbg(common, ATH_DBG_ANI,
+                "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
+                aniState->ofdmNoiseImmunityLevel,
+                immunityLevel, aniState->noiseFloor,
+                aniState->rssiThrLow, aniState->rssiThrHigh);
 
         aniState->ofdmNoiseImmunityLevel = immunityLevel;
 
@@ -380,14 +305,19 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
         }
 }
 
-static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
+static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        if (!use_new_ani(ah)) {
+                ath9k_hw_ani_ofdm_err_trigger_old(ah);
+                return;
+        }
+
+        aniState = &ah->curchan->ani;
 
         if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
                 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
@@ -398,17 +328,17 @@ static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
  */
 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath_common *common = ath9k_hw_common(ah);
         const struct ani_ofdm_level_entry *entry_ofdm;
         const struct ani_cck_level_entry *entry_cck;
 
         aniState->noiseFloor = BEACON_RSSI(ah);
-        ath_print(common, ATH_DBG_ANI,
-                  "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
-                  aniState->cckNoiseImmunityLevel, immunityLevel,
-                  aniState->noiseFloor, aniState->rssiThrLow,
-                  aniState->rssiThrHigh);
+        ath_dbg(common, ATH_DBG_ANI,
+                "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
+                aniState->cckNoiseImmunityLevel, immunityLevel,
+                aniState->noiseFloor, aniState->rssiThrLow,
+                aniState->rssiThrHigh);
 
         if ((ah->opmode == NL80211_IFTYPE_STATION ||
              ah->opmode == NL80211_IFTYPE_ADHOC) &&
@@ -428,7 +358,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
                                      entry_cck->fir_step_level);
 
         /* Skip MRC CCK for pre AR9003 families */
-        if (!AR_SREV_9300_20_OR_LATER(ah))
+        if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
                 return;
 
         if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
@@ -437,14 +367,19 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
                                      entry_cck->mrc_cck_on);
 }
 
-static void ath9k_hw_ani_cck_err_trigger_new(struct ath_hw *ah)
+static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        if (!use_new_ani(ah)) {
+                ath9k_hw_ani_cck_err_trigger_old(ah);
+                return;
+        }
+
+        aniState = &ah->curchan->ani;
 
         if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
                 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
@@ -455,7 +390,7 @@ static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
         struct ar5416AniState *aniState;
         int32_t rssi;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
 
         if (ah->opmode == NL80211_IFTYPE_AP) {
                 if (aniState->firstepLevel > 0) {
@@ -507,11 +442,16 @@ static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
  * only lower either OFDM or CCK errors per turn
  * we lower the other one next time
  */
-static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
+static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
+
+        if (!use_new_ani(ah)) {
+                ath9k_hw_ani_lower_immunity_old(ah);
+                return;
+        }
 
         /* lower OFDM noise immunity */
         if (aniState->ofdmNoiseImmunityLevel > 0 &&
@@ -525,90 +465,21 @@ static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
                 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
 }
 
-static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
-{
-        struct ath9k_channel *chan = ah->curchan;
-        struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
-        u8 clockrate; /* in MHz */
-
-        if (!ah->curchan) /* should really check for CCK instead */
-                clockrate = ATH9K_CLOCK_RATE_CCK;
-        else if (conf->channel->band == IEEE80211_BAND_2GHZ)
-                clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
-        else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
-                clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
-        else
-                clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
-
-        if (conf_is_ht40(conf))
-                return clockrate * 2;
-
-        return clockrate;
-}
-
-static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
-{
-        struct ar5416AniState *aniState;
-        struct ath_common *common = ath9k_hw_common(ah);
-        u32 txFrameCount, rxFrameCount, cycleCount;
-        int32_t listenTime;
-
-        txFrameCount = REG_READ(ah, AR_TFCNT);
-        rxFrameCount = REG_READ(ah, AR_RFCNT);
-        cycleCount = REG_READ(ah, AR_CCCNT);
-
-        aniState = ah->curani;
-        if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
-                listenTime = 0;
-                ah->stats.ast_ani_lzero++;
-                ath_print(common, ATH_DBG_ANI,
-                          "1st call: aniState->cycleCount=%d\n",
-                          aniState->cycleCount);
-        } else {
-                int32_t ccdelta = cycleCount - aniState->cycleCount;
-                int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
-                int32_t tfdelta = txFrameCount - aniState->txFrameCount;
-                int32_t clock_rate;
-
-                /*
-                 * convert HW counter values to ms using mode
-                 * specifix clock rate
-                 */
-                clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
-
-                listenTime = (ccdelta - rfdelta - tfdelta) / clock_rate;
-
-                ath_print(common, ATH_DBG_ANI,
-                          "cyclecount=%d, rfcount=%d, "
-                          "tfcount=%d, listenTime=%d CLOCK_RATE=%d\n",
-                          ccdelta, rfdelta, tfdelta, listenTime, clock_rate);
-        }
-
-        aniState->cycleCount = cycleCount;
-        aniState->txFrameCount = txFrameCount;
-        aniState->rxFrameCount = rxFrameCount;
-
-        return listenTime;
-}
-
 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
 {
         struct ar5416AniState *aniState;
         struct ath9k_channel *chan = ah->curchan;
         struct ath_common *common = ath9k_hw_common(ah);
-        int index;
 
         if (!DO_ANI(ah))
                 return;
 
-        index = ath9k_hw_get_ani_channel_idx(ah, chan);
-        aniState = &ah->ani[index];
-        ah->curani = aniState;
+        aniState = &ah->curchan->ani;
 
-        if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
+        if (ah->opmode != NL80211_IFTYPE_STATION
             && ah->opmode != NL80211_IFTYPE_ADHOC) {
-                ath_print(common, ATH_DBG_ANI,
-                          "Reset ANI state opmode %u\n", ah->opmode);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Reset ANI state opmode %u\n", ah->opmode);
                 ah->stats.ast_ani_reset++;
 
                 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -634,17 +505,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
                 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
                                      ATH9K_RX_FILTER_PHYERR);
 
-                if (ah->opmode == NL80211_IFTYPE_AP) {
-                        ah->curani->ofdmTrigHigh =
-                                ah->config.ofdm_trig_high;
-                        ah->curani->ofdmTrigLow =
-                                ah->config.ofdm_trig_low;
-                        ah->curani->cckTrigHigh =
-                                ah->config.cck_trig_high;
-                        ah->curani->cckTrigLow =
-                                ah->config.cck_trig_low;
-                }
-                ath9k_ani_restart_old(ah);
+                ath9k_ani_restart(ah);
                 return;
         }
 
@@ -666,7 +527,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
 
         ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
                              ~ATH9K_RX_FILTER_PHYERR);
-        ath9k_ani_restart_old(ah);
+        ath9k_ani_restart(ah);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -674,7 +535,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /*
@@ -682,15 +542,18 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
  * This routine should be called for every hardware reset and for
  * every channel change.
  */
-static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
+void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath9k_channel *chan = ah->curchan;
         struct ath_common *common = ath9k_hw_common(ah);
 
         if (!DO_ANI(ah))
                 return;
 
+        if (!use_new_ani(ah))
+                return ath9k_ani_reset_old(ah, is_scanning);
+
         BUG_ON(aniState == NULL);
         ah->stats.ast_ani_reset++;
 
@@ -721,16 +584,14 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
                     ATH9K_ANI_OFDM_DEF_LEVEL ||
                     aniState->cckNoiseImmunityLevel !=
                     ATH9K_ANI_CCK_DEF_LEVEL) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "Restore defaults: opmode %u "
-                                  "chan %d Mhz/0x%x is_scanning=%d "
-                                  "ofdm:%d cck:%d\n",
-                                  ah->opmode,
-                                  chan->channel,
-                                  chan->channelFlags,
-                                  is_scanning,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  aniState->cckNoiseImmunityLevel);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
+                                ah->opmode,
+                                chan->channel,
+                                chan->channelFlags,
+                                is_scanning,
+                                aniState->ofdmNoiseImmunityLevel,
+                                aniState->cckNoiseImmunityLevel);
 
                         ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
                         ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
@@ -739,16 +600,14 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
                 /*
                  * restore historical levels for this channel
                  */
-                ath_print(common, ATH_DBG_ANI,
-                          "Restore history: opmode %u "
-                          "chan %d Mhz/0x%x is_scanning=%d "
-                          "ofdm:%d cck:%d\n",
-                          ah->opmode,
-                          chan->channel,
-                          chan->channelFlags,
-                          is_scanning,
-                          aniState->ofdmNoiseImmunityLevel,
-                          aniState->cckNoiseImmunityLevel);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
+                        ah->opmode,
+                        chan->channel,
+                        chan->channelFlags,
+                        is_scanning,
+                        aniState->ofdmNoiseImmunityLevel,
+                        aniState->cckNoiseImmunityLevel);
 
                         ath9k_hw_set_ofdm_nil(ah,
                                               aniState->ofdmNoiseImmunityLevel);
@@ -760,7 +619,7 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
          * enable phy counters if hw supports or if not, enable phy
          * interrupts (so we can count each one)
          */
-        ath9k_ani_restart_new(ah);
+        ath9k_ani_restart(ah);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -768,28 +627,30 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
-static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
-                                     struct ath9k_channel *chan)
+static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
 {
-        struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
-        int32_t listenTime;
-        u32 phyCnt1, phyCnt2;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
+        u32 ofdm_base = 0;
+        u32 cck_base = 0;
         u32 ofdmPhyErrCnt, cckPhyErrCnt;
+        u32 phyCnt1, phyCnt2;
+        int32_t listenTime;
 
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
+        ath_hw_cycle_counters_update(common);
+        listenTime = ath_hw_get_listen_time(common);
 
-        listenTime = ath9k_hw_ani_get_listen_time(ah);
-        if (listenTime < 0) {
+        if (listenTime <= 0) {
                 ah->stats.ast_ani_lneg++;
-                ath9k_ani_restart_old(ah);
-                return;
+                ath9k_ani_restart(ah);
+                return false;
+        }
+
+        if (!use_new_ani(ah)) {
+                ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
+                cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
         }
 
         aniState->listenTime += listenTime;
@@ -799,215 +660,95 @@ static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
 
-        if (phyCnt1 < aniState->ofdmPhyErrBase ||
-            phyCnt2 < aniState->cckPhyErrBase) {
-                if (phyCnt1 < aniState->ofdmPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt1 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt1,
-                                  aniState->ofdmPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_1,
-                                  aniState->ofdmPhyErrBase);
+        if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
+                if (phyCnt1 < ofdm_base) {
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "phyCnt1 0x%x, resetting counter value to 0x%x\n",
+                                phyCnt1, ofdm_base);
+                        REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
                         REG_WRITE(ah, AR_PHY_ERR_MASK_1,
                                   AR_PHY_ERR_OFDM_TIMING);
                 }
-                if (phyCnt2 < aniState->cckPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt2 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt2,
-                                  aniState->cckPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_2,
-                                  aniState->cckPhyErrBase);
+                if (phyCnt2 < cck_base) {
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "phyCnt2 0x%x, resetting counter value to 0x%x\n",
+                                phyCnt2, cck_base);
+                        REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
                         REG_WRITE(ah, AR_PHY_ERR_MASK_2,
                                   AR_PHY_ERR_CCK_TIMING);
                 }
-                return;
+                return false;
         }
 
-        ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
+        ofdmPhyErrCnt = phyCnt1 - ofdm_base;
         ah->stats.ast_ani_ofdmerrs +=
                 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
         aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
 
-        cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
+        cckPhyErrCnt = phyCnt2 - cck_base;
         ah->stats.ast_ani_cckerrs +=
                 cckPhyErrCnt - aniState->cckPhyErrCount;
         aniState->cckPhyErrCount = cckPhyErrCnt;
-
-        if (aniState->listenTime > 5 * ah->aniperiod) {
-                if (aniState->ofdmPhyErrCount <= aniState->listenTime *
-                    aniState->ofdmTrigLow / 1000 &&
-                    aniState->cckPhyErrCount <= aniState->listenTime *
-                    aniState->cckTrigLow / 1000)
-                        ath9k_hw_ani_lower_immunity(ah);
-                ath9k_ani_restart_old(ah);
-        } else if (aniState->listenTime > ah->aniperiod) {
-                if (aniState->ofdmPhyErrCount > aniState->listenTime *
-                    aniState->ofdmTrigHigh / 1000) {
-                        ath9k_hw_ani_ofdm_err_trigger_old(ah);
-                        ath9k_ani_restart_old(ah);
-                } else if (aniState->cckPhyErrCount >
-                           aniState->listenTime * aniState->cckTrigHigh /
-                           1000) {
-                        ath9k_hw_ani_cck_err_trigger_old(ah);
-                        ath9k_ani_restart_old(ah);
-                }
-        }
+        return true;
 }
 
-static void ath9k_hw_ani_monitor_new(struct ath_hw *ah,
-                                     struct ath9k_channel *chan)
+void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
 {
         struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
-        int32_t listenTime;
-        u32 phyCnt1, phyCnt2;
-        u32 ofdmPhyErrCnt, cckPhyErrCnt;
         u32 ofdmPhyErrRate, cckPhyErrRate;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
         if (WARN_ON(!aniState))
                 return;
 
-        listenTime = ath9k_hw_ani_get_listen_time(ah);
-        if (listenTime <= 0) {
-                ah->stats.ast_ani_lneg++;
-                /* restart ANI period if listenTime is invalid */
-                ath_print(common, ATH_DBG_ANI,
-                          "listenTime=%d - on new ani monitor\n",
-                          listenTime);
-                ath9k_ani_restart_new(ah);
+        if (!ath9k_hw_ani_read_counters(ah))
                 return;
-        }
-
-        aniState->listenTime += listenTime;
-
-        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
-
-        phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
-        phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
-
-        if (phyCnt1 < aniState->ofdmPhyErrBase ||
-            phyCnt2 < aniState->cckPhyErrBase) {
-                if (phyCnt1 < aniState->ofdmPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt1 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt1,
-                                  aniState->ofdmPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_1,
-                                  aniState->ofdmPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_MASK_1,
-                                  AR_PHY_ERR_OFDM_TIMING);
-                }
-                if (phyCnt2 < aniState->cckPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt2 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt2,
-                                  aniState->cckPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_2,
-                                  aniState->cckPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_MASK_2,
-                                  AR_PHY_ERR_CCK_TIMING);
-                }
-                return;
-        }
-
-        ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
-        ah->stats.ast_ani_ofdmerrs +=
-                ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
-        aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
-
-        cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
-        ah->stats.ast_ani_cckerrs +=
-                cckPhyErrCnt - aniState->cckPhyErrCount;
-        aniState->cckPhyErrCount = cckPhyErrCnt;
-
-        ath_print(common, ATH_DBG_ANI,
-                  "Errors: OFDM=0x%08x-0x%08x=%d   "
-                  "CCK=0x%08x-0x%08x=%d\n",
-                  phyCnt1,
-                  aniState->ofdmPhyErrBase,
-                  ofdmPhyErrCnt,
-                  phyCnt2,
-                  aniState->cckPhyErrBase,
-                  cckPhyErrCnt);
 
         ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
                          aniState->listenTime;
         cckPhyErrRate =  aniState->cckPhyErrCount * 1000 /
                          aniState->listenTime;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
-                  "errs=%d/s ofdm_turn=%d\n",
-                  listenTime, aniState->ofdmNoiseImmunityLevel,
-                  ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
-                  cckPhyErrRate, aniState->ofdmsTurn);
+        ath_dbg(common, ATH_DBG_ANI,
+                "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
+                aniState->listenTime,
+                aniState->ofdmNoiseImmunityLevel,
+                ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
+                cckPhyErrRate, aniState->ofdmsTurn);
 
         if (aniState->listenTime > 5 * ah->aniperiod) {
-                if (ofdmPhyErrRate <= aniState->ofdmTrigLow &&
-                    cckPhyErrRate <= aniState->cckTrigLow) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "1. listenTime=%d OFDM:%d errs=%d/s(<%d)  "
-                                  "CCK:%d errs=%d/s(<%d) -> "
-                                  "ath9k_hw_ani_lower_immunity()\n",
-                                  aniState->listenTime,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  ofdmPhyErrRate,
-                                  aniState->ofdmTrigLow,
-                                  aniState->cckNoiseImmunityLevel,
-                                  cckPhyErrRate,
-                                  aniState->cckTrigLow);
+                if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
+                    cckPhyErrRate <= ah->config.cck_trig_low) {
                         ath9k_hw_ani_lower_immunity(ah);
                         aniState->ofdmsTurn = !aniState->ofdmsTurn;
                 }
-                ath_print(common, ATH_DBG_ANI,
-                          "1 listenTime=%d ofdm=%d/s cck=%d/s - "
-                          "calling ath9k_ani_restart_new()\n",
-                          aniState->listenTime, ofdmPhyErrRate, cckPhyErrRate);
-                ath9k_ani_restart_new(ah);
+                ath9k_ani_restart(ah);
         } else if (aniState->listenTime > ah->aniperiod) {
                 /* check to see if need to raise immunity */
-                if (ofdmPhyErrRate > aniState->ofdmTrigHigh &&
-                    (cckPhyErrRate <= aniState->cckTrigHigh ||
+                if (ofdmPhyErrRate > ah->config.ofdm_trig_high &&
+                    (cckPhyErrRate <= ah->config.cck_trig_high ||
                      aniState->ofdmsTurn)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "2 listenTime=%d OFDM:%d errs=%d/s(>%d) -> "
-                                  "ath9k_hw_ani_ofdm_err_trigger_new()\n",
-                                  aniState->listenTime,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  ofdmPhyErrRate,
-                                  aniState->ofdmTrigHigh);
-                        ath9k_hw_ani_ofdm_err_trigger_new(ah);
-                        ath9k_ani_restart_new(ah);
+                        ath9k_hw_ani_ofdm_err_trigger(ah);
+                        ath9k_ani_restart(ah);
                         aniState->ofdmsTurn = false;
-                } else if (cckPhyErrRate > aniState->cckTrigHigh) {
-                        ath_print(common, ATH_DBG_ANI,
-                                 "3 listenTime=%d CCK:%d errs=%d/s(>%d) -> "
-                                 "ath9k_hw_ani_cck_err_trigger_new()\n",
-                                 aniState->listenTime,
-                                 aniState->cckNoiseImmunityLevel,
-                                 cckPhyErrRate,
-                                 aniState->cckTrigHigh);
-                        ath9k_hw_ani_cck_err_trigger_new(ah);
-                        ath9k_ani_restart_new(ah);
+                } else if (cckPhyErrRate > ah->config.cck_trig_high) {
+                        ath9k_hw_ani_cck_err_trigger(ah);
+                        ath9k_ani_restart(ah);
                         aniState->ofdmsTurn = true;
                 }
         }
 }
+EXPORT_SYMBOL(ath9k_hw_ani_monitor);
 
 void ath9k_enable_mib_counters(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
+        ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");
 
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -1022,7 +763,6 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /* Freeze the MIB counters, get the stats and then clear them */
@@ -1030,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
+        ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");
 
         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -1040,53 +780,12 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
 
-u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
-                                  u32 *rxc_pcnt,
-                                  u32 *rxf_pcnt,
-                                  u32 *txf_pcnt)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        static u32 cycles, rx_clear, rx_frame, tx_frame;
-        u32 good = 1;
-
-        u32 rc = REG_READ(ah, AR_RCCNT);
-        u32 rf = REG_READ(ah, AR_RFCNT);
-        u32 tf = REG_READ(ah, AR_TFCNT);
-        u32 cc = REG_READ(ah, AR_CCCNT);
-
-        if (cycles == 0 || cycles > cc) {
-                ath_print(common, ATH_DBG_ANI,
-                          "cycle counter wrap. ExtBusy = 0\n");
-                good = 0;
-        } else {
-                u32 cc_d = cc - cycles;
-                u32 rc_d = rc - rx_clear;
-                u32 rf_d = rf - rx_frame;
-                u32 tf_d = tf - tx_frame;
-
-                if (cc_d != 0) {
-                        *rxc_pcnt = rc_d * 100 / cc_d;
-                        *rxf_pcnt = rf_d * 100 / cc_d;
-                        *txf_pcnt = tf_d * 100 / cc_d;
-                } else {
-                        good = 0;
-                }
-        }
-
-        cycles = cc;
-        rx_frame = rf;
-        rx_clear = rc;
-        tx_frame = tf;
-
-        return good;
-}
-
 /*
  * Process a MIB interrupt.  We may potentially be invoked because
  * any of the MIB counters overflow/trigger so don't assume we're
  * here because a PHY error counter triggered.
  */
-static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah)
+void ath9k_hw_proc_mib_event(struct ath_hw *ah)
 {
         u32 phyCnt1, phyCnt2;
 
@@ -1114,81 +813,24 @@ static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah)
         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
-                struct ar5416AniState *aniState = ah->curani;
-                u32 ofdmPhyErrCnt, cckPhyErrCnt;
 
-                /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
-                ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
-                ah->stats.ast_ani_ofdmerrs +=
-                        ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
-                aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
+                if (!use_new_ani(ah))
+                        ath9k_hw_ani_read_counters(ah);
 
-                cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
-                ah->stats.ast_ani_cckerrs +=
-                        cckPhyErrCnt - aniState->cckPhyErrCount;
-                aniState->cckPhyErrCount = cckPhyErrCnt;
-
-                /*
-                 * NB: figure out which counter triggered.  If both
-                 * trigger we'll only deal with one as the processing
-                 * clobbers the error counter so the trigger threshold
-                 * check will never be true.
-                 */
-                if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
-                        ath9k_hw_ani_ofdm_err_trigger_new(ah);
-                if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
-                        ath9k_hw_ani_cck_err_trigger_old(ah);
                 /* NB: always restart to insure the h/w counters are reset */
-                ath9k_ani_restart_old(ah);
-        }
-}
-
-/*
- * Process a MIB interrupt.  We may potentially be invoked because
- * any of the MIB counters overflow/trigger so don't assume we're
- * here because a PHY error counter triggered.
- */
-static void ath9k_hw_proc_mib_event_new(struct ath_hw *ah)
-{
-        u32 phyCnt1, phyCnt2;
-
-        /* Reset these counters regardless */
-        REG_WRITE(ah, AR_FILT_OFDM, 0);
-        REG_WRITE(ah, AR_FILT_CCK, 0);
-        if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
-                REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
-
-        /* Clear the mib counters and save them in the stats */
-        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
-
-        if (!DO_ANI(ah)) {
-                /*
-                 * We must always clear the interrupt cause by
-                 * resetting the phy error regs.
-                 */
-                REG_WRITE(ah, AR_PHY_ERR_1, 0);
-                REG_WRITE(ah, AR_PHY_ERR_2, 0);
-                return;
+                ath9k_ani_restart(ah);
         }
-
-        /* NB: these are not reset-on-read */
-        phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
-        phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
-
-        /* NB: always restart to insure the h/w counters are reset */
-        if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
-            ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK))
-                ath9k_ani_restart_new(ah);
 }
+EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
 
 void ath9k_hw_ani_setup(struct ath_hw *ah)
 {
         int i;
 
-        const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
-        const int coarseHigh[] = { -14, -14, -14, -14, -12 };
-        const int coarseLow[] = { -64, -64, -64, -64, -70 };
-        const int firpwr[] = { -78, -78, -78, -78, -80 };
+        static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
+        static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
+        static const int coarseLow[] = { -64, -64, -64, -64, -70 };
+        static const int firpwr[] = { -78, -78, -78, -78, -80 };
 
         for (i = 0; i < 5; i++) {
                 ah->totalSizeDesired[i] = totalSizeDesired[i];
@@ -1203,69 +845,60 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         int i;
 
-        ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
+        ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");
 
-        memset(ah->ani, 0, sizeof(ah->ani));
-        for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
-                if (AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani) {
-                        ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
-                        ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
+        if (use_new_ani(ah)) {
+                ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
+                ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
 
-                        ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
-                        ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW_NEW;
+                ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
+                ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
+        } else {
+                ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
+                ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
 
-                        ah->ani[i].spurImmunityLevel =
-                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
+                ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
+                ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
+        }
 
-                        ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
+        for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
+                struct ath9k_channel *chan = &ah->channels[i];
+                struct ar5416AniState *ani = &chan->ani;
 
-                        ah->ani[i].ofdmPhyErrBase = 0;
-                        ah->ani[i].cckPhyErrBase = 0;
+                if (use_new_ani(ah)) {
+                        ani->spurImmunityLevel =
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
+
+                        ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
 
                         if (AR_SREV_9300_20_OR_LATER(ah))
-                                ah->ani[i].mrcCCKOff =
+                                ani->mrcCCKOff =
                                         !ATH9K_ANI_ENABLE_MRC_CCK;
                         else
-                                ah->ani[i].mrcCCKOff = true;
+                                ani->mrcCCKOff = true;
 
-                        ah->ani[i].ofdmsTurn = true;
+                        ani->ofdmsTurn = true;
                 } else {
-                        ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
-                        ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
-
-                        ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
-                        ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW_OLD;
-
-                        ah->ani[i].spurImmunityLevel =
+                        ani->spurImmunityLevel =
                                 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
-                        ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
+                        ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
 
-                        ah->ani[i].ofdmPhyErrBase =
-                                AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
-                        ah->ani[i].cckPhyErrBase =
-                                AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH_OLD;
-                        ah->ani[i].cckWeakSigThreshold =
+                        ani->cckWeakSigThreshold =
                                 ATH9K_ANI_CCK_WEAK_SIG_THR;
                 }
 
-                ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
-                ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
-                ah->ani[i].ofdmWeakSigDetectOff =
+                ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
+                ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
+                ani->ofdmWeakSigDetectOff =
                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
-                ah->ani[i].cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
+                ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
         }
 
         /*
          * since we expect some ongoing maintenance on the tables, let's sanity
          * check here default level should not modify INI setting.
          */
-        if (AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani) {
-                const struct ani_ofdm_level_entry *entry_ofdm;
-                const struct ani_cck_level_entry *entry_cck;
-
-                entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL];
-                entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL];
-
+        if (use_new_ani(ah)) {
                 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
                 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
         } else {
@@ -1273,50 +906,9 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
                 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Setting OfdmErrBase = 0x%08x\n",
-                  ah->ani[0].ofdmPhyErrBase);
-        ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
-                  ah->ani[0].cckPhyErrBase);
-
-        ENABLE_REGWRITE_BUFFER(ah);
-
-        REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
-
-        REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
-
-        ath9k_enable_mib_counters(ah);
-
         if (ah->config.enable_ani)
                 ah->proc_phyerr |= HAL_PROCESS_ANI;
-}
-
-void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
-
-        priv_ops->ani_reset = ath9k_ani_reset_old;
-        priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_old;
-
-        ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_old;
-        ops->ani_monitor = ath9k_hw_ani_monitor_old;
-
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v1\n");
-}
-
-void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 
-        priv_ops->ani_reset = ath9k_ani_reset_new;
-        priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_new;
-
-        ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_new;
-        ops->ani_monitor = ath9k_hw_ani_monitor_new;
-
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v2\n");
+        ath9k_ani_restart(ah);
+        ath9k_enable_mib_counters(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
index f4d0a4d48b37..dbab5b9ce494 100644
--- a/drivers/net/wireless/ath/ath9k/ani.h
+++ b/drivers/net/wireless/ath/ath9k/ani.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,7 +19,7 @@
 
 #define HAL_PROCESS_ANI           0x00000001
 
-#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI))
+#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI) && ah->curchan)
 
 #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
 
@@ -123,20 +123,11 @@ struct ar5416AniState {
         u8 ofdmWeakSigDetectOff;
         u8 cckWeakSigThreshold;
         u32 listenTime;
-        u32 ofdmTrigHigh;
-        u32 ofdmTrigLow;
-        int32_t cckTrigHigh;
-        int32_t cckTrigLow;
         int32_t rssiThrLow;
         int32_t rssiThrHigh;
         u32 noiseFloor;
-        u32 txFrameCount;
-        u32 rxFrameCount;
-        u32 cycleCount;
         u32 ofdmPhyErrCount;
         u32 cckPhyErrCount;
-        u32 ofdmPhyErrBase;
-        u32 cckPhyErrBase;
         int16_t pktRssi[2];
         int16_t ofdmErrRssi[2];
         int16_t cckErrRssi[2];
@@ -166,8 +157,6 @@ struct ar5416Stats {
 
 void ath9k_enable_mib_counters(struct ath_hw *ah);
 void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
-u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
-                                  u32 *rxf_pcnt, u32 *txf_pcnt);
 void ath9k_hw_ani_setup(struct ath_hw *ah);
 void ath9k_hw_ani_init(struct ath_hw *ah);
 int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
index 36f7d0639db3..234617c948a1 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 3d2c8679bc85..441bb33f17ad 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -44,6 +44,34 @@ static const int m1ThreshExt_off = 127;
 static const int m2ThreshExt_off = 127;
 
 
+static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
+                                 int col)
+{
+        int i;
+
+        for (i = 0; i < array->ia_rows; i++)
+                bank[i] = INI_RA(array, i, col);
+}
+
+
+#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
+        ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
+
+static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                                  u32 *data, unsigned int *writecnt)
+{
+        int r;
+
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        for (r = 0; r < array->ia_rows; r++) {
+                REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
+                DO_DELAY(*writecnt);
+        }
+
+        REGWRITE_BUFFER_FLUSH(ah);
+}
+
 /**
  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  * @rfbuf:
@@ -118,7 +146,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
         if (!AR_SREV_5416(ah) || synth_freq >= 3000)
                 return;
 
-        BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
+        BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 
         if (synth_freq < 2412)
                 new_bias = 0;
@@ -130,9 +158,8 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
         /* pre-reverse this field */
         tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Force rf_pwd_icsyndiv to %1d on %4d\n",
-                  new_bias, synth_freq);
+        ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
+                new_bias, synth_freq);
 
         /* swizzle rf_pwd_icsyndiv */
         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
@@ -143,7 +170,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
 
 /**
  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
- * @ah: atheros hardware stucture
+ * @ah: atheros hardware structure
  * @chan:
  *
  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
@@ -173,8 +200,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                         channelSel = ((freq - 704) * 2 - 3040) / 10;
                         bModeSynth = 1;
                 } else {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Invalid channel %u MHz\n", freq);
+                        ath_err(common, "Invalid channel %u MHz\n", freq);
                         return -EINVAL;
                 }
 
@@ -206,8 +232,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
         } else {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Invalid channel %u MHz\n", freq);
+                ath_err(common, "Invalid channel %u MHz\n", freq);
                 return -EINVAL;
         }
 
@@ -244,13 +269,15 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
         int upper, lower, cur_vit_mask;
         int tmp, new;
         int i;
-        int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                          AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+        static int pilot_mask_reg[4] = {
+                AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
         };
-        int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                         AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+        static int chan_mask_reg[4] = {
+                AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
         };
-        int inc[4] = { 0, 100, 0, 0 };
+        static int inc[4] = { 0, 100, 0, 0 };
 
         int8_t mask_m[123];
         int8_t mask_p[123];
@@ -446,15 +473,14 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 #define ATH_ALLOC_BANK(bank, size) do { \
                 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
                 if (!bank) { \
-                        ath_print(common, ATH_DBG_FATAL, \
-                                  "Cannot allocate RF banks\n"); \
+                        ath_err(common, "Cannot allocate RF banks\n"); \
                         return -ENOMEM; \
                 } \
         } while (0);
 
         struct ath_common *common = ath9k_hw_common(ah);
 
-        BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
+        BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 
         ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
         ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
@@ -484,7 +510,7 @@ static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
                 bank = NULL; \
         } while (0);
 
-        BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
+        BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 
         ATH_FREE_BANK(ah->analogBank0Data);
         ATH_FREE_BANK(ah->analogBank1Data);
@@ -525,23 +551,23 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
          * for single chip devices, that is AR9280 or anything
          * after that.
          */
-        if (AR_SREV_9280_10_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah))
                 return true;
 
         /* Setup rf parameters */
         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 
         /* Setup Bank 0 Write */
-        RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
+        ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
 
         /* Setup Bank 1 Write */
-        RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
+        ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
 
         /* Setup Bank 2 Write */
-        RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
+        ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
 
         /* Setup Bank 6 Write */
-        RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
+        ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
                       modesIndex);
         {
                 int i;
@@ -571,7 +597,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
         }
 
         /* Setup Bank 7 Setup */
-        RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
+        ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
 
         /* Write Analog registers */
         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
@@ -613,14 +639,11 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
         rx_chainmask = ah->rxchainmask;
         tx_chainmask = ah->txchainmask;
 
-        ENABLE_REGWRITE_BUFFER(ah);
 
         switch (rx_chainmask) {
         case 0x5:
-                DISABLE_REGWRITE_BUFFER(ah);
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                             AR_PHY_SWAP_ALT_CHAIN);
-                ENABLE_REGWRITE_BUFFER(ah);
         case 0x3:
                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -630,17 +653,18 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
         case 0x1:
         case 0x2:
         case 0x7:
+                ENABLE_REGWRITE_BUFFER(ah);
                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
                 break;
         default:
+                ENABLE_REGWRITE_BUFFER(ah);
                 break;
         }
 
         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (tx_chainmask == 0x5) {
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
@@ -663,20 +687,20 @@ static void ar5008_hw_override_ini(struct ath_hw *ah,
          */
         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
 
                 if (!AR_SREV_9271(ah))
                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
 
-                if (AR_SREV_9287_10_OR_LATER(ah))
+                if (AR_SREV_9287_11_OR_LATER(ah))
                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
 
                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
         }
 
         if (!AR_SREV_5416_20_OR_LATER(ah) ||
-            AR_SREV_9280_10_OR_LATER(ah))
+            AR_SREV_9280_20_OR_LATER(ah))
                 return;
         /*
          * Disable BB clock gating
@@ -701,7 +725,7 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
         u32 phymode;
         u32 enableDacFifo = 0;
 
-        if (AR_SREV_9285_10_OR_LATER(ah))
+        if (AR_SREV_9285_12_OR_LATER(ah))
                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
                                          AR_PHY_FC_ENABLE_DAC_FIFO);
 
@@ -726,7 +750,6 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 
@@ -734,6 +757,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                                  struct ath9k_channel *chan)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+        struct ath_common *common = ath9k_hw_common(ah);
         int i, regWrites = 0;
         struct ieee80211_channel *channel = chan->chan;
         u32 modesIndex, freqIndex;
@@ -810,7 +834,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                 REG_WRITE(ah, reg, val);
 
                 if (reg >= 0x7800 && reg < 0x78a0
-                    && ah->config.analog_shiftreg) {
+                    && ah->config.analog_shiftreg
+                    && (common->bus_ops->ath_bus_type != ATH_USB)) {
                         udelay(100);
                 }
 
@@ -818,13 +843,12 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
-        if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
+        if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
 
         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
-            AR_SREV_9287_10_OR_LATER(ah))
+            AR_SREV_9287_11_OR_LATER(ah))
                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 
         if (AR_SREV_9271_10(ah))
@@ -841,7 +865,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                 REG_WRITE(ah, reg, val);
 
                 if (reg >= 0x7800 && reg < 0x78a0
-                    && ah->config.analog_shiftreg) {
+                    && ah->config.analog_shiftreg
+                    && (common->bus_ops->ath_bus_type != ATH_USB)) {
                         udelay(100);
                 }
 
@@ -849,7 +874,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (AR_SREV_9271(ah)) {
                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
@@ -878,12 +902,11 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), false);
 
         /* Write analog registers */
         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "ar5416SetRfRegs failed\n");
+                ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
                 return -EIO;
         }
 
@@ -900,7 +923,7 @@ static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 
-        if (!AR_SREV_9280_10_OR_LATER(ah))
+        if (!AR_SREV_9280_20_OR_LATER(ah))
                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 
@@ -969,18 +992,6 @@ static void ar5008_hw_rfbus_done(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
-{
-        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-
-        REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                    AR_GPIO_INPUT_MUX2_RFSILENT);
-
-        ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-        REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar5008_restore_chainmask(struct ath_hw *ah)
 {
         int rx_chainmask = ah->rxchainmask;
@@ -1053,7 +1064,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                                       enum ath9k_ani_cmd cmd,
                                       int param)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath_common *common = ath9k_hw_common(ah);
 
         switch (cmd & ah->ani_function) {
@@ -1061,10 +1072,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(ah->totalSizeDesired));
                         return false;
                 }
 
@@ -1089,12 +1099,12 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
-                const int m1ThreshLow[] = { 127, 50 };
-                const int m2ThreshLow[] = { 127, 40 };
-                const int m1Thresh[] = { 127, 0x4d };
-                const int m2Thresh[] = { 127, 0x40 };
-                const int m2CountThr[] = { 31, 16 };
-                const int m2CountThrLow[] = { 63, 48 };
+                static const int m1ThreshLow[] = { 127, 50 };
+                static const int m2ThreshLow[] = { 127, 40 };
+                static const int m1Thresh[] = { 127, 0x4d };
+                static const int m2Thresh[] = { 127, 0x40 };
+                static const int m2CountThr[] = { 31, 16 };
+                static const int m2CountThrLow[] = { 63, 48 };
                 u32 on = param ? 1 : 0;
 
                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
@@ -1146,7 +1156,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
-                const int weakSigThrCck[] = { 8, 6 };
+                static const int weakSigThrCck[] = { 8, 6 };
                 u32 high = param ? 1 : 0;
 
                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
@@ -1162,14 +1172,13 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_FIRSTEP_LEVEL:{
-                const int firstep[] = { 0, 4, 8 };
+                static const int firstep[] = { 0, 4, 8 };
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep));
                         return false;
                 }
                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -1183,14 +1192,13 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
-                const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
+                static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1));
                         return false;
                 }
                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -1206,27 +1214,23 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
-        ath_print(common, ATH_DBG_ANI,
-                  "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
-                  "ofdmWeakSigDetectOff=%d\n",
-                  aniState->noiseImmunityLevel,
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff);
-        ath_print(common, ATH_DBG_ANI,
-                  "cckWeakSigThreshold=%d, "
-                  "firstepLevel=%d, listenTime=%d\n",
-                  aniState->cckWeakSigThreshold,
-                  aniState->firstepLevel,
-                  aniState->listenTime);
-        ath_print(common, ATH_DBG_ANI,
-                "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
-                aniState->cycleCount,
+        ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
+        ath_dbg(common, ATH_DBG_ANI,
+                "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
+                aniState->noiseImmunityLevel,
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff);
+        ath_dbg(common, ATH_DBG_ANI,
+                "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
+                aniState->cckWeakSigThreshold,
+                aniState->firstepLevel,
+                aniState->listenTime);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
                 aniState->ofdmPhyErrCount,
                 aniState->cckPhyErrCount);
 
@@ -1237,9 +1241,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                                       enum ath9k_ani_cmd cmd,
                                       int param)
 {
-        struct ar5416AniState *aniState = ah->curani;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
+        struct ar5416AniState *aniState = &chan->ani;
         s32 value, value2;
 
         switch (cmd & ah->ani_function) {
@@ -1310,12 +1314,12 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                 if (!on != aniState->ofdmWeakSigDetectOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: ofdm weak signal: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->ofdmWeakSigDetectOff ?
-                                        "on" : "off",
-                                  on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: ofdm weak signal: %s=>%s\n",
+                                chan->channel,
+                                !aniState->ofdmWeakSigDetectOff ?
+                                "on" : "off",
+                                on ? "on" : "off");
                         if (on)
                                 ah->stats.ast_ani_ofdmon++;
                         else
@@ -1328,11 +1332,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_FIRSTEP_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep_table));
                         return false;
                 }
 
@@ -1367,24 +1369,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                               AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
 
                 if (level != aniState->firstepLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.firstep);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep_low[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.firstepLow);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value,
+                                aniState->iniDef.firstep);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value2,
+                                aniState->iniDef.firstepLow);
                         if (level > aniState->firstepLevel)
                                 ah->stats.ast_ani_stepup++;
                         else if (level < aniState->firstepLevel)
@@ -1397,11 +1397,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1_table));
                         return false;
                 }
                 /*
@@ -1435,24 +1433,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                               AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
 
                 if (level != aniState->spurImmunityLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.cycpwrThr1);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1Ext[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.cycpwrThr1Ext);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value,
+                                aniState->iniDef.cycpwrThr1);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value2,
+                                aniState->iniDef.cycpwrThr1Ext);
                         if (level > aniState->spurImmunityLevel)
                                 ah->stats.ast_ani_spurup++;
                         else if (level < aniState->spurImmunityLevel)
@@ -1471,24 +1467,19 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                  "MRCcck=%s listenTime=%d CC=%d listen=%d "
-                  "ofdmErrs=%d cckErrs=%d\n",
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
-                  aniState->firstepLevel,
-                  !aniState->mrcCCKOff ? "on" : "off",
-                  aniState->listenTime,
-                  aniState->cycleCount,
-                  aniState->listenTime,
-                  aniState->ofdmPhyErrCount,
-                  aniState->cckPhyErrCount);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+                aniState->firstepLevel,
+                !aniState->mrcCCKOff ? "on" : "off",
+                aniState->listenTime,
+                aniState->ofdmPhyErrCount,
+                aniState->cckPhyErrCount);
         return true;
 }
 
@@ -1498,25 +1489,25 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
-        nfarray[2] = sign_extend(nf, 9);
+        nfarray[2] = sign_extend32(nf, 8);
 
         if (!IS_CHAN_HT40(ah->curchan))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-        nfarray[3] = sign_extend(nf, 9);
+        nfarray[3] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
-        nfarray[4] = sign_extend(nf, 9);
+        nfarray[4] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
-        nfarray[5] = sign_extend(nf, 9);
+        nfarray[5] = sign_extend32(nf, 8);
 }
 
 /*
@@ -1526,25 +1517,20 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
  */
 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
 {
-        struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
+        struct ar5416AniState *aniState = &chan->ani;
         struct ath9k_ani_default *iniDef;
-        int index;
         u32 val;
 
-        index = ath9k_hw_get_ani_channel_idx(ah, chan);
-        aniState = &ah->ani[index];
-        ah->curani = aniState;
         iniDef = &aniState->iniDef;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
-                  ah->hw_version.macVersion,
-                  ah->hw_version.macRev,
-                  ah->opmode,
-                  chan->channel,
-                  chan->channelFlags);
+        ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+                ah->hw_version.macVersion,
+                ah->hw_version.macRev,
+                ah->opmode,
+                chan->channel,
+                chan->channelFlags);
 
         val = REG_READ(ah, AR_PHY_SFCORR);
         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1579,8 +1565,6 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
         aniState->mrcCCKOff = true; /* not available on pre AR9003 */
-
-        aniState->cycleCount = 0;
 }
 
 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
@@ -1593,10 +1577,55 @@ static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
 }
 
+static void ar5008_hw_set_radar_params(struct ath_hw *ah,
+                                       struct ath_hw_radar_conf *conf)
+{
+        u32 radar_0 = 0, radar_1 = 0;
+
+        if (!conf) {
+                REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+                return;
+        }
+
+        radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+        radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+        radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+        radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+        radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+        radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+        radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+        radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+        radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+        radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+        radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+        REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+        REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+        if (conf->ext_channel)
+                REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+        else
+                REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
+{
+        struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+        conf->fir_power = -33;
+        conf->radar_rssi = 20;
+        conf->pulse_height = 10;
+        conf->pulse_rssi = 24;
+        conf->pulse_inband = 15;
+        conf->pulse_maxlen = 255;
+        conf->pulse_inband_step = 12;
+        conf->radar_inband = 8;
+}
+
 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        const u32 ar5416_cca_regs[6] = {
+        static const u32 ar5416_cca_regs[6] = {
                 AR_PHY_CCA,
                 AR_PHY_CH1_CCA,
                 AR_PHY_CH2_CCA,
@@ -1619,10 +1648,10 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
         priv_ops->rfbus_req = ar5008_hw_rfbus_req;
         priv_ops->rfbus_done = ar5008_hw_rfbus_done;
-        priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
         priv_ops->restore_chainmask = ar5008_restore_chainmask;
         priv_ops->set_diversity = ar5008_set_diversity;
         priv_ops->do_getnf = ar5008_hw_do_getnf;
+        priv_ops->set_radar_params = ar5008_hw_set_radar_params;
 
         if (modparam_force_new_ani) {
                 priv_ops->ani_control = ar5008_hw_ani_control_new;
@@ -1638,5 +1667,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
                 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
 
         ar5008_hw_set_nf_limits(ah);
+        ar5008_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
index 69a94c7e45cb..6d2e2f3303f9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index fe7418aefc4a..2d4c0910295b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,6 +20,34 @@
 
 #define AR9285_CLCAL_REDO_THRESH    1
 
+enum ar9002_cal_types {
+        ADC_GAIN_CAL = BIT(0),
+        ADC_DC_CAL = BIT(1),
+        IQ_MISMATCH_CAL = BIT(2),
+};
+
+static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                enum ar9002_cal_types cal_type)
+{
+        bool supported = false;
+        switch (ah->supp_cals & cal_type) {
+        case IQ_MISMATCH_CAL:
+                /* Run IQ Mismatch for non-CCK only */
+                if (!IS_CHAN_B(chan))
+                        supported = true;
+                break;
+        case ADC_GAIN_CAL:
+        case ADC_DC_CAL:
+                /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
+                if (!IS_CHAN_B(chan) &&
+                    !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
+                        supported = true;
+                break;
+        }
+        return supported;
+}
+
 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
                                         struct ath9k_cal_list *currCal)
 {
@@ -32,26 +60,19 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah,
         switch (currCal->calData->calType) {
         case IQ_MISMATCH_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting IQ Mismatch Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting IQ Mismatch Calibration\n");
                 break;
         case ADC_GAIN_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting ADC Gain Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting ADC Gain Calibration\n");
                 break;
         case ADC_DC_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting ADC DC Calibration\n");
-                break;
-        case ADC_DC_INIT_CAL:
-                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting Init ADC DC Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting ADC DC Calibration\n");
                 break;
-        case TEMP_COMP_CAL:
-                break; /* Not supported */
         }
 
         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
@@ -96,25 +117,6 @@ static bool ar9002_hw_per_calibration(struct ath_hw *ah,
         return iscaldone;
 }
 
-/* Assumes you are talking about the currently configured channel */
-static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
-                                      enum ath9k_cal_types calType)
-{
-        struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
-
-        switch (calType & ah->supp_cals) {
-        case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
-                return true;
-        case ADC_GAIN_CAL:
-        case ADC_DC_CAL:
-                if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
-                      conf_is_ht20(conf)))
-                        return true;
-                break;
-        }
-        return false;
-}
-
 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
 {
         int i;
@@ -126,11 +128,11 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
                 ah->totalIqCorrMeas[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
-                          ah->cal_samples, i, ah->totalPowerMeasI[i],
-                          ah->totalPowerMeasQ[i],
-                          ah->totalIqCorrMeas[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+                        ah->cal_samples, i, ah->totalPowerMeasI[i],
+                        ah->totalPowerMeasQ[i],
+                        ah->totalIqCorrMeas[i]);
         }
 }
 
@@ -148,14 +150,13 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
                 ah->totalAdcQEvenPhase[i] +=
                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
-                          "oddq=0x%08x; evenq=0x%08x;\n",
-                          ah->cal_samples, i,
-                          ah->totalAdcIOddPhase[i],
-                          ah->totalAdcIEvenPhase[i],
-                          ah->totalAdcQOddPhase[i],
-                          ah->totalAdcQEvenPhase[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+                        ah->cal_samples, i,
+                        ah->totalAdcIOddPhase[i],
+                        ah->totalAdcIEvenPhase[i],
+                        ah->totalAdcQOddPhase[i],
+                        ah->totalAdcQEvenPhase[i]);
         }
 }
 
@@ -173,14 +174,13 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
                 ah->totalAdcDcOffsetQEvenPhase[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
-                          "oddq=0x%08x; evenq=0x%08x;\n",
-                          ah->cal_samples, i,
-                          ah->totalAdcDcOffsetIOddPhase[i],
-                          ah->totalAdcDcOffsetIEvenPhase[i],
-                          ah->totalAdcDcOffsetQOddPhase[i],
-                          ah->totalAdcDcOffsetQEvenPhase[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+                        ah->cal_samples, i,
+                        ah->totalAdcDcOffsetIOddPhase[i],
+                        ah->totalAdcDcOffsetIEvenPhase[i],
+                        ah->totalAdcDcOffsetQOddPhase[i],
+                        ah->totalAdcDcOffsetQEvenPhase[i]);
         }
 }
 
@@ -197,13 +197,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 powerMeasQ = ah->totalPowerMeasQ[i];
                 iqCorrMeas = ah->totalIqCorrMeas[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting IQ Cal and Correction for Chain %d\n",
-                          i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting IQ Cal and Correction for Chain %d\n",
+                        i);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
-                          i, ah->totalIqCorrMeas[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
 
@@ -212,12 +212,12 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iqCorrNeg = 1;
                 }
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-                ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
-                          iqCorrNeg);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
+                ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+                        iqCorrNeg);
 
                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
                 qCoffDenom = powerMeasQ / 64;
@@ -226,14 +226,14 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                     (qCoffDenom != 0)) {
                         iCoff = iqCorrMeas / iCoffDenom;
                         qCoff = powerMeasI / qCoffDenom - 64;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                         iCoff = iCoff & 0x3f;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
                         if (iqCorrNeg == 0x0)
                                 iCoff = 0x40 - iCoff;
 
@@ -242,9 +242,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         else if (qCoff <= -16)
                                 qCoff = -16;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                  i, iCoff, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
+                                i, iCoff, qCoff);
 
                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -252,9 +252,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
                                       qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ Cal and Correction done for Chain %d\n",
-                                  i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "IQ Cal and Correction done for Chain %d\n",
+                                i);
                 }
         }
 
@@ -274,21 +274,21 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                 qOddMeasOffset = ah->totalAdcQOddPhase[i];
                 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting ADC Gain Cal for Chain %d\n", i);
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
-                          iOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
-                          iEvenMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
-                          qOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
-                          qEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting ADC Gain Cal for Chain %d\n", i);
+
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
+                        iOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_i = 0x%08x\n", i,
+                        iEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
+                        qOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_q = 0x%08x\n", i,
+                        qEvenMeasOffset);
 
                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
                         iGainMismatch =
@@ -298,20 +298,20 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                                 ((qOddMeasOffset * 32) /
                                  qEvenMeasOffset) & 0x3f;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
-                                  iGainMismatch);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
-                                  qGainMismatch);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d gain_mismatch_i = 0x%08x\n", i,
+                                iGainMismatch);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d gain_mismatch_q = 0x%08x\n", i,
+                                qGainMismatch);
 
                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
                         val &= 0xfffff000;
                         val |= (qGainMismatch) | (iGainMismatch << 6);
                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "ADC Gain Cal done for Chain %d\n", i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "ADC Gain Cal done for Chain %d\n", i);
                 }
         }
 
@@ -336,41 +336,41 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
                 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
                 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                           "Starting ADC DC Offset Cal for Chain %d\n", i);
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_i = %d\n", i,
-                          iOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_i = %d\n", i,
-                          iEvenMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_q = %d\n", i,
-                          qOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_q = %d\n", i,
-                          qEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting ADC DC Offset Cal for Chain %d\n", i);
+
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_i = %d\n", i,
+                        iOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_i = %d\n", i,
+                        iEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_q = %d\n", i,
+                        qOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_q = %d\n", i,
+                        qEvenMeasOffset);
 
                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
                                numSamples) & 0x1ff;
                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
                                numSamples) & 0x1ff;
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
-                          iDcMismatch);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
-                          qDcMismatch);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
+                        iDcMismatch);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
+                        qDcMismatch);
 
                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
                 val &= 0xc0000fff;
                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "ADC DC Offset Cal done for Chain %d\n", i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "ADC DC Offset Cal done for Chain %d\n", i);
         }
 
         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -541,7 +541,6 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
@@ -560,18 +559,13 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 { 0x7838, 0 },
         };
 
-        ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
 
         /* PA CAL is not needed for high power solution */
         if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
             AR5416_EEP_TXGAIN_HIGH_POWER)
                 return;
 
-        if (AR_SREV_9285_11(ah)) {
-                REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
-                udelay(10);
-        }
-
         for (i = 0; i < ARRAY_SIZE(regList); i++)
                 regList[i][1] = REG_READ(ah, regList[i][0]);
 
@@ -651,10 +645,6 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 
         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
-
-        if (AR_SREV_9285_11(ah))
-                REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
-
 }
 
 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
@@ -664,7 +654,7 @@ static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                         ar9271_hw_pa_cal(ah, is_reset);
                 else
                         ah->pacal_info.skipcount--;
-        } else if (AR_SREV_9285_11_OR_LATER(ah)) {
+        } else if (AR_SREV_9285_12_OR_LATER(ah)) {
                 if (is_reset || !ah->pacal_info.skipcount)
                         ar9285_hw_pa_cal(ah, is_reset);
                 else
@@ -710,10 +700,6 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,
 
         /* Do NF cal only at longer intervals */
         if (longcal || nfcal_pending) {
-                /* Do periodic PAOffset Cal */
-                ar9002_hw_pa_cal(ah, false);
-                ar9002_hw_olc_temp_compensation(ah);
-
                 /*
                  * Get the value from the previous NF cal and update
                  * history buffer.
@@ -728,8 +714,12 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,
                         ath9k_hw_loadnf(ah, ah->curchan);
                 }
 
-                if (longcal)
+                if (longcal) {
                         ath9k_hw_start_nfcal(ah, false);
+                        /* Do periodic PAOffset Cal */
+                        ar9002_hw_pa_cal(ah, false);
+                        ar9002_hw_olc_temp_compensation(ah);
+                }
         }
 
         return iscaldone;
@@ -750,9 +740,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                   AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
-                        ath_print(common, ATH_DBG_CALIBRATE, "offset "
-                                  "calibration failed to complete in "
-                                  "1ms; noisy ??\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "offset calibration failed to complete in 1ms; noisy environment?\n");
                         return false;
                 }
                 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -765,8 +754,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                           0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
-                          "failed to complete in 1ms; noisy ??\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "offset calibration failed to complete in 1ms; noisy environment?\n");
                 return false;
         }
 
@@ -837,12 +826,15 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
+        if (AR_SREV_9271(ah)) {
+                if (!ar9285_hw_cl_cal(ah, chan))
+                        return false;
+        } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
                 if (!ar9285_hw_clc(ah, chan))
                         return false;
         } else {
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
-                        if (!AR_SREV_9287_10_OR_LATER(ah))
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        if (!AR_SREV_9287_11_OR_LATER(ah))
                                 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
                                             AR_PHY_ADC_CTL_OFF_PWDADC);
                         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
@@ -858,14 +850,13 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                    AR_PHY_AGC_CONTROL_CAL,
                                    0, AH_WAIT_TIMEOUT)) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "offset calibration failed to "
-                                  "complete in 1ms; noisy environment?\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "offset calibration failed to complete in 1ms; noisy environment?\n");
                         return false;
                 }
 
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
-                        if (!AR_SREV_9287_10_OR_LATER(ah))
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        if (!AR_SREV_9287_11_OR_LATER(ah))
                                 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
                                             AR_PHY_ADC_CTL_OFF_PWDADC);
                         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
@@ -886,23 +877,33 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 
         /* Enable IQ, ADC Gain and ADC DC offset CALs */
         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
-                if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
+                ah->supp_cals = IQ_MISMATCH_CAL;
+
+                if (AR_SREV_9160_10_OR_LATER(ah))
+                        ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
+
+                if (AR_SREV_9287(ah))
+                        ah->supp_cals &= ~ADC_GAIN_CAL;
+
+                if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
                         INIT_CAL(&ah->adcgain_caldata);
                         INSERT_CAL(ah, &ah->adcgain_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling ADC Gain Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "enabling ADC Gain Calibration.\n");
                 }
-                if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
+
+                if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
                         INIT_CAL(&ah->adcdc_caldata);
                         INSERT_CAL(ah, &ah->adcdc_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling ADC DC Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "enabling ADC DC Calibration.\n");
                 }
-                if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
+
+                if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
                         INIT_CAL(&ah->iq_caldata);
                         INSERT_CAL(ah, &ah->iq_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling IQ Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "enabling IQ Calibration.\n");
                 }
 
                 ah->cal_list_curr = ah->cal_list;
@@ -959,13 +960,6 @@ static const struct ath9k_percal_data adc_dc_cal_single_sample = {
         ar9002_hw_adc_dccal_collect,
         ar9002_hw_adc_dccal_calibrate
 };
-static const struct ath9k_percal_data adc_init_dc_cal = {
-        ADC_DC_INIT_CAL,
-        MIN_CAL_SAMPLES,
-        INIT_LOG_COUNT,
-        ar9002_hw_adc_dccal_collect,
-        ar9002_hw_adc_dccal_calibrate
-};
 
 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
 {
@@ -976,24 +970,23 @@ static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
         }
 
         if (AR_SREV_9160_10_OR_LATER(ah)) {
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
                         ah->iq_caldata.calData = &iq_cal_single_sample;
                         ah->adcgain_caldata.calData =
                                 &adc_gain_cal_single_sample;
                         ah->adcdc_caldata.calData =
                                 &adc_dc_cal_single_sample;
-                        ah->adcdc_calinitdata.calData =
-                                &adc_init_dc_cal;
                 } else {
                         ah->iq_caldata.calData = &iq_cal_multi_sample;
                         ah->adcgain_caldata.calData =
                                 &adc_gain_cal_multi_sample;
                         ah->adcdc_caldata.calData =
                                 &adc_dc_cal_multi_sample;
-                        ah->adcdc_calinitdata.calData =
-                                &adc_init_dc_cal;
                 }
                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
+
+                if (AR_SREV_9287(ah))
+                        ah->supp_cals &= ~ADC_GAIN_CAL;
         }
 }
 
@@ -1005,7 +998,6 @@ void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
         priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
         priv_ops->init_cal = ar9002_hw_init_cal;
         priv_ops->setup_calibration = ar9002_hw_setup_calibration;
-        priv_ops->iscal_supported = ar9002_hw_iscal_supported;
 
         ops->calibrate = ar9002_hw_calibrate;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 303c63da5ea3..f344cc2b3d59 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -22,28 +22,10 @@
 
 int modparam_force_new_ani;
 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
-MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
+MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
 
 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
 
-static bool ar9002_hw_macversion_supported(u32 macversion)
-{
-        switch (macversion) {
-        case AR_SREV_VERSION_5416_PCI:
-        case AR_SREV_VERSION_5416_PCIE:
-        case AR_SREV_VERSION_9160:
-        case AR_SREV_VERSION_9100:
-        case AR_SREV_VERSION_9280:
-        case AR_SREV_VERSION_9285:
-        case AR_SREV_VERSION_9287:
-        case AR_SREV_VERSION_9271:
-                return true;
-        default:
-                break;
-        }
-        return false;
-}
-
 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 {
         if (AR_SREV_9271(ah)) {
@@ -371,7 +353,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
                         REGWRITE_BUFFER_FLUSH(ah);
-                        DISABLE_REGWRITE_BUFFER(ah);
                 }
 
                 udelay(1000);
@@ -411,6 +392,9 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
                 }
 
+                if (AR_SREV_9280(ah))
+                        val |= AR_WA_BIT22;
+
                 if (AR_SREV_9285E_20(ah))
                         val |= AR_WA_BIT23;
 
@@ -442,9 +426,8 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                 }
 
                 /* WAR for ASPM system hang */
-                if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
+                if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
-                }
 
                 if (AR_SREV_9285E_20(ah))
                         val |= AR_WA_BIT23;
@@ -468,7 +451,6 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah)
                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
@@ -493,9 +475,9 @@ int ar9002_hw_rf_claim(struct ath_hw *ah)
         case AR_RAD2122_SREV_MAJOR:
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Radio Chip Rev 0x%02X not supported\n",
-                          val & AR_RADIO_SREV_MAJOR);
+                ath_err(ath9k_hw_common(ah),
+                        "Radio Chip Rev 0x%02X not supported\n",
+                        val & AR_RADIO_SREV_MAJOR);
                 return -EOPNOTSUPP;
         }
 
@@ -564,19 +546,61 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
 
         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
-        priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 
         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 
         ar5008_hw_attach_phy_ops(ah);
-        if (AR_SREV_9280_10_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah))
                 ar9002_hw_attach_phy_ops(ah);
 
         ar9002_hw_attach_calib_ops(ah);
         ar9002_hw_attach_mac_ops(ah);
+}
 
-        if (modparam_force_new_ani)
-                ath9k_hw_attach_ani_ops_new(ah);
-        else
-                ath9k_hw_attach_ani_ops_old(ah);
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
+{
+        u32 modesIndex;
+        int i;
+
+        switch (chan->chanmode) {
+        case CHANNEL_A:
+        case CHANNEL_A_HT20:
+                modesIndex = 1;
+                break;
+        case CHANNEL_A_HT40PLUS:
+        case CHANNEL_A_HT40MINUS:
+                modesIndex = 2;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_G_HT20:
+        case CHANNEL_B:
+                modesIndex = 4;
+                break;
+        case CHANNEL_G_HT40PLUS:
+        case CHANNEL_G_HT40MINUS:
+                modesIndex = 3;
+                break;
+
+        default:
+                return;
+        }
+
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
+                u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
+                u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
+                u32 val_orig;
+
+                if (reg == AR_PHY_CCK_DETECT) {
+                        val_orig = REG_READ(ah, reg);
+                        val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
+                        val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
+
+                        REG_WRITE(ah, reg, val|val_orig);
+                } else
+                        REG_WRITE(ah, reg, val);
+        }
+
+        REGWRITE_BUFFER_FLUSH(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
index 6203eed860dd..7573257731b6 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index 50dda394f8be..077e8a6983fa 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -90,13 +90,10 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 
                 *masked = isr & ATH9K_INT_COMMON;
 
-                if (ah->config.rx_intr_mitigation) {
-                        if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
-                                *masked |= ATH9K_INT_RX;
-                }
-
-                if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+                if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
+                           AR_ISR_RXOK | AR_ISR_RXERR))
                         *masked |= ATH9K_INT_RX;
+
                 if (isr &
                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
                      AR_ISR_TXEOL)) {
@@ -114,16 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 }
 
                 if (isr & AR_ISR_RXORN) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "receive FIFO overrun interrupt\n");
-                }
-
-                if (!AR_SREV_9100(ah)) {
-                        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
-                                u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
-                                if (isr5 & AR_ISR_S5_TIM_TIMER)
-                                        *masked |= ATH9K_INT_TIM_TIMER;
-                        }
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "receive FIFO overrun interrupt\n");
                 }
 
                 *masked |= mask2;
@@ -136,17 +125,18 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 u32 s5_s;
 
                 s5_s = REG_READ(ah, AR_ISR_S5_S);
-                if (isr & AR_ISR_GENTMR) {
-                        ah->intr_gen_timer_trigger =
+                ah->intr_gen_timer_trigger =
                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
 
-                        ah->intr_gen_timer_thresh =
-                                MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
+                ah->intr_gen_timer_thresh =
+                        MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
 
-                        if (ah->intr_gen_timer_trigger)
-                                *masked |= ATH9K_INT_GENTIMER;
+                if (ah->intr_gen_timer_trigger)
+                        *masked |= ATH9K_INT_GENTIMER;
 
-                }
+                if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
+                    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+                        *masked |= ATH9K_INT_TIM_TIMER;
         }
 
         if (sync_cause) {
@@ -157,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 
                 if (fatal_int) {
                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
-                                ath_print(common, ATH_DBG_ANY,
-                                          "received PCI FATAL interrupt\n");
+                                ath_dbg(common, ATH_DBG_ANY,
+                                        "received PCI FATAL interrupt\n");
                         }
                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
-                                ath_print(common, ATH_DBG_ANY,
-                                          "received PCI PERR interrupt\n");
+                                ath_dbg(common, ATH_DBG_ANY,
+                                        "received PCI PERR interrupt\n");
                         }
                         *masked |= ATH9K_INT_FATAL;
                 }
                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
                         REG_WRITE(ah, AR_RC, 0);
                         *masked |= ATH9K_INT_FATAL;
                 }
                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
                 }
 
                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -218,77 +208,70 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                  struct ath_tx_status *ts)
 {
         struct ar5416_desc *ads = AR5416DESC(ds);
+        u32 status;
 
-        if ((ads->ds_txstatus9 & AR_TxDone) == 0)
+        status = ACCESS_ONCE(ads->ds_txstatus9);
+        if ((status & AR_TxDone) == 0)
                 return -EINPROGRESS;
 
-        ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
         ts->ts_tstamp = ads->AR_SendTimestamp;
         ts->ts_status = 0;
         ts->ts_flags = 0;
 
-        if (ads->ds_txstatus1 & AR_FrmXmitOK)
+        if (status & AR_TxOpExceeded)
+                ts->ts_status |= ATH9K_TXERR_XTXOP;
+        ts->tid = MS(status, AR_TxTid);
+        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
+        ts->ts_seqnum = MS(status, AR_SeqNum);
+
+        status = ACCESS_ONCE(ads->ds_txstatus0);
+        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
+        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
+        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
+        if (status & AR_TxBaStatus) {
+                ts->ts_flags |= ATH9K_TX_BA;
+                ts->ba_low = ads->AR_BaBitmapLow;
+                ts->ba_high = ads->AR_BaBitmapHigh;
+        }
+
+        status = ACCESS_ONCE(ads->ds_txstatus1);
+        if (status & AR_FrmXmitOK)
                 ts->ts_status |= ATH9K_TX_ACKED;
-        if (ads->ds_txstatus1 & AR_ExcessiveRetries)
-                ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->ds_txstatus1 & AR_Filtered)
-                ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
-                ts->ts_status |= ATH9K_TXERR_FIFO;
-                ath9k_hw_updatetxtriglevel(ah, true);
+        else {
+                if (status & AR_ExcessiveRetries)
+                        ts->ts_status |= ATH9K_TXERR_XRETRY;
+                if (status & AR_Filtered)
+                        ts->ts_status |= ATH9K_TXERR_FILT;
+                if (status & AR_FIFOUnderrun) {
+                        ts->ts_status |= ATH9K_TXERR_FIFO;
+                        ath9k_hw_updatetxtriglevel(ah, true);
+                }
         }
-        if (ads->ds_txstatus9 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->ds_txstatus1 & AR_TxTimerExpired)
+        if (status & AR_TxTimerExpired)
                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->ds_txstatus1 & AR_DescCfgErr)
+        if (status & AR_DescCfgErr)
                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
+        if (status & AR_TxDataUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
+        if (status & AR_TxDelimUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->ds_txstatus0 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->AR_BaBitmapLow;
-                ts->ba_high = ads->AR_BaBitmapHigh;
-        }
+        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
+        ts->ts_longretry = MS(status, AR_DataFailCnt);
+        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
-        ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
-        switch (ts->ts_rateindex) {
-        case 0:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
-                break;
-        case 1:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
-                break;
-        case 2:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
-                break;
-        case 3:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
-                break;
-        }
+        status = ACCESS_ONCE(ads->ds_txstatus5);
+        ts->ts_rssi = MS(status, AR_TxRSSICombined);
+        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
+        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
+        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
-        ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
         ts->evm0 = ads->AR_TxEVM0;
         ts->evm1 = ads->AR_TxEVM1;
         ts->evm2 = ads->AR_TxEVM2;
-        ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
-        ts->tid = MS(ads->ds_txstatus9, AR_TxTid);
-        ts->ts_antenna = 0;
 
         return 0;
 }
@@ -300,7 +283,6 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
 {
         struct ar5416_desc *ads = AR5416DESC(ds);
 
-        txPower += ah->txpower_indexoffset;
         if (txPower > 63)
                 txPower = 63;
 
@@ -308,7 +290,6 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
                 | SM(txPower, AR_XmitPower)
                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
-                | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
 
@@ -329,6 +310,16 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         }
 }
 
+static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
+{
+        struct ar5416_desc *ads = AR5416DESC(ds);
+
+        if (val)
+                ads->ds_ctl0 |= AR_ClrDestMask;
+        else
+                ads->ds_ctl0 &= ~AR_ClrDestMask;
+}
+
 static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
                                           void *lastds,
                                           u32 durUpdateEn, u32 rtsctsRate,
@@ -424,26 +415,6 @@ static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
 }
 
-static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
-                                           u32 burstDuration)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_ctl2 &= ~AR_BurstDur;
-        ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
-}
-
-static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
-                                            u32 vmf)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        if (vmf)
-                ads->ds_ctl0 |= AR_VirtMoreFrag;
-        else
-                ads->ds_ctl0 &= ~AR_VirtMoreFrag;
-}
-
 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
                           u32 size, u32 flags)
 {
@@ -476,6 +447,5 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
         ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
         ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
         ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
-        ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
-        ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
+        ops->set_clrdmask = ar9002_hw_set_clrdmask;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index adbf031fbc5a..2fe0a34cbabc 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -175,13 +175,15 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         int upper, lower, cur_vit_mask;
         int tmp, newVal;
         int i;
-        int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                          AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+        static const int pilot_mask_reg[4] = {
+                AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
         };
-        int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                         AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+        static const int chan_mask_reg[4] = {
+                AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
         };
-        int inc[4] = { 0, 100, 0, 0 };
+        static const int inc[4] = { 0, 100, 0, 0 };
         struct chan_centers centers;
 
         int8_t mask_m[123];
@@ -201,13 +203,14 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
 
+                if (AR_NO_SPUR == cur_bb_spur)
+                        break;
+
                 if (is2GHz)
                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
                 else
                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
 
-                if (AR_NO_SPUR == cur_bb_spur)
-                        break;
                 cur_bb_spur = cur_bb_spur - freq;
 
                 if (IS_CHAN_HT40(chan)) {
@@ -415,7 +418,6 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ar9002_olc_init(struct ath_hw *ah)
@@ -474,21 +476,21 @@ static void ar9002_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
         if (IS_CHAN_HT40(ah->curchan))
-                nfarray[3] = sign_extend(nf, 9);
+                nfarray[3] = sign_extend32(nf, 8);
 
         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
         if (IS_CHAN_HT40(ah->curchan))
-                nfarray[4] = sign_extend(nf, 9);
+                nfarray[4] = sign_extend32(nf, 8);
 }
 
 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
@@ -515,9 +517,45 @@ static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
         }
 }
 
+static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
+        antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
+                                  AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
+        antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
+                                 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
+        antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
+                                  AR_PHY_9285_FAST_DIV_BIAS_S;
+        antconf->lna1_lna2_delta = -3;
+        antconf->div_group = 0;
+}
+
+static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
+        regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
+                    AR_PHY_9285_ANT_DIV_ALT_LNACONF |
+                    AR_PHY_9285_FAST_DIV_BIAS);
+        regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
+                   & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
+        regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
+                   & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
+        regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
+                   & AR_PHY_9285_FAST_DIV_BIAS);
+
+        REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
+}
+
 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 
         priv_ops->set_rf_regs = NULL;
         priv_ops->rf_alloc_ext_banks = NULL;
@@ -528,5 +566,8 @@ void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
         priv_ops->do_getnf = ar9002_hw_do_getnf;
 
+        ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
+        ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
+
         ar9002_hw_set_nf_limits(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
index c5151a4dd10b..453af6dc514b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -302,6 +302,8 @@
 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
 
 #define AR_PHY_MULTICHAIN_GAIN_CTL          0x99ac
+#define AR_PHY_9285_FAST_DIV_BIAS           0x00007E00
+#define AR_PHY_9285_FAST_DIV_BIAS_S         9
 #define AR_PHY_9285_ANT_DIV_CTL_ALL         0x7f000000
 #define AR_PHY_9285_ANT_DIV_CTL             0x01000000
 #define AR_PHY_9285_ANT_DIV_CTL_S           24
@@ -481,7 +483,11 @@
 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN     0x01F80000
 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S   19
 
+#define AR_PHY_TX_PWRCTRL8       0xa278
+
 #define AR_PHY_TX_PWRCTRL9       0xa27C
+
+#define AR_PHY_TX_PWRCTRL10       0xa394
 #define AR_PHY_TX_DESIRED_SCALE_CCK        0x00007C00
 #define AR_PHY_TX_DESIRED_SCALE_CCK_S      10
 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL  0x80000000
@@ -493,6 +499,8 @@
 
 #define AR_PHY_CH0_TX_PWRCTRL11  0xa398
 #define AR_PHY_CH1_TX_PWRCTRL11  0xb398
+#define AR_PHY_CH0_TX_PWRCTRL12  0xa3dc
+#define AR_PHY_CH0_TX_PWRCTRL13  0xa3e0
 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP   0x0000FC00
 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index ec98ab50748a..e8ac70da5ac7 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -34,6 +34,10 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
 
 static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -52,21 +56,21 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
         {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
         {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
-        {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
-        {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
-        {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
-        {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
-        {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
-        {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
-        {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
-        {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
-        {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
+        {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
+        {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
+        {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
+        {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
+        {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
+        {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
+        {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
+        {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
         {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
         {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
         {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -84,21 +88,45 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
         {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
         {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
-        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
-        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
-        {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
-        {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
-        {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
-        {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
-        {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
-        {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
-        {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
+        {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
+        {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
+        {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
+        {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
+        {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
+        {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
+        {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
+        {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
+        {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
+        {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
+        {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
         {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
@@ -118,7 +146,7 @@ static const u32 ar9300Modes_fast_clock_2p2[][3] = {
         {0x00008014, 0x044c044c, 0x08980898},
         {0x0000801c, 0x148ec02b, 0x148ec057},
         {0x00008318, 0x000044c0, 0x00008980},
-        {0x00009e00, 0x03721821, 0x03721821},
+        {0x00009e00, 0x0372131c, 0x0372131c},
         {0x0000a230, 0x0000000b, 0x00000016},
         {0x0000a254, 0x00000898, 0x00001130},
 };
@@ -595,20 +623,22 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
-        {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
-        {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
+        {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
         {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
         {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
-        {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+        {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
         {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
         {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
         {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27},
         {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
         {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
         {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
         {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+        {0x0000a22c, 0x01026a2f, 0x01026a2f, 0x01026a2f, 0x01026a2f},
         {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
         {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
         {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
@@ -624,16 +654,16 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
         {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
-        {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+        {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
         {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
         {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000be04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
         {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
@@ -649,13 +679,13 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x00009814, 0x9280c00a},
         {0x00009818, 0x00000000},
         {0x0000981c, 0x00020028},
-        {0x00009834, 0x5f3ca3de},
+        {0x00009834, 0x6400a290},
         {0x00009838, 0x0108ecff},
-        {0x0000983c, 0x14750600},
+        {0x0000983c, 0x0d000600},
         {0x00009880, 0x201fff00},
         {0x00009884, 0x00001042},
         {0x000098a4, 0x00200400},
-        {0x000098b0, 0x52440bbe},
+        {0x000098b0, 0x32840bbe},
         {0x000098d0, 0x004b6a8e},
         {0x000098d4, 0x00000820},
         {0x000098dc, 0x00000000},
@@ -681,7 +711,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x00009e30, 0x06336f77},
         {0x00009e34, 0x6af6532f},
         {0x00009e38, 0x0cc80c00},
-        {0x00009e3c, 0xcf946222},
         {0x00009e40, 0x0d261820},
         {0x00009e4c, 0x00001004},
         {0x00009e50, 0x00ff03f1},
@@ -694,7 +723,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a220, 0x00000000},
         {0x0000a224, 0x00000000},
         {0x0000a228, 0x10002310},
-        {0x0000a22c, 0x01036a1e},
         {0x0000a23c, 0x00000000},
         {0x0000a244, 0x0c000000},
         {0x0000a2a0, 0x00000001},
@@ -702,10 +730,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a2c8, 0x00000000},
         {0x0000a2cc, 0x18c43433},
         {0x0000a2d4, 0x00000000},
-        {0x0000a2dc, 0x00000000},
-        {0x0000a2e0, 0x00000000},
-        {0x0000a2e4, 0x00000000},
-        {0x0000a2e8, 0x00000000},
         {0x0000a2ec, 0x00000000},
         {0x0000a2f0, 0x00000000},
         {0x0000a2f4, 0x00000000},
@@ -753,33 +777,17 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a430, 0x1ce739ce},
         {0x0000a434, 0x00000000},
         {0x0000a438, 0x00001801},
-        {0x0000a43c, 0x00000000},
+        {0x0000a43c, 0x00100000},
         {0x0000a440, 0x00000000},
         {0x0000a444, 0x00000000},
         {0x0000a448, 0x06000080},
         {0x0000a44c, 0x00000001},
         {0x0000a450, 0x00010000},
         {0x0000a458, 0x00000000},
-        {0x0000a600, 0x00000000},
-        {0x0000a604, 0x00000000},
-        {0x0000a608, 0x00000000},
-        {0x0000a60c, 0x00000000},
-        {0x0000a610, 0x00000000},
-        {0x0000a614, 0x00000000},
-        {0x0000a618, 0x00000000},
-        {0x0000a61c, 0x00000000},
-        {0x0000a620, 0x00000000},
-        {0x0000a624, 0x00000000},
-        {0x0000a628, 0x00000000},
-        {0x0000a62c, 0x00000000},
-        {0x0000a630, 0x00000000},
-        {0x0000a634, 0x00000000},
-        {0x0000a638, 0x00000000},
-        {0x0000a63c, 0x00000000},
         {0x0000a640, 0x00000000},
         {0x0000a644, 0x3fad9d74},
         {0x0000a648, 0x0048060a},
-        {0x0000a64c, 0x00000637},
+        {0x0000a64c, 0x00003c37},
         {0x0000a670, 0x03020100},
         {0x0000a674, 0x09080504},
         {0x0000a678, 0x0d0c0b0a},
@@ -802,10 +810,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a8f4, 0x00000000},
         {0x0000b2d0, 0x00000080},
         {0x0000b2d4, 0x00000000},
-        {0x0000b2dc, 0x00000000},
-        {0x0000b2e0, 0x00000000},
-        {0x0000b2e4, 0x00000000},
-        {0x0000b2e8, 0x00000000},
         {0x0000b2ec, 0x00000000},
         {0x0000b2f0, 0x00000000},
         {0x0000b2f4, 0x00000000},
@@ -820,10 +824,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000b8f4, 0x00000000},
         {0x0000c2d0, 0x00000080},
         {0x0000c2d4, 0x00000000},
-        {0x0000c2dc, 0x00000000},
-        {0x0000c2e0, 0x00000000},
-        {0x0000c2e4, 0x00000000},
-        {0x0000c2e8, 0x00000000},
         {0x0000c2ec, 0x00000000},
         {0x0000c2f0, 0x00000000},
         {0x0000c2f4, 0x00000000},
@@ -835,6 +835,10 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
 
 static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -855,7 +859,7 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
         {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
         {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
         {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
-        {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+        {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
         {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
         {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
         {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
@@ -900,6 +904,30 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+        {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+        {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
         {0x00016048, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
         {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
@@ -913,6 +941,10 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
 
 static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -933,7 +965,7 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
         {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
         {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
-        {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+        {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
         {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
         {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
         {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
@@ -978,6 +1010,30 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+        {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+        {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
         {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
@@ -1151,14 +1207,14 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
         {0x0000b074, 0x00000000},
         {0x0000b078, 0x00000000},
         {0x0000b07c, 0x00000000},
-        {0x0000b080, 0x32323232},
-        {0x0000b084, 0x2f2f3232},
-        {0x0000b088, 0x23282a2d},
-        {0x0000b08c, 0x1c1e2123},
-        {0x0000b090, 0x14171919},
-        {0x0000b094, 0x0e0e1214},
-        {0x0000b098, 0x03050707},
-        {0x0000b09c, 0x00030303},
+        {0x0000b080, 0x2a2d2f32},
+        {0x0000b084, 0x21232328},
+        {0x0000b088, 0x19191c1e},
+        {0x0000b08c, 0x12141417},
+        {0x0000b090, 0x07070e0e},
+        {0x0000b094, 0x03030305},
+        {0x0000b098, 0x00000003},
+        {0x0000b09c, 0x00000000},
         {0x0000b0a0, 0x00000000},
         {0x0000b0a4, 0x00000000},
         {0x0000b0a8, 0x00000000},
@@ -1251,6 +1307,10 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
 
 static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -1269,21 +1329,21 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
         {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
         {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
-        {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
-        {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
-        {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
-        {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
-        {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
-        {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
-        {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
-        {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
-        {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
+        {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
+        {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
+        {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
+        {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
+        {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
+        {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
+        {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
+        {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
         {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
         {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
         {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -1301,21 +1361,45 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
         {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
         {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
-        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
-        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
-        {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
-        {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
-        {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
-        {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
-        {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
-        {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
-        {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
+        {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
+        {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
+        {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
+        {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
+        {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
+        {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
+        {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
+        {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
+        {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
+        {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
+        {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
         {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
@@ -1414,15 +1498,10 @@ static const u32 ar9300_2p2_mac_core[][2] = {
         {0x00008144, 0xffffffff},
         {0x00008168, 0x00000000},
         {0x0000816c, 0x00000000},
-        {0x00008170, 0x18486200},
-        {0x00008174, 0x33332210},
-        {0x00008178, 0x00000000},
-        {0x0000817c, 0x00020000},
         {0x000081c0, 0x00000000},
         {0x000081c4, 0x33332210},
         {0x000081c8, 0x00000000},
         {0x000081cc, 0x00000000},
-        {0x000081d4, 0x00000000},
         {0x000081ec, 0x00000000},
         {0x000081f0, 0x00000000},
         {0x000081f4, 0x00000000},
@@ -1763,7 +1842,7 @@ static const u32 ar9300_2p2_soc_preamble[][2] = {
 
 static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
         /* Addr      allmodes  */
-        {0x00004040, 0x08212e5e},
+        {0x00004040, 0x0821265e},
         {0x00004040, 0x0008003b},
         {0x00004044, 0x00000000},
 };
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 4674ea8c9c99..f48051c50092 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,21 @@
 #include "hw-ops.h"
 #include "ar9003_phy.h"
 
+#define MAX_MEASUREMENT 8
+#define MAX_MAG_DELTA   11
+#define MAX_PHS_DELTA   10
+
+struct coeff {
+        int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
+        int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
+        int iqc_coeff[2];
+};
+
+enum ar9003_cal_types {
+        IQ_MISMATCH_CAL = BIT(0),
+        TEMP_COMP_CAL = BIT(1),
+};
+
 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                                         struct ath9k_cal_list *currCal)
 {
@@ -35,8 +50,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                 currCal->calData->calCountMax);
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting IQ Mismatch Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting IQ Mismatch Calibration\n");
 
                 /* Kick-off cal */
                 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
@@ -47,13 +62,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
                               AR_PHY_65NM_CH0_THERM_START, 1);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting Temperature Compensation Calibration\n");
-                break;
-        case ADC_DC_INIT_CAL:
-        case ADC_GAIN_CAL:
-        case ADC_DC_CAL:
-                /* Not yet */
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting Temperature Compensation Calibration\n");
                 break;
         }
 }
@@ -175,17 +185,19 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
 
         /* Accumulate IQ cal measures for active chains */
         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
-                ah->totalPowerMeasI[i] +=
-                        REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
-                ah->totalPowerMeasQ[i] +=
-                        REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
-                ah->totalIqCorrMeas[i] +=
-                        (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
-                          ah->cal_samples, i, ah->totalPowerMeasI[i],
-                          ah->totalPowerMeasQ[i],
-                          ah->totalIqCorrMeas[i]);
+                if (ah->txchainmask & BIT(i)) {
+                        ah->totalPowerMeasI[i] +=
+                                REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
+                        ah->totalPowerMeasQ[i] +=
+                                REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
+                        ah->totalIqCorrMeas[i] +=
+                                (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                                "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+                                ah->cal_samples, i, ah->totalPowerMeasI[i],
+                                ah->totalPowerMeasQ[i],
+                                ah->totalIqCorrMeas[i]);
+                }
         }
 }
 
@@ -196,7 +208,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
         u32 qCoffDenom, iCoffDenom;
         int32_t qCoff, iCoff;
         int iqCorrNeg, i;
-        const u_int32_t offset_array[3] = {
+        static const u_int32_t offset_array[3] = {
                 AR_PHY_RX_IQCAL_CORR_B0,
                 AR_PHY_RX_IQCAL_CORR_B1,
                 AR_PHY_RX_IQCAL_CORR_B2,
@@ -207,13 +219,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 powerMeasQ = ah->totalPowerMeasQ[i];
                 iqCorrMeas = ah->totalIqCorrMeas[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting IQ Cal and Correction for Chain %d\n",
-                          i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting IQ Cal and Correction for Chain %d\n",
+                        i);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
-                          i, ah->totalIqCorrMeas[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
 
@@ -222,12 +234,12 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iqCorrNeg = 1;
                 }
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-                ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
-                          iqCorrNeg);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
+                ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+                        iqCorrNeg);
 
                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
                 qCoffDenom = powerMeasQ / 64;
@@ -235,10 +247,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
                         iCoff = iqCorrMeas / iCoffDenom;
                         qCoff = powerMeasI / qCoffDenom - 64;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                         /* Force bounds on iCoff */
                         if (iCoff >= 63)
@@ -259,14 +271,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iCoff = iCoff & 0x7f;
                         qCoff = qCoff & 0x7f;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                  i, iCoff, qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) "
-                                  "before update = 0x%x\n",
-                                  offset_array[i],
-                                  REG_READ(ah, offset_array[i]));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
+                                i, iCoff, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) before update = 0x%x\n",
+                                offset_array[i],
+                                REG_READ(ah, offset_array[i]));
 
                         REG_RMW_FIELD(ah, offset_array[i],
                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
@@ -274,33 +285,29 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         REG_RMW_FIELD(ah, offset_array[i],
                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
                                       qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) QI COFF "
-                                  "(bitfields 0x%08x) after update = 0x%x\n",
-                                  offset_array[i],
-                                  AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
-                                  REG_READ(ah, offset_array[i]));
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) QQ COFF "
-                                  "(bitfields 0x%08x) after update = 0x%x\n",
-                                  offset_array[i],
-                                  AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
-                                  REG_READ(ah, offset_array[i]));
-
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ Cal and Correction done for Chain %d\n",
-                                  i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
+                                offset_array[i],
+                                AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
+                                REG_READ(ah, offset_array[i]));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
+                                offset_array[i],
+                                AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
+                                REG_READ(ah, offset_array[i]));
+
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "IQ Cal and Correction done for Chain %d\n", i);
                 }
         }
 
         REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
                     AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "IQ Cal and Correction (offset 0x%04x) enabled "
-                  "(bit position 0x%08x). New Value 0x%08x\n",
-                  (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
-                  AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
-                  REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
+                (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
+                AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
+                REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
 }
 
 static const struct ath9k_percal_data iq_cal_single_sample = {
@@ -314,27 +321,6 @@ static const struct ath9k_percal_data iq_cal_single_sample = {
 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
 {
         ah->iq_caldata.calData = &iq_cal_single_sample;
-        ah->supp_cals = IQ_MISMATCH_CAL;
-}
-
-static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
-                                      enum ath9k_cal_types calType)
-{
-        switch (calType & ah->supp_cals) {
-        case IQ_MISMATCH_CAL:
-                /*
-                 * XXX: Run IQ Mismatch for non-CCK only
-                 * Note that CHANNEL_B is never set though.
-                 */
-                return true;
-        case ADC_GAIN_CAL:
-        case ADC_DC_CAL:
-                return false;
-        case TEMP_COMP_CAL:
-                return true;
-        }
-
-        return false;
 }
 
 /*
@@ -361,7 +347,7 @@ static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
         f2 = (f1 * f1 + f3 * f3) / result_shift;
 
         if (!f2) {
-                ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
                 return false;
         }
 
@@ -482,11 +468,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
             (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0:\na0_d0=%d\n"
-                          "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
-                          i2_p_q2_a0_d0, i2_p_q2_a0_d1,
-                          i2_p_q2_a1_d0, i2_p_q2_a1_d1);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0:\n"
+                        "a0_d0=%d\n"
+                        "a0_d1=%d\n"
+                        "a2_d0=%d\n"
+                        "a1_d1=%d\n",
+                        i2_p_q2_a0_d0, i2_p_q2_a0_d1,
+                        i2_p_q2_a1_d0, i2_p_q2_a1_d1);
                 return false;
         }
 
@@ -519,9 +508,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
 
         if ((mag1 == 0) || (mag2 == 0)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag1=%d, mag2=%d\n",
-                          mag1, mag2);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag1=%d, mag2=%d\n",
+                        mag1, mag2);
                 return false;
         }
 
@@ -538,8 +527,8 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
                              mag_a0_d0, phs_a0_d0,
                              mag_a1_d0,
                              phs_a1_d0, solved_eq)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Call to ar9003_hw_solve_iq_cal() failed.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Call to ar9003_hw_solve_iq_cal() failed.\n");
                 return false;
         }
 
@@ -548,14 +537,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         mag_rx = solved_eq[2];
         phs_rx = solved_eq[3];
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "chain %d: mag mismatch=%d phase mismatch=%d\n",
-                  chain_idx, mag_tx/res_scale, phs_tx/res_scale);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "chain %d: mag mismatch=%d phase mismatch=%d\n",
+                chain_idx, mag_tx/res_scale, phs_tx/res_scale);
 
         if (res_scale == mag_tx) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag_tx=%d, res_scale=%d\n",
-                          mag_tx, res_scale);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag_tx=%d, res_scale=%d\n",
+                        mag_tx, res_scale);
                 return false;
         }
 
@@ -566,9 +555,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         q_q_coff = (mag_corr_tx * 128 / res_scale);
         q_i_coff = (phs_corr_tx * 256 / res_scale);
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "tx chain %d: mag corr=%d  phase corr=%d\n",
-                  chain_idx, q_q_coff, q_i_coff);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "tx chain %d: mag corr=%d  phase corr=%d\n",
+                chain_idx, q_q_coff, q_i_coff);
 
         if (q_i_coff < -63)
                 q_i_coff = -63;
@@ -581,14 +570,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "tx chain %d: iq corr coeff=%x\n",
-                  chain_idx, iqc_coeff[0]);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "tx chain %d: iq corr coeff=%x\n",
+                chain_idx, iqc_coeff[0]);
 
         if (-mag_rx == res_scale) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag_rx=%d, res_scale=%d\n",
-                          mag_rx, res_scale);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag_rx=%d, res_scale=%d\n",
+                        mag_rx, res_scale);
                 return false;
         }
 
@@ -599,9 +588,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         q_q_coff = (mag_corr_rx * 128 / res_scale);
         q_i_coff = (phs_corr_rx * 256 / res_scale);
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "rx chain %d: mag corr=%d  phase corr=%d\n",
-                  chain_idx, q_q_coff, q_i_coff);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "rx chain %d: mag corr=%d  phase corr=%d\n",
+                chain_idx, q_q_coff, q_i_coff);
 
         if (q_i_coff < -63)
                 q_i_coff = -63;
@@ -614,14 +603,142 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "rx chain %d: iq corr coeff=%x\n",
-                  chain_idx, iqc_coeff[1]);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "rx chain %d: iq corr coeff=%x\n",
+                chain_idx, iqc_coeff[1]);
 
         return true;
 }
 
-static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
+static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
+                                     int max_delta)
+{
+        int mp_max = -64, max_idx = 0;
+        int mp_min = 63, min_idx = 0;
+        int mp_avg = 0, i, outlier_idx = 0;
+
+        /* find min/max mismatch across all calibrated gains */
+        for (i = 0; i < nmeasurement; i++) {
+                mp_avg += mp_coeff[i];
+                if (mp_coeff[i] > mp_max) {
+                        mp_max = mp_coeff[i];
+                        max_idx = i;
+                } else if (mp_coeff[i] < mp_min) {
+                        mp_min = mp_coeff[i];
+                        min_idx = i;
+                }
+        }
+
+        /* find average (exclude max abs value) */
+        for (i = 0; i < nmeasurement; i++) {
+                if ((abs(mp_coeff[i]) < abs(mp_max)) ||
+                    (abs(mp_coeff[i]) < abs(mp_min)))
+                        mp_avg += mp_coeff[i];
+        }
+        mp_avg /= (nmeasurement - 1);
+
+        /* detect outlier */
+        if (abs(mp_max - mp_min) > max_delta) {
+                if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
+                        outlier_idx = max_idx;
+                else
+                        outlier_idx = min_idx;
+        }
+        mp_coeff[outlier_idx] = mp_avg;
+}
+
+static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
+                                                 u8 num_chains,
+                                                 struct coeff *coeff)
+{
+        int i, im, nmeasurement;
+        u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
+
+        memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
+        for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
+                tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
+                if (!AR_SREV_9485(ah)) {
+                        tx_corr_coeff[i * 2][1] =
+                        tx_corr_coeff[(i * 2) + 1][1] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
+
+                        tx_corr_coeff[i * 2][2] =
+                        tx_corr_coeff[(i * 2) + 1][2] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
+                }
+        }
+
+        /* Load the average of 2 passes */
+        for (i = 0; i < num_chains; i++) {
+                nmeasurement = REG_READ_FIELD(ah,
+                                AR_PHY_TX_IQCAL_STATUS_B0,
+                                AR_PHY_CALIBRATED_GAINS_0);
+
+                if (nmeasurement > MAX_MEASUREMENT)
+                        nmeasurement = MAX_MEASUREMENT;
+
+                /* detect outlier only if nmeasurement > 1 */
+                if (nmeasurement > 1) {
+                        /* Detect magnitude outlier */
+                        ar9003_hw_detect_outlier(coeff->mag_coeff[i],
+                                        nmeasurement, MAX_MAG_DELTA);
+
+                        /* Detect phase outlier */
+                        ar9003_hw_detect_outlier(coeff->phs_coeff[i],
+                                        nmeasurement, MAX_PHS_DELTA);
+                }
+
+                for (im = 0; im < nmeasurement; im++) {
+
+                        coeff->iqc_coeff[0] = (coeff->mag_coeff[i][im] & 0x7f) |
+                                ((coeff->phs_coeff[i][im] & 0x7f) << 7);
+
+                        if ((im % 2) == 0)
+                                REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
+                                        coeff->iqc_coeff[0]);
+                        else
+                                REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
+                                        coeff->iqc_coeff[0]);
+                }
+        }
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
+                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
+        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
+                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
+
+        return;
+
+}
+
+static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u8 tx_gain_forced;
+
+        tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
+                                        AR_PHY_TXGAIN_FORCE);
+        if (tx_gain_forced)
+                REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
+                              AR_PHY_TXGAIN_FORCE, 0);
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
+                      AR_PHY_TX_IQCAL_START_DO_CAL, 1);
+
+        if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
+                        AR_PHY_TX_IQCAL_START_DO_CAL, 0,
+                        AH_WAIT_TIMEOUT)) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Tx IQ Cal is not completed.\n");
+                return false;
+        }
+        return true;
+}
+
+static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
         const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
@@ -629,128 +746,130 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
                 AR_PHY_TX_IQCAL_STATUS_B1,
                 AR_PHY_TX_IQCAL_STATUS_B2,
         };
-        const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
-        };
-        const u32 rx_corr[AR9300_MAX_CHAINS] = {
-                AR_PHY_RX_IQCAL_CORR_B0,
-                AR_PHY_RX_IQCAL_CORR_B1,
-                AR_PHY_RX_IQCAL_CORR_B2,
-        };
         const u_int32_t chan_info_tab[] = {
                 AR_PHY_CHAN_INFO_TAB_0,
                 AR_PHY_CHAN_INFO_TAB_1,
                 AR_PHY_CHAN_INFO_TAB_2,
         };
+        struct coeff coeff;
         s32 iq_res[6];
-        s32 iqc_coeff[2];
-        s32 i, j;
-        u32 num_chains = 0;
+        u8 num_chains = 0;
+        int i, im, j;
+        int nmeasurement;
 
         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
                 if (ah->txchainmask & (1 << i))
                         num_chains++;
         }
 
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
-                      AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
-                      DELPT);
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
-                      AR_PHY_TX_IQCAL_START_DO_CAL,
-                      AR_PHY_TX_IQCAL_START_DO_CAL);
-
-        if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
-                           AR_PHY_TX_IQCAL_START_DO_CAL,
-                           0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Tx IQ Cal not complete.\n");
-                goto TX_IQ_CAL_FAILED;
-        }
-
         for (i = 0; i < num_chains; i++) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Doing Tx IQ Cal for chain %d.\n", i);
-
-                if (REG_READ(ah, txiqcal_status[i]) &
-                             AR_PHY_TX_IQCAL_STATUS_FAILED) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Tx IQ Cal failed for chain %d.\n", i);
-                        goto TX_IQ_CAL_FAILED;
-                }
-
-                for (j = 0; j < 3; j++) {
-                        u_int8_t idx = 2 * j,
-                        offset = 4 * j;
-
-                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
-                                      AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
-
-                        /* 32 bits */
-                        iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
+                nmeasurement = REG_READ_FIELD(ah,
+                                AR_PHY_TX_IQCAL_STATUS_B0,
+                                AR_PHY_CALIBRATED_GAINS_0);
+                if (nmeasurement > MAX_MEASUREMENT)
+                        nmeasurement = MAX_MEASUREMENT;
+
+                for (im = 0; im < nmeasurement; im++) {
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Doing Tx IQ Cal for chain %d.\n", i);
+
+                        if (REG_READ(ah, txiqcal_status[i]) &
+                                        AR_PHY_TX_IQCAL_STATUS_FAILED) {
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "Tx IQ Cal failed for chain %d.\n", i);
+                                goto tx_iqcal_fail;
+                        }
 
-                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
-                                      AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
+                        for (j = 0; j < 3; j++) {
+                                u32 idx = 2 * j, offset = 4 * (3 * im + j);
+
+                                REG_RMW_FIELD(ah,
+                                                AR_PHY_CHAN_INFO_MEMORY,
+                                                AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                0);
+
+                                /* 32 bits */
+                                iq_res[idx] = REG_READ(ah,
+                                                chan_info_tab[i] +
+                                                offset);
+
+                                REG_RMW_FIELD(ah,
+                                                AR_PHY_CHAN_INFO_MEMORY,
+                                                AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                1);
+
+                                /* 16 bits */
+                                iq_res[idx + 1] = 0xffff & REG_READ(ah,
+                                                chan_info_tab[i] + offset);
+
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "IQ RES[%d]=0x%x"
+                                        "IQ_RES[%d]=0x%x\n",
+                                        idx, iq_res[idx], idx + 1,
+                                        iq_res[idx + 1]);
+                        }
 
-                        /* 16 bits */
-                        iq_res[idx+1] = 0xffff & REG_READ(ah,
-                                                          chan_info_tab[i] +
-                                                          offset);
+                        if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
+                                                coeff.iqc_coeff)) {
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "Failed in calculation of \
+                                        IQ correction.\n");
+                                goto tx_iqcal_fail;
+                        }
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
-                                  idx, iq_res[idx], idx+1, iq_res[idx+1]);
-                }
+                        coeff.mag_coeff[i][im] = coeff.iqc_coeff[0] & 0x7f;
+                        coeff.phs_coeff[i][im] =
+                                (coeff.iqc_coeff[0] >> 7) & 0x7f;
 
-                if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Failed in calculation of IQ correction.\n");
-                        goto TX_IQ_CAL_FAILED;
+                        if (coeff.mag_coeff[i][im] > 63)
+                                coeff.mag_coeff[i][im] -= 128;
+                        if (coeff.phs_coeff[i][im] > 63)
+                                coeff.phs_coeff[i][im] -= 128;
                 }
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
-                          iqc_coeff[0], iqc_coeff[1]);
-
-                REG_RMW_FIELD(ah, tx_corr_coeff[i],
-                              AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
-                              iqc_coeff[0]);
-                REG_RMW_FIELD(ah, rx_corr[i],
-                              AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
-                              iqc_coeff[1] >> 7);
-                REG_RMW_FIELD(ah, rx_corr[i],
-                              AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
-                              iqc_coeff[1]);
         }
-
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
-                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
-        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
-                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
+        ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
 
         return;
 
-TX_IQ_CAL_FAILED:
-        ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+tx_iqcal_fail:
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+        return;
 }
-
 static bool ar9003_hw_init_cal(struct ath_hw *ah,
                                struct ath9k_channel *chan)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_capabilities *pCap = &ah->caps;
+        int val;
+        bool txiqcal_done = false;
 
-        /*
-         * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
-         * running AGC/TxIQ cals
-         */
-        ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
+        val = REG_READ(ah, AR_ENT_OTP);
+        ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
+
+        /* Configure rx/tx chains before running AGC/TxiQ cals */
+        if (val & AR_ENT_OTP_CHAIN2_DISABLE)
+                ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
+        else
+                ar9003_hw_set_chain_masks(ah, pCap->rx_chainmask,
+                                          pCap->tx_chainmask);
 
         /* Do Tx IQ Calibration */
-        ar9003_hw_tx_iq_cal(ah);
-        REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-        udelay(5);
-        REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
+                      AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
+                      DELPT);
+
+        /*
+         * For AR9485 or later chips, TxIQ cal runs as part of
+         * AGC calibration
+         */
+        if (AR_SREV_9485_OR_LATER(ah))
+                txiqcal_done = true;
+        else {
+                txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
+                REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+                udelay(5);
+                REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+        }
 
         /* Calibrate the AGC */
         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -760,12 +879,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
         /* Poll for offset calibration complete */
         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                            0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "offset calibration failed to "
-                          "complete in 1ms; noisy environment?\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "offset calibration failed to complete in 1ms; noisy environment?\n");
                 return false;
         }
 
+        if (txiqcal_done)
+                ar9003_hw_tx_iq_cal_post_proc(ah);
+
         /* Revert chainmasks to their original values before NF cal */
         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 
@@ -773,19 +894,20 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
 
         /* Initialize list pointers */
         ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
+        ah->supp_cals = IQ_MISMATCH_CAL;
 
-        if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
+        if (ah->supp_cals & IQ_MISMATCH_CAL) {
                 INIT_CAL(&ah->iq_caldata);
                 INSERT_CAL(ah, &ah->iq_caldata);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling IQ Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling IQ Calibration.\n");
         }
 
-        if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
+        if (ah->supp_cals & TEMP_COMP_CAL) {
                 INIT_CAL(&ah->tempCompCalData);
                 INSERT_CAL(ah, &ah->tempCompCalData);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling Temperature Compensation Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling Temperature Compensation Calibration.\n");
         }
 
         /* Initialize current pointer to first element in list */
@@ -808,7 +930,6 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
         priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
         priv_ops->init_cal = ar9003_hw_init_cal;
         priv_ops->setup_calibration = ar9003_hw_setup_calibration;
-        priv_ops->iscal_supported = ar9003_hw_iscal_supported;
 
         ops->calibrate = ar9003_hw_calibrate;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 057fb69ddf7f..ff8150e46f0e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -22,12 +22,14 @@
 #define COMP_CKSUM_LEN 2
 
 #define AR_CH0_TOP (0x00016288)
-#define AR_CH0_TOP_XPABIASLVL (0x3)
+#define AR_CH0_TOP_XPABIASLVL (0x300)
 #define AR_CH0_TOP_XPABIASLVL_S (8)
 
 #define AR_CH0_THERM (0x00016290)
-#define AR_CH0_THERM_SPARE (0x3f)
-#define AR_CH0_THERM_SPARE_S (0)
+#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
+#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
+#define AR_CH0_THERM_XPASHORT2GND 0x4
+#define AR_CH0_THERM_XPASHORT2GND_S 2
 
 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
 #define AR_SWITCH_TABLE_COM_ALL_S (0)
@@ -55,6 +57,14 @@
 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
 
+#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
+
+#define EEPROM_DATA_LEN_9485    1088
+
+static int ar9003_hw_power_interpolate(int32_t x,
+                                       int32_t *px, int32_t *py, u_int16_t np);
+
+
 static const struct ar9300_eeprom ar9300_default = {
         .eepromVersion = 2,
         .templateVersion = 2,
@@ -65,7 +75,7 @@ static const struct ar9300_eeprom ar9300_default = {
                 .regDmn = { LE16(0), LE16(0x1f) },
                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
                 .opCapFlags = {
-                        .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
                         .eepMisc = 0,
                 },
                 .rfSilent = 0,
@@ -144,13 +154,16 @@ static const struct ar9300_eeprom ar9300_default = {
                 .txEndToRxOn = 0x2,
                 .txFrameToXpaOn = 0xe,
                 .thresh62 = 28,
-                .papdRateMaskHt20 = LE32(0x80c080),
-                .papdRateMaskHt40 = LE32(0x80c080),
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
                 .futureModal = {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                 },
          },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
         .calFreqPier2G = {
                 FREQ2FBIN(2412, 1),
                 FREQ2FBIN(2437, 1),
@@ -285,25 +298,25 @@ static const struct ar9300_eeprom ar9300_default = {
                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
-                        /* Data[11].ctlEdges[3].bChannel */
-                        FREQ2FBIN(2462, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
                 }
          },
         .ctlPowerData_2G = {
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 
-                 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
-                 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
          },
         .modalHeader5G = {
                 /* 4 idle,t1,t2,b (4 bits per setting) */
@@ -343,13 +356,20 @@ static const struct ar9300_eeprom ar9300_default = {
                 .txEndToRxOn = 0x2,
                 .txFrameToXpaOn = 0xe,
                 .thresh62 = 28,
-                .papdRateMaskHt20 = LE32(0xf0e0e0),
-                .papdRateMaskHt40 = LE32(0xf0e0e0),
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
                 .futureModal = {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                 },
          },
+        .base_ext2 = {
+                .tempSlopeLow = 0,
+                .tempSlopeHigh = 0,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+        },
         .calFreqPier5G = {
                 FREQ2FBIN(5180, 0),
                 FREQ2FBIN(5220, 0),
@@ -568,64 +588,2396 @@ static const struct ar9300_eeprom ar9300_default = {
         .ctlPowerData_5G = {
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+         }
+};
+
+static const struct ar9300_eeprom ar9300_x113 = {
+        .eepromVersion = 2,
+        .templateVersion = 6,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"x113-023-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                 /*
+                  * bit0 - enable tx temp comp - disabled
+                  * bit1 - enable tx volt comp - disabled
+                  * bit2 - enable fastClock - enabled
+                  * bit3 - enable doubling - enabled
+                  * bit4 - enable internal regulator - disabled
+                  * bit5 - enable pa predistortion - disabled
+                  */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x21,
+                .swreg = 0,
+         },
+        .modalHeader2G = {
+        /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+         .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+         },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+         },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTargetPowerCck = {
+                 /* 1L-5L,5S,11L,11S */
+                 { {34, 34, 34, 34} },
+                 { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                 /* 6-24,36,48,54 */
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+         },
+        .ctlPowerData_2G = {
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+         },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x11111),
+                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 68,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0xf,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+        .base_ext2 = {
+                .tempSlopeLow = 72,
+                .tempSlopeHigh = 105,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+         },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5190, 0),
+                FREQ2FBIN(5230, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5410, 0),
+                FREQ2FBIN(5510, 0),
+                FREQ2FBIN(5670, 0),
+                FREQ2FBIN(5755, 0),
+                FREQ2FBIN(5825, 0)
+         },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+         },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
+                { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
+         },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
+                { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
+         },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+         },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
                         }
                 },
                 {
                         {
-                                {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                                {60, 1}, {60, 0}, {60, 0}, {60, 0},
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                                {60, 0}, {60, 0}, {60, 0}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 0}, {60, 0}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 0}, {60, 1},
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
                         }
                 },
          }
 };
 
+
+static const struct ar9300_eeprom ar9300_h112 = {
+        .eepromVersion = 2,
+        .templateVersion = 3,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"h112-241-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                /*
+                 * bit0 - enable tx temp comp - disabled
+                 * bit1 - enable tx volt comp - disabled
+                 * bit2 - enable fastClock - enabled
+                 * bit3 - enable doubling - enabled
+                 * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
+                 */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x10,
+                .swreg = 0,
+        },
+        .modalHeader2G = {
+                /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x80c080),
+                .papdRateMaskHt40 = LE32(0x80c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+        },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2484, 1),
+        },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTargetPowerCck = {
+                /* 1L-5L,5S,11L,11S */
+                { {34, 34, 34, 34} },
+                { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                /* 6-24,36,48,54 */
+                { {34, 34, 32, 32} },
+                { {34, 34, 32, 32} },
+                { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+        },
+        .ctlPowerData_2G = {
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+        },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+                /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 45,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext2 = {
+                .tempSlopeLow = 40,
+                .tempSlopeHigh = 50,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+        },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calPierData5G = {
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+        },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
+        },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
+        },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+        },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+        }
+};
+
+
+static const struct ar9300_eeprom ar9300_x112 = {
+        .eepromVersion = 2,
+        .templateVersion = 5,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"x112-041-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                /*
+                 * bit0 - enable tx temp comp - disabled
+                 * bit1 - enable tx volt comp - disabled
+                 * bit2 - enable fastclock - enabled
+                 * bit3 - enable doubling - enabled
+                 * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
+                 */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x0,
+                .swreg = 0,
+        },
+        .modalHeader2G = {
+                /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x22222),
+
+                /*
+                 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+                /*
+                 * xatten1DB[AR9300_max_chains];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0x1b, 0x1b, 0x1b},
+
+                /*
+                 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x15, 0x15, 0x15},
+                .tempSlope = 50,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+        },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTargetPowerCck = {
+                /* 1L-5L,5S,11L,11s */
+                { {38, 38, 38, 38} },
+                { {38, 38, 38, 38} },
+        },
+        .calTargetPower2G = {
+                /* 6-24,36,48,54 */
+                { {38, 38, 36, 34} },
+                { {38, 38, 36, 34} },
+                { {38, 38, 34, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
+                { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
+                { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
+        },
+        .calTargetPower2GHT40 = {
+                { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
+                { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
+                { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
+                }
+        },
+        .ctlPowerData_2G = {
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+        },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x22222),
+                /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x0), LE16(0x0), LE16(0x0),
+                },
+                /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0x13, 0x19, 0x17},
+
+                /*
+                 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x19, 0x19, 0x19},
+                .tempSlope = 70,
+                .voltSlope = 15,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshch check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext2 = {
+                .tempSlopeLow = 72,
+                .tempSlopeHigh = 105,
+                .xatten1DBLow = {0x10, 0x14, 0x10},
+                .xatten1MarginLow = {0x19, 0x19 , 0x19},
+                .xatten1DBHigh = {0x1d, 0x20, 0x24},
+                .xatten1MarginHigh = {0x10, 0x10, 0x10}
+        },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {32, 32, 28, 26} },
+                { {32, 32, 28, 26} },
+                { {32, 32, 28, 26} },
+                { {32, 32, 26, 24} },
+                { {32, 32, 26, 24} },
+                { {32, 32, 24, 22} },
+                { {30, 30, 24, 22} },
+                { {30, 30, 24, 22} },
+        },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
+                { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
+                { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
+        },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
+                { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
+                { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+        },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctledges[6].bchannel */ 0xFF,
+                        /* Data[3].ctledges[7].bchannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctledges[4].bchannel */ 0xFF,
+                        /* Data[4].ctledges[5].bchannel */ 0xFF,
+                        /* Data[4].ctledges[6].bchannel */ 0xFF,
+                        /* Data[4].ctledges[7].bchannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctledges[6].bchannel */ 0xFF,
+                        /* Data[5].ctledges[7].bchannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
+                }
+        },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+        }
+};
+
+static const struct ar9300_eeprom ar9300_h116 = {
+        .eepromVersion = 2,
+        .templateVersion = 4,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"h116-041-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                 /*
+                  * bit0 - enable tx temp comp - disabled
+                  * bit1 - enable tx volt comp - disabled
+                  * bit2 - enable fastClock - enabled
+                  * bit3 - enable doubling - enabled
+                  * bit4 - enable internal regulator - disabled
+                  * bit5 - enable pa predistortion - disabled
+                  */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x10,
+                .swreg = 0,
+         },
+        .modalHeader2G = {
+        /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0x1f, 0x1f, 0x1f},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x12, 0x12, 0x12},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80C080),
+                .papdRateMaskHt40 = LE32(0x0080C080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+         .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+         },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+         },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTargetPowerCck = {
+                 /* 1L-5L,5S,11L,11S */
+                 { {34, 34, 34, 34} },
+                 { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                 /* 6-24,36,48,54 */
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+         },
+        .ctlPowerData_2G = {
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+         },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0x19, 0x19, 0x19},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x14, 0x14, 0x14},
+                .tempSlope = 70,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+        .base_ext2 = {
+                .tempSlopeLow = 35,
+                .tempSlopeHigh = 50,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+         },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+         },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+         },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+         },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+         },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+         },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+         }
+};
+
+
+static const struct ar9300_eeprom *ar9300_eep_templates[] = {
+        &ar9300_default,
+        &ar9300_x112,
+        &ar9300_h116,
+        &ar9300_h112,
+        &ar9300_x113,
+};
+
+static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
+{
+#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
+        int it;
+
+        for (it = 0; it < N_LOOP; it++)
+                if (ar9300_eep_templates[it]->templateVersion == id)
+                        return ar9300_eep_templates[it];
+        return NULL;
+#undef N_LOOP
+}
+
+
 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
 {
-        if (fbin == AR9300_BCHAN_UNUSED)
+        if (fbin == AR5416_BCHAN_UNUSED)
                 return fbin;
 
         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
@@ -636,6 +2988,16 @@ static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
         return 0;
 }
 
+static int interpolate(int x, int xa, int xb, int ya, int yb)
+{
+        int bf, factor, plus;
+
+        bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
+        factor = bf / 2;
+        plus = bf % 2;
+        return ya + factor + plus;
+}
+
 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                                       enum eeprom_param param)
 {
@@ -673,6 +3035,10 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                 return le32_to_cpu(pBase->swreg);
         case EEP_PAPRD:
                 return !!(pBase->featureEnable & BIT(5));
+        case EEP_CHAIN_MASK_REDUCE:
+                return (pBase->miscConfiguration >> 0x3) & 0x1;
+        case EEP_ANT_DIV_CTL1:
+                return le32_to_cpu(eep->base_ext1.ant_div_control);
         default:
                 return 0;
         }
@@ -711,8 +3077,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
         int i;
 
         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "eeprom address not in range\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "eeprom address not in range\n");
                 return false;
         }
 
@@ -743,11 +3109,41 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
         return true;
 
 error:
-        ath_print(common, ATH_DBG_EEPROM,
-                  "unable to read eeprom region at offset %d\n", address);
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "unable to read eeprom region at offset %d\n", address);
         return false;
 }
 
+static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
+{
+        REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
+
+        if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
+                           AR9300_OTP_STATUS_VALID, 1000))
+                return false;
+
+        *data = REG_READ(ah, AR9300_OTP_READ_DATA);
+        return true;
+}
+
+static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
+                            int count)
+{
+        u32 data;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                int offset = 8 * ((address - i) % 4);
+                if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
+                        return false;
+
+                buffer[i] = (data >> offset) & 0xff;
+        }
+
+        return true;
+}
+
+
 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
                                    int *length, int *major, int *minor)
 {
@@ -798,17 +3194,15 @@ static bool ar9300_uncompress_block(struct ath_hw *ah,
                 length &= 0xff;
 
                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Restore at %d: spot=%d "
-                                  "offset=%d length=%d\n",
-                                   it, spot, offset, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Restore at %d: spot=%d offset=%d length=%d\n",
+                                it, spot, offset, length);
                         memcpy(&mptr[spot], &block[it+2], length);
                         spot += length;
                 } else if (length > 0) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Bad restore at %d: spot=%d "
-                                  "offset=%d length=%d\n",
-                                  it, spot, offset, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Bad restore at %d: spot=%d offset=%d length=%d\n",
+                                it, spot, offset, length);
                         return false;
                 }
         }
@@ -823,46 +3217,79 @@ static int ar9300_compress_decision(struct ath_hw *ah,
                                     u8 *word, int length, int mdata_size)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        u8 *dptr;
+        const struct ar9300_eeprom *eep = NULL;
 
         switch (code) {
         case _CompressNone:
                 if (length != mdata_size) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "EEPROM structure size mismatch"
-                                  "memory=%d eeprom=%d\n", mdata_size, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "EEPROM structure size mismatch memory=%d eeprom=%d\n",
+                                mdata_size, length);
                         return -1;
                 }
                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
-                ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
-                          " uncompressed, length %d\n", it, length);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "restored eeprom %d: uncompressed, length %d\n",
+                        it, length);
                 break;
         case _CompressBlock:
                 if (reference == 0) {
-                        dptr = mptr;
                 } else {
-                        if (reference != 2) {
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "cant find reference eeprom"
-                                          "struct %d\n", reference);
+                        eep = ar9003_eeprom_struct_find_by_id(reference);
+                        if (eep == NULL) {
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "can't find reference eeprom struct %d\n",
+                                        reference);
                                 return -1;
                         }
-                        memcpy(mptr, &ar9300_default, mdata_size);
+                        memcpy(mptr, eep, mdata_size);
                 }
-                ath_print(common, ATH_DBG_EEPROM,
-                          "restore eeprom %d: block, reference %d,"
-                          " length %d\n", it, reference, length);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "restore eeprom %d: block, reference %d, length %d\n",
+                        it, reference, length);
                 ar9300_uncompress_block(ah, mptr, mdata_size,
                                         (u8 *) (word + COMP_HDR_LEN), length);
                 break;
         default:
-                ath_print(common, ATH_DBG_EEPROM, "unknown compression"
-                          " code %d\n", code);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "unknown compression code %d\n", code);
                 return -1;
         }
         return 0;
 }
 
+typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
+                               int count);
+
+static bool ar9300_check_header(void *data)
+{
+        u32 *word = data;
+        return !(*word == 0 || *word == ~0);
+}
+
+static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
+                                       int base_addr)
+{
+        u8 header[4];
+
+        if (!read(ah, base_addr, header, 4))
+                return false;
+
+        return ar9300_check_header(header);
+}
+
+static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
+                                       int mdata_size)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u16 *data = (u16 *) mptr;
+        int i;
+
+        for (i = 0; i < mdata_size / 2; i++, data++)
+                ath9k_hw_nvram_read(common, i, data);
+
+        return 0;
+}
 /*
  * Read the configuration data from the eeprom.
  * The data can be put in any specified memory buffer.
@@ -883,6 +3310,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
         int it;
         u16 checksum, mchecksum;
         struct ath_common *common = ath9k_hw_common(ah);
+        eeprom_read_op read;
+
+        if (ath9k_hw_use_flash(ah))
+                return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
 
         word = kzalloc(2048, GFP_KERNEL);
         if (!word)
@@ -890,43 +3321,73 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
 
         memcpy(mptr, &ar9300_default, mdata_size);
 
+        read = ar9300_read_eeprom;
+        if (AR_SREV_9485(ah))
+                cptr = AR9300_BASE_ADDR_4K;
+        else
+                cptr = AR9300_BASE_ADDR;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying EEPROM access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        cptr = AR9300_BASE_ADDR_512;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying EEPROM access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        read = ar9300_read_otp;
         cptr = AR9300_BASE_ADDR;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying OTP access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        cptr = AR9300_BASE_ADDR_512;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying OTP access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        goto fail;
+
+found:
+        ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
+
         for (it = 0; it < MSTATE; it++) {
-                if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
+                if (!read(ah, cptr, word, COMP_HDR_LEN))
                         goto fail;
 
-                if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
-                     word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
-                                       && word[2] == 0xff && word[3] == 0xff))
+                if (!ar9300_check_header(word))
                         break;
 
                 ar9300_comp_hdr_unpack(word, &code, &reference,
                                        &length, &major, &minor);
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Found block at %x: code=%d ref=%d"
-                          "length=%d major=%d minor=%d\n", cptr, code,
-                          reference, length, major, minor);
-                if (length >= 1024) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Skipping bad header\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
+                        cptr, code, reference, length, major, minor);
+                if ((!AR_SREV_9485(ah) && length >= 1024) ||
+                    (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Skipping bad header\n");
                         cptr -= COMP_HDR_LEN;
                         continue;
                 }
 
                 osize = length;
-                ar9300_read_eeprom(ah, cptr, word,
-                                   COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
+                read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
                 mchecksum = word[COMP_HDR_LEN + osize] |
                     (word[COMP_HDR_LEN + osize + 1] << 8);
-                ath_print(common, ATH_DBG_EEPROM,
-                          "checksum %x %x\n", checksum, mchecksum);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "checksum %x %x\n", checksum, mchecksum);
                 if (checksum == mchecksum) {
                         ar9300_compress_decision(ah, it, code, reference, mptr,
                                                  word, length, mdata_size);
                 } else {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "skipping block with bad checksum\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "skipping block with bad checksum\n");
                 }
                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
         }
@@ -967,18 +3428,6 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
         return 0;
 }
 
-static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
-                                             enum ieee80211_band freq_band)
-{
-        return 1;
-}
-
-static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                                  struct ath9k_channel *chan)
-{
-        return -EINVAL;
-}
-
 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 {
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
@@ -992,9 +3441,17 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
-        REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
-        REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
-                      ((bias >> 2) & 0x3));
+
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+        else {
+                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+                REG_RMW_FIELD(ah, AR_CH0_THERM,
+                                AR_CH0_THERM_XPABIASLVL_MSB,
+                                bias >> 2);
+                REG_RMW_FIELD(ah, AR_CH0_THERM,
+                                AR_CH0_THERM_XPASHORT2GND, 1);
+        }
 }
 
 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@ -1040,20 +3497,77 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
 
 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
 {
+        int chain;
+        u32 regval;
+        u32 ant_div_ctl1;
+        static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
+                        AR_PHY_SWITCH_CHAIN_0,
+                        AR_PHY_SWITCH_CHAIN_1,
+                        AR_PHY_SWITCH_CHAIN_2,
+        };
+
         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
+
         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
 
         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
+        for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
+                if ((ah->rxchainmask & BIT(chain)) ||
+                    (ah->txchainmask & BIT(chain))) {
+                        value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
+                                                             is2ghz);
+                        REG_RMW_FIELD(ah, switch_chain_reg[chain],
+                                      AR_SWITCH_TABLE_ALL, value);
+                }
+        }
+
+        if (AR_SREV_9485(ah)) {
+                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                /*
+                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
+                 * are the fields present
+                 */
+                regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                regval &= (~AR_ANT_DIV_CTRL_ALL);
+                regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
+                /* enable_lnadiv */
+                regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
+                regval |= ((value >> 6) & 0x1) <<
+                                AR_PHY_9485_ANT_DIV_LNADIV_S;
+                REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+
+                /*enable fast_div */
+                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
+                regval &= (~AR_FAST_DIV_ENABLE);
+                regval |= ((value >> 7) & 0x1) <<
+                                AR_FAST_DIV_ENABLE_S;
+                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
+                ant_div_ctl1 =
+                        ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                /* check whether antenna diversity is enabled */
+                if ((ant_div_ctl1 >> 0x6) == 0x3) {
+                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                        /*
+                         * clear bits 25-30 main_lnaconf, alt_lnaconf,
+                         * main_tb, alt_tb
+                         */
+                        regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                                        AR_PHY_9485_ANT_DIV_ALT_GAINTB |
+                                        AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
+                        /* by default use LNA1 for the main antenna */
+                        regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
+                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
+                        regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
+                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
+                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+                }
+
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
+        }
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
 }
 
 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@ -1097,28 +3611,180 @@ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
 }
 
+static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
+                                     struct ath9k_channel *chan)
+{
+        int f[3], t[3];
+        u16 value;
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (chain >= 0 && chain < 3) {
+                if (IS_CHAN_2GHZ(chan))
+                        return eep->modalHeader2G.xatten1DB[chain];
+                else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
+                        t[0] = eep->base_ext2.xatten1DBLow[chain];
+                        f[0] = 5180;
+                        t[1] = eep->modalHeader5G.xatten1DB[chain];
+                        f[1] = 5500;
+                        t[2] = eep->base_ext2.xatten1DBHigh[chain];
+                        f[2] = 5785;
+                        value = ar9003_hw_power_interpolate((s32) chan->channel,
+                                                            f, t, 3);
+                        return value;
+                } else
+                        return eep->modalHeader5G.xatten1DB[chain];
+        }
+
+        return 0;
+}
+
+
+static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
+                                            struct ath9k_channel *chan)
+{
+        int f[3], t[3];
+        u16 value;
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (chain >= 0 && chain < 3) {
+                if (IS_CHAN_2GHZ(chan))
+                        return eep->modalHeader2G.xatten1Margin[chain];
+                else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
+                        t[0] = eep->base_ext2.xatten1MarginLow[chain];
+                        f[0] = 5180;
+                        t[1] = eep->modalHeader5G.xatten1Margin[chain];
+                        f[1] = 5500;
+                        t[2] = eep->base_ext2.xatten1MarginHigh[chain];
+                        f[2] = 5785;
+                        value = ar9003_hw_power_interpolate((s32) chan->channel,
+                                                            f, t, 3);
+                        return value;
+                } else
+                        return eep->modalHeader5G.xatten1Margin[chain];
+        }
+
+        return 0;
+}
+
+static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
+{
+        int i;
+        u16 value;
+        unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
+                                          AR_PHY_EXT_ATTEN_CTL_1,
+                                          AR_PHY_EXT_ATTEN_CTL_2,
+                                         };
+
+        /* Test value. if 0 then attenuation is unused. Don't load anything. */
+        for (i = 0; i < 3; i++) {
+                if (ah->txchainmask & BIT(i)) {
+                        value = ar9003_hw_atten_chain_get(ah, i, chan);
+                        REG_RMW_FIELD(ah, ext_atten_reg[i],
+                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
+
+                        value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
+                        REG_RMW_FIELD(ah, ext_atten_reg[i],
+                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
+                                      value);
+                }
+        }
+}
+
+static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
+{
+        int timeout = 100;
+
+        while (pmu_set != REG_READ(ah, pmu_reg)) {
+                if (timeout-- == 0)
+                        return false;
+                REG_WRITE(ah, pmu_reg, pmu_set);
+                udelay(10);
+        }
+
+        return true;
+}
+
 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
 {
         int internal_regulator =
                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
 
         if (internal_regulator) {
-                /* Internal regulator is ON. Write swreg register. */
-                int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
-                REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                REG_READ(ah, AR_RTC_REG_CONTROL1) &
-                         (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
-                REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
-                /* Set REG_CONTROL1.SWREG_PROGRAM */
-                REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                          REG_READ(ah,
-                                   AR_RTC_REG_CONTROL1) |
-                                   AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+                if (AR_SREV_9485(ah)) {
+                        int reg_pmu_set;
+
+                        reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
+                                      (2 << 14) | (6 << 17) | (1 << 20) |
+                                      (3 << 24) | (1 << 28);
+
+                        REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
+                                        | (4 << 26);
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
+                                        | (1 << 21);
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+                } else {
+                        /* Internal regulator is ON. Write swreg register. */
+                        int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                  REG_READ(ah, AR_RTC_REG_CONTROL1) &
+                                  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
+                        /* Set REG_CONTROL1.SWREG_PROGRAM */
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                  REG_READ(ah,
+                                           AR_RTC_REG_CONTROL1) |
+                                           AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+                }
         } else {
-                REG_WRITE(ah, AR_RTC_SLEEP_CLK,
-                          (REG_READ(ah,
-                                    AR_RTC_SLEEP_CLK) |
-                                    AR_RTC_FORCE_SWREG_PRD));
+                if (AR_SREV_9485(ah)) {
+                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
+                        while (REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                              AR_PHY_PMU2_PGM))
+                                udelay(10);
+
+                        REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
+                        while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
+                                               AR_PHY_PMU1_PWD))
+                                udelay(10);
+                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
+                        while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                              AR_PHY_PMU2_PGM))
+                                udelay(10);
+                } else
+                        REG_WRITE(ah, AR_RTC_SLEEP_CLK,
+                                  (REG_READ(ah,
+                                   AR_RTC_SLEEP_CLK) |
+                                   AR_RTC_FORCE_SWREG_PRD));
+        }
+
+}
+
+static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+
+        if (eep->baseEepHeader.featureEnable & 0x40) {
+                tuning_caps_param &= 0x7f;
+                REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
+                              tuning_caps_param);
+                REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
+                              tuning_caps_param);
         }
 }
 
@@ -1128,7 +3794,11 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
         ar9003_hw_drive_strength_apply(ah);
-        ar9003_hw_internal_regulator_apply(ah);
+        ar9003_hw_atten_apply(ah, chan);
+        if (!AR_SREV_9340(ah))
+                ar9003_hw_internal_regulator_apply(ah);
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                ar9003_hw_apply_tuning_caps(ah);
 }
 
 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -1189,7 +3859,7 @@ static int ar9003_hw_power_interpolate(int32_t x,
                         if (hx == lx)
                                 y = ly;
                         else    /* interpolate  */
-                                y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
+                                y = interpolate(x, lx, hx, ly, hy);
                 } else          /* only low is good, use it */
                         y = ly;
         } else if (hhave)       /* only high is good, use it */
@@ -1336,19 +4006,19 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
 {
 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
         /* make sure forced gain is not set */
-        REG_WRITE(ah, 0xa458, 0);
+        REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
 
         /* Write the OFDM power per rate set */
 
         /* 6 (LSB), 9, 12, 18 (MSB) */
-        REG_WRITE(ah, 0xa3c0,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
 
         /* 24 (LSB), 36, 48, 54 (MSB) */
-        REG_WRITE(ah, 0xa3c4,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
@@ -1357,24 +4027,34 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
         /* Write the CCK power per rate set */
 
         /* 1L (LSB), reserved, 2L, 2S (MSB) */
-        REG_WRITE(ah, 0xa3c8,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
 
         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
-        REG_WRITE(ah, 0xa3cc,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
             );
 
+        /* Write the power for duplicated frames - HT40 */
+
+        /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
+        REG_WRITE(ah, 0xa3e0,
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
+            );
+
         /* Write the HT20 power per rate set */
 
         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
-        REG_WRITE(ah, 0xa3d0,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
@@ -1382,7 +4062,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 6 (LSB), 7, 12, 13 (MSB) */
-        REG_WRITE(ah, 0xa3d4,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
@@ -1390,7 +4070,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 14 (LSB), 15, 20, 21 */
-        REG_WRITE(ah, 0xa3e4,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
@@ -1400,7 +4080,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
         /* Mixed HT20 and HT40 rates */
 
         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
-        REG_WRITE(ah, 0xa3e8,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
@@ -1412,7 +4092,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
          * correct PAR difference between HT40 and HT20/LEGACY
          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
          */
-        REG_WRITE(ah, 0xa3d8,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
@@ -1420,7 +4100,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 6 (LSB), 7, 12, 13 (MSB) */
-        REG_WRITE(ah, 0xa3dc,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
@@ -1428,7 +4108,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 14 (LSB), 15, 20, 21 */
-        REG_WRITE(ah, 0xa3ec,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
@@ -1558,22 +4238,9 @@ static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
                                               is2GHz) + ht40PowerIncForPdadc;
 
-        while (i < ar9300RateSize) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
-                i++;
+        for (i = 0; i < ar9300RateSize; i++) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
         }
 }
 
@@ -1592,18 +4259,17 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
         struct ath_common *common = ath9k_hw_common(ah);
 
         if (ichain >= AR9300_MAX_CHAINS) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Invalid chain index, must be less than %d\n",
-                          AR9300_MAX_CHAINS);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Invalid chain index, must be less than %d\n",
+                        AR9300_MAX_CHAINS);
                 return -1;
         }
 
         if (mode) {             /* 5GHz */
                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Invalid 5GHz cal pier index, must "
-                                  "be less than %d\n",
-                                  AR9300_NUM_5G_CAL_PIERS);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Invalid 5GHz cal pier index, must be less than %d\n",
+                                AR9300_NUM_5G_CAL_PIERS);
                         return -1;
                 }
                 pCalPier = &(eep->calFreqPier5G[ipier]);
@@ -1611,9 +4277,9 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
                 is2GHz = 0;
         } else {
                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Invalid 2GHz cal pier index, must "
-                                  "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Invalid 2GHz cal pier index, must be less than %d\n",
+                                AR9300_NUM_2G_CAL_PIERS);
                         return -1;
                 }
 
@@ -1637,27 +4303,32 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
 {
         int tempSlope = 0;
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        int f[3], t[3];
 
         REG_RMW(ah, AR_PHY_TPC_11_B0,
                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                 AR_PHY_TPC_OLPC_GAIN_DELTA);
-        REG_RMW(ah, AR_PHY_TPC_11_B1,
-                (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-                AR_PHY_TPC_OLPC_GAIN_DELTA);
-        REG_RMW(ah, AR_PHY_TPC_11_B2,
-                (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-                AR_PHY_TPC_OLPC_GAIN_DELTA);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW(ah, AR_PHY_TPC_11_B1,
+                        (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                        AR_PHY_TPC_OLPC_GAIN_DELTA);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW(ah, AR_PHY_TPC_11_B2,
+                        (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                        AR_PHY_TPC_OLPC_GAIN_DELTA);
 
         /* enable open loop power control on chip */
         REG_RMW(ah, AR_PHY_TPC_6_B0,
                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                 AR_PHY_TPC_6_ERROR_EST_MODE);
-        REG_RMW(ah, AR_PHY_TPC_6_B1,
-                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-                AR_PHY_TPC_6_ERROR_EST_MODE);
-        REG_RMW(ah, AR_PHY_TPC_6_B2,
-                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-                AR_PHY_TPC_6_ERROR_EST_MODE);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW(ah, AR_PHY_TPC_6_B1,
+                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                        AR_PHY_TPC_6_ERROR_EST_MODE);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW(ah, AR_PHY_TPC_6_B2,
+                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                        AR_PHY_TPC_6_ERROR_EST_MODE);
 
         /*
          * enable temperature compensation
@@ -1665,7 +4336,16 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
          */
         if (frequency < 4000)
                 tempSlope = eep->modalHeader2G.tempSlope;
-        else
+        else if (eep->base_ext2.tempSlopeLow != 0) {
+                t[0] = eep->base_ext2.tempSlopeLow;
+                f[0] = 5180;
+                t[1] = eep->modalHeader5G.tempSlope;
+                f[1] = 5500;
+                t[2] = eep->base_ext2.tempSlopeHigh;
+                f[2] = 5785;
+                tempSlope = ar9003_hw_power_interpolate((s32) frequency,
+                                                        f, t, 3);
+        } else
                 tempSlope = eep->modalHeader5G.tempSlope;
 
         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
@@ -1753,11 +4433,11 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
 
         /* interpolate  */
         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "ch=%d f=%d low=%d %d h=%d %d\n",
-                          ichain, frequency, lfrequency[ichain],
-                          lcorrection[ichain], hfrequency[ichain],
-                          hcorrection[ichain]);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "ch=%d f=%d low=%d %d h=%d %d\n",
+                        ichain, frequency, lfrequency[ichain],
+                        lcorrection[ichain], hfrequency[ichain],
+                        hcorrection[ichain]);
                 /* they're the same, so just pick one */
                 if (hfrequency[ichain] == lfrequency[ichain]) {
                         correction[ichain] = lcorrection[ichain];
@@ -1769,25 +4449,23 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
                         /* so is the high frequency, interpolate */
                         if (hfrequency[ichain] - frequency < 1000) {
 
-                                correction[ichain] = lcorrection[ichain] +
-                                    (((frequency - lfrequency[ichain]) *
-                                      (hcorrection[ichain] -
-                                       lcorrection[ichain])) /
-                                     (hfrequency[ichain] - lfrequency[ichain]));
-
-                                temperature[ichain] = ltemperature[ichain] +
-                                    (((frequency - lfrequency[ichain]) *
-                                      (htemperature[ichain] -
-                                       ltemperature[ichain])) /
-                                     (hfrequency[ichain] - lfrequency[ichain]));
-
-                                voltage[ichain] =
-                                    lvoltage[ichain] +
-                                    (((frequency -
-                                       lfrequency[ichain]) * (hvoltage[ichain] -
-                                                              lvoltage[ichain]))
-                                     / (hfrequency[ichain] -
-                                        lfrequency[ichain]));
+                                correction[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                lcorrection[ichain],
+                                                hcorrection[ichain]);
+
+                                temperature[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                ltemperature[ichain],
+                                                htemperature[ichain]);
+
+                                voltage[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                lvoltage[ichain],
+                                                hvoltage[ichain]);
                         }
                         /* only low is good, use it */
                         else {
@@ -1811,9 +4489,9 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
                                          temperature);
 
-        ath_print(common, ATH_DBG_EEPROM,
-                  "for frequency=%d, calibration correction = %d %d %d\n",
-                  frequency, correction[0], correction[1], correction[2]);
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "for frequency=%d, calibration correction = %d %d %d\n",
+                frequency, correction[0], correction[1], correction[2]);
 
         return 0;
 }
@@ -1827,9 +4505,9 @@ static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
 
         if (is2GHz)
-                return ctl_2g[idx].ctlEdges[edge].tPower;
+                return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
         else
-                return ctl_5g[idx].ctlEdges[edge].tPower;
+                return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
 }
 
 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
@@ -1847,15 +4525,15 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
 
         if (is2GHz) {
                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
-                    ctl_2g[idx].ctlEdges[edge - 1].flag)
-                        return ctl_2g[idx].ctlEdges[edge - 1].tPower;
+                    CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
+                        return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
         } else {
                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
-                    ctl_5g[idx].ctlEdges[edge - 1].flag)
-                        return ctl_5g[idx].ctlEdges[edge - 1].tPower;
+                    CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
+                        return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
         }
 
-        return AR9300_MAX_RATE_POWER;
+        return MAX_RATE_POWER;
 }
 
 /*
@@ -1864,7 +4542,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
                                         u16 freq, int idx, bool is2GHz)
 {
-        u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         u8 *ctl_freqbin = is2GHz ?
                 &eep->ctl_freqbin_2G[idx][0] :
                 &eep->ctl_freqbin_5G[idx][0];
@@ -1874,7 +4552,7 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
 
         /* Get the edge power */
         for (edge = 0;
-             (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
+             (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
              edge++) {
                 /*
                  * If there's an exact channel match or an inband flag set
@@ -1912,21 +4590,23 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
-        u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] = {
-                0, 3, 6, 9, AR9300_MAX_RATE_POWER
+                0, 3, 6, 9, MAX_RATE_POWER
         };
         int i;
         int16_t  twiceLargestAntenna;
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11a[] = {
+        static const u16 ctlModesFor11a[] = {
                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
         };
-        u16 ctlModesFor11g[] = {
+        static const u16 ctlModesFor11g[] = {
                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
                 CTL_11G_EXT, CTL_2GHT40
         };
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         u8 *ctlIndex;
         u8 ctlNum;
@@ -1965,10 +4645,16 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         case 1:
                 break;
         case 2:
-                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         case 3:
-                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         }
 
@@ -2016,11 +4702,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                 else
                         freq = centers.ctl_center;
 
-                ath_print(common, ATH_DBG_REGULATORY,
-                          "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
-                          "EXT_ADDITIVE %d\n",
-                          ctlMode, numCtlModes, isHt40CtlMode,
-                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
+                ath_dbg(common, ATH_DBG_REGULATORY,
+                        "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
+                        ctlMode, numCtlModes, isHt40CtlMode,
+                        (pCtlMode[ctlMode] & EXT_ADDITIVE));
 
                 /* walk through each CTL index stored in EEPROM */
                 if (is2ghz) {
@@ -2032,12 +4717,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                 }
 
                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
-                        ath_print(common, ATH_DBG_REGULATORY,
-                                  "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
-                                  "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
-                                  "chan %dn",
-                                  i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
-                                  chan->channel);
+                        ath_dbg(common, ATH_DBG_REGULATORY,
+                                "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
+                                i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
+                                chan->channel);
 
                                 /*
                                  * compare test group from regulatory
@@ -2076,11 +4759,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
 
                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 
-                        ath_print(common, ATH_DBG_REGULATORY,
-                                  "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
-                                  "sP %d minCtlPwr %d\n",
-                                  ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
-                                  scaledPower, minCtlPower);
+                        ath_dbg(common, ATH_DBG_REGULATORY,
+                                "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
+                                ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
+                                scaledPower, minCtlPower);
 
                         /* Apply ctl mode to correct target power set */
                         switch (pCtlMode[ctlMode]) {
@@ -2127,40 +4809,101 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         } /* end ctl mode checking */
 }
 
+static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
+{
+        u8 mod_idx = mcs_idx % 8;
+
+        if (mod_idx <= 3)
+                return mod_idx ? (base_pwridx + 1) : base_pwridx;
+        else
+                return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
+}
+
 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
                                         struct ath9k_channel *chan, u16 cfgCtl,
                                         u8 twiceAntennaReduction,
                                         u8 twiceMaxRegulatoryPower,
-                                        u8 powerLimit)
+                                        u8 powerLimit, bool test)
 {
+        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        struct ar9300_modal_eep_header *modal_hdr;
         u8 targetPowerValT2[ar9300RateSize];
-        unsigned int i = 0;
+        u8 target_power_val_t2_eep[ar9300RateSize];
+        unsigned int i = 0, paprd_scale_factor = 0;
+        u8 pwr_idx, min_pwridx = 0;
 
         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
+
+        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
+                if (IS_CHAN_2GHZ(chan))
+                        modal_hdr = &eep->modalHeader2G;
+                else
+                        modal_hdr = &eep->modalHeader5G;
+
+                ah->paprd_ratemask =
+                        le32_to_cpu(modal_hdr->papdRateMaskHt20) &
+                        AR9300_PAPRD_RATE_MASK;
+
+                ah->paprd_ratemask_ht40 =
+                        le32_to_cpu(modal_hdr->papdRateMaskHt40) &
+                        AR9300_PAPRD_RATE_MASK;
+
+                paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
+                min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
+                                                  ALL_TARGET_HT20_0_8_16;
+
+                if (!ah->paprd_table_write_done) {
+                        memcpy(target_power_val_t2_eep, targetPowerValT2,
+                               sizeof(targetPowerValT2));
+                        for (i = 0; i < 24; i++) {
+                                pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
+                                if (ah->paprd_ratemask & (1 << i)) {
+                                        if (targetPowerValT2[pwr_idx] &&
+                                            targetPowerValT2[pwr_idx] ==
+                                            target_power_val_t2_eep[pwr_idx])
+                                                targetPowerValT2[pwr_idx] -=
+                                                        paprd_scale_factor;
+                                }
+                        }
+                }
+                memcpy(target_power_val_t2_eep, targetPowerValT2,
+                       sizeof(targetPowerValT2));
+        }
+
         ar9003_hw_set_power_per_rate_table(ah, chan,
                                            targetPowerValT2, cfgCtl,
                                            twiceAntennaReduction,
                                            twiceMaxRegulatoryPower,
                                            powerLimit);
 
-        while (i < ar9300RateSize) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
-                i++;
+        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
+                for (i = 0; i < ar9300RateSize; i++) {
+                        if ((ah->paprd_ratemask & (1 << i)) &&
+                            (abs(targetPowerValT2[i] -
+                                target_power_val_t2_eep[i]) >
+                            paprd_scale_factor)) {
+                                ah->paprd_ratemask &= ~(1 << i);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "paprd disabled for mcs %d\n", i);
+                        }
+                }
         }
 
-        /* Write target power array to registers */
-        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
+        regulatory->max_power_level = 0;
+        for (i = 0; i < ar9300RateSize; i++) {
+                if (targetPowerValT2[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = targetPowerValT2[i];
+        }
+
+        if (test)
+                return;
+
+        for (i = 0; i < ar9300RateSize; i++) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
+        }
 
         /*
          * This is the TX power we send back to driver core,
@@ -2180,8 +4923,24 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
                 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
 
         ah->txpower_limit = targetPowerValT2[i];
+        regulatory->max_power_level = targetPowerValT2[i];
 
+        /* Write target power array to registers */
+        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
         ar9003_hw_calibration_apply(ah, chan->channel);
+
+        if (IS_CHAN_2GHZ(chan)) {
+                if (IS_CHAN_HT40(chan))
+                        i = ALL_TARGET_HT40_0_8_16;
+                else
+                        i = ALL_TARGET_HT20_0_8_16;
+        } else {
+                if (IS_CHAN_HT40(chan))
+                        i = ALL_TARGET_HT40_7;
+                else
+                        i = ALL_TARGET_HT20_7;
+        }
+        ah->paprd_target_power = targetPowerValT2[i];
 }
 
 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
@@ -2204,14 +4963,43 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
 }
 
+u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (is_2ghz)
+                return eep->modalHeader2G.spurChans;
+        else
+                return eep->modalHeader5G.spurChans;
+}
+
+unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+                                           struct ath9k_channel *chan)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (IS_CHAN_2GHZ(chan))
+                return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
+                          AR9300_PAPRD_SCALE_1);
+        else {
+                if (chan->channel >= 5700)
+                return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
+                          AR9300_PAPRD_SCALE_1);
+                else if (chan->channel >= 5400)
+                        return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
+                                   AR9300_PAPRD_SCALE_2);
+                else
+                        return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
+                                  AR9300_PAPRD_SCALE_1);
+        }
+}
+
 const struct eeprom_ops eep_ar9300_ops = {
         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
-        .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
         .set_board_values = ath9k_hw_ar9300_set_board_values,
         .set_addac = ath9k_hw_ar9300_set_addac,
         .set_txpower = ath9k_hw_ar9300_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 3c533bb983c7..ab21a4915981 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
 #ifndef AR9003_EEPROM_H
 #define AR9003_EEPROM_H
 
@@ -20,47 +36,22 @@
 /* #define AR9300_NUM_CTLS              21 */
 #define AR9300_NUM_CTLS_5G           9
 #define AR9300_NUM_CTLS_2G           12
-#define AR9300_CTL_MODE_M            0xF
 #define AR9300_NUM_BAND_EDGES_5G     8
 #define AR9300_NUM_BAND_EDGES_2G     4
-#define AR9300_NUM_PD_GAINS          4
-#define AR9300_PD_GAINS_IN_MASK      4
-#define AR9300_PD_GAIN_ICEPTS        5
-#define AR9300_EEPROM_MODAL_SPURS    5
-#define AR9300_MAX_RATE_POWER        63
-#define AR9300_NUM_PDADC_VALUES      128
-#define AR9300_NUM_RATES             16
-#define AR9300_BCHAN_UNUSED          0xFF
-#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
-#define AR9300_OPFLAGS_11A           0x01
-#define AR9300_OPFLAGS_11G           0x02
-#define AR9300_OPFLAGS_5G_HT40       0x04
-#define AR9300_OPFLAGS_2G_HT40       0x08
-#define AR9300_OPFLAGS_5G_HT20       0x10
-#define AR9300_OPFLAGS_2G_HT20       0x20
 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
 #define AR9300_EEPMISC_WOW           0x02
 #define AR9300_CUSTOMER_DATA_SIZE    20
 
-#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
 #define AR9300_MAX_CHAINS            3
 #define AR9300_ANT_16S               25
 #define AR9300_FUTURE_MODAL_SZ       6
 
-#define AR9300_NUM_ANT_CHAIN_FIELDS     7
-#define AR9300_NUM_ANT_COMMON_FIELDS    4
-#define AR9300_SIZE_ANT_CHAIN_FIELD     3
-#define AR9300_SIZE_ANT_COMMON_FIELD    4
-#define AR9300_ANT_CHAIN_MASK           0x7
-#define AR9300_ANT_COMMON_MASK          0xf
-#define AR9300_CHAIN_0_IDX              0
-#define AR9300_CHAIN_1_IDX              1
-#define AR9300_CHAIN_2_IDX              2
-
-#define AR928X_NUM_ANT_CHAIN_FIELDS     6
-#define AR928X_SIZE_ANT_CHAIN_FIELD     2
-#define AR928X_ANT_CHAIN_MASK           0x3
+#define AR9300_PAPRD_RATE_MASK          0x01ffffff
+#define AR9300_PAPRD_SCALE_1            0x0e000000
+#define AR9300_PAPRD_SCALE_1_S          25
+#define AR9300_PAPRD_SCALE_2            0x70000000
+#define AR9300_PAPRD_SCALE_2_S          28
 
 /* Delta from which to start power to pdadc table */
 /* This offset is used in both open loop and closed loop power control
@@ -71,14 +62,20 @@
  */
 #define AR9300_PWR_TABLE_OFFSET  0
 
-/* enable flags for voltage and temp compensation */
-#define ENABLE_TEMP_COMPENSATION 0x01
-#define ENABLE_VOLT_COMPENSATION 0x02
 /* byte addressable */
 #define AR9300_EEPROM_SIZE (16*1024)
-#define FIXED_CCA_THRESHOLD 15
 
+#define AR9300_BASE_ADDR_4K 0xfff
 #define AR9300_BASE_ADDR 0x3ff
+#define AR9300_BASE_ADDR_512 0x1ff
+
+#define AR9300_OTP_BASE                 0x14000
+#define AR9300_OTP_STATUS               0x15f18
+#define AR9300_OTP_STATUS_TYPE          0x7
+#define AR9300_OTP_STATUS_VALID         0x4
+#define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
+#define AR9300_OTP_STATUS_SM_BUSY       0x1
+#define AR9300_OTP_READ_DATA            0x15f1c
 
 enum targetPowerHTRates {
         HT_TARGET_RATE_0_8_16,
@@ -216,7 +213,7 @@ struct ar9300_modal_eep_header {
         int8_t tempSlope;
         int8_t voltSlope;
         /* spur channels in usual fbin coding format */
-        u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
+        u8 spurChans[AR_EEPROM_MODAL_SPURS];
         /* 3  Check if the register is per chain */
         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
         u8 ob[AR9300_MAX_CHAINS];
@@ -236,7 +233,7 @@ struct ar9300_modal_eep_header {
         u8 thresh62;
         __le32 papdRateMaskHt20;
         __le32 papdRateMaskHt40;
-        u8 futureModal[24];
+        u8 futureModal[10];
 } __packed;
 
 struct ar9300_cal_data_per_freq_op_loop {
@@ -261,17 +258,26 @@ struct cal_tgt_pow_ht {
         u8 tPow2x[14];
 } __packed;
 
-struct cal_ctl_edge_pwr {
-        u8 tPower:6,
-           flag:2;
-} __packed;
-
 struct cal_ctl_data_2g {
-        struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_2G];
+        u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
 } __packed;
 
 struct cal_ctl_data_5g {
-        struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+        u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+} __packed;
+
+struct ar9300_BaseExtension_1 {
+        u8 ant_div_control;
+        u8 future[13];
+} __packed;
+
+struct ar9300_BaseExtension_2 {
+        int8_t    tempSlopeLow;
+        int8_t    tempSlopeHigh;
+        u8   xatten1DBLow[AR9300_MAX_CHAINS];
+        u8   xatten1MarginLow[AR9300_MAX_CHAINS];
+        u8   xatten1DBHigh[AR9300_MAX_CHAINS];
+        u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
 } __packed;
 
 struct ar9300_eeprom {
@@ -283,6 +289,7 @@ struct ar9300_eeprom {
         struct ar9300_base_eep_hdr baseEepHeader;
 
         struct ar9300_modal_eep_header modalHeader2G;
+        struct ar9300_BaseExtension_1 base_ext1;
         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
         struct ar9300_cal_data_per_freq_op_loop
          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
@@ -302,6 +309,7 @@ struct ar9300_eeprom {
         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
         struct ar9300_modal_eep_header modalHeader5G;
+        struct ar9300_BaseExtension_2 base_ext2;
         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
         struct ar9300_cal_data_per_freq_op_loop
          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
@@ -322,4 +330,8 @@ struct ar9300_eeprom {
 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
 
+u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
+
+unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+                                           struct ath9k_channel *chan);
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 064168909108..392bf0f8ff16 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,174 +16,203 @@
 
 #include "hw.h"
 #include "ar9003_mac.h"
-#include "ar9003_2p0_initvals.h"
 #include "ar9003_2p2_initvals.h"
+#include "ar9485_initvals.h"
+#include "ar9340_initvals.h"
 
 /* General hardware code for the AR9003 hadware family */
 
-static bool ar9003_hw_macversion_supported(u32 macversion)
-{
-        switch (macversion) {
-        case AR_SREV_VERSION_9300:
-                return true;
-        default:
-                break;
-        }
-        return false;
-}
-
-/* AR9003 2.0 */
-static void ar9003_2p0_hw_init_mode_regs(struct ath_hw *ah)
-{
-        /* mac */
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ar9300_2p0_mac_core,
-                       ARRAY_SIZE(ar9300_2p0_mac_core), 2);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
-                       ar9300_2p0_mac_postamble,
-                       ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
-
-        /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
-                       ar9300_2p0_baseband_core,
-                       ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
-                       ar9300_2p0_baseband_postamble,
-                       ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
-
-        /* radio */
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
-                       ar9300_2p0_radio_core,
-                       ARRAY_SIZE(ar9300_2p0_radio_core), 2);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
-                       ar9300_2p0_radio_postamble,
-                       ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
-
-        /* soc */
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-                       ar9300_2p0_soc_preamble,
-                       ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
-                       ar9300_2p0_soc_postamble,
-                       ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
-
-        /* rx/tx gain */
-        INIT_INI_ARRAY(&ah->iniModesRxGain,
-                       ar9300Common_rx_gain_table_2p0,
-                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
-        INIT_INI_ARRAY(&ah->iniModesTxGain,
-                       ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
-                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
-                       5);
-
-        /* Load PCIE SERDES settings from INI */
-
-        /* Awake Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                       ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
-                       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
-                       2);
-
-        /* Sleep Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                       ar9300PciePhy_clkreq_enable_L1_2p0,
-                       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
-                       2);
-
-        /* Fast clock modal settings */
-        INIT_INI_ARRAY(&ah->iniModesAdditional,
-                       ar9300Modes_fast_clock_2p0,
-                       ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
-                       3);
-}
-
-/* AR9003 2.2 */
-static void ar9003_2p2_hw_init_mode_regs(struct ath_hw *ah)
-{
-        /* mac */
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ar9300_2p2_mac_core,
-                       ARRAY_SIZE(ar9300_2p2_mac_core), 2);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
-                       ar9300_2p2_mac_postamble,
-                       ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
-
-        /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
-                       ar9300_2p2_baseband_core,
-                       ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
-                       ar9300_2p2_baseband_postamble,
-                       ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
-
-        /* radio */
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
-                       ar9300_2p2_radio_core,
-                       ARRAY_SIZE(ar9300_2p2_radio_core), 2);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
-                       ar9300_2p2_radio_postamble,
-                       ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
-
-        /* soc */
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-                       ar9300_2p2_soc_preamble,
-                       ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
-                       ar9300_2p2_soc_postamble,
-                       ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
-
-        /* rx/tx gain */
-        INIT_INI_ARRAY(&ah->iniModesRxGain,
-                       ar9300Common_rx_gain_table_2p2,
-                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
-        INIT_INI_ARRAY(&ah->iniModesTxGain,
-                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
-                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
-                       5);
-
-        /* Load PCIE SERDES settings from INI */
-
-        /* Awake Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                       ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
-                       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
-                       2);
-
-        /* Sleep Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                       ar9300PciePhy_clkreq_enable_L1_2p2,
-                       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
-                       2);
-
-        /* Fast clock modal settings */
-        INIT_INI_ARRAY(&ah->iniModesAdditional,
-                       ar9300Modes_fast_clock_2p2,
-                       ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
-                       3);
-}
-
 /*
  * The AR9003 family uses a new INI format (pre, core, post
- * arrays per subsystem).
+ * arrays per subsystem). This provides support for the
+ * AR9003 2.2 chipsets.
  */
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-        if (AR_SREV_9300_20(ah))
-                ar9003_2p0_hw_init_mode_regs(ah);
-        else
-                ar9003_2p2_hw_init_mode_regs(ah);
+        if (AR_SREV_9340(ah)) {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9340_1p0_mac_core,
+                                ARRAY_SIZE(ar9340_1p0_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9340_1p0_mac_postamble,
+                                ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9340_1p0_baseband_core,
+                                ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9340_1p0_baseband_postamble,
+                                ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9340_1p0_radio_core,
+                                ARRAY_SIZE(ar9340_1p0_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9340_1p0_radio_postamble,
+                                ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9340_1p0_soc_preamble,
+                                ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ar9340_1p0_soc_postamble,
+                                ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9340Common_wo_xlna_rx_gain_table_1p0,
+                                ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+                                5);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9340Modes_high_ob_db_tx_gain_table_1p0,
+                                ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+                                5);
+
+                INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                ar9340Modes_fast_clock_1p0,
+                                ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
+                                3);
+
+                INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
+                                ar9340_1p0_radio_core_40M,
+                                ARRAY_SIZE(ar9340_1p0_radio_core_40M),
+                                2);
+        } else if (AR_SREV_9485_11(ah)) {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9485_1_1_mac_core,
+                                ARRAY_SIZE(ar9485_1_1_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9485_1_1_mac_postamble,
+                                ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
+                                ARRAY_SIZE(ar9485_1_1), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9485_1_1_baseband_core,
+                                ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9485_1_1_baseband_postamble,
+                                ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9485_1_1_radio_core,
+                                ARRAY_SIZE(ar9485_1_1_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9485_1_1_radio_postamble,
+                                ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9485_1_1_soc_preamble,
+                                ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9485Common_wo_xlna_rx_gain_1_1,
+                                ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9485_modes_lowest_ob_db_tx_gain_1_1,
+                                ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+                                5);
+
+                /* Load PCIE SERDES settings from INI */
+
+                /* Awake Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9485_1_1_pcie_phy_clkreq_disable_L1,
+                                ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+                                2);
+
+                /* Sleep Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9485_1_1_pcie_phy_clkreq_disable_L1,
+                                ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+                                2);
+        } else {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9300_2p2_mac_core,
+                                ARRAY_SIZE(ar9300_2p2_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9300_2p2_mac_postamble,
+                                ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9300_2p2_baseband_core,
+                                ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9300_2p2_baseband_postamble,
+                                ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9300_2p2_radio_core,
+                                ARRAY_SIZE(ar9300_2p2_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9300_2p2_radio_postamble,
+                                ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9300_2p2_soc_preamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ar9300_2p2_soc_postamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9300Common_rx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+                                5);
+
+                /* Load PCIE SERDES settings from INI */
+
+                /* Awake Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                2);
+
+                /* Sleep Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                2);
+
+                /* Fast clock modal settings */
+                INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                ar9300Modes_fast_clock_2p2,
+                                ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+                                3);
+        }
 }
 
 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
@@ -191,10 +220,15 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
         switch (ar9003_hw_get_tx_gain_idx(ah)) {
         case 0:
         default:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
-                                       ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
+                                       ar9485_modes_lowest_ob_db_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
                                        5);
                 else
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -203,10 +237,15 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                        5);
                 break;
         case 1:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
-                                       ar9300Modes_high_ob_db_tx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
+                                       ar9485Modes_high_ob_db_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
                                        5);
                 else
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -215,10 +254,15 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                        5);
                 break;
         case 2:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
-                                       ar9300Modes_low_ob_db_tx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
+                                       ar9485Modes_low_ob_db_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
                                        5);
                 else
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -226,6 +270,23 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                        ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
                                        5);
                 break;
+        case 3:
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9485Modes_high_power_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
+                                       5);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9300Modes_high_power_tx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
+                                       5);
+                break;
         }
 }
 
@@ -234,10 +295,15 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
         switch (ar9003_hw_get_rx_gain_idx(ah)) {
         case 0:
         default:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9340Common_rx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
+                                       2);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
-                                       ar9300Common_rx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
+                                       ar9485Common_wo_xlna_rx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
                                        2);
                 else
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -246,10 +312,15 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
                                        2);
                 break;
         case 1:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9340Common_wo_xlna_rx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+                                       2);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
-                                       ar9300Common_wo_xlna_rx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
+                                       ar9485Common_wo_xlna_rx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
                                        2);
                 else
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -326,13 +397,10 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
 
         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
-        priv_ops->macversion_supported = ar9003_hw_macversion_supported;
 
         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 
         ar9003_hw_attach_phy_ops(ah);
         ar9003_hw_attach_calib_ops(ah);
         ar9003_hw_attach_mac_ops(ah);
-
-        ath9k_hw_attach_ani_ops_new(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 5b995bee70ae..10d71f7d3fc2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -182,10 +182,10 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 }
 
                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
 
-                        REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
+                REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 
         }
@@ -237,73 +237,76 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                  struct ath_tx_status *ts)
 {
         struct ar9003_txs *ads;
+        u32 status;
 
         ads = &ah->ts_ring[ah->ts_tail];
 
-        if ((ads->status8 & AR_TxDone) == 0)
+        status = ACCESS_ONCE(ads->status8);
+        if ((status & AR_TxDone) == 0)
                 return -EINPROGRESS;
 
         ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
 
         if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
             (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                          "Tx Descriptor error %x\n", ads->ds_info);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                        "Tx Descriptor error %x\n", ads->ds_info);
                 memset(ads, 0, sizeof(*ads));
                 return -EIO;
         }
 
+        if (status & AR_TxOpExceeded)
+                ts->ts_status |= ATH9K_TXERR_XTXOP;
+        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
+        ts->ts_seqnum = MS(status, AR_SeqNum);
+        ts->tid = MS(status, AR_TxTid);
+
         ts->qid = MS(ads->ds_info, AR_TxQcuNum);
         ts->desc_id = MS(ads->status1, AR_TxDescId);
-        ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
         ts->ts_tstamp = ads->status4;
         ts->ts_status = 0;
         ts->ts_flags  = 0;
 
-        if (ads->status3 & AR_ExcessiveRetries)
+        status = ACCESS_ONCE(ads->status2);
+        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
+        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
+        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
+        if (status & AR_TxBaStatus) {
+                ts->ts_flags |= ATH9K_TX_BA;
+                ts->ba_low = ads->status5;
+                ts->ba_high = ads->status6;
+        }
+
+        status = ACCESS_ONCE(ads->status3);
+        if (status & AR_ExcessiveRetries)
                 ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->status3 & AR_Filtered)
+        if (status & AR_Filtered)
                 ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->status3 & AR_FIFOUnderrun) {
+        if (status & AR_FIFOUnderrun) {
                 ts->ts_status |= ATH9K_TXERR_FIFO;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status8 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->status3 & AR_TxTimerExpired)
+        if (status & AR_TxTimerExpired)
                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->status3 & AR_DescCfgErr)
+        if (status & AR_DescCfgErr)
                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->status3 & AR_TxDataUnderrun) {
+        if (status & AR_TxDataUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status3 & AR_TxDelimUnderrun) {
+        if (status & AR_TxDelimUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status2 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->status5;
-                ts->ba_high = ads->status6;
-        }
-
-        ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
-
-        ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
-        ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
-        ts->ts_antenna = 0;
+        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
+        ts->ts_longretry = MS(status, AR_DataFailCnt);
+        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
-        ts->tid = MS(ads->status8, AR_TxTid);
+        status = ACCESS_ONCE(ads->status7);
+        ts->ts_rssi = MS(status, AR_TxRSSICombined);
+        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
+        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
+        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
         memset(ads, 0, sizeof(*ads));
 
@@ -319,7 +322,6 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         if (txpower > ah->txpower_limit)
                 txpower = ah->txpower_limit;
 
-        txpower += ah->txpower_indexoffset;
         if (txpower > 63)
                 txpower = 63;
 
@@ -327,7 +329,6 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
                 | SM(txpower, AR_XmitPower)
                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
-                | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
                 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
 
@@ -348,6 +349,16 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         ads->ctl22 = 0;
 }
 
+static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
+{
+        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
+
+        if (val)
+                ads->ctl11 |= AR_ClrDestMask;
+        else
+                ads->ctl11 &= ~AR_ClrDestMask;
+}
+
 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
                                           void *lastds,
                                           u32 durUpdateEn, u32 rtsctsRate,
@@ -407,12 +418,36 @@ static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
                                         u32 aggrLen)
 {
+#define FIRST_DESC_NDELIMS 60
         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
 
         ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
 
-        ads->ctl17 &= ~AR_AggrLen;
-        ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+        if (ah->ent_mode & AR_ENT_OTP_MPSD) {
+                u32 ctl17, ndelim;
+                /*
+                 * Add delimiter when using RTS/CTS with aggregation
+                 * and non enterprise AR9003 card
+                 */
+                ctl17 = ads->ctl17;
+                ndelim = MS(ctl17, AR_PadDelim);
+
+                if (ndelim < FIRST_DESC_NDELIMS) {
+                        aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
+                        ndelim = FIRST_DESC_NDELIMS;
+                }
+
+                ctl17 &= ~AR_AggrLen;
+                ctl17 |= SM(aggrLen, AR_AggrLen);
+
+                ctl17 &= ~AR_PadDelim;
+                ctl17 |= SM(ndelim, AR_PadDelim);
+
+                ads->ctl17 = ctl17;
+        } else {
+                ads->ctl17 &= ~AR_AggrLen;
+                ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+        }
 }
 
 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
@@ -449,27 +484,6 @@ static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
         ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
 }
 
-static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
-                                           u32 burstDuration)
-{
-        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
-
-        ads->ctl13 &= ~AR_BurstDur;
-        ads->ctl13 |= SM(burstDuration, AR_BurstDur);
-
-}
-
-static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
-                                             u32 vmf)
-{
-        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
-
-        if (vmf)
-                ads->ctl11 |=  AR_VirtMoreFrag;
-        else
-                ads->ctl11 &= ~AR_VirtMoreFrag;
-}
-
 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
 {
         struct ar9003_txc *ads = ds;
@@ -494,8 +508,7 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
         ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
         ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
         ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
-        ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
-        ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
+        ops->set_clrdmask = ar9003_hw_set_clrdmask;
 }
 
 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
@@ -587,9 +600,9 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
                  * possibly be reviewing the last subframe. AR_CRCErr
                  * is the CRC of the actual data.
                  */
-                if (rxsp->status11 & AR_CRCErr) {
+                if (rxsp->status11 & AR_CRCErr)
                         rxs->rs_status |= ATH9K_RXERR_CRC;
-                } else if (rxsp->status11 & AR_PHYErr) {
+                else if (rxsp->status11 & AR_PHYErr) {
                         phyerr = MS(rxsp->status11, AR_PHYErrCode);
                         /*
                          * If we reach a point here where AR_PostDelimCRCErr is
@@ -612,11 +625,13 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
                                 rxs->rs_phyerr = phyerr;
                         }
 
-                } else if (rxsp->status11 & AR_DecryptCRCErr) {
+                } else if (rxsp->status11 & AR_DecryptCRCErr)
                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
-                } else if (rxsp->status11 & AR_MichaelErr) {
+                else if (rxsp->status11 & AR_MichaelErr)
                         rxs->rs_status |= ATH9K_RXERR_MIC;
-                }
+
+                if (rxsp->status11 & AR_KeyMiss)
+                        rxs->rs_status |= ATH9K_RXERR_DECRYPT;
         }
 
         return 0;
@@ -630,10 +645,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
         memset((void *) ah->ts_ring, 0,
                 ah->ts_size * sizeof(struct ar9003_txs));
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                  "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
-                   ah->ts_paddr_start, ah->ts_paddr_end,
-                   ah->ts_ring, ah->ts_size);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
+                ah->ts_paddr_start, ah->ts_paddr_end,
+                ah->ts_ring, ah->ts_size);
 
         REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
         REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
index 9f2cea70a840..c50449387bf1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -65,7 +65,7 @@ struct ar9003_rxs {
         u32 status9;
         u32 status10;
         u32 status11;
-} __packed;
+} __packed __aligned(4);
 
 /* Transmit Control Descriptor */
 struct ar9003_txc {
@@ -93,7 +93,7 @@ struct ar9003_txc {
         u32 ctl21;  /* DMA control 21 */
         u32 ctl22;  /* DMA control 22 */
         u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
-} __packed;
+} __packed __aligned(4);
 
 struct ar9003_txs {
         u32 ds_info;
@@ -105,7 +105,7 @@ struct ar9003_txs {
         u32 status6;
         u32 status7;
         u32 status8;
-} __packed;
+} __packed __aligned(4);
 
 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 7c38229ba670..e4d6a87ec538 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,45 +19,124 @@
 
 void ar9003_paprd_enable(struct ath_hw *ah, bool val)
 {
+        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+        struct ath9k_channel *chan = ah->curchan;
+
+        if (val) {
+                ah->paprd_table_write_done = true;
+
+                ah->eep_ops->set_txpower(ah, chan,
+                                ath9k_regd_get_ctl(regulatory, chan),
+                                chan->chan->max_antenna_gain * 2,
+                                chan->chan->max_power * 2,
+                                min((u32) MAX_RATE_POWER,
+                                (u32) regulatory->power_limit), false);
+        }
+
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
                       AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
-                      AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
-                      AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
+                              AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
+                              AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
 }
 EXPORT_SYMBOL(ar9003_paprd_enable);
 
-static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
+static int ar9003_get_training_power_2g(struct ath_hw *ah)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        struct ar9300_modal_eep_header *hdr = &eep->modalHeader2G;
+        unsigned int power, scale, delta;
+
+        scale = MS(le32_to_cpu(hdr->papdRateMaskHt20), AR9300_PAPRD_SCALE_1);
+        power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
+                               AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
+
+        delta = abs((int) ah->paprd_target_power - (int) power);
+        if (delta > scale)
+                return -1;
+
+        if (delta < 4)
+                power -= 4 - delta;
+
+        return power;
+}
+
+static int ar9003_get_training_power_5g(struct ath_hw *ah)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
-        struct ar9300_modal_eep_header *hdr;
-        const u32 ctrl0[3] = {
+        struct ar9300_modal_eep_header *hdr = &eep->modalHeader5G;
+        struct ath9k_channel *chan = ah->curchan;
+        unsigned int power, scale, delta;
+
+        if (chan->channel >= 5700)
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt20),
+                           AR9300_PAPRD_SCALE_1);
+        else if (chan->channel >= 5400)
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
+                           AR9300_PAPRD_SCALE_2);
+        else
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
+                           AR9300_PAPRD_SCALE_1);
+
+        if (IS_CHAN_HT40(chan))
+                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
+                        AR_PHY_POWERTX_RATE8_POWERTXHT40_5);
+        else
+                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE6,
+                        AR_PHY_POWERTX_RATE6_POWERTXHT20_5);
+
+        power += scale;
+        delta = abs((int) ah->paprd_target_power - (int) power);
+        if (delta > scale)
+                return -1;
+
+        power += 2 * get_streams(common->tx_chainmask);
+        return power;
+}
+
+static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        static const u32 ctrl0[3] = {
                 AR_PHY_PAPRD_CTRL0_B0,
                 AR_PHY_PAPRD_CTRL0_B1,
                 AR_PHY_PAPRD_CTRL0_B2
         };
-        const u32 ctrl1[3] = {
+        static const u32 ctrl1[3] = {
                 AR_PHY_PAPRD_CTRL1_B0,
                 AR_PHY_PAPRD_CTRL1_B1,
                 AR_PHY_PAPRD_CTRL1_B2
         };
-        u32 am_mask, ht40_mask;
+        int training_power;
         int i;
 
-        if (ah->curchan && IS_CHAN_5GHZ(ah->curchan))
-                hdr = &eep->modalHeader5G;
+        if (IS_CHAN_2GHZ(ah->curchan))
+                training_power = ar9003_get_training_power_2g(ah);
         else
-                hdr = &eep->modalHeader2G;
-
-        am_mask = le32_to_cpu(hdr->papdRateMaskHt20);
-        ht40_mask = le32_to_cpu(hdr->papdRateMaskHt40);
+                training_power = ar9003_get_training_power_5g(ah);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, am_mask);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
-
-        for (i = 0; i < 3; i++) {
+        if (training_power < 0) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "PAPRD target power delta out of range");
+                return -ERANGE;
+        }
+        ah->paprd_training_power = training_power;
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "Training power: %d, Target power: %d\n",
+                ah->paprd_training_power, ah->paprd_target_power);
+
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
+                      ah->paprd_ratemask);
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
+                      ah->paprd_ratemask);
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
+                      ah->paprd_ratemask_ht40);
+
+        for (i = 0; i < ah->caps.max_txchains; i++) {
                 REG_RMW_FIELD(ah, ctrl0[i],
                               AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1);
                 REG_RMW_FIELD(ah, ctrl1[i],
@@ -102,8 +181,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
-                      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6);
+        if (AR_SREV_9485(ah))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+                              AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+                              -3);
+        else
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+                              AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+                              -6);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
                       -15);
@@ -132,6 +217,7 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
                       AR_PHY_PAPRD_PRE_POST_SCALING, 185706);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
                       AR_PHY_PAPRD_PRE_POST_SCALING, 175487);
+        return 0;
 }
 
 static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
@@ -347,6 +433,10 @@ static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
             (((Y[6] - Y[3]) * 1 << scale_factor) +
              (x_est[6] - x_est[3])) / (x_est[6] - x_est[3]);
 
+        /* prevent division by zero */
+        if (G_fxp == 0)
+                return false;
+
         Y_intercept =
             (G_fxp * (x_est[0] - x_est[3]) +
              (1 << scale_factor)) / (1 << scale_factor) + Y[3];
@@ -356,14 +446,12 @@ static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
 
         for (i = 0; i <= 3; i++) {
                 y_est[i] = i * 32;
-
-                /* prevent division by zero */
-                if (G_fxp == 0)
-                        return false;
-
                 x_est[i] = ((y_est[i] * 1 << scale_factor) + G_fxp) / G_fxp;
         }
 
+        if (y_est[max_index] == 0)
+                return false;
+
         x_est_fxp1_nonlin =
             x_est[max_index] - ((1 << scale_factor) * y_est[max_index] +
                                 G_fxp) / G_fxp;
@@ -457,6 +545,8 @@ static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
 
         Q_scale_B = find_proper_scale(find_expn(abs(scale_B)), 10);
         scale_B = scale_B / (1 << Q_scale_B);
+        if (scale_B == 0)
+                return false;
         Q_beta = find_proper_scale(find_expn(abs(beta_raw)), 10);
         Q_alpha = find_proper_scale(find_expn(abs(alpha_raw)), 10);
         beta_raw = beta_raw / (1 << Q_beta);
@@ -582,15 +672,10 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
 {
         u32 *paprd_table_val = caldata->pa_table[chain];
         u32 small_signal_gain = caldata->small_signal_gain[chain];
-        u32 training_power;
+        u32 training_power = ah->paprd_training_power;
         u32 reg = 0;
         int i;
 
-        training_power =
-            REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
-                           AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
-        training_power -= 4;
-
         if (chain == 0)
                 reg = AR_PHY_PAPRD_MEM_TAB_B0;
         else if (chain == 1)
@@ -616,26 +701,22 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
                       AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
                       training_power);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
-                      AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
-                      training_power);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
+                              AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
+                              training_power);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
-                      AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
-                      training_power);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
+                              AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
+                              training_power);
 }
 EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
 
 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
 {
-
         unsigned int i, desired_gain, gain_index;
-        unsigned int train_power;
-
-        train_power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
-                                     AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
-
-        train_power = train_power - 4;
+        unsigned int train_power = ah->paprd_training_power;
 
         desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
 
@@ -701,7 +782,12 @@ EXPORT_SYMBOL(ar9003_paprd_create_curve);
 
 int ar9003_paprd_init_table(struct ath_hw *ah)
 {
-        ar9003_paprd_setup_single_table(ah);
+        int ret;
+
+        ret = ar9003_paprd_setup_single_table(ah);
+        if (ret < 0)
+            return ret;
+
         ar9003_paprd_get_gain_table(ah);
         return 0;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index a491854fa38a..892c48b15434 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -75,13 +75,42 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
         freq = centers.synth_center;
 
         if (freq < 4800) {     /* 2 GHz, fractional mode */
-                channelSel = CHANSEL_2G(freq);
+                if (AR_SREV_9485(ah)) {
+                        u32 chan_frac;
+
+                        /*
+                         * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
+                         * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
+                         * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
+                         */
+                        channelSel = (freq * 4) / 120;
+                        chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
+                        channelSel = (channelSel << 17) | chan_frac;
+                } else if (AR_SREV_9340(ah)) {
+                        if (ah->is_clk_25mhz) {
+                                u32 chan_frac;
+
+                                channelSel = (freq * 2) / 75;
+                                chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
+                                channelSel = (channelSel << 17) | chan_frac;
+                        } else
+                                channelSel = CHANSEL_2G(freq) >> 1;
+                } else
+                        channelSel = CHANSEL_2G(freq);
                 /* Set to 2G mode */
                 bMode = 1;
         } else {
-                channelSel = CHANSEL_5G(freq);
-                /* Doubler is ON, so, divide channelSel by 2. */
-                channelSel >>= 1;
+                if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
+                        u32 chan_frac;
+
+                        channelSel = (freq * 2) / 75;
+                        chan_frac = ((freq % 75) * 0x20000) / 75;
+                        channelSel = (channelSel << 17) | chan_frac;
+                } else {
+                        channelSel = CHANSEL_5G(freq);
+                        /* Doubler is ON, so, divide channelSel by 2. */
+                        channelSel >>= 1;
+                }
                 /* Set to 5G mode */
                 bMode = 0;
         }
@@ -128,24 +157,53 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
                                             struct ath9k_channel *chan)
 {
-        u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
+        static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
         int cur_bb_spur, negative = 0, cck_spur_freq;
         int i;
+        int range, max_spur_cnts, synth_freq;
+        u8 *spur_fbin_ptr = NULL;
 
         /*
          * Need to verify range +/- 10 MHz in control channel, otherwise spur
          * is out-of-band and can be ignored.
          */
 
-        for (i = 0; i < 4; i++) {
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
+                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
+                                                         IS_CHAN_2GHZ(chan));
+                if (spur_fbin_ptr[0] == 0) /* No spur */
+                        return;
+                max_spur_cnts = 5;
+                if (IS_CHAN_HT40(chan)) {
+                        range = 19;
+                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                                           AR_PHY_GC_DYN2040_PRI_CH) == 0)
+                                synth_freq = chan->channel + 10;
+                        else
+                                synth_freq = chan->channel - 10;
+                } else {
+                        range = 10;
+                        synth_freq = chan->channel;
+                }
+        } else {
+                range = 10;
+                max_spur_cnts = 4;
+                synth_freq = chan->channel;
+        }
+
+        for (i = 0; i < max_spur_cnts; i++) {
                 negative = 0;
-                cur_bb_spur = spur_freq[i] - chan->channel;
+                if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
+                                        IS_CHAN_2GHZ(chan)) - synth_freq;
+                else
+                        cur_bb_spur = spur_freq[i] - synth_freq;
 
                 if (cur_bb_spur < 0) {
                         negative = 1;
                         cur_bb_spur = -cur_bb_spur;
                 }
-                if (cur_bb_spur < 10) {
+                if (cur_bb_spur < range) {
                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 
                         if (negative == 1)
@@ -369,7 +427,7 @@ static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 
         ar9003_hw_spur_ofdm_clear(ah);
 
-        for (i = 0; spurChansPtr[i] && i < 5; i++) {
+        for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
                 if (abs(freq_offset) < range) {
                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
@@ -487,7 +545,11 @@ void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
                 break;
         }
 
-        REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+        if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
+                REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
+        else
+                REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+
         if (tx == 0x5) {
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                             AR_PHY_SWAP_ALT_CHAIN);
@@ -542,10 +604,7 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
                 u32 reg = INI_RA(iniArr, i, 0);
                 u32 val = INI_RA(iniArr, i, column);
 
-                if (reg >= 0x16000 && reg < 0x17000)
-                        ath9k_hw_analog_shift_regwrite(ah, reg, val);
-                else
-                        REG_WRITE(ah, reg, val);
+                REG_WRITE(ah, reg, val);
 
                 DO_DELAY(regWrites);
         }
@@ -557,29 +616,25 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         unsigned int regWrites = 0, i;
         struct ieee80211_channel *channel = chan->chan;
-        u32 modesIndex, freqIndex;
+        u32 modesIndex;
 
         switch (chan->chanmode) {
         case CHANNEL_A:
         case CHANNEL_A_HT20:
                 modesIndex = 1;
-                freqIndex = 1;
                 break;
         case CHANNEL_A_HT40PLUS:
         case CHANNEL_A_HT40MINUS:
                 modesIndex = 2;
-                freqIndex = 1;
                 break;
         case CHANNEL_G:
         case CHANNEL_G_HT20:
         case CHANNEL_B:
                 modesIndex = 4;
-                freqIndex = 2;
                 break;
         case CHANNEL_G_HT40PLUS:
         case CHANNEL_G_HT40MINUS:
                 modesIndex = 3;
-                freqIndex = 2;
                 break;
 
         default:
@@ -604,6 +659,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                 modesIndex, regWrites);
 
+        if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
+                REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
+
         ar9003_hw_override_ini(ah);
         ar9003_hw_set_channel_regs(ah, chan);
         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
@@ -614,7 +672,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), false);
 
         return 0;
 }
@@ -712,28 +770,6 @@ static void ar9003_hw_rfbus_done(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-/*
- * Set the interrupt and GPIO values so the ISR can disable RF
- * on a switch signal.  Assumes GPIO port and interrupt polarity
- * are set prior to call.
- */
-static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
-{
-        /* Connect rfsilent_bb_l to baseband */
-        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-        /* Set input mux for rfsilent_bb_l to GPIO #0 */
-        REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                    AR_GPIO_INPUT_MUX2_RFSILENT);
-
-        /*
-         * Configure the desired GPIO port for input and
-         * enable baseband rf silence.
-         */
-        ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-        REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 {
         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
@@ -747,9 +783,9 @@ static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                   enum ath9k_ani_cmd cmd, int param)
 {
-        struct ar5416AniState *aniState = ah->curani;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
+        struct ar5416AniState *aniState = &chan->ani;
         s32 value, value2;
 
         switch (cmd & ah->ani_function) {
@@ -820,12 +856,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                 if (!on != aniState->ofdmWeakSigDetectOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: ofdm weak signal: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->ofdmWeakSigDetectOff ?
-                                        "on" : "off",
-                                  on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: ofdm weak signal: %s=>%s\n",
+                                chan->channel,
+                                !aniState->ofdmWeakSigDetectOff ?
+                                "on" : "off",
+                                on ? "on" : "off");
                         if (on)
                                 ah->stats.ast_ani_ofdmon++;
                         else
@@ -838,11 +874,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_FIRSTEP_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep_table));
                         return false;
                 }
 
@@ -877,24 +911,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 
                 if (level != aniState->firstepLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.firstep);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep_low[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.firstepLow);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value,
+                                aniState->iniDef.firstep);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value2,
+                                aniState->iniDef.firstepLow);
                         if (level > aniState->firstepLevel)
                                 ah->stats.ast_ani_stepup++;
                         else if (level < aniState->firstepLevel)
@@ -907,11 +939,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1_table));
                         return false;
                 }
                 /*
@@ -945,24 +975,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                               AR_PHY_EXT_CYCPWR_THR1, value2);
 
                 if (level != aniState->spurImmunityLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.cycpwrThr1);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1Ext[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.cycpwrThr1Ext);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value,
+                                aniState->iniDef.cycpwrThr1);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value2,
+                                aniState->iniDef.cycpwrThr1Ext);
                         if (level > aniState->spurImmunityLevel)
                                 ah->stats.ast_ani_spurup++;
                         else if (level < aniState->spurImmunityLevel)
@@ -982,11 +1010,11 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
                               AR_PHY_MRC_CCK_MUX_REG, is_on);
                 if (!is_on != aniState->mrcCCKOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: MRC CCK: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->mrcCCKOff ? "on" : "off",
-                                  is_on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: MRC CCK: %s=>%s\n",
+                                chan->channel,
+                                !aniState->mrcCCKOff ? "on" : "off",
+                                is_on ? "on" : "off");
                 if (is_on)
                         ah->stats.ast_ani_ccklow++;
                 else
@@ -998,52 +1026,48 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                  "MRCcck=%s listenTime=%d CC=%d listen=%d "
-                  "ofdmErrs=%d cckErrs=%d\n",
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
-                  aniState->firstepLevel,
-                  !aniState->mrcCCKOff ? "on" : "off",
-                  aniState->listenTime,
-                  aniState->cycleCount,
-                  aniState->listenTime,
-                  aniState->ofdmPhyErrCount,
-                  aniState->cckPhyErrCount);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+                aniState->firstepLevel,
+                !aniState->mrcCCKOff ? "on" : "off",
+                aniState->listenTime,
+                aniState->ofdmPhyErrCount,
+                aniState->cckPhyErrCount);
         return true;
 }
 
 static void ar9003_hw_do_getnf(struct ath_hw *ah,
                               int16_t nfarray[NUM_NF_READINGS])
 {
-        int16_t nf;
-
-        nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+#define AR_PHY_CH_MINCCA_PWR    0x1FF00000
+#define AR_PHY_CH_MINCCA_PWR_S  20
+#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
+#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
 
-        nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
-
-        nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
-        nfarray[2] = sign_extend(nf, 9);
-
-        if (!IS_CHAN_HT40(ah->curchan))
-                return;
+        int16_t nf;
+        int i;
 
-        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-        nfarray[3] = sign_extend(nf, 9);
+        for (i = 0; i < AR9300_MAX_CHAINS; i++) {
+                if (ah->rxchainmask & BIT(i)) {
+                        nf = MS(REG_READ(ah, ah->nf_regs[i]),
+                                         AR_PHY_CH_MINCCA_PWR);
+                        nfarray[i] = sign_extend32(nf, 8);
 
-        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
-        nfarray[4] = sign_extend(nf, 9);
+                        if (IS_CHAN_HT40(ah->curchan)) {
+                                u8 ext_idx = AR9300_MAX_CHAINS + i;
 
-        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
-        nfarray[5] = sign_extend(nf, 9);
+                                nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
+                                                 AR_PHY_CH_EXT_MINCCA_PWR);
+                                nfarray[ext_idx] = sign_extend32(nf, 8);
+                        }
+                }
+        }
 }
 
 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
@@ -1067,21 +1091,18 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
         struct ath9k_ani_default *iniDef;
-        int index;
         u32 val;
 
-        index = ath9k_hw_get_ani_channel_idx(ah, chan);
-        aniState = &ah->ani[index];
-        ah->curani = aniState;
+        aniState = &ah->curchan->ani;
         iniDef = &aniState->iniDef;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
-                  ah->hw_version.macVersion,
-                  ah->hw_version.macRev,
-                  ah->opmode,
-                  chan->channel,
-                  chan->channelFlags);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+                ah->hw_version.macVersion,
+                ah->hw_version.macRev,
+                ah->opmode,
+                chan->channel,
+                chan->channelFlags);
 
         val = REG_READ(ah, AR_PHY_SFCORR);
         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1116,14 +1137,100 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
+}
+
+static void ar9003_hw_set_radar_params(struct ath_hw *ah,
+                                       struct ath_hw_radar_conf *conf)
+{
+        u32 radar_0 = 0, radar_1 = 0;
+
+        if (!conf) {
+                REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+                return;
+        }
+
+        radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+        radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+        radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+        radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+        radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+        radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+        radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+        radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+        radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+        radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+        radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+        REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+        REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+        if (conf->ext_channel)
+                REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+        else
+                REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
+{
+        struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+        conf->fir_power = -28;
+        conf->radar_rssi = 0;
+        conf->pulse_height = 10;
+        conf->pulse_rssi = 24;
+        conf->pulse_inband = 8;
+        conf->pulse_maxlen = 255;
+        conf->pulse_inband_step = 12;
+        conf->radar_inband = 8;
+}
+
+static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+        antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
+                                  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
+        antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
+                                 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
+        antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
+                                  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
+        antconf->lna1_lna2_delta = -9;
+        antconf->div_group = 2;
+}
 
-        aniState->cycleCount = 0;
+static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+        regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                    AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                    AR_PHY_9485_ANT_FAST_DIV_BIAS |
+                    AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
+                    AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+        regval |= ((antconf->main_lna_conf <<
+                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
+                   & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
+        regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
+                   & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
+        regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
+                   & AR_PHY_9485_ANT_FAST_DIV_BIAS);
+        regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
+                   & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
+        regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
+                   & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+
+        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 }
 
 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        const u32 ar9300_cca_regs[6] = {
+        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
+        static const u32 ar9300_cca_regs[6] = {
                 AR_PHY_CCA_0,
                 AR_PHY_CCA_1,
                 AR_PHY_CCA_2,
@@ -1143,13 +1250,17 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
-        priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
         priv_ops->set_diversity = ar9003_hw_set_diversity;
         priv_ops->ani_control = ar9003_hw_ani_control;
         priv_ops->do_getnf = ar9003_hw_do_getnf;
         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
+        priv_ops->set_radar_params = ar9003_hw_set_radar_params;
+
+        ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
+        ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
 
         ar9003_hw_set_nf_limits(ah);
+        ar9003_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
 }
 
@@ -1172,7 +1283,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
                             AR_PHY_WATCHDOG_IDLE_ENABLE));
 
-                ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
+                ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
                 return;
         }
 
@@ -1208,9 +1319,9 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
                   AR_PHY_WATCHDOG_IDLE_MASK |
                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
 
-        ath_print(common, ATH_DBG_RESET,
-                  "Enabled BB Watchdog timeout (%u ms)\n",
-                  idle_tmo_ms);
+        ath_dbg(common, ATH_DBG_RESET,
+                "Enabled BB Watchdog timeout (%u ms)\n",
+                idle_tmo_ms);
 }
 
 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
@@ -1232,42 +1343,63 @@ void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status;
+        u32 status;
 
         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
                 return;
 
         status = ah->bb_watchdog_last_status;
-        ath_print(common, ATH_DBG_RESET,
-                  "\n==== BB update: BB status=0x%08x ====\n", status);
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
-                  "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
-                  MS(status, AR_PHY_WATCHDOG_INFO),
-                  MS(status, AR_PHY_WATCHDOG_DET_HANG),
-                  MS(status, AR_PHY_WATCHDOG_RADAR_SM),
-                  MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
-                  MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
-                  MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
-                  MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
-                  MS(status, AR_PHY_WATCHDOG_AGC_SM),
-                  MS(status,AR_PHY_WATCHDOG_SRCH_SM));
-
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
-                  REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
-                  REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB mode: BB_gen_controls=0x%08x **\n",
-                  REG_READ(ah, AR_PHY_GEN_CTRL));
-
-        if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt))
-                ath_print(common, ATH_DBG_RESET,
-                          "** BB busy times: rx_clear=%d%%, "
-                          "rx_frame=%d%%, tx_frame=%d%% **\n",
-                          rxc_pcnt, rxf_pcnt, txf_pcnt);
-
-        ath_print(common, ATH_DBG_RESET,
-                  "==== BB update: done ====\n\n");
+        ath_dbg(common, ATH_DBG_RESET,
+                "\n==== BB update: BB status=0x%08x ====\n", status);
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
+                MS(status, AR_PHY_WATCHDOG_INFO),
+                MS(status, AR_PHY_WATCHDOG_DET_HANG),
+                MS(status, AR_PHY_WATCHDOG_RADAR_SM),
+                MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
+                MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
+                MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
+                MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
+                MS(status, AR_PHY_WATCHDOG_AGC_SM),
+                MS(status, AR_PHY_WATCHDOG_SRCH_SM));
+
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
+                REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
+                REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB mode: BB_gen_controls=0x%08x **\n",
+                REG_READ(ah, AR_PHY_GEN_CTRL));
+
+#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
+        if (common->cc_survey.cycles)
+                ath_dbg(common, ATH_DBG_RESET,
+                        "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
+                        PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
+
+        ath_dbg(common, ATH_DBG_RESET,
+                "==== BB update: done ====\n\n");
 }
 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
+
+void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
+{
+        u32 val;
+
+        /* While receiving unsupported rate frame rx state machine
+         * gets into a state 0xb and if phy_restart happens in that
+         * state, BB would go hang. If RXSM is in 0xb state after
+         * first bb panic, ensure to disable the phy_restart.
+         */
+        if (!((MS(ah->bb_watchdog_last_status,
+                  AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
+            ah->bb_hang_rx_ofdm))
+                return;
+
+        ah->bb_hang_rx_ofdm = true;
+        val = REG_READ(ah, AR_PHY_RESTART);
+        val &= ~AR_PHY_RESTART_ENA;
+
+        REG_WRITE(ah, AR_PHY_RESTART, val);
+}
+EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 3394dfe52b42..443090d278e3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002-2010 Atheros Communications, Inc.
+ * Copyright (c) 2010-2011 Atheros Communications, Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -260,7 +260,35 @@
 #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
 #define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
 #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
+
+/*
+ * Antenna Diversity  settings
+ */
 #define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)
+#define AR_ANT_DIV_CTRL_ALL     0x7e000000
+#define AR_ANT_DIV_CTRL_ALL_S   25
+#define AR_ANT_DIV_ENABLE       0x1000000
+#define AR_ANT_DIV_ENABLE_S     24
+
+
+#define AR_PHY_9485_ANT_FAST_DIV_BIAS                   0x00007e00
+#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9
+#define AR_PHY_9485_ANT_DIV_LNADIV                      0x01000000
+#define AR_PHY_9485_ANT_DIV_LNADIV_S                    24
+#define AR_PHY_9485_ANT_DIV_ALT_LNACONF                 0x06000000
+#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S               25
+#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF                0x18000000
+#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S              27
+#define AR_PHY_9485_ANT_DIV_ALT_GAINTB                  0x20000000
+#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S                29
+#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB                 0x40000000
+#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S               30
+
+#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2             0x0
+#define AR_PHY_9485_ANT_DIV_LNA2                        0x1
+#define AR_PHY_9485_ANT_DIV_LNA1                        0x2
+#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2              0x3
+
 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
 #define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
@@ -271,7 +299,11 @@
 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
 #define AR_PHY_RSSI_0           (AR_AGC_BASE + 0x180)
 #define AR_PHY_SPUR_CCK_REP0    (AR_AGC_BASE + 0x184)
+
 #define AR_PHY_CCK_DETECT       (AR_AGC_BASE + 0x1c0)
+#define AR_FAST_DIV_ENABLE      0x2000
+#define AR_FAST_DIV_ENABLE_S    13
+
 #define AR_PHY_DAG_CTRLCCK      (AR_AGC_BASE + 0x1c4)
 #define AR_PHY_IQCORR_CTRL_CCK  (AR_AGC_BASE + 0x1c8)
 
@@ -476,6 +508,8 @@
 #define AR_PHY_HEAVYCLIP_40      (AR_SM_BASE + 0x1ac)
 #define AR_PHY_ILLEGAL_TXRATE    (AR_SM_BASE + 0x1b0)
 
+#define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
+
 #define AR_PHY_PWRTX_MAX         (AR_SM_BASE + 0x1f0)
 #define AR_PHY_POWER_TX_SUB      (AR_SM_BASE + 0x1f4)
 
@@ -536,10 +570,15 @@
 
 #define AR_PHY_TXGAIN_TABLE      (AR_SM_BASE + 0x300)
 
-#define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + 0x448)
-#define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + 0x440)
-#define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0    (AR_SM_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + AR_SREV_9485(ah) ? \
+                                                 0x3c8 : 0x448)
+#define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + AR_SREV_9485(ah) ? \
+                                                 0x3c4 : 0x440)
+#define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + AR_SREV_9485(ah) ? \
+                                                 0x3f0 : 0x48c)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i)    (AR_SM_BASE + \
+                                             (AR_SREV_9485(ah) ? \
+                                              0x3d0 : 0x450) + ((_i) << 2))
 
 #define AR_PHY_WATCHDOG_STATUS      (AR_SM_BASE + 0x5c0)
 #define AR_PHY_WATCHDOG_CTL_1       (AR_SM_BASE + 0x5c4)
@@ -568,7 +607,7 @@
 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
 #define AR_PHY_65NM_CH0_BIAS4       0x160cc
 #define AR_PHY_65NM_CH0_RXTX4       0x1610c
-#define AR_PHY_65NM_CH0_THERM       0x16290
+#define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 : 0x1628c)
 
 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
@@ -584,6 +623,24 @@
 #define AR_PHY_65NM_CH2_RXTX1       0x16900
 #define AR_PHY_65NM_CH2_RXTX2       0x16904
 
+#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
+#define AR_CH0_TOP2_XPABIASLVL          0xf000
+#define AR_CH0_TOP2_XPABIASLVL_S        12
+
+#define AR_CH0_XTAL             (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
+#define AR_CH0_XTAL_CAPINDAC    0x7f000000
+#define AR_CH0_XTAL_CAPINDAC_S  24
+#define AR_CH0_XTAL_CAPOUTDAC   0x00fe0000
+#define AR_CH0_XTAL_CAPOUTDAC_S 17
+
+#define AR_PHY_PMU1             0x16c40
+#define AR_PHY_PMU1_PWD         0x1
+#define AR_PHY_PMU1_PWD_S       0
+
+#define AR_PHY_PMU2             0x16c44
+#define AR_PHY_PMU2_PGM         0x00200000
+#define AR_PHY_PMU2_PGM_S       21
+
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT          0x00380000
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S        19
 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT          0x00c00000
@@ -683,6 +740,7 @@
 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN    0x00000001
 #define AR_PHY_TXGAIN_FORCE               0x00000001
+#define AR_PHY_TXGAIN_FORCE_S             0
 #define AR_PHY_TXGAIN_FORCED_PADVGNRA     0x00003c00
 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S   10
 #define AR_PHY_TXGAIN_FORCED_PADVGNRB     0x0003c000
@@ -719,14 +777,19 @@
 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT   0x01000000
 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR      0x00000004
-#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
-#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
-#define AR_PHY_TX_IQCAL_START_DO_CAL        0x00000001
-#define AR_PHY_TX_IQCAL_START_DO_CAL_S      0
+#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
+#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
+#define AR_PHY_TX_IQCAL_START_DO_CAL        0x00000001
+#define AR_PHY_TX_IQCAL_START_DO_CAL_S      0
 
 #define AR_PHY_TX_IQCAL_STATUS_FAILED    0x00000001
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x00003fff
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    0
+#define AR_PHY_CALIBRATED_GAINS_0        0x3e
+#define AR_PHY_CALIBRATED_GAINS_0_S      1
+
+#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE      0x00003fff
+#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S    0
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x0fffc000
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    14
 
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
@@ -785,7 +848,7 @@
 #define AR_PHY_TPC_11_B1         (AR_SM1_BASE + 0x220)
 #define AR_PHY_PDADC_TAB_1       (AR_SM1_BASE + 0x240)
 #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1    (AR_SM1_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM_BASE + 0x450 + ((_i) << 2))
 
 /*
  * Channel 2 Register Map
@@ -838,7 +901,7 @@
 #define AR_PHY_TPC_11_B2         (AR_SM2_BASE + 0x220)
 #define AR_PHY_PDADC_TAB_2       (AR_SM2_BASE + 0x240)
 #define AR_PHY_TX_IQCAL_STATUS_B2   (AR_SM2_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2    (AR_SM2_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i)    (AR_SM2_BASE + 0x450 + ((_i) << 2))
 
 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED    0x00000001
 
@@ -945,7 +1008,9 @@
 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT         0x0ffe0000
 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S       17
 
-#define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + 0x490)
+#define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x580 : 0x490))
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE     0x00000001
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S   0
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING       0x0000007e
@@ -961,11 +1026,15 @@
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP             0x0003f000
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S           12
 
-#define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + 0x494)
+#define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x584 : 0x494))
 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN     0xFFFFFFFF
 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S   0
 
-#define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + 0x498)
+#define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x588 : 0x498))
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE    0x0000003f
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S  0
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP          0x00000fc0
@@ -981,7 +1050,9 @@
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE     0x20000000
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S   29
 
-#define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + 0x49c)
+#define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x58c : 0x49c))
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES   0x03ff0000
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA        0x0000f000
@@ -1040,6 +1111,14 @@
 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0      0x3F
 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S    0
 
+#define AR_PHY_POWERTX_RATE6                    (AR_SM_BASE + 0x1d4)
+#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5      0x3F00
+#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S    8
+
+#define AR_PHY_POWERTX_RATE8                    (AR_SM_BASE + 0x1dc)
+#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5      0x3F00
+#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S    8
+
 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
 
 #endif  /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
index d3375fc4ce8b..815a8af1beef 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -14,26 +14,20 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#ifndef INITVALS_9003_2P0_H
-#define INITVALS_9003_2P0_H
+#ifndef INITVALS_9340_H
+#define INITVALS_9340_H
 
-/* AR9003 2.0 */
-
-static const u32 ar9300_2p0_radio_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-        {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
-        {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
-        {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
-        {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
-        {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
-        {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+static const u32 ar9340_1p0_radio_postamble[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+        {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
+        {0x0001610c, 0x08000000, 0x08000000, 0x00000000, 0x00000000},
+        {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
+        {0x0001650c, 0x08000000, 0x08000000, 0x00000000, 0x00000000},
+        {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
 };
 
-static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
+        /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -99,19 +93,14 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
-        {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
-        {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016448, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
-        {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016848, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
-        {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 };
 
-static const u32 ar9300Modes_fast_clock_2p0[][3] = {
-        /* Addr      5G_HT20     5G_HT40   */
+static const u32 ar9340Modes_fast_clock_1p0[][3] = {
+        /*  Addr      5G_HT20     5G_HT40  */
         {0x00001030, 0x00000268, 0x000004d0},
         {0x00001070, 0x0000018c, 0x00000318},
         {0x000010b0, 0x00000fd0, 0x00001fa0},
@@ -123,46 +112,49 @@ static const u32 ar9300Modes_fast_clock_2p0[][3] = {
         {0x0000a254, 0x00000898, 0x00001130},
 };
 
-static const u32 ar9300_2p0_radio_core[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_radio_core[][2] = {
+        /*  Addr     allmodes  */
         {0x00016000, 0x36db6db6},
         {0x00016004, 0x6db6db40},
         {0x00016008, 0x73f00000},
         {0x0001600c, 0x00000000},
         {0x00016040, 0x7f80fff8},
-        {0x0001604c, 0x76d005b5},
-        {0x00016050, 0x556cf031},
-        {0x00016054, 0x13449440},
-        {0x00016058, 0x0c51c92c},
-        {0x0001605c, 0x3db7fffc},
-        {0x00016060, 0xfffffffc},
-        {0x00016064, 0x000f0278},
-        {0x0001606c, 0x6db60000},
-        {0x00016080, 0x00000000},
+        {0x00016044, 0x03b6d2db},
+        {0x00016048, 0x24925266},
+        {0x0001604c, 0x000f0278},
+        {0x00016050, 0x6db6db6c},
+        {0x00016054, 0x6db60000},
+        {0x00016080, 0x00080000},
         {0x00016084, 0x0e48048c},
-        {0x00016088, 0x54214514},
-        {0x0001608c, 0x119f481e},
+        {0x00016088, 0x14214514},
+        {0x0001608c, 0x119f081c},
         {0x00016090, 0x24926490},
-        {0x00016098, 0xd2888888},
-        {0x000160a0, 0x0a108ffe},
+        {0x00016094, 0x00000000},
+        {0x00016098, 0xd411eb84},
+        {0x0001609c, 0x03e47f32},
+        {0x000160a0, 0xc2108ffe},
         {0x000160a4, 0x812fc370},
         {0x000160a8, 0x423c8000},
-        {0x000160b4, 0x92480080},
-        {0x000160c0, 0x00adb6d0},
+        {0x000160ac, 0xa4646800},
+        {0x000160b0, 0x00fe7f46},
+        {0x000160b4, 0x92480000},
+        {0x000160c0, 0x006db6db},
         {0x000160c4, 0x6db6db60},
         {0x000160c8, 0x6db6db6c},
-        {0x000160cc, 0x01e6c000},
-        {0x00016100, 0x3fffbe01},
+        {0x000160cc, 0x6de6db6c},
+        {0x000160d0, 0xb6da4924},
+        {0x00016100, 0x04cb0001},
         {0x00016104, 0xfff80000},
         {0x00016108, 0x00080010},
-        {0x00016144, 0x02084080},
-        {0x00016148, 0x00000000},
-        {0x00016280, 0x058a0001},
-        {0x00016284, 0x3d840208},
-        {0x00016288, 0x05a20408},
-        {0x0001628c, 0x00038c07},
-        {0x00016290, 0x40000004},
-        {0x00016294, 0x458aa14f},
+        {0x0001610c, 0x00000000},
+        {0x00016140, 0x50804008},
+        {0x00016144, 0x01884080},
+        {0x00016148, 0x000080c0},
+        {0x00016280, 0x01000015},
+        {0x00016284, 0x05530000},
+        {0x00016288, 0x00318000},
+        {0x0001628c, 0x50000000},
+        {0x00016290, 0x4080294f},
         {0x00016380, 0x00000000},
         {0x00016384, 0x00000000},
         {0x00016388, 0x00800700},
@@ -190,19 +182,18 @@ static const u32 ar9300_2p0_radio_core[][2] = {
         {0x00016408, 0x73f00000},
         {0x0001640c, 0x00000000},
         {0x00016440, 0x7f80fff8},
-        {0x0001644c, 0x76d005b5},
-        {0x00016450, 0x556cf031},
-        {0x00016454, 0x13449440},
-        {0x00016458, 0x0c51c92c},
-        {0x0001645c, 0x3db7fffc},
-        {0x00016460, 0xfffffffc},
-        {0x00016464, 0x000f0278},
-        {0x0001646c, 0x6db60000},
-        {0x00016500, 0x3fffbe01},
+        {0x00016444, 0x03b6d2db},
+        {0x00016448, 0x24927266},
+        {0x0001644c, 0x000f0278},
+        {0x00016450, 0x6db6db6c},
+        {0x00016454, 0x6db60000},
+        {0x00016500, 0x04cb0001},
         {0x00016504, 0xfff80000},
         {0x00016508, 0x00080010},
-        {0x00016544, 0x02084080},
-        {0x00016548, 0x00000000},
+        {0x0001650c, 0x00000000},
+        {0x00016540, 0x50804008},
+        {0x00016544, 0x01884080},
+        {0x00016548, 0x000080c0},
         {0x00016780, 0x00000000},
         {0x00016784, 0x00000000},
         {0x00016788, 0x00800700},
@@ -225,310 +216,16 @@ static const u32 ar9300_2p0_radio_core[][2] = {
         {0x000167cc, 0x00001402},
         {0x000167d0, 0x00000000},
         {0x000167d4, 0x00000000},
-        {0x00016800, 0x36db6db6},
-        {0x00016804, 0x6db6db40},
-        {0x00016808, 0x73f00000},
-        {0x0001680c, 0x00000000},
-        {0x00016840, 0x7f80fff8},
-        {0x0001684c, 0x76d005b5},
-        {0x00016850, 0x556cf031},
-        {0x00016854, 0x13449440},
-        {0x00016858, 0x0c51c92c},
-        {0x0001685c, 0x3db7fffc},
-        {0x00016860, 0xfffffffc},
-        {0x00016864, 0x000f0278},
-        {0x0001686c, 0x6db60000},
-        {0x00016900, 0x3fffbe01},
-        {0x00016904, 0xfff80000},
-        {0x00016908, 0x00080010},
-        {0x00016944, 0x02084080},
-        {0x00016948, 0x00000000},
-        {0x00016b80, 0x00000000},
-        {0x00016b84, 0x00000000},
-        {0x00016b88, 0x00800700},
-        {0x00016b8c, 0x00800700},
-        {0x00016b90, 0x00800700},
-        {0x00016b94, 0x00000000},
-        {0x00016b98, 0x00000000},
-        {0x00016b9c, 0x00000000},
-        {0x00016ba0, 0x00000001},
-        {0x00016ba4, 0x00000001},
-        {0x00016ba8, 0x00000000},
-        {0x00016bac, 0x00000000},
-        {0x00016bb0, 0x00000000},
-        {0x00016bb4, 0x00000000},
-        {0x00016bb8, 0x00000000},
-        {0x00016bbc, 0x00000000},
-        {0x00016bc0, 0x000000a0},
-        {0x00016bc4, 0x000c0000},
-        {0x00016bc8, 0x14021402},
-        {0x00016bcc, 0x00001402},
-        {0x00016bd0, 0x00000000},
-        {0x00016bd4, 0x00000000},
 };
 
-static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x0000a000, 0x02000101},
-        {0x0000a004, 0x02000102},
-        {0x0000a008, 0x02000103},
-        {0x0000a00c, 0x02000104},
-        {0x0000a010, 0x02000200},
-        {0x0000a014, 0x02000201},
-        {0x0000a018, 0x02000202},
-        {0x0000a01c, 0x02000203},
-        {0x0000a020, 0x02000204},
-        {0x0000a024, 0x02000205},
-        {0x0000a028, 0x02000208},
-        {0x0000a02c, 0x02000302},
-        {0x0000a030, 0x02000303},
-        {0x0000a034, 0x02000304},
-        {0x0000a038, 0x02000400},
-        {0x0000a03c, 0x02010300},
-        {0x0000a040, 0x02010301},
-        {0x0000a044, 0x02010302},
-        {0x0000a048, 0x02000500},
-        {0x0000a04c, 0x02010400},
-        {0x0000a050, 0x02020300},
-        {0x0000a054, 0x02020301},
-        {0x0000a058, 0x02020302},
-        {0x0000a05c, 0x02020303},
-        {0x0000a060, 0x02020400},
-        {0x0000a064, 0x02030300},
-        {0x0000a068, 0x02030301},
-        {0x0000a06c, 0x02030302},
-        {0x0000a070, 0x02030303},
-        {0x0000a074, 0x02030400},
-        {0x0000a078, 0x02040300},
-        {0x0000a07c, 0x02040301},
-        {0x0000a080, 0x02040302},
-        {0x0000a084, 0x02040303},
-        {0x0000a088, 0x02030500},
-        {0x0000a08c, 0x02040400},
-        {0x0000a090, 0x02050203},
-        {0x0000a094, 0x02050204},
-        {0x0000a098, 0x02050205},
-        {0x0000a09c, 0x02040500},
-        {0x0000a0a0, 0x02050301},
-        {0x0000a0a4, 0x02050302},
-        {0x0000a0a8, 0x02050303},
-        {0x0000a0ac, 0x02050400},
-        {0x0000a0b0, 0x02050401},
-        {0x0000a0b4, 0x02050402},
-        {0x0000a0b8, 0x02050403},
-        {0x0000a0bc, 0x02050500},
-        {0x0000a0c0, 0x02050501},
-        {0x0000a0c4, 0x02050502},
-        {0x0000a0c8, 0x02050503},
-        {0x0000a0cc, 0x02050504},
-        {0x0000a0d0, 0x02050600},
-        {0x0000a0d4, 0x02050601},
-        {0x0000a0d8, 0x02050602},
-        {0x0000a0dc, 0x02050603},
-        {0x0000a0e0, 0x02050604},
-        {0x0000a0e4, 0x02050700},
-        {0x0000a0e8, 0x02050701},
-        {0x0000a0ec, 0x02050702},
-        {0x0000a0f0, 0x02050703},
-        {0x0000a0f4, 0x02050704},
-        {0x0000a0f8, 0x02050705},
-        {0x0000a0fc, 0x02050708},
-        {0x0000a100, 0x02050709},
-        {0x0000a104, 0x0205070a},
-        {0x0000a108, 0x0205070b},
-        {0x0000a10c, 0x0205070c},
-        {0x0000a110, 0x0205070d},
-        {0x0000a114, 0x02050710},
-        {0x0000a118, 0x02050711},
-        {0x0000a11c, 0x02050712},
-        {0x0000a120, 0x02050713},
-        {0x0000a124, 0x02050714},
-        {0x0000a128, 0x02050715},
-        {0x0000a12c, 0x02050730},
-        {0x0000a130, 0x02050731},
-        {0x0000a134, 0x02050732},
-        {0x0000a138, 0x02050733},
-        {0x0000a13c, 0x02050734},
-        {0x0000a140, 0x02050735},
-        {0x0000a144, 0x02050750},
-        {0x0000a148, 0x02050751},
-        {0x0000a14c, 0x02050752},
-        {0x0000a150, 0x02050753},
-        {0x0000a154, 0x02050754},
-        {0x0000a158, 0x02050755},
-        {0x0000a15c, 0x02050770},
-        {0x0000a160, 0x02050771},
-        {0x0000a164, 0x02050772},
-        {0x0000a168, 0x02050773},
-        {0x0000a16c, 0x02050774},
-        {0x0000a170, 0x02050775},
-        {0x0000a174, 0x00000776},
-        {0x0000a178, 0x00000776},
-        {0x0000a17c, 0x00000776},
-        {0x0000a180, 0x00000776},
-        {0x0000a184, 0x00000776},
-        {0x0000a188, 0x00000776},
-        {0x0000a18c, 0x00000776},
-        {0x0000a190, 0x00000776},
-        {0x0000a194, 0x00000776},
-        {0x0000a198, 0x00000776},
-        {0x0000a19c, 0x00000776},
-        {0x0000a1a0, 0x00000776},
-        {0x0000a1a4, 0x00000776},
-        {0x0000a1a8, 0x00000776},
-        {0x0000a1ac, 0x00000776},
-        {0x0000a1b0, 0x00000776},
-        {0x0000a1b4, 0x00000776},
-        {0x0000a1b8, 0x00000776},
-        {0x0000a1bc, 0x00000776},
-        {0x0000a1c0, 0x00000776},
-        {0x0000a1c4, 0x00000776},
-        {0x0000a1c8, 0x00000776},
-        {0x0000a1cc, 0x00000776},
-        {0x0000a1d0, 0x00000776},
-        {0x0000a1d4, 0x00000776},
-        {0x0000a1d8, 0x00000776},
-        {0x0000a1dc, 0x00000776},
-        {0x0000a1e0, 0x00000776},
-        {0x0000a1e4, 0x00000776},
-        {0x0000a1e8, 0x00000776},
-        {0x0000a1ec, 0x00000776},
-        {0x0000a1f0, 0x00000776},
-        {0x0000a1f4, 0x00000776},
-        {0x0000a1f8, 0x00000776},
-        {0x0000a1fc, 0x00000776},
-        {0x0000b000, 0x02000101},
-        {0x0000b004, 0x02000102},
-        {0x0000b008, 0x02000103},
-        {0x0000b00c, 0x02000104},
-        {0x0000b010, 0x02000200},
-        {0x0000b014, 0x02000201},
-        {0x0000b018, 0x02000202},
-        {0x0000b01c, 0x02000203},
-        {0x0000b020, 0x02000204},
-        {0x0000b024, 0x02000205},
-        {0x0000b028, 0x02000208},
-        {0x0000b02c, 0x02000302},
-        {0x0000b030, 0x02000303},
-        {0x0000b034, 0x02000304},
-        {0x0000b038, 0x02000400},
-        {0x0000b03c, 0x02010300},
-        {0x0000b040, 0x02010301},
-        {0x0000b044, 0x02010302},
-        {0x0000b048, 0x02000500},
-        {0x0000b04c, 0x02010400},
-        {0x0000b050, 0x02020300},
-        {0x0000b054, 0x02020301},
-        {0x0000b058, 0x02020302},
-        {0x0000b05c, 0x02020303},
-        {0x0000b060, 0x02020400},
-        {0x0000b064, 0x02030300},
-        {0x0000b068, 0x02030301},
-        {0x0000b06c, 0x02030302},
-        {0x0000b070, 0x02030303},
-        {0x0000b074, 0x02030400},
-        {0x0000b078, 0x02040300},
-        {0x0000b07c, 0x02040301},
-        {0x0000b080, 0x02040302},
-        {0x0000b084, 0x02040303},
-        {0x0000b088, 0x02030500},
-        {0x0000b08c, 0x02040400},
-        {0x0000b090, 0x02050203},
-        {0x0000b094, 0x02050204},
-        {0x0000b098, 0x02050205},
-        {0x0000b09c, 0x02040500},
-        {0x0000b0a0, 0x02050301},
-        {0x0000b0a4, 0x02050302},
-        {0x0000b0a8, 0x02050303},
-        {0x0000b0ac, 0x02050400},
-        {0x0000b0b0, 0x02050401},
-        {0x0000b0b4, 0x02050402},
-        {0x0000b0b8, 0x02050403},
-        {0x0000b0bc, 0x02050500},
-        {0x0000b0c0, 0x02050501},
-        {0x0000b0c4, 0x02050502},
-        {0x0000b0c8, 0x02050503},
-        {0x0000b0cc, 0x02050504},
-        {0x0000b0d0, 0x02050600},
-        {0x0000b0d4, 0x02050601},
-        {0x0000b0d8, 0x02050602},
-        {0x0000b0dc, 0x02050603},
-        {0x0000b0e0, 0x02050604},
-        {0x0000b0e4, 0x02050700},
-        {0x0000b0e8, 0x02050701},
-        {0x0000b0ec, 0x02050702},
-        {0x0000b0f0, 0x02050703},
-        {0x0000b0f4, 0x02050704},
-        {0x0000b0f8, 0x02050705},
-        {0x0000b0fc, 0x02050708},
-        {0x0000b100, 0x02050709},
-        {0x0000b104, 0x0205070a},
-        {0x0000b108, 0x0205070b},
-        {0x0000b10c, 0x0205070c},
-        {0x0000b110, 0x0205070d},
-        {0x0000b114, 0x02050710},
-        {0x0000b118, 0x02050711},
-        {0x0000b11c, 0x02050712},
-        {0x0000b120, 0x02050713},
-        {0x0000b124, 0x02050714},
-        {0x0000b128, 0x02050715},
-        {0x0000b12c, 0x02050730},
-        {0x0000b130, 0x02050731},
-        {0x0000b134, 0x02050732},
-        {0x0000b138, 0x02050733},
-        {0x0000b13c, 0x02050734},
-        {0x0000b140, 0x02050735},
-        {0x0000b144, 0x02050750},
-        {0x0000b148, 0x02050751},
-        {0x0000b14c, 0x02050752},
-        {0x0000b150, 0x02050753},
-        {0x0000b154, 0x02050754},
-        {0x0000b158, 0x02050755},
-        {0x0000b15c, 0x02050770},
-        {0x0000b160, 0x02050771},
-        {0x0000b164, 0x02050772},
-        {0x0000b168, 0x02050773},
-        {0x0000b16c, 0x02050774},
-        {0x0000b170, 0x02050775},
-        {0x0000b174, 0x00000776},
-        {0x0000b178, 0x00000776},
-        {0x0000b17c, 0x00000776},
-        {0x0000b180, 0x00000776},
-        {0x0000b184, 0x00000776},
-        {0x0000b188, 0x00000776},
-        {0x0000b18c, 0x00000776},
-        {0x0000b190, 0x00000776},
-        {0x0000b194, 0x00000776},
-        {0x0000b198, 0x00000776},
-        {0x0000b19c, 0x00000776},
-        {0x0000b1a0, 0x00000776},
-        {0x0000b1a4, 0x00000776},
-        {0x0000b1a8, 0x00000776},
-        {0x0000b1ac, 0x00000776},
-        {0x0000b1b0, 0x00000776},
-        {0x0000b1b4, 0x00000776},
-        {0x0000b1b8, 0x00000776},
-        {0x0000b1bc, 0x00000776},
-        {0x0000b1c0, 0x00000776},
-        {0x0000b1c4, 0x00000776},
-        {0x0000b1c8, 0x00000776},
-        {0x0000b1cc, 0x00000776},
-        {0x0000b1d0, 0x00000776},
-        {0x0000b1d4, 0x00000776},
-        {0x0000b1d8, 0x00000776},
-        {0x0000b1dc, 0x00000776},
-        {0x0000b1e0, 0x00000776},
-        {0x0000b1e4, 0x00000776},
-        {0x0000b1e8, 0x00000776},
-        {0x0000b1ec, 0x00000776},
-        {0x0000b1f0, 0x00000776},
-        {0x0000b1f4, 0x00000776},
-        {0x0000b1f8, 0x00000776},
-        {0x0000b1fc, 0x00000776},
+static const u32 ar9340_1p0_radio_core_40M[][2] = {
+        {0x0001609c, 0x02566f3a},
+        {0x000160ac, 0xa4647c00},
+        {0x000160b0, 0x01885f5a},
 };
 
-static const u32 ar9300_2p0_mac_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340_1p0_mac_postamble[][5] = {
+        /* Addr       5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
         {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
         {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
         {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
@@ -539,66 +236,24 @@ static const u32 ar9300_2p0_mac_postamble[][5] = {
         {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
 };
 
-static const u32 ar9300_2p0_soc_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340_1p0_soc_postamble[][5] = {
+        /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
 };
 
-static const u32 ar9200_merlin_2p0_radio_core[][2] = {
-        /* Addr      allmodes  */
-        {0x00007800, 0x00040000},
-        {0x00007804, 0xdb005012},
-        {0x00007808, 0x04924914},
-        {0x0000780c, 0x21084210},
-        {0x00007810, 0x6d801300},
-        {0x00007814, 0x0019beff},
-        {0x00007818, 0x07e41000},
-        {0x0000781c, 0x00392000},
-        {0x00007820, 0x92592480},
-        {0x00007824, 0x00040000},
-        {0x00007828, 0xdb005012},
-        {0x0000782c, 0x04924914},
-        {0x00007830, 0x21084210},
-        {0x00007834, 0x6d801300},
-        {0x00007838, 0x0019beff},
-        {0x0000783c, 0x07e40000},
-        {0x00007840, 0x00392000},
-        {0x00007844, 0x92592480},
-        {0x00007848, 0x00100000},
-        {0x0000784c, 0x773f0567},
-        {0x00007850, 0x54214514},
-        {0x00007854, 0x12035828},
-        {0x00007858, 0x92592692},
-        {0x0000785c, 0x00000000},
-        {0x00007860, 0x56400000},
-        {0x00007864, 0x0a8e370e},
-        {0x00007868, 0xc0102850},
-        {0x0000786c, 0x812d4000},
-        {0x00007870, 0x807ec400},
-        {0x00007874, 0x001b6db0},
-        {0x00007878, 0x00376b63},
-        {0x0000787c, 0x06db6db6},
-        {0x00007880, 0x006d8000},
-        {0x00007884, 0xffeffffe},
-        {0x00007888, 0xffeffffe},
-        {0x0000788c, 0x00010000},
-        {0x00007890, 0x02060aeb},
-        {0x00007894, 0x5a108000},
-};
-
-static const u32 ar9300_2p0_baseband_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340_1p0_baseband_postamble[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
-        {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
+        {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
         {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
         {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
         {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
-        {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
         {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
-        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
+        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e},
         {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
@@ -607,7 +262,7 @@ static const u32 ar9300_2p0_baseband_postamble[][5] = {
         {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27},
         {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
         {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
-        {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
+        {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
         {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
         {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
         {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
@@ -619,33 +274,27 @@ static const u32 ar9300_2p0_baseband_postamble[][5] = {
         {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
         {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
         {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
-        {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
-        {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
+        {0x0000a288, 0x00000220, 0x00000220, 0x00000110, 0x00000110},
+        {0x0000a28c, 0x00011111, 0x00011111, 0x00022222, 0x00022222},
         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
         {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
         {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000ae04, 0x00180000, 0x00180000, 0x00180000, 0x00180000},
         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
         {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
-        {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
-        {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
-        {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
 };
 
-static const u32 ar9300_2p0_baseband_core[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_baseband_core[][2] = {
+        /*  Addr     allmodes  */
         {0x00009800, 0xafe68e30},
         {0x00009804, 0xfd14e000},
         {0x00009808, 0x9c0a9f6b},
         {0x0000980c, 0x04900000},
-        {0x00009814, 0x9280c00a},
+        {0x00009814, 0xb280c00a},
         {0x00009818, 0x00000000},
         {0x0000981c, 0x00020028},
         {0x00009834, 0x5f3ca3de},
@@ -794,7 +443,7 @@ static const u32 ar9300_2p0_baseband_core[][2] = {
         {0x0000a7cc, 0x00000000},
         {0x0000a7d0, 0x00000000},
         {0x0000a7d4, 0x00000004},
-        {0x0000a7dc, 0x00000001},
+        {0x0000a7dc, 0x00000000},
         {0x0000a8d0, 0x004b6a8e},
         {0x0000a8d4, 0x00000820},
         {0x0000a8dc, 0x00000000},
@@ -813,28 +462,10 @@ static const u32 ar9300_2p0_baseband_core[][2] = {
         {0x0000b408, 0x0e79e5c0},
         {0x0000b40c, 0x00820820},
         {0x0000b420, 0x00000000},
-        {0x0000b8d0, 0x004b6a8e},
-        {0x0000b8d4, 0x00000820},
-        {0x0000b8dc, 0x00000000},
-        {0x0000b8f0, 0x00000000},
-        {0x0000b8f4, 0x00000000},
-        {0x0000c2d0, 0x00000080},
-        {0x0000c2d4, 0x00000000},
-        {0x0000c2dc, 0x00000000},
-        {0x0000c2e0, 0x00000000},
-        {0x0000c2e4, 0x00000000},
-        {0x0000c2e8, 0x00000000},
-        {0x0000c2ec, 0x00000000},
-        {0x0000c2f0, 0x00000000},
-        {0x0000c2f4, 0x00000000},
-        {0x0000c2f8, 0x00000000},
-        {0x0000c408, 0x0e79e5c0},
-        {0x0000c40c, 0x00820820},
-        {0x0000c420, 0x00000000},
 };
 
-static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -900,19 +531,14 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
-        {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
-        {0x00016048, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
-        {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
-        {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
-        {0x00016448, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
-        {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
-        {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
-        {0x00016848, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
-        {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 };
 
-static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
+        /*  Addr       5G_HT20    5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -978,19 +604,87 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
-        {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
-        {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
-        {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
-        {0x00016448, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
-        {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
-        {0x00016848, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
-        {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+        {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016048, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266},
+        {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016448, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266},
+};
+static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
+        /*  Addr      5G_HT20      5G_HT40     2G_HT40    2G_HT20  */
+        {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+        {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+        {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
+        {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
+        {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
+        {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
+        {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
+        {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
+        {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
+        {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
+        {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
+        {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
+        {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
+        {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
+        {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
+        {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
+        {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
+        {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
+        {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+        {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+        {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
+        {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
+        {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
+        {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
+        {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
+        {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+        {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
+        {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
+        {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
+        {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
+        {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
+        {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
+        {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
+        {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
+        {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
+        {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
+        {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
+        {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
+        {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
+        {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
+        {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
+        {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
+        {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
+        {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
+        {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
+        {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
+        {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
+        {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
+        {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
+        {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
+        {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x00016044, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db},
+        {0x00016048, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266},
+        {0x00016444, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db},
+        {0x00016448, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266},
 };
 
-static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
-        /* Addr      allmodes  */
+
+static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
+        /*   Addr     allmodes */
         {0x0000a000, 0x00010000},
         {0x0000a004, 0x00030002},
         {0x0000a008, 0x00050004},
@@ -1249,8 +943,8 @@ static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
         {0x0000b1fc, 0x00000196},
 };
 
-static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -1316,19 +1010,87 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
-        {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016048, 0x64000001, 0x64000001, 0x64000001, 0x64000001},
-        {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016448, 0x64000001, 0x64000001, 0x64000001, 0x64000001},
-        {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016848, 0x64000001, 0x64000001, 0x64000001, 0x64000001},
-        {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+};
+
+static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
+        /*  Addr       5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
+        {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
+        {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
+        {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
+        {0x0000a518, 0x21020220, 0x21020220, 0x15000402, 0x15000402},
+        {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
+        {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603},
+        {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02},
+        {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04},
+        {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x26000a20, 0x26000a20},
+        {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2a000e20, 0x2a000e20},
+        {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
+        {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
+        {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
+        {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
+        {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
+        {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
+        {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x42001a83, 0x42001a83},
+        {0x0000a550, 0x61042a6c, 0x61042a6c, 0x44001c84, 0x44001c84},
+        {0x0000a554, 0x66062a6c, 0x66062a6c, 0x48001ce3, 0x48001ce3},
+        {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x4c001ce5, 0x4c001ce5},
+        {0x0000a55c, 0x7006308c, 0x7006308c, 0x50001ce9, 0x50001ce9},
+        {0x0000a560, 0x730a308a, 0x730a308a, 0x54001ceb, 0x54001ceb},
+        {0x0000a564, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a568, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a56c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a570, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a574, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a578, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a57c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
+        {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
+        {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
+        {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
+        {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
+        {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
+        {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
+        {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
+        {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
+        {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
+        {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
+        {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
+        {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
+        {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
+        {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
+        {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
+        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
+        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
+        {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
+        {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
+        {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
+        {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
+        {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
+        {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
+        {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016048, 0x24927266, 0x24927266, 0x8e483266, 0x8e483266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016448, 0x24927266, 0x24927266, 0x8e482266, 0x8e482266},
 };
 
-static const u32 ar9300_2p0_mac_core[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_mac_core[][2] = {
+        /*    Addr        allmodes        */
         {0x00000008, 0x00000000},
         {0x00000030, 0x00020085},
         {0x00000034, 0x00000005},
@@ -1437,7 +1199,7 @@ static const u32 ar9300_2p0_mac_core[][2] = {
         {0x00008258, 0x00000000},
         {0x0000825c, 0x40000000},
         {0x00008260, 0x00080922},
-        {0x00008264, 0x98a00010},
+        {0x00008264, 0x9d400010},
         {0x00008268, 0xffffffff},
         {0x0000826c, 0x0000ffff},
         {0x00008270, 0x00000000},
@@ -1491,8 +1253,8 @@ static const u32 ar9300_2p0_mac_core[][2] = {
         {0x000083d0, 0x000301ff},
 };
 
-static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = {
+        /*    Addr        allmodes        */
         {0x0000a000, 0x00010000},
         {0x0000a004, 0x00030002},
         {0x0000a008, 0x00050004},
@@ -1751,8 +1513,8 @@ static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
         {0x0000b1fc, 0x00000196},
 };
 
-static const u32 ar9300_2p0_soc_preamble[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_soc_preamble[][2] = {
+        /*    Addr        allmodes        */
         {0x000040a4, 0x00a0c1c9},
         {0x00007008, 0x00000000},
         {0x00007020, 0x00000000},
@@ -1760,25 +1522,4 @@ static const u32 ar9300_2p0_soc_preamble[][2] = {
         {0x00007038, 0x000004c2},
 };
 
-static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x00004040, 0x08212e5e},
-        {0x00004040, 0x0008003b},
-        {0x00004044, 0x00000000},
-};
-
-static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x00004040, 0x08253e5e},
-        {0x00004040, 0x0008003b},
-        {0x00004044, 0x00000000},
-};
-
-static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x00004040, 0x08213e5e},
-        {0x00004040, 0x0008003b},
-        {0x00004044, 0x00000000},
-};
-
-#endif /* INITVALS_9003_2P0_H */
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
new file mode 100644
index 000000000000..611ea6ce8508
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -0,0 +1,1161 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef INITVALS_9485_H
+#define INITVALS_9485_H
+
+static const u32 ar9485_1_1_mac_core[][2] = {
+        /*  Addr       allmodes */
+        {0x00000008, 0x00000000},
+        {0x00000030, 0x00020085},
+        {0x00000034, 0x00000005},
+        {0x00000040, 0x00000000},
+        {0x00000044, 0x00000000},
+        {0x00000048, 0x00000008},
+        {0x0000004c, 0x00000010},
+        {0x00000050, 0x00000000},
+        {0x00001040, 0x002ffc0f},
+        {0x00001044, 0x002ffc0f},
+        {0x00001048, 0x002ffc0f},
+        {0x0000104c, 0x002ffc0f},
+        {0x00001050, 0x002ffc0f},
+        {0x00001054, 0x002ffc0f},
+        {0x00001058, 0x002ffc0f},
+        {0x0000105c, 0x002ffc0f},
+        {0x00001060, 0x002ffc0f},
+        {0x00001064, 0x002ffc0f},
+        {0x000010f0, 0x00000100},
+        {0x00001270, 0x00000000},
+        {0x000012b0, 0x00000000},
+        {0x000012f0, 0x00000000},
+        {0x0000143c, 0x00000000},
+        {0x0000147c, 0x00000000},
+        {0x00008000, 0x00000000},
+        {0x00008004, 0x00000000},
+        {0x00008008, 0x00000000},
+        {0x0000800c, 0x00000000},
+        {0x00008018, 0x00000000},
+        {0x00008020, 0x00000000},
+        {0x00008038, 0x00000000},
+        {0x0000803c, 0x00000000},
+        {0x00008040, 0x00000000},
+        {0x00008044, 0x00000000},
+        {0x00008048, 0x00000000},
+        {0x0000804c, 0xffffffff},
+        {0x00008054, 0x00000000},
+        {0x00008058, 0x00000000},
+        {0x0000805c, 0x000fc78f},
+        {0x00008060, 0x0000000f},
+        {0x00008064, 0x00000000},
+        {0x00008070, 0x00000310},
+        {0x00008074, 0x00000020},
+        {0x00008078, 0x00000000},
+        {0x0000809c, 0x0000000f},
+        {0x000080a0, 0x00000000},
+        {0x000080a4, 0x02ff0000},
+        {0x000080a8, 0x0e070605},
+        {0x000080ac, 0x0000000d},
+        {0x000080b0, 0x00000000},
+        {0x000080b4, 0x00000000},
+        {0x000080b8, 0x00000000},
+        {0x000080bc, 0x00000000},
+        {0x000080c0, 0x2a800000},
+        {0x000080c4, 0x06900168},
+        {0x000080c8, 0x13881c22},
+        {0x000080cc, 0x01f40000},
+        {0x000080d0, 0x00252500},
+        {0x000080d4, 0x00a00000},
+        {0x000080d8, 0x00400000},
+        {0x000080dc, 0x00000000},
+        {0x000080e0, 0xffffffff},
+        {0x000080e4, 0x0000ffff},
+        {0x000080e8, 0x3f3f3f3f},
+        {0x000080ec, 0x00000000},
+        {0x000080f0, 0x00000000},
+        {0x000080f4, 0x00000000},
+        {0x000080fc, 0x00020000},
+        {0x00008100, 0x00000000},
+        {0x00008108, 0x00000052},
+        {0x0000810c, 0x00000000},
+        {0x00008110, 0x00000000},
+        {0x00008114, 0x000007ff},
+        {0x00008118, 0x000000aa},
+        {0x0000811c, 0x00003210},
+        {0x00008124, 0x00000000},
+        {0x00008128, 0x00000000},
+        {0x0000812c, 0x00000000},
+        {0x00008130, 0x00000000},
+        {0x00008134, 0x00000000},
+        {0x00008138, 0x00000000},
+        {0x0000813c, 0x0000ffff},
+        {0x00008144, 0xffffffff},
+        {0x00008168, 0x00000000},
+        {0x0000816c, 0x00000000},
+        {0x00008170, 0x18486200},
+        {0x00008174, 0x33332210},
+        {0x00008178, 0x00000000},
+        {0x0000817c, 0x00020000},
+        {0x000081c0, 0x00000000},
+        {0x000081c4, 0x33332210},
+        {0x000081d4, 0x00000000},
+        {0x000081ec, 0x00000000},
+        {0x000081f0, 0x00000000},
+        {0x000081f4, 0x00000000},
+        {0x000081f8, 0x00000000},
+        {0x000081fc, 0x00000000},
+        {0x00008240, 0x00100000},
+        {0x00008244, 0x0010f400},
+        {0x00008248, 0x00000800},
+        {0x0000824c, 0x0001e800},
+        {0x00008250, 0x00000000},
+        {0x00008254, 0x00000000},
+        {0x00008258, 0x00000000},
+        {0x0000825c, 0x40000000},
+        {0x00008260, 0x00080922},
+        {0x00008264, 0x9ca00010},
+        {0x00008268, 0xffffffff},
+        {0x0000826c, 0x0000ffff},
+        {0x00008270, 0x00000000},
+        {0x00008274, 0x40000000},
+        {0x00008278, 0x003e4180},
+        {0x0000827c, 0x00000004},
+        {0x00008284, 0x0000002c},
+        {0x00008288, 0x0000002c},
+        {0x0000828c, 0x000000ff},
+        {0x00008294, 0x00000000},
+        {0x00008298, 0x00000000},
+        {0x0000829c, 0x00000000},
+        {0x00008300, 0x00000140},
+        {0x00008314, 0x00000000},
+        {0x0000831c, 0x0000010d},
+        {0x00008328, 0x00000000},
+        {0x0000832c, 0x00000007},
+        {0x00008330, 0x00000302},
+        {0x00008334, 0x00000700},
+        {0x00008338, 0x00ff0000},
+        {0x0000833c, 0x02400000},
+        {0x00008340, 0x000107ff},
+        {0x00008344, 0xa248105b},
+        {0x00008348, 0x008f0000},
+        {0x0000835c, 0x00000000},
+        {0x00008360, 0xffffffff},
+        {0x00008364, 0xffffffff},
+        {0x00008368, 0x00000000},
+        {0x00008370, 0x00000000},
+        {0x00008374, 0x000000ff},
+        {0x00008378, 0x00000000},
+        {0x0000837c, 0x00000000},
+        {0x00008380, 0xffffffff},
+        {0x00008384, 0xffffffff},
+        {0x00008390, 0xffffffff},
+        {0x00008394, 0xffffffff},
+        {0x00008398, 0x00000000},
+        {0x0000839c, 0x00000000},
+        {0x000083a0, 0x00000000},
+        {0x000083a4, 0x0000fa14},
+        {0x000083a8, 0x000f0c00},
+        {0x000083ac, 0x33332210},
+        {0x000083b0, 0x33332210},
+        {0x000083b4, 0x33332210},
+        {0x000083b8, 0x33332210},
+        {0x000083bc, 0x00000000},
+        {0x000083c0, 0x00000000},
+        {0x000083c4, 0x00000000},
+        {0x000083c8, 0x00000000},
+        {0x000083cc, 0x00000200},
+        {0x000083d0, 0x000301ff},
+};
+
+static const u32 ar9485_1_1_baseband_core[][2] = {
+        /* Addr       allmodes */
+        {0x00009800, 0xafe68e30},
+        {0x00009804, 0xfd14e000},
+        {0x00009808, 0x9c0a8f6b},
+        {0x0000980c, 0x04800000},
+        {0x00009814, 0x9280c00a},
+        {0x00009818, 0x00000000},
+        {0x0000981c, 0x00020028},
+        {0x00009834, 0x5f3ca3de},
+        {0x00009838, 0x0108ecff},
+        {0x0000983c, 0x14750600},
+        {0x00009880, 0x201fff00},
+        {0x00009884, 0x00001042},
+        {0x000098a4, 0x00200400},
+        {0x000098b0, 0x52440bbe},
+        {0x000098d0, 0x004b6a8e},
+        {0x000098d4, 0x00000820},
+        {0x000098dc, 0x00000000},
+        {0x000098f0, 0x00000000},
+        {0x000098f4, 0x00000000},
+        {0x00009c04, 0x00000000},
+        {0x00009c08, 0x03200000},
+        {0x00009c0c, 0x00000000},
+        {0x00009c10, 0x00000000},
+        {0x00009c14, 0x00046384},
+        {0x00009c18, 0x05b6b440},
+        {0x00009c1c, 0x00b6b440},
+        {0x00009d00, 0xc080a333},
+        {0x00009d04, 0x40206c10},
+        {0x00009d08, 0x009c4060},
+        {0x00009d0c, 0x1883800a},
+        {0x00009d10, 0x01834061},
+        {0x00009d14, 0x00c00400},
+        {0x00009d18, 0x00000000},
+        {0x00009d1c, 0x00000000},
+        {0x00009e08, 0x0038233c},
+        {0x00009e24, 0x9927b515},
+        {0x00009e28, 0x12ef0200},
+        {0x00009e30, 0x06336f77},
+        {0x00009e34, 0x6af6532f},
+        {0x00009e38, 0x0cc80c00},
+        {0x00009e40, 0x0d261820},
+        {0x00009e4c, 0x00001004},
+        {0x00009e50, 0x00ff03f1},
+        {0x00009fc0, 0x80be4788},
+        {0x00009fc4, 0x0001efb5},
+        {0x00009fcc, 0x40000014},
+        {0x0000a20c, 0x00000000},
+        {0x0000a210, 0x00000000},
+        {0x0000a220, 0x00000000},
+        {0x0000a224, 0x00000000},
+        {0x0000a228, 0x10002310},
+        {0x0000a23c, 0x00000000},
+        {0x0000a244, 0x0c000000},
+        {0x0000a2a0, 0x00000001},
+        {0x0000a2c0, 0x00000001},
+        {0x0000a2c8, 0x00000000},
+        {0x0000a2cc, 0x18c43433},
+        {0x0000a2d4, 0x00000000},
+        {0x0000a2dc, 0x00000000},
+        {0x0000a2e0, 0x00000000},
+        {0x0000a2e4, 0x00000000},
+        {0x0000a2e8, 0x00000000},
+        {0x0000a2ec, 0x00000000},
+        {0x0000a2f0, 0x00000000},
+        {0x0000a2f4, 0x00000000},
+        {0x0000a2f8, 0x00000000},
+        {0x0000a344, 0x00000000},
+        {0x0000a34c, 0x00000000},
+        {0x0000a350, 0x0000a000},
+        {0x0000a364, 0x00000000},
+        {0x0000a370, 0x00000000},
+        {0x0000a390, 0x00000001},
+        {0x0000a394, 0x00000444},
+        {0x0000a398, 0x001f0e0f},
+        {0x0000a39c, 0x0075393f},
+        {0x0000a3a0, 0xb79f6427},
+        {0x0000a3a4, 0x000000ff},
+        {0x0000a3a8, 0x3b3b3b3b},
+        {0x0000a3ac, 0x2f2f2f2f},
+        {0x0000a3c0, 0x20202020},
+        {0x0000a3c4, 0x22222220},
+        {0x0000a3c8, 0x20200020},
+        {0x0000a3cc, 0x20202020},
+        {0x0000a3d0, 0x20202020},
+        {0x0000a3d4, 0x20202020},
+        {0x0000a3d8, 0x20202020},
+        {0x0000a3dc, 0x20202020},
+        {0x0000a3e0, 0x20202020},
+        {0x0000a3e4, 0x20202020},
+        {0x0000a3e8, 0x20202020},
+        {0x0000a3ec, 0x20202020},
+        {0x0000a3f0, 0x00000000},
+        {0x0000a3f4, 0x00000006},
+        {0x0000a3f8, 0x0cdbd380},
+        {0x0000a3fc, 0x000f0f01},
+        {0x0000a400, 0x8fa91f01},
+        {0x0000a404, 0x00000000},
+        {0x0000a408, 0x0e79e5c6},
+        {0x0000a40c, 0x00820820},
+        {0x0000a414, 0x1ce739cf},
+        {0x0000a418, 0x2d0019ce},
+        {0x0000a41c, 0x1ce739ce},
+        {0x0000a420, 0x000001ce},
+        {0x0000a424, 0x1ce739ce},
+        {0x0000a428, 0x000001ce},
+        {0x0000a42c, 0x1ce739ce},
+        {0x0000a430, 0x1ce739ce},
+        {0x0000a434, 0x00000000},
+        {0x0000a438, 0x00001801},
+        {0x0000a43c, 0x00000000},
+        {0x0000a440, 0x00000000},
+        {0x0000a444, 0x00000000},
+        {0x0000a448, 0x04000000},
+        {0x0000a44c, 0x00000001},
+        {0x0000a450, 0x00010000},
+        {0x0000a5c4, 0xbfad9d74},
+        {0x0000a5c8, 0x0048060a},
+        {0x0000a5cc, 0x00000637},
+        {0x0000a760, 0x03020100},
+        {0x0000a764, 0x09080504},
+        {0x0000a768, 0x0d0c0b0a},
+        {0x0000a76c, 0x13121110},
+        {0x0000a770, 0x31301514},
+        {0x0000a774, 0x35343332},
+        {0x0000a778, 0x00000036},
+        {0x0000a780, 0x00000838},
+        {0x0000a7c0, 0x00000000},
+        {0x0000a7c4, 0xfffffffc},
+        {0x0000a7c8, 0x00000000},
+        {0x0000a7cc, 0x00000000},
+        {0x0000a7d0, 0x00000000},
+        {0x0000a7d4, 0x00000004},
+        {0x0000a7dc, 0x00000000},
+};
+
+static const u32 ar9485Common_1_1[][2] = {
+        /*  Addr      allmodes */
+        {0x00007010, 0x00000022},
+        {0x00007020, 0x00000000},
+        {0x00007034, 0x00000002},
+        {0x00007038, 0x000004c2},
+};
+
+static const u32 ar9485_1_1_baseband_postamble[][5] = {
+        /* Addr       5G_HT20        5G_HT40       2G_HT40       2G_HT20 */
+        {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+        {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+        {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+        {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+        {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+        {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+        {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+        {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
+        {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+        {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
+        {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+        {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+        {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+        {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
+        {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+        {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+        {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+        {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
+        {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+        {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
+        {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
+        {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+        {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+        {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+        {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+        {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+        {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+        {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+        {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+        {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
+        {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+        {0x0000a2d0, 0x00071981, 0x00071981, 0x00071982, 0x00071982},
+        {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+        {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+};
+
+static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20  */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_1_1_radio_postamble[][2] = {
+        /* Addr        allmodes */
+        {0x0001609c, 0x0b283f31},
+        {0x000160ac, 0x24611800},
+        {0x000160b0, 0x03284f3e},
+        {0x0001610c, 0x00170000},
+        {0x00016140, 0x10804008},
+};
+
+static const u32 ar9485_1_1_mac_postamble[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+        {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+        {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+        {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+        {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+        {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+        {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+        {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+};
+
+static const u32 ar9485_1_1_radio_core[][2] = {
+        /* Addr        allmodes */
+        {0x00016000, 0x36db6db6},
+        {0x00016004, 0x6db6db40},
+        {0x00016008, 0x73800000},
+        {0x0001600c, 0x00000000},
+        {0x00016040, 0x7f80fff8},
+        {0x0001604c, 0x000f0278},
+        {0x00016050, 0x4db6db8c},
+        {0x00016054, 0x6db60000},
+        {0x00016080, 0x00080000},
+        {0x00016084, 0x0e48048c},
+        {0x00016088, 0x14214514},
+        {0x0001608c, 0x119f081e},
+        {0x00016090, 0x24926490},
+        {0x00016098, 0xd28b3330},
+        {0x000160a0, 0xc2108ffe},
+        {0x000160a4, 0x812fc370},
+        {0x000160a8, 0x423c8000},
+        {0x000160b4, 0x92480040},
+        {0x000160c0, 0x006db6db},
+        {0x000160c4, 0x0186db60},
+        {0x000160c8, 0x6db6db6c},
+        {0x000160cc, 0x6de6fbe0},
+        {0x000160d0, 0xf7dfcf3c},
+        {0x00016100, 0x04cb0001},
+        {0x00016104, 0xfff80015},
+        {0x00016108, 0x00080010},
+        {0x00016144, 0x01884080},
+        {0x00016148, 0x00008040},
+        {0x00016240, 0x08400000},
+        {0x00016244, 0x1bf90f00},
+        {0x00016248, 0x00000000},
+        {0x0001624c, 0x00000000},
+        {0x00016280, 0x01000015},
+        {0x00016284, 0x00d30000},
+        {0x00016288, 0x00318000},
+        {0x0001628c, 0x50000000},
+        {0x00016290, 0x4b96210f},
+        {0x00016380, 0x00000000},
+        {0x00016384, 0x00000000},
+        {0x00016388, 0x00800700},
+        {0x0001638c, 0x00800700},
+        {0x00016390, 0x00800700},
+        {0x00016394, 0x00000000},
+        {0x00016398, 0x00000000},
+        {0x0001639c, 0x00000000},
+        {0x000163a0, 0x00000001},
+        {0x000163a4, 0x00000001},
+        {0x000163a8, 0x00000000},
+        {0x000163ac, 0x00000000},
+        {0x000163b0, 0x00000000},
+        {0x000163b4, 0x00000000},
+        {0x000163b8, 0x00000000},
+        {0x000163bc, 0x00000000},
+        {0x000163c0, 0x000000a0},
+        {0x000163c4, 0x000c0000},
+        {0x000163c8, 0x14021402},
+        {0x000163cc, 0x00001402},
+        {0x000163d0, 0x00000000},
+        {0x000163d4, 0x00000000},
+        {0x00016c40, 0x13188278},
+        {0x00016c44, 0x12000000},
+};
+
+static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
+        /* Addr        allmodes */
+        {0x00018c00, 0x10052e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_1_1[][2] = {
+        /* Addr        allmodes */
+        {0x0000a580, 0x00000000},
+        {0x0000a584, 0x00000000},
+        {0x0000a588, 0x00000000},
+        {0x0000a58c, 0x00000000},
+        {0x0000a590, 0x00000000},
+        {0x0000a594, 0x00000000},
+        {0x0000a598, 0x00000000},
+        {0x0000a59c, 0x00000000},
+        {0x0000a5a0, 0x00000000},
+        {0x0000a5a4, 0x00000000},
+        {0x0000a5a8, 0x00000000},
+        {0x0000a5ac, 0x00000000},
+        {0x0000a5b0, 0x00000000},
+        {0x0000a5b4, 0x00000000},
+        {0x0000a5b8, 0x00000000},
+        {0x0000a5bc, 0x00000000},
+};
+
+static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000006, 0x00000006},
+        {0x0000a504, 0x05062002, 0x05062002, 0x03000201, 0x03000201},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x06000203, 0x06000203},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0a000401, 0x0a000401},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x0e000403, 0x0e000403},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x12000405, 0x12000405},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x15000604, 0x15000604},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x18000605, 0x18000605},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x1c000a04, 0x1c000a04},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x21000a06, 0x21000a06},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x29000a24, 0x29000a24},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2f000e21, 0x2f000e21},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000e20, 0x31000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x33000e20, 0x33000e20},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b504, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b508, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b50c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b510, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b514, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b518, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b51c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b520, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b524, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b528, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b52c, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a},
+        {0x0000b530, 0x0000003a, 0x0000003a, 0x0000003a, 0x0000003a},
+        {0x0000b534, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a},
+        {0x0000b538, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b53c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b540, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b544, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b548, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b54c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b550, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b554, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b558, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b55c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b560, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b564, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b568, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b56c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b570, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b574, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b578, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b57c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
+        /* Addr        allmodes */
+        {0x00018c00, 0x10013e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485_1_1_soc_preamble[][2] = {
+        /* Addr        allmodes */
+        {0x00004014, 0xba280400},
+        {0x00004090, 0x00aa10aa},
+        {0x000040a4, 0x00a0c9c9},
+        {0x00007010, 0x00000022},
+        {0x00007020, 0x00000000},
+        {0x00007034, 0x00000002},
+        {0x00007038, 0x000004c2},
+        {0x00007048, 0x00000002},
+};
+
+static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
+        /* Addr        allmodes */
+        {0x0000a398, 0x00000000},
+        {0x0000a39c, 0x6f7f0301},
+        {0x0000a3a0, 0xca9228ee},
+};
+
+static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20  */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
+        /* Addr        5G_HT2        5G_HT40  */
+        {0x00009e00, 0x03721821, 0x03721821},
+        {0x0000a230, 0x0000400b, 0x00004016},
+        {0x0000a254, 0x00000898, 0x00001130},
+};
+
+static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
+        /* Addr        allmodes  */
+        {0x00018c00, 0x10012e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485_common_rx_gain_1_1[][2] = {
+        /* Addr        allmodes */
+        {0x0000a000, 0x00010000},
+        {0x0000a004, 0x00030002},
+        {0x0000a008, 0x00050004},
+        {0x0000a00c, 0x00810080},
+        {0x0000a010, 0x01800082},
+        {0x0000a014, 0x01820181},
+        {0x0000a018, 0x01840183},
+        {0x0000a01c, 0x01880185},
+        {0x0000a020, 0x018a0189},
+        {0x0000a024, 0x02850284},
+        {0x0000a028, 0x02890288},
+        {0x0000a02c, 0x03850384},
+        {0x0000a030, 0x03890388},
+        {0x0000a034, 0x038b038a},
+        {0x0000a038, 0x038d038c},
+        {0x0000a03c, 0x03910390},
+        {0x0000a040, 0x03930392},
+        {0x0000a044, 0x03950394},
+        {0x0000a048, 0x00000396},
+        {0x0000a04c, 0x00000000},
+        {0x0000a050, 0x00000000},
+        {0x0000a054, 0x00000000},
+        {0x0000a058, 0x00000000},
+        {0x0000a05c, 0x00000000},
+        {0x0000a060, 0x00000000},
+        {0x0000a064, 0x00000000},
+        {0x0000a068, 0x00000000},
+        {0x0000a06c, 0x00000000},
+        {0x0000a070, 0x00000000},
+        {0x0000a074, 0x00000000},
+        {0x0000a078, 0x00000000},
+        {0x0000a07c, 0x00000000},
+        {0x0000a080, 0x28282828},
+        {0x0000a084, 0x28282828},
+        {0x0000a088, 0x28282828},
+        {0x0000a08c, 0x28282828},
+        {0x0000a090, 0x28282828},
+        {0x0000a094, 0x21212128},
+        {0x0000a098, 0x171c1c1c},
+        {0x0000a09c, 0x02020212},
+        {0x0000a0a0, 0x00000202},
+        {0x0000a0a4, 0x00000000},
+        {0x0000a0a8, 0x00000000},
+        {0x0000a0ac, 0x00000000},
+        {0x0000a0b0, 0x00000000},
+        {0x0000a0b4, 0x00000000},
+        {0x0000a0b8, 0x00000000},
+        {0x0000a0bc, 0x00000000},
+        {0x0000a0c0, 0x001f0000},
+        {0x0000a0c4, 0x111f1100},
+        {0x0000a0c8, 0x111d111e},
+        {0x0000a0cc, 0x111b111c},
+        {0x0000a0d0, 0x22032204},
+        {0x0000a0d4, 0x22012202},
+        {0x0000a0d8, 0x221f2200},
+        {0x0000a0dc, 0x221d221e},
+        {0x0000a0e0, 0x33013302},
+        {0x0000a0e4, 0x331f3300},
+        {0x0000a0e8, 0x4402331e},
+        {0x0000a0ec, 0x44004401},
+        {0x0000a0f0, 0x441e441f},
+        {0x0000a0f4, 0x55015502},
+        {0x0000a0f8, 0x551f5500},
+        {0x0000a0fc, 0x6602551e},
+        {0x0000a100, 0x66006601},
+        {0x0000a104, 0x661e661f},
+        {0x0000a108, 0x7703661d},
+        {0x0000a10c, 0x77017702},
+        {0x0000a110, 0x00007700},
+        {0x0000a114, 0x00000000},
+        {0x0000a118, 0x00000000},
+        {0x0000a11c, 0x00000000},
+        {0x0000a120, 0x00000000},
+        {0x0000a124, 0x00000000},
+        {0x0000a128, 0x00000000},
+        {0x0000a12c, 0x00000000},
+        {0x0000a130, 0x00000000},
+        {0x0000a134, 0x00000000},
+        {0x0000a138, 0x00000000},
+        {0x0000a13c, 0x00000000},
+        {0x0000a140, 0x001f0000},
+        {0x0000a144, 0x111f1100},
+        {0x0000a148, 0x111d111e},
+        {0x0000a14c, 0x111b111c},
+        {0x0000a150, 0x22032204},
+        {0x0000a154, 0x22012202},
+        {0x0000a158, 0x221f2200},
+        {0x0000a15c, 0x221d221e},
+        {0x0000a160, 0x33013302},
+        {0x0000a164, 0x331f3300},
+        {0x0000a168, 0x4402331e},
+        {0x0000a16c, 0x44004401},
+        {0x0000a170, 0x441e441f},
+        {0x0000a174, 0x55015502},
+        {0x0000a178, 0x551f5500},
+        {0x0000a17c, 0x6602551e},
+        {0x0000a180, 0x66006601},
+        {0x0000a184, 0x661e661f},
+        {0x0000a188, 0x7703661d},
+        {0x0000a18c, 0x77017702},
+        {0x0000a190, 0x00007700},
+        {0x0000a194, 0x00000000},
+        {0x0000a198, 0x00000000},
+        {0x0000a19c, 0x00000000},
+        {0x0000a1a0, 0x00000000},
+        {0x0000a1a4, 0x00000000},
+        {0x0000a1a8, 0x00000000},
+        {0x0000a1ac, 0x00000000},
+        {0x0000a1b0, 0x00000000},
+        {0x0000a1b4, 0x00000000},
+        {0x0000a1b8, 0x00000000},
+        {0x0000a1bc, 0x00000000},
+        {0x0000a1c0, 0x00000000},
+        {0x0000a1c4, 0x00000000},
+        {0x0000a1c8, 0x00000000},
+        {0x0000a1cc, 0x00000000},
+        {0x0000a1d0, 0x00000000},
+        {0x0000a1d4, 0x00000000},
+        {0x0000a1d8, 0x00000000},
+        {0x0000a1dc, 0x00000000},
+        {0x0000a1e0, 0x00000000},
+        {0x0000a1e4, 0x00000000},
+        {0x0000a1e8, 0x00000000},
+        {0x0000a1ec, 0x00000000},
+        {0x0000a1f0, 0x00000396},
+        {0x0000a1f4, 0x00000396},
+        {0x0000a1f8, 0x00000396},
+        {0x0000a1fc, 0x00000296},
+};
+
+static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
+        /* Addr        allmodes */
+        {0x00018c00, 0x10053e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
+        /* Addr        allmodes */
+        {0x0000a000, 0x00060005},
+        {0x0000a004, 0x00810080},
+        {0x0000a008, 0x00830082},
+        {0x0000a00c, 0x00850084},
+        {0x0000a010, 0x01820181},
+        {0x0000a014, 0x01840183},
+        {0x0000a018, 0x01880185},
+        {0x0000a01c, 0x018a0189},
+        {0x0000a020, 0x02850284},
+        {0x0000a024, 0x02890288},
+        {0x0000a028, 0x028b028a},
+        {0x0000a02c, 0x03850384},
+        {0x0000a030, 0x03890388},
+        {0x0000a034, 0x038b038a},
+        {0x0000a038, 0x038d038c},
+        {0x0000a03c, 0x03910390},
+        {0x0000a040, 0x03930392},
+        {0x0000a044, 0x03950394},
+        {0x0000a048, 0x00000396},
+        {0x0000a04c, 0x00000000},
+        {0x0000a050, 0x00000000},
+        {0x0000a054, 0x00000000},
+        {0x0000a058, 0x00000000},
+        {0x0000a05c, 0x00000000},
+        {0x0000a060, 0x00000000},
+        {0x0000a064, 0x00000000},
+        {0x0000a068, 0x00000000},
+        {0x0000a06c, 0x00000000},
+        {0x0000a070, 0x00000000},
+        {0x0000a074, 0x00000000},
+        {0x0000a078, 0x00000000},
+        {0x0000a07c, 0x00000000},
+        {0x0000a080, 0x28282828},
+        {0x0000a084, 0x28282828},
+        {0x0000a088, 0x28282828},
+        {0x0000a08c, 0x28282828},
+        {0x0000a090, 0x28282828},
+        {0x0000a094, 0x24242428},
+        {0x0000a098, 0x171e1e1e},
+        {0x0000a09c, 0x02020b0b},
+        {0x0000a0a0, 0x02020202},
+        {0x0000a0a4, 0x00000000},
+        {0x0000a0a8, 0x00000000},
+        {0x0000a0ac, 0x00000000},
+        {0x0000a0b0, 0x00000000},
+        {0x0000a0b4, 0x00000000},
+        {0x0000a0b8, 0x00000000},
+        {0x0000a0bc, 0x00000000},
+        {0x0000a0c0, 0x22072208},
+        {0x0000a0c4, 0x22052206},
+        {0x0000a0c8, 0x22032204},
+        {0x0000a0cc, 0x22012202},
+        {0x0000a0d0, 0x221f2200},
+        {0x0000a0d4, 0x221d221e},
+        {0x0000a0d8, 0x33023303},
+        {0x0000a0dc, 0x33003301},
+        {0x0000a0e0, 0x331e331f},
+        {0x0000a0e4, 0x4402331d},
+        {0x0000a0e8, 0x44004401},
+        {0x0000a0ec, 0x441e441f},
+        {0x0000a0f0, 0x55025503},
+        {0x0000a0f4, 0x55005501},
+        {0x0000a0f8, 0x551e551f},
+        {0x0000a0fc, 0x6602551d},
+        {0x0000a100, 0x66006601},
+        {0x0000a104, 0x661e661f},
+        {0x0000a108, 0x7703661d},
+        {0x0000a10c, 0x77017702},
+        {0x0000a110, 0x00007700},
+        {0x0000a114, 0x00000000},
+        {0x0000a118, 0x00000000},
+        {0x0000a11c, 0x00000000},
+        {0x0000a120, 0x00000000},
+        {0x0000a124, 0x00000000},
+        {0x0000a128, 0x00000000},
+        {0x0000a12c, 0x00000000},
+        {0x0000a130, 0x00000000},
+        {0x0000a134, 0x00000000},
+        {0x0000a138, 0x00000000},
+        {0x0000a13c, 0x00000000},
+        {0x0000a140, 0x001f0000},
+        {0x0000a144, 0x111f1100},
+        {0x0000a148, 0x111d111e},
+        {0x0000a14c, 0x111b111c},
+        {0x0000a150, 0x22032204},
+        {0x0000a154, 0x22012202},
+        {0x0000a158, 0x221f2200},
+        {0x0000a15c, 0x221d221e},
+        {0x0000a160, 0x33013302},
+        {0x0000a164, 0x331f3300},
+        {0x0000a168, 0x4402331e},
+        {0x0000a16c, 0x44004401},
+        {0x0000a170, 0x441e441f},
+        {0x0000a174, 0x55015502},
+        {0x0000a178, 0x551f5500},
+        {0x0000a17c, 0x6602551e},
+        {0x0000a180, 0x66006601},
+        {0x0000a184, 0x661e661f},
+        {0x0000a188, 0x7703661d},
+        {0x0000a18c, 0x77017702},
+        {0x0000a190, 0x00007700},
+        {0x0000a194, 0x00000000},
+        {0x0000a198, 0x00000000},
+        {0x0000a19c, 0x00000000},
+        {0x0000a1a0, 0x00000000},
+        {0x0000a1a4, 0x00000000},
+        {0x0000a1a8, 0x00000000},
+        {0x0000a1ac, 0x00000000},
+        {0x0000a1b0, 0x00000000},
+        {0x0000a1b4, 0x00000000},
+        {0x0000a1b8, 0x00000000},
+        {0x0000a1bc, 0x00000000},
+        {0x0000a1c0, 0x00000000},
+        {0x0000a1c4, 0x00000000},
+        {0x0000a1c8, 0x00000000},
+        {0x0000a1cc, 0x00000000},
+        {0x0000a1d0, 0x00000000},
+        {0x0000a1d4, 0x00000000},
+        {0x0000a1d8, 0x00000000},
+        {0x0000a1dc, 0x00000000},
+        {0x0000a1e0, 0x00000000},
+        {0x0000a1e4, 0x00000000},
+        {0x0000a1e8, 0x00000000},
+        {0x0000a1ec, 0x00000000},
+        {0x0000a1f0, 0x00000396},
+        {0x0000a1f4, 0x00000396},
+        {0x0000a1f8, 0x00000396},
+        {0x0000a1fc, 0x00000296},
+};
+
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 07f26ee7a723..f75068b4b310 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -62,7 +62,6 @@ struct ath_node;
 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
 
 struct ath_config {
-        u32 ath_aggr_prot;
         u16 txpowlimit;
         u8 cabqReadytime;
 };
@@ -86,33 +85,19 @@ struct ath_config {
 /**
  * enum buffer_type - Buffer type flags
  *
- * @BUF_HT: Send this buffer using HT capabilities
  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  *      (used in aggregation scheduling)
- * @BUF_RETRY: Indicates whether the buffer is retried
  * @BUF_XRETRY: To denote excessive retries of the buffer
  */
 enum buffer_type {
-        BUF_HT                  = BIT(1),
-        BUF_AMPDU               = BIT(2),
-        BUF_AGGR                = BIT(3),
-        BUF_RETRY               = BIT(4),
-        BUF_XRETRY              = BIT(5),
+        BUF_AMPDU               = BIT(0),
+        BUF_AGGR                = BIT(1),
+        BUF_XRETRY              = BIT(2),
 };
 
-#define bf_nframes              bf_state.bfs_nframes
-#define bf_al                   bf_state.bfs_al
-#define bf_frmlen               bf_state.bfs_frmlen
-#define bf_retries              bf_state.bfs_retries
-#define bf_seqno                bf_state.bfs_seqno
-#define bf_tidno                bf_state.bfs_tidno
-#define bf_keyix                bf_state.bfs_keyix
-#define bf_keytype              bf_state.bfs_keytype
-#define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
-#define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 
 #define ATH_TXSTATUS_RING_SIZE 64
@@ -134,13 +119,11 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 /* RX / TX */
 /***********/
 
-#define ATH_MAX_ANTENNA         3
 #define ATH_RXBUF               512
 #define ATH_TXBUF               512
 #define ATH_TXBUF_RESERVE       5
 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 #define ATH_TXMAXTRY            13
-#define ATH_MGT_TXMAXTRY        4
 
 #define TID_TO_WME_AC(_tid)                             \
         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
@@ -148,7 +131,6 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
          WME_AC_VO)
 
-#define ADDBA_EXCHANGE_ATTEMPTS    10
 #define ATH_AGGR_DELIM_SZ          4
 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 /* number of delimiters for encryption padding */
@@ -177,8 +159,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 
 /* returns delimiter padding required given the packet length */
 #define ATH_AGGR_GET_NDELIM(_len)                                       \
-        (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
-          (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
+       (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
+        DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 
 #define BAW_WITHIN(_start, _bawsz, _seqno) \
         ((((_seqno) - (_start)) & 4095) < (_bawsz))
@@ -195,12 +177,13 @@ enum ATH_AGGR_STATUS {
 
 #define ATH_TXFIFO_DEPTH 8
 struct ath_txq {
-        int axq_class;
-        u32 axq_qnum;
+        int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
+        u32 axq_qnum; /* ath9k hardware queue number */
         u32 *axq_link;
         struct list_head axq_q;
         spinlock_t axq_lock;
         u32 axq_depth;
+        u32 axq_ampdu_depth;
         bool stopped;
         bool axq_tx_inprogress;
         struct list_head axq_acq;
@@ -208,27 +191,30 @@ struct ath_txq {
         struct list_head txq_fifo_pending;
         u8 txq_headidx;
         u8 txq_tailidx;
+        int pending_frames;
 };
 
 struct ath_atx_ac {
+        struct ath_txq *txq;
         int sched;
-        int qnum;
         struct list_head list;
         struct list_head tid_q;
+        bool clear_ps_filter;
+};
+
+struct ath_frame_info {
+        int framelen;
+        u32 keyix;
+        enum ath9k_key_type keytype;
+        u8 retries;
+        u16 seqno;
 };
 
 struct ath_buf_state {
-        int bfs_nframes;
-        u16 bfs_al;
-        u16 bfs_frmlen;
-        int bfs_seqno;
-        int bfs_tidno;
-        int bfs_retries;
         u8 bf_type;
         u8 bfs_paprd;
         unsigned long bfs_paprd_timestamp;
-        u32 bfs_keyix;
-        enum ath9k_key_type bfs_keytype;
+        enum ath9k_internal_frame_type bfs_ftype;
 };
 
 struct ath_buf {
@@ -239,14 +225,10 @@ struct ath_buf {
         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
         void *bf_desc;                  /* virtual addr of desc */
         dma_addr_t bf_daddr;            /* physical addr of desc */
-        dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
+        dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
         bool bf_stale;
-        bool bf_isnullfunc;
-        bool bf_tx_aborted;
         u16 bf_flags;
         struct ath_buf_state bf_state;
-        dma_addr_t bf_dmacontext;
-        struct ath_wiphy *aphy;
 };
 
 struct ath_atx_tid {
@@ -254,7 +236,7 @@ struct ath_atx_tid {
         struct list_head buf_q;
         struct ath_node *an;
         struct ath_atx_ac *ac;
-        struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
+        unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
         u16 seq_start;
         u16 seq_next;
         u16 baw_size;
@@ -267,12 +249,18 @@ struct ath_atx_tid {
 };
 
 struct ath_node {
-        struct ath_common *common;
+#ifdef CONFIG_ATH9K_DEBUGFS
+        struct list_head list; /* for sc->nodes */
+        struct ieee80211_sta *sta; /* station struct we're part of */
+#endif
         struct ath_atx_tid tid[WME_NUM_TID];
         struct ath_atx_ac ac[WME_NUM_AC];
+        int ps_key;
+
         u16 maxampdu;
         u8 mpdudensity;
-        int last_rssi;
+
+        bool sleeping;
 };
 
 #define AGGR_CLEANUP         BIT(1)
@@ -281,6 +269,7 @@ struct ath_node {
 
 struct ath_tx_control {
         struct ath_txq *txq;
+        struct ath_node *an;
         int if_id;
         enum ath9k_internal_frame_type frame_type;
         u8 paprd;
@@ -290,15 +279,19 @@ struct ath_tx_control {
 #define ATH_TX_XRETRY       0x02
 #define ATH_TX_BAR          0x04
 
+/**
+ * @txq_map:  Index is mac80211 queue number.  This is
+ *  not necessarily the same as the hardware queue number
+ *  (axq_qnum).
+ */
 struct ath_tx {
         u16 seq_no;
         u32 txqsetup;
-        int hwq_map[WME_NUM_AC];
         spinlock_t txbuflock;
         struct list_head txbuf;
         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
         struct ath_descdma txdma;
-        int pending_frames[WME_NUM_AC];
+        struct ath_txq *txq_map[WME_NUM_AC];
 };
 
 struct ath_rx_edma {
@@ -312,12 +305,13 @@ struct ath_rx {
         u8 rxotherant;
         u32 *rxlink;
         unsigned int rxfilter;
-        spinlock_t rxflushlock;
         spinlock_t rxbuflock;
         struct list_head rxbuf;
         struct ath_descdma rxdma;
         struct ath_buf *rx_bufptr;
         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
+
+        struct sk_buff *frag;
 };
 
 int ath_startrecv(struct ath_softc *sc);
@@ -329,8 +323,7 @@ void ath_rx_cleanup(struct ath_softc *sc);
 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
-int ath_tx_setup(struct ath_softc *sc, int haltype);
-void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
+bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 void ath_draintxq(struct ath_softc *sc,
                      struct ath_txq *txq, bool retry_tx);
 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
@@ -344,13 +337,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
                  struct ath_tx_control *txctl);
 void ath_tx_tasklet(struct ath_softc *sc);
 void ath_tx_edma_tasklet(struct ath_softc *sc);
-void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
-bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
-void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
-                       u16 tid, u16 *ssn);
+int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
+                      u16 tid, u16 *ssn);
 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
-void ath9k_enable_ps(struct ath_softc *sc);
+
+void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
+bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an);
 
 /********/
 /* VIFs */
@@ -358,11 +351,9 @@ void ath9k_enable_ps(struct ath_softc *sc);
 
 struct ath_vif {
         int av_bslot;
+        bool is_bslot_active, primary_sta_vif;
         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
-        enum nl80211_iftype av_opmode;
         struct ath_buf *av_bcbuf;
-        struct ath_tx_control av_btxctl;
-        u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 };
 
 /*******************/
@@ -374,14 +365,14 @@ struct ath_vif {
  * number of BSSIDs) if a given beacon does not go out even after waiting this
  * number of beacon intervals, the game's up.
  */
-#define BSTUCK_THRESH                   (9 * ATH_BCBUF)
+#define BSTUCK_THRESH                   9
 #define ATH_BCBUF                       4
 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 #define ATH_DEFAULT_BMISS_LIMIT         10
 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 
 struct ath_beacon_config {
-        u16 beacon_interval;
+        int beacon_interval;
         u16 listen_interval;
         u16 dtim_period;
         u16 bmiss_timeout;
@@ -398,22 +389,26 @@ struct ath_beacon {
         u32 beaconq;
         u32 bmisscnt;
         u32 ast_be_xmit;
-        u64 bc_tstamp;
+        u32 bc_tstamp;
         struct ieee80211_vif *bslot[ATH_BCBUF];
-        struct ath_wiphy *bslot_aphy[ATH_BCBUF];
         int slottime;
         int slotupdate;
         struct ath9k_tx_queue_info beacon_qi;
         struct ath_descdma bdma;
         struct ath_txq *cabq;
         struct list_head bbuf;
+
+        bool tx_processed;
+        bool tx_last;
 };
 
 void ath_beacon_tasklet(unsigned long data);
 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
-int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
+int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 int ath_beaconq_config(struct ath_softc *sc);
+void ath_set_beacon(struct ath_softc *sc);
+void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
 
 /*******/
 /* ANI */
@@ -423,12 +418,14 @@ int ath_beaconq_config(struct ath_softc *sc);
 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
+#define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 
 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 
 void ath_hw_check(struct work_struct *work);
+void ath_hw_pll_work(struct work_struct *work);
 void ath_paprd_calibrate(struct work_struct *work);
 void ath_ani_calibrate(unsigned long data);
 
@@ -436,14 +433,6 @@ void ath_ani_calibrate(unsigned long data);
 /* BTCOEX */
 /**********/
 
-/* Defines the BT AR_BT_COEX_WGHT used */
-enum ath_stomp_type {
-        ATH_BTCOEX_NO_STOMP,
-        ATH_BTCOEX_STOMP_ALL,
-        ATH_BTCOEX_STOMP_LOW,
-        ATH_BTCOEX_STOMP_NONE
-};
-
 struct ath_btcoex {
         bool hw_timer_enabled;
         spinlock_t btcoex_lock;
@@ -467,26 +456,75 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 
 #define ATH_LED_PIN_DEF                 1
 #define ATH_LED_PIN_9287                8
-#define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
-#define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
-
-enum ath_led_type {
-        ATH_LED_RADIO,
-        ATH_LED_ASSOC,
-        ATH_LED_TX,
-        ATH_LED_RX
-};
-
-struct ath_led {
-        struct ath_softc *sc;
-        struct led_classdev led_cdev;
-        enum ath_led_type led_type;
-        char name[32];
-        bool registered;
-};
+#define ATH_LED_PIN_9300                10
+#define ATH_LED_PIN_9485                6
 
+#ifdef CONFIG_MAC80211_LEDS
 void ath_init_leds(struct ath_softc *sc);
 void ath_deinit_leds(struct ath_softc *sc);
+#else
+static inline void ath_init_leds(struct ath_softc *sc)
+{
+}
+
+static inline void ath_deinit_leds(struct ath_softc *sc)
+{
+}
+#endif
+
+
+/* Antenna diversity/combining */
+#define ATH_ANT_RX_CURRENT_SHIFT 4
+#define ATH_ANT_RX_MAIN_SHIFT 2
+#define ATH_ANT_RX_MASK 0x3
+
+#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
+#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
+#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
+#define ATH_ANT_DIV_COMB_INIT_COUNT 95
+#define ATH_ANT_DIV_COMB_MAX_COUNT 100
+#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
+#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
+
+#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
+#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
+#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
+#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
+
+enum ath9k_ant_div_comb_lna_conf {
+        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
+        ATH_ANT_DIV_COMB_LNA2,
+        ATH_ANT_DIV_COMB_LNA1,
+        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
+};
+
+struct ath_ant_comb {
+        u16 count;
+        u16 total_pkt_count;
+        bool scan;
+        bool scan_not_start;
+        int main_total_rssi;
+        int alt_total_rssi;
+        int alt_recv_cnt;
+        int main_recv_cnt;
+        int rssi_lna1;
+        int rssi_lna2;
+        int rssi_add;
+        int rssi_sub;
+        int rssi_first;
+        int rssi_second;
+        int rssi_third;
+        bool alt_good;
+        int quick_scan_cnt;
+        int main_conf;
+        enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
+        enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
+        int first_bias;
+        int second_bias;
+        bool first_ratio;
+        bool second_ratio;
+        unsigned long scan_start_time;
+};
 
 /********************/
 /* Main driver core */
@@ -501,7 +539,6 @@ void ath_deinit_leds(struct ath_softc *sc);
 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 #define ATH_MAX_SW_RETRIES      10
 #define ATH_CHAN_MAX            255
-#define IEEE80211_WEP_NKID      4       /* number of key ids */
 
 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 #define ATH_RATE_DUMMY_MARKER   0
@@ -516,11 +553,12 @@ void ath_deinit_leds(struct ath_softc *sc);
 #define SC_OP_RXFLUSH                BIT(7)
 #define SC_OP_LED_ASSOCIATED         BIT(8)
 #define SC_OP_LED_ON                 BIT(9)
-#define SC_OP_SCANNING               BIT(10)
 #define SC_OP_TSF_RESET              BIT(11)
 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 #define SC_OP_BT_SCAN                BIT(13)
 #define SC_OP_ANI_RUN                BIT(14)
+#define SC_OP_ENABLE_APM             BIT(15)
+#define SC_OP_PRIM_STA_VIF           BIT(16)
 
 /* Powersave flags */
 #define PS_WAIT_FOR_BEACON        BIT(0)
@@ -528,103 +566,91 @@ void ath_deinit_leds(struct ath_softc *sc);
 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 #define PS_BEACON_SYNC            BIT(4)
-#define PS_NULLFUNC_COMPLETED     BIT(5)
-#define PS_ENABLED                BIT(6)
+#define PS_TSFOOR_SYNC            BIT(5)
 
-struct ath_wiphy;
 struct ath_rate_table;
 
+struct ath9k_vif_iter_data {
+        const u8 *hw_macaddr; /* phy's hardware address, set
+                               * before starting iteration for
+                               * valid bssid mask.
+                               */
+        u8 mask[ETH_ALEN]; /* bssid mask */
+        int naps;      /* number of AP vifs */
+        int nmeshes;   /* number of mesh vifs */
+        int nstations; /* number of station vifs */
+        int nwds;      /* number of nwd vifs */
+        int nadhocs;   /* number of adhoc vifs */
+        int nothers;   /* number of vifs not specified above. */
+};
+
 struct ath_softc {
         struct ieee80211_hw *hw;
         struct device *dev;
 
-        spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
-        struct ath_wiphy *pri_wiphy;
-        struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
-                                       * have NULL entries */
-        int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
         int chan_idx;
         int chan_is_ht;
-        struct ath_wiphy *next_wiphy;
-        struct work_struct chan_work;
-        int wiphy_select_failures;
-        unsigned long wiphy_select_first_fail;
-        struct delayed_work wiphy_work;
-        unsigned long wiphy_scheduler_int;
-        int wiphy_scheduler_index;
+        struct survey_info *cur_survey;
+        struct survey_info survey[ATH9K_NUM_CHANNELS];
 
         struct tasklet_struct intr_tq;
         struct tasklet_struct bcon_tasklet;
         struct ath_hw *sc_ah;
         void __iomem *mem;
         int irq;
-        spinlock_t sc_resetlock;
         spinlock_t sc_serial_rw;
         spinlock_t sc_pm_lock;
+        spinlock_t sc_pcu_lock;
         struct mutex mutex;
         struct work_struct paprd_work;
         struct work_struct hw_check_work;
         struct completion paprd_complete;
 
+        unsigned int hw_busy_count;
+
         u32 intrstatus;
         u32 sc_flags; /* SC_OP_* */
         u16 ps_flags; /* PS_* */
         u16 curtxpow;
-        u8 nbcnvifs;
-        u16 nvifs;
         bool ps_enabled;
         bool ps_idle;
+        short nbcnvifs;
+        short nvifs;
         unsigned long ps_usecount;
 
         struct ath_config config;
         struct ath_rx rx;
         struct ath_tx tx;
         struct ath_beacon beacon;
-        const struct ath_rate_table *cur_rate_table;
-        enum wireless_mode cur_rate_mode;
         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 
-        struct ath_led radio_led;
-        struct ath_led assoc_led;
-        struct ath_led tx_led;
-        struct ath_led rx_led;
-        struct delayed_work ath_led_blink_work;
-        int led_on_duration;
-        int led_off_duration;
-        int led_on_cnt;
-        int led_off_cnt;
+#ifdef CONFIG_MAC80211_LEDS
+        bool led_registered;
+        char led_name[32];
+        struct led_classdev led_cdev;
+#endif
 
-        int beacon_interval;
+        struct ath9k_hw_cal_data caldata;
+        int last_rssi;
 
 #ifdef CONFIG_ATH9K_DEBUGFS
         struct ath9k_debug debug;
+        spinlock_t nodes_lock;
+        struct list_head nodes; /* basically, stations */
+        unsigned int tx_complete_poll_work_seen;
 #endif
         struct ath_beacon_config cur_beacon_conf;
         struct delayed_work tx_complete_work;
+        struct delayed_work hw_pll_work;
         struct ath_btcoex btcoex;
 
         struct ath_descdma txsdma;
-};
 
-struct ath_wiphy {
-        struct ath_softc *sc; /* shared for all virtual wiphys */
-        struct ieee80211_hw *hw;
-        struct ath9k_hw_cal_data caldata;
-        enum ath_wiphy_state {
-                ATH_WIPHY_INACTIVE,
-                ATH_WIPHY_ACTIVE,
-                ATH_WIPHY_PAUSING,
-                ATH_WIPHY_PAUSED,
-                ATH_WIPHY_SCAN,
-        } state;
-        bool idle;
-        int chan_idx;
-        int chan_is_ht;
+        struct ath_ant_comb ant_comb;
 };
 
 void ath9k_tasklet(unsigned long data);
 int ath_reset(struct ath_softc *sc, bool retry_tx);
-int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 int ath_cabq_update(struct ath_softc *);
 
 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
@@ -633,25 +659,25 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 }
 
 extern struct ieee80211_ops ath9k_ops;
-extern int modparam_nohwcrypt;
+extern int ath9k_modparam_nohwcrypt;
 extern int led_blink;
+extern bool is_ath9k_unloaded;
 
 irqreturn_t ath_isr(int irq, void *dev);
+void ath9k_init_crypto(struct ath_softc *sc);
 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
                     const struct ath_bus_ops *bus_ops);
 void ath9k_deinit_device(struct ath_softc *sc);
 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
-void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
-                           struct ath9k_channel *ichan);
-void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                     struct ath9k_channel *hchan);
 
 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
+bool ath9k_uses_beacons(int type);
 
-#ifdef CONFIG_PCI
+#ifdef CONFIG_ATH9K_PCI
 int ath_pci_init(void);
 void ath_pci_exit(void);
 #else
@@ -659,7 +685,7 @@ static inline int ath_pci_init(void) { return 0; };
 static inline void ath_pci_exit(void) {};
 #endif
 
-#ifdef CONFIG_ATHEROS_AR71XX
+#ifdef CONFIG_ATH9K_AHB
 int ath_ahb_init(void);
 void ath_ahb_exit(void);
 #else
@@ -670,27 +696,13 @@ static inline void ath_ahb_exit(void) {};
 void ath9k_ps_wakeup(struct ath_softc *sc);
 void ath9k_ps_restore(struct ath_softc *sc);
 
-void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
-int ath9k_wiphy_add(struct ath_softc *sc);
-int ath9k_wiphy_del(struct ath_wiphy *aphy);
-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
-int ath9k_wiphy_pause(struct ath_wiphy *aphy);
-int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
-int ath9k_wiphy_select(struct ath_wiphy *aphy);
-void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
-void ath9k_wiphy_chan_work(struct work_struct *work);
-bool ath9k_wiphy_started(struct ath_softc *sc);
-void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
-                                  struct ath_wiphy *selected);
-bool ath9k_wiphy_scanning(struct ath_softc *sc);
-void ath9k_wiphy_work(struct work_struct *work);
-bool ath9k_all_wiphys_idle(struct ath_softc *sc);
-void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
-
-void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
-bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
+u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 
 void ath_start_rfkill_poll(struct ath_softc *sc);
 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
+void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               struct ath9k_vif_iter_data *iter_data);
+
 
 #endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 4d4b22d52dfd..d4d8ceced89b 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,12 @@
 
 #define FUDGE 2
 
+static void ath9k_reset_beacon_status(struct ath_softc *sc)
+{
+        sc->beacon.tx_processed = false;
+        sc->beacon.tx_last = false;
+}
+
 /*
  *  This function will modify certain transmit queue properties depending on
  *  the operating mode of the station (AP or AdHoc).  Parameters are AIFS
@@ -28,7 +34,7 @@ int ath_beaconq_config(struct ath_softc *sc)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info qi, qi_be;
-        int qnum;
+        struct ath_txq *txq;
 
         ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
@@ -38,16 +44,16 @@ int ath_beaconq_config(struct ath_softc *sc)
                 qi.tqi_cwmax = 0;
         } else {
                 /* Adhoc mode; important thing is to use 2x cwmin. */
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+                txq = sc->tx.txq_map[WME_AC_BE];
+                ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi_be);
                 qi.tqi_aifs = qi_be.tqi_aifs;
                 qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
                 qi.tqi_cwmax = qi_be.tqi_cwmax;
         }
 
         if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to update h/w beacon queue parameters\n");
+                ath_err(common,
+                        "Unable to update h/w beacon queue parameters\n");
                 return 0;
         } else {
                 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -57,8 +63,8 @@ int ath_beaconq_config(struct ath_softc *sc)
 
 /*
  *  Associates the beacon frame buffer with a transmit descriptor.  Will set
- *  up all required antenna switch parameters, rate codes, and channel flags.
- *  Beacons are always sent out at the lowest rate, and are not retried.
+ *  up rate codes, and channel flags. Beacons are always sent out at the
+ *  lowest rate, and are not retried.
 */
 static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
                              struct ath_buf *bf, int rateidx)
@@ -68,20 +74,16 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_desc *ds;
         struct ath9k_11n_rate_series series[4];
-        int flags, antenna, ctsrate = 0, ctsduration = 0;
+        int flags, ctsrate = 0, ctsduration = 0;
         struct ieee80211_supported_band *sband;
         u8 rate = 0;
 
+        ath9k_reset_beacon_status(sc);
+
         ds = bf->bf_desc;
         flags = ATH9K_TXDESC_NOACK;
 
         ds->ds_link = 0;
-        /*
-         * Switch antenna every beacon.
-         * Should only switch every beacon period, not for every SWBA
-         * XXX assumes two antennae
-         */
-        antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
 
         sband = &sc->sbands[common->hw->conf.channel->band];
         rate = sband->bitrates[rateidx].hw_value;
@@ -103,17 +105,35 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
         memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
         series[0].Tries = 1;
         series[0].Rate = rate;
-        series[0].ChSel = common->tx_chainmask;
+        series[0].ChSel = ath_txchainmask_reduction(sc,
+                        common->tx_chainmask, series[0].Rate);
         series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
         ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
                                      series, 4, 0);
 }
 
+static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_tx_control txctl;
+
+        memset(&txctl, 0, sizeof(struct ath_tx_control));
+        txctl.txq = sc->beacon.cabq;
+
+        ath_dbg(common, ATH_DBG_XMIT,
+                "transmitting CABQ packet, skb: %p\n", skb);
+
+        if (ath_tx_start(hw, skb, &txctl) != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n");
+                dev_kfree_skb_any(skb);
+        }
+}
+
 static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
                                            struct ieee80211_vif *vif)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_buf *bf;
         struct ath_vif *avp;
@@ -122,13 +142,12 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
         struct ieee80211_tx_info *info;
         int cabq_depth;
 
-        if (aphy->state != ATH_WIPHY_ACTIVE)
-                return NULL;
+        ath9k_reset_beacon_status(sc);
 
         avp = (void *)vif->drv_priv;
         cabq = sc->beacon.cabq;
 
-        if (avp->av_bcbuf == NULL)
+        if ((avp->av_bcbuf == NULL) || !avp->is_bslot_active)
                 return NULL;
 
         /* Release the old beacon first */
@@ -136,9 +155,10 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
         bf = avp->av_bcbuf;
         skb = bf->bf_mpdu;
         if (skb) {
-                dma_unmap_single(sc->dev, bf->bf_dmacontext,
+                dma_unmap_single(sc->dev, bf->bf_buf_addr,
                                  skb->len, DMA_TO_DEVICE);
                 dev_kfree_skb_any(skb);
+                bf->bf_buf_addr = 0;
         }
 
         /* Get a new beacon from mac80211 */
@@ -162,14 +182,13 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
         }
 
-        bf->bf_buf_addr = bf->bf_dmacontext =
-                dma_map_single(sc->dev, skb->data,
-                               skb->len, DMA_TO_DEVICE);
+        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+                                         skb->len, DMA_TO_DEVICE);
         if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
-                ath_print(common, ATH_DBG_FATAL,
-                          "dma_mapping_error on beaconing\n");
+                bf->bf_buf_addr = 0;
+                ath_err(common, "dma_mapping_error on beaconing\n");
                 return NULL;
         }
 
@@ -189,8 +208,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
 
         if (skb && cabq_depth) {
                 if (sc->nvifs > 1) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "Flushing previous cabq traffic\n");
+                        ath_dbg(common, ATH_DBG_BEACON,
+                                "Flushing previous cabq traffic\n");
                         ath_draintxq(sc, cabq, false);
                 }
         }
@@ -205,13 +224,13 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
         return bf;
 }
 
-int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
+int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
 {
-        struct ath_softc *sc = aphy->sc;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_vif *avp;
         struct ath_buf *bf;
         struct sk_buff *skb;
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         __le64 tstamp;
 
         avp = (void *)vif->drv_priv;
@@ -224,9 +243,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                                                  struct ath_buf, list);
                 list_del(&avp->av_bcbuf->list);
 
-                if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
-                    sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC ||
-                    sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) {
+                if (ath9k_uses_beacons(vif->type)) {
                         int slot;
                         /*
                          * Assign the vif to a beacon xmit slot. As
@@ -236,6 +253,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                         for (slot = 0; slot < ATH_BCBUF; slot++)
                                 if (sc->beacon.bslot[slot] == NULL) {
                                         avp->av_bslot = slot;
+                                        avp->is_bslot_active = false;
 
                                         /* NB: keep looking for a double slot */
                                         if (slot == 0 || !sc->beacon.bslot[slot-1])
@@ -243,7 +261,6 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                                 }
                         BUG_ON(sc->beacon.bslot[avp->av_bslot] != NULL);
                         sc->beacon.bslot[avp->av_bslot] = vif;
-                        sc->beacon.bslot_aphy[avp->av_bslot] = aphy;
                         sc->nbcnvifs++;
                 }
         }
@@ -252,27 +269,26 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
         bf = avp->av_bcbuf;
         if (bf->bf_mpdu != NULL) {
                 skb = bf->bf_mpdu;
-                dma_unmap_single(sc->dev, bf->bf_dmacontext,
+                dma_unmap_single(sc->dev, bf->bf_buf_addr,
                                  skb->len, DMA_TO_DEVICE);
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
+                bf->bf_buf_addr = 0;
         }
 
         /* NB: the beacon data buffer must be 32-bit aligned. */
         skb = ieee80211_beacon_get(sc->hw, vif);
-        if (skb == NULL) {
-                ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
+        if (skb == NULL)
                 return -ENOMEM;
-        }
 
         tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
-        sc->beacon.bc_tstamp = le64_to_cpu(tstamp);
+        sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp);
         /* Calculate a TSF adjustment factor required for staggered beacons. */
         if (avp->av_bslot > 0) {
                 u64 tsfadjust;
                 int intval;
 
-                intval = sc->beacon_interval ? : ATH_DEFAULT_BINTVAL;
+                intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
 
                 /*
                  * Calculate the TSF offset for this beacon slot, i.e., the
@@ -282,13 +298,12 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                  * adjustment. Other slots are adjusted to get the timestamp
                  * close to the TBTT for the BSS.
                  */
-                tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
-                avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
+                tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
+                avp->tsf_adjust = cpu_to_le64(tsfadjust);
 
-                ath_print(common, ATH_DBG_BEACON,
-                          "stagger beacons, bslot %d intval "
-                          "%u tsfadjust %llu\n",
-                          avp->av_bslot, intval, (unsigned long long)tsfadjust);
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
+                        avp->av_bslot, intval, (unsigned long long)tsfadjust);
 
                 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
                         avp->tsf_adjust;
@@ -296,16 +311,16 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                 avp->tsf_adjust = cpu_to_le64(0);
 
         bf->bf_mpdu = skb;
-        bf->bf_buf_addr = bf->bf_dmacontext =
-                dma_map_single(sc->dev, skb->data,
-                               skb->len, DMA_TO_DEVICE);
+        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+                                         skb->len, DMA_TO_DEVICE);
         if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
-                ath_print(common, ATH_DBG_FATAL,
-                          "dma_mapping_error on beacon alloc\n");
+                bf->bf_buf_addr = 0;
+                ath_err(common, "dma_mapping_error on beacon alloc\n");
                 return -ENOMEM;
         }
+        avp->is_bslot_active = true;
 
         return 0;
 }
@@ -315,19 +330,21 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
         if (avp->av_bcbuf != NULL) {
                 struct ath_buf *bf;
 
+                avp->is_bslot_active = false;
                 if (avp->av_bslot != -1) {
                         sc->beacon.bslot[avp->av_bslot] = NULL;
-                        sc->beacon.bslot_aphy[avp->av_bslot] = NULL;
                         sc->nbcnvifs--;
+                        avp->av_bslot = -1;
                 }
 
                 bf = avp->av_bcbuf;
                 if (bf->bf_mpdu != NULL) {
                         struct sk_buff *skb = bf->bf_mpdu;
-                        dma_unmap_single(sc->dev, bf->bf_dmacontext,
+                        dma_unmap_single(sc->dev, bf->bf_buf_addr,
                                          skb->len, DMA_TO_DEVICE);
                         dev_kfree_skb_any(skb);
                         bf->bf_mpdu = NULL;
+                        bf->bf_buf_addr = 0;
                 }
                 list_add_tail(&bf->list, &sc->beacon.bbuf);
 
@@ -338,15 +355,13 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
 void ath_beacon_tasklet(unsigned long data)
 {
         struct ath_softc *sc = (struct ath_softc *)data;
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_buf *bf = NULL;
         struct ieee80211_vif *vif;
-        struct ath_wiphy *aphy;
         int slot;
-        u32 bfaddr, bc = 0, tsftu;
-        u64 tsf;
-        u16 intval;
+        u32 bfaddr, bc = 0;
 
         /*
          * Check if the previous beacon has gone out.  If
@@ -358,60 +373,65 @@ void ath_beacon_tasklet(unsigned long data)
         if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0) {
                 sc->beacon.bmisscnt++;
 
-                if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "missed %u consecutive beacons\n",
-                                  sc->beacon.bmisscnt);
+                if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "missed %u consecutive beacons\n",
+                                sc->beacon.bmisscnt);
+                        ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+                        if (sc->beacon.bmisscnt > 3)
+                                ath9k_hw_bstuck_nfcal(ah);
                 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "beacon is officially stuck\n");
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "beacon is officially stuck\n");
                         sc->sc_flags |= SC_OP_TSF_RESET;
-                        ath_reset(sc, false);
+                        ath_reset(sc, true);
                 }
 
                 return;
         }
 
-        if (sc->beacon.bmisscnt != 0) {
-                ath_print(common, ATH_DBG_BEACON,
-                          "resume beacon xmit after %u misses\n",
-                          sc->beacon.bmisscnt);
-                sc->beacon.bmisscnt = 0;
-        }
-
         /*
          * Generate beacon frames. we are sending frames
          * staggered so calculate the slot for this frame based
          * on the tsf to safeguard against missing an swba.
          */
 
-        intval = sc->beacon_interval ? : ATH_DEFAULT_BINTVAL;
 
-        tsf = ath9k_hw_gettsf64(ah);
-        tsftu = TSF_TO_TU(tsf>>32, tsf);
-        slot = ((tsftu % intval) * ATH_BCBUF) / intval;
-        /*
-         * Reverse the slot order to get slot 0 on the TBTT offset that does
-         * not require TSF adjustment and other slots adding
-         * slot/ATH_BCBUF * beacon_int to timestamp. For example, with
-         * ATH_BCBUF = 4, we process beacon slots as follows: 3 2 1 0 3 2 1 ..
-         * and slot 0 is at correct offset to TBTT.
-         */
-        slot = ATH_BCBUF - slot - 1;
-        vif = sc->beacon.bslot[slot];
-        aphy = sc->beacon.bslot_aphy[slot];
+        if (ah->opmode == NL80211_IFTYPE_AP) {
+                u16 intval;
+                u32 tsftu;
+                u64 tsf;
+
+                intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
+                tsf = ath9k_hw_gettsf64(ah);
+                tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
+                tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
+                slot = (tsftu % (intval * ATH_BCBUF)) / intval;
+                vif = sc->beacon.bslot[slot];
+
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
+                        slot, tsf, tsftu / ATH_BCBUF, intval, vif);
+        } else {
+                slot = 0;
+                vif = sc->beacon.bslot[slot];
+        }
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
-                  slot, tsf, tsftu, intval, vif);
 
         bfaddr = 0;
         if (vif) {
-                bf = ath_beacon_generate(aphy->hw, vif);
+                bf = ath_beacon_generate(sc->hw, vif);
                 if (bf != NULL) {
                         bfaddr = bf->bf_daddr;
                         bc = 1;
                 }
+
+                if (sc->beacon.bmisscnt != 0) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "resume beacon xmit after %u misses\n",
+                                sc->beacon.bmisscnt);
+                        sc->beacon.bmisscnt = 0;
+                }
         }
 
         /*
@@ -439,16 +459,6 @@ void ath_beacon_tasklet(unsigned long data)
                 sc->beacon.updateslot = OK;
         }
         if (bfaddr != 0) {
-                /*
-                 * Stop any current dma and put the new frame(s) on the queue.
-                 * This should never fail since we check above that no frames
-                 * are still pending on the queue.
-                 */
-                if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                "beacon queue %u did not stop?\n", sc->beacon.beaconq);
-                }
-
                 /* NB: cabq traffic should already be queued and primed */
                 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
                 ath9k_hw_txstart(ah, sc->beacon.beaconq);
@@ -461,13 +471,17 @@ static void ath9k_beacon_init(struct ath_softc *sc,
                               u32 next_beacon,
                               u32 beacon_period)
 {
-        if (beacon_period & ATH9K_BEACON_RESET_TSF)
+        if (sc->sc_flags & SC_OP_TSF_RESET) {
                 ath9k_ps_wakeup(sc);
+                ath9k_hw_reset_tsf(sc->sc_ah);
+        }
 
         ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
 
-        if (beacon_period & ATH9K_BEACON_RESET_TSF)
+        if (sc->sc_flags & SC_OP_TSF_RESET) {
                 ath9k_ps_restore(sc);
+                sc->sc_flags &= ~SC_OP_TSF_RESET;
+        }
 }
 
 /*
@@ -482,32 +496,23 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
         u32 nexttbtt, intval;
 
         /* NB: the beacon interval is kept internally in TU's */
-        intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
+        intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
         intval /= ATH_BCBUF;    /* for staggered beacons */
         nexttbtt = intval;
 
-        if (sc->sc_flags & SC_OP_TSF_RESET)
-                intval |= ATH9K_BEACON_RESET_TSF;
-
         /*
          * In AP mode we enable the beacon timers and SWBA interrupts to
          * prepare beacon frames.
          */
-        intval |= ATH9K_BEACON_ENA;
         ah->imask |= ATH9K_INT_SWBA;
         ath_beaconq_config(sc);
 
         /* Set the computed AP beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_beacon_init(sc, nexttbtt, intval);
         sc->beacon.bmisscnt = 0;
         ath9k_hw_set_interrupts(ah, ah->imask);
-
-        /* Clear the reset TSF flag, so that subsequent beacon updation
-           will not reset the HW TSF. */
-
-        sc->sc_flags &= ~SC_OP_TSF_RESET;
 }
 
 /*
@@ -532,8 +537,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
 
         /* No need to configure beacon if we are not associated */
         if (!common->curaid) {
-                ath_print(common, ATH_DBG_BEACON,
-                         "STA is not yet associated..skipping beacon config\n");
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "STA is not yet associated..skipping beacon config\n");
                 return;
         }
 
@@ -545,8 +550,6 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
          * last beacon we received (which may be none).
          */
         dtimperiod = conf->dtim_period;
-        if (dtimperiod <= 0)            /* NB: 0 if not known */
-                dtimperiod = 1;
         dtimcount = conf->dtim_count;
         if (dtimcount >= dtimperiod)    /* NB: sanity check */
                 dtimcount = 0;
@@ -554,8 +557,6 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
         cfpcount = 0;
 
         sleepduration = conf->listen_interval * intval;
-        if (sleepduration <= 0)
-                sleepduration = intval;
 
         /*
          * Pull nexttbtt forward to reflect the current
@@ -626,89 +627,135 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
         /* TSF out of range threshold fixed at 1 second */
         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
 
-        ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
-        ath_print(common, ATH_DBG_BEACON,
-                  "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
-                  bs.bs_bmissthreshold, bs.bs_sleepduration,
-                  bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
+        ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+                bs.bs_bmissthreshold, bs.bs_sleepduration,
+                bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
 
         /* Set the computed STA beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_hw_set_sta_beacon_timers(ah, &bs);
         ah->imask |= ATH9K_INT_BMISS;
-        ath9k_hw_set_interrupts(ah, ah->imask);
+
+        /*
+         * If the beacon config is called beacause of TSFOOR,
+         * Interrupts will be enabled back at the end of ath9k_tasklet
+         */
+        if (!(sc->ps_flags & PS_TSFOOR_SYNC))
+                ath9k_hw_set_interrupts(ah, ah->imask);
 }
 
 static void ath_beacon_config_adhoc(struct ath_softc *sc,
-                                    struct ath_beacon_config *conf,
-                                    struct ieee80211_vif *vif)
+                                    struct ath_beacon_config *conf)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
-        u64 tsf;
-        u32 tsftu, intval, nexttbtt;
-
-        intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
-
+        u32 tsf, delta, intval, nexttbtt;
 
-        /* Pull nexttbtt forward to reflect the current TSF */
+        ath9k_reset_beacon_status(sc);
 
-        nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
-        if (nexttbtt == 0)
-                nexttbtt = intval;
-        else if (intval)
-                nexttbtt = roundup(nexttbtt, intval);
+        tsf = ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE);
+        intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
 
-        tsf = ath9k_hw_gettsf64(ah);
-        tsftu = TSF_TO_TU((u32)(tsf>>32), (u32)tsf) + FUDGE;
-        do {
-                nexttbtt += intval;
-        } while (nexttbtt < tsftu);
+        if (!sc->beacon.bc_tstamp)
+                nexttbtt = tsf + intval;
+        else {
+                if (tsf > sc->beacon.bc_tstamp)
+                        delta = (tsf - sc->beacon.bc_tstamp);
+                else
+                        delta = (tsf + 1 + (~0U - sc->beacon.bc_tstamp));
+                nexttbtt = tsf + intval - (delta % intval);
+        }
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "IBSS nexttbtt %u intval %u (%u)\n",
-                  nexttbtt, intval, conf->beacon_interval);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "IBSS nexttbtt %u intval %u (%u)\n",
+                nexttbtt, intval, conf->beacon_interval);
 
         /*
          * In IBSS mode enable the beacon timers but only enable SWBA interrupts
          * if we need to manually prepare beacon frames.  Otherwise we use a
          * self-linked tx descriptor and let the hardware deal with things.
          */
-        intval |= ATH9K_BEACON_ENA;
         ah->imask |= ATH9K_INT_SWBA;
 
         ath_beaconq_config(sc);
 
         /* Set the computed ADHOC beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_beacon_init(sc, nexttbtt, intval);
         sc->beacon.bmisscnt = 0;
-        ath9k_hw_set_interrupts(ah, ah->imask);
+        /*
+         * If the beacon config is called beacause of TSFOOR,
+         * Interrupts will be enabled back at the end of ath9k_tasklet
+         */
+        if (!(sc->ps_flags & PS_TSFOOR_SYNC))
+                ath9k_hw_set_interrupts(ah, ah->imask);
 }
 
-void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
+static bool ath9k_allow_beacon_config(struct ath_softc *sc,
+                                      struct ieee80211_vif *vif)
 {
         struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        enum nl80211_iftype iftype;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath_vif *avp = (void *)vif->drv_priv;
 
-        /* Setup the beacon configuration parameters */
-        if (vif) {
-                struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        /*
+         * Can not have different beacon interval on multiple
+         * AP interface case
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+            (sc->nbcnvifs > 1) &&
+            (vif->type == NL80211_IFTYPE_AP) &&
+            (cur_conf->beacon_interval != bss_conf->beacon_int)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Changing beacon interval of multiple \
+                        AP interfaces !\n");
+                return false;
+        }
+        /*
+         * Can not configure station vif's beacon config
+         * while on AP opmode
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+            (vif->type != NL80211_IFTYPE_AP)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "STA vif's beacon not allowed on AP mode\n");
+                return false;
+        }
+        /*
+         * Do not allow beacon config if HW was already configured
+         * with another STA vif
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+            (vif->type == NL80211_IFTYPE_STATION) &&
+            (sc->sc_flags & SC_OP_BEACONS) &&
+            !avp->primary_sta_vif) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Beacon already configured for a station interface\n");
+                return false;
+        }
+        return true;
+}
 
-                iftype = vif->type;
+void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
+{
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
 
-                cur_conf->beacon_interval = bss_conf->beacon_int;
-                cur_conf->dtim_period = bss_conf->dtim_period;
-                cur_conf->listen_interval = 1;
-                cur_conf->dtim_count = 1;
-                cur_conf->bmiss_timeout =
-                        ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
-        } else {
-                iftype = sc->sc_ah->opmode;
-        }
+        if (!ath9k_allow_beacon_config(sc, vif))
+                return;
+
+        /* Setup the beacon configuration parameters */
+        cur_conf->beacon_interval = bss_conf->beacon_int;
+        cur_conf->dtim_period = bss_conf->dtim_period;
+        cur_conf->listen_interval = 1;
+        cur_conf->dtim_count = 1;
+        cur_conf->bmiss_timeout =
+                ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
 
         /*
          * It looks like mac80211 may end up using beacon interval of zero in
@@ -719,22 +766,80 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
         if (cur_conf->beacon_interval == 0)
                 cur_conf->beacon_interval = 100;
 
-        switch (iftype) {
+        /*
+         * We don't parse dtim period from mac80211 during the driver
+         * initialization as it breaks association with hidden-ssid
+         * AP and it causes latency in roaming
+         */
+        if (cur_conf->dtim_period == 0)
+                cur_conf->dtim_period = 1;
+
+        ath_set_beacon(sc);
+}
+
+static bool ath_has_valid_bslot(struct ath_softc *sc)
+{
+        struct ath_vif *avp;
+        int slot;
+        bool found = false;
+
+        for (slot = 0; slot < ATH_BCBUF; slot++) {
+                if (sc->beacon.bslot[slot]) {
+                        avp = (void *)sc->beacon.bslot[slot]->drv_priv;
+                        if (avp->is_bslot_active) {
+                                found = true;
+                                break;
+                        }
+                }
+        }
+        return found;
+}
+
+
+void ath_set_beacon(struct ath_softc *sc)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+
+        switch (sc->sc_ah->opmode) {
         case NL80211_IFTYPE_AP:
-                ath_beacon_config_ap(sc, cur_conf);
+                if (ath_has_valid_bslot(sc))
+                        ath_beacon_config_ap(sc, cur_conf);
                 break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
-                ath_beacon_config_adhoc(sc, cur_conf, vif);
+                ath_beacon_config_adhoc(sc, cur_conf);
                 break;
         case NL80211_IFTYPE_STATION:
                 ath_beacon_config_sta(sc, cur_conf);
                 break;
         default:
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unsupported beaconing mode\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
                 return;
         }
 
         sc->sc_flags |= SC_OP_BEACONS;
 }
+
+void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
+{
+        struct ath_hw *ah = sc->sc_ah;
+
+        if (!ath_has_valid_bslot(sc))
+                return;
+
+        ath9k_ps_wakeup(sc);
+        if (status) {
+                /* Re-enable beaconing */
+                ah->imask |= ATH9K_INT_SWBA;
+                ath9k_hw_set_interrupts(ah, ah->imask);
+        } else {
+                /* Disable SWBA interrupt */
+                ah->imask &= ~ATH9K_INT_SWBA;
+                ath9k_hw_set_interrupts(ah, ah->imask);
+                tasklet_kill(&sc->bcon_tasklet);
+                ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+        }
+        ath9k_ps_restore(sc);
+}
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index fb4ac15f3b93..41ce0b139886 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -35,29 +35,6 @@ struct ath_btcoex_config {
         bool bt_hold_rx_clear;
 };
 
-static const u16 ath_subsysid_tbl[] = {
-        AR9280_COEX2WIRE_SUBSYSID,
-        AT9285_COEX3WIRE_SA_SUBSYSID,
-        AT9285_COEX3WIRE_DA_SUBSYSID
-};
-
-/*
- * Checks the subsystem id of the device to see if it
- * supports btcoex
- */
-bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
-{
-        int i;
-
-        if (!ah->hw_version.subsysid)
-                return false;
-
-        for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
-                if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
-                        return true;
-
-        return false;
-}
 
 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
 {
@@ -74,6 +51,10 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
                 .bt_hold_rx_clear = true,
         };
         u32 i;
+        bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
+
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
 
         btcoex_hw->bt_coex_mode =
                 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
@@ -82,7 +63,7 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
                 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
                 SM(ath_bt_config.bt_mode, AR_BT_MODE) |
                 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
-                SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
+                SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
                 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
                 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
                 SM(qnum, AR_BT_QCU_THRESH);
@@ -165,18 +146,39 @@ void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
 }
 EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
 
+
 static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
 {
         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
+        u32  val;
 
         /*
          * Program coex mode and weight registers to
          * enable coex 3-wire
          */
         REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
-        REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
         REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
 
+
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ah->bt_coex_wlan_weight[0]);
+                REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ah->bt_coex_wlan_weight[1]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ah->bt_coex_bt_weight[0]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ah->bt_coex_bt_weight[1]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ah->bt_coex_bt_weight[2]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ah->bt_coex_bt_weight[3]);
+
+        } else
+                REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
+
+
+
+        if (AR_SREV_9271(ah)) {
+                val = REG_READ(ah, 0x50040);
+                val &= 0xFFFFFEFF;
+                REG_WRITE(ah, 0x50040, val);
+        }
+
         REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
         REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
 
@@ -218,10 +220,86 @@ void ath9k_hw_btcoex_disable(struct ath_hw *ah)
 
         if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
                 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
-                REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
                 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
+
+                if (AR_SREV_9300_20_OR_LATER(ah)) {
+                        REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
+                        REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
+                } else
+                        REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
+
         }
 
         ah->btcoex_hw.enabled = false;
 }
 EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
+
+static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
+                         enum ath_stomp_type stomp_type)
+{
+        ah->bt_coex_bt_weight[0] = AR9300_BT_WGHT;
+        ah->bt_coex_bt_weight[1] = AR9300_BT_WGHT;
+        ah->bt_coex_bt_weight[2] = AR9300_BT_WGHT;
+        ah->bt_coex_bt_weight[3] = AR9300_BT_WGHT;
+
+
+        switch (stomp_type) {
+        case ATH_BTCOEX_STOMP_ALL:
+                ah->bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
+                ah->bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
+                break;
+        case ATH_BTCOEX_STOMP_LOW:
+                ah->bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
+                ah->bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
+                break;
+        case ATH_BTCOEX_STOMP_NONE:
+                ah->bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
+                ah->bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
+                break;
+
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "Invalid Stomptype\n");
+                break;
+        }
+
+        ath9k_hw_btcoex_enable(ah);
+}
+
+/*
+ * Configures appropriate weight based on stomp type.
+ */
+void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
+                              enum ath_stomp_type stomp_type)
+{
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                ar9003_btcoex_bt_stomp(ah, stomp_type);
+                return;
+        }
+
+        switch (stomp_type) {
+        case ATH_BTCOEX_STOMP_ALL:
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                AR_STOMP_ALL_WLAN_WGHT);
+                break;
+        case ATH_BTCOEX_STOMP_LOW:
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                AR_STOMP_LOW_WLAN_WGHT);
+                break;
+        case ATH_BTCOEX_STOMP_NONE:
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                AR_STOMP_NONE_WLAN_WGHT);
+                break;
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "Invalid Stomptype\n");
+                break;
+        }
+
+        ath9k_hw_btcoex_enable(ah);
+}
+EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 1ee5a15ccbb1..234f77689b14 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,9 +19,13 @@
 
 #include "hw.h"
 
-#define ATH_WLANACTIVE_GPIO     5
-#define ATH_BTACTIVE_GPIO       6
-#define ATH_BTPRIORITY_GPIO     7
+#define ATH_WLANACTIVE_GPIO_9280     5
+#define ATH_BTACTIVE_GPIO_9280       6
+#define ATH_BTPRIORITY_GPIO_9285     7
+
+#define ATH_WLANACTIVE_GPIO_9300     5
+#define ATH_BTACTIVE_GPIO_9300       4
+#define ATH_BTPRIORITY_GPIO_9300     8
 
 #define ATH_BTCOEX_DEF_BT_PERIOD  45
 #define ATH_BTCOEX_DEF_DUTY_CYCLE 55
@@ -32,6 +36,14 @@
 #define ATH_BT_CNT_THRESHOLD           3
 #define ATH_BT_CNT_SCAN_THRESHOLD      15
 
+/* Defines the BT AR_BT_COEX_WGHT used */
+enum ath_stomp_type {
+        ATH_BTCOEX_NO_STOMP,
+        ATH_BTCOEX_STOMP_ALL,
+        ATH_BTCOEX_STOMP_LOW,
+        ATH_BTCOEX_STOMP_NONE
+};
+
 enum ath_btcoex_scheme {
         ATH_BTCOEX_CFG_NONE,
         ATH_BTCOEX_CFG_2WIRE,
@@ -49,7 +61,6 @@ struct ath_btcoex_hw {
         u32 bt_coex_mode2;      /* Register setting for AR_BT_COEX_MODE2 */
 };
 
-bool ath9k_hw_btcoex_supported(struct ath_hw *ah);
 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah);
 void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah);
 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum);
@@ -58,5 +69,7 @@ void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
                                 u32 wlan_weight);
 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
 void ath9k_hw_btcoex_disable(struct ath_hw *ah);
+void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
+                              enum ath_stomp_type stomp_type);
 
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 45208690c0ec..a1250c586e40 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,8 +19,7 @@
 
 /* Common calibration code */
 
-/* We can tune this as we go by monitoring really low values */
-#define ATH9K_NF_TOO_LOW        -60
+#define ATH9K_NF_TOO_HIGH       -60
 
 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
 {
@@ -45,12 +44,46 @@ static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
         return nfval;
 }
 
-static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
+static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah,
+                                                    struct ath9k_channel *chan)
+{
+        struct ath_nf_limits *limit;
+
+        if (!chan || IS_CHAN_2GHZ(chan))
+                limit = &ah->nf_2g;
+        else
+                limit = &ah->nf_5g;
+
+        return limit;
+}
+
+static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
+                                   struct ath9k_channel *chan)
+{
+        return ath9k_hw_get_nf_limits(ah, chan)->nominal;
+}
+
+
+static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
+                                              struct ath9k_hw_cal_data *cal,
                                               int16_t *nfarray)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_conf *conf = &common->hw->conf;
+        struct ath_nf_limits *limit;
+        struct ath9k_nfcal_hist *h;
+        bool high_nf_mid = false;
+        u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
         int i;
 
+        h = cal->nfCalHist;
+        limit = ath9k_hw_get_nf_limits(ah, ah->curchan);
+
         for (i = 0; i < NUM_NF_READINGS; i++) {
+                if (!(chainmask & (1 << i)) ||
+                    ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf)))
+                        continue;
+
                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
 
                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
@@ -63,7 +96,39 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
                         h[i].privNF =
                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
                 }
+
+                if (!h[i].privNF)
+                        continue;
+
+                if (h[i].privNF > limit->max) {
+                        high_nf_mid = true;
+
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NFmid[%d] (%d) > MAX (%d), %s\n",
+                                i, h[i].privNF, limit->max,
+                                (cal->nfcal_interference ?
+                                 "not corrected (due to interference)" :
+                                 "correcting to MAX"));
+
+                        /*
+                         * Normally we limit the average noise floor by the
+                         * hardware specific maximum here. However if we have
+                         * encountered stuck beacons because of interference,
+                         * we bypass this limit here in order to better deal
+                         * with our environment.
+                         */
+                        if (!cal->nfcal_interference)
+                                h[i].privNF = limit->max;
+                }
         }
+
+        /*
+         * If the noise floor seems normal for all chains, assume that
+         * there is no significant interference in the environment anymore.
+         * Re-enable the enforcement of the NF maximum again.
+         */
+        if (!high_nf_mid)
+                cal->nfcal_interference = false;
 }
 
 static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
@@ -104,19 +169,6 @@ void ath9k_hw_reset_calibration(struct ath_hw *ah,
         ah->cal_samples = 0;
 }
 
-static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
-                                   struct ath9k_channel *chan)
-{
-        struct ath_nf_limits *limit;
-
-        if (!chan || IS_CHAN_2GHZ(chan))
-                limit = &ah->nf_2g;
-        else
-                limit = &ah->nf_5g;
-
-        return limit->nominal;
-}
-
 /* This is done for the currently configured channel */
 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
 {
@@ -134,18 +186,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
                 return true;
 
         if (currCal->calState != CAL_DONE) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Calibration state incorrect, %d\n",
-                          currCal->calState);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Calibration state incorrect, %d\n",
+                        currCal->calState);
                 return true;
         }
 
-        if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
+        if (!(ah->supp_cals & currCal->calData->calType))
                 return true;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "Resetting Cal %d state for channel %u\n",
-                  currCal->calData->calType, conf->channel->center_freq);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "Resetting Cal %d state for channel %u\n",
+                currCal->calData->calType, conf->channel->center_freq);
 
         ah->caldata->CalValid &= ~currCal->calData->calType;
         currCal->calState = CAL_WAITING;
@@ -179,6 +231,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
         int32_t val;
         u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_conf *conf = &common->hw->conf;
         s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
 
         if (ah->caldata)
@@ -188,6 +241,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
                 if (chainmask & (1 << i)) {
                         s16 nfval;
 
+                        if ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf))
+                                continue;
+
                         if (h)
                                 nfval = h[i].privNF;
                         else
@@ -216,7 +272,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
          * since 250us often results in NF load timeout and causes deaf
          * condition during stress testing 12/12/2009
          */
-        for (j = 0; j < 1000; j++) {
+        for (j = 0; j < 10000; j++) {
                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
                      AR_PHY_AGC_CONTROL_NF) == 0)
                         break;
@@ -232,10 +288,10 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
          * here, the baseband nf cal will just be capped by our present
          * noisefloor until the next calibration timer.
          */
-        if (j == 1000) {
-                ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
-                          "to load: AR_PHY_AGC_CONTROL=0x%x\n",
-                          REG_READ(ah, AR_PHY_AGC_CONTROL));
+        if (j == 10000) {
+                ath_dbg(common, ATH_DBG_ANY,
+                        "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
+                        REG_READ(ah, AR_PHY_AGC_CONTROL));
                 return;
         }
 
@@ -247,6 +303,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
         ENABLE_REGWRITE_BUFFER(ah);
         for (i = 0; i < NUM_NF_READINGS; i++) {
                 if (chainmask & (1 << i)) {
+                        if ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf))
+                                continue;
+
                         val = REG_READ(ah, ah->nf_regs[i]);
                         val &= 0xFFFFFE00;
                         val |= (((u32) (-50) << 1) & 0x1ff);
@@ -254,7 +313,6 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
                 }
         }
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 
@@ -273,19 +331,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
                 if (!nf[i])
                         continue;
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "NF calibrated [%s] [chain %d] is %d\n",
-                          (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "NF calibrated [%s] [chain %d] is %d\n",
+                        (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
 
-                if (nf[i] > limit->max) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NF[%d] (%d) > MAX (%d), correcting to MAX",
-                                  i, nf[i], limit->max);
+                if (nf[i] > ATH9K_NF_TOO_HIGH) {
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
+                                i, nf[i], ATH9K_NF_TOO_HIGH);
                         nf[i] = limit->max;
                 } else if (nf[i] < limit->min) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NF[%d] (%d) < MIN (%d), correcting to NOM",
-                                  i, nf[i], limit->min);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
+                                i, nf[i], limit->min);
                         nf[i] = limit->nominal;
                 }
         }
@@ -300,34 +358,33 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
         struct ieee80211_channel *c = chan->chan;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
 
-        if (!caldata)
-                return false;
-
         chan->channelFlags &= (~CHANNEL_CW_INT);
         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "NF did not complete in calibration window\n");
-                nf = 0;
-                caldata->rawNoiseFloor = nf;
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "NF did not complete in calibration window\n");
+                return false;
+        }
+
+        ath9k_hw_do_getnf(ah, nfarray);
+        ath9k_hw_nf_sanitize(ah, nfarray);
+        nf = nfarray[0];
+        if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
+            && nf > nfThresh) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "noise floor failed detected; detected %d, threshold %d\n",
+                        nf, nfThresh);
+                chan->channelFlags |= CHANNEL_CW_INT;
+        }
+
+        if (!caldata) {
+                chan->noisefloor = nf;
                 return false;
-        } else {
-                ath9k_hw_do_getnf(ah, nfarray);
-                ath9k_hw_nf_sanitize(ah, nfarray);
-                nf = nfarray[0];
-                if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
-                    && nf > nfThresh) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "noise floor failed detected; "
-                                  "detected %d, threshold %d\n",
-                                  nf, nfThresh);
-                        chan->channelFlags |= CHANNEL_CW_INT;
-                }
         }
 
         h = caldata->nfCalHist;
         caldata->nfcal_pending = false;
-        ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
-        caldata->rawNoiseFloor = h[0].privNF;
+        ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
+        chan->noisefloor = h[0].privNF;
         return true;
 }
 
@@ -338,9 +395,8 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
         s16 default_nf;
         int i, j;
 
-        if (!ah->caldata)
-                return;
-
+        ah->caldata->channel = chan->channel;
+        ah->caldata->channelFlags = chan->channelFlags & ~CHANNEL_CW_INT;
         h = ah->caldata->nfCalHist;
         default_nf = ath9k_hw_get_default_nf(ah, chan);
         for (i = 0; i < NUM_NF_READINGS; i++) {
@@ -353,11 +409,28 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
         }
 }
 
-s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
+
+void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
 {
-        if (!ah->caldata || !ah->caldata->rawNoiseFloor)
-                return ath9k_hw_get_default_nf(ah, chan);
+        struct ath9k_hw_cal_data *caldata = ah->caldata;
+
+        if (unlikely(!caldata))
+                return;
 
-        return ah->caldata->rawNoiseFloor;
+        /*
+         * If beacons are stuck, the most likely cause is interference.
+         * Triggering a noise floor calibration at this point helps the
+         * hardware adapt to a noisy environment much faster.
+         * To ensure that we recover from stuck beacons quickly, let
+         * the baseband update the internal NF value itself, similar to
+         * what is being done after a full reset.
+         */
+        if (!caldata->nfcal_pending)
+                ath9k_hw_start_nfcal(ah, true);
+        else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
+                ath9k_hw_getnf(ah, ah->curchan);
+
+        caldata->nfcal_interference = true;
 }
-EXPORT_SYMBOL(ath9k_hw_getchan_noise);
+EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
+
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 0a304b3eeeb6..1bef41d1b1ff 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -58,14 +58,6 @@ struct ar5416IniArray {
                 }                                                       \
         } while (0)
 
-enum ath9k_cal_types {
-        ADC_DC_INIT_CAL = 0x1,
-        ADC_GAIN_CAL = 0x2,
-        ADC_DC_CAL = 0x4,
-        IQ_MISMATCH_CAL = 0x8,
-        TEMP_COMP_CAL = 0x10,
-};
-
 enum ath9k_cal_state {
         CAL_INACTIVE,
         CAL_WAITING,
@@ -80,7 +72,7 @@ enum ath9k_cal_state {
 #define PER_MAX_LOG_COUNT  10
 
 struct ath9k_percal_data {
-        enum ath9k_cal_types calType;
+        u32 calType;
         u32 calNumSamples;
         u32 calCountMax;
         void (*calCollect) (struct ath_hw *);
@@ -113,7 +105,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
 bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan);
 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
                                   struct ath9k_channel *chan);
-s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
+void ath9k_hw_bstuck_nfcal(struct ath_hw *ah);
 void ath9k_hw_reset_calibration(struct ath_hw *ah,
                                 struct ath9k_cal_list *currCal);
 
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
index c86f7d3593ab..fa6bd2d189e5 100644
--- a/drivers/net/wireless/ath/ath9k/common.c
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -46,12 +46,17 @@ int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb)
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
 
         if (tx_info->control.hw_key) {
-                if (tx_info->control.hw_key->alg == ALG_WEP)
+                switch (tx_info->control.hw_key->cipher) {
+                case WLAN_CIPHER_SUITE_WEP40:
+                case WLAN_CIPHER_SUITE_WEP104:
                         return ATH9K_KEY_TYPE_WEP;
-                else if (tx_info->control.hw_key->alg == ALG_TKIP)
+                case WLAN_CIPHER_SUITE_TKIP:
                         return ATH9K_KEY_TYPE_TKIP;
-                else if (tx_info->control.hw_key->alg == ALG_CCMP)
+                case WLAN_CIPHER_SUITE_CCMP:
                         return ATH9K_KEY_TYPE_AES;
+                default:
+                        break;
+                }
         }
 
         return ATH9K_KEY_TYPE_CLEAR;
@@ -102,26 +107,23 @@ static u32 ath9k_get_extchanmode(struct ieee80211_channel *chan,
 /*
  * Update internal channel flags.
  */
-void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-                               struct ath9k_channel *ichan)
+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
+                               struct ieee80211_channel *chan,
+                               enum nl80211_channel_type channel_type)
 {
-        struct ieee80211_channel *chan = hw->conf.channel;
-        struct ieee80211_conf *conf = &hw->conf;
-
         ichan->channel = chan->center_freq;
         ichan->chan = chan;
 
         if (chan->band == IEEE80211_BAND_2GHZ) {
                 ichan->chanmode = CHANNEL_G;
-                ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
+                ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
         } else {
                 ichan->chanmode = CHANNEL_A;
                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
         }
 
-        if (conf_is_ht(conf))
-                ichan->chanmode = ath9k_get_extchanmode(chan,
-                                                        conf->channel_type);
+        if (channel_type != NL80211_CHAN_NO_HT)
+                ichan->chanmode = ath9k_get_extchanmode(chan, channel_type);
 }
 EXPORT_SYMBOL(ath9k_cmn_update_ichannel);
 
@@ -137,270 +139,12 @@ struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
 
         chan_idx = curchan->hw_value;
         channel = &ah->channels[chan_idx];
-        ath9k_cmn_update_ichannel(hw, channel);
+        ath9k_cmn_update_ichannel(channel, curchan, hw->conf.channel_type);
 
         return channel;
 }
 EXPORT_SYMBOL(ath9k_cmn_get_curchannel);
 
-static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
-                           struct ath9k_keyval *hk, const u8 *addr,
-                           bool authenticator)
-{
-        struct ath_hw *ah = common->ah;
-        const u8 *key_rxmic;
-        const u8 *key_txmic;
-
-        key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
-        key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
-
-        if (addr == NULL) {
-                /*
-                 * Group key installation - only two key cache entries are used
-                 * regardless of splitmic capability since group key is only
-                 * used either for TX or RX.
-                 */
-                if (authenticator) {
-                        memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
-                        memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
-                } else {
-                        memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
-                        memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
-                }
-                return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
-        }
-        if (!common->splitmic) {
-                /* TX and RX keys share the same key cache entry. */
-                memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
-                memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
-                return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
-        }
-
-        /* Separate key cache entries for TX and RX */
-
-        /* TX key goes at first index, RX key at +32. */
-        memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
-        if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
-                /* TX MIC entry failed. No need to proceed further */
-                ath_print(common, ATH_DBG_FATAL,
-                          "Setting TX MIC Key Failed\n");
-                return 0;
-        }
-
-        memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
-        /* XXX delete tx key on failure? */
-        return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
-}
-
-static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
-{
-        int i;
-
-        for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
-                if (test_bit(i, common->keymap) ||
-                    test_bit(i + 64, common->keymap))
-                        continue; /* At least one part of TKIP key allocated */
-                if (common->splitmic &&
-                    (test_bit(i + 32, common->keymap) ||
-                     test_bit(i + 64 + 32, common->keymap)))
-                        continue; /* At least one part of TKIP key allocated */
-
-                /* Found a free slot for a TKIP key */
-                return i;
-        }
-        return -1;
-}
-
-static int ath_reserve_key_cache_slot(struct ath_common *common,
-                                      enum ieee80211_key_alg alg)
-{
-        int i;
-
-        if (alg == ALG_TKIP)
-                return ath_reserve_key_cache_slot_tkip(common);
-
-        /* First, try to find slots that would not be available for TKIP. */
-        if (common->splitmic) {
-                for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
-                        if (!test_bit(i, common->keymap) &&
-                            (test_bit(i + 32, common->keymap) ||
-                             test_bit(i + 64, common->keymap) ||
-                             test_bit(i + 64 + 32, common->keymap)))
-                                return i;
-                        if (!test_bit(i + 32, common->keymap) &&
-                            (test_bit(i, common->keymap) ||
-                             test_bit(i + 64, common->keymap) ||
-                             test_bit(i + 64 + 32, common->keymap)))
-                                return i + 32;
-                        if (!test_bit(i + 64, common->keymap) &&
-                            (test_bit(i , common->keymap) ||
-                             test_bit(i + 32, common->keymap) ||
-                             test_bit(i + 64 + 32, common->keymap)))
-                                return i + 64;
-                        if (!test_bit(i + 64 + 32, common->keymap) &&
-                            (test_bit(i, common->keymap) ||
-                             test_bit(i + 32, common->keymap) ||
-                             test_bit(i + 64, common->keymap)))
-                                return i + 64 + 32;
-                }
-        } else {
-                for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
-                        if (!test_bit(i, common->keymap) &&
-                            test_bit(i + 64, common->keymap))
-                                return i;
-                        if (test_bit(i, common->keymap) &&
-                            !test_bit(i + 64, common->keymap))
-                                return i + 64;
-                }
-        }
-
-        /* No partially used TKIP slots, pick any available slot */
-        for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
-                /* Do not allow slots that could be needed for TKIP group keys
-                 * to be used. This limitation could be removed if we know that
-                 * TKIP will not be used. */
-                if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
-                        continue;
-                if (common->splitmic) {
-                        if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
-                                continue;
-                        if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
-                                continue;
-                }
-
-                if (!test_bit(i, common->keymap))
-                        return i; /* Found a free slot for a key */
-        }
-
-        /* No free slot found */
-        return -1;
-}
-
-/*
- * Configure encryption in the HW.
- */
-int ath9k_cmn_key_config(struct ath_common *common,
-                         struct ieee80211_vif *vif,
-                         struct ieee80211_sta *sta,
-                         struct ieee80211_key_conf *key)
-{
-        struct ath_hw *ah = common->ah;
-        struct ath9k_keyval hk;
-        const u8 *mac = NULL;
-        u8 gmac[ETH_ALEN];
-        int ret = 0;
-        int idx;
-
-        memset(&hk, 0, sizeof(hk));
-
-        switch (key->alg) {
-        case ALG_WEP:
-                hk.kv_type = ATH9K_CIPHER_WEP;
-                break;
-        case ALG_TKIP:
-                hk.kv_type = ATH9K_CIPHER_TKIP;
-                break;
-        case ALG_CCMP:
-                hk.kv_type = ATH9K_CIPHER_AES_CCM;
-                break;
-        default:
-                return -EOPNOTSUPP;
-        }
-
-        hk.kv_len = key->keylen;
-        memcpy(hk.kv_val, key->key, key->keylen);
-
-        if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
-                switch (vif->type) {
-                case NL80211_IFTYPE_AP:
-                        memcpy(gmac, vif->addr, ETH_ALEN);
-                        gmac[0] |= 0x01;
-                        mac = gmac;
-                        idx = ath_reserve_key_cache_slot(common, key->alg);
-                        break;
-                case NL80211_IFTYPE_ADHOC:
-                        if (!sta) {
-                                idx = key->keyidx;
-                                break;
-                        }
-                        memcpy(gmac, sta->addr, ETH_ALEN);
-                        gmac[0] |= 0x01;
-                        mac = gmac;
-                        idx = ath_reserve_key_cache_slot(common, key->alg);
-                        break;
-                default:
-                        idx = key->keyidx;
-                        break;
-                }
-        } else if (key->keyidx) {
-                if (WARN_ON(!sta))
-                        return -EOPNOTSUPP;
-                mac = sta->addr;
-
-                if (vif->type != NL80211_IFTYPE_AP) {
-                        /* Only keyidx 0 should be used with unicast key, but
-                         * allow this for client mode for now. */
-                        idx = key->keyidx;
-                } else
-                        return -EIO;
-        } else {
-                if (WARN_ON(!sta))
-                        return -EOPNOTSUPP;
-                mac = sta->addr;
-
-                idx = ath_reserve_key_cache_slot(common, key->alg);
-        }
-
-        if (idx < 0)
-                return -ENOSPC; /* no free key cache entries */
-
-        if (key->alg == ALG_TKIP)
-                ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
-                                      vif->type == NL80211_IFTYPE_AP);
-        else
-                ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
-
-        if (!ret)
-                return -EIO;
-
-        set_bit(idx, common->keymap);
-        if (key->alg == ALG_TKIP) {
-                set_bit(idx + 64, common->keymap);
-                if (common->splitmic) {
-                        set_bit(idx + 32, common->keymap);
-                        set_bit(idx + 64 + 32, common->keymap);
-                }
-        }
-
-        return idx;
-}
-EXPORT_SYMBOL(ath9k_cmn_key_config);
-
-/*
- * Delete Key.
- */
-void ath9k_cmn_key_delete(struct ath_common *common,
-                          struct ieee80211_key_conf *key)
-{
-        struct ath_hw *ah = common->ah;
-
-        ath9k_hw_keyreset(ah, key->hw_key_idx);
-        if (key->hw_key_idx < IEEE80211_WEP_NKID)
-                return;
-
-        clear_bit(key->hw_key_idx, common->keymap);
-        if (key->alg != ALG_TKIP)
-                return;
-
-        clear_bit(key->hw_key_idx + 64, common->keymap);
-        if (common->splitmic) {
-                ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
-                clear_bit(key->hw_key_idx + 32, common->keymap);
-                clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
-        }
-}
-EXPORT_SYMBOL(ath9k_cmn_key_delete);
-
 int ath9k_cmn_count_streams(unsigned int chainmask, int max)
 {
         int streams = 0;
@@ -414,6 +158,17 @@ int ath9k_cmn_count_streams(unsigned int chainmask, int max)
 }
 EXPORT_SYMBOL(ath9k_cmn_count_streams);
 
+void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
+                            u16 new_txpow, u16 *txpower)
+{
+        if (cur_txpow != new_txpow) {
+                ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
+                /* read back in case value is clamped */
+                *txpower = ath9k_hw_regulatory(ah)->power_limit;
+        }
+}
+EXPORT_SYMBOL(ath9k_cmn_update_txpow);
+
 static int __init ath9k_cmn_init(void)
 {
         return 0;
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
index 97809d39c73f..77ec288b5a70 100644
--- a/drivers/net/wireless/ath/ath9k/common.h
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,24 +17,22 @@
 #include <net/mac80211.h>
 
 #include "../ath.h"
-#include "../debug.h"
 
 #include "hw.h"
 #include "hw-ops.h"
 
 /* Common header for Atheros 802.11n base driver cores */
 
-#define IEEE80211_WEP_NKID 4
-
 #define WME_NUM_TID             16
 #define WME_BA_BMP_SIZE         64
 #define WME_MAX_BA              WME_BA_BMP_SIZE
 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 
-#define WME_AC_BE   0
-#define WME_AC_BK   1
-#define WME_AC_VI   2
-#define WME_AC_VO   3
+/* These must match mac80211 skb queue mapping numbers */
+#define WME_AC_VO   0
+#define WME_AC_VI   1
+#define WME_AC_BE   2
+#define WME_AC_BK   3
 #define WME_NUM_AC  4
 
 #define ATH_RSSI_DUMMY_MARKER   0x127
@@ -54,14 +52,13 @@
 
 int ath9k_cmn_padpos(__le16 frame_control);
 int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb);
-void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-                               struct ath9k_channel *ichan);
+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
+                               struct ieee80211_channel *chan,
+                               enum nl80211_channel_type channel_type);
 struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
                                                struct ath_hw *ah);
-int ath9k_cmn_key_config(struct ath_common *common,
-                         struct ieee80211_vif *vif,
-                         struct ieee80211_sta *sta,
-                         struct ieee80211_key_conf *key);
-void ath9k_cmn_key_delete(struct ath_common *common,
-                          struct ieee80211_key_conf *key);
 int ath9k_cmn_count_streams(unsigned int chainmask, int max);
+void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common,
+                                  enum ath_stomp_type stomp_type);
+void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
+                            u16 new_txpow, u16 *txpower);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 54aae931424e..d55ffd7d4bd2 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,6 +15,7 @@
  */
 
 #include <linux/slab.h>
+#include <linux/vmalloc.h>
 #include <asm/unaligned.h>
 
 #include "ath9k.h"
@@ -24,14 +25,25 @@
 #define REG_READ_D(_ah, _reg) \
         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
 
-static struct dentry *ath9k_debugfs_root;
-
 static int ath9k_debugfs_open(struct inode *inode, struct file *file)
 {
         file->private_data = inode->i_private;
         return 0;
 }
 
+static ssize_t ath9k_debugfs_read_buf(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        u8 *buf = file->private_data;
+        return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
+}
+
+static int ath9k_debugfs_release_buf(struct inode *inode, struct file *file)
+{
+        vfree(file->private_data);
+        return 0;
+}
+
 #ifdef CONFIG_ATH_DEBUG
 
 static ssize_t read_file_debug(struct file *file, char __user *user_buf,
@@ -71,7 +83,8 @@ static const struct file_operations fops_debug = {
         .read = read_file_debug,
         .write = write_file_debug,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 #endif
@@ -116,7 +129,8 @@ static const struct file_operations fops_tx_chainmask = {
         .read = read_file_tx_chainmask,
         .write = write_file_tx_chainmask,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -158,7 +172,8 @@ static const struct file_operations fops_rx_chainmask = {
         .read = read_file_rx_chainmask,
         .write = write_file_rx_chainmask,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -259,7 +274,8 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
 static const struct file_operations fops_dma = {
         .read = read_file_dma,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -310,6 +326,8 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
                 sc->debug.stats.istats.dtimsync++;
         if (status & ATH9K_INT_DTIM)
                 sc->debug.stats.istats.dtim++;
+        if (status & ATH9K_INT_TSFOOR)
+                sc->debug.stats.istats.tsfoor++;
 }
 
 static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
@@ -364,8 +382,11 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
         len += snprintf(buf + len, sizeof(buf) - len,
                 "%8s: %10u\n", "DTIM", sc->debug.stats.istats.dtim);
         len += snprintf(buf + len, sizeof(buf) - len,
+                "%8s: %10u\n", "TSFOOR", sc->debug.stats.istats.tsfoor);
+        len += snprintf(buf + len, sizeof(buf) - len,
                 "%8s: %10u\n", "TOTAL", sc->debug.stats.istats.total);
 
+
         if (len > sizeof(buf))
                 len = sizeof(buf);
 
@@ -375,140 +396,46 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
 static const struct file_operations fops_interrupt = {
         .read = read_file_interrupt,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
-void ath_debug_stat_rc(struct ath_softc *sc, int final_rate)
-{
-        struct ath_rc_stats *stats;
-
-        stats = &sc->debug.stats.rcstats[final_rate];
-        stats->success++;
-}
-
-void ath_debug_stat_retries(struct ath_softc *sc, int rix,
-                            int xretries, int retries, u8 per)
+static const char *channel_type_str(enum nl80211_channel_type t)
 {
-        struct ath_rc_stats *stats = &sc->debug.stats.rcstats[rix];
-
-        stats->xretries += xretries;
-        stats->retries += retries;
-        stats->per = per;
-}
-
-static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
-                                size_t count, loff_t *ppos)
-{
-        struct ath_softc *sc = file->private_data;
-        char *buf;
-        unsigned int len = 0, max;
-        int i = 0;
-        ssize_t retval;
-
-        if (sc->cur_rate_table == NULL)
-                return 0;
-
-        max = 80 + sc->cur_rate_table->rate_cnt * 1024 + 1;
-        buf = kmalloc(max, GFP_KERNEL);
-        if (buf == NULL)
-                return -ENOMEM;
-
-        len += sprintf(buf, "%6s %6s %6s "
-                       "%10s %10s %10s %10s\n",
-                       "HT", "MCS", "Rate",
-                       "Success", "Retries", "XRetries", "PER");
-
-        for (i = 0; i < sc->cur_rate_table->rate_cnt; i++) {
-                u32 ratekbps = sc->cur_rate_table->info[i].ratekbps;
-                struct ath_rc_stats *stats = &sc->debug.stats.rcstats[i];
-                char mcs[5];
-                char htmode[5];
-                int used_mcs = 0, used_htmode = 0;
-
-                if (WLAN_RC_PHY_HT(sc->cur_rate_table->info[i].phy)) {
-                        used_mcs = snprintf(mcs, 5, "%d",
-                                sc->cur_rate_table->info[i].ratecode);
-
-                        if (WLAN_RC_PHY_40(sc->cur_rate_table->info[i].phy))
-                                used_htmode = snprintf(htmode, 5, "HT40");
-                        else if (WLAN_RC_PHY_20(sc->cur_rate_table->info[i].phy))
-                                used_htmode = snprintf(htmode, 5, "HT20");
-                        else
-                                used_htmode = snprintf(htmode, 5, "????");
-                }
-
-                mcs[used_mcs] = '\0';
-                htmode[used_htmode] = '\0';
-
-                len += snprintf(buf + len, max - len,
-                        "%6s %6s %3u.%d: "
-                        "%10u %10u %10u %10u\n",
-                        htmode,
-                        mcs,
-                        ratekbps / 1000,
-                        (ratekbps % 1000) / 100,
-                        stats->success,
-                        stats->retries,
-                        stats->xretries,
-                        stats->per);
+        switch (t) {
+        case NL80211_CHAN_NO_HT:
+                return "no ht";
+        case NL80211_CHAN_HT20:
+                return "ht20";
+        case NL80211_CHAN_HT40MINUS:
+                return "ht40-";
+        case NL80211_CHAN_HT40PLUS:
+                return "ht40+";
+        default:
+                return "???";
         }
-
-        if (len > max)
-                len = max;
-
-        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
-        kfree(buf);
-        return retval;
-}
-
-static const struct file_operations fops_rcstat = {
-        .read = read_file_rcstat,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-static const char * ath_wiphy_state_str(enum ath_wiphy_state state)
-{
-        switch (state) {
-        case ATH_WIPHY_INACTIVE:
-                return "INACTIVE";
-        case ATH_WIPHY_ACTIVE:
-                return "ACTIVE";
-        case ATH_WIPHY_PAUSING:
-                return "PAUSING";
-        case ATH_WIPHY_PAUSED:
-                return "PAUSED";
-        case ATH_WIPHY_SCAN:
-                return "SCAN";
-        }
-        return "?";
 }
 
 static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
                                size_t count, loff_t *ppos)
 {
         struct ath_softc *sc = file->private_data;
+        struct ieee80211_channel *chan = sc->hw->conf.channel;
+        struct ieee80211_conf *conf = &(sc->hw->conf);
         char buf[512];
         unsigned int len = 0;
-        int i;
         u8 addr[ETH_ALEN];
+        u32 tmp;
 
         len += snprintf(buf + len, sizeof(buf) - len,
-                        "primary: %s (%s chan=%d ht=%d)\n",
-                        wiphy_name(sc->pri_wiphy->hw->wiphy),
-                        ath_wiphy_state_str(sc->pri_wiphy->state),
-                        sc->pri_wiphy->chan_idx, sc->pri_wiphy->chan_is_ht);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
-                        continue;
-                len += snprintf(buf + len, sizeof(buf) - len,
-                                "secondary: %s (%s chan=%d ht=%d)\n",
-                                wiphy_name(aphy->hw->wiphy),
-                                ath_wiphy_state_str(aphy->state),
-                                aphy->chan_idx, aphy->chan_is_ht);
-        }
+                        "%s (chan=%d  center-freq: %d MHz  channel-type: %d (%s))\n",
+                        wiphy_name(sc->hw->wiphy),
+                        ieee80211_frequency_to_channel(chan->center_freq),
+                        chan->center_freq,
+                        conf->channel_type,
+                        channel_type_str(conf->channel_type));
 
+        ath9k_ps_wakeup(sc);
         put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_STA_ID0), addr);
         put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4);
         len += snprintf(buf + len, sizeof(buf) - len,
@@ -517,6 +444,38 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
         put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_BSSMSKU) & 0xffff, addr + 4);
         len += snprintf(buf + len, sizeof(buf) - len,
                         "addrmask: %pM\n", addr);
+        tmp = ath9k_hw_getrxfilter(sc->sc_ah);
+        ath9k_ps_restore(sc);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "rfilt: 0x%x", tmp);
+        if (tmp & ATH9K_RX_FILTER_UCAST)
+                len += snprintf(buf + len, sizeof(buf) - len, " UCAST");
+        if (tmp & ATH9K_RX_FILTER_MCAST)
+                len += snprintf(buf + len, sizeof(buf) - len, " MCAST");
+        if (tmp & ATH9K_RX_FILTER_BCAST)
+                len += snprintf(buf + len, sizeof(buf) - len, " BCAST");
+        if (tmp & ATH9K_RX_FILTER_CONTROL)
+                len += snprintf(buf + len, sizeof(buf) - len, " CONTROL");
+        if (tmp & ATH9K_RX_FILTER_BEACON)
+                len += snprintf(buf + len, sizeof(buf) - len, " BEACON");
+        if (tmp & ATH9K_RX_FILTER_PROM)
+                len += snprintf(buf + len, sizeof(buf) - len, " PROM");
+        if (tmp & ATH9K_RX_FILTER_PROBEREQ)
+                len += snprintf(buf + len, sizeof(buf) - len, " PROBEREQ");
+        if (tmp & ATH9K_RX_FILTER_PHYERR)
+                len += snprintf(buf + len, sizeof(buf) - len, " PHYERR");
+        if (tmp & ATH9K_RX_FILTER_MYBEACON)
+                len += snprintf(buf + len, sizeof(buf) - len, " MYBEACON");
+        if (tmp & ATH9K_RX_FILTER_COMP_BAR)
+                len += snprintf(buf + len, sizeof(buf) - len, " COMP_BAR");
+        if (tmp & ATH9K_RX_FILTER_PSPOLL)
+                len += snprintf(buf + len, sizeof(buf) - len, " PSPOLL");
+        if (tmp & ATH9K_RX_FILTER_PHYRADAR)
+                len += snprintf(buf + len, sizeof(buf) - len, " PHYRADAR");
+        if (tmp & ATH9K_RX_FILTER_MCAST_BCAST_ALL)
+                len += snprintf(buf + len, sizeof(buf) - len, " MCAST_BCAST_ALL\n");
+        else
+                len += snprintf(buf + len, sizeof(buf) - len, "\n");
 
         if (len > sizeof(buf))
                 len = sizeof(buf);
@@ -524,136 +483,76 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 }
 
-static struct ath_wiphy * get_wiphy(struct ath_softc *sc, const char *name)
-{
-        int i;
-        if (strcmp(name, wiphy_name(sc->pri_wiphy->hw->wiphy)) == 0)
-                return sc->pri_wiphy;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy && strcmp(name, wiphy_name(aphy->hw->wiphy)) == 0)
-                        return aphy;
-        }
-        return NULL;
-}
-
-static int del_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_del(aphy);
-}
-
-static int pause_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_pause(aphy);
-}
-
-static int unpause_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_unpause(aphy);
-}
-
-static int select_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_select(aphy);
-}
-
-static int schedule_wiphy(struct ath_softc *sc, const char *msec)
-{
-        ath9k_wiphy_set_scheduler(sc, simple_strtoul(msec, NULL, 0));
-        return 0;
-}
-
-static ssize_t write_file_wiphy(struct file *file, const char __user *user_buf,
-                                size_t count, loff_t *ppos)
-{
-        struct ath_softc *sc = file->private_data;
-        char buf[50];
-        size_t len;
-
-        len = min(count, sizeof(buf) - 1);
-        if (copy_from_user(buf, user_buf, len))
-                return -EFAULT;
-        buf[len] = '\0';
-        if (len > 0 && buf[len - 1] == '\n')
-                buf[len - 1] = '\0';
-
-        if (strncmp(buf, "add", 3) == 0) {
-                int res = ath9k_wiphy_add(sc);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "del=", 4) == 0) {
-                int res = del_wiphy(sc, buf + 4);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "pause=", 6) == 0) {
-                int res = pause_wiphy(sc, buf + 6);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "unpause=", 8) == 0) {
-                int res = unpause_wiphy(sc, buf + 8);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "select=", 7) == 0) {
-                int res = select_wiphy(sc, buf + 7);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "schedule=", 9) == 0) {
-                int res = schedule_wiphy(sc, buf + 9);
-                if (res < 0)
-                        return res;
-        } else
-                return -EOPNOTSUPP;
-
-        return count;
-}
-
 static const struct file_operations fops_wiphy = {
         .read = read_file_wiphy,
-        .write = write_file_wiphy,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
+#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
 #define PR(str, elem)                                                   \
         do {                                                            \
                 len += snprintf(buf + len, size - len,                  \
                                 "%s%13u%11u%10u%10u\n", str,            \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BE]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BK]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VI]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VO]].elem); \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem, \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem, \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem, \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem); \
+                if (len >= size)                          \
+                        goto done;                        \
 } while(0)
 
+#define PRX(str, elem)                                                  \
+do {                                                                    \
+        len += snprintf(buf + len, size - len,                          \
+                        "%s%13u%11u%10u%10u\n", str,                    \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_BE]->elem),        \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_BK]->elem),        \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_VI]->elem),        \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_VO]->elem));       \
+        if (len >= size)                                                \
+                goto done;                                              \
+} while(0)
+
+#define PRQLE(str, elem)                                                \
+do {                                                                    \
+        len += snprintf(buf + len, size - len,                          \
+                        "%s%13i%11i%10i%10i\n", str,                    \
+                        list_empty(&sc->tx.txq_map[WME_AC_BE]->elem),   \
+                        list_empty(&sc->tx.txq_map[WME_AC_BK]->elem),   \
+                        list_empty(&sc->tx.txq_map[WME_AC_VI]->elem),   \
+                        list_empty(&sc->tx.txq_map[WME_AC_VO]->elem));  \
+        if (len >= size)                                                \
+                goto done;                                              \
+} while (0)
+
 static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
                               size_t count, loff_t *ppos)
 {
         struct ath_softc *sc = file->private_data;
         char *buf;
-        unsigned int len = 0, size = 2048;
+        unsigned int len = 0, size = 8000;
+        int i;
         ssize_t retval = 0;
+        char tmp[32];
 
         buf = kzalloc(size, GFP_KERNEL);
         if (buf == NULL)
                 return -ENOMEM;
 
-        len += sprintf(buf, "%30s %10s%10s%10s\n\n", "BE", "BK", "VI", "VO");
+        len += sprintf(buf, "Num-Tx-Queues: %i  tx-queues-setup: 0x%x"
+                       " poll-work-seen: %u\n"
+                       "%30s %10s%10s%10s\n\n",
+                       ATH9K_NUM_TX_QUEUES, sc->tx.txqsetup,
+                       sc->tx_complete_poll_work_seen,
+                       "BE", "BK", "VI", "VO");
 
         PR("MPDUs Queued:    ", queued);
         PR("MPDUs Completed: ", completed);
         PR("Aggregates:      ", a_aggr);
-        PR("AMPDUs Queued:   ", a_queued);
+        PR("AMPDUs Queued HW:", a_queued_hw);
+        PR("AMPDUs Queued SW:", a_queued_sw);
         PR("AMPDUs Completed:", a_completed);
         PR("AMPDUs Retried:  ", a_retries);
         PR("AMPDUs XRetried: ", a_xretries);
@@ -663,7 +562,64 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
         PR("DESC CFG Error:  ", desc_cfg_err);
         PR("DATA Underrun:   ", data_underrun);
         PR("DELIM Underrun:  ", delim_underrun);
+        PR("TX-Pkts-All:     ", tx_pkts_all);
+        PR("TX-Bytes-All:    ", tx_bytes_all);
+        PR("hw-put-tx-buf:   ", puttxbuf);
+        PR("hw-tx-start:     ", txstart);
+        PR("hw-tx-proc-desc: ", txprocdesc);
+        len += snprintf(buf + len, size - len,
+                        "%s%11p%11p%10p%10p\n", "txq-memory-address:",
+                        sc->tx.txq_map[WME_AC_BE],
+                        sc->tx.txq_map[WME_AC_BK],
+                        sc->tx.txq_map[WME_AC_VI],
+                        sc->tx.txq_map[WME_AC_VO]);
+        if (len >= size)
+                goto done;
+
+        PRX("axq-qnum:        ", axq_qnum);
+        PRX("axq-depth:       ", axq_depth);
+        PRX("axq-ampdu_depth: ", axq_ampdu_depth);
+        PRX("axq-stopped      ", stopped);
+        PRX("tx-in-progress   ", axq_tx_inprogress);
+        PRX("pending-frames   ", pending_frames);
+        PRX("txq_headidx:     ", txq_headidx);
+        PRX("txq_tailidx:     ", txq_headidx);
+
+        PRQLE("axq_q empty:       ", axq_q);
+        PRQLE("axq_acq empty:     ", axq_acq);
+        PRQLE("txq_fifo_pending:  ", txq_fifo_pending);
+        for (i = 0; i < ATH_TXFIFO_DEPTH; i++) {
+                snprintf(tmp, sizeof(tmp) - 1, "txq_fifo[%i] empty: ", i);
+                PRQLE(tmp, txq_fifo[i]);
+        }
 
+        /* Print out more detailed queue-info */
+        for (i = 0; i <= WME_AC_BK; i++) {
+                struct ath_txq *txq = &(sc->tx.txq[i]);
+                struct ath_atx_ac *ac;
+                struct ath_atx_tid *tid;
+                if (len >= size)
+                        goto done;
+                spin_lock_bh(&txq->axq_lock);
+                if (!list_empty(&txq->axq_acq)) {
+                        ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac,
+                                              list);
+                        len += snprintf(buf + len, size - len,
+                                        "txq[%i] first-ac: %p sched: %i\n",
+                                        i, ac, ac->sched);
+                        if (list_empty(&ac->tid_q) || (len >= size))
+                                goto done_for;
+                        tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
+                                               list);
+                        len += snprintf(buf + len, size - len,
+                                        " first-tid: %p sched: %i paused: %i\n",
+                                        tid, tid->sched, tid->paused);
+                }
+        done_for:
+                spin_unlock_bh(&txq->axq_lock);
+        }
+
+done:
         if (len > size)
                 len = size;
 
@@ -673,36 +629,220 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
         return retval;
 }
 
-void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-                       struct ath_buf *bf, struct ath_tx_status *ts)
+static ssize_t read_file_stations(struct file *file, char __user *user_buf,
+                                  size_t count, loff_t *ppos)
 {
+        struct ath_softc *sc = file->private_data;
+        char *buf;
+        unsigned int len = 0, size = 64000;
+        struct ath_node *an = NULL;
+        ssize_t retval = 0;
+        int q;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "Stations:\n"
+                        " tid: addr sched paused buf_q-empty an ac\n"
+                        " ac: addr sched tid_q-empty txq\n");
+
+        spin_lock(&sc->nodes_lock);
+        list_for_each_entry(an, &sc->nodes, list) {
+                len += snprintf(buf + len, size - len,
+                                "%pM\n", an->sta->addr);
+                if (len >= size)
+                        goto done;
+
+                for (q = 0; q < WME_NUM_TID; q++) {
+                        struct ath_atx_tid *tid = &(an->tid[q]);
+                        len += snprintf(buf + len, size - len,
+                                        " tid: %p %s %s %i %p %p\n",
+                                        tid, tid->sched ? "sched" : "idle",
+                                        tid->paused ? "paused" : "running",
+                                        list_empty(&tid->buf_q),
+                                        tid->an, tid->ac);
+                        if (len >= size)
+                                goto done;
+                }
+
+                for (q = 0; q < WME_NUM_AC; q++) {
+                        struct ath_atx_ac *ac = &(an->ac[q]);
+                        len += snprintf(buf + len, size - len,
+                                        " ac: %p %s %i %p\n",
+                                        ac, ac->sched ? "sched" : "idle",
+                                        list_empty(&ac->tid_q), ac->txq);
+                        if (len >= size)
+                                goto done;
+                }
+        }
+
+done:
+        spin_unlock(&sc->nodes_lock);
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+static ssize_t read_file_misc(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+        struct ath_softc *sc = file->private_data;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_hw *ah = sc->sc_ah;
+        struct ieee80211_hw *hw = sc->hw;
+        char *buf;
+        unsigned int len = 0, size = 8000;
+        ssize_t retval = 0;
+        const char *tmp;
+        unsigned int reg;
+        struct ath9k_vif_iter_data iter_data;
+
+        ath9k_calculate_iter_data(hw, NULL, &iter_data);
+        
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        switch (sc->sc_ah->opmode) {
+        case  NL80211_IFTYPE_ADHOC:
+                tmp = "ADHOC";
+                break;
+        case  NL80211_IFTYPE_MESH_POINT:
+                tmp = "MESH";
+                break;
+        case  NL80211_IFTYPE_AP:
+                tmp = "AP";
+                break;
+        case  NL80211_IFTYPE_STATION:
+                tmp = "STATION";
+                break;
+        default:
+                tmp = "???";
+                break;
+        }
+
+        ath9k_ps_wakeup(sc);
+        len += snprintf(buf + len, size - len,
+                        "curbssid: %pM\n"
+                        "OP-Mode: %s(%i)\n"
+                        "Beacon-Timer-Register: 0x%x\n",
+                        common->curbssid,
+                        tmp, (int)(sc->sc_ah->opmode),
+                        REG_READ(ah, AR_BEACON_PERIOD));
+
+        reg = REG_READ(ah, AR_TIMER_MODE);
+        ath9k_ps_restore(sc);
+        len += snprintf(buf + len, size - len, "Timer-Mode-Register: 0x%x (",
+                        reg);
+        if (reg & AR_TBTT_TIMER_EN)
+                len += snprintf(buf + len, size - len, "TBTT ");
+        if (reg & AR_DBA_TIMER_EN)
+                len += snprintf(buf + len, size - len, "DBA ");
+        if (reg & AR_SWBA_TIMER_EN)
+                len += snprintf(buf + len, size - len, "SWBA ");
+        if (reg & AR_HCF_TIMER_EN)
+                len += snprintf(buf + len, size - len, "HCF ");
+        if (reg & AR_TIM_TIMER_EN)
+                len += snprintf(buf + len, size - len, "TIM ");
+        if (reg & AR_DTIM_TIMER_EN)
+                len += snprintf(buf + len, size - len, "DTIM ");
+        len += snprintf(buf + len, size - len, ")\n");
+
+        reg = sc->sc_ah->imask;
+        len += snprintf(buf + len, size - len, "imask: 0x%x (", reg);
+        if (reg & ATH9K_INT_SWBA)
+                len += snprintf(buf + len, size - len, "SWBA ");
+        if (reg & ATH9K_INT_BMISS)
+                len += snprintf(buf + len, size - len, "BMISS ");
+        if (reg & ATH9K_INT_CST)
+                len += snprintf(buf + len, size - len, "CST ");
+        if (reg & ATH9K_INT_RX)
+                len += snprintf(buf + len, size - len, "RX ");
+        if (reg & ATH9K_INT_RXHP)
+                len += snprintf(buf + len, size - len, "RXHP ");
+        if (reg & ATH9K_INT_RXLP)
+                len += snprintf(buf + len, size - len, "RXLP ");
+        if (reg & ATH9K_INT_BB_WATCHDOG)
+                len += snprintf(buf + len, size - len, "BB_WATCHDOG ");
+        /* there are other IRQs if one wanted to add them. */
+        len += snprintf(buf + len, size - len, ")\n");
+
+        len += snprintf(buf + len, size - len,
+                        "VIF Counts: AP: %i STA: %i MESH: %i WDS: %i"
+                        " ADHOC: %i OTHER: %i nvifs: %hi beacon-vifs: %hi\n",
+                        iter_data.naps, iter_data.nstations, iter_data.nmeshes,
+                        iter_data.nwds, iter_data.nadhocs, iter_data.nothers,
+                        sc->nvifs, sc->nbcnvifs);
+
+        len += snprintf(buf + len, size - len,
+                        "Calculated-BSSID-Mask: %pM\n",
+                        iter_data.mask);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
+                       struct ath_tx_status *ts, struct ath_txq *txq)
+{
+        int qnum = txq->axq_qnum;
+
+        TX_STAT_INC(qnum, tx_pkts_all);
+        sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len;
+
         if (bf_isampdu(bf)) {
                 if (bf_isxretried(bf))
-                        TX_STAT_INC(txq->axq_qnum, a_xretries);
+                        TX_STAT_INC(qnum, a_xretries);
                 else
-                        TX_STAT_INC(txq->axq_qnum, a_completed);
+                        TX_STAT_INC(qnum, a_completed);
         } else {
-                TX_STAT_INC(txq->axq_qnum, completed);
+                TX_STAT_INC(qnum, completed);
         }
 
         if (ts->ts_status & ATH9K_TXERR_FIFO)
-                TX_STAT_INC(txq->axq_qnum, fifo_underrun);
+                TX_STAT_INC(qnum, fifo_underrun);
         if (ts->ts_status & ATH9K_TXERR_XTXOP)
-                TX_STAT_INC(txq->axq_qnum, xtxop);
+                TX_STAT_INC(qnum, xtxop);
         if (ts->ts_status & ATH9K_TXERR_TIMER_EXPIRED)
-                TX_STAT_INC(txq->axq_qnum, timer_exp);
+                TX_STAT_INC(qnum, timer_exp);
         if (ts->ts_flags & ATH9K_TX_DESC_CFG_ERR)
-                TX_STAT_INC(txq->axq_qnum, desc_cfg_err);
+                TX_STAT_INC(qnum, desc_cfg_err);
         if (ts->ts_flags & ATH9K_TX_DATA_UNDERRUN)
-                TX_STAT_INC(txq->axq_qnum, data_underrun);
+                TX_STAT_INC(qnum, data_underrun);
         if (ts->ts_flags & ATH9K_TX_DELIM_UNDERRUN)
-                TX_STAT_INC(txq->axq_qnum, delim_underrun);
+                TX_STAT_INC(qnum, delim_underrun);
 }
 
 static const struct file_operations fops_xmit = {
         .read = read_file_xmit,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static const struct file_operations fops_stations = {
+        .read = read_file_stations,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static const struct file_operations fops_misc = {
+        .read = read_file_misc,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 static ssize_t read_file_recv(struct file *file, char __user *user_buf,
@@ -714,7 +854,7 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
 
         struct ath_softc *sc = file->private_data;
         char *buf;
-        unsigned int len = 0, size = 1152;
+        unsigned int len = 0, size = 1400;
         ssize_t retval = 0;
 
         buf = kzalloc(size, GFP_KERNEL);
@@ -743,6 +883,34 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
                         "%18s : %10u\n", "DECRYPT BUSY ERR",
                         sc->debug.stats.rxstats.decrypt_busy_err);
 
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-CTL0",
+                        sc->debug.stats.rxstats.rs_rssi_ctl0);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-CTL1",
+                        sc->debug.stats.rxstats.rs_rssi_ctl1);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-CTL2",
+                        sc->debug.stats.rxstats.rs_rssi_ctl2);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-EXT0",
+                        sc->debug.stats.rxstats.rs_rssi_ext0);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-EXT1",
+                        sc->debug.stats.rxstats.rs_rssi_ext1);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-EXT2",
+                        sc->debug.stats.rxstats.rs_rssi_ext2);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "Rx Antenna",
+                        sc->debug.stats.rxstats.rs_antenna);
+
         PHY_ERR("UNDERRUN", ATH9K_PHYERR_UNDERRUN);
         PHY_ERR("TIMING", ATH9K_PHYERR_TIMING);
         PHY_ERR("PARITY", ATH9K_PHYERR_PARITY);
@@ -770,6 +938,13 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
         PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL);
         PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL);
 
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10u\n", "RX-Pkts-All",
+                        sc->debug.stats.rxstats.rx_pkts_all);
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10u\n", "RX-Bytes-All",
+                        sc->debug.stats.rxstats.rx_bytes_all);
+
         if (len > size)
                 len = size;
 
@@ -788,6 +963,9 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
 
         u32 phyerr;
 
+        RX_STAT_INC(rx_pkts_all);
+        sc->debug.stats.rxstats.rx_bytes_all += rs->rs_datalen;
+
         if (rs->rs_status & ATH9K_RXERR_CRC)
                 RX_STAT_INC(crc_err);
         if (rs->rs_status & ATH9K_RXERR_DECRYPT)
@@ -807,6 +985,16 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
                 RX_PHY_ERR_INC(phyerr);
         }
 
+        sc->debug.stats.rxstats.rs_rssi_ctl0 = rs->rs_rssi_ctl0;
+        sc->debug.stats.rxstats.rs_rssi_ctl1 = rs->rs_rssi_ctl1;
+        sc->debug.stats.rxstats.rs_rssi_ctl2 = rs->rs_rssi_ctl2;
+
+        sc->debug.stats.rxstats.rs_rssi_ext0 = rs->rs_rssi_ext0;
+        sc->debug.stats.rxstats.rs_rssi_ext1 = rs->rs_rssi_ext1;
+        sc->debug.stats.rxstats.rs_rssi_ext2 = rs->rs_rssi_ext2;
+
+        sc->debug.stats.rxstats.rs_antenna = rs->rs_antenna;
+
 #undef RX_STAT_INC
 #undef RX_PHY_ERR_INC
 }
@@ -814,7 +1002,8 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
 static const struct file_operations fops_recv = {
         .read = read_file_recv,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 static ssize_t read_file_regidx(struct file *file, char __user *user_buf,
@@ -852,7 +1041,8 @@ static const struct file_operations fops_regidx = {
         .read = read_file_regidx,
         .write = write_file_regidx,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 static ssize_t read_file_regval(struct file *file, char __user *user_buf,
@@ -864,7 +1054,9 @@ static ssize_t read_file_regval(struct file *file, char __user *user_buf,
         unsigned int len;
         u32 regval;
 
+        ath9k_ps_wakeup(sc);
         regval = REG_READ_D(ah, sc->debug.regidx);
+        ath9k_ps_restore(sc);
         len = sprintf(buf, "0x%08x\n", regval);
         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 }
@@ -886,7 +1078,9 @@ static ssize_t write_file_regval(struct file *file, const char __user *user_buf,
         if (strict_strtoul(buf, 0, &regval))
                 return -EINVAL;
 
+        ath9k_ps_wakeup(sc);
         REG_WRITE_D(ah, sc->debug.regidx, regval);
+        ath9k_ps_restore(sc);
         return count;
 }
 
@@ -894,98 +1088,94 @@ static const struct file_operations fops_regval = {
         .read = read_file_regval,
         .write = write_file_regval,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
-int ath9k_init_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath_softc *sc = (struct ath_softc *) common->priv;
+#define REGDUMP_LINE_SIZE       20
 
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
+static int open_file_regdump(struct inode *inode, struct file *file)
+{
+        struct ath_softc *sc = inode->i_private;
+        unsigned int len = 0;
+        u8 *buf;
+        int i;
+        unsigned long num_regs, regdump_len, max_reg_offset;
 
-        sc->debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
-                                                      ath9k_debugfs_root);
-        if (!sc->debug.debugfs_phy)
+        max_reg_offset = AR_SREV_9300_20_OR_LATER(sc->sc_ah) ? 0x16bd4 : 0xb500;
+        num_regs = max_reg_offset / 4 + 1;
+        regdump_len = num_regs * REGDUMP_LINE_SIZE + 1;
+        buf = vmalloc(regdump_len);
+        if (!buf)
                 return -ENOMEM;
 
-#ifdef CONFIG_ATH_DEBUG
-        if (!debugfs_create_file("debug", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_debug))
-                goto err;
-#endif
-
-        if (!debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_dma))
-                goto err;
-
-        if (!debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_interrupt))
-                goto err;
-
-        if (!debugfs_create_file("rcstat", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_rcstat))
-                goto err;
-
-        if (!debugfs_create_file("wiphy", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_wiphy))
-                goto err;
-
-        if (!debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_xmit))
-                goto err;
-
-        if (!debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_recv))
-                goto err;
-
-        if (!debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_rx_chainmask))
-                goto err;
-
-        if (!debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_tx_chainmask))
-                goto err;
-
-        if (!debugfs_create_file("regidx", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_regidx))
-                goto err;
-
-        if (!debugfs_create_file("regval", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_regval))
-                goto err;
+        ath9k_ps_wakeup(sc);
+        for (i = 0; i < num_regs; i++)
+                len += scnprintf(buf + len, regdump_len - len,
+                        "0x%06x 0x%08x\n", i << 2, REG_READ(sc->sc_ah, i << 2));
+        ath9k_ps_restore(sc);
 
-        if (!debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, &ah->config.cwm_ignore_extcca))
-                goto err;
+        file->private_data = buf;
 
-        sc->debug.regidx = 0;
         return 0;
-err:
-        ath9k_exit_debug(ah);
-        return -ENOMEM;
 }
 
-void ath9k_exit_debug(struct ath_hw *ah)
+static const struct file_operations fops_regdump = {
+        .open = open_file_regdump,
+        .read = ath9k_debugfs_read_buf,
+        .release = ath9k_debugfs_release_buf,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,/* read accesses f_pos */
+};
+
+int ath9k_init_debug(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_softc *sc = (struct ath_softc *) common->priv;
 
-        debugfs_remove_recursive(sc->debug.debugfs_phy);
-}
+        sc->debug.debugfs_phy = debugfs_create_dir("ath9k",
+                                                   sc->hw->wiphy->debugfsdir);
+        if (!sc->debug.debugfs_phy)
+                return -ENOMEM;
 
-int ath9k_debug_create_root(void)
-{
-        ath9k_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
+#ifdef CONFIG_ATH_DEBUG
+        debugfs_create_file("debug", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_debug);
+#endif
+        debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_dma);
+        debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_interrupt);
+        debugfs_create_file("wiphy", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_wiphy);
+        debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_xmit);
+        debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_stations);
+        debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_misc);
+        debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_recv);
+        debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
+                            sc->debug.debugfs_phy, sc, &fops_rx_chainmask);
+        debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
+                            sc->debug.debugfs_phy, sc, &fops_tx_chainmask);
+        debugfs_create_file("regidx", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_regidx);
+        debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_regval);
+        debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
+                            sc->debug.debugfs_phy,
+                            &ah->config.cwm_ignore_extcca);
+        debugfs_create_file("regdump", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_regdump);
+
+        debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
+                           sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
+
+        debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
+                           sc->debug.debugfs_phy, &sc->sc_ah->gpio_val);
 
+        sc->debug.regidx = 0;
         return 0;
 }
-
-void ath9k_debug_remove_root(void)
-{
-        debugfs_remove(ath9k_debugfs_root);
-        ath9k_debugfs_root = NULL;
-}
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 5d21704e87ff..8ce6ad80f4e2 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -54,6 +54,9 @@ struct ath_buf;
  * @dtimsync: DTIM sync lossage
  * @dtim: RX Beacon with DTIM
  * @bb_watchdog: Baseband watchdog
+ * @tsfoor: TSF out of range, indicates that the corrected TSF received
+ * from a beacon differs from the PCU's internal TSF by more than a
+ * (programmable) threshold
  */
 struct ath_interrupt_stats {
         u32 total;
@@ -78,21 +81,20 @@ struct ath_interrupt_stats {
         u32 dtimsync;
         u32 dtim;
         u32 bb_watchdog;
-};
-
-struct ath_rc_stats {
-        u32 success;
-        u32 retries;
-        u32 xretries;
-        u8 per;
+        u32 tsfoor;
 };
 
 /**
  * struct ath_tx_stats - Statistics about TX
+ * @tx_pkts_all:  No. of total frames transmitted, including ones that
+        may have had errors.
+ * @tx_bytes_all:  No. of total bytes transmitted, including ones that
+        may have had errors.
  * @queued: Total MPDUs (non-aggr) queued
  * @completed: Total MPDUs (non-aggr) completed
  * @a_aggr: Total no. of aggregates queued
- * @a_queued: Total AMPDUs queued
+ * @a_queued_hw: Total AMPDUs queued to hardware
+ * @a_queued_sw: Total AMPDUs queued to software queues
  * @a_completed: Total AMPDUs completed
  * @a_retries: No. of AMPDUs retried (SW)
  * @a_xretries: No. of AMPDUs dropped due to xretries
@@ -105,12 +107,18 @@ struct ath_rc_stats {
  * @desc_cfg_err: Descriptor configuration errors
  * @data_urn: TX data underrun errors
  * @delim_urn: TX delimiter underrun errors
+ * @puttxbuf: Number of times hardware was given txbuf to write.
+ * @txstart:  Number of times hardware was told to start tx.
+ * @txprocdesc:  Number of times tx descriptor was processed
  */
 struct ath_tx_stats {
+        u32 tx_pkts_all;
+        u32 tx_bytes_all;
         u32 queued;
         u32 completed;
         u32 a_aggr;
-        u32 a_queued;
+        u32 a_queued_hw;
+        u32 a_queued_sw;
         u32 a_completed;
         u32 a_retries;
         u32 a_xretries;
@@ -120,10 +128,17 @@ struct ath_tx_stats {
         u32 desc_cfg_err;
         u32 data_underrun;
         u32 delim_underrun;
+        u32 puttxbuf;
+        u32 txstart;
+        u32 txprocdesc;
 };
 
 /**
  * struct ath_rx_stats - RX Statistics
+ * @rx_pkts_all:  No. of total frames received, including ones that
+        may have had errors.
+ * @rx_bytes_all:  No. of total bytes received, including ones that
+        may have had errors.
  * @crc_err: No. of frames with incorrect CRC value
  * @decrypt_crc_err: No. of frames whose CRC check failed after
         decryption process completed
@@ -136,6 +151,8 @@ struct ath_tx_stats {
  * @phy_err_stats: Individual PHY error statistics
  */
 struct ath_rx_stats {
+        u32 rx_pkts_all;
+        u32 rx_bytes_all;
         u32 crc_err;
         u32 decrypt_crc_err;
         u32 phy_err;
@@ -144,11 +161,17 @@ struct ath_rx_stats {
         u32 post_delim_crc_err;
         u32 decrypt_busy_err;
         u32 phy_err_stats[ATH9K_PHYERR_MAX];
+        int8_t rs_rssi_ctl0;
+        int8_t rs_rssi_ctl1;
+        int8_t rs_rssi_ctl2;
+        int8_t rs_rssi_ext0;
+        int8_t rs_rssi_ext1;
+        int8_t rs_rssi_ext2;
+        u8 rs_antenna;
 };
 
 struct ath_stats {
         struct ath_interrupt_stats istats;
-        struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
         struct ath_rx_stats rxstats;
 };
@@ -160,17 +183,11 @@ struct ath9k_debug {
 };
 
 int ath9k_init_debug(struct ath_hw *ah);
-void ath9k_exit_debug(struct ath_hw *ah);
 
-int ath9k_debug_create_root(void);
-void ath9k_debug_remove_root(void);
 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
-void ath_debug_stat_rc(struct ath_softc *sc, int final_rate);
-void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-                       struct ath_buf *bf, struct ath_tx_status *ts);
+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
+                       struct ath_tx_status *ts, struct ath_txq *txq);
 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
-void ath_debug_stat_retries(struct ath_softc *sc, int rix,
-                            int xretries, int retries, u8 per);
 
 #else
 
@@ -179,33 +196,15 @@ static inline int ath9k_init_debug(struct ath_hw *ah)
         return 0;
 }
 
-static inline void ath9k_exit_debug(struct ath_hw *ah)
-{
-}
-
-static inline int ath9k_debug_create_root(void)
-{
-        return 0;
-}
-
-static inline void ath9k_debug_remove_root(void)
-{
-}
-
 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
                                             enum ath9k_int status)
 {
 }
 
-static inline void ath_debug_stat_rc(struct ath_softc *sc,
-                                     int final_rate)
-{
-}
-
 static inline void ath_debug_stat_tx(struct ath_softc *sc,
-                                     struct ath_txq *txq,
                                      struct ath_buf *bf,
-                                     struct ath_tx_status *ts)
+                                     struct ath_tx_status *ts,
+                                     struct ath_txq *txq)
 {
 }
 
@@ -214,11 +213,6 @@ static inline void ath_debug_stat_rx(struct ath_softc *sc,
 {
 }
 
-static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
-                                          int xretries, int retries, u8 per)
-{
-}
-
 #endif /* CONFIG_ATH9K_DEBUGFS */
 
 #endif /* DEBUG_H */
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 1266333f586d..e61404dda8c5 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -89,6 +89,38 @@ bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
         return false;
 }
 
+void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
+                                  int eep_start_loc, int size)
+{
+        int i = 0, j, addr;
+        u32 addrdata[8];
+        u32 data[8];
+
+        for (addr = 0; addr < size; addr++) {
+                addrdata[i] = AR5416_EEPROM_OFFSET +
+                        ((addr + eep_start_loc) << AR5416_EEPROM_S);
+                i++;
+                if (i == 8) {
+                        REG_READ_MULTI(ah, addrdata, data, i);
+
+                        for (j = 0; j < i; j++) {
+                                *eep_data = data[j];
+                                eep_data++;
+                        }
+                        i = 0;
+                }
+        }
+
+        if (i != 0) {
+                REG_READ_MULTI(ah, addrdata, data, i);
+
+                for (j = 0; j < i; j++) {
+                        *eep_data = data[j];
+                        eep_data++;
+                }
+        }
+}
+
 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
 {
         return common->bus_ops->eeprom_read(common, off, data);
@@ -234,22 +266,22 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah,
 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
                                 bool is2GHz, int num_band_edges)
 {
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         int i;
 
         for (i = 0; (i < num_band_edges) &&
                      (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
-                        twiceMaxEdgePower = pRdEdgesPower[i].tPower;
+                        twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
                         break;
                 } else if ((i > 0) &&
                            (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
                                                       is2GHz))) {
                         if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
                                                is2GHz) < freq &&
-                            pRdEdgesPower[i - 1].flag) {
+                            CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
                                 twiceMaxEdgePower =
-                                        pRdEdgesPower[i - 1].tPower;
+                                        CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
                         }
                         break;
                 }
@@ -273,12 +305,225 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
                 break;
         default:
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Invalid chainmask configuration\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Invalid chainmask configuration\n");
                 break;
         }
 }
 
+void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                void *pRawDataSet,
+                                u8 *bChans, u16 availPiers,
+                                u16 tPdGainOverlap,
+                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
+                                u16 numXpdGains)
+{
+        int i, j, k;
+        int16_t ss;
+        u16 idxL = 0, idxR = 0, numPiers;
+        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+        u8 minPwrT4[AR5416_NUM_PD_GAINS];
+        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
+        int16_t vpdStep;
+        int16_t tmpVal;
+        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
+        bool match;
+        int16_t minDelta = 0;
+        struct chan_centers centers;
+        int pdgain_boundary_default;
+        struct cal_data_per_freq *data_def = pRawDataSet;
+        struct cal_data_per_freq_4k *data_4k = pRawDataSet;
+        struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
+        bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
+        int intercepts;
+
+        if (AR_SREV_9287(ah))
+                intercepts = AR9287_PD_GAIN_ICEPTS;
+        else
+                intercepts = AR5416_PD_GAIN_ICEPTS;
+
+        memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
+        ath9k_hw_get_channel_centers(ah, chan, &centers);
+
+        for (numPiers = 0; numPiers < availPiers; numPiers++) {
+                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
+                        break;
+        }
+
+        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
+                                                             IS_CHAN_2GHZ(chan)),
+                                               bChans, numPiers, &idxL, &idxR);
+
+        if (match) {
+                if (AR_SREV_9287(ah)) {
+                        /* FIXME: array overrun? */
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_9287[idxL].pwrPdg[i],
+                                                data_9287[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                } else if (eeprom_4k) {
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_4k[idxL].pwrPdg[i],
+                                                data_4k[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                } else {
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_def[idxL].pwrPdg[i],
+                                                data_def[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                }
+        } else {
+                for (i = 0; i < numXpdGains; i++) {
+                        if (AR_SREV_9287(ah)) {
+                                pVpdL = data_9287[idxL].vpdPdg[i];
+                                pPwrL = data_9287[idxL].pwrPdg[i];
+                                pVpdR = data_9287[idxR].vpdPdg[i];
+                                pPwrR = data_9287[idxR].pwrPdg[i];
+                        } else if (eeprom_4k) {
+                                pVpdL = data_4k[idxL].vpdPdg[i];
+                                pPwrL = data_4k[idxL].pwrPdg[i];
+                                pVpdR = data_4k[idxR].vpdPdg[i];
+                                pPwrR = data_4k[idxR].pwrPdg[i];
+                        } else {
+                                pVpdL = data_def[idxL].vpdPdg[i];
+                                pPwrL = data_def[idxL].pwrPdg[i];
+                                pVpdR = data_def[idxR].vpdPdg[i];
+                                pPwrR = data_def[idxR].pwrPdg[i];
+                        }
+
+                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
+
+                        maxPwrT4[i] =
+                                min(pPwrL[intercepts - 1],
+                                    pPwrR[intercepts - 1]);
+
+
+                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                pPwrL, pVpdL,
+                                                intercepts,
+                                                vpdTableL[i]);
+                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                pPwrR, pVpdR,
+                                                intercepts,
+                                                vpdTableR[i]);
+
+                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
+                                vpdTableI[i][j] =
+                                        (u8)(ath9k_hw_interpolate((u16)
+                                             FREQ2FBIN(centers.
+                                                       synth_center,
+                                                       IS_CHAN_2GHZ
+                                                       (chan)),
+                                             bChans[idxL], bChans[idxR],
+                                             vpdTableL[i][j], vpdTableR[i][j]));
+                        }
+                }
+        }
+
+        k = 0;
+
+        for (i = 0; i < numXpdGains; i++) {
+                if (i == (numXpdGains - 1))
+                        pPdGainBoundaries[i] =
+                                (u16)(maxPwrT4[i] / 2);
+                else
+                        pPdGainBoundaries[i] =
+                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
+
+                pPdGainBoundaries[i] =
+                        min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
+
+                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
+                        minDelta = pPdGainBoundaries[0] - 23;
+                        pPdGainBoundaries[0] = 23;
+                } else {
+                        minDelta = 0;
+                }
+
+                if (i == 0) {
+                        if (AR_SREV_9280_20_OR_LATER(ah))
+                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
+                        else
+                                ss = 0;
+                } else {
+                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
+                                        (minPwrT4[i] / 2)) -
+                                       tPdGainOverlap + 1 + minDelta);
+                }
+                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
+                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+
+                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
+                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
+                        ss++;
+                }
+
+                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
+                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
+                                (minPwrT4[i] / 2));
+                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
+                        tgtIndex : sizeCurrVpdTable;
+
+                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                        pPDADCValues[k++] = vpdTableI[i][ss++];
+                }
+
+                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
+                                    vpdTableI[i][sizeCurrVpdTable - 2]);
+                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+
+                if (tgtIndex >= maxIndex) {
+                        while ((ss <= tgtIndex) &&
+                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
+                                                    (ss - maxIndex + 1) * vpdStep));
+                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
+                                                         255 : tmpVal);
+                                ss++;
+                        }
+                }
+        }
+
+        if (eeprom_4k)
+                pdgain_boundary_default = 58;
+        else
+                pdgain_boundary_default = pPdGainBoundaries[i - 1];
+
+        while (i < AR5416_PD_GAINS_IN_MASK) {
+                pPdGainBoundaries[i] = pdgain_boundary_default;
+                i++;
+        }
+
+        while (k < AR5416_NUM_PDADC_VALUES) {
+                pPDADCValues[k] = pPDADCValues[k - 1];
+                k++;
+        }
+}
+
 int ath9k_hw_eeprom_init(struct ath_hw *ah)
 {
         int status;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 0b09db0f8e7d..de99c0da52e4 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,12 +17,12 @@
 #ifndef EEPROM_H
 #define EEPROM_H
 
+#define AR_EEPROM_MODAL_SPURS   5
+
 #include "../ath.h"
 #include <net/cfg80211.h>
 #include "ar9003_eeprom.h"
 
-#define AH_USE_EEPROM   0x1
-
 #ifdef __BIG_ENDIAN
 #define AR5416_EEPROM_MAGIC 0x5aa5
 #else
@@ -101,7 +101,7 @@
 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
-#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
+#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 
 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
@@ -149,8 +149,6 @@
 #define AR5416_NUM_PD_GAINS             4
 #define AR5416_PD_GAINS_IN_MASK         4
 #define AR5416_PD_GAIN_ICEPTS           5
-#define AR5416_EEPROM_MODAL_SPURS       5
-#define AR5416_MAX_RATE_POWER           63
 #define AR5416_NUM_PDADC_VALUES         128
 #define AR5416_BCHAN_UNUSED             0xFF
 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
@@ -175,8 +173,6 @@
 #define AR5416_EEP4K_NUM_CTLS                 12
 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 #define AR5416_EEP4K_NUM_PD_GAINS             2
-#define AR5416_EEP4K_PD_GAINS_IN_MASK         4
-#define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 #define AR5416_EEP4K_MAX_CHAINS               1
 
 #define AR9280_TX_GAIN_TABLE_SIZE 22
@@ -198,41 +194,30 @@
 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 #define AR9287_NUM_CTLS                 12
 #define AR9287_NUM_BAND_EDGES           4
-#define AR9287_NUM_PD_GAINS             4
-#define AR9287_PD_GAINS_IN_MASK         4
 #define AR9287_PD_GAIN_ICEPTS           1
-#define AR9287_EEPROM_MODAL_SPURS       5
-#define AR9287_MAX_RATE_POWER           63
-#define AR9287_NUM_PDADC_VALUES         128
-#define AR9287_NUM_RATES                16
-#define AR9287_BCHAN_UNUSED             0xFF
-#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
-#define AR9287_OPFLAGS_11A              0x01
-#define AR9287_OPFLAGS_11G              0x02
-#define AR9287_OPFLAGS_2G_HT40          0x08
-#define AR9287_OPFLAGS_2G_HT20          0x20
-#define AR9287_OPFLAGS_5G_HT40          0x04
-#define AR9287_OPFLAGS_5G_HT20          0x10
 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 #define AR9287_EEPMISC_WOW              0x02
 #define AR9287_MAX_CHAINS               2
 #define AR9287_ANT_16S                  32
-#define AR9287_custdatasize             20
-
-#define AR9287_NUM_ANT_CHAIN_FIELDS     6
-#define AR9287_NUM_ANT_COMMON_FIELDS    4
-#define AR9287_SIZE_ANT_CHAIN_FIELD     2
-#define AR9287_SIZE_ANT_COMMON_FIELD    4
-#define AR9287_ANT_CHAIN_MASK           0x3
-#define AR9287_ANT_COMMON_MASK          0xf
-#define AR9287_CHAIN_0_IDX              0
-#define AR9287_CHAIN_1_IDX              1
+
 #define AR9287_DATA_SZ                  32
 
 #define AR9287_PWR_TABLE_OFFSET_DB  -5
 
 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
 
+#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
+#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
+
+#define LNA_CTL_BUF_MODE        BIT(0)
+#define LNA_CTL_ISEL_LO         BIT(1)
+#define LNA_CTL_ISEL_HI         BIT(2)
+#define LNA_CTL_BUF_IN          BIT(3)
+#define LNA_CTL_FEM_BAND        BIT(4)
+#define LNA_CTL_LOCAL_BIAS      BIT(5)
+#define LNA_CTL_FORCE_XPA       BIT(6)
+#define LNA_CTL_USE_ANT1        BIT(7)
+
 enum eeprom_param {
         EEP_NFTHRESH_5,
         EEP_NFTHRESH_2,
@@ -266,6 +251,9 @@ enum eeprom_param {
         EEP_INTERNAL_REGULATOR,
         EEP_SWREG,
         EEP_PAPRD,
+        EEP_MODAL_VER,
+        EEP_ANT_DIV_CTL1,
+        EEP_CHAIN_MASK_REDUCE
 };
 
 enum ar5416_rates {
@@ -376,15 +364,12 @@ struct modal_eep_header {
         u8 xatten2Margin[AR5416_MAX_CHAINS];
         u8 ob_ch1;
         u8 db_ch1;
-        u8 useAnt1:1,
-            force_xpaon:1,
-            local_bias:1,
-            femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
+        u8 lna_ctl;
         u8 miscBits;
         u16 xpaBiasLvlFreq[3];
         u8 futureModal[6];
 
-        struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct calDataPerFreqOpLoop {
@@ -451,8 +436,12 @@ struct modal_eep_4k_header {
         u8 db2_2:4, db2_3:4;
         u8 db2_4:4, reserved:4;
 #endif
-        u8 futureModal[4];
-        struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
+        u8 tx_diversity;
+        u8 flc_pwr_thresh;
+        u8 bb_scale_smrt_antenna;
+#define EEP_4K_BB_DESIRED_SCALE_MASK    0x1f
+        u8 futureModal[1];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct base_eep_ar9287_header {
@@ -510,7 +499,7 @@ struct modal_eep_ar9287_header {
         u8 ob_qam;
         u8 ob_pal_off;
         u8 futureModal[30];
-        struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct cal_data_per_freq {
@@ -519,8 +508,8 @@ struct cal_data_per_freq {
 } __packed;
 
 struct cal_data_per_freq_4k {
-        u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
-        u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
+        u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+        u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 } __packed;
 
 struct cal_target_power_leg {
@@ -533,18 +522,10 @@ struct cal_target_power_ht {
         u8 tPow2x[8];
 } __packed;
 
-
-#ifdef __BIG_ENDIAN_BITFIELD
 struct cal_ctl_edges {
         u8 bChannel;
-        u8 flag:2, tPower:6;
+        u8 ctl;
 } __packed;
-#else
-struct cal_ctl_edges {
-        u8 bChannel;
-        u8 tPower:6, flag:2;
-} __packed;
-#endif
 
 struct cal_data_op_loop_ar9287 {
         u8 pwrPdg[2][5];
@@ -554,8 +535,8 @@ struct cal_data_op_loop_ar9287 {
 } __packed;
 
 struct cal_data_per_freq_ar9287 {
-        u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
-        u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+        u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+        u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 } __packed;
 
 union cal_data_per_freq_ar9287_u {
@@ -670,14 +651,12 @@ struct eeprom_ops {
         bool (*fill_eeprom)(struct ath_hw *hw);
         int (*get_eeprom_ver)(struct ath_hw *hw);
         int (*get_eeprom_rev)(struct ath_hw *hw);
-        u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
-        u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
-                                      struct ath9k_channel *chan);
         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
                            u16 cfgCtl, u8 twiceAntennaReduction,
-                           u8 twiceMaxRegulatoryPower, u8 powerLimit);
+                           u8 twiceMaxRegulatoryPower, u8 powerLimit,
+                           bool test);
         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 };
 
@@ -690,6 +669,8 @@ int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
                                     u16 *indexL, u16 *indexR);
 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
+void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
+                                  int eep_start_loc, int size);
 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
                              u8 *pVpdList, u16 numIntercepts,
                              u8 *pRetVpdList);
@@ -710,6 +691,14 @@ u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 
+void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                void *pRawDataSet,
+                                u8 *bChans, u16 availPiers,
+                                u16 tPdGainOverlap,
+                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
+                                u16 numXpdGains);
+
 #define ar5416_get_ntxchains(_txchainmask)                      \
         (((_txchainmask >> 2) & 1) +                            \
          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 9cccd12e8f21..5b1e894f3d67 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -27,33 +27,52 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
 }
 
-static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
-{
 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
+
+static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
+{
         struct ath_common *common = ath9k_hw_common(ah);
         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
-        int addr, eep_start_loc = 0;
-
-        eep_start_loc = 64;
-
-        if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Reading from EEPROM, not flash\n");
-        }
+        int addr, eep_start_loc = 64;
 
         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Unable to read eeprom region\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
         }
 
         return true;
-#undef SIZE_EEPROM_4K
 }
 
+static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
+{
+        u16 *eep_data = (u16 *)&ah->eeprom.map4k;
+
+        ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
+
+        return true;
+}
+
+static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!ath9k_hw_use_flash(ah)) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
+        }
+
+        if (common->bus_ops->ath_bus_type == ATH_USB)
+                return __ath9k_hw_usb_4k_fill_eeprom(ah);
+        else
+                return __ath9k_hw_4k_fill_eeprom(ah);
+}
+
+#undef SIZE_EEPROM_4K
+
 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 {
 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
@@ -69,13 +88,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
         if (!ath9k_hw_use_flash(ah)) {
                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
                                          &magic)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Reading Magic # failed\n");
+                        ath_err(common, "Reading Magic # failed\n");
                         return false;
                 }
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -90,16 +108,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -120,8 +137,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                 u32 integer;
                 u16 word;
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "EEPROM Endianness is not native.. Changing\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "EEPROM Endianness is not native.. Changing\n");
 
                 word = swab16(eep->baseEepHeader.length);
                 eep->baseEepHeader.length = word;
@@ -155,7 +172,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                         eep->modalHeader.antCtrlChain[i] = integer;
                 }
 
-                for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
                         eep->modalHeader.spurChans[i].spurChan = word;
                 }
@@ -163,9 +180,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
-                          sum, ah->eep_ops->get_eeprom_ver(ah));
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                        sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
@@ -179,6 +195,9 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
         struct modal_eep_4k_header *pModal = &eep->modalHeader;
         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
+        u16 ver_minor;
+
+        ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 
         switch (param) {
         case EEP_NFTHRESH_2:
@@ -204,7 +223,7 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
         case EEP_DB_2:
                 return pModal->db1_1;
         case EEP_MINOR_REV:
-                return pBase->version & AR5416_EEP_VER_MINOR_MASK;
+                return ver_minor;
         case EEP_TX_MASK:
                 return pBase->txMask;
         case EEP_RX_MASK:
@@ -213,178 +232,20 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
                 return 0;
         case EEP_PWR_TABLE_OFFSET:
                 return AR5416_PWR_TABLE_OFFSET_DB;
+        case EEP_MODAL_VER:
+                return pModal->version;
+        case EEP_ANT_DIV_CTL1:
+                return pModal->antdiv_ctl1;
+        case EEP_TXGAIN_TYPE:
+                if (ver_minor >= AR5416_EEP_MINOR_VER_19)
+                        return pBase->txGainType;
+                else
+                        return AR5416_EEP_TXGAIN_ORIGINAL;
         default:
                 return 0;
         }
 }
 
-static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
-                                struct ath9k_channel *chan,
-                                struct cal_data_per_freq_4k *pRawDataSet,
-                                u8 *bChans, u16 availPiers,
-                                u16 tPdGainOverlap,
-                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
-                                u16 numXpdGains)
-{
-#define TMP_VAL_VPD_TABLE \
-        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
-        u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-#define PD_GAIN_BOUNDARY_DEFAULT 58;
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index(
-                                        (u8)FREQ2FBIN(centers.synth_center,
-                                        IS_CHAN_2GHZ(chan)), bChans, numPiers,
-                                        &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                        pRawDataSet[idxL].pwrPdg[i],
-                                        pRawDataSet[idxL].vpdPdg[i],
-                                        AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                        vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] =
-                                min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
-                                    pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
-
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] =
-                                        (u8)(ath9k_hw_interpolate((u16)
-                                             FREQ2FBIN(centers.
-                                                       synth_center,
-                                                       IS_CHAN_2GHZ
-                                                       (chan)),
-                                             bChans[idxL], bChans[idxR],
-                                             vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
-
-                pPdGainBoundaries[i] =
-                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
-
-                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
-                        minDelta = pPdGainBoundaries[0] - 23;
-                        pPdGainBoundaries[0] = 23;
-                } else {
-                        minDelta = 0;
-                }
-
-                if (i == 0) {
-                        if (AR_SREV_9280_10_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
-                                (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                        tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex >= maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
-                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
-                                                         255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
-                i++;
-        }
-
-        while (k < AR5416_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k - 1];
-                k++;
-        }
-
-        return;
-#undef TMP_VAL_VPD_TABLE
-}
-
 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                                   struct ath9k_channel *chan,
                                   int16_t *pTxPowerIndexOffset)
@@ -395,7 +256,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
         u8 *pCalBChans = NULL;
         u16 pdGainOverlap_t2;
         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
-        u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
+        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
         u16 numPiers, i, j;
         u16 numXpdGain, xpdMask;
         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
@@ -417,12 +278,12 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 
         numXpdGain = 0;
 
-        for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
-                if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
+        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
                                 break;
                         xpdGainValues[numXpdGain] =
-                                (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
+                                (u16)(AR5416_PD_GAINS_IN_MASK - i);
                         numXpdGain++;
                 }
         }
@@ -446,7 +307,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
                         pRawDataset = pEepData->calPierData2G[i];
 
-                        ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
+                        ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
                                             pRawDataset, pCalBChans,
                                             numPiers, pdGainOverlap_t2,
                                             gainBoundaries,
@@ -476,27 +337,25 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
                                 REG_WRITE(ah, regOffset, reg32);
 
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
-                                          i, regChainOffset, regOffset,
-                                          reg32);
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC: Chain %d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d |\n",
-                                          i, 4 * j, pdadcValues[4 * j],
-                                          4 * j + 1, pdadcValues[4 * j + 1],
-                                          4 * j + 2, pdadcValues[4 * j + 2],
-                                          4 * j + 3,
-                                          pdadcValues[4 * j + 3]);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
+                                        i, regChainOffset, regOffset,
+                                        reg32);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC: Chain %d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d |\n",
+                                        i, 4 * j, pdadcValues[4 * j],
+                                        4 * j + 1, pdadcValues[4 * j + 1],
+                                        4 * j + 2, pdadcValues[4 * j + 2],
+                                        4 * j + 3, pdadcValues[4 * j + 3]);
 
                                 regOffset += 4;
                         }
 
                         REGWRITE_BUFFER_FLUSH(ah);
-                        DISABLE_REGWRITE_BUFFER(ah);
                 }
         }
 
@@ -521,14 +380,16 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
         int i;
         int16_t twiceLargestAntenna;
         u16 twiceMinEdgePower;
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         struct cal_ctl_data_4k *rep;
         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
                 0, { 0, 0, 0, 0}
         };
@@ -539,10 +400,10 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
                 0, {0, 0, 0, 0}
         };
-        u16 ctlModesFor11g[] =
-                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
-                  CTL_2GHT40
-                };
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
 
         ath9k_hw_get_channel_centers(ah, chan, &centers);
 
@@ -604,7 +465,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 
                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+                        twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
                              pEepData->ctlIndex[i]; i++) {
@@ -715,7 +576,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
                                     u16 cfgCtl,
                                     u8 twiceAntennaReduction,
                                     u8 twiceMaxRegulatoryPower,
-                                    u8 powerLimit)
+                                    u8 powerLimit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
@@ -740,15 +601,20 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
-                        ratesArray[i] = AR5416_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
         }
 
+        if (test)
+            return;
 
         /* Update regulatory */
-
         i = rate6mb;
         if (IS_CHAN_HT40(chan))
                 i = rateHt40_0;
@@ -757,7 +623,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 
         regulatory->max_power_level = ratesArray[i];
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++)
                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
         }
@@ -828,7 +694,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
@@ -905,9 +770,6 @@ static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
-
-        if (AR_SREV_9285_11(ah))
-                REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
 }
 
 /*
@@ -919,6 +781,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 {
         struct modal_eep_4k_header *pModal;
         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
+        struct base_eep_header_4k *pBase = &eep->baseEepHeader;
         u8 txRxAttenLocal;
         u8 ob[5], db1[5], db2[5];
         u8 ant_div_control1, ant_div_control2;
@@ -927,8 +790,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
         pModal = &eep->modalHeader;
         txRxAttenLocal = 23;
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 
         /* Single chain for 4K EEPROM*/
         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
@@ -1105,9 +967,6 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
         }
 
 
-        if (AR_SREV_9285_11(ah))
-                REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
-
         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
                       pModal->switchSettling);
         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
@@ -1145,21 +1004,31 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
                                       AR_PHY_SETTLING_SWITCH,
                                       pModal->swSettleHt40);
         }
-}
-
-static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                              struct ath9k_channel *chan)
-{
-        struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
-        struct modal_eep_4k_header *pModal = &eep->modalHeader;
-
-        return pModal->antCtrlCommon;
-}
-
-static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
-                                         enum ieee80211_band freq_band)
-{
-        return 1;
+        if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {
+                u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
+                                EEP_4K_BB_DESIRED_SCALE_MASK);
+                if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
+                        u32 pwrctrl, mask, clr;
+
+                        mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
+                        pwrctrl = mask * bb_desired_scale;
+                        clr = mask * 0x1f;
+                        REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
+                        REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
+                        REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
+
+                        mask = BIT(0)|BIT(5)|BIT(15);
+                        pwrctrl = mask * bb_desired_scale;
+                        clr = mask * 0x1f;
+                        REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
+
+                        mask = BIT(0)|BIT(5);
+                        pwrctrl = mask * bb_desired_scale;
+                        clr = mask * 0x1f;
+                        REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
+                        REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
+                }
+        }
 }
 
 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
@@ -1170,17 +1039,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_MAP4K_SPURCHAN;
@@ -1198,8 +1067,6 @@ const struct eeprom_ops eep_4k_ops = {
         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_4k_set_board_values,
         .set_addac              = ath9k_hw_4k_set_addac,
         .set_txpower            = ath9k_hw_4k_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index dff2da777312..343fc9f946db 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,7 +17,7 @@
 #include "hw.h"
 #include "ar9002_phy.h"
 
-#define NUM_EEP_WORDS (sizeof(struct ar9287_eeprom) / sizeof(u16))
+#define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
 
 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
 {
@@ -29,29 +29,19 @@ static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
         return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
 }
 
-static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
+static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
 {
         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
         struct ath_common *common = ath9k_hw_common(ah);
         u16 *eep_data;
-        int addr, eep_start_loc;
+        int addr, eep_start_loc = AR9287_EEP_START_LOC;
         eep_data = (u16 *)eep;
 
-        if (ah->hw_version.devid == 0x7015)
-                eep_start_loc = AR9287_HTC_EEP_START_LOC;
-        else
-                eep_start_loc = AR9287_EEP_START_LOC;
-
-        if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Reading from EEPROM, not flash\n");
-        }
-
-        for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
+        for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
                                          eep_data)) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Unable to read eeprom region\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
@@ -60,6 +50,31 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
         return true;
 }
 
+static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
+{
+        u16 *eep_data = (u16 *)&ah->eeprom.map9287;
+
+        ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
+                                     AR9287_HTC_EEP_START_LOC,
+                                     SIZE_EEPROM_AR9287);
+        return true;
+}
+
+static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!ath9k_hw_use_flash(ah)) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
+        }
+
+        if (common->bus_ops->ath_bus_type == ATH_USB)
+                return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
+        else
+                return __ath9k_hw_ar9287_fill_eeprom(ah);
+}
+
 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
 {
         u32 sum = 0, el, integer;
@@ -72,13 +87,12 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
         if (!ath9k_hw_use_flash(ah)) {
                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
                                          &magic)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Reading Magic # failed\n");
+                        ath_err(common, "Reading Magic # failed\n");
                         return false;
                 }
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -87,22 +101,21 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
                                 need_swap = true;
                                 eepdata = (u16 *)(&ah->eeprom);
 
-                                for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
+                                for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
                                         temp = swab16(*eepdata);
                                         *eepdata = temp;
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "Endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -152,7 +165,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
                         eep->modalHeader.antCtrlChain[i] = integer;
                 }
 
-                for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
+                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
                         eep->modalHeader.spurChans[i].spurChan = word;
                 }
@@ -160,9 +173,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
             || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
-                           sum, ah->eep_ops->get_eeprom_ver(ah));
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                        sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
@@ -223,163 +235,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
         }
 }
 
-static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
-                               struct ath9k_channel *chan,
-                               struct cal_data_per_freq_ar9287 *pRawDataSet,
-                               u8 *bChans, u16 availPiers,
-                               u16 tPdGainOverlap,
-                               u16 *pPdGainBoundaries,
-                               u8 *pPDADCValues,
-                               u16 numXpdGains)
-{
-#define TMP_VAL_VPD_TABLE                                               \
-        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
-
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR9287_NUM_PD_GAINS];
-        u8 maxPwrT4[AR9287_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index(
-                (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
-                bChans, numPiers, &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pRawDataSet[idxL].pwrPdg[i],
-                                                pRawDataSet[idxL].vpdPdg[i],
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
-                                          pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
-                                       (u16)FREQ2FBIN(centers. synth_center,
-                                                      IS_CHAN_2GHZ(chan)),
-                                       bChans[idxL], bChans[idxR],
-                                       vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
-
-                pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
-                                           pPdGainBoundaries[i]);
-
-
-                minDelta = 0;
-
-                if (i == 0) {
-                        if (AR_SREV_9280_10_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i-1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] +
-                                tPdGainOverlap - (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                            tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex > maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                                (k < (AR9287_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
-                                pPDADCValues[k++] =
-                                        (u8)((tmpVal > 255) ? 255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR9287_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
-                i++;
-        }
-
-        while (k < AR9287_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k-1];
-                k++;
-        }
-
-#undef TMP_VAL_VPD_TABLE
-}
-
 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
                             struct ath9k_channel *chan,
                             struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
@@ -392,7 +247,7 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
         ath9k_hw_get_channel_centers(ah, chan, &centers);
 
         for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
+                if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
                         break;
         }
 
@@ -458,16 +313,15 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
         struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
         u8 *pCalBChans = NULL;
         u16 pdGainOverlap_t2;
-        u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
-        u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
+        u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
+        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
         u16 numPiers = 0, i, j;
         u16 numXpdGain, xpdMask;
-        u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
+        u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
         u32 reg32, regOffset, regChainOffset, regval;
-        int16_t modalIdx, diff = 0;
+        int16_t diff = 0;
         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
 
-        modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
         xpdMask = pEepData->modalHeader.xpdGain;
 
         if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
@@ -490,12 +344,12 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
         numXpdGain = 0;
 
         /* Calculate the value of xpdgains from the xpdGain Mask */
-        for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
-                if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
-                        if (numXpdGain >= AR9287_NUM_PD_GAINS)
+        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
+                        if (numXpdGain >= AR5416_NUM_PD_GAINS)
                                 break;
                         xpdGainValues[numXpdGain] =
-                                (u16)(AR9287_PD_GAINS_IN_MASK-i);
+                                (u16)(AR5416_PD_GAINS_IN_MASK-i);
                         numXpdGain++;
                 }
         }
@@ -528,7 +382,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                         (struct cal_data_per_freq_ar9287 *)
                                         pEepData->calPierData2G[i];
 
-                                ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan,
+                                ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
                                                            pRawDataset,
                                                            pCalBChans, numPiers,
                                                            pdGainOverlap_t2,
@@ -537,6 +391,8 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                                            numXpdGain);
                         }
 
+                        ENABLE_REGWRITE_BUFFER(ah);
+
                         if (i == 0) {
                                 if (!ath9k_hw_ar9287_get_eeprom(ah,
                                                         EEP_OL_PWRCTRL)) {
@@ -564,13 +420,13 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                              (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
                                 diff *= 2;
 
-                                for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++)
+                                for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
                                         pdadcValues[j] = pdadcValues[j+diff];
 
-                                for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
-                                     j < AR9287_NUM_PDADC_VALUES; j++)
+                                for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
+                                     j < AR5416_NUM_PDADC_VALUES; j++)
                                         pdadcValues[j] =
-                                          pdadcValues[AR9287_NUM_PDADC_VALUES-diff];
+                                          pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
                         }
 
                         if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
@@ -587,6 +443,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                         regOffset += 4;
                                 }
                         }
+                        REGWRITE_BUFFER_FLUSH(ah);
                 }
         }
 
@@ -613,9 +470,9 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
 
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
         int i;
         int16_t twiceLargestAntenna;
         struct cal_ctl_data_ar9287 *rep;
@@ -626,13 +483,13 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
         struct cal_target_power_ht targetPowerHt20,
                                     targetPowerHt40 = {0, {0, 0, 0, 0} };
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11g[] = {CTL_11B,
-                                CTL_11G,
-                                CTL_2GHT20,
-                                CTL_11B_EXT,
-                                CTL_11G_EXT,
-                                CTL_2GHT40};
-        u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
+        u16 numCtlModes = 0;
+        const u16 *pCtlMode = NULL;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         int tx_chainmask;
         u16 twiceMinEdgePower;
@@ -667,10 +524,16 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
         case 1:
                 break;
         case 2:
-                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         case 3:
-                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         }
         scaledPower = max((u16)0, scaledPower);
@@ -853,7 +716,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                                         struct ath9k_channel *chan, u16 cfgCtl,
                                         u8 twiceAntennaReduction,
                                         u8 twiceMaxRegulatoryPower,
-                                        u8 powerLimit)
+                                        u8 powerLimit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
@@ -877,17 +740,33 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR9287_MAX_RATE_POWER)
-                        ratesArray[i] = AR9287_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (test)
+                return;
+
+        if (IS_CHAN_2GHZ(chan))
+                i = rate1l;
+        else
+                i = rate6mb;
+
+        regulatory->max_power_level = ratesArray[i];
+
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++)
                         ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
         }
 
+        ENABLE_REGWRITE_BUFFER(ah);
+
         /* OFDM power per rate */
         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
@@ -971,17 +850,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
         }
-
-        if (IS_CHAN_2GHZ(chan))
-                i = rate1l;
-        else
-                i = rate6mb;
-
-        if (AR_SREV_9280_10_OR_LATER(ah))
-                regulatory->max_power_level =
-                        ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
-        else
-                regulatory->max_power_level = ratesArray[i];
+        REGWRITE_BUFFER_FLUSH(ah);
 }
 
 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
@@ -994,37 +863,13 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
 {
         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
-        u16 antWrites[AR9287_ANT_16S];
         u32 regChainOffset, regval;
         u8 txRxAttenLocal;
-        int i, j, offset_num;
+        int i;
 
         pModal = &eep->modalHeader;
 
-        antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
-        antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
-        antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
-        antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
-        antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
-        antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
-        antWrites[6] = (u16)((pModal->antCtrlCommon >> 4)  & 0xF);
-        antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
-
-        offset_num = 8;
-
-        for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
-                antWrites[j++] = 0;
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
-                antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
-        }
-
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 
         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
                 regChainOffset = i * 0x1000;
@@ -1125,21 +970,6 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
                                   pModal->xpaBiasLvl);
 }
 
-static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
-                                             enum ieee80211_band freq_band)
-{
-        return 1;
-}
-
-static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                                  struct ath9k_channel *chan)
-{
-        struct ar9287_eeprom *eep = &ah->eeprom.map9287;
-        struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
-
-        return pModal->antCtrlCommon;
-}
-
 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
                                             u16 i, bool is2GHz)
 {
@@ -1149,17 +979,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
         struct ath_common *common = ath9k_hw_common(ah);
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_MAP9287_SPURCHAN;
@@ -1177,8 +1007,6 @@ const struct eeprom_ops eep_ar9287_ops = {
         .fill_eeprom            = ath9k_hw_ar9287_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_ar9287_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_ar9287_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_ar9287_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_ar9287_set_board_values,
         .set_addac              = ath9k_hw_ar9287_set_addac,
         .set_txpower            = ath9k_hw_ar9287_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index afa2b73ddbdd..17f0a6806207 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -86,9 +86,10 @@ static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
 }
 
-static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
-{
 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
+
+static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
+{
         struct ath_common *common = ath9k_hw_common(ah);
         u16 *eep_data = (u16 *)&ah->eeprom.def;
         int addr, ar5416_eep_start_loc = 0x100;
@@ -96,16 +97,41 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
                                          eep_data)) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "Unable to read eeprom region\n");
+                        ath_err(ath9k_hw_common(ah),
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
         }
         return true;
-#undef SIZE_EEPROM_DEF
 }
 
+static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
+{
+        u16 *eep_data = (u16 *)&ah->eeprom.def;
+
+        ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
+                                     0x100, SIZE_EEPROM_DEF);
+        return true;
+}
+
+static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!ath9k_hw_use_flash(ah)) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
+        }
+
+        if (common->bus_ops->ath_bus_type == ATH_USB)
+                return __ath9k_hw_usb_def_fill_eeprom(ah);
+        else
+                return __ath9k_hw_def_fill_eeprom(ah);
+}
+
+#undef SIZE_EEPROM_DEF
+
 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 {
         struct ar5416_eeprom_def *eep =
@@ -117,13 +143,13 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
         int i, addr, size;
 
         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
-                ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
+                ath_err(common, "Reading Magic # failed\n");
                 return false;
         }
 
         if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -139,16 +165,15 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "Endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -169,8 +194,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                 u32 integer, j;
                 u16 word;
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "EEPROM Endianness is not native.. Changing.\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "EEPROM Endianness is not native.. Changing.\n");
 
                 word = swab16(eep->baseEepHeader.length);
                 eep->baseEepHeader.length = word;
@@ -206,8 +231,12 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                                 integer = swab32(pModal->antCtrlChain[i]);
                                 pModal->antCtrlChain[i] = integer;
                         }
+                        for (i = 0; i < 3; i++) {
+                                word = swab16(pModal->xpaBiasLvlFreq[i]);
+                                pModal->xpaBiasLvlFreq[i] = word;
+                        }
 
-                        for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+                        for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                                 word = swab16(pModal->spurChans[i].spurChan);
                                 pModal->spurChans[i].spurChan = word;
                         }
@@ -216,18 +245,21 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
                         sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
         /* Enable fixup for AR_AN_TOP2 if necessary */
-        if (AR_SREV_9280_10_OR_LATER(ah) &&
-            (eep->baseEepHeader.version & 0xff) > 0x0a &&
-            eep->baseEepHeader.pwdclkind == 0)
+        if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
+            ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
+            (eep->baseEepHeader.pwdclkind == 0))
                 ah->need_an_top2_fixup = 1;
 
+        if ((common->bus_ops->ath_bus_type == ATH_USB) &&
+            (AR_SREV_9280(ah)))
+                eep->modalHeader[0].xpaBiasLvl = 0;
+
         return 0;
 }
 
@@ -317,7 +349,7 @@ static void ath9k_hw_def_set_gain(struct ath_hw *ah,
         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
                 txRxAttenLocal = pModal->txRxAttenCh[i];
 
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
                               pModal->bswMargin[i]);
@@ -344,7 +376,7 @@ static void ath9k_hw_def_set_gain(struct ath_hw *ah,
                 }
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 REG_RMW_FIELD(ah,
                       AR_PHY_RXGAIN + regChainOffset,
                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
@@ -376,8 +408,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
 
         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
                 if (AR_SREV_9280(ah)) {
@@ -408,7 +439,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
                                               regChainOffset, i);
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 if (IS_CHAN_2GHZ(chan)) {
                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
                                                   AR_AN_RF2G1_CH0_OB,
@@ -451,9 +482,10 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
                                           AR_AN_TOP2_LOCALBIAS,
                                           AR_AN_TOP2_LOCALBIAS_S,
-                                          pModal->local_bias);
+                                          !!(pModal->lna_ctl &
+                                             LNA_CTL_LOCAL_BIAS));
                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
-                              pModal->force_xpaon);
+                              !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
         }
 
         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
@@ -461,7 +493,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
                       pModal->adcDesiredSize);
 
-        if (!AR_SREV_9280_10_OR_LATER(ah))
+        if (!AR_SREV_9280_20_OR_LATER(ah))
                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
                               AR_PHY_DESIRED_SZ_PGA,
                               pModal->pgaDesiredSize);
@@ -478,7 +510,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
                       pModal->txEndToRxOn);
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
                               pModal->thresh62);
                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
@@ -589,168 +621,6 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 #undef XPA_LVL_FREQ
 }
 
-static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
-                                struct ath9k_channel *chan,
-                                struct cal_data_per_freq *pRawDataSet,
-                                u8 *bChans, u16 availPiers,
-                                u16 tPdGainOverlap,
-                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
-                                u16 numXpdGains)
-{
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR5416_NUM_PD_GAINS];
-        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
-                                                             IS_CHAN_2GHZ(chan)),
-                                               bChans, numPiers, &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                        pRawDataSet[idxL].pwrPdg[i],
-                                        pRawDataSet[idxL].vpdPdg[i],
-                                        AR5416_PD_GAIN_ICEPTS,
-                                        vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] =
-                                min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
-                                    pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
-
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR5416_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR5416_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] =
-                                        (u8)(ath9k_hw_interpolate((u16)
-                                             FREQ2FBIN(centers.
-                                                       synth_center,
-                                                       IS_CHAN_2GHZ
-                                                       (chan)),
-                                             bChans[idxL], bChans[idxR],
-                                             vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
-
-                pPdGainBoundaries[i] =
-                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
-
-                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
-                        minDelta = pPdGainBoundaries[0] - 23;
-                        pPdGainBoundaries[0] = 23;
-                } else {
-                        minDelta = 0;
-                }
-
-                if (i == 0) {
-                        if (AR_SREV_9280_10_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
-                                (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                        tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-                }
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex >= maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
-                                                    (ss - maxIndex + 1) * vpdStep));
-                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
-                                                         255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR5416_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
-                i++;
-        }
-
-        while (k < AR5416_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k - 1];
-                k++;
-        }
-}
-
 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
                                 u16 *gb,
                                 u16 numXpdGain,
@@ -783,7 +653,7 @@ static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
                 /* Because of a hardware limitation, ensure the gain boundary
                  * is not larger than (63 - overlap)
                  */
-                gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
+                gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 
                 for (k = 0; k < numXpdGain; k++)
                         gb[k] = (u16)min(gb_limit, gb[k]);
@@ -917,7 +787,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
                                                      txPower/2, pdadcValues);
                         } else {
-                                ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
+                                ath9k_hw_get_gain_boundaries_pdadcs(ah,
                                                         chan, pRawDataset,
                                                         pCalBChans, numPiers,
                                                         pdGainOverlap_t2,
@@ -933,6 +803,8 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                                            pwr_table_offset,
                                                            &diff);
 
+                        ENABLE_REGWRITE_BUFFER(ah);
+
                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
                                 if (OLC_FOR_AR9280_20_LATER) {
                                         REG_WRITE(ah,
@@ -965,23 +837,23 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
                                 REG_WRITE(ah, regOffset, reg32);
 
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
-                                          i, regChainOffset, regOffset,
-                                          reg32);
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC: Chain %d | PDADC %3d "
-                                          "Value %3d | PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | PDADC %3d "
-                                          "Value %3d |\n",
-                                          i, 4 * j, pdadcValues[4 * j],
-                                          4 * j + 1, pdadcValues[4 * j + 1],
-                                          4 * j + 2, pdadcValues[4 * j + 2],
-                                          4 * j + 3,
-                                          pdadcValues[4 * j + 3]);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
+                                        i, regChainOffset, regOffset,
+                                        reg32);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC: Chain %d | PDADC %3d "
+                                        "Value %3d | PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | PDADC %3d "
+                                        "Value %3d |\n",
+                                        i, 4 * j, pdadcValues[4 * j],
+                                        4 * j + 1, pdadcValues[4 * j + 1],
+                                        4 * j + 2, pdadcValues[4 * j + 2],
+                                        4 * j + 3, pdadcValues[4 * j + 3]);
 
                                 regOffset += 4;
                         }
+                        REGWRITE_BUFFER_FLUSH(ah);
                 }
         }
 
@@ -1003,9 +875,9 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
 
         int i;
         int16_t twiceLargestAntenna;
@@ -1021,13 +893,16 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
                 0, {0, 0, 0, 0}
         };
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11a[] =
-                { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
-        u16 ctlModesFor11g[] =
-                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
-                  CTL_2GHT40
-                };
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        static const u16 ctlModesFor11a[] = {
+                CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
+        };
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         int tx_chainmask;
         u16 twiceMinEdgePower;
@@ -1062,15 +937,19 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
         case 1:
                 break;
         case 2:
-                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         case 3:
-                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         }
 
-        scaledPower = max((u16)0, scaledPower);
-
         if (IS_CHAN_2GHZ(chan)) {
                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
                         SUB_NUM_CTL_MODES_AT_2G_40;
@@ -1143,7 +1022,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 
                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+                        twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                         if ((((cfgCtl & ~CTL_MODE_M) |
@@ -1258,7 +1137,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                                     u16 cfgCtl,
                                     u8 twiceAntennaReduction,
                                     u8 twiceMaxRegulatoryPower,
-                                    u8 powerLimit)
+                                    u8 powerLimit, bool test)
 {
 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
@@ -1285,13 +1164,45 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
-                        ratesArray[i] = AR5416_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
+        }
+
+        if (!test) {
+                i = rate6mb;
+
+                if (IS_CHAN_HT40(chan))
+                        i = rateHt40_0;
+                else if (IS_CHAN_HT20(chan))
+                        i = rateHt20_0;
+
+                regulatory->max_power_level = ratesArray[i];
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        switch(ar5416_get_ntxchains(ah->txchainmask)) {
+        case 1:
+                break;
+        case 2:
+                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
+                break;
+        case 3:
+                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
+                break;
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
+                        "Invalid chainmask configuration\n");
+                break;
+        }
+
+        if (test)
+                return;
+
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++) {
                         int8_t pwr_table_offset;
 
@@ -1301,6 +1212,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                 }
         }
 
+        ENABLE_REGWRITE_BUFFER(ah);
+
         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
@@ -1388,61 +1301,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
 
-        i = rate6mb;
-
-        if (IS_CHAN_HT40(chan))
-                i = rateHt40_0;
-        else if (IS_CHAN_HT20(chan))
-                i = rateHt20_0;
-
-        if (AR_SREV_9280_10_OR_LATER(ah))
-                regulatory->max_power_level =
-                        ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
-        else
-                regulatory->max_power_level = ratesArray[i];
-
-        switch(ar5416_get_ntxchains(ah->txchainmask)) {
-        case 1:
-                break;
-        case 2:
-                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
-                break;
-        case 3:
-                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
-                break;
-        default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
-                          "Invalid chainmask configuration\n");
-                break;
-        }
-}
-
-static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
-                                          enum ieee80211_band freq_band)
-{
-        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
-        struct modal_eep_header *pModal =
-                &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
-        struct base_eep_header *pBase = &eep->baseEepHeader;
-        u8 num_ant_config;
-
-        num_ant_config = 1;
-
-        if (pBase->version >= 0x0E0D)
-                if (pModal->useAnt1)
-                        num_ant_config += 1;
-
-        return num_ant_config;
-}
-
-static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                               struct ath9k_channel *chan)
-{
-        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
-        struct modal_eep_header *pModal =
-                &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
-
-        return pModal->antCtrlCommon;
+        REGWRITE_BUFFER_FLUSH(ah);
 }
 
 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
@@ -1453,17 +1312,17 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_DEF_SPURCHAN;
@@ -1481,8 +1340,6 @@ const struct eeprom_ops eep_def_ops = {
         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_def_set_board_values,
         .set_addac              = ath9k_hw_def_set_addac,
         .set_txpower            = ath9k_hw_def_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 3a8ee999da5d..bc713fc28191 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,123 +20,37 @@
 /*       LED functions          */
 /********************************/
 
-static void ath_led_blink_work(struct work_struct *work)
-{
-        struct ath_softc *sc = container_of(work, struct ath_softc,
-                                            ath_led_blink_work.work);
-
-        if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
-                return;
-
-        if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
-            (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
-                ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
-        else
-                ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
-                                  (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
-
-        ieee80211_queue_delayed_work(sc->hw,
-                                     &sc->ath_led_blink_work,
-                                     (sc->sc_flags & SC_OP_LED_ON) ?
-                                        msecs_to_jiffies(sc->led_off_duration) :
-                                        msecs_to_jiffies(sc->led_on_duration));
-
-        sc->led_on_duration = sc->led_on_cnt ?
-                        max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
-                        ATH_LED_ON_DURATION_IDLE;
-        sc->led_off_duration = sc->led_off_cnt ?
-                        max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
-                        ATH_LED_OFF_DURATION_IDLE;
-        sc->led_on_cnt = sc->led_off_cnt = 0;
-        if (sc->sc_flags & SC_OP_LED_ON)
-                sc->sc_flags &= ~SC_OP_LED_ON;
-        else
-                sc->sc_flags |= SC_OP_LED_ON;
-}
-
+#ifdef CONFIG_MAC80211_LEDS
 static void ath_led_brightness(struct led_classdev *led_cdev,
                                enum led_brightness brightness)
 {
-        struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
-        struct ath_softc *sc = led->sc;
-
-        switch (brightness) {
-        case LED_OFF:
-                if (led->led_type == ATH_LED_ASSOC ||
-                    led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
-                                (led->led_type == ATH_LED_RADIO));
-                        sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
-                        if (led->led_type == ATH_LED_RADIO)
-                                sc->sc_flags &= ~SC_OP_LED_ON;
-                } else {
-                        sc->led_off_cnt++;
-                }
-                break;
-        case LED_FULL:
-                if (led->led_type == ATH_LED_ASSOC) {
-                        sc->sc_flags |= SC_OP_LED_ASSOCIATED;
-                        if (led_blink)
-                                ieee80211_queue_delayed_work(sc->hw,
-                                                     &sc->ath_led_blink_work, 0);
-                } else if (led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
-                        sc->sc_flags |= SC_OP_LED_ON;
-                } else {
-                        sc->led_on_cnt++;
-                }
-                break;
-        default:
-                break;
-        }
-}
-
-static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
-                            char *trigger)
-{
-        int ret;
-
-        led->sc = sc;
-        led->led_cdev.name = led->name;
-        led->led_cdev.default_trigger = trigger;
-        led->led_cdev.brightness_set = ath_led_brightness;
-
-        ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
-        if (ret)
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Failed to register led:%s", led->name);
-        else
-                led->registered = 1;
-        return ret;
-}
-
-static void ath_unregister_led(struct ath_led *led)
-{
-        if (led->registered) {
-                led_classdev_unregister(&led->led_cdev);
-                led->registered = 0;
-        }
+        struct ath_softc *sc = container_of(led_cdev, struct ath_softc, led_cdev);
+        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, (brightness == LED_OFF));
 }
 
 void ath_deinit_leds(struct ath_softc *sc)
 {
-        ath_unregister_led(&sc->assoc_led);
-        sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
-        ath_unregister_led(&sc->tx_led);
-        ath_unregister_led(&sc->rx_led);
-        ath_unregister_led(&sc->radio_led);
-        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
+        if (!sc->led_registered)
+                return;
+
+        ath_led_brightness(&sc->led_cdev, LED_OFF);
+        led_classdev_unregister(&sc->led_cdev);
 }
 
 void ath_init_leds(struct ath_softc *sc)
 {
-        char *trigger;
         int ret;
 
-        if (AR_SREV_9287(sc->sc_ah))
-                sc->sc_ah->led_pin = ATH_LED_PIN_9287;
-        else
-                sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
+        if (sc->sc_ah->led_pin < 0) {
+                if (AR_SREV_9287(sc->sc_ah))
+                        sc->sc_ah->led_pin = ATH_LED_PIN_9287;
+                else if (AR_SREV_9485(sc->sc_ah))
+                        sc->sc_ah->led_pin = ATH_LED_PIN_9485;
+                else if (AR_SREV_9300(sc->sc_ah))
+                        sc->sc_ah->led_pin = ATH_LED_PIN_9300;
+                else
+                        sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
+        }
 
         /* Configure gpio 1 for output */
         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
@@ -144,48 +58,22 @@ void ath_init_leds(struct ath_softc *sc)
         /* LED off, active low */
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
-        if (led_blink)
-                INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
-
-        trigger = ieee80211_get_radio_led_name(sc->hw);
-        snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
-                "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->radio_led, trigger);
-        sc->radio_led.led_type = ATH_LED_RADIO;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_assoc_led_name(sc->hw);
-        snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
-                "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->assoc_led, trigger);
-        sc->assoc_led.led_type = ATH_LED_ASSOC;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_tx_led_name(sc->hw);
-        snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
-                "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->tx_led, trigger);
-        sc->tx_led.led_type = ATH_LED_TX;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_rx_led_name(sc->hw);
-        snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
-                "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->rx_led, trigger);
-        sc->rx_led.led_type = ATH_LED_RX;
-        if (ret)
-                goto fail;
-
-        return;
-
-fail:
-        if (led_blink)
-                cancel_delayed_work_sync(&sc->ath_led_blink_work);
-        ath_deinit_leds(sc);
+        if (!led_blink)
+                sc->led_cdev.default_trigger =
+                        ieee80211_get_radio_led_name(sc->hw);
+
+        snprintf(sc->led_name, sizeof(sc->led_name),
+                "ath9k-%s", wiphy_name(sc->hw->wiphy));
+        sc->led_cdev.name = sc->led_name;
+        sc->led_cdev.brightness_set = ath_led_brightness;
+
+        ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &sc->led_cdev);
+        if (ret < 0)
+                return;
+
+        sc->led_registered = true;
 }
+#endif
 
 /*******************/
 /*      Rfkill     */
@@ -201,8 +89,7 @@ static bool ath_is_rfkill_set(struct ath_softc *sc)
 
 void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         bool blocked = !!ath_is_rfkill_set(sc);
 
         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
@@ -236,13 +123,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
                 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
                 /* Detect if colocated bt started scanning */
                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
-                                  "BT scan detected");
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
+                                "BT scan detected\n");
                         sc->sc_flags |= (SC_OP_BT_SCAN |
                                          SC_OP_BT_PRIORITY_DETECTED);
                 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
-                                  "BT priority traffic detected");
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
+                                "BT priority traffic detected\n");
                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
                 }
 
@@ -251,45 +138,15 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
         }
 }
 
-/*
- * Configures appropriate weight based on stomp type.
- */
-static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
-                                  enum ath_stomp_type stomp_type)
-{
-        struct ath_hw *ah = sc->sc_ah;
-
-        switch (stomp_type) {
-        case ATH_BTCOEX_STOMP_ALL:
-                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
-                                           AR_STOMP_ALL_WLAN_WGHT);
-                break;
-        case ATH_BTCOEX_STOMP_LOW:
-                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
-                                           AR_STOMP_LOW_WLAN_WGHT);
-                break;
-        case ATH_BTCOEX_STOMP_NONE:
-                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
-                                           AR_STOMP_NONE_WLAN_WGHT);
-                break;
-        default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                          "Invalid Stomptype\n");
-                break;
-        }
-
-        ath9k_hw_btcoex_enable(ah);
-}
-
 static void ath9k_gen_timer_start(struct ath_hw *ah,
                                   struct ath_gen_timer *timer,
-                                  u32 timer_next,
+                                  u32 trig_timeout,
                                   u32 timer_period)
 {
-        ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
+        ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
 
         if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 ah->imask |= ATH9K_INT_GENTIMER;
                 ath9k_hw_set_interrupts(ah, ah->imask);
         }
@@ -303,7 +160,7 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
 
         /* if no timer is enabled, turn off interrupt mask */
         if (timer_table->timer_mask.val == 0) {
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 ah->imask &= ~ATH9K_INT_GENTIMER;
                 ath9k_hw_set_interrupts(ah, ah->imask);
         }
@@ -322,13 +179,14 @@ static void ath_btcoex_period_timer(unsigned long data)
         u32 timer_period;
         bool is_btscan;
 
+        ath9k_ps_wakeup(sc);
         ath_detect_bt_priority(sc);
 
         is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
 
         spin_lock_bh(&btcoex->btcoex_lock);
 
-        ath9k_btcoex_bt_stomp(sc, is_btscan ? ATH_BTCOEX_STOMP_ALL :
+        ath9k_hw_btcoex_bt_stomp(ah, is_btscan ? ATH_BTCOEX_STOMP_ALL :
                               btcoex->bt_stomp_type);
 
         spin_unlock_bh(&btcoex->btcoex_lock);
@@ -339,13 +197,12 @@ static void ath_btcoex_period_timer(unsigned long data)
 
                 timer_period = is_btscan ? btcoex->btscan_no_stomp :
                                            btcoex->btcoex_no_stomp;
-                ath9k_gen_timer_start(ah,
-                                      btcoex->no_stomp_timer,
-                                      (ath9k_hw_gettsf32(ah) +
-                                       timer_period), timer_period * 10);
+                ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
+                                      timer_period * 10);
                 btcoex->hw_timer_enabled = true;
         }
 
+        ath9k_ps_restore(sc);
         mod_timer(&btcoex->period_timer, jiffies +
                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
 }
@@ -359,19 +216,22 @@ static void ath_btcoex_no_stomp_timer(void *arg)
         struct ath_softc *sc = (struct ath_softc *)arg;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_btcoex *btcoex = &sc->btcoex;
+        struct ath_common *common = ath9k_hw_common(ah);
         bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                  "no stomp timer running\n");
+        ath_dbg(common, ATH_DBG_BTCOEX,
+                "no stomp timer running\n");
 
+        ath9k_ps_wakeup(sc);
         spin_lock_bh(&btcoex->btcoex_lock);
 
         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
-                ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
-                ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
 
         spin_unlock_bh(&btcoex->btcoex_lock);
+        ath9k_ps_restore(sc);
 }
 
 int ath_init_btcoex_timer(struct ath_softc *sc)
@@ -408,8 +268,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
         struct ath_btcoex *btcoex = &sc->btcoex;
         struct ath_hw *ah = sc->sc_ah;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                  "Starting btcoex timers");
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                "Starting btcoex timers\n");
 
         /* make sure duty cycle timer is also stopped when resuming */
         if (btcoex->hw_timer_enabled)
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 17e7a9a367e7..260f1f37a60e 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,26 +17,42 @@
 #include "htc.h"
 
 /* identify firmware images */
-#define FIRMWARE_AR7010         "ar7010.fw"
-#define FIRMWARE_AR7010_1_1     "ar7010_1_1.fw"
-#define FIRMWARE_AR9271         "ar9271.fw"
+#define FIRMWARE_AR7010_1_1     "htc_7010.fw"
+#define FIRMWARE_AR9271         "htc_9271.fw"
 
-MODULE_FIRMWARE(FIRMWARE_AR7010);
 MODULE_FIRMWARE(FIRMWARE_AR7010_1_1);
 MODULE_FIRMWARE(FIRMWARE_AR9271);
 
 static struct usb_device_id ath9k_hif_usb_ids[] = {
         { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */
         { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */
-        { USB_DEVICE(0x0cf3, 0x7010) }, /* Atheros */
-        { USB_DEVICE(0x0cf3, 0x7015) }, /* Atheros */
         { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */
-        { USB_DEVICE(0x0846, 0x9018) }, /* Netgear WNDA3200 */
         { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */
         { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */
         { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */
+        { USB_DEVICE(0x13D3, 0x3346) }, /* IMC Networks */
+        { USB_DEVICE(0x13D3, 0x3348) }, /* Azurewave */
+        { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */
+        { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */
         { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */
-        { USB_DEVICE(0x083A, 0xA704) }, /* SMC Networks */
+        { USB_DEVICE(0x040D, 0x3801) }, /* VIA */
+        { USB_DEVICE(0x0cf3, 0xb003) }, /* Ubiquiti WifiStation Ext */
+
+        { USB_DEVICE(0x0cf3, 0x7015),
+          .driver_info = AR9287_USB },  /* Atheros */
+        { USB_DEVICE(0x1668, 0x1200),
+          .driver_info = AR9287_USB },  /* Verizon */
+
+        { USB_DEVICE(0x0cf3, 0x7010),
+          .driver_info = AR9280_USB },  /* Atheros */
+        { USB_DEVICE(0x0846, 0x9018),
+          .driver_info = AR9280_USB },  /* Netgear WNDA3200 */
+        { USB_DEVICE(0x083A, 0xA704),
+          .driver_info = AR9280_USB },  /* SMC Networks */
+
+        { USB_DEVICE(0x0cf3, 0x20ff),
+          .driver_info = STORAGE_DEVICE },
+
         { },
 };
 
@@ -62,7 +78,7 @@ static void hif_usb_regout_cb(struct urb *urb)
 
         if (cmd) {
                 ath9k_htc_txcompletion_cb(cmd->hif_dev->htc_handle,
-                                          cmd->skb, 1);
+                                          cmd->skb, true);
                 kfree(cmd);
         }
 
@@ -92,10 +108,10 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
         cmd->skb = skb;
         cmd->hif_dev = hif_dev;
 
-        usb_fill_int_urb(urb, hif_dev->udev,
-                         usb_sndintpipe(hif_dev->udev, USB_REG_OUT_PIPE),
+        usb_fill_bulk_urb(urb, hif_dev->udev,
+                         usb_sndbulkpipe(hif_dev->udev, USB_REG_OUT_PIPE),
                          skb->data, skb->len,
-                         hif_usb_regout_cb, cmd, 1);
+                         hif_usb_regout_cb, cmd);
 
         usb_anchor_urb(urb, &hif_dev->regout_submitted);
         ret = usb_submit_urb(urb, GFP_KERNEL);
@@ -108,6 +124,90 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
         return ret;
 }
 
+static void hif_usb_mgmt_cb(struct urb *urb)
+{
+        struct cmd_buf *cmd = (struct cmd_buf *)urb->context;
+        struct hif_device_usb *hif_dev = cmd->hif_dev;
+        bool txok = true;
+
+        if (!cmd || !cmd->skb || !cmd->hif_dev)
+                return;
+
+        switch (urb->status) {
+        case 0:
+                break;
+        case -ENOENT:
+        case -ECONNRESET:
+        case -ENODEV:
+        case -ESHUTDOWN:
+                txok = false;
+
+                /*
+                 * If the URBs are being flushed, no need to complete
+                 * this packet.
+                 */
+                spin_lock(&hif_dev->tx.tx_lock);
+                if (hif_dev->tx.flags & HIF_USB_TX_FLUSH) {
+                        spin_unlock(&hif_dev->tx.tx_lock);
+                        dev_kfree_skb_any(cmd->skb);
+                        kfree(cmd);
+                        return;
+                }
+                spin_unlock(&hif_dev->tx.tx_lock);
+
+                break;
+        default:
+                txok = false;
+                break;
+        }
+
+        skb_pull(cmd->skb, 4);
+        ath9k_htc_txcompletion_cb(cmd->hif_dev->htc_handle,
+                                  cmd->skb, txok);
+        kfree(cmd);
+}
+
+static int hif_usb_send_mgmt(struct hif_device_usb *hif_dev,
+                             struct sk_buff *skb)
+{
+        struct urb *urb;
+        struct cmd_buf *cmd;
+        int ret = 0;
+        __le16 *hdr;
+
+        urb = usb_alloc_urb(0, GFP_ATOMIC);
+        if (urb == NULL)
+                return -ENOMEM;
+
+        cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
+        if (cmd == NULL) {
+                usb_free_urb(urb);
+                return -ENOMEM;
+        }
+
+        cmd->skb = skb;
+        cmd->hif_dev = hif_dev;
+
+        hdr = (__le16 *) skb_push(skb, 4);
+        *hdr++ = cpu_to_le16(skb->len - 4);
+        *hdr++ = cpu_to_le16(ATH_USB_TX_STREAM_MODE_TAG);
+
+        usb_fill_bulk_urb(urb, hif_dev->udev,
+                         usb_sndbulkpipe(hif_dev->udev, USB_WLAN_TX_PIPE),
+                         skb->data, skb->len,
+                         hif_usb_mgmt_cb, cmd);
+
+        usb_anchor_urb(urb, &hif_dev->mgmt_submitted);
+        ret = usb_submit_urb(urb, GFP_ATOMIC);
+        if (ret) {
+                usb_unanchor_urb(urb);
+                kfree(cmd);
+        }
+        usb_free_urb(urb);
+
+        return ret;
+}
+
 static inline void ath9k_skb_queue_purge(struct hif_device_usb *hif_dev,
                                          struct sk_buff_head *list)
 {
@@ -115,7 +215,22 @@ static inline void ath9k_skb_queue_purge(struct hif_device_usb *hif_dev,
 
         while ((skb = __skb_dequeue(list)) != NULL) {
                 dev_kfree_skb_any(skb);
-                TX_STAT_INC(skb_dropped);
+        }
+}
+
+static inline void ath9k_skb_queue_complete(struct hif_device_usb *hif_dev,
+                                            struct sk_buff_head *queue,
+                                            bool txok)
+{
+        struct sk_buff *skb;
+
+        while ((skb = __skb_dequeue(queue)) != NULL) {
+                ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
+                                          skb, txok);
+                if (txok)
+                        TX_STAT_INC(skb_success);
+                else
+                        TX_STAT_INC(skb_failed);
         }
 }
 
@@ -123,7 +238,7 @@ static void hif_usb_tx_cb(struct urb *urb)
 {
         struct tx_buf *tx_buf = (struct tx_buf *) urb->context;
         struct hif_device_usb *hif_dev;
-        struct sk_buff *skb;
+        bool txok = true;
 
         if (!tx_buf || !tx_buf->hif_dev)
                 return;
@@ -137,33 +252,28 @@ static void hif_usb_tx_cb(struct urb *urb)
         case -ECONNRESET:
         case -ENODEV:
         case -ESHUTDOWN:
+                txok = false;
+
                 /*
-                 * The URB has been killed, free the SKBs
-                 * and return.
+                 * If the URBs are being flushed, no need to add this
+                 * URB to the free list.
                  */
-                ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
-                return;
+                spin_lock(&hif_dev->tx.tx_lock);
+                if (hif_dev->tx.flags & HIF_USB_TX_FLUSH) {
+                        spin_unlock(&hif_dev->tx.tx_lock);
+                        ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
+                        return;
+                }
+                spin_unlock(&hif_dev->tx.tx_lock);
+
+                break;
         default:
+                txok = false;
                 break;
         }
 
-        /* Check if TX has been stopped */
-        spin_lock(&hif_dev->tx.tx_lock);
-        if (hif_dev->tx.flags & HIF_USB_TX_STOP) {
-                spin_unlock(&hif_dev->tx.tx_lock);
-                ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
-                goto add_free;
-        }
-        spin_unlock(&hif_dev->tx.tx_lock);
-
-        /* Complete the queued SKBs. */
-        while ((skb = __skb_dequeue(&tx_buf->skb_queue)) != NULL) {
-                ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
-                                          skb, 1);
-                TX_STAT_INC(skb_completed);
-        }
+        ath9k_skb_queue_complete(hif_dev, &tx_buf->skb_queue, txok);
 
-add_free:
         /* Re-initialize the SKB queue */
         tx_buf->len = tx_buf->offset = 0;
         __skb_queue_head_init(&tx_buf->skb_queue);
@@ -184,8 +294,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
         struct tx_buf *tx_buf = NULL;
         struct sk_buff *nskb = NULL;
         int ret = 0, i;
-        u16 *hdr, tx_skb_cnt = 0;
+        u16 tx_skb_cnt = 0;
         u8 *buf;
+        __le16 *hdr;
 
         if (hif_dev->tx.tx_skb_cnt == 0)
                 return 0;
@@ -210,9 +321,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
 
                 buf = tx_buf->buf;
                 buf += tx_buf->offset;
-                hdr = (u16 *)buf;
-                *hdr++ = nskb->len;
-                *hdr++ = ATH_USB_TX_STREAM_MODE_TAG;
+                hdr = (__le16 *)buf;
+                *hdr++ = cpu_to_le16(nskb->len);
+                *hdr++ = cpu_to_le16(ATH_USB_TX_STREAM_MODE_TAG);
                 buf += 4;
                 memcpy(buf, nskb->data, nskb->len);
                 tx_buf->len = nskb->len + 4;
@@ -235,7 +346,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
         ret = usb_submit_urb(tx_buf->urb, GFP_ATOMIC);
         if (ret) {
                 tx_buf->len = tx_buf->offset = 0;
-                ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
+                ath9k_skb_queue_complete(hif_dev, &tx_buf->skb_queue, false);
                 __skb_queue_head_init(&tx_buf->skb_queue);
                 list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf);
                 hif_dev->tx.tx_buf_cnt++;
@@ -247,10 +358,11 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
         return ret;
 }
 
-static int hif_usb_send_tx(struct hif_device_usb *hif_dev, struct sk_buff *skb,
-                           struct ath9k_htc_tx_ctl *tx_ctl)
+static int hif_usb_send_tx(struct hif_device_usb *hif_dev, struct sk_buff *skb)
 {
+        struct ath9k_htc_tx_ctl *tx_ctl;
         unsigned long flags;
+        int ret = 0;
 
         spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
 
@@ -265,26 +377,36 @@ static int hif_usb_send_tx(struct hif_device_usb *hif_dev, struct sk_buff *skb,
                 return -ENOMEM;
         }
 
-        __skb_queue_tail(&hif_dev->tx.tx_skb_queue, skb);
-        hif_dev->tx.tx_skb_cnt++;
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
+        tx_ctl = HTC_SKB_CB(skb);
 
-        /* Send normal frames immediately */
-        if (!tx_ctl || (tx_ctl && (tx_ctl->type == ATH9K_HTC_NORMAL)))
-                __hif_usb_tx(hif_dev);
+        /* Mgmt/Beacon frames don't use the TX buffer pool */
+        if ((tx_ctl->type == ATH9K_HTC_MGMT) ||
+            (tx_ctl->type == ATH9K_HTC_BEACON)) {
+                ret = hif_usb_send_mgmt(hif_dev, skb);
+        }
+
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+
+        if ((tx_ctl->type == ATH9K_HTC_NORMAL) ||
+            (tx_ctl->type == ATH9K_HTC_AMPDU)) {
+                __skb_queue_tail(&hif_dev->tx.tx_skb_queue, skb);
+                hif_dev->tx.tx_skb_cnt++;
+        }
 
         /* Check if AMPDUs have to be sent immediately */
-        if (tx_ctl && (tx_ctl->type == ATH9K_HTC_AMPDU) &&
-            (hif_dev->tx.tx_buf_cnt == MAX_TX_URB_NUM) &&
+        if ((hif_dev->tx.tx_buf_cnt == MAX_TX_URB_NUM) &&
             (hif_dev->tx.tx_skb_cnt < 2)) {
                 __hif_usb_tx(hif_dev);
         }
 
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
 
-        return 0;
+        return ret;
 }
 
-static void hif_usb_start(void *hif_handle, u8 pipe_id)
+static void hif_usb_start(void *hif_handle)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
         unsigned long flags;
@@ -296,27 +418,35 @@ static void hif_usb_start(void *hif_handle, u8 pipe_id)
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
 }
 
-static void hif_usb_stop(void *hif_handle, u8 pipe_id)
+static void hif_usb_stop(void *hif_handle)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
+        struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
         unsigned long flags;
 
         spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
-        ath9k_skb_queue_purge(hif_dev, &hif_dev->tx.tx_skb_queue);
+        ath9k_skb_queue_complete(hif_dev, &hif_dev->tx.tx_skb_queue, false);
         hif_dev->tx.tx_skb_cnt = 0;
         hif_dev->tx.flags |= HIF_USB_TX_STOP;
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
+        /* The pending URBs have to be canceled. */
+        list_for_each_entry_safe(tx_buf, tx_buf_tmp,
+                                 &hif_dev->tx.tx_pending, list) {
+                usb_kill_urb(tx_buf->urb);
+        }
+
+        usb_kill_anchored_urbs(&hif_dev->mgmt_submitted);
 }
 
-static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb,
-                        struct ath9k_htc_tx_ctl *tx_ctl)
+static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
         int ret = 0;
 
         switch (pipe_id) {
         case USB_WLAN_TX_PIPE:
-                ret = hif_usb_send_tx(hif_dev, skb, tx_ctl);
+                ret = hif_usb_send_tx(hif_dev, skb);
                 break;
         case USB_REG_OUT_PIPE:
                 ret = hif_usb_send_regout(hif_dev, skb);
@@ -331,6 +461,40 @@ static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb,
         return ret;
 }
 
+static inline bool check_index(struct sk_buff *skb, u8 idx)
+{
+        struct ath9k_htc_tx_ctl *tx_ctl;
+
+        tx_ctl = HTC_SKB_CB(skb);
+
+        if ((tx_ctl->type == ATH9K_HTC_AMPDU) &&
+            (tx_ctl->sta_idx == idx))
+                return true;
+
+        return false;
+}
+
+static void hif_usb_sta_drain(void *hif_handle, u8 idx)
+{
+        struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
+        struct sk_buff *skb, *tmp;
+        unsigned long flags;
+
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+
+        skb_queue_walk_safe(&hif_dev->tx.tx_skb_queue, skb, tmp) {
+                if (check_index(skb, idx)) {
+                        __skb_unlink(skb, &hif_dev->tx.tx_skb_queue);
+                        ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
+                                                  skb, false);
+                        hif_dev->tx.tx_skb_cnt--;
+                        TX_STAT_INC(skb_failed);
+                }
+        }
+
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+}
+
 static struct ath9k_htc_hif hif_usb = {
         .transport = ATH9K_HIF_USB,
         .name = "ath9k_hif_usb",
@@ -340,6 +504,7 @@ static struct ath9k_htc_hif hif_usb = {
 
         .start = hif_usb_start,
         .stop = hif_usb_stop,
+        .sta_drain = hif_usb_sta_drain,
         .send = hif_usb_send,
 };
 
@@ -347,9 +512,9 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
                                     struct sk_buff *skb)
 {
         struct sk_buff *nskb, *skb_pool[MAX_PKT_NUM_IN_TRANSFER];
-        int index = 0, i = 0, chk_idx, len = skb->len;
-        int rx_remain_len = 0, rx_pkt_len = 0;
-        u16 pkt_len, pkt_tag, pool_index = 0;
+        int index = 0, i = 0, len = skb->len;
+        int rx_remain_len, rx_pkt_len;
+        u16 pool_index = 0;
         u8 *ptr;
 
         spin_lock(&hif_dev->rx_lock);
@@ -383,64 +548,64 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
         spin_unlock(&hif_dev->rx_lock);
 
         while (index < len) {
+                u16 pkt_len;
+                u16 pkt_tag;
+                u16 pad_len;
+                int chk_idx;
+
                 ptr = (u8 *) skb->data;
 
                 pkt_len = ptr[index] + (ptr[index+1] << 8);
                 pkt_tag = ptr[index+2] + (ptr[index+3] << 8);
 
-                if (pkt_tag == ATH_USB_RX_STREAM_MODE_TAG) {
-                        u16 pad_len;
-
-                        pad_len = 4 - (pkt_len & 0x3);
-                        if (pad_len == 4)
-                                pad_len = 0;
-
-                        chk_idx = index;
-                        index = index + 4 + pkt_len + pad_len;
-
-                        if (index > MAX_RX_BUF_SIZE) {
-                                spin_lock(&hif_dev->rx_lock);
-                                hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE;
-                                hif_dev->rx_transfer_len =
-                                        MAX_RX_BUF_SIZE - chk_idx - 4;
-                                hif_dev->rx_pad_len = pad_len;
-
-                                nskb = __dev_alloc_skb(pkt_len + 32,
-                                                       GFP_ATOMIC);
-                                if (!nskb) {
-                                        dev_err(&hif_dev->udev->dev,
-                                        "ath9k_htc: RX memory allocation"
-                                        " error\n");
-                                        spin_unlock(&hif_dev->rx_lock);
-                                        goto err;
-                                }
-                                skb_reserve(nskb, 32);
-                                RX_STAT_INC(skb_allocated);
-
-                                memcpy(nskb->data, &(skb->data[chk_idx+4]),
-                                       hif_dev->rx_transfer_len);
-
-                                /* Record the buffer pointer */
-                                hif_dev->remain_skb = nskb;
+                if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) {
+                        RX_STAT_INC(skb_dropped);
+                        return;
+                }
+
+                pad_len = 4 - (pkt_len & 0x3);
+                if (pad_len == 4)
+                        pad_len = 0;
+
+                chk_idx = index;
+                index = index + 4 + pkt_len + pad_len;
+
+                if (index > MAX_RX_BUF_SIZE) {
+                        spin_lock(&hif_dev->rx_lock);
+                        hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE;
+                        hif_dev->rx_transfer_len =
+                                MAX_RX_BUF_SIZE - chk_idx - 4;
+                        hif_dev->rx_pad_len = pad_len;
+
+                        nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
+                        if (!nskb) {
+                                dev_err(&hif_dev->udev->dev,
+                                        "ath9k_htc: RX memory allocation error\n");
                                 spin_unlock(&hif_dev->rx_lock);
-                        } else {
-                                nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
-                                if (!nskb) {
-                                        dev_err(&hif_dev->udev->dev,
-                                        "ath9k_htc: RX memory allocation"
-                                        " error\n");
-                                        goto err;
-                                }
-                                skb_reserve(nskb, 32);
-                                RX_STAT_INC(skb_allocated);
-
-                                memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len);
-                                skb_put(nskb, pkt_len);
-                                skb_pool[pool_index++] = nskb;
+                                goto err;
                         }
+                        skb_reserve(nskb, 32);
+                        RX_STAT_INC(skb_allocated);
+
+                        memcpy(nskb->data, &(skb->data[chk_idx+4]),
+                               hif_dev->rx_transfer_len);
+
+                        /* Record the buffer pointer */
+                        hif_dev->remain_skb = nskb;
+                        spin_unlock(&hif_dev->rx_lock);
                 } else {
-                        RX_STAT_INC(skb_dropped);
-                        return;
+                        nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
+                        if (!nskb) {
+                                dev_err(&hif_dev->udev->dev,
+                                        "ath9k_htc: RX memory allocation error\n");
+                                goto err;
+                        }
+                        skb_reserve(nskb, 32);
+                        RX_STAT_INC(skb_allocated);
+
+                        memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len);
+                        skb_put(nskb, pkt_len);
+                        skb_pool[pool_index++] = nskb;
                 }
         }
 
@@ -455,7 +620,7 @@ err:
 static void ath9k_hif_usb_rx_cb(struct urb *urb)
 {
         struct sk_buff *skb = (struct sk_buff *) urb->context;
-        struct hif_device_usb *hif_dev = (struct hif_device_usb *)
+        struct hif_device_usb *hif_dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int ret;
 
@@ -502,7 +667,7 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
 {
         struct sk_buff *skb = (struct sk_buff *) urb->context;
         struct sk_buff *nskb;
-        struct hif_device_usb *hif_dev = (struct hif_device_usb *)
+        struct hif_device_usb *hif_dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int ret;
 
@@ -521,6 +686,9 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
         case -ESHUTDOWN:
                 goto free;
         default:
+                skb_reset_tail_pointer(skb);
+                skb_trim(skb, 0);
+
                 goto resubmit;
         }
 
@@ -540,27 +708,20 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
                         return;
                 }
 
-                usb_fill_int_urb(urb, hif_dev->udev,
-                                 usb_rcvintpipe(hif_dev->udev, USB_REG_IN_PIPE),
+                usb_fill_bulk_urb(urb, hif_dev->udev,
+                                 usb_rcvbulkpipe(hif_dev->udev,
+                                                 USB_REG_IN_PIPE),
                                  nskb->data, MAX_REG_IN_BUF_SIZE,
-                                 ath9k_hif_usb_reg_in_cb, nskb, 1);
-
-                ret = usb_submit_urb(urb, GFP_ATOMIC);
-                if (ret) {
-                        kfree_skb(nskb);
-                        urb->context = NULL;
-                }
-
-                return;
+                                 ath9k_hif_usb_reg_in_cb, nskb);
         }
 
 resubmit:
-        skb_reset_tail_pointer(skb);
-        skb_trim(skb, 0);
-
+        usb_anchor_urb(urb, &hif_dev->reg_in_submitted);
         ret = usb_submit_urb(urb, GFP_ATOMIC);
-        if (ret)
+        if (ret) {
+                usb_unanchor_urb(urb);
                 goto free;
+        }
 
         return;
 free:
@@ -571,6 +732,7 @@ free:
 static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
 {
         struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
+        unsigned long flags;
 
         list_for_each_entry_safe(tx_buf, tx_buf_tmp,
                                  &hif_dev->tx.tx_buf, list) {
@@ -581,6 +743,10 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
                 kfree(tx_buf);
         }
 
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+        hif_dev->tx.flags |= HIF_USB_TX_FLUSH;
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
         list_for_each_entry_safe(tx_buf, tx_buf_tmp,
                                  &hif_dev->tx.tx_pending, list) {
                 usb_kill_urb(tx_buf->urb);
@@ -589,6 +755,8 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
                 kfree(tx_buf->buf);
                 kfree(tx_buf);
         }
+
+        usb_kill_anchored_urbs(&hif_dev->mgmt_submitted);
 }
 
 static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev)
@@ -600,6 +768,7 @@ static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev)
         INIT_LIST_HEAD(&hif_dev->tx.tx_pending);
         spin_lock_init(&hif_dev->tx.tx_lock);
         __skb_queue_head_init(&hif_dev->tx.tx_skb_queue);
+        init_usb_anchor(&hif_dev->mgmt_submitted);
 
         for (i = 0; i < MAX_TX_URB_NUM; i++) {
                 tx_buf = kzalloc(sizeof(struct tx_buf), GFP_KERNEL);
@@ -696,42 +865,67 @@ err_urb:
         return ret;
 }
 
-static void ath9k_hif_usb_dealloc_reg_in_urb(struct hif_device_usb *hif_dev)
+static void ath9k_hif_usb_dealloc_reg_in_urbs(struct hif_device_usb *hif_dev)
 {
-        if (hif_dev->reg_in_urb) {
-                usb_kill_urb(hif_dev->reg_in_urb);
-                if (hif_dev->reg_in_urb->context)
-                        kfree_skb((void *)hif_dev->reg_in_urb->context);
-                usb_free_urb(hif_dev->reg_in_urb);
-                hif_dev->reg_in_urb = NULL;
-        }
+        usb_kill_anchored_urbs(&hif_dev->reg_in_submitted);
 }
 
-static int ath9k_hif_usb_alloc_reg_in_urb(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_alloc_reg_in_urbs(struct hif_device_usb *hif_dev)
 {
-        struct sk_buff *skb;
+        struct urb *urb = NULL;
+        struct sk_buff *skb = NULL;
+        int i, ret;
 
-        hif_dev->reg_in_urb = usb_alloc_urb(0, GFP_KERNEL);
-        if (hif_dev->reg_in_urb == NULL)
-                return -ENOMEM;
+        init_usb_anchor(&hif_dev->reg_in_submitted);
 
-        skb = alloc_skb(MAX_REG_IN_BUF_SIZE, GFP_KERNEL);
-        if (!skb)
-                goto err;
+        for (i = 0; i < MAX_REG_IN_URB_NUM; i++) {
+
+                /* Allocate URB */
+                urb = usb_alloc_urb(0, GFP_KERNEL);
+                if (urb == NULL) {
+                        ret = -ENOMEM;
+                        goto err_urb;
+                }
 
-        usb_fill_int_urb(hif_dev->reg_in_urb, hif_dev->udev,
-                         usb_rcvintpipe(hif_dev->udev, USB_REG_IN_PIPE),
-                         skb->data, MAX_REG_IN_BUF_SIZE,
-                         ath9k_hif_usb_reg_in_cb, skb, 1);
+                /* Allocate buffer */
+                skb = alloc_skb(MAX_REG_IN_BUF_SIZE, GFP_KERNEL);
+                if (!skb) {
+                        ret = -ENOMEM;
+                        goto err_skb;
+                }
 
-        if (usb_submit_urb(hif_dev->reg_in_urb, GFP_KERNEL) != 0)
-                goto err;
+                usb_fill_bulk_urb(urb, hif_dev->udev,
+                                  usb_rcvbulkpipe(hif_dev->udev,
+                                                  USB_REG_IN_PIPE),
+                                  skb->data, MAX_REG_IN_BUF_SIZE,
+                                  ath9k_hif_usb_reg_in_cb, skb);
+
+                /* Anchor URB */
+                usb_anchor_urb(urb, &hif_dev->reg_in_submitted);
+
+                /* Submit URB */
+                ret = usb_submit_urb(urb, GFP_KERNEL);
+                if (ret) {
+                        usb_unanchor_urb(urb);
+                        goto err_submit;
+                }
+
+                /*
+                 * Drop reference count.
+                 * This ensures that the URB is freed when killing them.
+                 */
+                usb_free_urb(urb);
+        }
 
         return 0;
 
-err:
-        ath9k_hif_usb_dealloc_reg_in_urb(hif_dev);
-        return -ENOMEM;
+err_submit:
+        kfree_skb(skb);
+err_skb:
+        usb_free_urb(urb);
+err_urb:
+        ath9k_hif_usb_dealloc_reg_in_urbs(hif_dev);
+        return ret;
 }
 
 static int ath9k_hif_usb_alloc_urbs(struct hif_device_usb *hif_dev)
@@ -748,7 +942,7 @@ static int ath9k_hif_usb_alloc_urbs(struct hif_device_usb *hif_dev)
                 goto err_rx;
 
         /* Register Read */
-        if (ath9k_hif_usb_alloc_reg_in_urb(hif_dev) < 0)
+        if (ath9k_hif_usb_alloc_reg_in_urbs(hif_dev) < 0)
                 goto err_reg;
 
         return 0;
@@ -763,12 +957,13 @@ err:
 static void ath9k_hif_usb_dealloc_urbs(struct hif_device_usb *hif_dev)
 {
         usb_kill_anchored_urbs(&hif_dev->regout_submitted);
-        ath9k_hif_usb_dealloc_reg_in_urb(hif_dev);
+        ath9k_hif_usb_dealloc_reg_in_urbs(hif_dev);
         ath9k_hif_usb_dealloc_tx_urbs(hif_dev);
         ath9k_hif_usb_dealloc_rx_urbs(hif_dev);
 }
 
-static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
+                                     u32 drv_info)
 {
         int transfer, err;
         const void *data = hif_dev->firmware->data;
@@ -799,7 +994,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
         }
         kfree(buf);
 
-        if ((hif_dev->device_id == 0x7010) || (hif_dev->device_id == 0x7015))
+        if (IS_AR7010_DEVICE(drv_info))
                 firm_offset = AR7010_FIRMWARE_TEXT;
         else
                 firm_offset = AR9271_FIRMWARE_TEXT;
@@ -820,9 +1015,11 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
         return 0;
 }
 
-static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
 {
-        int ret;
+        int ret, idx;
+        struct usb_host_interface *alt = &hif_dev->interface->altsetting[0];
+        struct usb_endpoint_descriptor *endp;
 
         /* Request firmware */
         ret = request_firmware(&hif_dev->firmware, hif_dev->fw_name,
@@ -833,28 +1030,40 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
                 goto err_fw_req;
         }
 
-        /* Alloc URBs */
-        ret = ath9k_hif_usb_alloc_urbs(hif_dev);
+        /* Download firmware */
+        ret = ath9k_hif_usb_download_fw(hif_dev, drv_info);
         if (ret) {
                 dev_err(&hif_dev->udev->dev,
-                        "ath9k_htc: Unable to allocate URBs\n");
-                goto err_urb;
+                        "ath9k_htc: Firmware - %s download failed\n",
+                        hif_dev->fw_name);
+                goto err_fw_download;
         }
 
-        /* Download firmware */
-        ret = ath9k_hif_usb_download_fw(hif_dev);
+        /* On downloading the firmware to the target, the USB descriptor of EP4
+         * is 'patched' to change the type of the endpoint to Bulk. This will
+         * bring down CPU usage during the scan period.
+         */
+        for (idx = 0; idx < alt->desc.bNumEndpoints; idx++) {
+                endp = &alt->endpoint[idx].desc;
+                if ((endp->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
+                                == USB_ENDPOINT_XFER_INT) {
+                        endp->bmAttributes &= ~USB_ENDPOINT_XFERTYPE_MASK;
+                        endp->bmAttributes |= USB_ENDPOINT_XFER_BULK;
+                        endp->bInterval = 0;
+                }
+        }
+
+        /* Alloc URBs */
+        ret = ath9k_hif_usb_alloc_urbs(hif_dev);
         if (ret) {
                 dev_err(&hif_dev->udev->dev,
-                        "ath9k_htc: Firmware - %s download failed\n",
-                        hif_dev->fw_name);
+                        "ath9k_htc: Unable to allocate URBs\n");
                 goto err_fw_download;
         }
 
         return 0;
 
 err_fw_download:
-        ath9k_hif_usb_dealloc_urbs(hif_dev);
-err_urb:
         release_firmware(hif_dev->firmware);
 err_fw_req:
         hif_dev->firmware = NULL;
@@ -868,6 +1077,61 @@ static void ath9k_hif_usb_dev_deinit(struct hif_device_usb *hif_dev)
                 release_firmware(hif_dev->firmware);
 }
 
+/*
+ * An exact copy of the function from zd1211rw.
+ */
+static int send_eject_command(struct usb_interface *interface)
+{
+        struct usb_device *udev = interface_to_usbdev(interface);
+        struct usb_host_interface *iface_desc = &interface->altsetting[0];
+        struct usb_endpoint_descriptor *endpoint;
+        unsigned char *cmd;
+        u8 bulk_out_ep;
+        int r;
+
+        /* Find bulk out endpoint */
+        for (r = 1; r >= 0; r--) {
+                endpoint = &iface_desc->endpoint[r].desc;
+                if (usb_endpoint_dir_out(endpoint) &&
+                    usb_endpoint_xfer_bulk(endpoint)) {
+                        bulk_out_ep = endpoint->bEndpointAddress;
+                        break;
+                }
+        }
+        if (r == -1) {
+                dev_err(&udev->dev,
+                        "ath9k_htc: Could not find bulk out endpoint\n");
+                return -ENODEV;
+        }
+
+        cmd = kzalloc(31, GFP_KERNEL);
+        if (cmd == NULL)
+                return -ENODEV;
+
+        /* USB bulk command block */
+        cmd[0] = 0x55;  /* bulk command signature */
+        cmd[1] = 0x53;  /* bulk command signature */
+        cmd[2] = 0x42;  /* bulk command signature */
+        cmd[3] = 0x43;  /* bulk command signature */
+        cmd[14] = 6;    /* command length */
+
+        cmd[15] = 0x1b; /* SCSI command: START STOP UNIT */
+        cmd[19] = 0x2;  /* eject disc */
+
+        dev_info(&udev->dev, "Ejecting storage device...\n");
+        r = usb_bulk_msg(udev, usb_sndbulkpipe(udev, bulk_out_ep),
+                cmd, 31, NULL, 2000);
+        kfree(cmd);
+        if (r)
+                return r;
+
+        /* At this point, the device disconnects and reconnects with the real
+         * ID numbers. */
+
+        usb_set_intfdata(interface, NULL);
+        return 0;
+}
+
 static int ath9k_hif_usb_probe(struct usb_interface *interface,
                                const struct usb_device_id *id)
 {
@@ -875,6 +1139,9 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
         struct hif_device_usb *hif_dev;
         int ret = 0;
 
+        if (id->driver_info == STORAGE_DEVICE)
+                return send_eject_command(interface);
+
         hif_dev = kzalloc(sizeof(struct hif_device_usb), GFP_KERNEL);
         if (!hif_dev) {
                 ret = -ENOMEM;
@@ -899,28 +1166,20 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
 
         /* Find out which firmware to load */
 
-        switch(hif_dev->device_id) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
-                if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202)
-                        hif_dev->fw_name = FIRMWARE_AR7010_1_1;
-                else
-                        hif_dev->fw_name = FIRMWARE_AR7010;
-                break;
-        default:
+        if (IS_AR7010_DEVICE(id->driver_info))
+                hif_dev->fw_name = FIRMWARE_AR7010_1_1;
+        else
                 hif_dev->fw_name = FIRMWARE_AR9271;
-                break;
-        }
 
-        ret = ath9k_hif_usb_dev_init(hif_dev);
+        ret = ath9k_hif_usb_dev_init(hif_dev, id->driver_info);
         if (ret) {
                 ret = -EINVAL;
                 goto err_hif_init_usb;
         }
 
         ret = ath9k_htc_hw_init(hif_dev->htc_handle,
-                                &hif_dev->udev->dev, hif_dev->device_id);
+                                &interface->dev, hif_dev->device_id,
+                                hif_dev->udev->product, id->driver_info);
         if (ret) {
                 ret = -EINVAL;
                 goto err_htc_hw_init;
@@ -963,18 +1222,18 @@ static void ath9k_hif_usb_reboot(struct usb_device *udev)
 static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
 {
         struct usb_device *udev = interface_to_usbdev(interface);
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
-
-        if (hif_dev) {
-                ath9k_htc_hw_deinit(hif_dev->htc_handle,
-                    (udev->state == USB_STATE_NOTATTACHED) ? true : false);
-                ath9k_htc_hw_free(hif_dev->htc_handle);
-                ath9k_hif_usb_dev_deinit(hif_dev);
-                usb_set_intfdata(interface, NULL);
-        }
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+        bool unplugged = (udev->state == USB_STATE_NOTATTACHED) ? true : false;
+
+        if (!hif_dev)
+                return;
+
+        ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged);
+        ath9k_htc_hw_free(hif_dev->htc_handle);
+        ath9k_hif_usb_dev_deinit(hif_dev);
+        usb_set_intfdata(interface, NULL);
 
-        if (hif_dev->flags & HIF_USB_START)
+        if (!unplugged && (hif_dev->flags & HIF_USB_START))
                 ath9k_hif_usb_reboot(udev);
 
         kfree(hif_dev);
@@ -986,8 +1245,14 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
 static int ath9k_hif_usb_suspend(struct usb_interface *interface,
                                  pm_message_t message)
 {
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+
+        /*
+         * The device has to be set to FULLSLEEP mode in case no
+         * interface is up.
+         */
+        if (!(hif_dev->flags & HIF_USB_START))
+                ath9k_htc_suspend(hif_dev->htc_handle);
 
         ath9k_hif_usb_dealloc_urbs(hif_dev);
 
@@ -996,8 +1261,8 @@ static int ath9k_hif_usb_suspend(struct usb_interface *interface,
 
 static int ath9k_hif_usb_resume(struct usb_interface *interface)
 {
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+        struct htc_target *htc_handle = hif_dev->htc_handle;
         int ret;
 
         ret = ath9k_hif_usb_alloc_urbs(hif_dev);
@@ -1005,7 +1270,8 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
                 return ret;
 
         if (hif_dev->firmware) {
-                ret = ath9k_hif_usb_download_fw(hif_dev);
+                ret = ath9k_hif_usb_download_fw(hif_dev,
+                                htc_handle->drv_priv->ah->hw_version.usbdev);
                 if (ret)
                         goto fail_resume;
         } else {
@@ -1015,7 +1281,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
 
         mdelay(100);
 
-        ret = ath9k_htc_resume(hif_dev->htc_handle);
+        ret = ath9k_htc_resume(htc_handle);
 
         if (ret)
                 goto fail_resume;
@@ -1030,7 +1296,7 @@ fail_resume:
 #endif
 
 static struct usb_driver ath9k_hif_usb_driver = {
-        .name = "ath9k_hif_usb",
+        .name = KBUILD_MODNAME,
         .probe = ath9k_hif_usb_probe,
         .disconnect = ath9k_hif_usb_disconnect,
 #ifdef CONFIG_PM
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
index 2daf97b11c08..794f63094e5d 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.h
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,6 +17,11 @@
 #ifndef HTC_USB_H
 #define HTC_USB_H
 
+#define MAJOR_VERSION_REQ 1
+#define MINOR_VERSION_REQ 3
+
+#define IS_AR7010_DEVICE(_v) (((_v) == AR9280_USB) || ((_v) == AR9287_USB))
+
 #define AR9271_FIRMWARE       0x501000
 #define AR9271_FIRMWARE_TEXT  0x903000
 #define AR7010_FIRMWARE_TEXT  0x906000
@@ -29,7 +34,7 @@
 
 /* FIXME: Verify these numbers (with Windows) */
 #define MAX_TX_URB_NUM  8
-#define MAX_TX_BUF_NUM  1024
+#define MAX_TX_BUF_NUM  256
 #define MAX_TX_BUF_SIZE 32768
 #define MAX_TX_AGGR_NUM 20
 
@@ -38,7 +43,7 @@
 #define MAX_PKT_NUM_IN_TRANSFER 10
 
 #define MAX_REG_OUT_URB_NUM  1
-#define MAX_REG_OUT_BUF_NUM  8
+#define MAX_REG_IN_URB_NUM   64
 
 #define MAX_REG_IN_BUF_SIZE 64
 
@@ -62,6 +67,7 @@ struct tx_buf {
 };
 
 #define HIF_USB_TX_STOP  BIT(0)
+#define HIF_USB_TX_FLUSH BIT(1)
 
 struct hif_usb_tx {
         u8 flags;
@@ -87,9 +93,10 @@ struct hif_device_usb {
         const struct firmware *firmware;
         struct htc_target *htc_handle;
         struct hif_usb_tx tx;
-        struct urb *reg_in_urb;
         struct usb_anchor regout_submitted;
         struct usb_anchor rx_submitted;
+        struct usb_anchor reg_in_submitted;
+        struct usb_anchor mgmt_submitted;
         struct sk_buff *remain_skb;
         const char *fw_name;
         int rx_remain_len;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 43b9e21bc562..5bc022087e65 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -32,6 +32,7 @@
 #include "wmi.h"
 
 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
+#define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 #define ATH_ANI_POLLINTERVAL      100     /* 100 ms */
 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
@@ -45,15 +46,8 @@ extern struct ieee80211_ops ath9k_htc_ops;
 extern int htc_modparam_nohwcrypt;
 
 enum htc_phymode {
-        HTC_MODE_AUTO           = 0,
-        HTC_MODE_11A            = 1,
-        HTC_MODE_11B            = 2,
-        HTC_MODE_11G            = 3,
-        HTC_MODE_FH             = 4,
-        HTC_MODE_TURBO_A        = 5,
-        HTC_MODE_TURBO_G        = 6,
-        HTC_MODE_11NA           = 7,
-        HTC_MODE_11NG           = 8
+        HTC_MODE_11NA           = 0,
+        HTC_MODE_11NG           = 1
 };
 
 enum htc_opmode {
@@ -65,23 +59,24 @@ enum htc_opmode {
         HTC_M_WDS       = 2
 };
 
-#define ATH9K_HTC_HDRSPACE sizeof(struct htc_frame_hdr)
-#define ATH9K_HTC_AMPDU 1
+#define ATH9K_HTC_AMPDU  1
 #define ATH9K_HTC_NORMAL 2
+#define ATH9K_HTC_BEACON 3
+#define ATH9K_HTC_MGMT   4
 
 #define ATH9K_HTC_TX_CTSONLY      0x1
 #define ATH9K_HTC_TX_RTSCTS       0x2
-#define ATH9K_HTC_TX_USE_MIN_RATE 0x100
 
 struct tx_frame_hdr {
         u8 data_type;
         u8 node_idx;
         u8 vif_idx;
         u8 tidno;
-        u32 flags; /* ATH9K_HTC_TX_* */
+        __be32 flags; /* ATH9K_HTC_TX_* */
         u8 key_type;
         u8 keyix;
-        u8 reserved[26];
+        u8 cookie;
+        u8 pad;
 } __packed;
 
 struct tx_mgmt_hdr {
@@ -91,78 +86,46 @@ struct tx_mgmt_hdr {
         u8 flags;
         u8 key_type;
         u8 keyix;
-        u16 reserved;
+        u8 cookie;
+        u8 pad;
 } __packed;
 
 struct tx_beacon_header {
-        u8 len_changed;
         u8 vif_index;
+        u8 len_changed;
         u16 rev;
 } __packed;
 
-struct ath9k_htc_target_hw {
-        u32 flags;
-        u32 flags_ext;
-        u32 ampdu_limit;
-        u8 ampdu_subframes;
-        u8 tx_chainmask;
-        u8 tx_chainmask_legacy;
-        u8 rtscts_ratecode;
-        u8 protmode;
-} __packed;
+#define MAX_TX_AMPDU_SUBFRAMES_9271 17
+#define MAX_TX_AMPDU_SUBFRAMES_7010 22
 
 struct ath9k_htc_cap_target {
-        u32 flags;
-        u32 flags_ext;
-        u32 ampdu_limit;
+        __be32 ampdu_limit;
         u8 ampdu_subframes;
+        u8 enable_coex;
         u8 tx_chainmask;
-        u8 tx_chainmask_legacy;
-        u8 rtscts_ratecode;
-        u8 protmode;
+        u8 pad;
 } __packed;
 
 struct ath9k_htc_target_vif {
         u8 index;
-        u8 des_bssid[ETH_ALEN];
-        __be32 opmode;
+        u8 opmode;
         u8 myaddr[ETH_ALEN];
-        u8 bssid[ETH_ALEN];
-        u32 flags;
-        u32 flags_ext;
-        u16 ps_sta;
-        __be16 rtsthreshold;
         u8 ath_cap;
-        u8 node;
-        s8 mcast_rate;
+        __be16 rtsthreshold;
+        u8 pad;
 } __packed;
 
-#define ATH_HTC_STA_AUTH  0x0001
-#define ATH_HTC_STA_QOS   0x0002
-#define ATH_HTC_STA_ERP   0x0004
-#define ATH_HTC_STA_HT    0x0008
-
-/* FIXME: UAPSD variables */
 struct ath9k_htc_target_sta {
-        u16 associd;
-        u16 txpower;
-        u32 ucastkey;
         u8 macaddr[ETH_ALEN];
         u8 bssid[ETH_ALEN];
         u8 sta_index;
         u8 vif_index;
-        u8 vif_sta;
-        __be16 flags; /* ATH_HTC_STA_* */
-        u16 htcap;
-        u8 valid;
-        u16 capinfo;
-        struct ath9k_htc_target_hw *hw;
-        struct ath9k_htc_target_vif *vif;
-        u16 txseqmgmt;
         u8 is_vif_sta;
-        u16 maxampdu;
-        u16 iv16;
-        u32 iv32;
+        __be16 flags;
+        __be16 htcap;
+        __be16 maxampdu;
+        u8 pad;
 } __packed;
 
 struct ath9k_htc_target_aggr {
@@ -196,16 +159,86 @@ struct ath9k_htc_target_rate {
         struct ath9k_htc_rate rates;
 };
 
-struct ath9k_htc_target_stats {
-        __be32 tx_shortretry;
-        __be32 tx_longretry;
-        __be32 tx_xretries;
-        __be32 ht_txunaggr_xretry;
-        __be32 ht_tx_xretries;
+struct ath9k_htc_target_rate_mask {
+        u8 vif_index;
+        u8 band;
+        __be32 mask;
+        u16 pad;
 } __packed;
 
+struct ath9k_htc_target_int_stats {
+        __be32 rx;
+        __be32 rxorn;
+        __be32 rxeol;
+        __be32 txurn;
+        __be32 txto;
+        __be32 cst;
+} __packed;
+
+struct ath9k_htc_target_tx_stats {
+        __be32 xretries;
+        __be32 fifoerr;
+        __be32 filtered;
+        __be32 timer_exp;
+        __be32 shortretries;
+        __be32 longretries;
+        __be32 qnull;
+        __be32 encap_fail;
+        __be32 nobuf;
+} __packed;
+
+struct ath9k_htc_target_rx_stats {
+        __be32 nobuf;
+        __be32 host_send;
+        __be32 host_done;
+} __packed;
+
+#define ATH9K_HTC_MAX_VIF 2
+#define ATH9K_HTC_MAX_BCN_VIF 2
+
+#define INC_VIF(_priv, _type) do {              \
+                switch (_type) {                \
+                case NL80211_IFTYPE_STATION:    \
+                        _priv->num_sta_vif++;   \
+                        break;                  \
+                case NL80211_IFTYPE_ADHOC:      \
+                        _priv->num_ibss_vif++;  \
+                        break;                  \
+                case NL80211_IFTYPE_AP:         \
+                        _priv->num_ap_vif++;    \
+                        break;                  \
+                default:                        \
+                        break;                  \
+                }                               \
+        } while (0)
+
+#define DEC_VIF(_priv, _type) do {              \
+                switch (_type) {                \
+                case NL80211_IFTYPE_STATION:    \
+                        _priv->num_sta_vif--;   \
+                        break;                  \
+                case NL80211_IFTYPE_ADHOC:      \
+                        _priv->num_ibss_vif--;  \
+                        break;                  \
+                case NL80211_IFTYPE_AP:         \
+                        _priv->num_ap_vif--;    \
+                        break;                  \
+                default:                        \
+                        break;                  \
+                }                               \
+        } while (0)
+
 struct ath9k_htc_vif {
         u8 index;
+        u16 seq_no;
+        bool beacon_configured;
+        int bslot;
+        __le64 tsfadjust;
+};
+
+struct ath9k_vif_iter_data {
+        const u8 *hw_macaddr;
+        u8 mask[ETH_ALEN];
 };
 
 #define ATH9K_HTC_MAX_STA 8
@@ -239,23 +272,65 @@ struct ath9k_htc_rx {
         spinlock_t rxbuflock;
 };
 
+#define ATH9K_HTC_TX_CLEANUP_INTERVAL 50 /* ms */
+#define ATH9K_HTC_TX_TIMEOUT_INTERVAL 3000 /* ms */
+#define ATH9K_HTC_TX_RESERVE 10
+#define ATH9K_HTC_TX_TIMEOUT_COUNT 40
+#define ATH9K_HTC_TX_THRESHOLD (MAX_TX_BUF_NUM - ATH9K_HTC_TX_RESERVE)
+
+#define ATH9K_HTC_OP_TX_QUEUES_STOP BIT(0)
+#define ATH9K_HTC_OP_TX_DRAIN       BIT(1)
+
+struct ath9k_htc_tx {
+        u8 flags;
+        int queued_cnt;
+        struct sk_buff_head mgmt_ep_queue;
+        struct sk_buff_head cab_ep_queue;
+        struct sk_buff_head data_be_queue;
+        struct sk_buff_head data_bk_queue;
+        struct sk_buff_head data_vi_queue;
+        struct sk_buff_head data_vo_queue;
+        struct sk_buff_head tx_failed;
+        DECLARE_BITMAP(tx_slot, MAX_TX_BUF_NUM);
+        struct timer_list cleanup_timer;
+        spinlock_t tx_lock;
+};
+
 struct ath9k_htc_tx_ctl {
         u8 type; /* ATH9K_HTC_* */
+        u8 epid;
+        u8 txok;
+        u8 sta_idx;
+        unsigned long timestamp;
 };
 
+static inline struct ath9k_htc_tx_ctl *HTC_SKB_CB(struct sk_buff *skb)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+
+        BUILD_BUG_ON(sizeof(struct ath9k_htc_tx_ctl) >
+                     IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
+        return (struct ath9k_htc_tx_ctl *) &tx_info->driver_data;
+}
+
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
 
 #define TX_STAT_INC(c) (hif_dev->htc_handle->drv_priv->debug.tx_stats.c++)
 #define RX_STAT_INC(c) (hif_dev->htc_handle->drv_priv->debug.rx_stats.c++)
+#define CAB_STAT_INC   priv->debug.tx_stats.cab_queued++
 
 #define TX_QSTAT_INC(q) (priv->debug.tx_stats.queue_stats[q]++)
 
+void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv,
+                           struct ath_htc_rx_status *rxs);
+
 struct ath_tx_stats {
         u32 buf_queued;
         u32 buf_completed;
         u32 skb_queued;
-        u32 skb_completed;
-        u32 skb_dropped;
+        u32 skb_success;
+        u32 skb_failed;
+        u32 cab_queued;
         u32 queue_stats[WME_NUM_AC];
 };
 
@@ -263,70 +338,79 @@ struct ath_rx_stats {
         u32 skb_allocated;
         u32 skb_completed;
         u32 skb_dropped;
+        u32 err_crc;
+        u32 err_decrypt_crc;
+        u32 err_mic;
+        u32 err_pre_delim;
+        u32 err_post_delim;
+        u32 err_decrypt_busy;
+        u32 err_phy;
+        u32 err_phy_stats[ATH9K_PHYERR_MAX];
 };
 
 struct ath9k_debug {
         struct dentry *debugfs_phy;
-        struct dentry *debugfs_tgt_stats;
-        struct dentry *debugfs_xmit;
-        struct dentry *debugfs_recv;
         struct ath_tx_stats tx_stats;
         struct ath_rx_stats rx_stats;
-        u32 txrate;
 };
 
 #else
 
 #define TX_STAT_INC(c) do { } while (0)
 #define RX_STAT_INC(c) do { } while (0)
+#define CAB_STAT_INC   do { } while (0)
 
 #define TX_QSTAT_INC(c) do { } while (0)
 
+static inline void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv,
+                                         struct ath_htc_rx_status *rxs)
+{
+}
+
 #endif /* CONFIG_ATH9K_HTC_DEBUGFS */
 
 #define ATH_LED_PIN_DEF             1
-#define ATH_LED_PIN_9287            8
+#define ATH_LED_PIN_9287            10
 #define ATH_LED_PIN_9271            15
 #define ATH_LED_PIN_7010            12
-#define ATH_LED_ON_DURATION_IDLE    350 /* in msecs */
-#define ATH_LED_OFF_DURATION_IDLE   250 /* in msecs */
-
-enum ath_led_type {
-        ATH_LED_RADIO,
-        ATH_LED_ASSOC,
-        ATH_LED_TX,
-        ATH_LED_RX
-};
 
-struct ath_led {
-        struct ath9k_htc_priv *priv;
-        struct led_classdev led_cdev;
-        enum ath_led_type led_type;
-        struct delayed_work brightness_work;
-        char name[32];
-        bool registered;
-        int brightness;
-};
+#define BSTUCK_THRESHOLD 10
+
+/*
+ * Adjust these when the max. no of beaconing interfaces is
+ * increased.
+ */
+#define DEFAULT_SWBA_RESPONSE 40 /* in TUs */
+#define MIN_SWBA_RESPONSE     10 /* in TUs */
 
 struct htc_beacon_config {
+        struct ieee80211_vif *bslot[ATH9K_HTC_MAX_BCN_VIF];
         u16 beacon_interval;
-        u16 listen_interval;
         u16 dtim_period;
         u16 bmiss_timeout;
-        u8 dtim_count;
+        u32 bmiss_cnt;
+};
+
+struct ath_btcoex {
+        u32 bt_priority_cnt;
+        unsigned long bt_priority_time;
+        int bt_stomp_type; /* Types of BT stomping */
+        u32 btcoex_no_stomp;
+        u32 btcoex_period;
+        u32 btscan_no_stomp;
 };
 
-#define OP_INVALID        BIT(0)
-#define OP_SCANNING       BIT(1)
-#define OP_FULL_RESET     BIT(2)
-#define OP_LED_ASSOCIATED BIT(3)
-#define OP_LED_ON         BIT(4)
-#define OP_PREAMBLE_SHORT BIT(5)
-#define OP_PROTECT_ENABLE BIT(6)
-#define OP_ASSOCIATED     BIT(7)
-#define OP_ENABLE_BEACON  BIT(8)
-#define OP_LED_DEINIT     BIT(9)
-#define OP_UNPLUGGED      BIT(10)
+void ath_htc_init_btcoex_work(struct ath9k_htc_priv *priv);
+void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv);
+void ath_htc_cancel_btcoex_work(struct ath9k_htc_priv *priv);
+
+#define OP_INVALID                 BIT(0)
+#define OP_SCANNING                BIT(1)
+#define OP_ENABLE_BEACON           BIT(2)
+#define OP_BT_PRIORITY_DETECTED    BIT(3)
+#define OP_BT_SCAN                 BIT(4)
+#define OP_ANI_RUNNING             BIT(5)
+#define OP_TSF_RESET               BIT(6)
 
 struct ath9k_htc_priv {
         struct device *dev;
@@ -335,6 +419,9 @@ struct ath9k_htc_priv {
         struct htc_target *htc;
         struct wmi *wmi;
 
+        u16 fw_version_major;
+        u16 fw_version_minor;
+
         enum htc_endpoint_id wmi_cmd_ep;
         enum htc_endpoint_id beacon_ep;
         enum htc_endpoint_id cab_ep;
@@ -345,52 +432,60 @@ struct ath9k_htc_priv {
         enum htc_endpoint_id data_vi_ep;
         enum htc_endpoint_id data_vo_ep;
 
+        u8 vif_slot;
+        u8 mon_vif_idx;
+        u8 sta_slot;
+        u8 vif_sta_pos[ATH9K_HTC_MAX_VIF];
+        u8 num_ibss_vif;
+        u8 num_sta_vif;
+        u8 num_sta_assoc_vif;
+        u8 num_ap_vif;
+
         u16 op_flags;
         u16 curtxpow;
         u16 txpowlimit;
         u16 nvifs;
         u16 nstations;
-        u16 seq_no;
-        u32 bmiss_cnt;
+        bool rearm_ani;
+        bool reconfig_beacon;
+        unsigned int rxfilter;
 
-        struct ath9k_hw_cal_data caldata[38];
+        struct ath9k_hw_cal_data caldata;
+        struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 
         spinlock_t beacon_lock;
+        struct htc_beacon_config cur_beacon_conf;
 
-        bool tx_queues_stop;
-        spinlock_t tx_lock;
+        struct ath9k_htc_rx rx;
+        struct ath9k_htc_tx tx;
 
-        struct ieee80211_vif *vif;
-        struct htc_beacon_config cur_beacon_conf;
-        unsigned int rxfilter;
-        struct tasklet_struct wmi_tasklet;
+        struct tasklet_struct swba_tasklet;
         struct tasklet_struct rx_tasklet;
-        struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
-        struct ath9k_htc_rx rx;
-        struct tasklet_struct tx_tasklet;
-        struct sk_buff_head tx_queue;
-        struct delayed_work ath9k_ani_work;
+        struct delayed_work ani_work;
+        struct tasklet_struct tx_failed_tasklet;
         struct work_struct ps_work;
+        struct work_struct fatal_work;
 
         struct mutex htc_pm_lock;
         unsigned long ps_usecount;
         bool ps_enabled;
         bool ps_idle;
 
-        struct ath_led radio_led;
-        struct ath_led assoc_led;
-        struct ath_led tx_led;
-        struct ath_led rx_led;
-        struct delayed_work ath9k_led_blink_work;
-        int led_on_duration;
-        int led_off_duration;
-        int led_on_cnt;
-        int led_off_cnt;
+#ifdef CONFIG_MAC80211_LEDS
+        enum led_brightness brightness;
+        bool led_registered;
+        char led_name[32];
+        struct led_classdev led_cdev;
+        struct work_struct led_work;
+#endif
 
         int beaconq;
         int cabq;
         int hwq_map[WME_NUM_AC];
 
+        struct ath_btcoex btcoex;
+        struct delayed_work coex_period_work;
+        struct delayed_work duty_cycle_work;
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
         struct ath9k_debug debug;
 #endif
@@ -402,10 +497,20 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
         common->bus_ops->read_cachesize(common, csz);
 }
 
+void ath9k_htc_reset(struct ath9k_htc_priv *priv);
+
+void ath9k_htc_assign_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif);
+void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif);
+void ath9k_htc_set_tsfadjust(struct ath9k_htc_priv *priv,
+                             struct ieee80211_vif *vif);
 void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv);
 void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
                              struct ieee80211_vif *vif);
-void ath9k_htc_swba(struct ath9k_htc_priv *priv, u8 beacon_pending);
+void ath9k_htc_beacon_reconfig(struct ath9k_htc_priv *priv);
+void ath9k_htc_swba(struct ath9k_htc_priv *priv,
+                    struct wmi_event_swba *swba);
 
 void ath9k_htc_rxep(void *priv, struct sk_buff *skb,
                     enum htc_endpoint_id ep_id);
@@ -414,19 +519,32 @@ void ath9k_htc_txep(void *priv, struct sk_buff *skb, enum htc_endpoint_id ep_id,
 void ath9k_htc_beaconep(void *drv_priv, struct sk_buff *skb,
                         enum htc_endpoint_id ep_id, bool txok);
 
+int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv,
+                                u8 enable_coex);
 void ath9k_htc_station_work(struct work_struct *work);
 void ath9k_htc_aggr_work(struct work_struct *work);
-void ath9k_ani_work(struct work_struct *work);;
+void ath9k_htc_ani_work(struct work_struct *work);
+void ath9k_htc_start_ani(struct ath9k_htc_priv *priv);
+void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv);
 
 int ath9k_tx_init(struct ath9k_htc_priv *priv);
-void ath9k_tx_tasklet(unsigned long data);
-int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, struct sk_buff *skb);
+int ath9k_htc_tx_start(struct ath9k_htc_priv *priv,
+                       struct sk_buff *skb, u8 slot, bool is_cab);
 void ath9k_tx_cleanup(struct ath9k_htc_priv *priv);
 bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype);
 int ath9k_htc_cabq_setup(struct ath9k_htc_priv *priv);
 int get_hw_qnum(u16 queue, int *hwq_map);
 int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
                        struct ath9k_tx_queue_info *qinfo);
+void ath9k_htc_check_stop_queues(struct ath9k_htc_priv *priv);
+void ath9k_htc_check_wake_queues(struct ath9k_htc_priv *priv);
+int ath9k_htc_tx_get_slot(struct ath9k_htc_priv *priv);
+void ath9k_htc_tx_clear_slot(struct ath9k_htc_priv *priv, int slot);
+void ath9k_htc_tx_drain(struct ath9k_htc_priv *priv);
+void ath9k_htc_txstatus(struct ath9k_htc_priv *priv, void *wmi_event);
+void ath9k_htc_tx_failed(struct ath9k_htc_priv *priv);
+void ath9k_tx_failed_tasklet(unsigned long data);
+void ath9k_htc_tx_cleanup_timer(unsigned long data);
 
 int ath9k_rx_init(struct ath9k_htc_priv *priv);
 void ath9k_rx_cleanup(struct ath9k_htc_priv *priv);
@@ -437,27 +555,43 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv);
 void ath9k_htc_ps_wakeup(struct ath9k_htc_priv *priv);
 void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv);
 void ath9k_ps_work(struct work_struct *work);
+bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
+                        enum ath9k_power_mode mode);
 
 void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv);
+void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw);
+void ath9k_htc_radio_enable(struct ieee80211_hw *hw);
+void ath9k_htc_radio_disable(struct ieee80211_hw *hw);
+
+#ifdef CONFIG_MAC80211_LEDS
 void ath9k_init_leds(struct ath9k_htc_priv *priv);
 void ath9k_deinit_leds(struct ath9k_htc_priv *priv);
+void ath9k_led_work(struct work_struct *work);
+#else
+static inline void ath9k_init_leds(struct ath9k_htc_priv *priv)
+{
+}
+
+static inline void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
+{
+}
+
+static inline void ath9k_led_work(struct work_struct *work)
+{
+}
+#endif
 
 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
-                           u16 devid);
+                           u16 devid, char *product, u32 drv_info);
 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug);
 #ifdef CONFIG_PM
+void ath9k_htc_suspend(struct htc_target *htc_handle);
 int ath9k_htc_resume(struct htc_target *htc_handle);
 #endif
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
-int ath9k_htc_debug_create_root(void);
-void ath9k_htc_debug_remove_root(void);
 int ath9k_htc_init_debug(struct ath_hw *ah);
-void ath9k_htc_exit_debug(struct ath_hw *ah);
 #else
-static inline int ath9k_htc_debug_create_root(void) { return 0; };
-static inline void ath9k_htc_debug_remove_root(void) {};
 static inline int ath9k_htc_init_debug(struct ath_hw *ah) { return 0; };
-static inline void ath9k_htc_exit_debug(struct ath_hw *ah) {};
 #endif /* CONFIG_ATH9K_HTC_DEBUGFS */
 
 #endif /* HTC_H */
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index bd1506e69105..aa6a73118706 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,50 @@
 
 #define FUDGE 2
 
+void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
+{
+        struct ath_hw *ah = priv->ah;
+        struct ath9k_tx_queue_info qi, qi_be;
+
+        memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
+        memset(&qi_be, 0, sizeof(struct ath9k_tx_queue_info));
+
+        ath9k_hw_get_txq_props(ah, priv->beaconq, &qi);
+
+        if (priv->ah->opmode == NL80211_IFTYPE_AP) {
+                qi.tqi_aifs = 1;
+                qi.tqi_cwmin = 0;
+                qi.tqi_cwmax = 0;
+        } else if (priv->ah->opmode == NL80211_IFTYPE_ADHOC) {
+                int qnum = priv->hwq_map[WME_AC_BE];
+
+                ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+
+                qi.tqi_aifs = qi_be.tqi_aifs;
+
+                /*
+                 * For WIFI Beacon Distribution
+                 * Long slot time  : 2x cwmin
+                 * Short slot time : 4x cwmin
+                 */
+                if (ah->slottime == ATH9K_SLOT_TIME_20)
+                        qi.tqi_cwmin = 2*qi_be.tqi_cwmin;
+                else
+                        qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
+
+                qi.tqi_cwmax = qi_be.tqi_cwmax;
+
+        }
+
+        if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) {
+                ath_err(ath9k_hw_common(ah),
+                        "Unable to update beacon queue %u!\n", priv->beaconq);
+        } else {
+                ath9k_hw_resettxqueue(ah, priv->beaconq);
+        }
+}
+
+
 static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
                                         struct htc_beacon_config *bss_conf)
 {
@@ -30,7 +74,7 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         __be32 htc_imask = 0;
         u64 tsf;
         int num_beacons, offset, dtim_dec_count, cfp_dec_count;
-        int ret;
+        int ret __attribute__ ((unused));
         u8 cmd_rsp;
 
         memset(&bs, 0, sizeof(bs));
@@ -123,11 +167,12 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         /* TSF out of range threshold fixed at 1 second */
         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
 
-        ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
-        ath_print(common, ATH_DBG_BEACON,
-                  "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
-                  bs.bs_bmissthreshold, bs.bs_sleepduration,
-                  bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
+        ath_dbg(common, ATH_DBG_CONFIG, "intval: %u tsf: %llu tsftu: %u\n",
+                intval, tsf, tsftu);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+                bs.bs_bmissthreshold, bs.bs_sleepduration,
+                bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
 
         /* Set the computed STA beacon timers */
 
@@ -138,29 +183,105 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
 }
 
+static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
+                                       struct htc_beacon_config *bss_conf)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        enum ath9k_int imask = 0;
+        u32 nexttbtt, intval, tsftu;
+        __be32 htc_imask = 0;
+        int ret __attribute__ ((unused));
+        u8 cmd_rsp;
+        u64 tsf;
+
+        intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD;
+        intval /= ATH9K_HTC_MAX_BCN_VIF;
+        nexttbtt = intval;
+
+        /*
+         * To reduce beacon misses under heavy TX load,
+         * set the beacon response time to a larger value.
+         */
+        if (intval > DEFAULT_SWBA_RESPONSE)
+                priv->ah->config.sw_beacon_response_time = DEFAULT_SWBA_RESPONSE;
+        else
+                priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
+
+        if (priv->op_flags & OP_TSF_RESET) {
+                ath9k_hw_reset_tsf(priv->ah);
+                priv->op_flags &= ~OP_TSF_RESET;
+        } else {
+                /*
+                 * Pull nexttbtt forward to reflect the current TSF.
+                 */
+                tsf = ath9k_hw_gettsf64(priv->ah);
+                tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
+                do {
+                        nexttbtt += intval;
+                } while (nexttbtt < tsftu);
+        }
+
+        if (priv->op_flags & OP_ENABLE_BEACON)
+                imask |= ATH9K_INT_SWBA;
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "AP Beacon config, intval: %d, nexttbtt: %u, resp_time: %d "
+                "imask: 0x%x\n",
+                bss_conf->beacon_interval, nexttbtt,
+                priv->ah->config.sw_beacon_response_time, imask);
+
+        ath9k_htc_beaconq_config(priv);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+        ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
+        priv->cur_beacon_conf.bmiss_cnt = 0;
+        htc_imask = cpu_to_be32(imask);
+        WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
+}
+
 static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
                                           struct htc_beacon_config *bss_conf)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         enum ath9k_int imask = 0;
-        u32 nexttbtt, intval;
+        u32 nexttbtt, intval, tsftu;
         __be32 htc_imask = 0;
-        int ret;
+        int ret __attribute__ ((unused));
         u8 cmd_rsp;
+        u64 tsf;
 
         intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD;
         nexttbtt = intval;
-        intval |= ATH9K_BEACON_ENA;
+
+        /*
+         * Pull nexttbtt forward to reflect the current TSF.
+         */
+        tsf = ath9k_hw_gettsf64(priv->ah);
+        tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
+        do {
+                nexttbtt += intval;
+        } while (nexttbtt < tsftu);
+
+        /*
+         * Only one IBSS interfce is allowed.
+         */
+        if (intval > DEFAULT_SWBA_RESPONSE)
+                priv->ah->config.sw_beacon_response_time = DEFAULT_SWBA_RESPONSE;
+        else
+                priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
+
         if (priv->op_flags & OP_ENABLE_BEACON)
                 imask |= ATH9K_INT_SWBA;
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "IBSS Beacon config, intval: %d, imask: 0x%x\n",
-                  bss_conf->beacon_interval, imask);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "IBSS Beacon config, intval: %d, nexttbtt: %u, "
+                "resp_time: %d, imask: 0x%x\n",
+                bss_conf->beacon_interval, nexttbtt,
+                priv->ah->config.sw_beacon_response_time, imask);
 
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
-        ath9k_hw_beaconinit(priv->ah, nexttbtt, intval);
-        priv->bmiss_cnt = 0;
+        ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
+        priv->cur_beacon_conf.bmiss_cnt = 0;
         htc_imask = cpu_to_be32(imask);
         WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
 }
@@ -171,79 +292,318 @@ void ath9k_htc_beaconep(void *drv_priv, struct sk_buff *skb,
         dev_kfree_skb_any(skb);
 }
 
-void ath9k_htc_swba(struct ath9k_htc_priv *priv, u8 beacon_pending)
+static void ath9k_htc_send_buffered(struct ath9k_htc_priv *priv,
+                                    int slot)
 {
-        struct ath9k_htc_vif *avp = (void *)priv->vif->drv_priv;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ieee80211_vif *vif;
+        struct sk_buff *skb;
+        struct ieee80211_hdr *hdr;
+        int padpos, padsize, ret, tx_slot;
+
+        spin_lock_bh(&priv->beacon_lock);
+
+        vif = priv->cur_beacon_conf.bslot[slot];
+
+        skb = ieee80211_get_buffered_bc(priv->hw, vif);
+
+        while(skb) {
+                hdr = (struct ieee80211_hdr *) skb->data;
+
+                padpos = ath9k_cmn_padpos(hdr->frame_control);
+                padsize = padpos & 3;
+                if (padsize && skb->len > padpos) {
+                        if (skb_headroom(skb) < padsize) {
+                                dev_kfree_skb_any(skb);
+                                goto next;
+                        }
+                        skb_push(skb, padsize);
+                        memmove(skb->data, skb->data + padsize, padpos);
+                }
+
+                tx_slot = ath9k_htc_tx_get_slot(priv);
+                if (tx_slot < 0) {
+                        ath_dbg(common, ATH_DBG_XMIT, "No free CAB slot\n");
+                        dev_kfree_skb_any(skb);
+                        goto next;
+                }
+
+                ret = ath9k_htc_tx_start(priv, skb, tx_slot, true);
+                if (ret != 0) {
+                        ath9k_htc_tx_clear_slot(priv, tx_slot);
+                        dev_kfree_skb_any(skb);
+
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Failed to send CAB frame\n");
+                } else {
+                        spin_lock_bh(&priv->tx.tx_lock);
+                        priv->tx.queued_cnt++;
+                        spin_unlock_bh(&priv->tx.tx_lock);
+                }
+        next:
+                skb = ieee80211_get_buffered_bc(priv->hw, vif);
+        }
+
+        spin_unlock_bh(&priv->beacon_lock);
+}
+
+static void ath9k_htc_send_beacon(struct ath9k_htc_priv *priv,
+                                  int slot)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ieee80211_vif *vif;
+        struct ath9k_htc_vif *avp;
         struct tx_beacon_header beacon_hdr;
-        struct ath9k_htc_tx_ctl tx_ctl;
+        struct ath9k_htc_tx_ctl *tx_ctl;
         struct ieee80211_tx_info *info;
+        struct ieee80211_mgmt *mgmt;
         struct sk_buff *beacon;
         u8 *tx_fhdr;
+        int ret;
 
         memset(&beacon_hdr, 0, sizeof(struct tx_beacon_header));
-        memset(&tx_ctl, 0, sizeof(struct ath9k_htc_tx_ctl));
-
-        /* FIXME: Handle BMISS */
-        if (beacon_pending != 0) {
-                priv->bmiss_cnt++;
-                return;
-        }
 
         spin_lock_bh(&priv->beacon_lock);
 
+        vif = priv->cur_beacon_conf.bslot[slot];
+        avp = (struct ath9k_htc_vif *)vif->drv_priv;
+
         if (unlikely(priv->op_flags & OP_SCANNING)) {
                 spin_unlock_bh(&priv->beacon_lock);
                 return;
         }
 
         /* Get a new beacon */
-        beacon = ieee80211_beacon_get(priv->hw, priv->vif);
+        beacon = ieee80211_beacon_get(priv->hw, vif);
         if (!beacon) {
                 spin_unlock_bh(&priv->beacon_lock);
                 return;
         }
 
+        /*
+         * Update the TSF adjust value here, the HW will
+         * add this value for every beacon.
+         */
+        mgmt = (struct ieee80211_mgmt *)beacon->data;
+        mgmt->u.beacon.timestamp = avp->tsfadjust;
+
         info = IEEE80211_SKB_CB(beacon);
         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
                 struct ieee80211_hdr *hdr =
                         (struct ieee80211_hdr *) beacon->data;
-                priv->seq_no += 0x10;
+                avp->seq_no += 0x10;
                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
-                hdr->seq_ctrl |= cpu_to_le16(priv->seq_no);
+                hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
         }
 
-        tx_ctl.type = ATH9K_HTC_NORMAL;
+        tx_ctl = HTC_SKB_CB(beacon);
+        memset(tx_ctl, 0, sizeof(*tx_ctl));
+
+        tx_ctl->type = ATH9K_HTC_BEACON;
+        tx_ctl->epid = priv->beacon_ep;
+
         beacon_hdr.vif_index = avp->index;
         tx_fhdr = skb_push(beacon, sizeof(beacon_hdr));
         memcpy(tx_fhdr, (u8 *) &beacon_hdr, sizeof(beacon_hdr));
 
-        htc_send(priv->htc, beacon, priv->beacon_ep, &tx_ctl);
+        ret = htc_send(priv->htc, beacon);
+        if (ret != 0) {
+                if (ret == -ENOMEM) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "Failed to send beacon, no free TX buffer\n");
+                }
+                dev_kfree_skb_any(beacon);
+        }
 
         spin_unlock_bh(&priv->beacon_lock);
 }
 
-/* Currently, only for IBSS */
-void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
+static int ath9k_htc_choose_bslot(struct ath9k_htc_priv *priv,
+                                  struct wmi_event_swba *swba)
 {
-        struct ath_hw *ah = priv->ah;
-        struct ath9k_tx_queue_info qi, qi_be;
-        int qnum = priv->hwq_map[WME_AC_BE];
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        u64 tsf;
+        u32 tsftu;
+        u16 intval;
+        int slot;
 
-        memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
-        memset(&qi_be, 0, sizeof(struct ath9k_tx_queue_info));
+        intval = priv->cur_beacon_conf.beacon_interval & ATH9K_BEACON_PERIOD;
 
-        ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+        tsf = be64_to_cpu(swba->tsf);
+        tsftu = TSF_TO_TU(tsf >> 32, tsf);
+        slot = ((tsftu % intval) * ATH9K_HTC_MAX_BCN_VIF) / intval;
+        slot = ATH9K_HTC_MAX_BCN_VIF - slot - 1;
 
-        qi.tqi_aifs = qi_be.tqi_aifs;
-        qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
-        qi.tqi_cwmax = qi_be.tqi_cwmax;
+        ath_dbg(common, ATH_DBG_BEACON,
+                "Choose slot: %d, tsf: %llu, tsftu: %u, intval: %u\n",
+                slot, tsf, tsftu, intval);
 
-        if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unable to update beacon queue %u!\n", qnum);
-        } else {
-                ath9k_hw_resettxqueue(ah, priv->beaconq);
+        return slot;
+}
+
+void ath9k_htc_swba(struct ath9k_htc_priv *priv,
+                    struct wmi_event_swba *swba)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        int slot;
+
+        if (swba->beacon_pending != 0) {
+                priv->cur_beacon_conf.bmiss_cnt++;
+                if (priv->cur_beacon_conf.bmiss_cnt > BSTUCK_THRESHOLD) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "Beacon stuck, HW reset\n");
+                        ieee80211_queue_work(priv->hw,
+                                             &priv->fatal_work);
+                }
+                return;
+        }
+
+        if (priv->cur_beacon_conf.bmiss_cnt) {
+                ath_dbg(common, ATH_DBG_BSTUCK,
+                        "Resuming beacon xmit after %u misses\n",
+                        priv->cur_beacon_conf.bmiss_cnt);
+                priv->cur_beacon_conf.bmiss_cnt = 0;
+        }
+
+        slot = ath9k_htc_choose_bslot(priv, swba);
+        spin_lock_bh(&priv->beacon_lock);
+        if (priv->cur_beacon_conf.bslot[slot] == NULL) {
+                spin_unlock_bh(&priv->beacon_lock);
+                return;
+        }
+        spin_unlock_bh(&priv->beacon_lock);
+
+        ath9k_htc_send_buffered(priv, slot);
+        ath9k_htc_send_beacon(priv, slot);
+}
+
+void ath9k_htc_assign_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *)vif->drv_priv;
+        int i = 0;
+
+        spin_lock_bh(&priv->beacon_lock);
+        for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++) {
+                if (priv->cur_beacon_conf.bslot[i] == NULL) {
+                        avp->bslot = i;
+                        break;
+                }
+        }
+
+        priv->cur_beacon_conf.bslot[avp->bslot] = vif;
+        spin_unlock_bh(&priv->beacon_lock);
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Added interface at beacon slot: %d\n", avp->bslot);
+}
+
+void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *)vif->drv_priv;
+
+        spin_lock_bh(&priv->beacon_lock);
+        priv->cur_beacon_conf.bslot[avp->bslot] = NULL;
+        spin_unlock_bh(&priv->beacon_lock);
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Removed interface at beacon slot: %d\n", avp->bslot);
+}
+
+/*
+ * Calculate the TSF adjustment value for all slots
+ * other than zero.
+ */
+void ath9k_htc_set_tsfadjust(struct ath9k_htc_priv *priv,
+                             struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *)vif->drv_priv;
+        struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
+        u64 tsfadjust;
+
+        if (avp->bslot == 0)
+                return;
+
+        /*
+         * The beacon interval cannot be different for multi-AP mode,
+         * and we reach here only for VIF slots greater than zero,
+         * so beacon_interval is guaranteed to be set in cur_conf.
+         */
+        tsfadjust = cur_conf->beacon_interval * avp->bslot / ATH9K_HTC_MAX_BCN_VIF;
+        avp->tsfadjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "tsfadjust is: %llu for bslot: %d\n",
+                (unsigned long long)tsfadjust, avp->bslot);
+}
+
+static void ath9k_htc_beacon_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        bool *beacon_configured = (bool *)data;
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
+
+        if (vif->type == NL80211_IFTYPE_STATION &&
+            avp->beacon_configured)
+                *beacon_configured = true;
+}
+
+static bool ath9k_htc_check_beacon_config(struct ath9k_htc_priv *priv,
+                                          struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        bool beacon_configured;
+
+        /*
+         * Changing the beacon interval when multiple AP interfaces
+         * are configured will affect beacon transmission of all
+         * of them.
+         */
+        if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
+            (priv->num_ap_vif > 1) &&
+            (vif->type == NL80211_IFTYPE_AP) &&
+            (cur_conf->beacon_interval != bss_conf->beacon_int)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Changing beacon interval of multiple AP interfaces !\n");
+                return false;
         }
+
+        /*
+         * If the HW is operating in AP mode, any new station interfaces that
+         * are added cannot change the beacon parameters.
+         */
+        if (priv->num_ap_vif &&
+            (vif->type != NL80211_IFTYPE_AP)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "HW in AP mode, cannot set STA beacon parameters\n");
+                return false;
+        }
+
+        /*
+         * The beacon parameters are configured only for the first
+         * station interface.
+         */
+        if ((priv->ah->opmode == NL80211_IFTYPE_STATION) &&
+            (priv->num_sta_vif > 1) &&
+            (vif->type == NL80211_IFTYPE_STATION)) {
+                beacon_configured = false;
+                ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                           ath9k_htc_beacon_iter,
+                                                           &beacon_configured);
+
+                if (beacon_configured) {
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Beacon already configured for a station interface\n");
+                        return false;
+                }
+        }
+
+        return true;
 }
 
 void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
@@ -252,27 +612,55 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
         struct ath_common *common = ath9k_hw_common(priv->ah);
         struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
         struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
+
+        if (!ath9k_htc_check_beacon_config(priv, vif))
+                return;
 
         cur_conf->beacon_interval = bss_conf->beacon_int;
         if (cur_conf->beacon_interval == 0)
                 cur_conf->beacon_interval = 100;
 
         cur_conf->dtim_period = bss_conf->dtim_period;
-        cur_conf->listen_interval = 1;
-        cur_conf->dtim_count = 1;
         cur_conf->bmiss_timeout =
                 ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
 
         switch (vif->type) {
         case NL80211_IFTYPE_STATION:
                 ath9k_htc_beacon_config_sta(priv, cur_conf);
+                avp->beacon_configured = true;
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                ath9k_htc_beacon_config_adhoc(priv, cur_conf);
+                break;
+        case NL80211_IFTYPE_AP:
+                ath9k_htc_beacon_config_ap(priv, cur_conf);
+                break;
+        default:
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
+                return;
+        }
+}
+
+void ath9k_htc_beacon_reconfig(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
+
+        switch (priv->ah->opmode) {
+        case NL80211_IFTYPE_STATION:
+                ath9k_htc_beacon_config_sta(priv, cur_conf);
                 break;
         case NL80211_IFTYPE_ADHOC:
                 ath9k_htc_beacon_config_adhoc(priv, cur_conf);
                 break;
+        case NL80211_IFTYPE_AP:
+                ath9k_htc_beacon_config_ap(priv, cur_conf);
+                break;
         default:
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unsupported beaconing mode\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
                 return;
         }
 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
new file mode 100644
index 000000000000..aa48b3abbc48
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
@@ -0,0 +1,960 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "htc.h"
+
+static int ath9k_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t read_file_tgt_int_stats(struct file *file, char __user *user_buf,
+                                       size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath9k_htc_target_int_stats cmd_rsp;
+        char buf[512];
+        unsigned int len = 0;
+        int ret = 0;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        ath9k_htc_ps_wakeup(priv);
+
+        WMI_CMD(WMI_INT_STATS_CMDID);
+        if (ret) {
+                ath9k_htc_ps_restore(priv);
+                return -EINVAL;
+        }
+
+        ath9k_htc_ps_restore(priv);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "RX",
+                        be32_to_cpu(cmd_rsp.rx));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "RXORN",
+                        be32_to_cpu(cmd_rsp.rxorn));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "RXEOL",
+                        be32_to_cpu(cmd_rsp.rxeol));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "TXURN",
+                        be32_to_cpu(cmd_rsp.txurn));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "TXTO",
+                        be32_to_cpu(cmd_rsp.txto));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "CST",
+                        be32_to_cpu(cmd_rsp.cst));
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_tgt_int_stats = {
+        .read = read_file_tgt_int_stats,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_tgt_tx_stats(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath9k_htc_target_tx_stats cmd_rsp;
+        char buf[512];
+        unsigned int len = 0;
+        int ret = 0;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        ath9k_htc_ps_wakeup(priv);
+
+        WMI_CMD(WMI_TX_STATS_CMDID);
+        if (ret) {
+                ath9k_htc_ps_restore(priv);
+                return -EINVAL;
+        }
+
+        ath9k_htc_ps_restore(priv);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Xretries",
+                        be32_to_cpu(cmd_rsp.xretries));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "FifoErr",
+                        be32_to_cpu(cmd_rsp.fifoerr));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Filtered",
+                        be32_to_cpu(cmd_rsp.filtered));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "TimerExp",
+                        be32_to_cpu(cmd_rsp.timer_exp));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "ShortRetries",
+                        be32_to_cpu(cmd_rsp.shortretries));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "LongRetries",
+                        be32_to_cpu(cmd_rsp.longretries));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "QueueNull",
+                        be32_to_cpu(cmd_rsp.qnull));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "EncapFail",
+                        be32_to_cpu(cmd_rsp.encap_fail));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "NoBuf",
+                        be32_to_cpu(cmd_rsp.nobuf));
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_tgt_tx_stats = {
+        .read = read_file_tgt_tx_stats,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_tgt_rx_stats(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath9k_htc_target_rx_stats cmd_rsp;
+        char buf[512];
+        unsigned int len = 0;
+        int ret = 0;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        ath9k_htc_ps_wakeup(priv);
+
+        WMI_CMD(WMI_RX_STATS_CMDID);
+        if (ret) {
+                ath9k_htc_ps_restore(priv);
+                return -EINVAL;
+        }
+
+        ath9k_htc_ps_restore(priv);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "NoBuf",
+                        be32_to_cpu(cmd_rsp.nobuf));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "HostSend",
+                        be32_to_cpu(cmd_rsp.host_send));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "HostDone",
+                        be32_to_cpu(cmd_rsp.host_done));
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_tgt_rx_stats = {
+        .read = read_file_tgt_rx_stats,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        char buf[512];
+        unsigned int len = 0;
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Buffers queued",
+                        priv->debug.tx_stats.buf_queued);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Buffers completed",
+                        priv->debug.tx_stats.buf_completed);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "SKBs queued",
+                        priv->debug.tx_stats.skb_queued);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "SKBs success",
+                        priv->debug.tx_stats.skb_success);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "SKBs failed",
+                        priv->debug.tx_stats.skb_failed);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "CAB queued",
+                        priv->debug.tx_stats.cab_queued);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "BE queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_BE]);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "BK queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_BK]);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "VI queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_VI]);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "VO queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_VO]);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_xmit = {
+        .read = read_file_xmit,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv,
+                           struct ath_htc_rx_status *rxs)
+{
+#define RX_PHY_ERR_INC(c) priv->debug.rx_stats.err_phy_stats[c]++
+
+        if (rxs->rs_status & ATH9K_RXERR_CRC)
+                priv->debug.rx_stats.err_crc++;
+        if (rxs->rs_status & ATH9K_RXERR_DECRYPT)
+                priv->debug.rx_stats.err_decrypt_crc++;
+        if (rxs->rs_status & ATH9K_RXERR_MIC)
+                priv->debug.rx_stats.err_mic++;
+        if (rxs->rs_status & ATH9K_RX_DELIM_CRC_PRE)
+                priv->debug.rx_stats.err_pre_delim++;
+        if (rxs->rs_status & ATH9K_RX_DELIM_CRC_POST)
+                priv->debug.rx_stats.err_post_delim++;
+        if (rxs->rs_status & ATH9K_RX_DECRYPT_BUSY)
+                priv->debug.rx_stats.err_decrypt_busy++;
+
+        if (rxs->rs_status & ATH9K_RXERR_PHY) {
+                priv->debug.rx_stats.err_phy++;
+                if (rxs->rs_phyerr < ATH9K_PHYERR_MAX)
+                        RX_PHY_ERR_INC(rxs->rs_phyerr);
+        }
+
+#undef RX_PHY_ERR_INC
+}
+
+static ssize_t read_file_recv(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+#define PHY_ERR(s, p)                                                   \
+        len += snprintf(buf + len, size - len, "%20s : %10u\n", s,      \
+                        priv->debug.rx_stats.err_phy_stats[p]);
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        char *buf;
+        unsigned int len = 0, size = 1500;
+        ssize_t retval = 0;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "SKBs allocated",
+                        priv->debug.rx_stats.skb_allocated);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "SKBs completed",
+                        priv->debug.rx_stats.skb_completed);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "SKBs Dropped",
+                        priv->debug.rx_stats.skb_dropped);
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "CRC ERR",
+                        priv->debug.rx_stats.err_crc);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "DECRYPT CRC ERR",
+                        priv->debug.rx_stats.err_decrypt_crc);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "MIC ERR",
+                        priv->debug.rx_stats.err_mic);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "PRE-DELIM CRC ERR",
+                        priv->debug.rx_stats.err_pre_delim);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "POST-DELIM CRC ERR",
+                        priv->debug.rx_stats.err_post_delim);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "DECRYPT BUSY ERR",
+                        priv->debug.rx_stats.err_decrypt_busy);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "TOTAL PHY ERR",
+                        priv->debug.rx_stats.err_phy);
+
+
+        PHY_ERR("UNDERRUN", ATH9K_PHYERR_UNDERRUN);
+        PHY_ERR("TIMING", ATH9K_PHYERR_TIMING);
+        PHY_ERR("PARITY", ATH9K_PHYERR_PARITY);
+        PHY_ERR("RATE", ATH9K_PHYERR_RATE);
+        PHY_ERR("LENGTH", ATH9K_PHYERR_LENGTH);
+        PHY_ERR("RADAR", ATH9K_PHYERR_RADAR);
+        PHY_ERR("SERVICE", ATH9K_PHYERR_SERVICE);
+        PHY_ERR("TOR", ATH9K_PHYERR_TOR);
+        PHY_ERR("OFDM-TIMING", ATH9K_PHYERR_OFDM_TIMING);
+        PHY_ERR("OFDM-SIGNAL-PARITY", ATH9K_PHYERR_OFDM_SIGNAL_PARITY);
+        PHY_ERR("OFDM-RATE", ATH9K_PHYERR_OFDM_RATE_ILLEGAL);
+        PHY_ERR("OFDM-LENGTH", ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL);
+        PHY_ERR("OFDM-POWER-DROP", ATH9K_PHYERR_OFDM_POWER_DROP);
+        PHY_ERR("OFDM-SERVICE", ATH9K_PHYERR_OFDM_SERVICE);
+        PHY_ERR("OFDM-RESTART", ATH9K_PHYERR_OFDM_RESTART);
+        PHY_ERR("FALSE-RADAR-EXT", ATH9K_PHYERR_FALSE_RADAR_EXT);
+        PHY_ERR("CCK-TIMING", ATH9K_PHYERR_CCK_TIMING);
+        PHY_ERR("CCK-HEADER-CRC", ATH9K_PHYERR_CCK_HEADER_CRC);
+        PHY_ERR("CCK-RATE", ATH9K_PHYERR_CCK_RATE_ILLEGAL);
+        PHY_ERR("CCK-SERVICE", ATH9K_PHYERR_CCK_SERVICE);
+        PHY_ERR("CCK-RESTART", ATH9K_PHYERR_CCK_RESTART);
+        PHY_ERR("CCK-LENGTH", ATH9K_PHYERR_CCK_LENGTH_ILLEGAL);
+        PHY_ERR("CCK-POWER-DROP", ATH9K_PHYERR_CCK_POWER_DROP);
+        PHY_ERR("HT-CRC", ATH9K_PHYERR_HT_CRC_ERROR);
+        PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL);
+        PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PHY_ERR
+}
+
+static const struct file_operations fops_recv = {
+        .read = read_file_recv,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_slot(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        char buf[512];
+        unsigned int len = 0;
+
+        spin_lock_bh(&priv->tx.tx_lock);
+
+        len += snprintf(buf + len, sizeof(buf) - len, "TX slot bitmap : ");
+
+        len += bitmap_scnprintf(buf + len, sizeof(buf) - len,
+                               priv->tx.tx_slot, MAX_TX_BUF_NUM);
+
+        len += snprintf(buf + len, sizeof(buf) - len, "\n");
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "Used slots     : %d\n",
+                        bitmap_weight(priv->tx.tx_slot, MAX_TX_BUF_NUM));
+
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_slot = {
+        .read = read_file_slot,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_queue(struct file *file, char __user *user_buf,
+                               size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        char buf[512];
+        unsigned int len = 0;
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Mgmt endpoint", skb_queue_len(&priv->tx.mgmt_ep_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Cab endpoint", skb_queue_len(&priv->tx.cab_ep_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data BE endpoint", skb_queue_len(&priv->tx.data_be_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data BK endpoint", skb_queue_len(&priv->tx.data_bk_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data VI endpoint", skb_queue_len(&priv->tx.data_vi_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data VO endpoint", skb_queue_len(&priv->tx.data_vo_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Failed queue", skb_queue_len(&priv->tx.tx_failed));
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Queued count", priv->tx.queued_cnt);
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+
+}
+
+static const struct file_operations fops_queue = {
+        .read = read_file_queue,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_debug(struct file *file, char __user *user_buf,
+                               size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        char buf[32];
+        unsigned int len;
+
+        len = sprintf(buf, "0x%08x\n", common->debug_mask);
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
+                                size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        unsigned long mask;
+        char buf[32];
+        ssize_t len;
+
+        len = min(count, sizeof(buf) - 1);
+        if (copy_from_user(buf, user_buf, len))
+                return -EFAULT;
+
+        buf[len] = '\0';
+        if (strict_strtoul(buf, 0, &mask))
+                return -EINVAL;
+
+        common->debug_mask = mask;
+        return count;
+}
+
+static const struct file_operations fops_debug = {
+        .read = read_file_debug,
+        .write = write_file_debug,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_base_eeprom(struct file *file, char __user *user_buf,
+                                     size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct base_eep_header *pBase = NULL;
+        unsigned int len = 0, size = 1500;
+        ssize_t retval = 0;
+        char *buf;
+
+        /*
+         * This can be done since all the 3 EEPROM families have the
+         * same base header upto a certain point, and we are interested in
+         * the data only upto that point.
+         */
+
+        if (AR_SREV_9271(priv->ah))
+                pBase = (struct base_eep_header *)
+                        &priv->ah->eeprom.map4k.baseEepHeader;
+        else if (priv->ah->hw_version.usbdev == AR9280_USB)
+                pBase = (struct base_eep_header *)
+                        &priv->ah->eeprom.def.baseEepHeader;
+        else if (priv->ah->hw_version.usbdev == AR9287_USB)
+                pBase = (struct base_eep_header *)
+                        &priv->ah->eeprom.map9287.baseEepHeader;
+
+        if (pBase == NULL) {
+                ath_err(common, "Unknown EEPROM type\n");
+                return 0;
+        }
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Major Version",
+                        pBase->version >> 12);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Minor Version",
+                        pBase->version & 0xFFF);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Checksum",
+                        pBase->checksum);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Length",
+                        pBase->length);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "RegDomain1",
+                        pBase->regDmn[0]);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "RegDomain2",
+                        pBase->regDmn[1]);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "TX Mask", pBase->txMask);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "RX Mask", pBase->rxMask);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Allow 5GHz",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Allow 2GHz",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 2GHz HT20",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_2G_HT20));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 2GHz HT40",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_2G_HT40));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 5Ghz HT20",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_5G_HT20));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 5Ghz HT40",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_5G_HT40));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Big Endian",
+                        !!(pBase->eepMisc & 0x01));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Cal Bin Major Ver",
+                        (pBase->binBuildNumber >> 24) & 0xFF);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Cal Bin Minor Ver",
+                        (pBase->binBuildNumber >> 16) & 0xFF);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Cal Bin Build",
+                        (pBase->binBuildNumber >> 8) & 0xFF);
+
+        /*
+         * UB91 specific data.
+         */
+        if (AR_SREV_9271(priv->ah)) {
+                struct base_eep_header_4k *pBase4k =
+                        &priv->ah->eeprom.map4k.baseEepHeader;
+
+                len += snprintf(buf + len, size - len,
+                                "%20s : %10d\n",
+                                "TX Gain type",
+                                pBase4k->txGainType);
+        }
+
+        /*
+         * UB95 specific data.
+         */
+        if (priv->ah->hw_version.usbdev == AR9287_USB) {
+                struct base_eep_ar9287_header *pBase9287 =
+                        &priv->ah->eeprom.map9287.baseEepHeader;
+
+                len += snprintf(buf + len, size - len,
+                                "%20s : %10ddB\n",
+                                "Power Table Offset",
+                                pBase9287->pwrTableOffset);
+
+                len += snprintf(buf + len, size - len,
+                                "%20s : %10d\n",
+                                "OpenLoop Power Ctrl",
+                                pBase9287->openLoopPwrCntl);
+        }
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %02X:%02X:%02X:%02X:%02X:%02X\n",
+                        "MacAddress",
+                        pBase->macAddr[0], pBase->macAddr[1], pBase->macAddr[2],
+                        pBase->macAddr[3], pBase->macAddr[4], pBase->macAddr[5]);
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+static const struct file_operations fops_base_eeprom = {
+        .read = read_file_base_eeprom,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_4k_modal_eeprom(struct file *file,
+                                    char __user *user_buf,
+                                    size_t count, loff_t *ppos)
+{
+#define PR_EEP(_s, _val)                                                \
+        do {                                                            \
+                len += snprintf(buf + len, size - len, "%20s : %10d\n", \
+                                _s, (_val));                            \
+        } while (0)
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct modal_eep_4k_header *pModal = &priv->ah->eeprom.map4k.modalHeader;
+        unsigned int len = 0, size = 2048;
+        ssize_t retval = 0;
+        char *buf;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        PR_EEP("Chain0 Ant. Control", pModal->antCtrlChain[0]);
+        PR_EEP("Ant. Common Control", pModal->antCtrlCommon);
+        PR_EEP("Chain0 Ant. Gain", pModal->antennaGainCh[0]);
+        PR_EEP("Switch Settle", pModal->switchSettling);
+        PR_EEP("Chain0 TxRxAtten", pModal->txRxAttenCh[0]);
+        PR_EEP("Chain0 RxTxMargin", pModal->rxTxMarginCh[0]);
+        PR_EEP("ADC Desired size", pModal->adcDesiredSize);
+        PR_EEP("PGA Desired size", pModal->pgaDesiredSize);
+        PR_EEP("Chain0 xlna Gain", pModal->xlnaGainCh[0]);
+        PR_EEP("txEndToXpaOff", pModal->txEndToXpaOff);
+        PR_EEP("txEndToRxOn", pModal->txEndToRxOn);
+        PR_EEP("txFrameToXpaOn", pModal->txFrameToXpaOn);
+        PR_EEP("CCA Threshold)", pModal->thresh62);
+        PR_EEP("Chain0 NF Threshold", pModal->noiseFloorThreshCh[0]);
+        PR_EEP("xpdGain", pModal->xpdGain);
+        PR_EEP("External PD", pModal->xpd);
+        PR_EEP("Chain0 I Coefficient", pModal->iqCalICh[0]);
+        PR_EEP("Chain0 Q Coefficient", pModal->iqCalQCh[0]);
+        PR_EEP("pdGainOverlap", pModal->pdGainOverlap);
+        PR_EEP("O/D Bias Version", pModal->version);
+        PR_EEP("CCK OutputBias", pModal->ob_0);
+        PR_EEP("BPSK OutputBias", pModal->ob_1);
+        PR_EEP("QPSK OutputBias", pModal->ob_2);
+        PR_EEP("16QAM OutputBias", pModal->ob_3);
+        PR_EEP("64QAM OutputBias", pModal->ob_4);
+        PR_EEP("CCK Driver1_Bias", pModal->db1_0);
+        PR_EEP("BPSK Driver1_Bias", pModal->db1_1);
+        PR_EEP("QPSK Driver1_Bias", pModal->db1_2);
+        PR_EEP("16QAM Driver1_Bias", pModal->db1_3);
+        PR_EEP("64QAM Driver1_Bias", pModal->db1_4);
+        PR_EEP("CCK Driver2_Bias", pModal->db2_0);
+        PR_EEP("BPSK Driver2_Bias", pModal->db2_1);
+        PR_EEP("QPSK Driver2_Bias", pModal->db2_2);
+        PR_EEP("16QAM Driver2_Bias", pModal->db2_3);
+        PR_EEP("64QAM Driver2_Bias", pModal->db2_4);
+        PR_EEP("xPA Bias Level", pModal->xpaBiasLvl);
+        PR_EEP("txFrameToDataStart", pModal->txFrameToDataStart);
+        PR_EEP("txFrameToPaOn", pModal->txFrameToPaOn);
+        PR_EEP("HT40 Power Inc.", pModal->ht40PowerIncForPdadc);
+        PR_EEP("Chain0 bswAtten", pModal->bswAtten[0]);
+        PR_EEP("Chain0 bswMargin", pModal->bswMargin[0]);
+        PR_EEP("HT40 Switch Settle", pModal->swSettleHt40);
+        PR_EEP("Chain0 xatten2Db", pModal->xatten2Db[0]);
+        PR_EEP("Chain0 xatten2Margin", pModal->xatten2Margin[0]);
+        PR_EEP("Ant. Diversity ctl1", pModal->antdiv_ctl1);
+        PR_EEP("Ant. Diversity ctl2", pModal->antdiv_ctl2);
+        PR_EEP("TX Diversity", pModal->tx_diversity);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PR_EEP
+}
+
+static ssize_t read_def_modal_eeprom(struct file *file,
+                                     char __user *user_buf,
+                                     size_t count, loff_t *ppos)
+{
+#define PR_EEP(_s, _val)                                                \
+        do {                                                            \
+                if (pBase->opCapFlags & AR5416_OPFLAGS_11G) {           \
+                        pModal = &priv->ah->eeprom.def.modalHeader[1];  \
+                        len += snprintf(buf + len, size - len, "%20s : %8d%7s", \
+                                        _s, (_val), "|");               \
+                }                                                       \
+                if (pBase->opCapFlags & AR5416_OPFLAGS_11A) {           \
+                        pModal = &priv->ah->eeprom.def.modalHeader[0];  \
+                        len += snprintf(buf + len, size - len, "%9d\n", \
+                                        (_val));                        \
+                }                                                       \
+        } while (0)
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct base_eep_header *pBase = &priv->ah->eeprom.def.baseEepHeader;
+        struct modal_eep_header *pModal = NULL;
+        unsigned int len = 0, size = 3500;
+        ssize_t retval = 0;
+        char *buf;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "%31s %15s\n", "2G", "5G");
+        len += snprintf(buf + len, size - len,
+                        "%32s %16s\n", "====", "====\n");
+
+        PR_EEP("Chain0 Ant. Control", pModal->antCtrlChain[0]);
+        PR_EEP("Chain1 Ant. Control", pModal->antCtrlChain[1]);
+        PR_EEP("Chain2 Ant. Control", pModal->antCtrlChain[2]);
+        PR_EEP("Ant. Common Control", pModal->antCtrlCommon);
+        PR_EEP("Chain0 Ant. Gain", pModal->antennaGainCh[0]);
+        PR_EEP("Chain1 Ant. Gain", pModal->antennaGainCh[1]);
+        PR_EEP("Chain2 Ant. Gain", pModal->antennaGainCh[2]);
+        PR_EEP("Switch Settle", pModal->switchSettling);
+        PR_EEP("Chain0 TxRxAtten", pModal->txRxAttenCh[0]);
+        PR_EEP("Chain1 TxRxAtten", pModal->txRxAttenCh[1]);
+        PR_EEP("Chain2 TxRxAtten", pModal->txRxAttenCh[2]);
+        PR_EEP("Chain0 RxTxMargin", pModal->rxTxMarginCh[0]);
+        PR_EEP("Chain1 RxTxMargin", pModal->rxTxMarginCh[1]);
+        PR_EEP("Chain2 RxTxMargin", pModal->rxTxMarginCh[2]);
+        PR_EEP("ADC Desired size", pModal->adcDesiredSize);
+        PR_EEP("PGA Desired size", pModal->pgaDesiredSize);
+        PR_EEP("Chain0 xlna Gain", pModal->xlnaGainCh[0]);
+        PR_EEP("Chain1 xlna Gain", pModal->xlnaGainCh[1]);
+        PR_EEP("Chain2 xlna Gain", pModal->xlnaGainCh[2]);
+        PR_EEP("txEndToXpaOff", pModal->txEndToXpaOff);
+        PR_EEP("txEndToRxOn", pModal->txEndToRxOn);
+        PR_EEP("txFrameToXpaOn", pModal->txFrameToXpaOn);
+        PR_EEP("CCA Threshold)", pModal->thresh62);
+        PR_EEP("Chain0 NF Threshold", pModal->noiseFloorThreshCh[0]);
+        PR_EEP("Chain1 NF Threshold", pModal->noiseFloorThreshCh[1]);
+        PR_EEP("Chain2 NF Threshold", pModal->noiseFloorThreshCh[2]);
+        PR_EEP("xpdGain", pModal->xpdGain);
+        PR_EEP("External PD", pModal->xpd);
+        PR_EEP("Chain0 I Coefficient", pModal->iqCalICh[0]);
+        PR_EEP("Chain1 I Coefficient", pModal->iqCalICh[1]);
+        PR_EEP("Chain2 I Coefficient", pModal->iqCalICh[2]);
+        PR_EEP("Chain0 Q Coefficient", pModal->iqCalQCh[0]);
+        PR_EEP("Chain1 Q Coefficient", pModal->iqCalQCh[1]);
+        PR_EEP("Chain2 Q Coefficient", pModal->iqCalQCh[2]);
+        PR_EEP("pdGainOverlap", pModal->pdGainOverlap);
+        PR_EEP("Chain0 OutputBias", pModal->ob);
+        PR_EEP("Chain0 DriverBias", pModal->db);
+        PR_EEP("xPA Bias Level", pModal->xpaBiasLvl);
+        PR_EEP("2chain pwr decrease", pModal->pwrDecreaseFor2Chain);
+        PR_EEP("3chain pwr decrease", pModal->pwrDecreaseFor3Chain);
+        PR_EEP("txFrameToDataStart", pModal->txFrameToDataStart);
+        PR_EEP("txFrameToPaOn", pModal->txFrameToPaOn);
+        PR_EEP("HT40 Power Inc.", pModal->ht40PowerIncForPdadc);
+        PR_EEP("Chain0 bswAtten", pModal->bswAtten[0]);
+        PR_EEP("Chain1 bswAtten", pModal->bswAtten[1]);
+        PR_EEP("Chain2 bswAtten", pModal->bswAtten[2]);
+        PR_EEP("Chain0 bswMargin", pModal->bswMargin[0]);
+        PR_EEP("Chain1 bswMargin", pModal->bswMargin[1]);
+        PR_EEP("Chain2 bswMargin", pModal->bswMargin[2]);
+        PR_EEP("HT40 Switch Settle", pModal->swSettleHt40);
+        PR_EEP("Chain0 xatten2Db", pModal->xatten2Db[0]);
+        PR_EEP("Chain1 xatten2Db", pModal->xatten2Db[1]);
+        PR_EEP("Chain2 xatten2Db", pModal->xatten2Db[2]);
+        PR_EEP("Chain0 xatten2Margin", pModal->xatten2Margin[0]);
+        PR_EEP("Chain1 xatten2Margin", pModal->xatten2Margin[1]);
+        PR_EEP("Chain2 xatten2Margin", pModal->xatten2Margin[2]);
+        PR_EEP("Chain1 OutputBias", pModal->ob_ch1);
+        PR_EEP("Chain1 DriverBias", pModal->db_ch1);
+        PR_EEP("LNA Control", pModal->lna_ctl);
+        PR_EEP("XPA Bias Freq0", pModal->xpaBiasLvlFreq[0]);
+        PR_EEP("XPA Bias Freq1", pModal->xpaBiasLvlFreq[1]);
+        PR_EEP("XPA Bias Freq2", pModal->xpaBiasLvlFreq[2]);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PR_EEP
+}
+
+static ssize_t read_9287_modal_eeprom(struct file *file,
+                                      char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+#define PR_EEP(_s, _val)                                                \
+        do {                                                            \
+                len += snprintf(buf + len, size - len, "%20s : %10d\n", \
+                                _s, (_val));                            \
+        } while (0)
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct modal_eep_ar9287_header *pModal = &priv->ah->eeprom.map9287.modalHeader;
+        unsigned int len = 0, size = 3000;
+        ssize_t retval = 0;
+        char *buf;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        PR_EEP("Chain0 Ant. Control", pModal->antCtrlChain[0]);
+        PR_EEP("Chain1 Ant. Control", pModal->antCtrlChain[1]);
+        PR_EEP("Ant. Common Control", pModal->antCtrlCommon);
+        PR_EEP("Chain0 Ant. Gain", pModal->antennaGainCh[0]);
+        PR_EEP("Chain1 Ant. Gain", pModal->antennaGainCh[1]);
+        PR_EEP("Switch Settle", pModal->switchSettling);
+        PR_EEP("Chain0 TxRxAtten", pModal->txRxAttenCh[0]);
+        PR_EEP("Chain1 TxRxAtten", pModal->txRxAttenCh[1]);
+        PR_EEP("Chain0 RxTxMargin", pModal->rxTxMarginCh[0]);
+        PR_EEP("Chain1 RxTxMargin", pModal->rxTxMarginCh[1]);
+        PR_EEP("ADC Desired size", pModal->adcDesiredSize);
+        PR_EEP("txEndToXpaOff", pModal->txEndToXpaOff);
+        PR_EEP("txEndToRxOn", pModal->txEndToRxOn);
+        PR_EEP("txFrameToXpaOn", pModal->txFrameToXpaOn);
+        PR_EEP("CCA Threshold)", pModal->thresh62);
+        PR_EEP("Chain0 NF Threshold", pModal->noiseFloorThreshCh[0]);
+        PR_EEP("Chain1 NF Threshold", pModal->noiseFloorThreshCh[1]);
+        PR_EEP("xpdGain", pModal->xpdGain);
+        PR_EEP("External PD", pModal->xpd);
+        PR_EEP("Chain0 I Coefficient", pModal->iqCalICh[0]);
+        PR_EEP("Chain1 I Coefficient", pModal->iqCalICh[1]);
+        PR_EEP("Chain0 Q Coefficient", pModal->iqCalQCh[0]);
+        PR_EEP("Chain1 Q Coefficient", pModal->iqCalQCh[1]);
+        PR_EEP("pdGainOverlap", pModal->pdGainOverlap);
+        PR_EEP("xPA Bias Level", pModal->xpaBiasLvl);
+        PR_EEP("txFrameToDataStart", pModal->txFrameToDataStart);
+        PR_EEP("txFrameToPaOn", pModal->txFrameToPaOn);
+        PR_EEP("HT40 Power Inc.", pModal->ht40PowerIncForPdadc);
+        PR_EEP("Chain0 bswAtten", pModal->bswAtten[0]);
+        PR_EEP("Chain1 bswAtten", pModal->bswAtten[1]);
+        PR_EEP("Chain0 bswMargin", pModal->bswMargin[0]);
+        PR_EEP("Chain1 bswMargin", pModal->bswMargin[1]);
+        PR_EEP("HT40 Switch Settle", pModal->swSettleHt40);
+        PR_EEP("AR92x7 Version", pModal->version);
+        PR_EEP("DriverBias1", pModal->db1);
+        PR_EEP("DriverBias2", pModal->db1);
+        PR_EEP("CCK OutputBias", pModal->ob_cck);
+        PR_EEP("PSK OutputBias", pModal->ob_psk);
+        PR_EEP("QAM OutputBias", pModal->ob_qam);
+        PR_EEP("PAL_OFF OutputBias", pModal->ob_pal_off);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PR_EEP
+}
+
+static ssize_t read_file_modal_eeprom(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+
+        if (AR_SREV_9271(priv->ah))
+                return read_4k_modal_eeprom(file, user_buf, count, ppos);
+        else if (priv->ah->hw_version.usbdev == AR9280_USB)
+                return read_def_modal_eeprom(file, user_buf, count, ppos);
+        else if (priv->ah->hw_version.usbdev == AR9287_USB)
+                return read_9287_modal_eeprom(file, user_buf, count, ppos);
+
+        return 0;
+}
+
+static const struct file_operations fops_modal_eeprom = {
+        .read = read_file_modal_eeprom,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+int ath9k_htc_init_debug(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
+
+        priv->debug.debugfs_phy = debugfs_create_dir(KBUILD_MODNAME,
+                                             priv->hw->wiphy->debugfsdir);
+        if (!priv->debug.debugfs_phy)
+                return -ENOMEM;
+
+        debugfs_create_file("tgt_int_stats", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_tgt_int_stats);
+        debugfs_create_file("tgt_tx_stats", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_tgt_tx_stats);
+        debugfs_create_file("tgt_rx_stats", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_tgt_rx_stats);
+        debugfs_create_file("xmit", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_xmit);
+        debugfs_create_file("recv", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_recv);
+        debugfs_create_file("slot", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_slot);
+        debugfs_create_file("queue", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_queue);
+        debugfs_create_file("debug", S_IRUSR | S_IWUSR, priv->debug.debugfs_phy,
+                            priv, &fops_debug);
+        debugfs_create_file("base_eeprom", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_base_eeprom);
+        debugfs_create_file("modal_eeprom", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_modal_eeprom);
+
+        return 0;
+}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
new file mode 100644
index 000000000000..db2352e5cc0d
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "htc.h"
+
+/******************/
+/*     BTCOEX     */
+/******************/
+
+/*
+ * Detects if there is any priority bt traffic
+ */
+static void ath_detect_bt_priority(struct ath9k_htc_priv *priv)
+{
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_hw *ah = priv->ah;
+
+        if (ath9k_hw_gpio_get(ah, ah->btcoex_hw.btpriority_gpio))
+                btcoex->bt_priority_cnt++;
+
+        if (time_after(jiffies, btcoex->bt_priority_time +
+                        msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
+                priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN);
+                /* Detect if colocated bt started scanning */
+                if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "BT scan detected\n");
+                        priv->op_flags |= (OP_BT_SCAN |
+                                         OP_BT_PRIORITY_DETECTED);
+                } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "BT priority traffic detected\n");
+                        priv->op_flags |= OP_BT_PRIORITY_DETECTED;
+                }
+
+                btcoex->bt_priority_cnt = 0;
+                btcoex->bt_priority_time = jiffies;
+        }
+}
+
+/*
+ * This is the master bt coex work which runs for every
+ * 45ms, bt traffic will be given priority during 55% of this
+ * period while wlan gets remaining 45%
+ */
+static void ath_btcoex_period_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   coex_period_work.work);
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        u32 timer_period;
+        bool is_btscan;
+        int ret;
+
+        ath_detect_bt_priority(priv);
+
+        is_btscan = !!(priv->op_flags & OP_BT_SCAN);
+
+        ret = ath9k_htc_update_cap_target(priv,
+                                  !!(priv->op_flags & OP_BT_PRIORITY_DETECTED));
+        if (ret) {
+                ath_err(common, "Unable to set BTCOEX parameters\n");
+                return;
+        }
+
+        ath9k_hw_btcoex_bt_stomp(priv->ah, is_btscan ? ATH_BTCOEX_STOMP_ALL :
+                        btcoex->bt_stomp_type);
+
+        timer_period = is_btscan ? btcoex->btscan_no_stomp :
+                btcoex->btcoex_no_stomp;
+        ieee80211_queue_delayed_work(priv->hw, &priv->duty_cycle_work,
+                                     msecs_to_jiffies(timer_period));
+        ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work,
+                                     msecs_to_jiffies(btcoex->btcoex_period));
+}
+
+/*
+ * Work to time slice between wlan and bt traffic and
+ * configure weight registers
+ */
+static void ath_btcoex_duty_cycle_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   duty_cycle_work.work);
+        struct ath_hw *ah = priv->ah;
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_common *common = ath9k_hw_common(ah);
+        bool is_btscan = priv->op_flags & OP_BT_SCAN;
+
+        ath_dbg(common, ATH_DBG_BTCOEX,
+                "time slice work for bt and wlan\n");
+
+        if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
+        else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
+}
+
+void ath_htc_init_btcoex_work(struct ath9k_htc_priv *priv)
+{
+        struct ath_btcoex *btcoex = &priv->btcoex;
+
+        btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
+        btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
+                btcoex->btcoex_period / 100;
+        btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
+                                   btcoex->btcoex_period / 100;
+        INIT_DELAYED_WORK(&priv->coex_period_work, ath_btcoex_period_work);
+        INIT_DELAYED_WORK(&priv->duty_cycle_work, ath_btcoex_duty_cycle_work);
+}
+
+/*
+ * (Re)start btcoex work
+ */
+
+void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv)
+{
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_hw *ah = priv->ah;
+
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, "Starting btcoex work\n");
+
+        btcoex->bt_priority_cnt = 0;
+        btcoex->bt_priority_time = jiffies;
+        priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN);
+        ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 0);
+}
+
+
+/*
+ * Cancel btcoex and bt duty cycle work.
+ */
+void ath_htc_cancel_btcoex_work(struct ath9k_htc_priv *priv)
+{
+        cancel_delayed_work_sync(&priv->coex_period_work);
+        cancel_delayed_work_sync(&priv->duty_cycle_work);
+}
+
+/*******/
+/* LED */
+/*******/
+
+#ifdef CONFIG_MAC80211_LEDS
+void ath9k_led_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work,
+                                                   struct ath9k_htc_priv,
+                                                   led_work);
+
+        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
+                          (priv->brightness == LED_OFF));
+}
+
+static void ath9k_led_brightness(struct led_classdev *led_cdev,
+                                 enum led_brightness brightness)
+{
+        struct ath9k_htc_priv *priv = container_of(led_cdev,
+                                                   struct ath9k_htc_priv,
+                                                   led_cdev);
+
+        /* Not locked, but it's just a tiny green light..*/
+        priv->brightness = brightness;
+        ieee80211_queue_work(priv->hw, &priv->led_work);
+}
+
+void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
+{
+        if (!priv->led_registered)
+                return;
+
+        ath9k_led_brightness(&priv->led_cdev, LED_OFF);
+        led_classdev_unregister(&priv->led_cdev);
+        cancel_work_sync(&priv->led_work);
+}
+
+void ath9k_init_leds(struct ath9k_htc_priv *priv)
+{
+        int ret;
+
+        if (AR_SREV_9287(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_9287;
+        else if (AR_SREV_9271(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_9271;
+        else if (AR_DEVID_7010(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_7010;
+        else
+                priv->ah->led_pin = ATH_LED_PIN_DEF;
+
+        /* Configure gpio 1 for output */
+        ath9k_hw_cfg_output(priv->ah, priv->ah->led_pin,
+                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+        /* LED off, active low */
+        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
+
+        snprintf(priv->led_name, sizeof(priv->led_name),
+                "ath9k_htc-%s", wiphy_name(priv->hw->wiphy));
+        priv->led_cdev.name = priv->led_name;
+        priv->led_cdev.brightness_set = ath9k_led_brightness;
+
+        ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &priv->led_cdev);
+        if (ret < 0)
+                return;
+
+        INIT_WORK(&priv->led_work, ath9k_led_work);
+        priv->led_registered = true;
+
+        return;
+}
+#endif
+
+/*******************/
+/*      Rfkill     */
+/*******************/
+
+static bool ath_is_rfkill_set(struct ath9k_htc_priv *priv)
+{
+        return ath9k_hw_gpio_get(priv->ah, priv->ah->rfkill_gpio) ==
+                priv->ah->rfkill_polarity;
+}
+
+void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        bool blocked = !!ath_is_rfkill_set(priv);
+
+        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
+}
+
+void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
+{
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
+                wiphy_rfkill_start_polling(priv->hw->wiphy);
+}
+
+void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret;
+        u8 cmd_rsp;
+
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        /* Reset the HW */
+        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, ah->curchan->channel);
+        }
+
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
+
+        /* Start RX */
+        WMI_CMD(WMI_START_RECV_CMDID);
+        ath9k_host_rx_init(priv);
+
+        /* Start TX */
+        htc_start(priv->htc);
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
+        spin_unlock_bh(&priv->tx.tx_lock);
+        ieee80211_wake_queues(hw);
+
+        WMI_CMD(WMI_ENABLE_INTR_CMDID);
+
+        /* Enable LED */
+        ath9k_hw_cfg_output(ah, ah->led_pin,
+                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
+}
+
+void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret;
+        u8 cmd_rsp;
+
+        ath9k_htc_ps_wakeup(priv);
+
+        /* Disable LED */
+        ath9k_hw_set_gpio(ah, ah->led_pin, 1);
+        ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+
+        /* Stop TX */
+        ieee80211_stop_queues(hw);
+        ath9k_htc_tx_drain(priv);
+        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
+
+        /* Stop RX */
+        WMI_CMD(WMI_STOP_RECV_CMDID);
+
+        /* Clear the WMI event queue */
+        ath9k_wmi_event_drain(priv);
+
+        /*
+         * The MIB counters have to be disabled here,
+         * since the target doesn't do it.
+         */
+        ath9k_hw_disable_mib_counters(ah);
+
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        /* Reset the HW */
+        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, ah->curchan->channel);
+        }
+
+        /* Disable the PHY */
+        ath9k_hw_phy_disable(ah);
+
+        ath9k_htc_ps_restore(priv);
+        ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
+}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 2d4279191d7a..61e6d3950718 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -41,6 +41,8 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
         .max_power = 20, \
 }
 
+#define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
+
 static struct ieee80211_channel ath9k_2ghz_channels[] = {
         CHAN2G(2412, 0), /* Channel 1 */
         CHAN2G(2417, 1), /* Channel 2 */
@@ -115,6 +117,21 @@ static struct ieee80211_rate ath9k_legacy_rates[] = {
         RATE(540, 0x0c, 0),
 };
 
+#ifdef CONFIG_MAC80211_LEDS
+static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
+        { .throughput = 0 * 1024, .blink_time = 334 },
+        { .throughput = 1 * 1024, .blink_time = 260 },
+        { .throughput = 5 * 1024, .blink_time = 220 },
+        { .throughput = 10 * 1024, .blink_time = 190 },
+        { .throughput = 20 * 1024, .blink_time = 170 },
+        { .throughput = 50 * 1024, .blink_time = 150 },
+        { .throughput = 70 * 1024, .blink_time = 130 },
+        { .throughput = 100 * 1024, .blink_time = 110 },
+        { .throughput = 200 * 1024, .blink_time = 80 },
+        { .throughput = 300 * 1024, .blink_time = 50 },
+};
+#endif
+
 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
 {
         int time_left;
@@ -138,11 +155,7 @@ static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
 
 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
 {
-        ath9k_htc_exit_debug(priv->ah);
         ath9k_hw_deinit(priv->ah);
-        tasklet_kill(&priv->wmi_tasklet);
-        tasklet_kill(&priv->rx_tasklet);
-        tasklet_kill(&priv->tx_tasklet);
         kfree(priv->ah);
         priv->ah = NULL;
 }
@@ -179,7 +192,8 @@ static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
         return htc_connect_service(priv->htc, &req, ep_id);
 }
 
-static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
+static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
+                                   u32 drv_info)
 {
         int ret;
 
@@ -243,15 +257,10 @@ static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
          * the HIF layer, shouldn't matter much.
          */
 
-        switch(devid) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
+        if (IS_AR7010_DEVICE(drv_info))
                 priv->htc->credits = 45;
-                break;
-        default:
+        else
                 priv->htc->credits = 33;
-        }
 
         ret = htc_init(priv->htc);
         if (ret)
@@ -290,21 +299,49 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
                           (u8 *) &val, sizeof(val),
                           100);
         if (unlikely(r)) {
-                ath_print(common, ATH_DBG_WMI,
-                          "REGISTER READ FAILED: (0x%04x, %d)\n",
-                           reg_offset, r);
+                ath_dbg(common, ATH_DBG_WMI,
+                        "REGISTER READ FAILED: (0x%04x, %d)\n",
+                        reg_offset, r);
                 return -EIO;
         }
 
         return be32_to_cpu(val);
 }
 
+static void ath9k_multi_regread(void *hw_priv, u32 *addr,
+                                u32 *val, u16 count)
+{
+        struct ath_hw *ah = (struct ath_hw *) hw_priv;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
+        __be32 tmpaddr[8];
+        __be32 tmpval[8];
+        int i, ret;
+
+       for (i = 0; i < count; i++) {
+               tmpaddr[i] = cpu_to_be32(addr[i]);
+       }
+
+       ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
+                           (u8 *)tmpaddr , sizeof(u32) * count,
+                           (u8 *)tmpval, sizeof(u32) * count,
+                           100);
+        if (unlikely(ret)) {
+                ath_dbg(common, ATH_DBG_WMI,
+                        "Multiple REGISTER READ FAILED (count: %d)\n", count);
+        }
+
+       for (i = 0; i < count; i++) {
+               val[i] = be32_to_cpu(tmpval[i]);
+       }
+}
+
 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
 {
         struct ath_hw *ah = (struct ath_hw *) hw_priv;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-        __be32 buf[2] = {
+        const __be32 buf[2] = {
                 cpu_to_be32(reg_offset),
                 cpu_to_be32(val),
         };
@@ -315,9 +352,9 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
                           (u8 *) &val, sizeof(val),
                           100);
         if (unlikely(r)) {
-                ath_print(common, ATH_DBG_WMI,
-                          "REGISTER WRITE FAILED:(0x%04x, %d)\n",
-                          reg_offset, r);
+                ath_dbg(common, ATH_DBG_WMI,
+                        "REGISTER WRITE FAILED:(0x%04x, %d)\n",
+                        reg_offset, r);
         }
 }
 
@@ -347,9 +384,9 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
                           (u8 *) &rsp_status, sizeof(rsp_status),
                           100);
                 if (unlikely(r)) {
-                        ath_print(common, ATH_DBG_WMI,
-                                  "REGISTER WRITE FAILED, multi len: %d\n",
-                                  priv->wmi->multi_write_idx);
+                        ath_dbg(common, ATH_DBG_WMI,
+                                "REGISTER WRITE FAILED, multi len: %d\n",
+                                priv->wmi->multi_write_idx);
                 }
                 priv->wmi->multi_write_idx = 0;
         }
@@ -378,15 +415,6 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv)
         atomic_inc(&priv->wmi->mwrite_cnt);
 }
 
-static void ath9k_disable_regwrite_buffer(void *hw_priv)
-{
-        struct ath_hw *ah = (struct ath_hw *) hw_priv;
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-        atomic_dec(&priv->wmi->mwrite_cnt);
-}
-
 static void ath9k_regwrite_flush(void *hw_priv)
 {
         struct ath_hw *ah = (struct ath_hw *) hw_priv;
@@ -395,6 +423,8 @@ static void ath9k_regwrite_flush(void *hw_priv)
         u32 rsp_status;
         int r;
 
+        atomic_dec(&priv->wmi->mwrite_cnt);
+
         mutex_lock(&priv->wmi->multi_write_mutex);
 
         if (priv->wmi->multi_write_idx) {
@@ -404,9 +434,9 @@ static void ath9k_regwrite_flush(void *hw_priv)
                           (u8 *) &rsp_status, sizeof(rsp_status),
                           100);
                 if (unlikely(r)) {
-                        ath_print(common, ATH_DBG_WMI,
-                                  "REGISTER WRITE FAILED, multi len: %d\n",
-                                  priv->wmi->multi_write_idx);
+                        ath_dbg(common, ATH_DBG_WMI,
+                                "REGISTER WRITE FAILED, multi len: %d\n",
+                                priv->wmi->multi_write_idx);
                 }
                 priv->wmi->multi_write_idx = 0;
         }
@@ -414,13 +444,16 @@ static void ath9k_regwrite_flush(void *hw_priv)
         mutex_unlock(&priv->wmi->multi_write_mutex);
 }
 
-static const struct ath_ops ath9k_common_ops = {
-        .read = ath9k_regread,
-        .write = ath9k_regwrite,
-        .enable_write_buffer = ath9k_enable_regwrite_buffer,
-        .disable_write_buffer = ath9k_disable_regwrite_buffer,
-        .write_flush = ath9k_regwrite_flush,
-};
+static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
+{
+        u32 val;
+
+        val = ath9k_regread(hw_priv, reg_offset);
+        val &= ~clr;
+        val |= set;
+        ath9k_regwrite(hw_priv, val, reg_offset);
+        return val;
+}
 
 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
 {
@@ -479,9 +512,9 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv,
         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "TX streams %d, RX streams: %d\n",
-                  tx_streams, rx_streams);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "TX streams %d, RX streams: %d\n",
+                tx_streams, rx_streams);
 
         if (tx_streams != rx_streams) {
                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -505,37 +538,31 @@ static int ath9k_init_queues(struct ath9k_htc_priv *priv)
 
         priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
         if (priv->beaconq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup BEACON xmit queue\n");
+                ath_err(common, "Unable to setup BEACON xmit queue\n");
                 goto err;
         }
 
         priv->cabq = ath9k_htc_cabq_setup(priv);
         if (priv->cabq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup CAB xmit queue\n");
+                ath_err(common, "Unable to setup CAB xmit queue\n");
                 goto err;
         }
 
         if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BE traffic\n");
+                ath_err(common, "Unable to setup xmit queue for BE traffic\n");
                 goto err;
         }
 
         if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BK traffic\n");
+                ath_err(common, "Unable to setup xmit queue for BK traffic\n");
                 goto err;
         }
         if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VI traffic\n");
+                ath_err(common, "Unable to setup xmit queue for VI traffic\n");
                 goto err;
         }
         if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VO traffic\n");
+                ath_err(common, "Unable to setup xmit queue for VO traffic\n");
                 goto err;
         }
 
@@ -551,25 +578,22 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
         int i = 0;
 
         /* Get the hardware key cache size. */
-        common->keymax = priv->ah->caps.keycache_size;
-        if (common->keymax > ATH_KEYMAX) {
-                ath_print(common, ATH_DBG_ANY,
-                          "Warning, using only %u entries in %u key cache\n",
-                          ATH_KEYMAX, common->keymax);
-                common->keymax = ATH_KEYMAX;
-        }
+        common->keymax = AR_KEYTABLE_SIZE;
+
+        if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
+                common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
 
         /*
          * Reset the key cache since some parts do not
          * reset the contents on initial power up.
          */
         for (i = 0; i < common->keymax; i++)
-                ath9k_hw_keyreset(priv->ah, (u16) i);
+                ath_hw_keyreset(common, (u16) i);
 }
 
 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
 {
-        if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
                 priv->sbands[IEEE80211_BAND_2GHZ].channels =
                         ath9k_2ghz_channels;
                 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
@@ -580,7 +604,7 @@ static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
                         ARRAY_SIZE(ath9k_legacy_rates);
         }
 
-        if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) {
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
                 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
                 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
                 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
@@ -599,17 +623,41 @@ static void ath9k_init_misc(struct ath9k_htc_priv *priv)
         common->tx_chainmask = priv->ah->caps.tx_chainmask;
         common->rx_chainmask = priv->ah->caps.rx_chainmask;
 
-        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
+        memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 
         priv->ah->opmode = NL80211_IFTYPE_STATION;
 }
 
-static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
+static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
+{
+        int qnum;
+
+        switch (priv->ah->btcoex_hw.scheme) {
+        case ATH_BTCOEX_CFG_NONE:
+                break;
+        case ATH_BTCOEX_CFG_3WIRE:
+                priv->ah->btcoex_hw.btactive_gpio = 7;
+                priv->ah->btcoex_hw.btpriority_gpio = 6;
+                priv->ah->btcoex_hw.wlanactive_gpio = 8;
+                priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
+                ath9k_hw_btcoex_init_3wire(priv->ah);
+                ath_htc_init_btcoex_work(priv);
+                qnum = priv->hwq_map[WME_AC_BE];
+                ath9k_hw_init_btcoex_hw(priv->ah, qnum);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+}
+
+static int ath9k_init_priv(struct ath9k_htc_priv *priv,
+                           u16 devid, char *product,
+                           u32 drv_info)
 {
         struct ath_hw *ah = NULL;
         struct ath_common *common;
-        int ret = 0, csz = 0;
+        int i, ret = 0, csz = 0;
 
         priv->op_flags |= OP_INVALID;
 
@@ -619,28 +667,37 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
 
         ah->hw_version.devid = devid;
         ah->hw_version.subsysid = 0; /* FIXME */
+        ah->hw_version.usbdev = drv_info;
+        ah->ah_flags |= AH_USE_EEPROM;
+        ah->reg_ops.read = ath9k_regread;
+        ah->reg_ops.multi_read = ath9k_multi_regread;
+        ah->reg_ops.write = ath9k_regwrite;
+        ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
+        ah->reg_ops.write_flush = ath9k_regwrite_flush;
+        ah->reg_ops.rmw = ath9k_reg_rmw;
         priv->ah = ah;
 
         common = ath9k_hw_common(ah);
-        common->ops = &ath9k_common_ops;
+        common->ops = &ah->reg_ops;
         common->bus_ops = &ath9k_usb_bus_ops;
         common->ah = ah;
         common->hw = priv->hw;
         common->priv = priv;
         common->debug_mask = ath9k_debug;
 
-        spin_lock_init(&priv->wmi->wmi_lock);
         spin_lock_init(&priv->beacon_lock);
-        spin_lock_init(&priv->tx_lock);
+        spin_lock_init(&priv->tx.tx_lock);
         mutex_init(&priv->mutex);
         mutex_init(&priv->htc_pm_lock);
-        tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
-                     (unsigned long)priv);
         tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
                      (unsigned long)priv);
-        tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
-        INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
+        tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
+                     (unsigned long)priv);
+        INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
         INIT_WORK(&priv->ps_work, ath9k_ps_work);
+        INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
+        setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
+                    (unsigned long)priv);
 
         /*
          * Cache line size is used to size and align various
@@ -651,32 +708,31 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
 
         ret = ath9k_hw_init(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize hardware; "
-                          "initialization status: %d\n", ret);
+                ath_err(common,
+                        "Unable to initialize hardware; initialization status: %d\n",
+                        ret);
                 goto err_hw;
         }
 
-        ret = ath9k_htc_init_debug(ah);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to create debugfs files\n");
-                goto err_debug;
-        }
-
         ret = ath9k_init_queues(priv);
         if (ret)
                 goto err_queues;
 
+        for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
+                priv->cur_beacon_conf.bslot[i] = NULL;
+
         ath9k_init_crypto(priv);
         ath9k_init_channels_rates(priv);
         ath9k_init_misc(priv);
 
+        if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
+                ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
+                ath9k_init_btcoex(priv);
+        }
+
         return 0;
 
 err_queues:
-        ath9k_htc_exit_debug(ah);
-err_debug:
         ath9k_hw_deinit(ah);
 err_hw:
 
@@ -697,17 +753,22 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
                 IEEE80211_HW_HAS_RATE_CONTROL |
                 IEEE80211_HW_RX_INCLUDES_FCS |
                 IEEE80211_HW_SUPPORTS_PS |
-                IEEE80211_HW_PS_NULLFUNC_STACK;
+                IEEE80211_HW_PS_NULLFUNC_STACK |
+                IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
 
         hw->wiphy->interface_modes =
                 BIT(NL80211_IFTYPE_STATION) |
-                BIT(NL80211_IFTYPE_ADHOC);
+                BIT(NL80211_IFTYPE_ADHOC) |
+                BIT(NL80211_IFTYPE_AP) |
+                BIT(NL80211_IFTYPE_P2P_GO) |
+                BIT(NL80211_IFTYPE_P2P_CLIENT);
 
         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 
         hw->queues = 4;
         hw->channel_change_time = 5000;
         hw->max_listen_interval = 10;
+
         hw->vif_data_size = sizeof(struct ath9k_htc_vif);
         hw->sta_data_size = sizeof(struct ath9k_htc_sta);
 
@@ -715,18 +776,18 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
         hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
                 sizeof(struct htc_frame_hdr) + 4;
 
-        if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &priv->sbands[IEEE80211_BAND_2GHZ];
-        if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
                         &priv->sbands[IEEE80211_BAND_5GHZ];
 
         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
-                if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
+                if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                         setup_ht_cap(priv,
                                      &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
-                if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
+                if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                         setup_ht_cap(priv,
                                      &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
         }
@@ -734,16 +795,55 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 }
 
-static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
+static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
+{
+        struct ieee80211_hw *hw = priv->hw;
+        struct wmi_fw_version cmd_rsp;
+        int ret;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        WMI_CMD(WMI_GET_FW_VERSION);
+        if (ret)
+                return -EINVAL;
+
+        priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
+        priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
+
+        snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
+                 priv->fw_version_major,
+                 priv->fw_version_minor);
+
+        dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
+                 priv->fw_version_major,
+                 priv->fw_version_minor);
+
+        /*
+         * Check if the available FW matches the driver's
+         * required version.
+         */
+        if (priv->fw_version_major != MAJOR_VERSION_REQ ||
+            priv->fw_version_minor != MINOR_VERSION_REQ) {
+                dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
+                        MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int ath9k_init_device(struct ath9k_htc_priv *priv,
+                             u16 devid, char *product, u32 drv_info)
 {
         struct ieee80211_hw *hw = priv->hw;
         struct ath_common *common;
         struct ath_hw *ah;
         int error = 0;
         struct ath_regulatory *reg;
+        char hw_name[64];
 
         /* Bring up device */
-        error = ath9k_init_priv(priv, devid);
+        error = ath9k_init_priv(priv, devid, product, drv_info);
         if (error != 0)
                 goto err_init;
 
@@ -751,6 +851,10 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
         common = ath9k_hw_common(ah);
         ath9k_set_hw_capab(priv, hw);
 
+        error = ath9k_init_firmware_version(priv);
+        if (error != 0)
+                goto err_fw;
+
         /* Initialize regulatory */
         error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
                               ath9k_reg_notifier);
@@ -769,6 +873,13 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
         if (error != 0)
                 goto err_rx;
 
+#ifdef CONFIG_MAC80211_LEDS
+        /* must be initialized before ieee80211_register_hw */
+        priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
+                IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
+                ARRAY_SIZE(ath9k_htc_tpt_blink));
+#endif
+
         /* Register with mac80211 */
         error = ieee80211_register_hw(hw);
         if (error)
@@ -781,6 +892,28 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
                         goto err_world;
         }
 
+        error = ath9k_htc_init_debug(priv->ah);
+        if (error) {
+                ath_err(common, "Unable to create debugfs files\n");
+                goto err_world;
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, "
+                "BE:%d, BK:%d, VI:%d, VO:%d\n",
+                priv->wmi_cmd_ep,
+                priv->beacon_ep,
+                priv->cab_ep,
+                priv->uapsd_ep,
+                priv->mgmt_ep,
+                priv->data_be_ep,
+                priv->data_bk_ep,
+                priv->data_vi_ep,
+                priv->data_vo_ep);
+
+        ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
+        wiphy_info(hw->wiphy, "%s\n", hw_name);
+
         ath9k_init_leds(priv);
         ath9k_start_rfkill_poll(priv);
 
@@ -795,13 +928,15 @@ err_rx:
 err_tx:
         /* Nothing */
 err_regd:
+        /* Nothing */
+err_fw:
         ath9k_deinit_priv(priv);
 err_init:
         return error;
 }
 
 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
-                           u16 devid)
+                           u16 devid, char *product, u32 drv_info)
 {
         struct ieee80211_hw *hw;
         struct ath9k_htc_priv *priv;
@@ -828,14 +963,11 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
                 goto err_free;
         }
 
-        ret = ath9k_init_htc_services(priv, devid);
+        ret = ath9k_init_htc_services(priv, devid, drv_info);
         if (ret)
                 goto err_init;
 
-        /* The device may have been unplugged earlier. */
-        priv->op_flags &= ~OP_UNPLUGGED;
-
-        ret = ath9k_init_device(priv, devid);
+        ret = ath9k_init_device(priv, devid, product, drv_info);
         if (ret)
                 goto err_init;
 
@@ -854,7 +986,7 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 
                 /* Check if the device has been yanked out. */
                 if (hotunplug)
-                        htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
+                        htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
 
                 ath9k_deinit_device(htc_handle->drv_priv);
                 ath9k_deinit_wmi(htc_handle->drv_priv);
@@ -863,54 +995,43 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 }
 
 #ifdef CONFIG_PM
+
+void ath9k_htc_suspend(struct htc_target *htc_handle)
+{
+        ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
+}
+
 int ath9k_htc_resume(struct htc_target *htc_handle)
 {
+        struct ath9k_htc_priv *priv = htc_handle->drv_priv;
         int ret;
 
-        ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
+        ret = ath9k_htc_wait_for_target(priv);
         if (ret)
                 return ret;
 
-        ret = ath9k_init_htc_services(htc_handle->drv_priv,
-                              htc_handle->drv_priv->ah->hw_version.devid);
+        ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
+                                      priv->ah->hw_version.usbdev);
         return ret;
 }
 #endif
 
 static int __init ath9k_htc_init(void)
 {
-        int error;
-
-        error = ath9k_htc_debug_create_root();
-        if (error < 0) {
-                printk(KERN_ERR
-                        "ath9k_htc: Unable to create debugfs root: %d\n",
-                        error);
-                goto err_dbg;
-        }
-
-        error = ath9k_hif_usb_init();
-        if (error < 0) {
+        if (ath9k_hif_usb_init() < 0) {
                 printk(KERN_ERR
                         "ath9k_htc: No USB devices found,"
                         " driver not installed.\n");
-                error = -ENODEV;
-                goto err_usb;
+                return -ENODEV;
         }
 
         return 0;
-
-err_usb:
-        ath9k_htc_debug_remove_root();
-err_dbg:
-        return error;
 }
 module_init(ath9k_htc_init);
 
 static void __exit ath9k_htc_exit(void)
 {
         ath9k_hif_usb_exit();
-        ath9k_htc_debug_remove_root();
         printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
 }
 module_exit(ath9k_htc_exit);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 7d09b4b17bbd..7b7796895432 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,32 +16,17 @@
 
 #include "htc.h"
 
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-static struct dentry *ath9k_debugfs_root;
-#endif
-
 /*************/
 /* Utilities */
 /*************/
 
-static void ath_update_txpow(struct ath9k_htc_priv *priv)
-{
-        struct ath_hw *ah = priv->ah;
-
-        if (priv->curtxpow != priv->txpowlimit) {
-                ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit);
-                /* read back in case value is clamped */
-                priv->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
-        }
-}
-
 /* HACK Alert: Use 11NG for 2.4, use 11NA for 5 */
 static enum htc_phymode ath9k_htc_get_curmode(struct ath9k_htc_priv *priv,
                                               struct ath9k_channel *ichan)
 {
         enum htc_phymode mode;
 
-        mode = HTC_MODE_AUTO;
+        mode = -EINVAL;
 
         switch (ichan->chanmode) {
         case CHANNEL_G:
@@ -60,11 +45,13 @@ static enum htc_phymode ath9k_htc_get_curmode(struct ath9k_htc_priv *priv,
                 break;
         }
 
+        WARN_ON(mode < 0);
+
         return mode;
 }
 
-static bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
-                               enum ath9k_power_mode mode)
+bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
+                        enum ath9k_power_mode mode)
 {
         bool ret;
 
@@ -116,6 +103,138 @@ void ath9k_ps_work(struct work_struct *work)
         ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
 }
 
+static void ath9k_htc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_htc_priv *priv = data;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+
+        if ((vif->type == NL80211_IFTYPE_AP) && bss_conf->enable_beacon)
+                priv->reconfig_beacon = true;
+
+        if (bss_conf->assoc) {
+                priv->rearm_ani = true;
+                priv->reconfig_beacon = true;
+        }
+}
+
+static void ath9k_htc_vif_reconfig(struct ath9k_htc_priv *priv)
+{
+        priv->rearm_ani = false;
+        priv->reconfig_beacon = false;
+
+        ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                   ath9k_htc_vif_iter, priv);
+        if (priv->rearm_ani)
+                ath9k_htc_start_ani(priv);
+
+        if (priv->reconfig_beacon) {
+                ath9k_htc_ps_wakeup(priv);
+                ath9k_htc_beacon_reconfig(priv);
+                ath9k_htc_ps_restore(priv);
+        }
+}
+
+static void ath9k_htc_bssid_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_vif_iter_data *iter_data = data;
+        int i;
+
+        for (i = 0; i < ETH_ALEN; i++)
+                iter_data->mask[i] &= ~(iter_data->hw_macaddr[i] ^ mac[i]);
+}
+
+static void ath9k_htc_set_bssid_mask(struct ath9k_htc_priv *priv,
+                                     struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_vif_iter_data iter_data;
+
+        /*
+         * Use the hardware MAC address as reference, the hardware uses it
+         * together with the BSSID mask when matching addresses.
+         */
+        iter_data.hw_macaddr = common->macaddr;
+        memset(&iter_data.mask, 0xff, ETH_ALEN);
+
+        if (vif)
+                ath9k_htc_bssid_iter(&iter_data, vif->addr, vif);
+
+        /* Get list of all active MAC addresses */
+        ieee80211_iterate_active_interfaces_atomic(priv->hw, ath9k_htc_bssid_iter,
+                                                   &iter_data);
+
+        memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
+        ath_hw_setbssidmask(common);
+}
+
+static void ath9k_htc_set_opmode(struct ath9k_htc_priv *priv)
+{
+        if (priv->num_ibss_vif)
+                priv->ah->opmode = NL80211_IFTYPE_ADHOC;
+        else if (priv->num_ap_vif)
+                priv->ah->opmode = NL80211_IFTYPE_AP;
+        else
+                priv->ah->opmode = NL80211_IFTYPE_STATION;
+
+        ath9k_hw_setopmode(priv->ah);
+}
+
+void ath9k_htc_reset(struct ath9k_htc_priv *priv)
+{
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_channel *channel = priv->hw->conf.channel;
+        struct ath9k_hw_cal_data *caldata = NULL;
+        enum htc_phymode mode;
+        __be16 htc_mode;
+        u8 cmd_rsp;
+        int ret;
+
+        mutex_lock(&priv->mutex);
+        ath9k_htc_ps_wakeup(priv);
+
+        ath9k_htc_stop_ani(priv);
+        ieee80211_stop_queues(priv->hw);
+
+        del_timer_sync(&priv->tx.cleanup_timer);
+        ath9k_htc_tx_drain(priv);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
+        WMI_CMD(WMI_STOP_RECV_CMDID);
+
+        ath9k_wmi_event_drain(priv);
+
+        caldata = &priv->caldata;
+        ret = ath9k_hw_reset(ah, ah->curchan, caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset device (%u Mhz) reset status %d\n",
+                        channel->center_freq, ret);
+        }
+
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
+
+        WMI_CMD(WMI_START_RECV_CMDID);
+        ath9k_host_rx_init(priv);
+
+        mode = ath9k_htc_get_curmode(priv, ah->curchan);
+        htc_mode = cpu_to_be16(mode);
+        WMI_CMD_BUF(WMI_SET_MODE_CMDID, &htc_mode);
+
+        WMI_CMD(WMI_ENABLE_INTR_CMDID);
+        htc_start(priv->htc);
+        ath9k_htc_vif_reconfig(priv);
+        ieee80211_wake_queues(priv->hw);
+
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
+
+        ath9k_htc_ps_restore(priv);
+        mutex_unlock(&priv->mutex);
+}
+
 static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
                                  struct ieee80211_hw *hw,
                                  struct ath9k_channel *hchan)
@@ -123,9 +242,9 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_conf *conf = &common->hw->conf;
-        bool fastcc = true;
+        bool fastcc;
         struct ieee80211_channel *channel = hw->conf.channel;
-        struct ath9k_hw_cal_data *caldata;
+        struct ath9k_hw_cal_data *caldata = NULL;
         enum htc_phymode mode;
         __be16 htc_mode;
         u8 cmd_rsp;
@@ -134,32 +253,38 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         if (priv->op_flags & OP_INVALID)
                 return -EIO;
 
-        if (priv->op_flags & OP_FULL_RESET)
-                fastcc = false;
+        fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
 
-        /* Fiddle around with fastcc later on, for now just use full reset */
-        fastcc = false;
         ath9k_htc_ps_wakeup(priv);
-        htc_stop(priv->htc);
+
+        del_timer_sync(&priv->tx.cleanup_timer);
+        ath9k_htc_tx_drain(priv);
+
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
         WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
         WMI_CMD(WMI_STOP_RECV_CMDID);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "(%u MHz) -> (%u MHz), HT: %d, HT40: %d\n",
-                  priv->ah->curchan->channel,
-                  channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf));
+        ath9k_wmi_event_drain(priv);
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n",
+                priv->ah->curchan->channel,
+                channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf),
+                fastcc);
+
+        if (!fastcc)
+                caldata = &priv->caldata;
 
-        caldata = &priv->caldata[channel->hw_value];
         ret = ath9k_hw_reset(ah, hchan, caldata, fastcc);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u Mhz) "
-                          "reset status %d\n", channel->center_freq, ret);
+                ath_err(common,
+                        "Unable to reset channel (%u Mhz) reset status %d\n",
+                        channel->center_freq, ret);
                 goto err;
         }
 
-        ath_update_txpow(priv);
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
 
         WMI_CMD(WMI_START_RECV_CMDID);
         if (ret)
@@ -179,51 +304,159 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
 
         htc_start(priv->htc);
 
-        priv->op_flags &= ~OP_FULL_RESET;
+        if (!(priv->op_flags & OP_SCANNING) &&
+            !(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
+                ath9k_htc_vif_reconfig(priv);
+
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
+
 err:
         ath9k_htc_ps_restore(priv);
         return ret;
 }
 
-static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv)
+/*
+ * Monitor mode handling is a tad complicated because the firmware requires
+ * an interface to be created exclusively, while mac80211 doesn't associate
+ * an interface with the mode.
+ *
+ * So, for now, only one monitor interface can be configured.
+ */
+static void __ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         struct ath9k_htc_target_vif hvif;
         int ret = 0;
         u8 cmd_rsp;
 
-        if (priv->nvifs > 0)
-                return -ENOBUFS;
+        memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
+        memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
+        hvif.index = priv->mon_vif_idx;
+        WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
+        if (ret) {
+                ath_err(common, "Unable to remove monitor interface at idx: %d\n",
+                        priv->mon_vif_idx);
+        }
 
+        priv->nvifs--;
+        priv->vif_slot &= ~(1 << priv->mon_vif_idx);
+}
+
+static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_target_vif hvif;
+        struct ath9k_htc_target_sta tsta;
+        int ret = 0, sta_idx;
+        u8 cmd_rsp;
+
+        if ((priv->nvifs >= ATH9K_HTC_MAX_VIF) ||
+            (priv->nstations >= ATH9K_HTC_MAX_STA)) {
+                ret = -ENOBUFS;
+                goto err_vif;
+        }
+
+        sta_idx = ffz(priv->sta_slot);
+        if ((sta_idx < 0) || (sta_idx > ATH9K_HTC_MAX_STA)) {
+                ret = -ENOBUFS;
+                goto err_vif;
+        }
+
+        /*
+         * Add an interface.
+         */
         memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
         memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
 
-        hvif.opmode = cpu_to_be32(HTC_M_MONITOR);
-        priv->ah->opmode = NL80211_IFTYPE_MONITOR;
-        hvif.index = priv->nvifs;
+        hvif.opmode = HTC_M_MONITOR;
+        hvif.index = ffz(priv->vif_slot);
 
         WMI_CMD_BUF(WMI_VAP_CREATE_CMDID, &hvif);
         if (ret)
-                return ret;
+                goto err_vif;
+
+        /*
+         * Assign the monitor interface index as a special case here.
+         * This is needed when the interface is brought down.
+         */
+        priv->mon_vif_idx = hvif.index;
+        priv->vif_slot |= (1 << hvif.index);
+
+        /*
+         * Set the hardware mode to monitor only if there are no
+         * other interfaces.
+         */
+        if (!priv->nvifs)
+                priv->ah->opmode = NL80211_IFTYPE_MONITOR;
 
         priv->nvifs++;
+
+        /*
+         * Associate a station with the interface for packet injection.
+         */
+        memset(&tsta, 0, sizeof(struct ath9k_htc_target_sta));
+
+        memcpy(&tsta.macaddr, common->macaddr, ETH_ALEN);
+
+        tsta.is_vif_sta = 1;
+        tsta.sta_index = sta_idx;
+        tsta.vif_index = hvif.index;
+        tsta.maxampdu = cpu_to_be16(0xffff);
+
+        WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
+        if (ret) {
+                ath_err(common, "Unable to add station entry for monitor mode\n");
+                goto err_sta;
+        }
+
+        priv->sta_slot |= (1 << sta_idx);
+        priv->nstations++;
+        priv->vif_sta_pos[priv->mon_vif_idx] = sta_idx;
+        priv->ah->is_monitoring = true;
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attached a monitor interface at idx: %d, sta idx: %d\n",
+                priv->mon_vif_idx, sta_idx);
+
         return 0;
+
+err_sta:
+        /*
+         * Remove the interface from the target.
+         */
+        __ath9k_htc_remove_monitor_interface(priv);
+err_vif:
+        ath_dbg(common, ATH_DBG_FATAL, "Unable to attach a monitor interface\n");
+
+        return ret;
 }
 
 static int ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct ath9k_htc_target_vif hvif;
         int ret = 0;
-        u8 cmd_rsp;
+        u8 cmd_rsp, sta_idx;
 
-        memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
-        memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
-        hvif.index = 0; /* Should do for now */
-        WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
-        priv->nvifs--;
+        __ath9k_htc_remove_monitor_interface(priv);
 
-        return ret;
+        sta_idx = priv->vif_sta_pos[priv->mon_vif_idx];
+
+        WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
+        if (ret) {
+                ath_err(common, "Unable to remove station entry for monitor mode\n");
+                return ret;
+        }
+
+        priv->sta_slot &= ~(1 << sta_idx);
+        priv->nstations--;
+        priv->ah->is_monitoring = false;
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Removed a monitor interface at idx: %d, sta idx: %d\n",
+                priv->mon_vif_idx, sta_idx);
+
+        return 0;
 }
 
 static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
@@ -234,47 +467,65 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
         struct ath9k_htc_target_sta tsta;
         struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
         struct ath9k_htc_sta *ista;
-        int ret;
+        int ret, sta_idx;
         u8 cmd_rsp;
+        u16 maxampdu;
 
         if (priv->nstations >= ATH9K_HTC_MAX_STA)
                 return -ENOBUFS;
 
+        sta_idx = ffz(priv->sta_slot);
+        if ((sta_idx < 0) || (sta_idx > ATH9K_HTC_MAX_STA))
+                return -ENOBUFS;
+
         memset(&tsta, 0, sizeof(struct ath9k_htc_target_sta));
 
         if (sta) {
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
                 memcpy(&tsta.macaddr, sta->addr, ETH_ALEN);
                 memcpy(&tsta.bssid, common->curbssid, ETH_ALEN);
-                tsta.associd = common->curaid;
                 tsta.is_vif_sta = 0;
-                tsta.valid = true;
-                ista->index = priv->nstations;
+                ista->index = sta_idx;
         } else {
                 memcpy(&tsta.macaddr, vif->addr, ETH_ALEN);
                 tsta.is_vif_sta = 1;
         }
 
-        tsta.sta_index = priv->nstations;
+        tsta.sta_index = sta_idx;
         tsta.vif_index = avp->index;
-        tsta.maxampdu = 0xffff;
-        if (sta && sta->ht_cap.ht_supported)
-                tsta.flags = cpu_to_be16(ATH_HTC_STA_HT);
+
+        if (!sta) {
+                tsta.maxampdu = cpu_to_be16(0xffff);
+        } else {
+                maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
+                                 sta->ht_cap.ampdu_factor);
+                tsta.maxampdu = cpu_to_be16(maxampdu);
+        }
 
         WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
         if (ret) {
                 if (sta)
-                        ath_print(common, ATH_DBG_FATAL,
-                          "Unable to add station entry for: %pM\n", sta->addr);
+                        ath_err(common,
+                                "Unable to add station entry for: %pM\n",
+                                sta->addr);
                 return ret;
         }
 
-        if (sta)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Added a station entry for: %pM (idx: %d)\n",
-                          sta->addr, tsta.sta_index);
+        if (sta) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Added a station entry for: %pM (idx: %d)\n",
+                        sta->addr, tsta.sta_index);
+        } else {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Added a station entry for VIF %d (idx: %d)\n",
+                        avp->index, tsta.sta_index);
+        }
 
+        priv->sta_slot |= (1 << sta_idx);
         priv->nstations++;
+        if (!sta)
+                priv->vif_sta_pos[avp->index] = sta_idx;
+
         return 0;
 }
 
@@ -283,6 +534,7 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv,
                                     struct ieee80211_sta *sta)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
         struct ath9k_htc_sta *ista;
         int ret;
         u8 cmd_rsp, sta_idx;
@@ -291,28 +543,36 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv,
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
                 sta_idx = ista->index;
         } else {
-                sta_idx = 0;
+                sta_idx = priv->vif_sta_pos[avp->index];
         }
 
         WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
         if (ret) {
                 if (sta)
-                        ath_print(common, ATH_DBG_FATAL,
-                          "Unable to remove station entry for: %pM\n",
-                          sta->addr);
+                        ath_err(common,
+                                "Unable to remove station entry for: %pM\n",
+                                sta->addr);
                 return ret;
         }
 
-        if (sta)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Removed a station entry for: %pM (idx: %d)\n",
-                          sta->addr, sta_idx);
+        if (sta) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Removed a station entry for: %pM (idx: %d)\n",
+                        sta->addr, sta_idx);
+        } else {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Removed a station entry for VIF %d (idx: %d)\n",
+                        avp->index, sta_idx);
+        }
 
+        priv->sta_slot &= ~(1 << sta_idx);
         priv->nstations--;
+
         return 0;
 }
 
-static int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv)
+int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv,
+                                u8 enable_coex)
 {
         struct ath9k_htc_cap_target tcap;
         int ret;
@@ -320,13 +580,9 @@ static int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv)
 
         memset(&tcap, 0, sizeof(struct ath9k_htc_cap_target));
 
-        /* FIXME: Values are hardcoded */
-        tcap.flags = 0x240c40;
-        tcap.flags_ext = 0x80601000;
-        tcap.ampdu_limit = 0xffff0000;
-        tcap.ampdu_subframes = 20;
-        tcap.tx_chainmask_legacy = priv->ah->caps.tx_chainmask;
-        tcap.protmode = 1;
+        tcap.ampdu_limit = cpu_to_be32(0xffff);
+        tcap.ampdu_subframes = 0xff;
+        tcap.enable_coex = enable_coex;
         tcap.tx_chainmask = priv->ah->caps.tx_chainmask;
 
         WMI_CMD_BUF(WMI_TARGET_IC_UPDATE_CMDID, &tcap);
@@ -391,8 +647,8 @@ static int ath9k_htc_send_rate_cmd(struct ath9k_htc_priv *priv,
 
         WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, trate);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize Rate information on target\n");
+                ath_err(common,
+                        "Unable to initialize Rate information on target\n");
         }
 
         return ret;
@@ -409,9 +665,9 @@ static void ath9k_htc_init_rate(struct ath9k_htc_priv *priv,
         ath9k_htc_setup_rate(priv, sta, &trate);
         ret = ath9k_htc_send_rate_cmd(priv, &trate);
         if (!ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Updated target sta: %pM, rate caps: 0x%X\n",
-                          sta->addr, be32_to_cpu(trate.capflags));
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Updated target sta: %pM, rate caps: 0x%X\n",
+                        sta->addr, be32_to_cpu(trate.capflags));
 }
 
 static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
@@ -436,9 +692,9 @@ static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
 
         ret = ath9k_htc_send_rate_cmd(priv, &trate);
         if (!ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Updated target sta: %pM, rate caps: 0x%X\n",
-                          bss_conf->bssid, be32_to_cpu(trate.capflags));
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Updated target sta: %pM, rate caps: 0x%X\n",
+                        bss_conf->bssid, be32_to_cpu(trate.capflags));
 }
 
 static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
@@ -465,229 +721,27 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
 
         WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr);
         if (ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unable to %s TX aggregation for (%pM, %d)\n",
-                          (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unable to %s TX aggregation for (%pM, %d)\n",
+                        (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
         else
-                ath_print(common, ATH_DBG_CONFIG,
-                          "%s TX aggregation for (%pM, %d)\n",
-                          (aggr.aggr_enable) ? "Starting" : "Stopping",
-                          sta->addr, tid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "%s TX aggregation for (%pM, %d)\n",
+                        (aggr.aggr_enable) ? "Starting" : "Stopping",
+                        sta->addr, tid);
 
-        spin_lock_bh(&priv->tx_lock);
+        spin_lock_bh(&priv->tx.tx_lock);
         ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP;
-        spin_unlock_bh(&priv->tx_lock);
+        spin_unlock_bh(&priv->tx.tx_lock);
 
         return ret;
 }
 
-/*********/
-/* DEBUG */
-/*********/
-
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-
-static int ath9k_debugfs_open(struct inode *inode, struct file *file)
-{
-        file->private_data = inode->i_private;
-        return 0;
-}
-
-static ssize_t read_file_tgt_stats(struct file *file, char __user *user_buf,
-                                   size_t count, loff_t *ppos)
-{
-        struct ath9k_htc_priv *priv = file->private_data;
-        struct ath9k_htc_target_stats cmd_rsp;
-        char buf[512];
-        unsigned int len = 0;
-        int ret = 0;
-
-        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
-
-        WMI_CMD(WMI_TGT_STATS_CMDID);
-        if (ret)
-                return -EINVAL;
-
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Short Retries",
-                        be32_to_cpu(cmd_rsp.tx_shortretry));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Long Retries",
-                        be32_to_cpu(cmd_rsp.tx_longretry));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Xretries",
-                        be32_to_cpu(cmd_rsp.tx_xretries));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Unaggr. Xretries",
-                        be32_to_cpu(cmd_rsp.ht_txunaggr_xretry));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Xretries (HT)",
-                        be32_to_cpu(cmd_rsp.ht_tx_xretries));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Rate", priv->debug.txrate);
-
-        if (len > sizeof(buf))
-                len = sizeof(buf);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
-static const struct file_operations fops_tgt_stats = {
-        .read = read_file_tgt_stats,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
-                              size_t count, loff_t *ppos)
-{
-        struct ath9k_htc_priv *priv = file->private_data;
-        char buf[512];
-        unsigned int len = 0;
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "Buffers queued",
-                        priv->debug.tx_stats.buf_queued);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "Buffers completed",
-                        priv->debug.tx_stats.buf_completed);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs queued",
-                        priv->debug.tx_stats.skb_queued);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs completed",
-                        priv->debug.tx_stats.skb_completed);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs dropped",
-                        priv->debug.tx_stats.skb_dropped);
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "BE queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_BE]);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "BK queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_BK]);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "VI queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_VI]);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "VO queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_VO]);
-
-        if (len > sizeof(buf))
-                len = sizeof(buf);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
-static const struct file_operations fops_xmit = {
-        .read = read_file_xmit,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-static ssize_t read_file_recv(struct file *file, char __user *user_buf,
-                              size_t count, loff_t *ppos)
-{
-        struct ath9k_htc_priv *priv = file->private_data;
-        char buf[512];
-        unsigned int len = 0;
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs allocated",
-                        priv->debug.rx_stats.skb_allocated);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs completed",
-                        priv->debug.rx_stats.skb_completed);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs Dropped",
-                        priv->debug.rx_stats.skb_dropped);
-
-        if (len > sizeof(buf))
-                len = sizeof(buf);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
-static const struct file_operations fops_recv = {
-        .read = read_file_recv,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-int ath9k_htc_init_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
-
-        priv->debug.debugfs_phy = debugfs_create_dir(wiphy_name(priv->hw->wiphy),
-                                                     ath9k_debugfs_root);
-        if (!priv->debug.debugfs_phy)
-                goto err;
-
-        priv->debug.debugfs_tgt_stats = debugfs_create_file("tgt_stats", S_IRUSR,
-                                                    priv->debug.debugfs_phy,
-                                                    priv, &fops_tgt_stats);
-        if (!priv->debug.debugfs_tgt_stats)
-                goto err;
-
-
-        priv->debug.debugfs_xmit = debugfs_create_file("xmit", S_IRUSR,
-                                                       priv->debug.debugfs_phy,
-                                                       priv, &fops_xmit);
-        if (!priv->debug.debugfs_xmit)
-                goto err;
-
-        priv->debug.debugfs_recv = debugfs_create_file("recv", S_IRUSR,
-                                                       priv->debug.debugfs_phy,
-                                                       priv, &fops_recv);
-        if (!priv->debug.debugfs_recv)
-                goto err;
-
-        return 0;
-
-err:
-        ath9k_htc_exit_debug(ah);
-        return -ENOMEM;
-}
-
-void ath9k_htc_exit_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-        debugfs_remove(priv->debug.debugfs_recv);
-        debugfs_remove(priv->debug.debugfs_xmit);
-        debugfs_remove(priv->debug.debugfs_tgt_stats);
-        debugfs_remove(priv->debug.debugfs_phy);
-}
-
-int ath9k_htc_debug_create_root(void)
-{
-        ath9k_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
-
-        return 0;
-}
-
-void ath9k_htc_debug_remove_root(void)
-{
-        debugfs_remove(ath9k_debugfs_root);
-        ath9k_debugfs_root = NULL;
-}
-
-#endif /* CONFIG_ATH9K_HTC_DEBUGFS */
-
 /*******/
 /* ANI */
 /*******/
 
-static void ath_start_ani(struct ath9k_htc_priv *priv)
+void ath9k_htc_start_ani(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         unsigned long timestamp = jiffies_to_msecs(jiffies);
@@ -696,15 +750,22 @@ static void ath_start_ani(struct ath9k_htc_priv *priv)
         common->ani.shortcal_timer = timestamp;
         common->ani.checkani_timer = timestamp;
 
-        ieee80211_queue_delayed_work(common->hw, &priv->ath9k_ani_work,
+        priv->op_flags |= OP_ANI_RUNNING;
+
+        ieee80211_queue_delayed_work(common->hw, &priv->ani_work,
                                      msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 }
 
-void ath9k_ani_work(struct work_struct *work)
+void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv)
+{
+        cancel_delayed_work_sync(&priv->ani_work);
+        priv->op_flags &= ~OP_ANI_RUNNING;
+}
+
+void ath9k_htc_ani_work(struct work_struct *work)
 {
         struct ath9k_htc_priv *priv =
-                container_of(work, struct ath9k_htc_priv,
-                             ath9k_ani_work.work);
+                container_of(work, struct ath9k_htc_priv, ani_work.work);
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
         bool longcal = false;
@@ -713,7 +774,8 @@ void ath9k_ani_work(struct work_struct *work)
         unsigned int timestamp = jiffies_to_msecs(jiffies);
         u32 cal_interval, short_cal_interval;
 
-        short_cal_interval = ATH_STA_SHORT_CALINTERVAL;
+        short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
+                ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 
         /* Only calibrate if awake */
         if (ah->power_mode != ATH9K_PM_AWAKE)
@@ -722,7 +784,7 @@ void ath9k_ani_work(struct work_struct *work)
         /* Long calibration runs independently of short calibration. */
         if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
                 longcal = true;
-                ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
+                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -731,8 +793,8 @@ void ath9k_ani_work(struct work_struct *work)
                 if ((timestamp - common->ani.shortcal_timer) >=
                     short_cal_interval) {
                         shortcal = true;
-                        ath_print(common, ATH_DBG_ANI,
-                                  "shortcal @%lu\n", jiffies);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -761,23 +823,12 @@ void ath9k_ani_work(struct work_struct *work)
                         ath9k_hw_ani_monitor(ah, ah->curchan);
 
                 /* Perform calibration if necessary */
-                if (longcal || shortcal) {
+                if (longcal || shortcal)
                         common->ani.caldone =
                                 ath9k_hw_calibrate(ah, ah->curchan,
                                                    common->rx_chainmask,
                                                    longcal);
 
-                        if (longcal)
-                                common->ani.noise_floor =
-                                        ath9k_hw_getchan_noise(ah, ah->curchan);
-
-                        ath_print(common, ATH_DBG_ANI,
-                                  " calibrate chan %u/%x nf: %d\n",
-                                  ah->curchan->channel,
-                                  ah->curchan->channelFlags,
-                                  common->ani.noise_floor);
-                }
-
                 ath9k_htc_ps_restore(priv);
         }
 
@@ -793,330 +844,20 @@ set_timer:
         if (!common->ani.caldone)
                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 
-        ieee80211_queue_delayed_work(common->hw, &priv->ath9k_ani_work,
+        ieee80211_queue_delayed_work(common->hw, &priv->ani_work,
                                      msecs_to_jiffies(cal_interval));
 }
 
-/*******/
-/* LED */
-/*******/
-
-static void ath9k_led_blink_work(struct work_struct *work)
-{
-        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
-                                                   ath9k_led_blink_work.work);
-
-        if (!(priv->op_flags & OP_LED_ASSOCIATED))
-                return;
-
-        if ((priv->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
-            (priv->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
-                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
-        else
-                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
-                                  (priv->op_flags & OP_LED_ON) ? 1 : 0);
-
-        ieee80211_queue_delayed_work(priv->hw,
-                                     &priv->ath9k_led_blink_work,
-                                     (priv->op_flags & OP_LED_ON) ?
-                                     msecs_to_jiffies(priv->led_off_duration) :
-                                     msecs_to_jiffies(priv->led_on_duration));
-
-        priv->led_on_duration = priv->led_on_cnt ?
-                max((ATH_LED_ON_DURATION_IDLE - priv->led_on_cnt), 25) :
-                ATH_LED_ON_DURATION_IDLE;
-        priv->led_off_duration = priv->led_off_cnt ?
-                max((ATH_LED_OFF_DURATION_IDLE - priv->led_off_cnt), 10) :
-                ATH_LED_OFF_DURATION_IDLE;
-        priv->led_on_cnt = priv->led_off_cnt = 0;
-
-        if (priv->op_flags & OP_LED_ON)
-                priv->op_flags &= ~OP_LED_ON;
-        else
-                priv->op_flags |= OP_LED_ON;
-}
-
-static void ath9k_led_brightness_work(struct work_struct *work)
-{
-        struct ath_led *led = container_of(work, struct ath_led,
-                                           brightness_work.work);
-        struct ath9k_htc_priv *priv = led->priv;
-
-        switch (led->brightness) {
-        case LED_OFF:
-                if (led->led_type == ATH_LED_ASSOC ||
-                    led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
-                                          (led->led_type == ATH_LED_RADIO));
-                        priv->op_flags &= ~OP_LED_ASSOCIATED;
-                        if (led->led_type == ATH_LED_RADIO)
-                                priv->op_flags &= ~OP_LED_ON;
-                } else {
-                        priv->led_off_cnt++;
-                }
-                break;
-        case LED_FULL:
-                if (led->led_type == ATH_LED_ASSOC) {
-                        priv->op_flags |= OP_LED_ASSOCIATED;
-                        ieee80211_queue_delayed_work(priv->hw,
-                                             &priv->ath9k_led_blink_work, 0);
-                } else if (led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
-                        priv->op_flags |= OP_LED_ON;
-                } else {
-                        priv->led_on_cnt++;
-                }
-                break;
-        default:
-                break;
-        }
-}
-
-static void ath9k_led_brightness(struct led_classdev *led_cdev,
-                                 enum led_brightness brightness)
-{
-        struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
-        struct ath9k_htc_priv *priv = led->priv;
-
-        led->brightness = brightness;
-        if (!(priv->op_flags & OP_LED_DEINIT))
-                ieee80211_queue_delayed_work(priv->hw,
-                                             &led->brightness_work, 0);
-}
-
-static void ath9k_led_stop_brightness(struct ath9k_htc_priv *priv)
-{
-        cancel_delayed_work_sync(&priv->radio_led.brightness_work);
-        cancel_delayed_work_sync(&priv->assoc_led.brightness_work);
-        cancel_delayed_work_sync(&priv->tx_led.brightness_work);
-        cancel_delayed_work_sync(&priv->rx_led.brightness_work);
-}
-
-static int ath9k_register_led(struct ath9k_htc_priv *priv, struct ath_led *led,
-                              char *trigger)
-{
-        int ret;
-
-        led->priv = priv;
-        led->led_cdev.name = led->name;
-        led->led_cdev.default_trigger = trigger;
-        led->led_cdev.brightness_set = ath9k_led_brightness;
-
-        ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &led->led_cdev);
-        if (ret)
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL,
-                          "Failed to register led:%s", led->name);
-        else
-                led->registered = 1;
-
-        INIT_DELAYED_WORK(&led->brightness_work, ath9k_led_brightness_work);
-
-        return ret;
-}
-
-static void ath9k_unregister_led(struct ath_led *led)
-{
-        if (led->registered) {
-                led_classdev_unregister(&led->led_cdev);
-                led->registered = 0;
-        }
-}
-
-void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
-{
-        priv->op_flags |= OP_LED_DEINIT;
-        ath9k_unregister_led(&priv->assoc_led);
-        priv->op_flags &= ~OP_LED_ASSOCIATED;
-        ath9k_unregister_led(&priv->tx_led);
-        ath9k_unregister_led(&priv->rx_led);
-        ath9k_unregister_led(&priv->radio_led);
-}
-
-void ath9k_init_leds(struct ath9k_htc_priv *priv)
-{
-        char *trigger;
-        int ret;
-
-        if (AR_SREV_9287(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_9287;
-        else if (AR_SREV_9271(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_9271;
-        else if (AR_DEVID_7010(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_7010;
-        else
-                priv->ah->led_pin = ATH_LED_PIN_DEF;
-
-        /* Configure gpio 1 for output */
-        ath9k_hw_cfg_output(priv->ah, priv->ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        /* LED off, active low */
-        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
-
-        INIT_DELAYED_WORK(&priv->ath9k_led_blink_work, ath9k_led_blink_work);
-
-        trigger = ieee80211_get_radio_led_name(priv->hw);
-        snprintf(priv->radio_led.name, sizeof(priv->radio_led.name),
-                "ath9k-%s::radio", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->radio_led, trigger);
-        priv->radio_led.led_type = ATH_LED_RADIO;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_assoc_led_name(priv->hw);
-        snprintf(priv->assoc_led.name, sizeof(priv->assoc_led.name),
-                "ath9k-%s::assoc", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->assoc_led, trigger);
-        priv->assoc_led.led_type = ATH_LED_ASSOC;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_tx_led_name(priv->hw);
-        snprintf(priv->tx_led.name, sizeof(priv->tx_led.name),
-                "ath9k-%s::tx", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->tx_led, trigger);
-        priv->tx_led.led_type = ATH_LED_TX;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_rx_led_name(priv->hw);
-        snprintf(priv->rx_led.name, sizeof(priv->rx_led.name),
-                "ath9k-%s::rx", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->rx_led, trigger);
-        priv->rx_led.led_type = ATH_LED_RX;
-        if (ret)
-                goto fail;
-
-        priv->op_flags &= ~OP_LED_DEINIT;
-
-        return;
-
-fail:
-        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
-        ath9k_deinit_leds(priv);
-}
-
-/*******************/
-/*      Rfkill     */
-/*******************/
-
-static bool ath_is_rfkill_set(struct ath9k_htc_priv *priv)
-{
-        return ath9k_hw_gpio_get(priv->ah, priv->ah->rfkill_gpio) ==
-                priv->ah->rfkill_polarity;
-}
-
-static void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        bool blocked = !!ath_is_rfkill_set(priv);
-
-        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
-}
-
-void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
-{
-        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
-                wiphy_rfkill_start_polling(priv->hw->wiphy);
-}
-
-static void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        int ret;
-        u8 cmd_rsp;
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        /* Reset the HW */
-        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, ah->curchan->channel);
-        }
-
-        ath_update_txpow(priv);
-
-        /* Start RX */
-        WMI_CMD(WMI_START_RECV_CMDID);
-        ath9k_host_rx_init(priv);
-
-        /* Start TX */
-        htc_start(priv->htc);
-        spin_lock_bh(&priv->tx_lock);
-        priv->tx_queues_stop = false;
-        spin_unlock_bh(&priv->tx_lock);
-        ieee80211_wake_queues(hw);
-
-        WMI_CMD(WMI_ENABLE_INTR_CMDID);
-
-        /* Enable LED */
-        ath9k_hw_cfg_output(ah, ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
-}
-
-static void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        int ret;
-        u8 cmd_rsp;
-
-        ath9k_htc_ps_wakeup(priv);
-
-        /* Disable LED */
-        ath9k_hw_set_gpio(ah, ah->led_pin, 1);
-        ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
-
-        WMI_CMD(WMI_DISABLE_INTR_CMDID);
-
-        /* Stop TX */
-        ieee80211_stop_queues(hw);
-        htc_stop(priv->htc);
-        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
-        skb_queue_purge(&priv->tx_queue);
-
-        /* Stop RX */
-        WMI_CMD(WMI_STOP_RECV_CMDID);
-
-        /*
-         * The MIB counters have to be disabled here,
-         * since the target doesn't do it.
-         */
-        ath9k_hw_disable_mib_counters(ah);
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        /* Reset the HW */
-        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, ah->curchan->channel);
-        }
-
-        /* Disable the PHY */
-        ath9k_hw_phy_disable(ah);
-
-        ath9k_htc_ps_restore(priv);
-        ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
-}
-
 /**********************/
 /* mac80211 Callbacks */
 /**********************/
 
-static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+static void ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 {
         struct ieee80211_hdr *hdr;
         struct ath9k_htc_priv *priv = hw->priv;
-        int padpos, padsize, ret;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        int padpos, padsize, ret, slot;
 
         hdr = (struct ieee80211_hdr *) skb->data;
 
@@ -1124,33 +865,34 @@ static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         padpos = ath9k_cmn_padpos(hdr->frame_control);
         padsize = padpos & 3;
         if (padsize && skb->len > padpos) {
-                if (skb_headroom(skb) < padsize)
-                        return -1;
+                if (skb_headroom(skb) < padsize) {
+                        ath_dbg(common, ATH_DBG_XMIT, "No room for padding\n");
+                        goto fail_tx;
+                }
                 skb_push(skb, padsize);
                 memmove(skb->data, skb->data + padsize, padpos);
         }
 
-        ret = ath9k_htc_tx_start(priv, skb);
-        if (ret != 0) {
-                if (ret == -ENOMEM) {
-                        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                                  "Stopping TX queues\n");
-                        ieee80211_stop_queues(hw);
-                        spin_lock_bh(&priv->tx_lock);
-                        priv->tx_queues_stop = true;
-                        spin_unlock_bh(&priv->tx_lock);
-                } else {
-                        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                                  "Tx failed");
-                }
+        slot = ath9k_htc_tx_get_slot(priv);
+        if (slot < 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "No free TX slot\n");
                 goto fail_tx;
         }
 
-        return 0;
+        ret = ath9k_htc_tx_start(priv, skb, slot, false);
+        if (ret != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "Tx failed\n");
+                goto clear_slot;
+        }
+
+        ath9k_htc_check_stop_queues(priv);
+
+        return;
 
+clear_slot:
+        ath9k_htc_tx_clear_slot(priv, slot);
 fail_tx:
         dev_kfree_skb_any(skb);
-        return 0;
 }
 
 static int ath9k_htc_start(struct ieee80211_hw *hw)
@@ -1167,9 +909,9 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
 
         mutex_lock(&priv->mutex);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Starting driver with initial channel: %d MHz\n",
-                  curchan->center_freq);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Starting driver with initial channel: %d MHz\n",
+                curchan->center_freq);
 
         /* Ensure that HW is awake before flushing RX */
         ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
@@ -1178,20 +920,18 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
         /* setup initial channel */
         init_channel = ath9k_cmn_get_curchannel(hw, ah);
 
-        /* Reset SERDES registers */
-        ath9k_hw_configpcipowersave(ah, 0, 0);
-
         ath9k_hw_htc_resetinit(ah);
         ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, curchan->center_freq);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, curchan->center_freq);
                 mutex_unlock(&priv->mutex);
                 return ret;
         }
 
-        ath_update_txpow(priv);
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
 
         mode = ath9k_htc_get_curmode(priv, init_channel);
         htc_mode = cpu_to_be16(mode);
@@ -1201,15 +941,29 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
 
         ath9k_host_rx_init(priv);
 
+        ret = ath9k_htc_update_cap_target(priv, 0);
+        if (ret)
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Failed to update capability in target\n");
+
         priv->op_flags &= ~OP_INVALID;
         htc_start(priv->htc);
 
-        spin_lock_bh(&priv->tx_lock);
-        priv->tx_queues_stop = false;
-        spin_unlock_bh(&priv->tx_lock);
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
+        spin_unlock_bh(&priv->tx.tx_lock);
 
         ieee80211_wake_queues(hw);
 
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
+
+        if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) {
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                           AR_STOMP_LOW_WLAN_WGHT);
+                ath9k_hw_btcoex_enable(ah);
+                ath_htc_resume_btcoex_work(priv);
+        }
         mutex_unlock(&priv->mutex);
 
         return ret;
@@ -1220,49 +974,60 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
         struct ath9k_htc_priv *priv = hw->priv;
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
-        int ret = 0;
+        int ret __attribute__ ((unused));
         u8 cmd_rsp;
 
         mutex_lock(&priv->mutex);
 
         if (priv->op_flags & OP_INVALID) {
-                ath_print(common, ATH_DBG_ANY, "Device not present\n");
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&priv->mutex);
                 return;
         }
 
-        /* Cancel all the running timers/work .. */
-        cancel_work_sync(&priv->ps_work);
-        cancel_delayed_work_sync(&priv->ath9k_ani_work);
-        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
-        ath9k_led_stop_brightness(priv);
-
         ath9k_htc_ps_wakeup(priv);
-        htc_stop(priv->htc);
+
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
         WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
         WMI_CMD(WMI_STOP_RECV_CMDID);
-        skb_queue_purge(&priv->tx_queue);
 
-        /* Remove monitor interface here */
-        if (ah->opmode == NL80211_IFTYPE_MONITOR) {
-                if (ath9k_htc_remove_monitor_interface(priv))
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to remove monitor interface\n");
-                else
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "Monitor interface removed\n");
+        tasklet_kill(&priv->rx_tasklet);
+
+        del_timer_sync(&priv->tx.cleanup_timer);
+        ath9k_htc_tx_drain(priv);
+        ath9k_wmi_event_drain(priv);
+
+        mutex_unlock(&priv->mutex);
+
+        /* Cancel all the running timers/work .. */
+        cancel_work_sync(&priv->fatal_work);
+        cancel_work_sync(&priv->ps_work);
+
+#ifdef CONFIG_MAC80211_LEDS
+        cancel_work_sync(&priv->led_work);
+#endif
+        ath9k_htc_stop_ani(priv);
+
+        mutex_lock(&priv->mutex);
+
+        if (ah->btcoex_hw.enabled) {
+                ath9k_hw_btcoex_disable(ah);
+                if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
+                        ath_htc_cancel_btcoex_work(priv);
         }
 
+        /* Remove a monitor interface if it's present. */
+        if (priv->ah->is_monitoring)
+                ath9k_htc_remove_monitor_interface(priv);
+
         ath9k_hw_phy_disable(ah);
         ath9k_hw_disable(ah);
-        ath9k_hw_configpcipowersave(ah, 1, 1);
         ath9k_htc_ps_restore(priv);
         ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
 
         priv->op_flags |= OP_INVALID;
 
-        ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
         mutex_unlock(&priv->mutex);
 }
 
@@ -1278,10 +1043,24 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
 
         mutex_lock(&priv->mutex);
 
-        /* Only one interface for now */
-        if (priv->nvifs > 0) {
-                ret = -ENOBUFS;
-                goto out;
+        if (priv->nvifs >= ATH9K_HTC_MAX_VIF) {
+                mutex_unlock(&priv->mutex);
+                return -ENOBUFS;
+        }
+
+        if (priv->num_ibss_vif ||
+            (priv->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
+                ath_err(common, "IBSS coexistence with other modes is not allowed\n");
+                mutex_unlock(&priv->mutex);
+                return -ENOBUFS;
+        }
+
+        if (((vif->type == NL80211_IFTYPE_AP) ||
+             (vif->type == NL80211_IFTYPE_ADHOC)) &&
+            ((priv->num_ap_vif + priv->num_ibss_vif) >= ATH9K_HTC_MAX_BCN_VIF)) {
+                ath_err(common, "Max. number of beaconing interfaces reached\n");
+                mutex_unlock(&priv->mutex);
+                return -ENOBUFS;
         }
 
         ath9k_htc_ps_wakeup(priv);
@@ -1290,46 +1069,60 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
 
         switch (vif->type) {
         case NL80211_IFTYPE_STATION:
-                hvif.opmode = cpu_to_be32(HTC_M_STA);
+                hvif.opmode = HTC_M_STA;
                 break;
         case NL80211_IFTYPE_ADHOC:
-                hvif.opmode = cpu_to_be32(HTC_M_IBSS);
+                hvif.opmode = HTC_M_IBSS;
+                break;
+        case NL80211_IFTYPE_AP:
+                hvif.opmode = HTC_M_HOSTAP;
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
+                ath_err(common,
                         "Interface type %d not yet supported\n", vif->type);
                 ret = -EOPNOTSUPP;
                 goto out;
         }
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Attach a VIF of type: %d\n", vif->type);
-
-        priv->ah->opmode = vif->type;
-
         /* Index starts from zero on the target */
-        avp->index = hvif.index = priv->nvifs;
+        avp->index = hvif.index = ffz(priv->vif_slot);
         hvif.rtsthreshold = cpu_to_be16(2304);
         WMI_CMD_BUF(WMI_VAP_CREATE_CMDID, &hvif);
         if (ret)
                 goto out;
 
-        priv->nvifs++;
-
         /*
          * We need a node in target to tx mgmt frames
          * before association.
          */
         ret = ath9k_htc_add_station(priv, vif, NULL);
-        if (ret)
+        if (ret) {
+                WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
                 goto out;
+        }
 
-        ret = ath9k_htc_update_cap_target(priv);
-        if (ret)
-                ath_print(common, ATH_DBG_CONFIG, "Failed to update"
-                          " capability in target \n");
+        ath9k_htc_set_bssid_mask(priv, vif);
+
+        priv->vif_slot |= (1 << avp->index);
+        priv->nvifs++;
+
+        INC_VIF(priv, vif->type);
+
+        if ((vif->type == NL80211_IFTYPE_AP) ||
+            (vif->type == NL80211_IFTYPE_ADHOC))
+                ath9k_htc_assign_bslot(priv, vif);
+
+        ath9k_htc_set_opmode(priv);
+
+        if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
+            !(priv->op_flags & OP_ANI_RUNNING)) {
+                ath9k_hw_set_tsfadjust(priv->ah, 1);
+                ath9k_htc_start_ani(priv);
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attach a VIF of type: %d at idx: %d\n", vif->type, avp->index);
 
-        priv->vif = vif;
 out:
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1347,8 +1140,6 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw,
         int ret = 0;
         u8 cmd_rsp;
 
-        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
-
         mutex_lock(&priv->mutex);
         ath9k_htc_ps_wakeup(priv);
 
@@ -1356,10 +1147,37 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw,
         memcpy(&hvif.myaddr, vif->addr, ETH_ALEN);
         hvif.index = avp->index;
         WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
+        if (ret) {
+                ath_err(common, "Unable to remove interface at idx: %d\n",
+                        avp->index);
+        }
         priv->nvifs--;
+        priv->vif_slot &= ~(1 << avp->index);
 
         ath9k_htc_remove_station(priv, vif, NULL);
-        priv->vif = NULL;
+
+        DEC_VIF(priv, vif->type);
+
+        if ((vif->type == NL80211_IFTYPE_AP) ||
+            (vif->type == NL80211_IFTYPE_ADHOC))
+                ath9k_htc_remove_bslot(priv, vif);
+
+        ath9k_htc_set_opmode(priv);
+
+        ath9k_htc_set_bssid_mask(priv, vif);
+
+        /*
+         * Stop ANI only if there are no associated station interfaces.
+         */
+        if ((vif->type == NL80211_IFTYPE_AP) && (priv->num_ap_vif == 0)) {
+                priv->rearm_ani = false;
+                ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                   ath9k_htc_vif_iter, priv);
+                if (!priv->rearm_ani)
+                        ath9k_htc_stop_ani(priv);
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface at idx: %d\n", avp->index);
 
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1384,30 +1202,44 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 mutex_unlock(&priv->htc_pm_lock);
 
                 if (enable_radio) {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "not-idle: enabling radio\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "not-idle: enabling radio\n");
                         ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
                         ath9k_htc_radio_enable(hw);
                 }
         }
 
+        /*
+         * Monitor interface should be added before
+         * IEEE80211_CONF_CHANGE_CHANNEL is handled.
+         */
+        if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
+                if ((conf->flags & IEEE80211_CONF_MONITOR) &&
+                    !priv->ah->is_monitoring)
+                        ath9k_htc_add_monitor_interface(priv);
+                else if (priv->ah->is_monitoring)
+                        ath9k_htc_remove_monitor_interface(priv);
+        }
+
         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
                 struct ieee80211_channel *curchan = hw->conf.channel;
                 int pos = curchan->hw_value;
 
-                ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
-                          curchan->center_freq);
+                ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
+                        curchan->center_freq);
 
-                ath9k_cmn_update_ichannel(hw, &priv->ah->channels[pos]);
+                ath9k_cmn_update_ichannel(&priv->ah->channels[pos],
+                                          hw->conf.channel,
+                                          hw->conf.channel_type);
 
                 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to set channel\n");
+                        ath_err(common, "Unable to set channel\n");
                         mutex_unlock(&priv->mutex);
                         return -EINVAL;
                 }
 
         }
+
         if (changed & IEEE80211_CONF_CHANGE_PS) {
                 if (conf->flags & IEEE80211_CONF_PS) {
                         ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
@@ -1419,15 +1251,10 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 }
         }
 
-        if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
-                if (conf->flags & IEEE80211_CONF_MONITOR) {
-                        if (ath9k_htc_add_monitor_interface(priv))
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Failed to set monitor mode\n");
-                        else
-                                ath_print(common, ATH_DBG_CONFIG,
-                                          "HW opmode set to Monitor mode\n");
-                }
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                priv->txpowlimit = 2 * conf->power_level;
+                ath9k_cmn_update_txpow(priv->ah, priv->curtxpow,
+                                       priv->txpowlimit, &priv->curtxpow);
         }
 
         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
@@ -1438,8 +1265,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 }
                 mutex_unlock(&priv->htc_pm_lock);
 
-                ath_print(common, ATH_DBG_CONFIG,
-                          "idle: disabling radio\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "idle: disabling radio\n");
                 ath9k_htc_radio_disable(hw);
         }
 
@@ -1455,6 +1282,7 @@ out:
         FIF_PSPOLL |                            \
         FIF_OTHER_BSS |                         \
         FIF_BCN_PRBRESP_PROMISC |               \
+        FIF_PROBE_REQ |                         \
         FIF_FCSFAIL)
 
 static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
@@ -1475,8 +1303,8 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
         rfilt = ath9k_htc_calcrxfilter(priv);
         ath9k_hw_setrxfilter(priv->ah, rfilt);
 
-        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
-                  "Set HW RX filter: 0x%x\n", rfilt);
+        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
+                "Set HW RX filter: 0x%x\n", rfilt);
 
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1505,10 +1333,13 @@ static int ath9k_htc_sta_remove(struct ieee80211_hw *hw,
                                 struct ieee80211_sta *sta)
 {
         struct ath9k_htc_priv *priv = hw->priv;
+        struct ath9k_htc_sta *ista;
         int ret;
 
         mutex_lock(&priv->mutex);
         ath9k_htc_ps_wakeup(priv);
+        ista = (struct ath9k_htc_sta *) sta->drv_priv;
+        htc_sta_drain(priv->htc, ista->index);
         ret = ath9k_htc_remove_station(priv, vif, sta);
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1539,15 +1370,14 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, u16 queue,
 
         qnum = get_hw_qnum(queue, priv->hwq_map);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Configure tx [queue/hwq] [%d/%d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, qnum, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Configure tx [queue/hwq] [%d/%d],  aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                queue, qnum, params->aifs, params->cw_min,
+                params->cw_max, params->txop);
 
         ret = ath_htc_txq_update(priv, qnum, &qi);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+                ath_err(common, "TXQ Update failed\n");
                 goto out;
         }
 
@@ -1575,25 +1405,26 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
                 return -ENOSPC;
 
         mutex_lock(&priv->mutex);
-        ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
         ath9k_htc_ps_wakeup(priv);
 
         switch (cmd) {
         case SET_KEY:
-                ret = ath9k_cmn_key_config(common, vif, sta, key);
+                ret = ath_key_config(common, vif, sta, key);
                 if (ret >= 0) {
                         key->hw_key_idx = ret;
                         /* push IV and Michael MIC generation to stack */
                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
-                        if (key->alg == ALG_TKIP)
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
-                        if (priv->ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
+                        if (priv->ah->sw_mgmt_crypto &&
+                            key->cipher == WLAN_CIPHER_SUITE_CCMP)
                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
                         ret = 0;
                 }
                 break;
         case DISABLE_KEY:
-                ath9k_cmn_key_delete(common, key);
+                ath_key_delete(common, key);
                 break;
         default:
                 ret = -EINVAL;
@@ -1605,6 +1436,37 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
         return ret;
 }
 
+static void ath9k_htc_set_bssid(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+
+        ath9k_hw_write_associd(priv->ah);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "BSSID: %pM aid: 0x%x\n",
+                common->curbssid, common->curaid);
+}
+
+static void ath9k_htc_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+
+        if ((vif->type == NL80211_IFTYPE_STATION) && bss_conf->assoc) {
+                common->curaid = bss_conf->aid;
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+        }
+}
+
+static void ath9k_htc_choose_set_bssid(struct ath9k_htc_priv *priv)
+{
+        if (priv->num_sta_assoc_vif == 1) {
+                ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                           ath9k_htc_bss_iter, priv);
+                ath9k_htc_set_bssid(priv);
+        }
+}
+
 static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
                                        struct ieee80211_vif *vif,
                                        struct ieee80211_bss_conf *bss_conf,
@@ -1618,61 +1480,66 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
         ath9k_htc_ps_wakeup(priv);
 
         if (changed & BSS_CHANGED_ASSOC) {
-                common->curaid = bss_conf->assoc ?
-                                 bss_conf->aid : 0;
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
                         bss_conf->assoc);
 
-                if (bss_conf->assoc) {
-                        priv->op_flags |= OP_ASSOCIATED;
-                        ath_start_ani(priv);
-                } else {
-                        priv->op_flags &= ~OP_ASSOCIATED;
-                        cancel_delayed_work_sync(&priv->ath9k_ani_work);
+                bss_conf->assoc ?
+                        priv->num_sta_assoc_vif++ : priv->num_sta_assoc_vif--;
+
+                if (priv->ah->opmode == NL80211_IFTYPE_STATION) {
+                        if (bss_conf->assoc && (priv->num_sta_assoc_vif == 1))
+                                ath9k_htc_start_ani(priv);
+                        else if (priv->num_sta_assoc_vif == 0)
+                                ath9k_htc_stop_ani(priv);
                 }
         }
 
         if (changed & BSS_CHANGED_BSSID) {
-                /* Set BSSID */
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                ath9k_hw_write_associd(ah);
-
-                ath_print(common, ATH_DBG_CONFIG,
-                          "BSSID: %pM aid: 0x%x\n",
-                          common->curbssid, common->curaid);
+                if (priv->ah->opmode == NL80211_IFTYPE_ADHOC) {
+                        common->curaid = bss_conf->aid;
+                        memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                        ath9k_htc_set_bssid(priv);
+                } else if (priv->ah->opmode == NL80211_IFTYPE_STATION) {
+                        ath9k_htc_choose_set_bssid(priv);
+                }
         }
 
-        if ((changed & BSS_CHANGED_BEACON_INT) ||
-            (changed & BSS_CHANGED_BEACON) ||
-            ((changed & BSS_CHANGED_BEACON_ENABLED) &&
-            bss_conf->enable_beacon)) {
+        if ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Beacon enabled for BSS: %pM\n", bss_conf->bssid);
+                ath9k_htc_set_tsfadjust(priv, vif);
                 priv->op_flags |= OP_ENABLE_BEACON;
                 ath9k_htc_beacon_config(priv, vif);
         }
 
-        if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
-            !bss_conf->enable_beacon) {
-                priv->op_flags &= ~OP_ENABLE_BEACON;
-                ath9k_htc_beacon_config(priv, vif);
-        }
-
-        if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
-                          bss_conf->use_short_preamble);
-                if (bss_conf->use_short_preamble)
-                        priv->op_flags |= OP_PREAMBLE_SHORT;
-                else
-                        priv->op_flags &= ~OP_PREAMBLE_SHORT;
+        if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) {
+                /*
+                 * Disable SWBA interrupt only if there are no
+                 * AP/IBSS interfaces.
+                 */
+                if ((priv->num_ap_vif <= 1) || priv->num_ibss_vif) {
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Beacon disabled for BSS: %pM\n",
+                                bss_conf->bssid);
+                        priv->op_flags &= ~OP_ENABLE_BEACON;
+                        ath9k_htc_beacon_config(priv, vif);
+                }
         }
 
-        if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
-                          bss_conf->use_cts_prot);
-                if (bss_conf->use_cts_prot &&
-                    hw->conf.channel->band != IEEE80211_BAND_5GHZ)
-                        priv->op_flags |= OP_PROTECT_ENABLE;
-                else
-                        priv->op_flags &= ~OP_PROTECT_ENABLE;
+        if (changed & BSS_CHANGED_BEACON_INT) {
+                /*
+                 * Reset the HW TSF for the first AP interface.
+                 */
+                if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
+                    (priv->nvifs == 1) &&
+                    (priv->num_ap_vif == 1) &&
+                    (vif->type == NL80211_IFTYPE_AP)) {
+                        priv->op_flags |= OP_TSF_RESET;
+                }
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Beacon interval changed for BSS: %pM\n",
+                        bss_conf->bssid);
+                ath9k_htc_beacon_config(priv, vif);
         }
 
         if (changed & BSS_CHANGED_ERP_SLOT) {
@@ -1731,12 +1598,15 @@ static int ath9k_htc_ampdu_action(struct ieee80211_hw *hw,
                                   struct ieee80211_vif *vif,
                                   enum ieee80211_ampdu_mlme_action action,
                                   struct ieee80211_sta *sta,
-                                  u16 tid, u16 *ssn)
+                                  u16 tid, u16 *ssn, u8 buf_size)
 {
         struct ath9k_htc_priv *priv = hw->priv;
         struct ath9k_htc_sta *ista;
         int ret = 0;
 
+        mutex_lock(&priv->mutex);
+        ath9k_htc_ps_wakeup(priv);
+
         switch (action) {
         case IEEE80211_AMPDU_RX_START:
                 break;
@@ -1753,15 +1623,17 @@ static int ath9k_htc_ampdu_action(struct ieee80211_hw *hw,
                 break;
         case IEEE80211_AMPDU_TX_OPERATIONAL:
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
-                spin_lock_bh(&priv->tx_lock);
+                spin_lock_bh(&priv->tx.tx_lock);
                 ista->tid_state[tid] = AGGR_OPERATIONAL;
-                spin_unlock_bh(&priv->tx_lock);
+                spin_unlock_bh(&priv->tx.tx_lock);
                 break;
         default:
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL,
-                          "Unknown AMPDU action\n");
+                ath_err(ath9k_hw_common(priv->ah), "Unknown AMPDU action\n");
         }
 
+        ath9k_htc_ps_restore(priv);
+        mutex_unlock(&priv->mutex);
+
         return ret;
 }
 
@@ -1774,7 +1646,7 @@ static void ath9k_htc_sw_scan_start(struct ieee80211_hw *hw)
         priv->op_flags |= OP_SCANNING;
         spin_unlock_bh(&priv->beacon_lock);
         cancel_work_sync(&priv->ps_work);
-        cancel_delayed_work_sync(&priv->ath9k_ani_work);
+        ath9k_htc_stop_ani(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -1783,14 +1655,11 @@ static void ath9k_htc_sw_scan_complete(struct ieee80211_hw *hw)
         struct ath9k_htc_priv *priv = hw->priv;
 
         mutex_lock(&priv->mutex);
-        ath9k_htc_ps_wakeup(priv);
         spin_lock_bh(&priv->beacon_lock);
         priv->op_flags &= ~OP_SCANNING;
         spin_unlock_bh(&priv->beacon_lock);
-        priv->op_flags |= OP_FULL_RESET;
-        if (priv->op_flags & OP_ASSOCIATED)
-                ath9k_htc_beacon_config(priv, priv->vif);
-        ath_start_ani(priv);
+        ath9k_htc_ps_wakeup(priv);
+        ath9k_htc_vif_reconfig(priv);
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
 }
@@ -1813,6 +1682,55 @@ static void ath9k_htc_set_coverage_class(struct ieee80211_hw *hw,
         mutex_unlock(&priv->mutex);
 }
 
+/*
+ * Currently, this is used only for selecting the minimum rate
+ * for management frames, rate selection for data frames remain
+ * unaffected.
+ */
+static int ath9k_htc_set_bitrate_mask(struct ieee80211_hw *hw,
+                                      struct ieee80211_vif *vif,
+                                      const struct cfg80211_bitrate_mask *mask)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_target_rate_mask tmask;
+        struct ath9k_htc_vif *avp = (void *)vif->drv_priv;
+        int ret = 0;
+        u8 cmd_rsp;
+
+        memset(&tmask, 0, sizeof(struct ath9k_htc_target_rate_mask));
+
+        tmask.vif_index = avp->index;
+        tmask.band = IEEE80211_BAND_2GHZ;
+        tmask.mask = cpu_to_be32(mask->control[IEEE80211_BAND_2GHZ].legacy);
+
+        WMI_CMD_BUF(WMI_BITRATE_MASK_CMDID, &tmask);
+        if (ret) {
+                ath_err(common,
+                        "Unable to set 2G rate mask for "
+                        "interface at idx: %d\n", avp->index);
+                goto out;
+        }
+
+        tmask.band = IEEE80211_BAND_5GHZ;
+        tmask.mask = cpu_to_be32(mask->control[IEEE80211_BAND_5GHZ].legacy);
+
+        WMI_CMD_BUF(WMI_BITRATE_MASK_CMDID, &tmask);
+        if (ret) {
+                ath_err(common,
+                        "Unable to set 5G rate mask for "
+                        "interface at idx: %d\n", avp->index);
+                goto out;
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Set bitrate masks: 0x%x, 0x%x\n",
+                mask->control[IEEE80211_BAND_2GHZ].legacy,
+                mask->control[IEEE80211_BAND_5GHZ].legacy);
+out:
+        return ret;
+}
+
 struct ieee80211_ops ath9k_htc_ops = {
         .tx                 = ath9k_htc_tx,
         .start              = ath9k_htc_start,
@@ -1835,4 +1753,5 @@ struct ieee80211_ops ath9k_htc_ops = {
         .set_rts_threshold  = ath9k_htc_set_rts_threshold,
         .rfkill_poll        = ath9k_htc_rfkill_poll_state,
         .set_coverage_class = ath9k_htc_set_coverage_class,
+        .set_bitrate_mask   = ath9k_htc_set_bitrate_mask,
 };
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 2a6e45a293a9..2d81c700e201 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,8 +20,15 @@
 /* TX */
 /******/
 
+static const int subtype_txq_to_hwq[] = {
+        [WME_AC_BE] = ATH_TXQ_AC_BE,
+        [WME_AC_BK] = ATH_TXQ_AC_BK,
+        [WME_AC_VI] = ATH_TXQ_AC_VI,
+        [WME_AC_VO] = ATH_TXQ_AC_VO,
+};
+
 #define ATH9K_HTC_INIT_TXQ(subtype) do {                        \
-                qi.tqi_subtype = subtype;                       \
+                qi.tqi_subtype = subtype_txq_to_hwq[subtype];   \
                 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;             \
                 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;            \
                 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;            \
@@ -46,6 +53,138 @@ int get_hw_qnum(u16 queue, int *hwq_map)
         }
 }
 
+void ath9k_htc_check_stop_queues(struct ath9k_htc_priv *priv)
+{
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.queued_cnt++;
+        if ((priv->tx.queued_cnt >= ATH9K_HTC_TX_THRESHOLD) &&
+            !(priv->tx.flags & ATH9K_HTC_OP_TX_QUEUES_STOP)) {
+                priv->tx.flags |= ATH9K_HTC_OP_TX_QUEUES_STOP;
+                ieee80211_stop_queues(priv->hw);
+        }
+        spin_unlock_bh(&priv->tx.tx_lock);
+}
+
+void ath9k_htc_check_wake_queues(struct ath9k_htc_priv *priv)
+{
+        spin_lock_bh(&priv->tx.tx_lock);
+        if ((priv->tx.queued_cnt < ATH9K_HTC_TX_THRESHOLD) &&
+            (priv->tx.flags & ATH9K_HTC_OP_TX_QUEUES_STOP)) {
+                priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
+                ieee80211_wake_queues(priv->hw);
+        }
+        spin_unlock_bh(&priv->tx.tx_lock);
+}
+
+int ath9k_htc_tx_get_slot(struct ath9k_htc_priv *priv)
+{
+        int slot;
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        slot = find_first_zero_bit(priv->tx.tx_slot, MAX_TX_BUF_NUM);
+        if (slot >= MAX_TX_BUF_NUM) {
+                spin_unlock_bh(&priv->tx.tx_lock);
+                return -ENOBUFS;
+        }
+        __set_bit(slot, priv->tx.tx_slot);
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        return slot;
+}
+
+void ath9k_htc_tx_clear_slot(struct ath9k_htc_priv *priv, int slot)
+{
+        spin_lock_bh(&priv->tx.tx_lock);
+        __clear_bit(slot, priv->tx.tx_slot);
+        spin_unlock_bh(&priv->tx.tx_lock);
+}
+
+static inline enum htc_endpoint_id get_htc_epid(struct ath9k_htc_priv *priv,
+                                                u16 qnum)
+{
+        enum htc_endpoint_id epid;
+
+        switch (qnum) {
+        case 0:
+                TX_QSTAT_INC(WME_AC_VO);
+                epid = priv->data_vo_ep;
+                break;
+        case 1:
+                TX_QSTAT_INC(WME_AC_VI);
+                epid = priv->data_vi_ep;
+                break;
+        case 2:
+                TX_QSTAT_INC(WME_AC_BE);
+                epid = priv->data_be_ep;
+                break;
+        case 3:
+        default:
+                TX_QSTAT_INC(WME_AC_BK);
+                epid = priv->data_bk_ep;
+                break;
+        }
+
+        return epid;
+}
+
+static inline struct sk_buff_head*
+get_htc_epid_queue(struct ath9k_htc_priv *priv, u8 epid)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct sk_buff_head *epid_queue = NULL;
+
+        if (epid == priv->mgmt_ep)
+                epid_queue = &priv->tx.mgmt_ep_queue;
+        else if (epid == priv->cab_ep)
+                epid_queue = &priv->tx.cab_ep_queue;
+        else if (epid == priv->data_be_ep)
+                epid_queue = &priv->tx.data_be_queue;
+        else if (epid == priv->data_bk_ep)
+                epid_queue = &priv->tx.data_bk_queue;
+        else if (epid == priv->data_vi_ep)
+                epid_queue = &priv->tx.data_vi_queue;
+        else if (epid == priv->data_vo_ep)
+                epid_queue = &priv->tx.data_vo_queue;
+        else
+                ath_err(common, "Invalid EPID: %d\n", epid);
+
+        return epid_queue;
+}
+
+/*
+ * Removes the driver header and returns the TX slot number
+ */
+static inline int strip_drv_header(struct ath9k_htc_priv *priv,
+                                   struct sk_buff *skb)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        int slot;
+
+        tx_ctl = HTC_SKB_CB(skb);
+
+        if (tx_ctl->epid == priv->mgmt_ep) {
+                struct tx_mgmt_hdr *tx_mhdr =
+                        (struct tx_mgmt_hdr *)skb->data;
+                slot = tx_mhdr->cookie;
+                skb_pull(skb, sizeof(struct tx_mgmt_hdr));
+        } else if ((tx_ctl->epid == priv->data_bk_ep) ||
+                   (tx_ctl->epid == priv->data_be_ep) ||
+                   (tx_ctl->epid == priv->data_vi_ep) ||
+                   (tx_ctl->epid == priv->data_vo_ep) ||
+                   (tx_ctl->epid == priv->cab_ep)) {
+                struct tx_frame_hdr *tx_fhdr =
+                        (struct tx_frame_hdr *)skb->data;
+                slot = tx_fhdr->cookie;
+                skb_pull(skb, sizeof(struct tx_frame_hdr));
+        } else {
+                ath_err(common, "Unsupported EPID: %d\n", tx_ctl->epid);
+                slot = -EINVAL;
+        }
+
+        return slot;
+}
+
 int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
                        struct ath9k_tx_queue_info *qinfo)
 {
@@ -62,8 +201,8 @@ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
         qi.tqi_readyTime = qinfo->tqi_readyTime;
 
         if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unable to update hardware queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(ah),
+                        "Unable to update hardware queue %u!\n", qnum);
                 error = -EIO;
         } else {
                 ath9k_hw_resettxqueue(ah, qnum);
@@ -72,241 +211,592 @@ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
         return error;
 }
 
-int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, struct sk_buff *skb)
+static void ath9k_htc_tx_mgmt(struct ath9k_htc_priv *priv,
+                              struct ath9k_htc_vif *avp,
+                              struct sk_buff *skb,
+                              u8 sta_idx, u8 vif_idx, u8 slot)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_mgmt *mgmt;
+        struct ieee80211_hdr *hdr;
+        struct tx_mgmt_hdr mgmt_hdr;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        u8 *tx_fhdr;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        hdr = (struct ieee80211_hdr *) skb->data;
+
+        memset(tx_ctl, 0, sizeof(*tx_ctl));
+        memset(&mgmt_hdr, 0, sizeof(struct tx_mgmt_hdr));
+
+        /*
+         * Set the TSF adjust value for probe response
+         * frame also.
+         */
+        if (avp && unlikely(ieee80211_is_probe_resp(hdr->frame_control))) {
+                mgmt = (struct ieee80211_mgmt *)skb->data;
+                mgmt->u.probe_resp.timestamp = avp->tsfadjust;
+        }
+
+        tx_ctl->type = ATH9K_HTC_MGMT;
+
+        mgmt_hdr.node_idx = sta_idx;
+        mgmt_hdr.vif_idx = vif_idx;
+        mgmt_hdr.tidno = 0;
+        mgmt_hdr.flags = 0;
+        mgmt_hdr.cookie = slot;
+
+        mgmt_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
+        if (mgmt_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
+                mgmt_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
+        else
+                mgmt_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+
+        tx_fhdr = skb_push(skb, sizeof(mgmt_hdr));
+        memcpy(tx_fhdr, (u8 *) &mgmt_hdr, sizeof(mgmt_hdr));
+        tx_ctl->epid = priv->mgmt_ep;
+}
+
+static void ath9k_htc_tx_data(struct ath9k_htc_priv *priv,
+                              struct ieee80211_vif *vif,
+                              struct sk_buff *skb,
+                              u8 sta_idx, u8 vif_idx, u8 slot,
+                              bool is_cab)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_hdr *hdr;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        struct tx_frame_hdr tx_hdr;
+        u32 flags = 0;
+        u8 *qc, *tx_fhdr;
+        u16 qnum;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        hdr = (struct ieee80211_hdr *) skb->data;
+
+        memset(tx_ctl, 0, sizeof(*tx_ctl));
+        memset(&tx_hdr, 0, sizeof(struct tx_frame_hdr));
+
+        tx_hdr.node_idx = sta_idx;
+        tx_hdr.vif_idx = vif_idx;
+        tx_hdr.cookie = slot;
+
+        /*
+         * This is a bit redundant but it helps to get
+         * the per-packet index quickly when draining the
+         * TX queue in the HIF layer. Otherwise we would
+         * have to parse the packet contents ...
+         */
+        tx_ctl->sta_idx = sta_idx;
+
+        if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+                tx_ctl->type = ATH9K_HTC_AMPDU;
+                tx_hdr.data_type = ATH9K_HTC_AMPDU;
+        } else {
+                tx_ctl->type = ATH9K_HTC_NORMAL;
+                tx_hdr.data_type = ATH9K_HTC_NORMAL;
+        }
+
+        if (ieee80211_is_data_qos(hdr->frame_control)) {
+                qc = ieee80211_get_qos_ctl(hdr);
+                tx_hdr.tidno = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
+        }
+
+        /* Check for RTS protection */
+        if (priv->hw->wiphy->rts_threshold != (u32) -1)
+                if (skb->len > priv->hw->wiphy->rts_threshold)
+                        flags |= ATH9K_HTC_TX_RTSCTS;
+
+        /* CTS-to-self */
+        if (!(flags & ATH9K_HTC_TX_RTSCTS) &&
+            (vif && vif->bss_conf.use_cts_prot))
+                flags |= ATH9K_HTC_TX_CTSONLY;
+
+        tx_hdr.flags = cpu_to_be32(flags);
+        tx_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
+        if (tx_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
+                tx_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
+        else
+                tx_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+
+        tx_fhdr = skb_push(skb, sizeof(tx_hdr));
+        memcpy(tx_fhdr, (u8 *) &tx_hdr, sizeof(tx_hdr));
+
+        if (is_cab) {
+                CAB_STAT_INC;
+                tx_ctl->epid = priv->cab_ep;
+                return;
+        }
+
+        qnum = skb_get_queue_mapping(skb);
+        tx_ctl->epid = get_htc_epid(priv, qnum);
+}
+
+int ath9k_htc_tx_start(struct ath9k_htc_priv *priv,
+                       struct sk_buff *skb,
+                       u8 slot, bool is_cab)
 {
         struct ieee80211_hdr *hdr;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         struct ieee80211_sta *sta = tx_info->control.sta;
+        struct ieee80211_vif *vif = tx_info->control.vif;
         struct ath9k_htc_sta *ista;
-        struct ath9k_htc_tx_ctl tx_ctl;
-        enum htc_endpoint_id epid;
-        u16 qnum;
-        __le16 fc;
-        u8 *tx_fhdr;
+        struct ath9k_htc_vif *avp = NULL;
         u8 sta_idx, vif_idx;
 
         hdr = (struct ieee80211_hdr *) skb->data;
-        fc = hdr->frame_control;
 
-        if (tx_info->control.vif &&
-                        (struct ath9k_htc_vif *) tx_info->control.vif->drv_priv)
-                vif_idx = ((struct ath9k_htc_vif *)
-                                tx_info->control.vif->drv_priv)->index;
-        else
-                vif_idx = priv->nvifs;
+        /*
+         * Find out on which interface this packet has to be
+         * sent out.
+         */
+        if (vif) {
+                avp = (struct ath9k_htc_vif *) vif->drv_priv;
+                vif_idx = avp->index;
+        } else {
+                if (!priv->ah->is_monitoring) {
+                        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
+                                "VIF is null, but no monitor interface !\n");
+                        return -EINVAL;
+                }
+
+                vif_idx = priv->mon_vif_idx;
+        }
 
+        /*
+         * Find out which station this packet is destined for.
+         */
         if (sta) {
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
                 sta_idx = ista->index;
         } else {
-                sta_idx = 0;
+                sta_idx = priv->vif_sta_pos[vif_idx];
         }
 
-        memset(&tx_ctl, 0, sizeof(struct ath9k_htc_tx_ctl));
+        if (ieee80211_is_data(hdr->frame_control))
+                ath9k_htc_tx_data(priv, vif, skb,
+                                  sta_idx, vif_idx, slot, is_cab);
+        else
+                ath9k_htc_tx_mgmt(priv, avp, skb,
+                                  sta_idx, vif_idx, slot);
 
-        if (ieee80211_is_data(fc)) {
-                struct tx_frame_hdr tx_hdr;
-                u8 *qc;
 
-                memset(&tx_hdr, 0, sizeof(struct tx_frame_hdr));
+        return htc_send(priv->htc, skb);
+}
 
-                tx_hdr.node_idx = sta_idx;
-                tx_hdr.vif_idx = vif_idx;
+static inline bool __ath9k_htc_check_tx_aggr(struct ath9k_htc_priv *priv,
+                                             struct ath9k_htc_sta *ista, u8 tid)
+{
+        bool ret = false;
 
-                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
-                        tx_ctl.type = ATH9K_HTC_AMPDU;
-                        tx_hdr.data_type = ATH9K_HTC_AMPDU;
-                } else {
-                        tx_ctl.type = ATH9K_HTC_NORMAL;
-                        tx_hdr.data_type = ATH9K_HTC_NORMAL;
-                }
+        spin_lock_bh(&priv->tx.tx_lock);
+        if ((tid < ATH9K_HTC_MAX_TID) && (ista->tid_state[tid] == AGGR_STOP))
+                ret = true;
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        return ret;
+}
+
+static void ath9k_htc_check_tx_aggr(struct ath9k_htc_priv *priv,
+                                    struct ieee80211_vif *vif,
+                                    struct sk_buff *skb)
+{
+        struct ieee80211_sta *sta;
+        struct ieee80211_hdr *hdr;
+        __le16 fc;
+
+        hdr = (struct ieee80211_hdr *) skb->data;
+        fc = hdr->frame_control;
+
+        rcu_read_lock();
+
+        sta = ieee80211_find_sta(vif, hdr->addr1);
+        if (!sta) {
+                rcu_read_unlock();
+                return;
+        }
+
+        if (sta && conf_is_ht(&priv->hw->conf) &&
+            !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
+                if (ieee80211_is_data_qos(fc)) {
+                        u8 *qc, tid;
+                        struct ath9k_htc_sta *ista;
 
-                if (ieee80211_is_data(fc)) {
                         qc = ieee80211_get_qos_ctl(hdr);
-                        tx_hdr.tidno = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
+                        tid = qc[0] & 0xf;
+                        ista = (struct ath9k_htc_sta *)sta->drv_priv;
+                        if (__ath9k_htc_check_tx_aggr(priv, ista, tid)) {
+                                ieee80211_start_tx_ba_session(sta, tid, 0);
+                                spin_lock_bh(&priv->tx.tx_lock);
+                                ista->tid_state[tid] = AGGR_PROGRESS;
+                                spin_unlock_bh(&priv->tx.tx_lock);
+                        }
                 }
+        }
 
-                /* Check for RTS protection */
-                if (priv->hw->wiphy->rts_threshold != (u32) -1)
-                        if (skb->len > priv->hw->wiphy->rts_threshold)
-                                tx_hdr.flags |= ATH9K_HTC_TX_RTSCTS;
+        rcu_read_unlock();
+}
 
-                /* CTS-to-self */
-                if (!(tx_hdr.flags & ATH9K_HTC_TX_RTSCTS) &&
-                    (priv->op_flags & OP_PROTECT_ENABLE))
-                        tx_hdr.flags |= ATH9K_HTC_TX_CTSONLY;
+static void ath9k_htc_tx_process(struct ath9k_htc_priv *priv,
+                                 struct sk_buff *skb,
+                                 struct __wmi_event_txstatus *txs)
+{
+        struct ieee80211_vif *vif;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        struct ieee80211_tx_info *tx_info;
+        struct ieee80211_tx_rate *rate;
+        struct ieee80211_conf *cur_conf = &priv->hw->conf;
+        bool txok;
+        int slot;
 
-                tx_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
-                if (tx_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
-                        tx_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
-                else
-                        tx_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+        slot = strip_drv_header(priv, skb);
+        if (slot < 0) {
+                dev_kfree_skb_any(skb);
+                return;
+        }
 
-                tx_fhdr = skb_push(skb, sizeof(tx_hdr));
-                memcpy(tx_fhdr, (u8 *) &tx_hdr, sizeof(tx_hdr));
+        tx_ctl = HTC_SKB_CB(skb);
+        txok = tx_ctl->txok;
+        tx_info = IEEE80211_SKB_CB(skb);
+        vif = tx_info->control.vif;
+        rate = &tx_info->status.rates[0];
 
-                qnum = skb_get_queue_mapping(skb);
+        memset(&tx_info->status, 0, sizeof(tx_info->status));
 
-                switch (qnum) {
-                case 0:
-                        TX_QSTAT_INC(WME_AC_VO);
-                        epid = priv->data_vo_ep;
-                        break;
-                case 1:
-                        TX_QSTAT_INC(WME_AC_VI);
-                        epid = priv->data_vi_ep;
-                        break;
-                case 2:
-                        TX_QSTAT_INC(WME_AC_BE);
-                        epid = priv->data_be_ep;
-                        break;
-                case 3:
-                default:
-                        TX_QSTAT_INC(WME_AC_BK);
-                        epid = priv->data_bk_ep;
-                        break;
-                }
-        } else {
-                struct tx_mgmt_hdr mgmt_hdr;
+        /*
+         * URB submission failed for this frame, it never reached
+         * the target.
+         */
+        if (!txok || !vif || !txs)
+                goto send_mac80211;
+
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_ACK)
+                tx_info->flags |= IEEE80211_TX_STAT_ACK;
 
-                memset(&mgmt_hdr, 0, sizeof(struct tx_mgmt_hdr));
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_FILT)
+                tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
 
-                tx_ctl.type = ATH9K_HTC_NORMAL;
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_RTC_CTS)
+                rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
 
-                mgmt_hdr.node_idx = sta_idx;
-                mgmt_hdr.vif_idx = vif_idx;
-                mgmt_hdr.tidno = 0;
-                mgmt_hdr.flags = 0;
+        rate->count = 1;
+        rate->idx = MS(txs->ts_rate, ATH9K_HTC_TXSTAT_RATE);
 
-                mgmt_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
-                if (mgmt_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
-                        mgmt_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
-                else
-                        mgmt_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_MCS) {
+                rate->flags |= IEEE80211_TX_RC_MCS;
 
-                tx_fhdr = skb_push(skb, sizeof(mgmt_hdr));
-                memcpy(tx_fhdr, (u8 *) &mgmt_hdr, sizeof(mgmt_hdr));
-                epid = priv->mgmt_ep;
+                if (txs->ts_flags & ATH9K_HTC_TXSTAT_CW40)
+                        rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
+                if (txs->ts_flags & ATH9K_HTC_TXSTAT_SGI)
+                        rate->flags |= IEEE80211_TX_RC_SHORT_GI;
+        } else {
+                if (cur_conf->channel->band == IEEE80211_BAND_5GHZ)
+                        rate->idx += 4; /* No CCK rates */
         }
 
-        return htc_send(priv->htc, skb, epid, &tx_ctl);
+        ath9k_htc_check_tx_aggr(priv, vif, skb);
+
+send_mac80211:
+        spin_lock_bh(&priv->tx.tx_lock);
+        if (WARN_ON(--priv->tx.queued_cnt < 0))
+                priv->tx.queued_cnt = 0;
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        ath9k_htc_tx_clear_slot(priv, slot);
+
+        /* Send status to mac80211 */
+        ieee80211_tx_status(priv->hw, skb);
 }
 
-static bool ath9k_htc_check_tx_aggr(struct ath9k_htc_priv *priv,
-                                    struct ath9k_htc_sta *ista, u8 tid)
+static inline void ath9k_htc_tx_drainq(struct ath9k_htc_priv *priv,
+                                       struct sk_buff_head *queue)
 {
-        bool ret = false;
+        struct sk_buff *skb;
 
-        spin_lock_bh(&priv->tx_lock);
-        if ((tid < ATH9K_HTC_MAX_TID) && (ista->tid_state[tid] == AGGR_STOP))
-                ret = true;
-        spin_unlock_bh(&priv->tx_lock);
+        while ((skb = skb_dequeue(queue)) != NULL) {
+                ath9k_htc_tx_process(priv, skb, NULL);
+        }
+}
 
-        return ret;
+void ath9k_htc_tx_drain(struct ath9k_htc_priv *priv)
+{
+        struct ath9k_htc_tx_event *event, *tmp;
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags |= ATH9K_HTC_OP_TX_DRAIN;
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        /*
+         * Ensure that all pending TX frames are flushed,
+         * and that the TX completion/failed tasklets is killed.
+         */
+        htc_stop(priv->htc);
+        tasklet_kill(&priv->wmi->wmi_event_tasklet);
+        tasklet_kill(&priv->tx_failed_tasklet);
+
+        ath9k_htc_tx_drainq(priv, &priv->tx.mgmt_ep_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.cab_ep_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_be_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_bk_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_vi_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_vo_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.tx_failed);
+
+        /*
+         * The TX cleanup timer has already been killed.
+         */
+        spin_lock_bh(&priv->wmi->event_lock);
+        list_for_each_entry_safe(event, tmp, &priv->wmi->pending_tx_events, list) {
+                list_del(&event->list);
+                kfree(event);
+        }
+        spin_unlock_bh(&priv->wmi->event_lock);
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags &= ~ATH9K_HTC_OP_TX_DRAIN;
+        spin_unlock_bh(&priv->tx.tx_lock);
 }
 
-void ath9k_tx_tasklet(unsigned long data)
+void ath9k_tx_failed_tasklet(unsigned long data)
 {
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
-        struct ieee80211_sta *sta;
-        struct ieee80211_hdr *hdr;
-        struct ieee80211_tx_info *tx_info;
-        struct sk_buff *skb = NULL;
-        __le16 fc;
 
-        while ((skb = skb_dequeue(&priv->tx_queue)) != NULL) {
+        spin_lock_bh(&priv->tx.tx_lock);
+        if (priv->tx.flags & ATH9K_HTC_OP_TX_DRAIN) {
+                spin_unlock_bh(&priv->tx.tx_lock);
+                return;
+        }
+        spin_unlock_bh(&priv->tx.tx_lock);
 
-                hdr = (struct ieee80211_hdr *) skb->data;
-                fc = hdr->frame_control;
-                tx_info = IEEE80211_SKB_CB(skb);
+        ath9k_htc_tx_drainq(priv, &priv->tx.tx_failed);
+}
 
-                memset(&tx_info->status, 0, sizeof(tx_info->status));
+static inline bool check_cookie(struct ath9k_htc_priv *priv,
+                                struct sk_buff *skb,
+                                u8 cookie, u8 epid)
+{
+        u8 fcookie = 0;
+
+        if (epid == priv->mgmt_ep) {
+                struct tx_mgmt_hdr *hdr;
+                hdr = (struct tx_mgmt_hdr *) skb->data;
+                fcookie = hdr->cookie;
+        } else if ((epid == priv->data_bk_ep) ||
+                   (epid == priv->data_be_ep) ||
+                   (epid == priv->data_vi_ep) ||
+                   (epid == priv->data_vo_ep) ||
+                   (epid == priv->cab_ep)) {
+                struct tx_frame_hdr *hdr;
+                hdr = (struct tx_frame_hdr *) skb->data;
+                fcookie = hdr->cookie;
+        }
 
-                rcu_read_lock();
+        if (fcookie == cookie)
+                return true;
 
-                sta = ieee80211_find_sta(priv->vif, hdr->addr1);
-                if (!sta) {
-                        rcu_read_unlock();
-                        ieee80211_tx_status(priv->hw, skb);
-                        continue;
+        return false;
+}
+
+static struct sk_buff* ath9k_htc_tx_get_packet(struct ath9k_htc_priv *priv,
+                                               struct __wmi_event_txstatus *txs)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct sk_buff_head *epid_queue;
+        struct sk_buff *skb, *tmp;
+        unsigned long flags;
+        u8 epid = MS(txs->ts_rate, ATH9K_HTC_TXSTAT_EPID);
+
+        epid_queue = get_htc_epid_queue(priv, epid);
+        if (!epid_queue)
+                return NULL;
+
+        spin_lock_irqsave(&epid_queue->lock, flags);
+        skb_queue_walk_safe(epid_queue, skb, tmp) {
+                if (check_cookie(priv, skb, txs->cookie, epid)) {
+                        __skb_unlink(skb, epid_queue);
+                        spin_unlock_irqrestore(&epid_queue->lock, flags);
+                        return skb;
                 }
+        }
+        spin_unlock_irqrestore(&epid_queue->lock, flags);
 
-                /* Check if we need to start aggregation */
+        ath_dbg(common, ATH_DBG_XMIT,
+                "No matching packet for cookie: %d, epid: %d\n",
+                txs->cookie, epid);
 
-                if (sta && conf_is_ht(&priv->hw->conf) &&
-                    !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
-                        if (ieee80211_is_data_qos(fc)) {
-                                u8 *qc, tid;
-                                struct ath9k_htc_sta *ista;
+        return NULL;
+}
 
-                                qc = ieee80211_get_qos_ctl(hdr);
-                                tid = qc[0] & 0xf;
-                                ista = (struct ath9k_htc_sta *)sta->drv_priv;
+void ath9k_htc_txstatus(struct ath9k_htc_priv *priv, void *wmi_event)
+{
+        struct wmi_event_txstatus *txs = (struct wmi_event_txstatus *)wmi_event;
+        struct __wmi_event_txstatus *__txs;
+        struct sk_buff *skb;
+        struct ath9k_htc_tx_event *tx_pend;
+        int i;
 
-                                if (ath9k_htc_check_tx_aggr(priv, ista, tid)) {
-                                        ieee80211_start_tx_ba_session(sta, tid);
-                                        spin_lock_bh(&priv->tx_lock);
-                                        ista->tid_state[tid] = AGGR_PROGRESS;
-                                        spin_unlock_bh(&priv->tx_lock);
-                                }
-                        }
-                }
+        for (i = 0; i < txs->cnt; i++) {
+                WARN_ON(txs->cnt > HTC_MAX_TX_STATUS);
 
-                rcu_read_unlock();
+                __txs = &txs->txstatus[i];
+
+                skb = ath9k_htc_tx_get_packet(priv, __txs);
+                if (!skb) {
+                        /*
+                         * Store this event, so that the TX cleanup
+                         * routine can check later for the needed packet.
+                         */
+                        tx_pend = kzalloc(sizeof(struct ath9k_htc_tx_event),
+                                          GFP_ATOMIC);
+                        if (!tx_pend)
+                                continue;
+
+                        memcpy(&tx_pend->txs, __txs,
+                               sizeof(struct __wmi_event_txstatus));
 
-                /* Send status to mac80211 */
-                ieee80211_tx_status(priv->hw, skb);
+                        spin_lock(&priv->wmi->event_lock);
+                        list_add_tail(&tx_pend->list,
+                                      &priv->wmi->pending_tx_events);
+                        spin_unlock(&priv->wmi->event_lock);
+
+                        continue;
+                }
+
+                ath9k_htc_tx_process(priv, skb, __txs);
         }
 
         /* Wake TX queues if needed */
-        spin_lock_bh(&priv->tx_lock);
-        if (priv->tx_queues_stop) {
-                priv->tx_queues_stop = false;
-                spin_unlock_bh(&priv->tx_lock);
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                          "Waking up TX queues\n");
-                ieee80211_wake_queues(priv->hw);
-                return;
-        }
-        spin_unlock_bh(&priv->tx_lock);
+        ath9k_htc_check_wake_queues(priv);
 }
 
 void ath9k_htc_txep(void *drv_priv, struct sk_buff *skb,
                     enum htc_endpoint_id ep_id, bool txok)
 {
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) drv_priv;
-        struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct ieee80211_tx_info *tx_info;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        struct sk_buff_head *epid_queue;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        tx_ctl->txok = txok;
+        tx_ctl->timestamp = jiffies;
 
-        if (!skb)
+        if (!txok) {
+                skb_queue_tail(&priv->tx.tx_failed, skb);
+                tasklet_schedule(&priv->tx_failed_tasklet);
                 return;
+        }
 
-        if (ep_id == priv->mgmt_ep) {
-                skb_pull(skb, sizeof(struct tx_mgmt_hdr));
-        } else if ((ep_id == priv->data_bk_ep) ||
-                   (ep_id == priv->data_be_ep) ||
-                   (ep_id == priv->data_vi_ep) ||
-                   (ep_id == priv->data_vo_ep)) {
-                skb_pull(skb, sizeof(struct tx_frame_hdr));
-        } else {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unsupported TX EPID: %d\n", ep_id);
+        epid_queue = get_htc_epid_queue(priv, ep_id);
+        if (!epid_queue) {
                 dev_kfree_skb_any(skb);
                 return;
         }
 
-        tx_info = IEEE80211_SKB_CB(skb);
+        skb_queue_tail(epid_queue, skb);
+}
 
-        if (txok)
-                tx_info->flags |= IEEE80211_TX_STAT_ACK;
+static inline bool check_packet(struct ath9k_htc_priv *priv, struct sk_buff *skb)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_tx_ctl *tx_ctl;
+
+        tx_ctl = HTC_SKB_CB(skb);
+
+        if (time_after(jiffies,
+                       tx_ctl->timestamp +
+                       msecs_to_jiffies(ATH9K_HTC_TX_TIMEOUT_INTERVAL))) {
+                ath_dbg(common, ATH_DBG_XMIT,
+                        "Dropping a packet due to TX timeout\n");
+                return true;
+        }
 
-        skb_queue_tail(&priv->tx_queue, skb);
-        tasklet_schedule(&priv->tx_tasklet);
+        return false;
+}
+
+static void ath9k_htc_tx_cleanup_queue(struct ath9k_htc_priv *priv,
+                                       struct sk_buff_head *epid_queue)
+{
+        bool process = false;
+        unsigned long flags;
+        struct sk_buff *skb, *tmp;
+        struct sk_buff_head queue;
+
+        skb_queue_head_init(&queue);
+
+        spin_lock_irqsave(&epid_queue->lock, flags);
+        skb_queue_walk_safe(epid_queue, skb, tmp) {
+                if (check_packet(priv, skb)) {
+                        __skb_unlink(skb, epid_queue);
+                        __skb_queue_tail(&queue, skb);
+                        process = true;
+                }
+        }
+        spin_unlock_irqrestore(&epid_queue->lock, flags);
+
+        if (process) {
+                skb_queue_walk_safe(&queue, skb, tmp) {
+                        __skb_unlink(skb, &queue);
+                        ath9k_htc_tx_process(priv, skb, NULL);
+                }
+        }
+}
+
+void ath9k_htc_tx_cleanup_timer(unsigned long data)
+{
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_tx_event *event, *tmp;
+        struct sk_buff *skb;
+
+        spin_lock(&priv->wmi->event_lock);
+        list_for_each_entry_safe(event, tmp, &priv->wmi->pending_tx_events, list) {
+
+                skb = ath9k_htc_tx_get_packet(priv, &event->txs);
+                if (skb) {
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Found packet for cookie: %d, epid: %d\n",
+                                event->txs.cookie,
+                                MS(event->txs.ts_rate, ATH9K_HTC_TXSTAT_EPID));
+
+                        ath9k_htc_tx_process(priv, skb, &event->txs);
+                        list_del(&event->list);
+                        kfree(event);
+                        continue;
+                }
+
+                if (++event->count >= ATH9K_HTC_TX_TIMEOUT_COUNT) {
+                        list_del(&event->list);
+                        kfree(event);
+                }
+        }
+        spin_unlock(&priv->wmi->event_lock);
+
+        /*
+         * Check if status-pending packets have to be cleaned up.
+         */
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.mgmt_ep_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.cab_ep_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_be_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_bk_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_vi_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_vo_queue);
+
+        /* Wake TX queues if needed */
+        ath9k_htc_check_wake_queues(priv);
+
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
 }
 
 int ath9k_tx_init(struct ath9k_htc_priv *priv)
 {
-        skb_queue_head_init(&priv->tx_queue);
+        skb_queue_head_init(&priv->tx.mgmt_ep_queue);
+        skb_queue_head_init(&priv->tx.cab_ep_queue);
+        skb_queue_head_init(&priv->tx.data_be_queue);
+        skb_queue_head_init(&priv->tx.data_bk_queue);
+        skb_queue_head_init(&priv->tx.data_vi_queue);
+        skb_queue_head_init(&priv->tx.data_vo_queue);
+        skb_queue_head_init(&priv->tx.tx_failed);
         return 0;
 }
 
@@ -330,9 +820,8 @@ bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype)
                 return false;
 
         if (qnum >= ARRAY_SIZE(priv->hwq_map)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "qnum %u out of range, max %u!\n",
-                          qnum, (unsigned int)ARRAY_SIZE(priv->hwq_map));
+                ath_err(common, "qnum %u out of range, max %zu!\n",
+                        qnum, ARRAY_SIZE(priv->hwq_map));
                 ath9k_hw_releasetxqueue(ah, qnum);
                 return false;
         }
@@ -369,8 +858,7 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv)
                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
                 | ATH9K_RX_FILTER_MCAST;
 
-        /* If not a STA, enable processing of Probe Requests */
-        if (ah->opmode != NL80211_IFTYPE_STATION)
+        if (priv->rxfilter & FIF_PROBE_REQ)
                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 
         /*
@@ -380,20 +868,29 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv)
          */
         if (((ah->opmode != NL80211_IFTYPE_AP) &&
              (priv->rxfilter & FIF_PROMISC_IN_BSS)) ||
-            (ah->opmode == NL80211_IFTYPE_MONITOR))
+            ah->is_monitoring)
                 rfilt |= ATH9K_RX_FILTER_PROM;
 
         if (priv->rxfilter & FIF_CONTROL)
                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 
         if ((ah->opmode == NL80211_IFTYPE_STATION) &&
+            (priv->nvifs <= 1) &&
             !(priv->rxfilter & FIF_BCN_PRBRESP_PROMISC))
                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
         else
                 rfilt |= ATH9K_RX_FILTER_BEACON;
 
-        if (conf_is_ht(&priv->hw->conf))
+        if (conf_is_ht(&priv->hw->conf)) {
                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
+                rfilt |= ATH9K_RX_FILTER_UNCOMP_BA_BAR;
+        }
+
+        if (priv->rxfilter & FIF_PSPOLL)
+                rfilt |= ATH9K_RX_FILTER_PSPOLL;
+
+        if (priv->nvifs > 1)
+                rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
 
         return rfilt;
 
@@ -406,21 +903,12 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv)
 static void ath9k_htc_opmode_init(struct ath9k_htc_priv *priv)
 {
         struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
         u32 rfilt, mfilt[2];
 
         /* configure rx filter */
         rfilt = ath9k_htc_calcrxfilter(priv);
         ath9k_hw_setrxfilter(ah, rfilt);
 
-        /* configure bssid mask */
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                ath_hw_setbssidmask(common);
-
-        /* configure operational mode */
-        ath9k_hw_setopmode(ah);
-
         /* calculate and install multicast filter */
         mfilt[0] = mfilt[1] = ~0;
         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
@@ -484,9 +972,9 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
         int last_rssi = ATH_RSSI_DUMMY_MARKER;
         __le16 fc;
 
-        if (skb->len <= HTC_RX_FRAME_HEADER_SIZE) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Corrupted RX frame, dropping\n");
+        if (skb->len < HTC_RX_FRAME_HEADER_SIZE) {
+                ath_err(common, "Corrupted RX frame, dropping (len: %d)\n",
+                        skb->len);
                 goto rx_next;
         }
 
@@ -494,13 +982,14 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
 
         if (be16_to_cpu(rxstatus->rs_datalen) -
             (skb->len - HTC_RX_FRAME_HEADER_SIZE) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Corrupted RX data len, dropping "
-                          "(dlen: %d, skblen: %d)\n",
-                          rxstatus->rs_datalen, skb->len);
+                ath_err(common,
+                        "Corrupted RX data len, dropping (dlen: %d, skblen: %d)\n",
+                        rxstatus->rs_datalen, skb->len);
                 goto rx_next;
         }
 
+        ath9k_htc_err_stat_rx(priv, rxstatus);
+
         /* Get the RX status information */
         memcpy(&rxbuf->rxstatus, rxstatus, HTC_RX_FRAME_HEADER_SIZE);
         skb_pull(skb, HTC_RX_FRAME_HEADER_SIZE);
@@ -573,31 +1062,29 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
         ath9k_process_rate(hw, rx_status, rxbuf->rxstatus.rs_rate,
                            rxbuf->rxstatus.rs_flags);
 
-        if (priv->op_flags & OP_ASSOCIATED) {
-                if (rxbuf->rxstatus.rs_rssi != ATH9K_RSSI_BAD &&
-                    !rxbuf->rxstatus.rs_moreaggr)
-                        ATH_RSSI_LPF(priv->rx.last_rssi,
-                                     rxbuf->rxstatus.rs_rssi);
+        if (rxbuf->rxstatus.rs_rssi != ATH9K_RSSI_BAD &&
+            !rxbuf->rxstatus.rs_moreaggr)
+                ATH_RSSI_LPF(priv->rx.last_rssi,
+                             rxbuf->rxstatus.rs_rssi);
 
-                last_rssi = priv->rx.last_rssi;
+        last_rssi = priv->rx.last_rssi;
 
-                if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
-                        rxbuf->rxstatus.rs_rssi = ATH_EP_RND(last_rssi,
-                                                             ATH_RSSI_EP_MULTIPLIER);
+        if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
+                rxbuf->rxstatus.rs_rssi = ATH_EP_RND(last_rssi,
+                                                     ATH_RSSI_EP_MULTIPLIER);
 
-                if (rxbuf->rxstatus.rs_rssi < 0)
-                        rxbuf->rxstatus.rs_rssi = 0;
+        if (rxbuf->rxstatus.rs_rssi < 0)
+                rxbuf->rxstatus.rs_rssi = 0;
 
-                if (ieee80211_is_beacon(fc))
-                        priv->ah->stats.avgbrssi = rxbuf->rxstatus.rs_rssi;
-        }
+        if (ieee80211_is_beacon(fc))
+                priv->ah->stats.avgbrssi = rxbuf->rxstatus.rs_rssi;
 
         rx_status->mactime = be64_to_cpu(rxbuf->rxstatus.rs_tstamp);
         rx_status->band = hw->conf.channel->band;
         rx_status->freq = hw->conf.channel->center_freq;
         rx_status->signal =  rxbuf->rxstatus.rs_rssi + ATH_DEFAULT_NOISE_FLOOR;
         rx_status->antenna = rxbuf->rxstatus.rs_antenna;
-        rx_status->flag |= RX_FLAG_TSFT;
+        rx_status->flag |= RX_FLAG_MACTIME_MPDU;
 
         return true;
 
@@ -680,8 +1167,8 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb,
         spin_unlock(&priv->rx.rxbuflock);
 
         if (rxbuf == NULL) {
-                ath_print(common, ATH_DBG_ANY,
-                          "No free RX buffer\n");
+                ath_dbg(common, ATH_DBG_ANY,
+                        "No free RX buffer\n");
                 goto err;
         }
 
@@ -723,8 +1210,7 @@ int ath9k_rx_init(struct ath9k_htc_priv *priv)
         for (i = 0; i < ATH9K_HTC_RXBUF; i++) {
                 rxbuf = kzalloc(sizeof(struct ath9k_htc_rxbuf), GFP_KERNEL);
                 if (rxbuf == NULL) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to allocate RX buffers\n");
+                        ath_err(common, "Unable to allocate RX buffers\n");
                         goto err;
                 }
                 list_add_tail(&rxbuf->list, &priv->rx.rxbuf);
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
index 705c0f342e1c..1b90ed8795c3 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,8 +17,8 @@
 #include "htc.h"
 
 static int htc_issue_send(struct htc_target *target, struct sk_buff* skb,
-                          u16 len, u8 flags, u8 epid,
-                          struct ath9k_htc_tx_ctl *tx_ctl)
+                          u16 len, u8 flags, u8 epid)
+
 {
         struct htc_frame_hdr *hdr;
         struct htc_endpoint *endpoint = &target->endpoint[epid];
@@ -30,8 +30,8 @@ static int htc_issue_send(struct htc_target *target, struct sk_buff* skb,
         hdr->flags = flags;
         hdr->payload_len = cpu_to_be16(len);
 
-        status = target->hif->send(target->hif_dev, endpoint->ul_pipeid, skb,
-                                   tx_ctl);
+        status = target->hif->send(target->hif_dev, endpoint->ul_pipeid, skb);
+
         return status;
 }
 
@@ -162,7 +162,7 @@ static int htc_config_pipe_credits(struct htc_target *target)
 
         target->htc_flags |= HTC_OP_CONFIG_PIPE_CREDITS;
 
-        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0, NULL);
+        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0);
         if (ret)
                 goto err;
 
@@ -197,7 +197,7 @@ static int htc_setup_complete(struct htc_target *target)
 
         target->htc_flags |= HTC_OP_START_WAIT;
 
-        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0, NULL);
+        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0);
         if (ret)
                 goto err;
 
@@ -268,7 +268,7 @@ int htc_connect_service(struct htc_target *target,
         conn_msg->dl_pipeid = endpoint->dl_pipeid;
         conn_msg->ul_pipeid = endpoint->ul_pipeid;
 
-        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0, NULL);
+        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0);
         if (ret)
                 goto err;
 
@@ -286,35 +286,33 @@ err:
         return ret;
 }
 
-int htc_send(struct htc_target *target, struct sk_buff *skb,
-             enum htc_endpoint_id epid, struct ath9k_htc_tx_ctl *tx_ctl)
+int htc_send(struct htc_target *target, struct sk_buff *skb)
 {
-        return htc_issue_send(target, skb, skb->len, 0, epid, tx_ctl);
+        struct ath9k_htc_tx_ctl *tx_ctl;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        return htc_issue_send(target, skb, skb->len, 0, tx_ctl->epid);
 }
 
-void htc_stop(struct htc_target *target)
+int htc_send_epid(struct htc_target *target, struct sk_buff *skb,
+                  enum htc_endpoint_id epid)
 {
-        enum htc_endpoint_id epid;
-        struct htc_endpoint *endpoint;
+        return htc_issue_send(target, skb, skb->len, 0, epid);
+}
 
-        for (epid = ENDPOINT0; epid < ENDPOINT_MAX; epid++) {
-                endpoint = &target->endpoint[epid];
-                if (endpoint->service_id != 0)
-                        target->hif->stop(target->hif_dev, endpoint->ul_pipeid);
-        }
+void htc_stop(struct htc_target *target)
+{
+        target->hif->stop(target->hif_dev);
 }
 
 void htc_start(struct htc_target *target)
 {
-        enum htc_endpoint_id epid;
-        struct htc_endpoint *endpoint;
+        target->hif->start(target->hif_dev);
+}
 
-        for (epid = ENDPOINT0; epid < ENDPOINT_MAX; epid++) {
-                endpoint = &target->endpoint[epid];
-                if (endpoint->service_id != 0)
-                        target->hif->start(target->hif_dev,
-                                           endpoint->ul_pipeid);
-        }
+void htc_sta_drain(struct htc_target *target, u8 idx)
+{
+        target->hif->sta_drain(target->hif_dev, idx);
 }
 
 void ath9k_htc_txcompletion_cb(struct htc_target *htc_handle,
@@ -360,7 +358,7 @@ ret:
  * HTC Messages are handled directly here and the obtained SKB
  * is freed.
  *
- * Sevice messages (Data, WMI) passed to the corresponding
+ * Service messages (Data, WMI) passed to the corresponding
  * endpoint RX handlers, which have to free the SKB.
  */
 void ath9k_htc_rx_msg(struct htc_target *htc_handle,
@@ -462,9 +460,10 @@ void ath9k_htc_hw_free(struct htc_target *htc)
 }
 
 int ath9k_htc_hw_init(struct htc_target *target,
-                      struct device *dev, u16 devid)
+                      struct device *dev, u16 devid,
+                      char *product, u32 drv_info)
 {
-        if (ath9k_htc_probe_device(target, dev, devid)) {
+        if (ath9k_htc_probe_device(target, dev, devid, product, drv_info)) {
                 printk(KERN_ERR "Failed to initialize the device\n");
                 return -ENODEV;
         }
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.h b/drivers/net/wireless/ath/ath9k/htc_hst.h
index faba6790328b..e1ffbb6bd636 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.h
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -33,10 +33,10 @@ struct ath9k_htc_hif {
         u8 control_dl_pipe;
         u8 control_ul_pipe;
 
-        void (*start) (void *hif_handle, u8 pipe);
-        void (*stop) (void *hif_handle, u8 pipe);
-        int (*send) (void *hif_handle, u8 pipe, struct sk_buff *buf,
-                     struct ath9k_htc_tx_ctl *tx_ctl);
+        void (*start) (void *hif_handle);
+        void (*stop) (void *hif_handle);
+        void (*sta_drain) (void *hif_handle, u8 idx);
+        int (*send) (void *hif_handle, u8 pipe, struct sk_buff *buf);
 };
 
 enum htc_endpoint_id {
@@ -77,41 +77,16 @@ struct htc_config_pipe_msg {
         u8 credits;
 } __packed;
 
-struct htc_packet {
-        void *pktcontext;
-        u8 *buf;
-        u8 *buf_payload;
-        u32 buflen;
-        u32 payload_len;
-
-        int endpoint;
-        int status;
-
-        void *context;
-        u32 reserved;
-};
-
 struct htc_ep_callbacks {
         void *priv;
         void (*tx) (void *, struct sk_buff *, enum htc_endpoint_id, bool txok);
         void (*rx) (void *, struct sk_buff *, enum htc_endpoint_id);
 };
 
-#define HTC_TX_QUEUE_SIZE 256
-
-struct htc_txq {
-        struct sk_buff *buf[HTC_TX_QUEUE_SIZE];
-        u32 txqdepth;
-        u16 txbuf_cnt;
-        u16 txq_head;
-        u16 txq_tail;
-};
-
 struct htc_endpoint {
         u16 service_id;
 
         struct htc_ep_callbacks ep_callbacks;
-        struct htc_txq htc_txq;
         u32 max_txqdepth;
         int max_msglen;
 
@@ -123,11 +98,6 @@ struct htc_endpoint {
 #define HTC_CONTROL_BUFFER_SIZE \
         (HTC_MAX_CONTROL_MESSAGE_LENGTH + sizeof(struct htc_frame_hdr))
 
-struct htc_control_buf {
-        struct htc_packet htc_pkt;
-        u8 buf[HTC_CONTROL_BUFFER_SIZE];
-};
-
 #define HTC_OP_START_WAIT           BIT(0)
 #define HTC_OP_CONFIG_PIPE_CREDITS  BIT(1)
 
@@ -224,10 +194,12 @@ int htc_init(struct htc_target *target);
 int htc_connect_service(struct htc_target *target,
                           struct htc_service_connreq *service_connreq,
                           enum htc_endpoint_id *conn_rsp_eid);
-int htc_send(struct htc_target *target, struct sk_buff *skb,
-             enum htc_endpoint_id eid, struct ath9k_htc_tx_ctl *tx_ctl);
+int htc_send(struct htc_target *target, struct sk_buff *skb);
+int htc_send_epid(struct htc_target *target, struct sk_buff *skb,
+                  enum htc_endpoint_id epid);
 void htc_stop(struct htc_target *target);
 void htc_start(struct htc_target *target);
+void htc_sta_drain(struct htc_target *target, u8 idx);
 
 void ath9k_htc_rx_msg(struct htc_target *htc_handle,
                       struct sk_buff *skb, u32 len, u8 pipe_id);
@@ -239,7 +211,8 @@ struct htc_target *ath9k_htc_hw_alloc(void *hif_handle,
                                       struct device *dev);
 void ath9k_htc_hw_free(struct htc_target *htc);
 int ath9k_htc_hw_init(struct htc_target *target,
-                      struct device *dev, u16 devid);
+                      struct device *dev, u16 devid, char *product,
+                      u32 drv_info);
 void ath9k_htc_hw_deinit(struct htc_target *target, bool hot_unplug);
 
 #endif /* HTC_HST_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index ffecbadaea4a..2f3e07263fcb 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -116,27 +116,21 @@ static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
         ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
 }
 
-static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
-                                                 u32 burstDuration)
+static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
 {
-        ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
+        ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
 }
 
-static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
-                                                   u32 vmf)
+static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                struct ath_hw_antcomb_conf *antconf)
 {
-        ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
+        ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf);
 }
 
-static inline void ath9k_hw_procmibevent(struct ath_hw *ah)
+static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                struct ath_hw_antcomb_conf *antconf)
 {
-        ath9k_hw_ops(ah)->ani_proc_mib_event(ah);
-}
-
-static inline void ath9k_hw_ani_monitor(struct ath_hw *ah,
-                                        struct ath9k_channel *chan)
-{
-        ath9k_hw_ops(ah)->ani_monitor(ah, chan);
+        ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
 }
 
 /* Private hardware call ops */
@@ -234,11 +228,6 @@ static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
         return ath9k_hw_private_ops(ah)->rfbus_done(ah);
 }
 
-static inline void ath9k_enable_rfkill(struct ath_hw *ah)
-{
-        return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
-}
-
 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
 {
         if (!ath9k_hw_private_ops(ah)->restore_chainmask)
@@ -276,15 +265,4 @@ static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
         ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
 }
 
-static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
-                                            enum ath9k_cal_types calType)
-{
-        return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
-}
-
-static inline void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
-{
-        ath9k_hw_private_ops(ah)->ani_reset(ah, is_scanning);
-}
-
 #endif /* ATH9K_HW_OPS_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 3384ca164562..1be7c8bbef84 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
 }
 
-static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-
-        return priv_ops->macversion_supported(ah->hw_version.macVersion);
-}
-
 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
                                         struct ath9k_channel *chan)
 {
@@ -88,29 +81,32 @@ static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
 /* Helper Functions */
 /********************/
 
-static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
+static void ath9k_hw_set_clockrate(struct ath_hw *ah)
 {
         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+        struct ath_common *common = ath9k_hw_common(ah);
+        unsigned int clockrate;
 
         if (!ah->curchan) /* should really check for CCK instead */
-                return usecs *ATH9K_CLOCK_RATE_CCK;
-        if (conf->channel->band == IEEE80211_BAND_2GHZ)
-                return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
-
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
-                return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
+                clockrate = ATH9K_CLOCK_RATE_CCK;
+        else if (conf->channel->band == IEEE80211_BAND_2GHZ)
+                clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
+        else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
+                clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
         else
-                return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
+                clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
+
+        if (conf_is_ht40(conf))
+                clockrate *= 2;
+
+        common->clockrate = clockrate;
 }
 
 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 {
-        struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+        struct ath_common *common = ath9k_hw_common(ah);
 
-        if (conf_is_ht40(conf))
-                return ath9k_hw_mac_clks(ah, usecs) * 2;
-        else
-                return ath9k_hw_mac_clks(ah, usecs);
+        return usecs * common->clockrate;
 }
 
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
@@ -126,14 +122,28 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
                 udelay(AH_TIME_QUANTUM);
         }
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
-                  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
-                  timeout, reg, REG_READ(ah, reg), mask, val);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
+                "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
+                timeout, reg, REG_READ(ah, reg), mask, val);
 
         return false;
 }
 EXPORT_SYMBOL(ath9k_hw_wait);
 
+void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                          int column, unsigned int *writecnt)
+{
+        int r;
+
+        ENABLE_REGWRITE_BUFFER(ah);
+        for (r = 0; r < array->ia_rows; r++) {
+                REG_WRITE(ah, INI_RA(array, r, 0),
+                          INI_RA(array, r, column));
+                DO_DELAY(*writecnt);
+        }
+        REGWRITE_BUFFER_FLUSH(ah);
+}
+
 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 {
         u32 retval;
@@ -146,25 +156,6 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
         return retval;
 }
 
-bool ath9k_get_channel_edges(struct ath_hw *ah,
-                             u16 flags, u16 *low,
-                             u16 *high)
-{
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
-
-        if (flags & CHANNEL_5GHZ) {
-                *low = pCap->low_5ghz_chan;
-                *high = pCap->high_5ghz_chan;
-                return true;
-        }
-        if ((flags & CHANNEL_2GHZ)) {
-                *low = pCap->low_2ghz_chan;
-                *high = pCap->high_2ghz_chan;
-                return true;
-        }
-        return false;
-}
-
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                            u8 phy, int kbps,
                            u32 frameLen, u16 rateix,
@@ -208,8 +199,8 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                 }
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unknown phy %u (rate ix %u)\n", phy, rateix);
+                ath_err(ath9k_hw_common(ah),
+                        "Unknown phy %u (rate ix %u)\n", phy, rateix);
                 txTime = 0;
                 break;
         }
@@ -256,6 +247,17 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
 {
         u32 val;
 
+        switch (ah->hw_version.devid) {
+        case AR5416_AR9100_DEVID:
+                ah->hw_version.macVersion = AR_SREV_VERSION_9100;
+                break;
+        case AR9300_DEVID_AR9340:
+                ah->hw_version.macVersion = AR_SREV_VERSION_9340;
+                val = REG_READ(ah, AR_SREV);
+                ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
+                return;
+        }
+
         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 
         if (val == 0xFF) {
@@ -281,11 +283,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
 
 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 {
-        if (AR_SREV_9100(ah))
+        if (!AR_SREV_5416(ah))
                 return;
 
-        ENABLE_REGWRITE_BUFFER(ah);
-
         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -297,9 +297,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 
         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
-
-        REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /* This should work for all families including legacy */
@@ -308,10 +305,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         u32 regAddr[2] = { AR_STA_ID0 };
         u32 regHold[2];
-        u32 patternData[4] = { 0x55555555,
-                               0xaaaaaaaa,
-                               0x66666666,
-                               0x99999999 };
+        static const u32 patternData[4] = {
+                0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
+        };
         int i, j, loop_max;
 
         if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@ -330,11 +326,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                         REG_WRITE(ah, addr, wrData);
                         rdData = REG_READ(ah, addr);
                         if (rdData != wrData) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "address test failed "
-                                          "addr: 0x%08x - wr:0x%08x != "
-                                          "rd:0x%08x\n",
-                                          addr, wrData, rdData);
+                                ath_err(common,
+                                        "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+                                        addr, wrData, rdData);
                                 return false;
                         }
                 }
@@ -343,11 +337,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                         REG_WRITE(ah, addr, wrData);
                         rdData = REG_READ(ah, addr);
                         if (wrData != rdData) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "address test failed "
-                                          "addr: 0x%08x - wr:0x%08x != "
-                                          "rd:0x%08x\n",
-                                          addr, wrData, rdData);
+                                ath_err(common,
+                                        "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+                                        addr, wrData, rdData);
                                 return false;
                         }
                 }
@@ -371,10 +363,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
         ah->config.pcie_clock_req = 0;
         ah->config.pcie_waen = 0;
         ah->config.analog_shiftreg = 1;
-        ah->config.ofdm_trig_low = 200;
-        ah->config.ofdm_trig_high = 500;
-        ah->config.cck_trig_high = 200;
-        ah->config.cck_trig_low = 100;
         ah->config.enable_ani = true;
 
         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
@@ -382,10 +370,8 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
                 ah->config.spurchans[i][1] = AR_NO_SPUR;
         }
 
-        if (ah->hw_version.devid != AR2427_DEVID_PCIE)
-                ah->config.ht_enable = 1;
-        else
-                ah->config.ht_enable = 0;
+        /* PAPRD needs some more work to be enabled */
+        ah->config.paprd_disable = 1;
 
         ah->config.rx_intr_mitigation = true;
         ah->config.pcieSerDesWrite = true;
@@ -421,17 +407,14 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
         ah->hw_version.magic = AR5416_MAGIC;
         ah->hw_version.subvendorid = 0;
 
-        ah->ah_flags = 0;
-        if (!AR_SREV_9100(ah))
-                ah->ah_flags = AH_USE_EEPROM;
-
         ah->atim_window = 0;
         ah->sta_id1_defaults =
                 AR_STA_ID1_CRPT_MIC_ENABLE |
                 AR_STA_ID1_MCAST_KSRCH;
-        ah->beacon_interval = 100;
+        if (AR_SREV_9100(ah))
+                ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
         ah->enable_32kHz_clock = DONT_USE_32KHZ;
-        ah->slottime = (u32) -1;
+        ah->slottime = 20;
         ah->globaltxtimeout = (u32) -1;
         ah->power_mode = ATH9K_PM_UNDEFINED;
 }
@@ -442,7 +425,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
         u32 sum;
         int i;
         u16 eeval;
-        u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
+        static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 
         sum = 0;
         for (i = 0; i < 3; i++) {
@@ -459,9 +442,10 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 
 static int ath9k_hw_post_init(struct ath_hw *ah)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
         int ecode;
 
-        if (!AR_SREV_9271(ah)) {
+        if (common->bus_ops->ath_bus_type != ATH_USB) {
                 if (!ath9k_hw_chip_test(ah))
                         return -ENODEV;
         }
@@ -476,20 +460,20 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
         if (ecode != 0)
                 return ecode;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
-                  "Eeprom VER: %d, REV: %d\n",
-                  ah->eep_ops->get_eeprom_ver(ah),
-                  ah->eep_ops->get_eeprom_rev(ah));
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
+                "Eeprom VER: %d, REV: %d\n",
+                ah->eep_ops->get_eeprom_ver(ah),
+                ah->eep_ops->get_eeprom_rev(ah));
 
         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
         if (ecode) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Failed allocating banks for "
-                          "external radio\n");
+                ath_err(ath9k_hw_common(ah),
+                        "Failed allocating banks for external radio\n");
+                ath9k_hw_rf_free_ext_banks(ah);
                 return ecode;
         }
 
-        if (!AR_SREV_9100(ah)) {
+        if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
                 ath9k_hw_ani_setup(ah);
                 ath9k_hw_ani_init(ah);
         }
@@ -511,12 +495,19 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         int r = 0;
 
-        if (ah->hw_version.devid == AR5416_AR9100_DEVID)
-                ah->hw_version.macVersion = AR_SREV_VERSION_9100;
+        ath9k_hw_read_revisions(ah);
+
+        /*
+         * Read back AR_WA into a permanent copy and set bits 14 and 17.
+         * We need to do this to avoid RMW of this register. We cannot
+         * read the reg when chip is asleep.
+         */
+        ah->WARegVal = REG_READ(ah, AR_WA);
+        ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
+                         AR_WA_ASPM_TIMER_BASED_DISABLE);
 
         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Couldn't reset chip\n");
+                ath_err(common, "Couldn't reset chip\n");
                 return -EIO;
         }
 
@@ -526,7 +517,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         ath9k_hw_attach_ops(ah);
 
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
-                ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
+                ath_err(common, "Couldn't wakeup chip\n");
                 return -EIO;
         }
 
@@ -542,7 +533,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
                 }
         }
 
-        ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
+        ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
                 ah->config.serialize_regmode);
 
         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
@@ -550,36 +541,40 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         else
                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 
-        if (!ath9k_hw_macversion_supported(ah)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Mac Chip Rev 0x%02x.%x is not supported by "
-                          "this driver\n", ah->hw_version.macVersion,
-                          ah->hw_version.macRev);
+        switch (ah->hw_version.macVersion) {
+        case AR_SREV_VERSION_5416_PCI:
+        case AR_SREV_VERSION_5416_PCIE:
+        case AR_SREV_VERSION_9160:
+        case AR_SREV_VERSION_9100:
+        case AR_SREV_VERSION_9280:
+        case AR_SREV_VERSION_9285:
+        case AR_SREV_VERSION_9287:
+        case AR_SREV_VERSION_9271:
+        case AR_SREV_VERSION_9300:
+        case AR_SREV_VERSION_9485:
+        case AR_SREV_VERSION_9340:
+                break;
+        default:
+                ath_err(common,
+                        "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
+                        ah->hw_version.macVersion, ah->hw_version.macRev);
                 return -EOPNOTSUPP;
         }
 
-        if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
+        if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
                 ah->is_pciexpress = false;
 
         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
         ath9k_hw_init_cal_settings(ah);
 
         ah->ani_function = ATH9K_ANI_ALL;
-        if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
         if (!AR_SREV_9300_20_OR_LATER(ah))
                 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 
         ath9k_hw_init_mode_regs(ah);
 
-        /*
-         * Read back AR_WA into a permanent copy and set bits 14 and 17.
-         * We need to do this to avoid RMW of this register. We cannot
-         * read the reg when chip is asleep.
-         */
-        ah->WARegVal = REG_READ(ah, AR_WA);
-        ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
-                         AR_WA_ASPM_TIMER_BASED_DISABLE);
 
         if (ah->is_pciexpress)
                 ath9k_hw_configpcipowersave(ah, 0, 0);
@@ -600,8 +595,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
 
         r = ath9k_hw_init_macaddr(ah);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to initialize MAC address\n");
+                ath_err(common, "Failed to initialize MAC address\n");
                 return r;
         }
 
@@ -635,21 +629,22 @@ int ath9k_hw_init(struct ath_hw *ah)
         case AR9287_DEVID_PCIE:
         case AR2427_DEVID_PCIE:
         case AR9300_DEVID_PCIE:
+        case AR9300_DEVID_AR9485_PCIE:
+        case AR9300_DEVID_AR9340:
                 break;
         default:
                 if (common->bus_ops->ath_bus_type == ATH_USB)
                         break;
-                ath_print(common, ATH_DBG_FATAL,
-                          "Hardware device ID 0x%04x not supported\n",
-                          ah->hw_version.devid);
+                ath_err(common, "Hardware device ID 0x%04x not supported\n",
+                        ah->hw_version.devid);
                 return -EOPNOTSUPP;
         }
 
         ret = __ath9k_hw_init(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize hardware; "
-                          "initialization status: %d\n", ret);
+                ath_err(common,
+                        "Unable to initialize hardware; initialization status: %d\n",
+                        ret);
                 return ret;
         }
 
@@ -676,16 +671,101 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
+u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
+{
+        REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
+        udelay(100);
+        REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
+
+        while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
+                udelay(100);
+
+        return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
+}
+EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
+
 static void ath9k_hw_init_pll(struct ath_hw *ah,
                               struct ath9k_channel *chan)
 {
-        u32 pll = ath9k_hw_compute_pll_control(ah, chan);
+        u32 pll;
+
+        if (AR_SREV_9485(ah)) {
+
+                /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_DPLL2_KD, 0x40);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_DPLL2_KI, 0x4);
+
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
+                              AR_CH0_BB_DPLL1_REFDIV, 0x5);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
+                              AR_CH0_BB_DPLL1_NINI, 0x58);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
+                              AR_CH0_BB_DPLL1_NFRAC, 0x0);
+
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_OUTDIV, 0x1);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
+
+                /* program BB PLL phase_shift to 0x6 */
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
+                              AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
+
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
+                udelay(1000);
+        } else if (AR_SREV_9340(ah)) {
+                u32 regval, pll2_divint, pll2_divfrac, refdiv;
+
+                REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
+                udelay(1000);
+
+                REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
+                udelay(100);
+
+                if (ah->is_clk_25mhz) {
+                        pll2_divint = 0x54;
+                        pll2_divfrac = 0x1eb85;
+                        refdiv = 3;
+                } else {
+                        pll2_divint = 88;
+                        pll2_divfrac = 0;
+                        refdiv = 5;
+                }
+
+                regval = REG_READ(ah, AR_PHY_PLL_MODE);
+                regval |= (0x1 << 16);
+                REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
+                udelay(100);
+
+                REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
+                          (pll2_divint << 18) | pll2_divfrac);
+                udelay(100);
+
+                regval = REG_READ(ah, AR_PHY_PLL_MODE);
+                regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
+                         (0x4 << 26) | (0x18 << 19);
+                REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
+                REG_WRITE(ah, AR_PHY_PLL_MODE,
+                          REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
+                udelay(1000);
+        }
+
+        pll = ath9k_hw_compute_pll_control(ah, chan);
 
         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                udelay(1000);
+
         /* Switch the core clock for ar9271 to 117Mhz */
         if (AR_SREV_9271(ah)) {
                 udelay(500);
@@ -695,17 +775,34 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
         udelay(RTC_PLL_SETTLE_DELAY);
 
         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
+
+        if (AR_SREV_9340(ah)) {
+                if (ah->is_clk_25mhz) {
+                        REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
+                        REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
+                        REG_WRITE(ah,  AR_SLP32_INC, 0x0001e7ae);
+                } else {
+                        REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
+                        REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
+                        REG_WRITE(ah,  AR_SLP32_INC, 0x0001e800);
+                }
+                udelay(100);
+        }
 }
 
 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
                                           enum nl80211_iftype opmode)
 {
+        u32 sync_default = AR_INTR_SYNC_DEFAULT;
         u32 imr_reg = AR_IMR_TXERR |
                 AR_IMR_TXURN |
                 AR_IMR_RXERR |
                 AR_IMR_RXORN |
                 AR_IMR_BCNMISC;
 
+        if (AR_SREV_9340(ah))
+                sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
+
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 imr_reg |= AR_IMR_RXOK_HP;
                 if (ah->config.rx_intr_mitigation)
@@ -736,12 +833,11 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 
         if (!AR_SREV_9100(ah)) {
                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
-                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
@@ -775,8 +871,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 {
         if (tu > 0xFFFF) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                          "bad global tx timeout %u\n", tu);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                        "bad global tx timeout %u\n", tu);
                 ah->globaltxtimeout = (u32) -1;
                 return false;
         } else {
@@ -793,12 +889,11 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
         int slottime;
         int sifstime;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
-                  ah->misc_mode);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
+                ah->misc_mode);
 
         if (ah->misc_mode != 0)
-                REG_WRITE(ah, AR_PCU_MISC,
-                          REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
+                REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
 
         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
                 sifstime = 16;
@@ -819,7 +914,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
                 acktimeout += 64 - sifstime - ah->slottime;
 
-        ath9k_hw_setslottime(ah, slottime);
+        ath9k_hw_setslottime(ah, ah->slottime);
         ath9k_hw_set_ack_timeout(ah, acktimeout);
         ath9k_hw_set_cts_timeout(ah, acktimeout);
         if (ah->globaltxtimeout != (u32) -1)
@@ -866,26 +961,21 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        u32 regval;
 
         ENABLE_REGWRITE_BUFFER(ah);
 
         /*
          * set AHB_MODE not to do cacheline prefetches
         */
-        if (!AR_SREV_9300_20_OR_LATER(ah)) {
-                regval = REG_READ(ah, AR_AHB_MODE);
-                REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
-        }
+        if (!AR_SREV_9300_20_OR_LATER(ah))
+                REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
 
         /*
          * let mac dma reads be in 128 byte chunks
          */
-        regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
-        REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
+        REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         /*
          * Restore TX Trigger Level to its pre-reset value.
@@ -900,8 +990,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
         /*
          * let mac dma writes be in 128 byte chunks
          */
-        regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
-        REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
+        REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
 
         /*
          * Setup receive FIFO threshold to hold off TX activities
@@ -933,7 +1022,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah))
                 ath9k_hw_reset_txstatus_ring(ah);
@@ -941,27 +1029,27 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 
 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 {
-        u32 val;
+        u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
+        u32 set = AR_STA_ID1_KSRCH_MODE;
 
-        val = REG_READ(ah, AR_STA_ID1);
-        val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
         switch (opmode) {
-        case NL80211_IFTYPE_AP:
-                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
-                          | AR_STA_ID1_KSRCH_MODE);
-                REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
-                break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
-                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
-                          | AR_STA_ID1_KSRCH_MODE);
+                set |= AR_STA_ID1_ADHOC;
                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
                 break;
+        case NL80211_IFTYPE_AP:
+                set |= AR_STA_ID1_STA_AP;
+                /* fall through */
         case NL80211_IFTYPE_STATION:
-        case NL80211_IFTYPE_MONITOR:
-                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
+                REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+                break;
+        default:
+                if (!ah->is_monitoring)
+                        set = 0;
                 break;
         }
+        REG_RMW(ah, AR_STA_ID1, set, mask);
 }
 
 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
@@ -987,10 +1075,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
         u32 tmpReg;
 
         if (AR_SREV_9100(ah)) {
-                u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
-                val &= ~AR_RTC_DERIVED_CLK_PERIOD;
-                val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
-                REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
+                REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
+                              AR_RTC_DERIVED_CLK_PERIOD, 1);
                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
         }
 
@@ -1031,14 +1117,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
         REG_WRITE(ah, AR_RTC_RC, rst_flags);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         udelay(50);
 
         REG_WRITE(ah, AR_RTC_RC, 0);
         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "RTC stuck in MAC reset\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "RTC stuck in MAC reset\n");
                 return false;
         }
 
@@ -1067,10 +1152,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
 
         REG_WRITE(ah, AR_RTC_RESET, 0);
-        udelay(2);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (!AR_SREV_9300_20_OR_LATER(ah))
                 udelay(2);
@@ -1085,13 +1168,11 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
                            AR_RTC_STATUS_M,
                            AR_RTC_STATUS_ON,
                            AH_WAIT_TIMEOUT)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "RTC not waking up\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "RTC not waking up\n");
                 return false;
         }
 
-        ath9k_hw_read_revisions(ah);
-
         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
 }
 
@@ -1146,16 +1227,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
 
         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
                 if (ath9k_hw_numtxpending(ah, qnum)) {
-                        ath_print(common, ATH_DBG_QUEUE,
-                                  "Transmit frames pending on "
-                                  "queue %d\n", qnum);
+                        ath_dbg(common, ATH_DBG_QUEUE,
+                                "Transmit frames pending on queue %d\n", qnum);
                         return false;
                 }
         }
 
         if (!ath9k_hw_rfbus_req(ah)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Could not kill baseband RX\n");
+                ath_err(common, "Could not kill baseband RX\n");
                 return false;
         }
 
@@ -1163,17 +1242,17 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
 
         r = ath9k_hw_rf_set_freq(ah, chan);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to set channel\n");
+                ath_err(common, "Failed to set channel\n");
                 return false;
         }
+        ath9k_hw_set_clockrate(ah);
 
         ah->eep_ops->set_txpower(ah, chan,
                              ath9k_regd_get_ctl(regulatory, chan),
                              channel->max_antenna_gain * 2,
                              channel->max_power * 2,
                              min((u32) MAX_RATE_POWER,
-                             (u32) regulatory->power_limit));
+                             (u32) regulatory->power_limit), false);
 
         ath9k_hw_rfbus_done(ah);
 
@@ -1185,12 +1264,26 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
         return true;
 }
 
+static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
+{
+        u32 gpio_mask = ah->gpio_mask;
+        int i;
+
+        for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
+                if (!(gpio_mask & 1))
+                        continue;
+
+                ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+                ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
+        }
+}
+
 bool ath9k_hw_check_alive(struct ath_hw *ah)
 {
         int count = 50;
         u32 reg;
 
-        if (AR_SREV_9285_10_OR_LATER(ah))
+        if (AR_SREV_9285_12_OR_LATER(ah))
                 return true;
 
         do {
@@ -1227,19 +1320,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ah->txchainmask = common->tx_chainmask;
         ah->rxchainmask = common->rx_chainmask;
 
-        if (!ah->chip_fullsleep) {
-                ath9k_hw_abortpcurecv(ah);
-                if (!ath9k_hw_stopdmarecv(ah)) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                "Failed to stop receive dma\n");
-                        bChannelChange = false;
-                }
-        }
-
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                 return -EIO;
 
-        if (curchan && !ah->chip_fullsleep && ah->caldata)
+        if (curchan && !ah->chip_fullsleep)
                 ath9k_hw_getnf(ah, curchan);
 
         ah->caldata = caldata;
@@ -1258,11 +1342,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
             (chan->channel != ah->curchan->channel) &&
             ((chan->channelFlags & CHANNEL_ALL) ==
              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
-            !AR_SREV_9280(ah)) {
+            (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
 
                 if (ath9k_hw_channel_change(ah, chan)) {
                         ath9k_hw_loadnf(ah, ah->curchan);
                         ath9k_hw_start_nfcal(ah, true);
+                        if (AR_SREV_9271(ah))
+                                ar9002_hw_load_ani_reg(ah, chan);
                         return 0;
                 }
         }
@@ -1284,6 +1370,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
         ath9k_hw_mark_phy_inactive(ah);
 
+        ah->paprd_table_write_done = false;
+
         /* Only required on the first reset */
         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
                 REG_WRITE(ah,
@@ -1293,7 +1381,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         }
 
         if (!ath9k_hw_chip_reset(ah, chan)) {
-                ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
+                ath_err(common, "Chip reset failed\n");
                 return -EINVAL;
         }
 
@@ -1310,7 +1398,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (tsf)
                 ath9k_hw_settsf64(ah, tsf);
 
-        if (AR_SREV_9280_10_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah))
                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
 
         if (!AR_SREV_9300_20_OR_LATER(ah))
@@ -1354,8 +1442,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ath9k_hw_spur_mitigate_freq(ah, chan);
         ah->eep_ops->set_board_values(ah, chan);
 
-        ath9k_hw_set_operating_mode(ah, ah->opmode);
-
         ENABLE_REGWRITE_BUFFER(ah);
 
         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
@@ -1372,22 +1458,24 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
+
+        ath9k_hw_set_operating_mode(ah, ah->opmode);
 
         r = ath9k_hw_rf_set_freq(ah, chan);
         if (r)
                 return r;
 
+        ath9k_hw_set_clockrate(ah);
+
         ENABLE_REGWRITE_BUFFER(ah);
 
         for (i = 0; i < AR_NUM_DCU; i++)
                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         ah->intr_txqs = 0;
-        for (i = 0; i < ah->caps.total_queues; i++)
+        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
                 ath9k_hw_resettxqueue(ah, i);
 
         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
@@ -1395,7 +1483,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ath9k_hw_init_qos(ah);
 
         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
-                ath9k_enable_rfkill(ah);
+                ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 
         ath9k_hw_init_global_settings(ah);
 
@@ -1404,8 +1492,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 ar9002_hw_enable_wep_aggregation(ah);
         }
 
-        REG_WRITE(ah, AR_STA_ID1,
-                  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
+        REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
 
         ath9k_hw_set_dma(ah);
 
@@ -1432,7 +1519,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         /*
          * For big endian systems turn on swapping for descriptors
@@ -1441,13 +1527,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 u32 mask;
                 mask = REG_READ(ah, AR_CFG);
                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
-                        ath_print(common, ATH_DBG_RESET,
+                        ath_dbg(common, ATH_DBG_RESET,
                                 "CFG Byte Swap Set 0x%x\n", mask);
                 } else {
                         mask =
                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
                         REG_WRITE(ah, AR_CFG, mask);
-                        ath_print(common, ATH_DBG_RESET,
+                        ath_dbg(common, ATH_DBG_RESET,
                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
                 }
         } else {
@@ -1459,7 +1545,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
                 }
 #ifdef __BIG_ENDIAN
-                else
+                else if (AR_SREV_9340(ah))
+                        REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
+                else
                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
 #endif
         }
@@ -1467,289 +1555,17 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (ah->btcoex_hw.enabled)
                 ath9k_hw_btcoex_enable(ah);
 
-        if (AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
                 ar9003_hw_bb_watchdog_config(ah);
 
-        return 0;
-}
-EXPORT_SYMBOL(ath9k_hw_reset);
-
-/************************/
-/* Key Cache Management */
-/************************/
-
-bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
-{
-        u32 keyType;
-
-        if (entry >= ah->caps.keycache_size) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "keychache entry %u out of range\n", entry);
-                return false;
+                ar9003_hw_disable_phy_restart(ah);
         }
 
-        keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
+        ath9k_hw_apply_gpio_override(ah);
 
-        REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
-        REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
-
-        if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
-                u16 micentry = entry + 64;
-
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
-
-        }
-
-        return true;
-}
-EXPORT_SYMBOL(ath9k_hw_keyreset);
-
-static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
-{
-        u32 macHi, macLo;
-        u32 unicast_flag = AR_KEYTABLE_VALID;
-
-        if (entry >= ah->caps.keycache_size) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "keychache entry %u out of range\n", entry);
-                return false;
-        }
-
-        if (mac != NULL) {
-                /*
-                 * AR_KEYTABLE_VALID indicates that the address is a unicast
-                 * address, which must match the transmitter address for
-                 * decrypting frames.
-                 * Not setting this bit allows the hardware to use the key
-                 * for multicast frame decryption.
-                 */
-                if (mac[0] & 0x01)
-                        unicast_flag = 0;
-
-                macHi = (mac[5] << 8) | mac[4];
-                macLo = (mac[3] << 24) |
-                        (mac[2] << 16) |
-                        (mac[1] << 8) |
-                        mac[0];
-                macLo >>= 1;
-                macLo |= (macHi & 1) << 31;
-                macHi >>= 1;
-        } else {
-                macLo = macHi = 0;
-        }
-        REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
-        REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
-
-        return true;
-}
-
-bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
-                                 const struct ath9k_keyval *k,
-                                 const u8 *mac)
-{
-        const struct ath9k_hw_capabilities *pCap = &ah->caps;
-        struct ath_common *common = ath9k_hw_common(ah);
-        u32 key0, key1, key2, key3, key4;
-        u32 keyType;
-
-        if (entry >= pCap->keycache_size) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "keycache entry %u out of range\n", entry);
-                return false;
-        }
-
-        switch (k->kv_type) {
-        case ATH9K_CIPHER_AES_OCB:
-                keyType = AR_KEYTABLE_TYPE_AES;
-                break;
-        case ATH9K_CIPHER_AES_CCM:
-                if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "AES-CCM not supported by mac rev 0x%x\n",
-                                  ah->hw_version.macRev);
-                        return false;
-                }
-                keyType = AR_KEYTABLE_TYPE_CCM;
-                break;
-        case ATH9K_CIPHER_TKIP:
-                keyType = AR_KEYTABLE_TYPE_TKIP;
-                if (ATH9K_IS_MIC_ENABLED(ah)
-                    && entry + 64 >= pCap->keycache_size) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "entry %u inappropriate for TKIP\n", entry);
-                        return false;
-                }
-                break;
-        case ATH9K_CIPHER_WEP:
-                if (k->kv_len < WLAN_KEY_LEN_WEP40) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "WEP key length %u too small\n", k->kv_len);
-                        return false;
-                }
-                if (k->kv_len <= WLAN_KEY_LEN_WEP40)
-                        keyType = AR_KEYTABLE_TYPE_40;
-                else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
-                        keyType = AR_KEYTABLE_TYPE_104;
-                else
-                        keyType = AR_KEYTABLE_TYPE_128;
-                break;
-        case ATH9K_CIPHER_CLR:
-                keyType = AR_KEYTABLE_TYPE_CLR;
-                break;
-        default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "cipher %u not supported\n", k->kv_type);
-                return false;
-        }
-
-        key0 = get_unaligned_le32(k->kv_val + 0);
-        key1 = get_unaligned_le16(k->kv_val + 4);
-        key2 = get_unaligned_le32(k->kv_val + 6);
-        key3 = get_unaligned_le16(k->kv_val + 10);
-        key4 = get_unaligned_le32(k->kv_val + 12);
-        if (k->kv_len <= WLAN_KEY_LEN_WEP104)
-                key4 &= 0xff;
-
-        /*
-         * Note: Key cache registers access special memory area that requires
-         * two 32-bit writes to actually update the values in the internal
-         * memory. Consequently, the exact order and pairs used here must be
-         * maintained.
-         */
-
-        if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
-                u16 micentry = entry + 64;
-
-                /*
-                 * Write inverted key[47:0] first to avoid Michael MIC errors
-                 * on frames that could be sent or received at the same time.
-                 * The correct key will be written in the end once everything
-                 * else is ready.
-                 */
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
-
-                /* Write key[95:48] */
-                REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
-                REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
-
-                /* Write key[127:96] and key type */
-                REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
-                REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
-
-                /* Write MAC address for the entry */
-                (void) ath9k_hw_keysetmac(ah, entry, mac);
-
-                if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
-                        /*
-                         * TKIP uses two key cache entries:
-                         * Michael MIC TX/RX keys in the same key cache entry
-                         * (idx = main index + 64):
-                         * key0 [31:0] = RX key [31:0]
-                         * key1 [15:0] = TX key [31:16]
-                         * key1 [31:16] = reserved
-                         * key2 [31:0] = RX key [63:32]
-                         * key3 [15:0] = TX key [15:0]
-                         * key3 [31:16] = reserved
-                         * key4 [31:0] = TX key [63:32]
-                         */
-                        u32 mic0, mic1, mic2, mic3, mic4;
-
-                        mic0 = get_unaligned_le32(k->kv_mic + 0);
-                        mic2 = get_unaligned_le32(k->kv_mic + 4);
-                        mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
-                        mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
-                        mic4 = get_unaligned_le32(k->kv_txmic + 4);
-
-                        /* Write RX[31:0] and TX[31:16] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
-
-                        /* Write RX[63:32] and TX[15:0] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
-
-                        /* Write TX[63:32] and keyType(reserved) */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
-                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
-                                  AR_KEYTABLE_TYPE_CLR);
-
-                } else {
-                        /*
-                         * TKIP uses four key cache entries (two for group
-                         * keys):
-                         * Michael MIC TX/RX keys are in different key cache
-                         * entries (idx = main index + 64 for TX and
-                         * main index + 32 + 96 for RX):
-                         * key0 [31:0] = TX/RX MIC key [31:0]
-                         * key1 [31:0] = reserved
-                         * key2 [31:0] = TX/RX MIC key [63:32]
-                         * key3 [31:0] = reserved
-                         * key4 [31:0] = reserved
-                         *
-                         * Upper layer code will call this function separately
-                         * for TX and RX keys when these registers offsets are
-                         * used.
-                         */
-                        u32 mic0, mic2;
-
-                        mic0 = get_unaligned_le32(k->kv_mic + 0);
-                        mic2 = get_unaligned_le32(k->kv_mic + 4);
-
-                        /* Write MIC key[31:0] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
-
-                        /* Write MIC key[63:32] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
-
-                        /* Write TX[63:32] and keyType(reserved) */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
-                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
-                                  AR_KEYTABLE_TYPE_CLR);
-                }
-
-                /* MAC address registers are reserved for the MIC entry */
-                REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
-
-                /*
-                 * Write the correct (un-inverted) key[47:0] last to enable
-                 * TKIP now that all other registers are set with correct
-                 * values.
-                 */
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
-        } else {
-                /* Write key[47:0] */
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
-
-                /* Write key[95:48] */
-                REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
-                REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
-
-                /* Write key[127:96] and key type */
-                REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
-                REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
-
-                /* Write MAC address for the entry */
-                (void) ath9k_hw_keysetmac(ah, entry, mac);
-        }
-
-        return true;
+        return 0;
 }
-EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
+EXPORT_SYMBOL(ath9k_hw_reset);
 
 /******************************/
 /* Power Management (Chipset) */
@@ -1852,9 +1668,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
                                     AR_RTC_FORCE_WAKE_EN);
                 }
                 if (i == 0) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "Failed to wakeup in %uus\n",
-                                  POWER_UP_TIME / 20);
+                        ath_err(ath9k_hw_common(ah),
+                                "Failed to wakeup in %uus\n",
+                                POWER_UP_TIME / 20);
                         return false;
                 }
         }
@@ -1878,8 +1694,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
         if (ah->power_mode == mode)
                 return status;
 
-        ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
-                  modes[ah->power_mode], modes[mode]);
+        ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
+                modes[ah->power_mode], modes[mode]);
 
         switch (mode) {
         case ATH9K_PM_AWAKE:
@@ -1893,12 +1709,20 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
                 ath9k_set_power_network_sleep(ah, setChip);
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unknown power mode %u\n", mode);
+                ath_err(common, "Unknown power mode %u\n", mode);
                 return false;
         }
         ah->power_mode = mode;
 
+        /*
+         * XXX: If this warning never comes up after a while then
+         * simply keep the ATH_DBG_WARN_ON_ONCE() but make
+         * ath9k_hw_setpower() return type void.
+         */
+
+        if (!(ah->ah_flags & AH_UNPLUGGED))
+                ATH_DBG_WARN_ON_ONCE(!status);
+
         return status;
 }
 EXPORT_SYMBOL(ath9k_hw_setpower);
@@ -1911,60 +1735,39 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
 {
         int flags = 0;
 
-        ah->beacon_interval = beacon_period;
-
         ENABLE_REGWRITE_BUFFER(ah);
 
         switch (ah->opmode) {
-        case NL80211_IFTYPE_STATION:
-        case NL80211_IFTYPE_MONITOR:
-                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
-                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
-                REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
-                flags |= AR_TBTT_TIMER_EN;
-                break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
                 REG_SET_BIT(ah, AR_TXCFG,
                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
-                REG_WRITE(ah, AR_NEXT_NDP_TIMER,
-                          TU_TO_USEC(next_beacon +
-                                     (ah->atim_window ? ah->
-                                      atim_window : 1)));
+                REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
+                          TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
                 flags |= AR_NDP_TIMER_EN;
         case NL80211_IFTYPE_AP:
-                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
-                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
-                          TU_TO_USEC(next_beacon -
-                                     ah->config.
-                                     dma_beacon_response_time));
-                REG_WRITE(ah, AR_NEXT_SWBA,
-                          TU_TO_USEC(next_beacon -
-                                     ah->config.
-                                     sw_beacon_response_time));
+                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
+                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
+                          TU_TO_USEC(ah->config.dma_beacon_response_time));
+                REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
+                          TU_TO_USEC(ah->config.sw_beacon_response_time));
                 flags |=
                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
-                          "%s: unsupported opmode: %d\n",
-                          __func__, ah->opmode);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
+                        "%s: unsupported opmode: %d\n",
+                        __func__, ah->opmode);
                 return;
                 break;
         }
 
-        REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
-        REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
-        REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
-        REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
+        REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
+        REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
+        REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
+        REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
-
-        beacon_period &= ~ATH9K_BEACON_ENA;
-        if (beacon_period & ATH9K_BEACON_RESET_TSF) {
-                ath9k_hw_reset_tsf(ah);
-        }
 
         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
 }
@@ -1987,7 +1790,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         REG_RMW_FIELD(ah, AR_RSSI_THR,
                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
@@ -2006,10 +1808,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
         else
                 nextTbtt = bs->bs_nexttbtt;
 
-        ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
-        ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
-        ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
-        ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
+        ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
+        ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
+        ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
+        ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -2033,7 +1835,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         REG_SET_BIT(ah, AR_TIMER_MODE,
                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
@@ -2055,18 +1856,17 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
-        u16 capField = 0, eeval;
+        u16 eeval;
+        u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
         regulatory->current_rd = eeval;
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
-        if (AR_SREV_9285_10_OR_LATER(ah))
+        if (AR_SREV_9285_12_OR_LATER(ah))
                 eeval |= AR9285_RDEXT_DEFAULT;
         regulatory->current_rd_ext = eeval;
 
-        capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
-
         if (ah->opmode != NL80211_IFTYPE_AP &&
             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
                 if (regulatory->current_rd == 0x64 ||
@@ -2074,48 +1874,22 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                         regulatory->current_rd += 5;
                 else if (regulatory->current_rd == 0x41)
                         regulatory->current_rd = 0x43;
-                ath_print(common, ATH_DBG_REGULATORY,
-                          "regdomain mapped to 0x%x\n", regulatory->current_rd);
+                ath_dbg(common, ATH_DBG_REGULATORY,
+                        "regdomain mapped to 0x%x\n", regulatory->current_rd);
         }
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "no band has been marked as supported in EEPROM.\n");
+                ath_err(common,
+                        "no band has been marked as supported in EEPROM\n");
                 return -EINVAL;
         }
 
-        bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
+        if (eeval & AR5416_OPFLAGS_11A)
+                pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
 
-        if (eeval & AR5416_OPFLAGS_11A) {
-                set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
-                if (ah->config.ht_enable) {
-                        if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
-                                set_bit(ATH9K_MODE_11NA_HT20,
-                                        pCap->wireless_modes);
-                        if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
-                                set_bit(ATH9K_MODE_11NA_HT40PLUS,
-                                        pCap->wireless_modes);
-                                set_bit(ATH9K_MODE_11NA_HT40MINUS,
-                                        pCap->wireless_modes);
-                        }
-                }
-        }
-
-        if (eeval & AR5416_OPFLAGS_11G) {
-                set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
-                if (ah->config.ht_enable) {
-                        if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
-                                set_bit(ATH9K_MODE_11NG_HT20,
-                                        pCap->wireless_modes);
-                        if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
-                                set_bit(ATH9K_MODE_11NG_HT40PLUS,
-                                        pCap->wireless_modes);
-                                set_bit(ATH9K_MODE_11NG_HT40MINUS,
-                                        pCap->wireless_modes);
-                        }
-                }
-        }
+        if (eeval & AR5416_OPFLAGS_11G)
+                pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
 
         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
         /*
@@ -2127,63 +1901,32 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
             !(AR_SREV_9271(ah)))
                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
+        else if (AR_SREV_9100(ah))
+                pCap->rx_chainmask = 0x7;
         else
                 /* Use rx_chainmask from EEPROM. */
                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
 
-        if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
-                ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
+        ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
 
-        pCap->low_2ghz_chan = 2312;
-        pCap->high_2ghz_chan = 2732;
-
-        pCap->low_5ghz_chan = 4920;
-        pCap->high_5ghz_chan = 6100;
-
-        pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
+        /* enable key search for every frame in an aggregate */
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
 
-        pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
+        common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
 
-        if (ah->config.ht_enable)
+        if (ah->hw_version.devid != AR2427_DEVID_PCIE)
                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
         else
                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
 
-        pCap->hw_caps |= ATH9K_HW_CAP_GTT;
-        pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
-        pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
-        pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
-
-        if (capField & AR_EEPROM_EEPCAP_MAXQCU)
-                pCap->total_queues =
-                        MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
-        else
-                pCap->total_queues = ATH9K_NUM_TX_QUEUES;
-
-        if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
-                pCap->keycache_size =
-                        1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
-        else
-                pCap->keycache_size = AR_KEYTABLE_SIZE;
-
-        pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
-
-        if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
-                pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
-        else
-                pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
-
         if (AR_SREV_9271(ah))
                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
         else if (AR_DEVID_7010(ah))
                 pCap->num_gpio_pins = AR7010_NUM_GPIO;
-        else if (AR_SREV_9285_10_OR_LATER(ah))
+        else if (AR_SREV_9285_12_OR_LATER(ah))
                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
-        else if (AR_SREV_9280_10_OR_LATER(ah))
+        else if (AR_SREV_9280_20_OR_LATER(ah))
                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
         else
                 pCap->num_gpio_pins = AR_NUM_GPIO;
@@ -2195,8 +1938,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                 pCap->rts_aggr_limit = (8 * 1024);
         }
 
-        pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
-
 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
@@ -2218,52 +1959,40 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         else
                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
 
-        if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
-                pCap->reg_cap =
-                        AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
-                        AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
-                        AR_EEPROM_EEREGCAP_EN_KK_U2 |
-                        AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
-        } else {
-                pCap->reg_cap =
-                        AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
-                        AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
-        }
-
-        /* Advertise midband for AR5416 with FCC midband set in eeprom */
-        if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
-            AR_SREV_5416(ah))
-                pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
-
-        pCap->num_antcfg_5ghz =
-                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
-        pCap->num_antcfg_2ghz =
-                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
-
-        if (AR_SREV_9280_10_OR_LATER(ah) &&
-            ath9k_hw_btcoex_supported(ah)) {
-                btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
-                btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
-
-                if (AR_SREV_9285(ah)) {
+        if (common->btcoex_enabled) {
+                if (AR_SREV_9300_20_OR_LATER(ah)) {
                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
-                        btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
-                } else {
-                        btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
+                        btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
+                        btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
+                        btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
+                } else if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
+                        btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
+
+                        if (AR_SREV_9285(ah)) {
+                                btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
+                                btcoex_hw->btpriority_gpio =
+                                                ATH_BTPRIORITY_GPIO_9285;
+                        } else {
+                                btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
+                        }
                 }
         } else {
                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
         }
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
-                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
-                                 ATH9K_HW_CAP_FASTCLOCK;
+                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
+                if (!AR_SREV_9485(ah))
+                        pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
+
                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
                 pCap->txs_len = sizeof(struct ar9003_txs);
-                if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
+                if (!ah->config.paprd_disable &&
+                    ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
                         pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
         } else {
                 pCap->tx_desc_len = sizeof(struct ath_desc);
@@ -2277,9 +2006,59 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         if (AR_SREV_9300_20_OR_LATER(ah))
                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
 
-        if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
+
+        if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
 
+        if (AR_SREV_9285(ah))
+                if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
+                        ant_div_ctl1 =
+                                ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                        if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
+                                pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
+                }
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
+                        pCap->hw_caps |= ATH9K_HW_CAP_APM;
+        }
+
+
+        if (AR_SREV_9485(ah)) {
+                ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                /*
+                 * enable the diversity-combining algorithm only when
+                 * both enable_lna_div and enable_fast_div are set
+                 *              Table for Diversity
+                 * ant_div_alt_lnaconf          bit 0-1
+                 * ant_div_main_lnaconf         bit 2-3
+                 * ant_div_alt_gaintb           bit 4
+                 * ant_div_main_gaintb          bit 5
+                 * enable_ant_div_lnadiv        bit 6
+                 * enable_ant_fast_div          bit 7
+                 */
+                if ((ant_div_ctl1 >> 0x6) == 0x3)
+                        pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
+        }
+
+        if (AR_SREV_9485_10(ah)) {
+                pCap->pcie_lcr_extsync_en = true;
+                pCap->pcie_lcr_offset = 0x80;
+        }
+
+        tx_chainmask = pCap->tx_chainmask;
+        rx_chainmask = pCap->rx_chainmask;
+        while (tx_chainmask || rx_chainmask) {
+                if (tx_chainmask & BIT(0))
+                        pCap->max_txchains++;
+                if (rx_chainmask & BIT(0))
+                        pCap->max_rxchains++;
+
+                tx_chainmask >>= 1;
+                rx_chainmask >>= 1;
+        }
+
         return 0;
 }
 
@@ -2350,14 +2129,15 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
                 val = REG_READ(ah, AR7010_GPIO_IN);
                 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
         } else if (AR_SREV_9300_20_OR_LATER(ah))
-                return MS_REG_READ(AR9300, gpio) != 0;
+                return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
+                        AR_GPIO_BIT(gpio)) != 0;
         else if (AR_SREV_9271(ah))
                 return MS_REG_READ(AR9271, gpio) != 0;
-        else if (AR_SREV_9287_10_OR_LATER(ah))
+        else if (AR_SREV_9287_11_OR_LATER(ah))
                 return MS_REG_READ(AR9287, gpio) != 0;
-        else if (AR_SREV_9285_10_OR_LATER(ah))
+        else if (AR_SREV_9285_12_OR_LATER(ah))
                 return MS_REG_READ(AR9285, gpio) != 0;
-        else if (AR_SREV_9280_10_OR_LATER(ah))
+        else if (AR_SREV_9280_20_OR_LATER(ah))
                 return MS_REG_READ(AR928X, gpio) != 0;
         else
                 return MS_REG_READ(AR, gpio) != 0;
@@ -2449,14 +2229,11 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
         REG_WRITE(ah, AR_PHY_ERR, phybits);
 
         if (phybits)
-                REG_WRITE(ah, AR_RXCFG,
-                          REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+                REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
         else
-                REG_WRITE(ah, AR_RXCFG,
-                          REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
+                REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
 
@@ -2483,7 +2260,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_disable);
 
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath9k_channel *chan = ah->curchan;
@@ -2496,7 +2273,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), test);
 }
 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
 
@@ -2556,8 +2333,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
 {
         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
                            AH_TSF_WRITE_TIMEOUT))
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
 
         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
 }
@@ -2648,9 +2425,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
 
         if (timer == NULL) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Failed to allocate memory"
-                          "for hw timer[%d]\n", timer_index);
+                ath_err(ath9k_hw_common(ah),
+                        "Failed to allocate memory for hw timer[%d]\n",
+                        timer_index);
                 return NULL;
         }
 
@@ -2667,11 +2444,11 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
 
 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
                               struct ath_gen_timer *timer,
-                              u32 timer_next,
+                              u32 trig_timeout,
                               u32 timer_period)
 {
         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
-        u32 tsf;
+        u32 tsf, timer_next;
 
         BUG_ON(!timer_period);
 
@@ -2679,16 +2456,11 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 
         tsf = ath9k_hw_gettsf32(ah);
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
-                  "curent tsf %x period %x"
-                  "timer_next %x\n", tsf, timer_period, timer_next);
+        timer_next = tsf + trig_timeout;
 
-        /*
-         * Pull timer_next forward if the current TSF already passed it
-         * because of software latency
-         */
-        if (timer_next < tsf)
-                timer_next = tsf + timer_period;
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
+                "current tsf %x period %x timer_next %x\n",
+                tsf, timer_period, timer_next);
 
         /*
          * Program generic timer registers
@@ -2761,8 +2533,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
                 index = rightmost_index(timer_table, &thresh_mask);
                 timer = timer_table->timers[index];
                 BUG_ON(!timer);
-                ath_print(common, ATH_DBG_HWTIMER,
-                          "TSF overflow for Gen timer %d\n", index);
+                ath_dbg(common, ATH_DBG_HWTIMER,
+                        "TSF overflow for Gen timer %d\n", index);
                 timer->overflow(timer->arg);
         }
 
@@ -2770,8 +2542,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
                 index = rightmost_index(timer_table, &trigger_mask);
                 timer = timer_table->timers[index];
                 BUG_ON(!timer);
-                ath_print(common, ATH_DBG_HWTIMER,
-                          "Gen timer[%d] trigger\n", index);
+                ath_dbg(common, ATH_DBG_HWTIMER,
+                        "Gen timer[%d] trigger\n", index);
                 timer->trigger(timer->arg);
         }
 }
@@ -2802,6 +2574,7 @@ static struct {
         { AR_SREV_VERSION_9287,         "9287" },
         { AR_SREV_VERSION_9271,         "9271" },
         { AR_SREV_VERSION_9300,         "9300" },
+        { AR_SREV_VERSION_9485,         "9485" },
 };
 
 /* For devices with external radios */
@@ -2854,7 +2627,7 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
         int used;
 
         /* chipsets >= AR9280 are single-chip */
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 used = snprintf(hw_name, len,
                                "Atheros AR%s Rev:%x",
                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 399f7c1283cd..4b157c53d1a8 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -30,7 +30,6 @@
 #include "btcoex.h"
 
 #include "../regd.h"
-#include "../debug.h"
 
 #define ATHEROS_VENDOR_ID       0x168c
 
@@ -44,6 +43,8 @@
 #define AR9287_DEVID_PCI        0x002d
 #define AR9287_DEVID_PCIE       0x002e
 #define AR9300_DEVID_PCIE       0x0030
+#define AR9300_DEVID_AR9340     0x0031
+#define AR9300_DEVID_AR9485_PCIE 0x0032
 
 #define AR5416_AR9100_DEVID     0x000b
 
@@ -55,64 +56,62 @@
 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
 
+#define AR9300_NUM_BT_WEIGHTS   4
+#define AR9300_NUM_WLAN_WEIGHTS 4
+
 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 
 #define ATH_DEFAULT_NOISE_FLOOR -95
 
 #define ATH9K_RSSI_BAD                  -128
 
+#define ATH9K_NUM_CHANNELS      38
+
 /* Register read/write primitives */
 #define REG_WRITE(_ah, _reg, _val) \
-        ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
+        (_ah)->reg_ops.write((_ah), (_val), (_reg))
 
 #define REG_READ(_ah, _reg) \
-        ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
+        (_ah)->reg_ops.read((_ah), (_reg))
 
-#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
-        do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
-        } while (0)
+#define REG_READ_MULTI(_ah, _addr, _val, _cnt)          \
+        (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
+
+#define REG_RMW(_ah, _reg, _set, _clr) \
+        (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
 
-#define DISABLE_REGWRITE_BUFFER(_ah)                                    \
+#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
         do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
+                if ((_ah)->reg_ops.enable_write_buffer) \
+                        (_ah)->reg_ops.enable_write_buffer((_ah)); \
         } while (0)
 
 #define REGWRITE_BUFFER_FLUSH(_ah)                                      \
         do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->write_flush((_ah));  \
+                if ((_ah)->reg_ops.write_flush)         \
+                        (_ah)->reg_ops.write_flush((_ah));      \
         } while (0)
 
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
-#define REG_RMW(_a, _r, _set, _clr)    \
-        REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
 #define REG_RMW_FIELD(_a, _r, _f, _v) \
-        REG_WRITE(_a, _r, \
-        (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
+        REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
 #define REG_READ_FIELD(_a, _r, _f) \
         (((REG_READ(_a, _r) & _f) >> _f##_S))
 #define REG_SET_BIT(_a, _r, _f) \
-        REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
+        REG_RMW(_a, _r, (_f), 0)
 #define REG_CLR_BIT(_a, _r, _f) \
-        REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
+        REG_RMW(_a, _r, 0, (_f))
 
-#define DO_DELAY(x) do {                        \
-                if ((++(x) % 64) == 0)          \
-                        udelay(1);              \
+#define DO_DELAY(x) do {                                        \
+                if (((++(x) % 64) == 0) &&                      \
+                    (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
+                        != ATH_USB))                            \
+                        udelay(1);                              \
         } while (0)
 
-#define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
-                int r;                                                  \
-                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
-                        REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
-                                  INI_RA((iniarray), r, (column)));     \
-                        DO_DELAY(regWr);                                \
-                }                                                       \
-        } while (0)
+#define REG_WRITE_ARRAY(iniarray, column, regWr) \
+        ath9k_hw_write_array(ah, iniarray, column, &(regWr))
 
 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
@@ -126,7 +125,7 @@
 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 
 #define BASE_ACTIVATE_DELAY         100
-#define RTC_PLL_SETTLE_DELAY        100
+#define RTC_PLL_SETTLE_DELAY        (AR_SREV_9340(ah) ? 1000 : 100)
 #define COEF_SCALE_S                24
 #define HT40_CHANNEL_CENTER_SHIFT   10
 
@@ -161,6 +160,13 @@
 #define PAPRD_GAIN_TABLE_ENTRIES    32
 #define PAPRD_TABLE_SZ              24
 
+enum ath_hw_txq_subtype {
+        ATH_TXQ_AC_BE = 0,
+        ATH_TXQ_AC_BK = 1,
+        ATH_TXQ_AC_VI = 2,
+        ATH_TXQ_AC_VO = 3,
+};
+
 enum ath_ini_subsys {
         ATH_INI_PRE = 0,
         ATH_INI_CORE,
@@ -168,64 +174,39 @@ enum ath_ini_subsys {
         ATH_INI_NUM_SPLIT,
 };
 
-enum wireless_mode {
-        ATH9K_MODE_11A = 0,
-        ATH9K_MODE_11G,
-        ATH9K_MODE_11NA_HT20,
-        ATH9K_MODE_11NG_HT20,
-        ATH9K_MODE_11NA_HT40PLUS,
-        ATH9K_MODE_11NA_HT40MINUS,
-        ATH9K_MODE_11NG_HT40PLUS,
-        ATH9K_MODE_11NG_HT40MINUS,
-        ATH9K_MODE_MAX,
-};
-
 enum ath9k_hw_caps {
-        ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
-        ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
-        ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
-        ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
-        ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
-        ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
-        ATH9K_HW_CAP_VEOL                       = BIT(6),
-        ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
-        ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
-        ATH9K_HW_CAP_HT                         = BIT(9),
-        ATH9K_HW_CAP_GTT                        = BIT(10),
-        ATH9K_HW_CAP_FASTCC                     = BIT(11),
-        ATH9K_HW_CAP_RFSILENT                   = BIT(12),
-        ATH9K_HW_CAP_CST                        = BIT(13),
-        ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
-        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
-        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
-        ATH9K_HW_CAP_EDMA                       = BIT(17),
-        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(18),
-        ATH9K_HW_CAP_LDPC                       = BIT(19),
-        ATH9K_HW_CAP_FASTCLOCK                  = BIT(20),
-        ATH9K_HW_CAP_SGI_20                     = BIT(21),
-        ATH9K_HW_CAP_PAPRD                      = BIT(22),
+        ATH9K_HW_CAP_HT                         = BIT(0),
+        ATH9K_HW_CAP_RFSILENT                   = BIT(1),
+        ATH9K_HW_CAP_CST                        = BIT(2),
+        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
+        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
+        ATH9K_HW_CAP_EDMA                       = BIT(6),
+        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(7),
+        ATH9K_HW_CAP_LDPC                       = BIT(8),
+        ATH9K_HW_CAP_FASTCLOCK                  = BIT(9),
+        ATH9K_HW_CAP_SGI_20                     = BIT(10),
+        ATH9K_HW_CAP_PAPRD                      = BIT(11),
+        ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
+        ATH9K_HW_CAP_2GHZ                       = BIT(13),
+        ATH9K_HW_CAP_5GHZ                       = BIT(14),
+        ATH9K_HW_CAP_APM                        = BIT(15),
 };
 
 struct ath9k_hw_capabilities {
         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
-        DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
-        u16 total_queues;
-        u16 keycache_size;
-        u16 low_5ghz_chan, high_5ghz_chan;
-        u16 low_2ghz_chan, high_2ghz_chan;
         u16 rts_aggr_limit;
         u8 tx_chainmask;
         u8 rx_chainmask;
-        u16 tx_triglevel_max;
-        u16 reg_cap;
+        u8 max_txchains;
+        u8 max_rxchains;
         u8 num_gpio_pins;
-        u8 num_antcfg_2ghz;
-        u8 num_antcfg_5ghz;
         u8 rx_hp_qdepth;
         u8 rx_lp_qdepth;
         u8 rx_status_len;
         u8 tx_desc_len;
         u8 txs_len;
+        u16 pcie_lcr_offset;
+        bool pcie_lcr_extsync_en;
 };
 
 struct ath9k_ops_config {
@@ -239,7 +220,7 @@ struct ath9k_ops_config {
         u8 pcie_clock_req;
         u32 pcie_waen;
         u8 analog_shiftreg;
-        u8 ht_enable;
+        u8 paprd_disable;
         u32 ofdm_trig_low;
         u32 ofdm_trig_high;
         u32 cck_trig_high;
@@ -251,7 +232,6 @@ struct ath9k_ops_config {
 #define SPUR_DISABLE            0
 #define SPUR_ENABLE_IOCTL       1
 #define SPUR_ENABLE_EEPROM      2
-#define AR_EEPROM_MODAL_SPURS   5
 #define AR_SPUR_5413_1          1640
 #define AR_SPUR_5413_2          1200
 #define AR_NO_SPUR              0x8000
@@ -352,9 +332,9 @@ struct ath9k_hw_cal_data {
         int32_t CalValid;
         int8_t iCoff;
         int8_t qCoff;
-        int16_t rawNoiseFloor;
         bool paprd_done;
         bool nfcal_pending;
+        bool nfcal_interference;
         u16 small_signal_gain[AR9300_MAX_CHAINS];
         u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
@@ -362,9 +342,11 @@ struct ath9k_hw_cal_data {
 
 struct ath9k_channel {
         struct ieee80211_channel *chan;
+        struct ar5416AniState ani;
         u16 channel;
         u32 channelFlags;
         u32 chanmode;
+        s16 noisefloor;
 };
 
 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
@@ -422,8 +404,6 @@ struct ath9k_beacon_state {
         u32 bs_nextdtim;
         u32 bs_intval;
 #define ATH9K_BEACON_PERIOD       0x0000ffff
-#define ATH9K_BEACON_ENA          0x00800000
-#define ATH9K_BEACON_RESET_TSF    0x01000000
 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
         u32 bs_dtimperiod;
         u16 bs_cfpperiod;
@@ -457,6 +437,7 @@ struct ath9k_hw_version {
         u16 analog5GhzRev;
         u16 analog2GhzRev;
         u16 subsysid;
+        enum ath_usb_dev usbdev;
 };
 
 /* Generic TSF timer definitions */
@@ -494,6 +475,50 @@ struct ath_gen_timer_table {
         } timer_mask;
 };
 
+struct ath_hw_antcomb_conf {
+        u8 main_lna_conf;
+        u8 alt_lna_conf;
+        u8 fast_div_bias;
+        u8 main_gaintb;
+        u8 alt_gaintb;
+        int lna1_lna2_delta;
+        u8 div_group;
+};
+
+/**
+ * struct ath_hw_radar_conf - radar detection initialization parameters
+ *
+ * @pulse_inband: threshold for checking the ratio of in-band power
+ *      to total power for short radar pulses (half dB steps)
+ * @pulse_inband_step: threshold for checking an in-band power to total
+ *      power ratio increase for short radar pulses (half dB steps)
+ * @pulse_height: threshold for detecting the beginning of a short
+ *      radar pulse (dB step)
+ * @pulse_rssi: threshold for detecting if a short radar pulse is
+ *      gone (dB step)
+ * @pulse_maxlen: maximum pulse length (0.8 us steps)
+ *
+ * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
+ * @radar_inband: threshold for checking the ratio of in-band power
+ *      to total power for long radar pulses (half dB steps)
+ * @fir_power: threshold for detecting the end of a long radar pulse (dB)
+ *
+ * @ext_channel: enable extension channel radar detection
+ */
+struct ath_hw_radar_conf {
+        unsigned int pulse_inband;
+        unsigned int pulse_inband_step;
+        unsigned int pulse_height;
+        unsigned int pulse_rssi;
+        unsigned int pulse_maxlen;
+
+        unsigned int radar_rssi;
+        unsigned int radar_inband;
+        int fir_power;
+
+        bool ext_channel;
+};
+
 /**
  * struct ath_hw_private_ops - callbacks used internally by hardware code
  *
@@ -505,7 +530,6 @@ struct ath_gen_timer_table {
  *
  * @init_mode_regs: Initializes mode registers
  * @init_mode_gain_regs: Initialize TX/RX gain registers
- * @macversion_supported: If this specific mac revision is supported
  *
  * @rf_set_freq: change frequency
  * @spur_mitigate_freq: spur mitigation
@@ -517,14 +541,6 @@ struct ath_gen_timer_table {
  * @setup_calibration: set up calibration
  * @iscal_supported: used to query if a type of calibration is supported
  *
- * @ani_reset: reset ANI parameters to default values
- * @ani_lower_immunity: lower the noise immunity level. The level controls
- *      the power-based packet detection on hardware. If a power jump is
- *      detected the adapter takes it as an indication that a packet has
- *      arrived. The level ranges from 0-5. Each level corresponds to a
- *      few dB more of noise immunity. If you have a strong time-varying
- *      interference that is causing false detections (OFDM timing errors or
- *      CCK timing errors) the level can be increased.
  * @ani_cache_ini_regs: cache the values for ANI from the initial
  *      register settings through the register initialization.
  */
@@ -535,11 +551,8 @@ struct ath_hw_private_ops {
 
         void (*init_mode_regs)(struct ath_hw *ah);
         void (*init_mode_gain_regs)(struct ath_hw *ah);
-        bool (*macversion_supported)(u32 macversion);
         void (*setup_calibration)(struct ath_hw *ah,
                                   struct ath9k_cal_list *currCal);
-        bool (*iscal_supported)(struct ath_hw *ah,
-                                enum ath9k_cal_types calType);
 
         /* PHY ops */
         int (*rf_set_freq)(struct ath_hw *ah,
@@ -561,7 +574,6 @@ struct ath_hw_private_ops {
         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
         bool (*rfbus_req)(struct ath_hw *ah);
         void (*rfbus_done)(struct ath_hw *ah);
-        void (*enable_rfkill)(struct ath_hw *ah);
         void (*restore_chainmask)(struct ath_hw *ah);
         void (*set_diversity)(struct ath_hw *ah, bool value);
         u32 (*compute_pll_control)(struct ath_hw *ah,
@@ -569,10 +581,10 @@ struct ath_hw_private_ops {
         bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
                             int param);
         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
+        void (*set_radar_params)(struct ath_hw *ah,
+                                 struct ath_hw_radar_conf *conf);
 
         /* ANI */
-        void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
-        void (*ani_lower_immunity)(struct ath_hw *ah);
         void (*ani_cache_ini_regs)(struct ath_hw *ah);
 };
 
@@ -584,11 +596,6 @@ struct ath_hw_private_ops {
  *
  * @config_pci_powersave:
  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
- *
- * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
- *      thresholds being reached or having overflowed.
- * @ani_monitor: called periodically by the core driver to collect
- *      MIB stats and adjust ANI if specific thresholds have been reached.
  */
 struct ath_hw_ops {
         void (*config_pci_powersave)(struct ath_hw *ah,
@@ -625,13 +632,12 @@ struct ath_hw_ops {
                                    u32 numDelims);
         void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
         void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
-        void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
-                                     u32 burstDuration);
-        void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
-                                       u32 vmf);
+        void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
+        void (*antdiv_comb_conf_get)(struct ath_hw *ah,
+                        struct ath_hw_antcomb_conf *antconf);
+        void (*antdiv_comb_conf_set)(struct ath_hw *ah,
+                        struct ath_hw_antcomb_conf *antconf);
 
-        void (*ani_proc_mib_event)(struct ath_hw *ah);
-        void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
 };
 
 struct ath_nf_limits {
@@ -640,13 +646,19 @@ struct ath_nf_limits {
         s16 nominal;
 };
 
+/* ah_flags */
+#define AH_USE_EEPROM   0x1
+#define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
+
 struct ath_hw {
+        struct ath_ops reg_ops;
+
         struct ieee80211_hw *hw;
         struct ath_common common;
         struct ath9k_hw_version hw_version;
         struct ath9k_ops_config config;
         struct ath9k_hw_capabilities caps;
-        struct ath9k_channel channels[38];
+        struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
         struct ath9k_channel *curchan;
 
         union {
@@ -659,6 +671,7 @@ struct ath_hw {
 
         bool sw_mgmt_crypto;
         bool is_pciexpress;
+        bool is_monitoring;
         bool need_an_top2_fixup;
         u16 tx_trig_level;
 
@@ -692,10 +705,9 @@ struct ath_hw {
         u32 atim_window;
 
         /* Calibration */
-        enum ath9k_cal_types supp_cals;
+        u32 supp_cals;
         struct ath9k_cal_list iq_caldata;
         struct ath9k_cal_list adcgain_caldata;
-        struct ath9k_cal_list adcdc_calinitdata;
         struct ath9k_cal_list adcdc_caldata;
         struct ath9k_cal_list tempCompCalData;
         struct ath9k_cal_list *cal_list;
@@ -755,17 +767,13 @@ struct ath_hw {
         u32 *bank6Temp;
 
         u8 txpower_limit;
-        int16_t txpower_indexoffset;
         int coverage_class;
-        u32 beacon_interval;
         u32 slottime;
         u32 globaltxtimeout;
 
         /* ANI */
         u32 proc_phyerr;
         u32 aniperiod;
-        struct ar5416AniState *curani;
-        struct ar5416AniState ani[255];
         int totalSizeDesired[5];
         int coarse_high[5];
         int coarse_low[5];
@@ -774,15 +782,21 @@ struct ath_hw {
 
         /* Bluetooth coexistance */
         struct ath_btcoex_hw btcoex_hw;
+        u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
+        u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
 
         u32 intr_txqs;
         u8 txchainmask;
         u8 rxchainmask;
 
+        struct ath_hw_radar_conf radar_conf;
+
         u32 originalGain[22];
         int initPDADC;
         int PDADCdelta;
-        u8 led_pin;
+        int led_pin;
+        u32 gpio_mask;
+        u32 gpio_val;
 
         struct ar5416IniArray iniModes;
         struct ar5416IniArray iniCommon;
@@ -798,6 +812,7 @@ struct ath_hw {
         struct ar5416IniArray iniPcieSerdes;
         struct ar5416IniArray iniPcieSerdesLowPower;
         struct ar5416IniArray iniModesAdditional;
+        struct ar5416IniArray iniModesAdditional_40M;
         struct ar5416IniArray iniModesRxGain;
         struct ar5416IniArray iniModesTxGain;
         struct ar5416IniArray iniModes_9271_1_0_only;
@@ -827,7 +842,13 @@ struct ath_hw {
 
         u32 bb_watchdog_last_status;
         u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
+        u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
 
+        unsigned int paprd_target_power;
+        unsigned int paprd_training_power;
+        unsigned int paprd_ratemask;
+        unsigned int paprd_ratemask_ht40;
+        bool paprd_table_write_done;
         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
         /*
@@ -836,6 +857,19 @@ struct ath_hw {
          * this register when in sleep states.
          */
         u32 WARegVal;
+
+        /* Enterprise mode cap */
+        u32 ent_mode;
+
+        bool is_clk_25mhz;
+};
+
+struct ath_bus_ops {
+        enum ath_bus_type ath_bus_type;
+        void (*read_cachesize)(struct ath_common *common, int *csz);
+        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
+        void (*bt_coex_prep)(struct ath_common *common);
+        void (*extn_synch_en)(struct ath_common *common);
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -858,10 +892,9 @@ static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
         return &ah->ops;
 }
 
-static inline int sign_extend(int val, const int nbits)
+static inline u8 get_streams(int mask)
 {
-        int order = BIT(nbits-1);
-        return (val ^ order) - order;
+        return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
 }
 
 /* Initialization, Detach, Reset */
@@ -873,12 +906,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 
-/* Key Cache Management */
-bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
-bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
-                                 const struct ath9k_keyval *k,
-                                 const u8 *mac);
-
 /* GPIO / RFKILL / Antennae */
 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
@@ -890,8 +917,9 @@ void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 
 /* General Operation */
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
+void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                          int column, unsigned int *writecnt);
 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
-bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                            u8 phy, int kbps,
                            u32 frameLen, u16 rateix, bool shortPreamble);
@@ -902,16 +930,18 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 bool ath9k_hw_disable(struct ath_hw *ah);
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
 void ath9k_hw_setopmode(struct ath_hw *ah);
 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 void ath9k_hw_write_associd(struct ath_hw *ah);
+u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 void ath9k_hw_init_global_settings(struct ath_hw *ah);
+u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
@@ -934,7 +964,6 @@ void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 
 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 void ath_gen_timer_isr(struct ath_hw *hw);
-u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 
 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 
@@ -962,6 +991,7 @@ void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
+void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
                                         struct ath9k_hw_cal_data *caldata,
@@ -984,6 +1014,7 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
 void ar9002_hw_attach_ops(struct ath_hw *ah);
 void ar9003_hw_attach_ops(struct ath_hw *ah);
 
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
 /*
  * ANI work can be shared between all families but a next
  * generation implementation of ANI will be used only for AR9003 only
@@ -992,8 +1023,9 @@ void ar9003_hw_attach_ops(struct ath_hw *ah);
  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
  */
 extern int modparam_force_new_ani;
-void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
-void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah);
+void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
+void ath9k_hw_proc_mib_event(struct ath_hw *ah);
+void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
 
 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 #define ATH_PCIE_CAP_LINK_L0S   1
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 243c1775f343..45c585a337e9 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,6 +15,7 @@
  */
 
 #include <linux/slab.h>
+#include <linux/ath9k_platform.h>
 
 #include "ath9k.h"
 
@@ -29,17 +30,23 @@ static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
 module_param_named(debug, ath9k_debug, uint, 0);
 MODULE_PARM_DESC(debug, "Debugging mask");
 
-int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
+int ath9k_modparam_nohwcrypt;
+module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
 
-int led_blink = 1;
+int led_blink;
 module_param_named(blink, led_blink, int, 0444);
 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
 
+static int ath9k_btcoex_enable;
+module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
+MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
+
+bool is_ath9k_unloaded;
 /* We use the hw_value as an index into our private channel structure */
 
 #define CHAN2G(_freq, _idx)  { \
+        .band = IEEE80211_BAND_2GHZ, \
         .center_freq = (_freq), \
         .hw_value = (_idx), \
         .max_power = 20, \
@@ -56,7 +63,7 @@ MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  * on 5 MHz steps, we support the channels which we know
  * we have calibration data for all cards though to make
  * this static */
-static struct ieee80211_channel ath9k_2ghz_chantable[] = {
+static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
         CHAN2G(2412, 0), /* Channel 1 */
         CHAN2G(2417, 1), /* Channel 2 */
         CHAN2G(2422, 2), /* Channel 3 */
@@ -77,7 +84,7 @@ static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  * on 5 MHz steps, we support the channels which we know
  * we have calibration data for all cards though to make
  * this static */
-static struct ieee80211_channel ath9k_5ghz_chantable[] = {
+static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
         /* _We_ call this UNII 1 */
         CHAN5G(5180, 14), /* Channel 36 */
         CHAN5G(5200, 15), /* Channel 40 */
@@ -134,6 +141,21 @@ static struct ieee80211_rate ath9k_legacy_rates[] = {
         RATE(540, 0x0c, 0),
 };
 
+#ifdef CONFIG_MAC80211_LEDS
+static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
+        { .throughput = 0 * 1024, .blink_time = 334 },
+        { .throughput = 1 * 1024, .blink_time = 260 },
+        { .throughput = 5 * 1024, .blink_time = 220 },
+        { .throughput = 10 * 1024, .blink_time = 190 },
+        { .throughput = 20 * 1024, .blink_time = 170 },
+        { .throughput = 50 * 1024, .blink_time = 150 },
+        { .throughput = 70 * 1024, .blink_time = 130 },
+        { .throughput = 100 * 1024, .blink_time = 110 },
+        { .throughput = 200 * 1024, .blink_time = 80 },
+        { .throughput = 300 * 1024, .blink_time = 50 },
+};
+#endif
+
 static void ath9k_deinit_softc(struct ath_softc *sc);
 
 /*
@@ -174,10 +196,27 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
         return val;
 }
 
-static const struct ath_ops ath9k_common_ops = {
-        .read = ath9k_ioread32,
-        .write = ath9k_iowrite32,
-};
+static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
+{
+        struct ath_hw *ah = (struct ath_hw *) hw_priv;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        unsigned long uninitialized_var(flags);
+        u32 val;
+
+        if (ah->config.serialize_regmode == SER_REG_MODE_ON)
+                spin_lock_irqsave(&sc->sc_serial_rw, flags);
+
+        val = ioread32(sc->mem + reg_offset);
+        val &= ~clr;
+        val |= set;
+        iowrite32(val, sc->mem + reg_offset);
+
+        if (ah->config.serialize_regmode == SER_REG_MODE_ON)
+                spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
+
+        return val;
+}
 
 /**************************/
 /*     Initialization     */
@@ -206,12 +245,14 @@ static void setup_ht_cap(struct ath_softc *sc,
         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 
-        if (AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9485(ah))
+                max_streams = 1;
+        else if (AR_SREV_9300_20_OR_LATER(ah))
                 max_streams = 3;
         else
                 max_streams = 2;
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 if (max_streams >= 2)
                         ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
                 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
@@ -222,9 +263,9 @@ static void setup_ht_cap(struct ath_softc *sc,
         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "TX streams %d, RX streams: %d\n",
-                  tx_streams, rx_streams);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "TX streams %d, RX streams: %d\n",
+                tx_streams, rx_streams);
 
         if (tx_streams != rx_streams) {
                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -242,8 +283,7 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
                               struct regulatory_request *request)
 {
         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
 
         return ath_reg_notifier_apply(wiphy, request, reg);
@@ -267,8 +307,8 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
         struct ath_buf *bf;
         int i, bsize, error, desc_len;
 
-        ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
-                  name, nbuf, ndesc);
+        ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
+                name, nbuf, ndesc);
 
         INIT_LIST_HEAD(head);
 
@@ -279,8 +319,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 
         /* ath_desc must be a multiple of DWORDs */
         if ((desc_len % 4) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "ath_desc not DWORD aligned\n");
+                ath_err(common, "ath_desc not DWORD aligned\n");
                 BUG_ON((desc_len % 4) != 0);
                 error = -ENOMEM;
                 goto fail;
@@ -314,9 +353,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
                 goto fail;
         }
         ds = (u8 *) dd->dd_desc;
-        ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
-                  name, ds, (u32) dd->dd_desc_len,
-                  ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
+        ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
+                name, ds, (u32) dd->dd_desc_len,
+                ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 
         /* allocate buffers */
         bsize = sizeof(struct ath_buf) * nbuf;
@@ -362,26 +401,20 @@ fail:
 #undef DS2PHYS
 }
 
-static void ath9k_init_crypto(struct ath_softc *sc)
+void ath9k_init_crypto(struct ath_softc *sc)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
         /* Get the hardware key cache size. */
-        common->keymax = sc->sc_ah->caps.keycache_size;
-        if (common->keymax > ATH_KEYMAX) {
-                ath_print(common, ATH_DBG_ANY,
-                          "Warning, using only %u entries in %u key cache\n",
-                          ATH_KEYMAX, common->keymax);
-                common->keymax = ATH_KEYMAX;
-        }
+        common->keymax = AR_KEYTABLE_SIZE;
 
         /*
          * Reset the key cache since some parts do not
          * reset the contents on initial power up.
          */
         for (i = 0; i < common->keymax; i++)
-                ath9k_hw_keyreset(sc->sc_ah, (u16) i);
+                ath_hw_keyreset(common, (u16) i);
 
         /*
          * Check whether the separate key cache entries
@@ -389,13 +422,14 @@ static void ath9k_init_crypto(struct ath_softc *sc)
          * With split mic keys the number of stations is limited
          * to 27 otherwise 59.
          */
-        if (!(sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA))
-                common->splitmic = 1;
+        if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
+                common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
 }
 
 static int ath9k_init_btcoex(struct ath_softc *sc)
 {
-        int r, qnum;
+        struct ath_txq *txq;
+        int r;
 
         switch (sc->sc_ah->btcoex_hw.scheme) {
         case ATH_BTCOEX_CFG_NONE:
@@ -408,8 +442,8 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
                 r = ath_init_btcoex_timer(sc);
                 if (r)
                         return -1;
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
+                txq = sc->tx.txq_map[WME_AC_BE];
+                ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
                 break;
         default:
@@ -422,65 +456,36 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
 
 static int ath9k_init_queues(struct ath_softc *sc)
 {
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
-        for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
-                sc->tx.hwq_map[i] = -1;
-
         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
-        if (sc->beacon.beaconq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup a beacon xmit queue\n");
-                goto err;
-        }
-
         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
-        if (sc->beacon.cabq == NULL) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup CAB xmit queue\n");
-                goto err;
-        }
 
         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
         ath_cabq_update(sc);
 
-        if (!ath_tx_setup(sc, WME_AC_BK)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BK traffic\n");
-                goto err;
-        }
-
-        if (!ath_tx_setup(sc, WME_AC_BE)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BE traffic\n");
-                goto err;
-        }
-        if (!ath_tx_setup(sc, WME_AC_VI)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VI traffic\n");
-                goto err;
-        }
-        if (!ath_tx_setup(sc, WME_AC_VO)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VO traffic\n");
-                goto err;
+        for (i = 0; i < WME_NUM_AC; i++) {
+                sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
+                sc->tx.txq_map[i]->mac80211_qnum = i;
         }
-
         return 0;
-
-err:
-        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
-                if (ATH_TXQ_SETUP(sc, i))
-                        ath_tx_cleanupq(sc, &sc->tx.txq[i]);
-
-        return -EIO;
 }
 
-static void ath9k_init_channels_rates(struct ath_softc *sc)
+static int ath9k_init_channels_rates(struct ath_softc *sc)
 {
-        if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
-                sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
+        void *channels;
+
+        BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
+                     ARRAY_SIZE(ath9k_5ghz_chantable) !=
+                     ATH9K_NUM_CHANNELS);
+
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
+                channels = kmemdup(ath9k_2ghz_chantable,
+                        sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
+                if (!channels)
+                    return -ENOMEM;
+
+                sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
                 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
                 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
                         ARRAY_SIZE(ath9k_2ghz_chantable);
@@ -489,8 +494,16 @@ static void ath9k_init_channels_rates(struct ath_softc *sc)
                         ARRAY_SIZE(ath9k_legacy_rates);
         }
 
-        if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
-                sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
+                channels = kmemdup(ath9k_5ghz_chantable,
+                        sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
+                if (!channels) {
+                        if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
+                                kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
+                        return -ENOMEM;
+                }
+
+                sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
                         ARRAY_SIZE(ath9k_5ghz_chantable);
@@ -499,6 +512,7 @@ static void ath9k_init_channels_rates(struct ath_softc *sc)
                 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
         }
+        return 0;
 }
 
 static void ath9k_init_misc(struct ath_softc *sc)
@@ -506,7 +520,6 @@ static void ath9k_init_misc(struct ath_softc *sc)
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
-        common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
 
         sc->config.txpowlimit = ATH_TXPOWER_MAX;
@@ -522,20 +535,21 @@ static void ath9k_init_misc(struct ath_softc *sc)
         ath9k_hw_set_diversity(sc->sc_ah, true);
         sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
 
-        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
+        memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 
         sc->beacon.slottime = ATH9K_SLOT_TIME_9;
 
-        for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
+        for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
                 sc->beacon.bslot[i] = NULL;
-                sc->beacon.bslot_aphy[i] = NULL;
-        }
+
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
+                sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
 }
 
 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
                             const struct ath_bus_ops *bus_ops)
 {
+        struct ath9k_platform_data *pdata = sc->dev->platform_data;
         struct ath_hw *ah = NULL;
         struct ath_common *common;
         int ret = 0, i;
@@ -545,23 +559,41 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (!ah)
                 return -ENOMEM;
 
+        ah->hw = sc->hw;
         ah->hw_version.devid = devid;
         ah->hw_version.subsysid = subsysid;
+        ah->reg_ops.read = ath9k_ioread32;
+        ah->reg_ops.write = ath9k_iowrite32;
+        ah->reg_ops.rmw = ath9k_reg_rmw;
         sc->sc_ah = ah;
 
+        if (!pdata) {
+                ah->ah_flags |= AH_USE_EEPROM;
+                sc->sc_ah->led_pin = -1;
+        } else {
+                sc->sc_ah->gpio_mask = pdata->gpio_mask;
+                sc->sc_ah->gpio_val = pdata->gpio_val;
+                sc->sc_ah->led_pin = pdata->led_pin;
+                ah->is_clk_25mhz = pdata->is_clk_25mhz;
+        }
+
         common = ath9k_hw_common(ah);
-        common->ops = &ath9k_common_ops;
+        common->ops = &ah->reg_ops;
         common->bus_ops = bus_ops;
         common->ah = ah;
         common->hw = sc->hw;
         common->priv = sc;
         common->debug_mask = ath9k_debug;
+        common->btcoex_enabled = ath9k_btcoex_enable == 1;
+        spin_lock_init(&common->cc_lock);
 
-        spin_lock_init(&sc->wiphy_lock);
-        spin_lock_init(&sc->sc_resetlock);
         spin_lock_init(&sc->sc_serial_rw);
         spin_lock_init(&sc->sc_pm_lock);
         mutex_init(&sc->mutex);
+#ifdef CONFIG_ATH9K_DEBUGFS
+        spin_lock_init(&sc->nodes_lock);
+        INIT_LIST_HEAD(&sc->nodes);
+#endif
         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
                      (unsigned long)sc);
@@ -578,12 +610,8 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (ret)
                 goto err_hw;
 
-        ret = ath9k_init_debug(ah);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to create debugfs files\n");
-                goto err_debug;
-        }
+        if (pdata && pdata->macaddr)
+                memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
 
         ret = ath9k_init_queues(sc);
         if (ret)
@@ -593,8 +621,11 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (ret)
                 goto err_btcoex;
 
+        ret = ath9k_init_channels_rates(sc);
+        if (ret)
+                goto err_btcoex;
+
         ath9k_init_crypto(sc);
-        ath9k_init_channels_rates(sc);
         ath9k_init_misc(sc);
 
         return 0;
@@ -604,12 +635,8 @@ err_btcoex:
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 err_queues:
-        ath9k_exit_debug(ah);
-err_debug:
         ath9k_hw_deinit(ah);
 err_hw:
-        tasklet_kill(&sc->intr_tq);
-        tasklet_kill(&sc->bcon_tasklet);
 
         kfree(ah);
         sc->sc_ah = NULL;
@@ -617,6 +644,37 @@ err_hw:
         return ret;
 }
 
+static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
+{
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *chan;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
+        int i;
+
+        sband = &sc->sbands[band];
+        for (i = 0; i < sband->n_channels; i++) {
+                chan = &sband->channels[i];
+                ah->curchan = &ah->channels[chan->hw_value];
+                ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
+                ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
+                chan->max_power = reg->max_power_level / 2;
+        }
+}
+
+static void ath9k_init_txpower_limits(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *curchan = ah->curchan;
+
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
+                ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
+                ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
+
+        ah->curchan = curchan;
+}
+
 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -632,16 +690,22 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
                  hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
 
-        if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
+        if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
 
         hw->wiphy->interface_modes =
+                BIT(NL80211_IFTYPE_P2P_GO) |
+                BIT(NL80211_IFTYPE_P2P_CLIENT) |
                 BIT(NL80211_IFTYPE_AP) |
+                BIT(NL80211_IFTYPE_WDS) |
                 BIT(NL80211_IFTYPE_STATION) |
                 BIT(NL80211_IFTYPE_ADHOC) |
                 BIT(NL80211_IFTYPE_MESH_POINT);
 
-        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        if (AR_SREV_5416(sc->sc_ah))
+                hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+
+        hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
 
         hw->queues = 4;
         hw->max_rates = 4;
@@ -651,19 +715,21 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         hw->sta_data_size = sizeof(struct ath_node);
         hw->vif_data_size = sizeof(struct ath_vif);
 
+#ifdef CONFIG_ATH9K_RATE_CONTROL
         hw->rate_control_algorithm = "ath9k_rate_control";
+#endif
 
-        if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &sc->sbands[IEEE80211_BAND_2GHZ];
-        if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
                         &sc->sbands[IEEE80211_BAND_5GHZ];
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
-                if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
+                if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
-                if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
+                if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
         }
 
@@ -706,11 +772,26 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (error != 0)
                 goto error_rx;
 
+        ath9k_init_txpower_limits(sc);
+
+#ifdef CONFIG_MAC80211_LEDS
+        /* must be initialized before ieee80211_register_hw */
+        sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
+                IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
+                ARRAY_SIZE(ath9k_tpt_blink));
+#endif
+
         /* Register with mac80211 */
         error = ieee80211_register_hw(hw);
         if (error)
                 goto error_register;
 
+        error = ath9k_init_debug(ah);
+        if (error) {
+                ath_err(common, "Unable to create debugfs files\n");
+                goto error_world;
+        }
+
         /* Handle world regulatory */
         if (!ath_is_world_regd(reg)) {
                 error = regulatory_hint(hw->wiphy, reg->alpha2);
@@ -720,9 +801,8 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
 
         INIT_WORK(&sc->hw_check_work, ath_hw_check);
         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
-        INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
-        INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
-        sc->wiphy_scheduler_int = msecs_to_jiffies(500);
+        INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
+        sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
 
         ath_init_leds(sc);
         ath_start_rfkill_poll(sc);
@@ -751,6 +831,12 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
 {
         int i = 0;
 
+        if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
+                kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
+
+        if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
+                kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
+
         if ((sc->btcoex.no_stomp_timer) &&
             sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
                 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
@@ -759,12 +845,8 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 
-        ath9k_exit_debug(sc->sc_ah);
         ath9k_hw_deinit(sc->sc_ah);
 
-        tasklet_kill(&sc->intr_tq);
-        tasklet_kill(&sc->bcon_tasklet);
-
         kfree(sc->sc_ah);
         sc->sc_ah = NULL;
 }
@@ -772,27 +854,18 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
 void ath9k_deinit_device(struct ath_softc *sc)
 {
         struct ieee80211_hw *hw = sc->hw;
-        int i = 0;
 
         ath9k_ps_wakeup(sc);
 
         wiphy_rfkill_stop_polling(sc->hw->wiphy);
         ath_deinit_leds(sc);
 
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
-                        continue;
-                sc->sec_wiphy[i] = NULL;
-                ieee80211_unregister_hw(aphy->hw);
-                ieee80211_free_hw(aphy->hw);
-        }
+        ath9k_ps_restore(sc);
 
         ieee80211_unregister_hw(hw);
         ath_rx_cleanup(sc);
         ath_tx_cleanup(sc);
         ath9k_deinit_softc(sc);
-        kfree(sc->sec_wiphy);
 }
 
 void ath_descdma_cleanup(struct ath_softc *sc,
@@ -825,20 +898,12 @@ static int __init ath9k_init(void)
                 goto err_out;
         }
 
-        error = ath9k_debug_create_root();
-        if (error) {
-                printk(KERN_ERR
-                        "ath9k: Unable to create debugfs root: %d\n",
-                        error);
-                goto err_rate_unregister;
-        }
-
         error = ath_pci_init();
         if (error < 0) {
                 printk(KERN_ERR
                         "ath9k: No PCI devices found, driver not installed.\n");
                 error = -ENODEV;
-                goto err_remove_root;
+                goto err_rate_unregister;
         }
 
         error = ath_ahb_init();
@@ -852,8 +917,6 @@ static int __init ath9k_init(void)
  err_pci_exit:
         ath_pci_exit();
 
- err_remove_root:
-        ath9k_debug_remove_root();
  err_rate_unregister:
         ath_rate_control_unregister();
  err_out:
@@ -863,9 +926,9 @@ module_init(ath9k_init);
 
 static void __exit ath9k_exit(void)
 {
+        is_ath9k_unloaded = true;
         ath_ahb_exit();
         ath_pci_exit();
-        ath9k_debug_remove_root();
         ath_rate_control_unregister();
         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
 }
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index e955bb9d98cb..c2091f1f4096 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,11 +20,11 @@
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                                         struct ath9k_tx_queue_info *qi)
 {
-        ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
-                  "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
-                  ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
-                  ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
-                  ah->txurn_interrupt_mask);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
+                "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
+                ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
+                ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
+                ah->txurn_interrupt_mask);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -40,7 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -57,8 +56,8 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf);
 
 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
 {
-        ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
-                  "Enable TXE on queue: %u\n", q);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
+                "Enable TXE on queue: %u\n", q);
         REG_WRITE(ah, AR_Q_TXE, 1 << q);
 }
 EXPORT_SYMBOL(ath9k_hw_txstart);
@@ -118,12 +117,11 @@ EXPORT_SYMBOL(ath9k_hw_numtxpending);
 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
 {
         u32 txcfg, curLevel, newLevel;
-        enum ath9k_int omask;
 
         if (ah->tx_trig_level >= ah->config.max_txtrig_level)
                 return false;
 
-        omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
+        ath9k_hw_disable_interrupts(ah);
 
         txcfg = REG_READ(ah, AR_TXCFG);
         curLevel = MS(txcfg, AR_FTRIG);
@@ -137,7 +135,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
                 REG_WRITE(ah, AR_TXCFG,
                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
 
-        ath9k_hw_set_interrupts(ah, omask);
+        ath9k_hw_enable_interrupts(ah);
 
         ah->tx_trig_level = newLevel;
 
@@ -145,85 +143,59 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
 }
 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
 
-bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
+void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
 {
-#define ATH9K_TX_STOP_DMA_TIMEOUT       4000    /* usec */
-#define ATH9K_TIME_QUANTUM              100     /* usec */
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
-        struct ath9k_tx_queue_info *qi;
-        u32 tsfLow, j, wait;
-        u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
+        int i, q;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
+        REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
 
-        qi = &ah->txq[q];
-        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                          "inactive queue: %u\n", q);
-                return false;
-        }
+        REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
+        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+        REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
 
-        REG_WRITE(ah, AR_Q_TXD, 1 << q);
+        for (q = 0; q < AR_NUM_QCU; q++) {
+                for (i = 0; i < 1000; i++) {
+                        if (i)
+                                udelay(5);
 
-        for (wait = wait_time; wait != 0; wait--) {
-                if (ath9k_hw_numtxpending(ah, q) == 0)
-                        break;
-                udelay(ATH9K_TIME_QUANTUM);
+                        if (!ath9k_hw_numtxpending(ah, q))
+                                break;
+                }
         }
 
-        if (ath9k_hw_numtxpending(ah, q)) {
-                ath_print(common, ATH_DBG_QUEUE,
-                          "%s: Num of pending TX Frames %d on Q %d\n",
-                          __func__, ath9k_hw_numtxpending(ah, q), q);
-
-                for (j = 0; j < 2; j++) {
-                        tsfLow = REG_READ(ah, AR_TSF_L32);
-                        REG_WRITE(ah, AR_QUIET2,
-                                  SM(10, AR_QUIET2_QUIET_DUR));
-                        REG_WRITE(ah, AR_QUIET_PERIOD, 100);
-                        REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
-                        REG_SET_BIT(ah, AR_TIMER_MODE,
-                                       AR_QUIET_TIMER_EN);
-
-                        if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
-                                break;
+        REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
+        REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+        REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
 
-                        ath_print(common, ATH_DBG_QUEUE,
-                                  "TSF has moved while trying to set "
-                                  "quiet time TSF: 0x%08x\n", tsfLow);
-                }
+        REG_WRITE(ah, AR_Q_TXD, 0);
+}
+EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
 
-                REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
+{
+#define ATH9K_TX_STOP_DMA_TIMEOUT       1000    /* usec */
+#define ATH9K_TIME_QUANTUM              100     /* usec */
+        int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
+        int wait;
 
-                udelay(200);
-                REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
+        REG_WRITE(ah, AR_Q_TXD, 1 << q);
 
-                wait = wait_time;
-                while (ath9k_hw_numtxpending(ah, q)) {
-                        if ((--wait) == 0) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Failed to stop TX DMA in 100 "
-                                          "msec after killing last frame\n");
-                                break;
-                        }
+        for (wait = wait_time; wait != 0; wait--) {
+                if (wait != wait_time)
                         udelay(ATH9K_TIME_QUANTUM);
-                }
 
-                REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+                if (ath9k_hw_numtxpending(ah, q) == 0)
+                        break;
         }
 
         REG_WRITE(ah, AR_Q_TXD, 0);
+
         return wait != 0;
 
 #undef ATH9K_TX_STOP_DMA_TIMEOUT
 #undef ATH9K_TIME_QUANTUM
 }
-EXPORT_SYMBOL(ath9k_hw_stoptxdma);
+EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
 
 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
 {
@@ -237,23 +209,16 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
 {
         u32 cw;
         struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath9k_tx_queue_info *qi;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
-
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Set TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
 
         qi->tqi_ver = qinfo->tqi_ver;
         qi->tqi_subtype = qinfo->tqi_subtype;
@@ -308,19 +273,12 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
                             struct ath9k_tx_queue_info *qinfo)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath9k_tx_queue_info *qi;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
-
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Get TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
@@ -348,45 +306,41 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
 {
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info *qi;
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         int q;
 
         switch (type) {
         case ATH9K_TX_QUEUE_BEACON:
-                q = pCap->total_queues - 1;
+                q = ATH9K_NUM_TX_QUEUES - 1;
                 break;
         case ATH9K_TX_QUEUE_CAB:
-                q = pCap->total_queues - 2;
+                q = ATH9K_NUM_TX_QUEUES - 2;
                 break;
         case ATH9K_TX_QUEUE_PSPOLL:
                 q = 1;
                 break;
         case ATH9K_TX_QUEUE_UAPSD:
-                q = pCap->total_queues - 3;
+                q = ATH9K_NUM_TX_QUEUES - 3;
                 break;
         case ATH9K_TX_QUEUE_DATA:
-                for (q = 0; q < pCap->total_queues; q++)
+                for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
                         if (ah->txq[q].tqi_type ==
                             ATH9K_TX_QUEUE_INACTIVE)
                                 break;
-                if (q == pCap->total_queues) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "No available TX queue\n");
+                if (q == ATH9K_NUM_TX_QUEUES) {
+                        ath_err(common, "No available TX queue\n");
                         return -1;
                 }
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "Invalid TX queue type: %u\n", type);
+                ath_err(common, "Invalid TX queue type: %u\n", type);
                 return -1;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
 
         qi = &ah->txq[q];
         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "TX queue: %u already active\n", q);
+                ath_err(common, "TX queue: %u already active\n", q);
                 return -1;
         }
         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -413,23 +367,17 @@ EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
 
 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
 {
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info *qi;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Release TXQ, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
 
         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
         ah->txok_interrupt_mask &= ~(1 << q);
@@ -445,26 +393,19 @@ EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
 
 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
 {
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
         struct ath9k_tx_queue_info *qi;
         u32 cwMin, chanCwMin, value;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
-
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Reset TXQ, inactive queue: %u\n", q);
                 return true;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
 
         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                 if (chan && IS_CHAN_B(chan))
@@ -489,19 +430,21 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                   SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
 
         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
-        REG_WRITE(ah, AR_DMISC(q),
-                  AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
 
-        REGWRITE_BUFFER_FLUSH(ah);
+        if (AR_SREV_9340(ah))
+                REG_WRITE(ah, AR_DMISC(q),
+                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
+        else
+                REG_WRITE(ah, AR_DMISC(q),
+                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
 
         if (qi->tqi_cbrPeriod) {
                 REG_WRITE(ah, AR_QCBRCFG(q),
                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
                           SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
-                REG_WRITE(ah, AR_QMISC(q),
-                          REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
-                          (qi->tqi_cbrOverflowLimit ?
-                           AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
+                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
+                            (qi->tqi_cbrOverflowLimit ?
+                             AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
         }
         if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
@@ -509,51 +452,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                           AR_Q_RDYTIMECFG_EN);
         }
 
-        REGWRITE_BUFFER_FLUSH(ah);
-
         REG_WRITE(ah, AR_DCHNTIME(q),
                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
 
         if (qi->tqi_burstTime
-            && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
-                REG_WRITE(ah, AR_QMISC(q),
-                          REG_READ(ah, AR_QMISC(q)) |
-                          AR_Q_MISC_RDYTIME_EXP_POLICY);
+            && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
+                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
 
-        }
-
-        if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
-                REG_WRITE(ah, AR_DMISC(q),
-                          REG_READ(ah, AR_DMISC(q)) |
-                          AR_D_MISC_POST_FR_BKOFF_DIS);
-        }
+        if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
+                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
-        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
-                REG_WRITE(ah, AR_DMISC(q),
-                          REG_READ(ah, AR_DMISC(q)) |
-                          AR_D_MISC_FRAG_BKOFF_EN);
-        }
+        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
+                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
+
         switch (qi->tqi_type) {
         case ATH9K_TX_QUEUE_BEACON:
                 ENABLE_REGWRITE_BUFFER(ah);
 
-                REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
-                          | AR_Q_MISC_FSP_DBA_GATED
-                          | AR_Q_MISC_BEACON_USE
-                          | AR_Q_MISC_CBR_INCR_DIS1);
+                REG_SET_BIT(ah, AR_QMISC(q),
+                            AR_Q_MISC_FSP_DBA_GATED
+                            | AR_Q_MISC_BEACON_USE
+                            | AR_Q_MISC_CBR_INCR_DIS1);
 
-                REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
-                          | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
+                REG_SET_BIT(ah, AR_DMISC(q),
+                            (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
-                          | AR_D_MISC_BEACON_USE
-                          | AR_D_MISC_POST_FR_BKOFF_DIS);
+                            | AR_D_MISC_BEACON_USE
+                            | AR_D_MISC_POST_FR_BKOFF_DIS);
 
                 REGWRITE_BUFFER_FLUSH(ah);
-                DISABLE_REGWRITE_BUFFER(ah);
 
                 /*
                  * cwmin and cwmax should be 0 for beacon queue
@@ -570,42 +500,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
         case ATH9K_TX_QUEUE_CAB:
                 ENABLE_REGWRITE_BUFFER(ah);
 
-                REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
-                          | AR_Q_MISC_FSP_DBA_GATED
-                          | AR_Q_MISC_CBR_INCR_DIS1
-                          | AR_Q_MISC_CBR_INCR_DIS0);
+                REG_SET_BIT(ah, AR_QMISC(q),
+                            AR_Q_MISC_FSP_DBA_GATED
+                            | AR_Q_MISC_CBR_INCR_DIS1
+                            | AR_Q_MISC_CBR_INCR_DIS0);
                 value = (qi->tqi_readyTime -
                          (ah->config.sw_beacon_response_time -
                           ah->config.dma_beacon_response_time) -
                          ah->config.additional_swba_backoff) * 1024;
                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
                           value | AR_Q_RDYTIMECFG_EN);
-                REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
-                          | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
+                REG_SET_BIT(ah, AR_DMISC(q),
+                            (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
 
                 REGWRITE_BUFFER_FLUSH(ah);
-                DISABLE_REGWRITE_BUFFER(ah);
 
                 break;
         case ATH9K_TX_QUEUE_PSPOLL:
-                REG_WRITE(ah, AR_QMISC(q),
-                          REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
+                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
                 break;
         case ATH9K_TX_QUEUE_UAPSD:
-                REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
-                          AR_D_MISC_POST_FR_BKOFF_DIS);
+                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
                 break;
         default:
                 break;
         }
 
         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
-                REG_WRITE(ah, AR_DMISC(q),
-                          REG_READ(ah, AR_DMISC(q)) |
-                          SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
-                             AR_D_MISC_ARB_LOCKOUT_CNTRL) |
-                          AR_D_MISC_POST_FR_BKOFF_DIS);
+                REG_SET_BIT(ah, AR_DMISC(q),
+                            SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
+                               AR_D_MISC_ARB_LOCKOUT_CNTRL) |
+                            AR_D_MISC_POST_FR_BKOFF_DIS);
         }
 
         if (AR_SREV_9300_20_OR_LATER(ah))
@@ -703,6 +629,12 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
                 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
 
         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
+                /*
+                 * Treat these errors as mutually exclusive to avoid spurious
+                 * extra error reports from the hardware. If a CRC error is
+                 * reported, then decryption and MIC errors are irrelevant,
+                 * the frame is going to be dropped either way
+                 */
                 if (ads.ds_rxstatus8 & AR_CRCErr)
                         rs->rs_status |= ATH9K_RXERR_CRC;
                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
@@ -713,6 +645,9 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
                         rs->rs_status |= ATH9K_RXERR_DECRYPT;
                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
                         rs->rs_status |= ATH9K_RXERR_MIC;
+
+                if (ads.ds_rxstatus8 & AR_KeyMiss)
+                        rs->rs_status |= ATH9K_RXERR_DECRYPT;
         }
 
         return 0;
@@ -741,9 +676,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
                                      AR_DIAG_RX_ABORT));
 
                         reg = REG_READ(ah, AR_OBS_BUS_1);
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "RX failed to go idle in 10 ms RXSM=0x%x\n",
-                                  reg);
+                        ath_err(ath9k_hw_common(ah),
+                                "RX failed to go idle in 10 ms RXSM=0x%x\n",
+                                reg);
 
                         return false;
                 }
@@ -772,14 +707,6 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
 }
 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
 
-void ath9k_hw_stoppcurecv(struct ath_hw *ah)
-{
-        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
-
-        ath9k_hw_disable_mib_counters(ah);
-}
-EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
-
 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
 {
         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
@@ -788,35 +715,51 @@ void ath9k_hw_abortpcurecv(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
 
-bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
+bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
 {
 #define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
-#define AH_RX_TIME_QUANTUM     100     /* usec */
         struct ath_common *common = ath9k_hw_common(ah);
+        u32 mac_status, last_mac_status = 0;
         int i;
 
+        /* Enable access to the DMA observation bus */
+        REG_WRITE(ah, AR_MACMISC,
+                  ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
+                   (AR_MACMISC_MISC_OBS_BUS_1 <<
+                    AR_MACMISC_MISC_OBS_BUS_MSB_S)));
+
         REG_WRITE(ah, AR_CR, AR_CR_RXD);
 
         /* Wait for rx enable bit to go low */
         for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
                 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
                         break;
+
+                if (!AR_SREV_9300_20_OR_LATER(ah)) {
+                        mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
+                        if (mac_status == 0x1c0 && mac_status == last_mac_status) {
+                                *reset = true;
+                                break;
+                        }
+
+                        last_mac_status = mac_status;
+                }
+
                 udelay(AH_TIME_QUANTUM);
         }
 
         if (i == 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "DMA failed to stop in %d ms "
-                          "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
-                          AH_RX_STOP_DMA_TIMEOUT / 1000,
-                          REG_READ(ah, AR_CR),
-                          REG_READ(ah, AR_DIAG_SW));
+                ath_err(common,
+                        "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
+                        AH_RX_STOP_DMA_TIMEOUT / 1000,
+                        REG_READ(ah, AR_CR),
+                        REG_READ(ah, AR_DIAG_SW),
+                        REG_READ(ah, AR_DMADBG_7));
                 return false;
         } else {
                 return true;
         }
 
-#undef AH_RX_TIME_QUANTUM
 #undef AH_RX_STOP_DMA_TIMEOUT
 }
 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
@@ -854,28 +797,61 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_intrpend);
 
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                              enum ath9k_int ints)
+void ath9k_hw_disable_interrupts(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
+        REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+        (void) REG_READ(ah, AR_IER);
+        if (!AR_SREV_9100(ah)) {
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+                (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+                (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
+        }
+}
+EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
+
+void ath9k_hw_enable_interrupts(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u32 sync_default = AR_INTR_SYNC_DEFAULT;
+
+        if (!(ah->imask & ATH9K_INT_GLOBAL))
+                return;
+
+        if (AR_SREV_9340(ah))
+                sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
+
+        ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
+        REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+        if (!AR_SREV_9100(ah)) {
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
+                          AR_INTR_MAC_IRQ);
+                REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
+                REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
+        }
+        ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+                REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+}
+EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
+
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
 {
         enum ath9k_int omask = ah->imask;
         u32 mask, mask2;
         struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
-
-        if (omask & ATH9K_INT_GLOBAL) {
-                ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
-                REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
-                (void) REG_READ(ah, AR_IER);
-                if (!AR_SREV_9100(ah)) {
-                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
-                        (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+        if (!(ints & ATH9K_INT_GLOBAL))
+                ath9k_hw_disable_interrupts(ah);
 
-                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-                        (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
-                }
-        }
+        ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
 
         /* TODO: global int Ref count */
         mask = ints & ATH9K_INT_COMMON;
@@ -914,6 +890,9 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         mask |= AR_IMR_GENTMR;
         }
 
+        if (ints & ATH9K_INT_GENTIMER)
+                mask |= AR_IMR_GENTMR;
+
         if (ints & (ATH9K_INT_BMISC)) {
                 mask |= AR_IMR_BCNMISC;
                 if (ints & ATH9K_INT_TIM)
@@ -936,7 +915,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         mask2 |= AR_IMR_S2_CST;
         }
 
-        ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+        ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
         REG_WRITE(ah, AR_IMR, mask);
         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
@@ -951,24 +930,9 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
         }
 
-        if (ints & ATH9K_INT_GLOBAL) {
-                ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
-                REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
-                if (!AR_SREV_9100(ah)) {
-                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
-                                  AR_INTR_MAC_IRQ);
-                        REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
-
-
-                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
-                                  AR_INTR_SYNC_DEFAULT);
-                        REG_WRITE(ah, AR_INTR_SYNC_MASK,
-                                  AR_INTR_SYNC_DEFAULT);
-                }
-                ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
-                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
-        }
+        if (ints & ATH9K_INT_GLOBAL)
+                ath9k_hw_enable_interrupts(ah);
 
-        return omask;
+        return;
 }
 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 2633896d3998..8e848c4d16ba 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -104,13 +104,11 @@ struct ath_tx_status {
         u32 ts_tstamp;
         u16 ts_seqnum;
         u8 ts_status;
-        u8 ts_ratecode;
         u8 ts_rateindex;
         int8_t ts_rssi;
         u8 ts_shortretry;
         u8 ts_longretry;
         u8 ts_virtcol;
-        u8 ts_antenna;
         u8 ts_flags;
         int8_t ts_rssi_ctl0;
         int8_t ts_rssi_ctl1;
@@ -121,7 +119,6 @@ struct ath_tx_status {
         u8 qid;
         u16 desc_id;
         u8 tid;
-        u8 pad[2];
         u32 ba_low;
         u32 ba_high;
         u32 evm0;
@@ -240,9 +237,8 @@ struct ath_desc {
         u32 ds_ctl1;
         u32 ds_hw[20];
         void *ds_vdata;
-} __packed;
+} __packed __aligned(4);
 
-#define ATH9K_TXDESC_CLRDMASK           0x0001
 #define ATH9K_TXDESC_NOACK              0x0002
 #define ATH9K_TXDESC_RTSENA             0x0004
 #define ATH9K_TXDESC_CTSENA             0x0008
@@ -310,7 +306,7 @@ struct ar5416_desc {
                         u32 status8;
                 } rx;
         } u;
-} __packed;
+} __packed __aligned(4);
 
 #define AR5416DESC(_ds)         ((struct ar5416_desc *)(_ds))
 #define AR5416DESC_CONST(_ds)   ((const struct ar5416_desc *)(_ds))
@@ -642,6 +638,8 @@ enum ath9k_rx_filter {
         ATH9K_RX_FILTER_PHYERR = 0x00000100,
         ATH9K_RX_FILTER_MYBEACON = 0x00000200,
         ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
+        ATH9K_RX_FILTER_COMP_BA = 0x00000800,
+        ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
         ATH9K_RX_FILTER_PSPOLL = 0x00004000,
         ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
         ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
@@ -660,17 +658,6 @@ struct ath9k_11n_rate_series {
         u32 RateFlags;
 };
 
-struct ath9k_keyval {
-        u8 kv_type;
-        u8 kv_pad;
-        u16 kv_len;
-        u8 kv_val[16]; /* TK */
-        u8 kv_mic[8]; /* Michael MIC key */
-        u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
-                         * supports both MIC keys in the same key cache entry;
-                         * in that case, kv_mic is the RX key) */
-};
-
 enum ath9k_key_type {
         ATH9K_KEY_TYPE_CLEAR,
         ATH9K_KEY_TYPE_WEP,
@@ -678,18 +665,9 @@ enum ath9k_key_type {
         ATH9K_KEY_TYPE_TKIP,
 };
 
-enum ath9k_cipher {
-        ATH9K_CIPHER_WEP = 0,
-        ATH9K_CIPHER_AES_OCB = 1,
-        ATH9K_CIPHER_AES_CCM = 2,
-        ATH9K_CIPHER_CKIP = 3,
-        ATH9K_CIPHER_TKIP = 4,
-        ATH9K_CIPHER_CLR = 5,
-        ATH9K_CIPHER_MIC = 127
-};
-
 struct ath_hw;
 struct ath9k_channel;
+enum ath9k_int;
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
@@ -697,7 +675,8 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
-bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
+bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
+void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
                             const struct ath9k_tx_queue_info *qinfo);
@@ -714,15 +693,15 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
-void ath9k_hw_stoppcurecv(struct ath_hw *ah);
 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
-bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
+bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);
 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
 
 /* Interrupt Handling */
 bool ath9k_hw_intrpend(struct ath_hw *ah);
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                       enum ath9k_int ints);
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
+void ath9k_hw_enable_interrupts(struct ath_hw *ah);
+void ath9k_hw_disable_interrupts(struct ath_hw *ah);
 
 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
 
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 3caa32316e7b..2ca351fe6d3c 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,50 +15,10 @@
  */
 
 #include <linux/nl80211.h>
+#include <linux/delay.h>
 #include "ath9k.h"
 #include "btcoex.h"
 
-static void ath_cache_conf_rate(struct ath_softc *sc,
-                                struct ieee80211_conf *conf)
-{
-        switch (conf->channel->band) {
-        case IEEE80211_BAND_2GHZ:
-                if (conf_is_ht20(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
-                else if (conf_is_ht40_minus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
-                else if (conf_is_ht40_plus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
-                else
-                        sc->cur_rate_mode = ATH9K_MODE_11G;
-                break;
-        case IEEE80211_BAND_5GHZ:
-                if (conf_is_ht20(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
-                else if (conf_is_ht40_minus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
-                else if (conf_is_ht40_plus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
-                else
-                        sc->cur_rate_mode = ATH9K_MODE_11A;
-                break;
-        default:
-                BUG_ON(1);
-                break;
-        }
-}
-
-static void ath_update_txpow(struct ath_softc *sc)
-{
-        struct ath_hw *ah = sc->sc_ah;
-
-        if (sc->curtxpow != sc->config.txpowlimit) {
-                ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
-                /* read back in case value is clamped */
-                sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
-        }
-}
-
 static u8 parse_mpdudensity(u8 mpdudensity)
 {
         /*
@@ -94,17 +54,19 @@ static u8 parse_mpdudensity(u8 mpdudensity)
         }
 }
 
-static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
-                                                struct ieee80211_hw *hw)
+static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
 {
-        struct ieee80211_channel *curchan = hw->conf.channel;
-        struct ath9k_channel *channel;
-        u8 chan_idx;
+        bool pending = false;
+
+        spin_lock_bh(&txq->axq_lock);
+
+        if (txq->axq_depth || !list_empty(&txq->axq_acq))
+                pending = true;
+        else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
+                pending = !list_empty(&txq->txq_fifo_pending);
 
-        chan_idx = curchan->hw_value;
-        channel = &sc->sc_ah->channels[chan_idx];
-        ath9k_update_ichannel(sc, hw, channel);
-        return channel;
+        spin_unlock_bh(&txq->axq_lock);
+        return pending;
 }
 
 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
@@ -121,26 +83,46 @@ bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 
 void ath9k_ps_wakeup(struct ath_softc *sc)
 {
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         unsigned long flags;
+        enum ath9k_power_mode power_mode;
 
         spin_lock_irqsave(&sc->sc_pm_lock, flags);
         if (++sc->ps_usecount != 1)
                 goto unlock;
 
+        power_mode = sc->sc_ah->power_mode;
         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 
+        /*
+         * While the hardware is asleep, the cycle counters contain no
+         * useful data. Better clear them now so that they don't mess up
+         * survey data results.
+         */
+        if (power_mode != ATH9K_PM_AWAKE) {
+                spin_lock(&common->cc_lock);
+                ath_hw_cycle_counters_update(common);
+                memset(&common->cc_survey, 0, sizeof(common->cc_survey));
+                spin_unlock(&common->cc_lock);
+        }
+
  unlock:
         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 }
 
 void ath9k_ps_restore(struct ath_softc *sc)
 {
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         unsigned long flags;
 
         spin_lock_irqsave(&sc->sc_pm_lock, flags);
         if (--sc->ps_usecount != 0)
                 goto unlock;
 
+        spin_lock(&common->cc_lock);
+        ath_hw_cycle_counters_update(common);
+        spin_unlock(&common->cc_lock);
+
         if (sc->ps_idle)
                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
         else if (sc->ps_enabled &&
@@ -175,6 +157,63 @@ static void ath_start_ani(struct ath_common *common)
                         msecs_to_jiffies((u32)ah->config.ani_poll_interval));
 }
 
+static void ath_update_survey_nf(struct ath_softc *sc, int channel)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *chan = &ah->channels[channel];
+        struct survey_info *survey = &sc->survey[channel];
+
+        if (chan->noisefloor) {
+                survey->filled |= SURVEY_INFO_NOISE_DBM;
+                survey->noise = chan->noisefloor;
+        }
+}
+
+/*
+ * Updates the survey statistics and returns the busy time since last
+ * update in %, if the measurement duration was long enough for the
+ * result to be useful, -1 otherwise.
+ */
+static int ath_update_survey_stats(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int pos = ah->curchan - &ah->channels[0];
+        struct survey_info *survey = &sc->survey[pos];
+        struct ath_cycle_counters *cc = &common->cc_survey;
+        unsigned int div = common->clockrate * 1000;
+        int ret = 0;
+
+        if (!ah->curchan)
+                return -1;
+
+        if (ah->power_mode == ATH9K_PM_AWAKE)
+                ath_hw_cycle_counters_update(common);
+
+        if (cc->cycles > 0) {
+                survey->filled |= SURVEY_INFO_CHANNEL_TIME |
+                        SURVEY_INFO_CHANNEL_TIME_BUSY |
+                        SURVEY_INFO_CHANNEL_TIME_RX |
+                        SURVEY_INFO_CHANNEL_TIME_TX;
+                survey->channel_time += cc->cycles / div;
+                survey->channel_time_busy += cc->rx_busy / div;
+                survey->channel_time_rx += cc->rx_frame / div;
+                survey->channel_time_tx += cc->tx_frame / div;
+        }
+
+        if (cc->cycles < div)
+                return -1;
+
+        if (cc->cycles > 0)
+                ret = cc->rx_busy * 100 / cc->cycles;
+
+        memset(cc, 0, sizeof(*cc));
+
+        ath_update_survey_nf(sc, pos);
+
+        return ret;
+}
+
 /*
  * Set/change channels.  If the channel is really being changed, it's done
  * by reseting the chip.  To accomplish this we must first cleanup any pending
@@ -183,7 +222,6 @@ static void ath_start_ani(struct ath_common *common)
 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                     struct ath9k_channel *hchan)
 {
-        struct ath_wiphy *aphy = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_conf *conf = &common->hw->conf;
@@ -195,13 +233,18 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
         if (sc->sc_flags & SC_OP_INVALID)
                 return -EIO;
 
+        sc->hw_busy_count = 0;
+
         del_timer_sync(&common->ani.timer);
         cancel_work_sync(&sc->paprd_work);
         cancel_work_sync(&sc->hw_check_work);
         cancel_delayed_work_sync(&sc->tx_complete_work);
+        cancel_delayed_work_sync(&sc->hw_pll_work);
 
         ath9k_ps_wakeup(sc);
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         /*
          * This is only performed if the channel settings have
          * actually changed.
@@ -211,9 +254,14 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
          * hardware at the new frequency, and then re-enable
          * the relevant bits of the h/w.
          */
-        ath9k_hw_set_interrupts(ah, 0);
-        ath_drain_all_txq(sc, false);
-        stopped = ath_stoprecv(sc);
+        ath9k_hw_disable_interrupts(ah);
+        stopped = ath_drain_all_txq(sc, false);
+
+        if (!ath_stoprecv(sc))
+                stopped = false;
+
+        if (!ath9k_hw_check_alive(ah))
+                stopped = false;
 
         /* XXX: do not flush receive queue here. We don't want
          * to flush data frames already in queue because of
@@ -223,44 +271,45 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                 fastcc = false;
 
         if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
-                caldata = &aphy->caldata;
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
-                  sc->sc_ah->curchan->channel,
-                  channel->center_freq, conf_is_ht40(conf));
+                caldata = &sc->caldata;
 
-        spin_lock_bh(&sc->sc_resetlock);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
+                sc->sc_ah->curchan->channel,
+                channel->center_freq, conf_is_ht40(conf),
+                fastcc);
 
         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
-                spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
                 goto ps_restore;
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to restart recv logic\n");
+                ath_err(common, "Unable to restart recv logic\n");
                 r = -EIO;
                 goto ps_restore;
         }
 
-        ath_cache_conf_rate(sc, &hw->conf);
-        ath_update_txpow(sc);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                               sc->config.txpowlimit, &sc->curtxpow);
         ath9k_hw_set_interrupts(ah, ah->imask);
 
-        if (!(sc->sc_flags & (SC_OP_OFFCHANNEL | SC_OP_SCANNING))) {
-                ath_start_ani(common);
+        if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
+                if (sc->sc_flags & SC_OP_BEACONS)
+                        ath_set_beacon(sc);
                 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
-                ath_beacon_config(sc, NULL);
+                ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
+                ath_start_ani(common);
         }
 
  ps_restore:
+        ieee80211_wake_queues(hw);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
         return r;
 }
@@ -269,6 +318,7 @@ static void ath_paprd_activate(struct ath_softc *sc)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
+        struct ath_common *common = ath9k_hw_common(ah);
         int chain;
 
         if (!caldata || !caldata->paprd_done)
@@ -277,7 +327,7 @@ static void ath_paprd_activate(struct ath_softc *sc)
         ath9k_ps_wakeup(sc);
         ar9003_paprd_enable(ah, false);
         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
-                if (!(ah->caps.tx_chainmask & BIT(chain)))
+                if (!(common->tx_chainmask & BIT(chain)))
                         continue;
 
                 ar9003_paprd_populate_single_table(ah, caldata, chain);
@@ -287,6 +337,46 @@ static void ath_paprd_activate(struct ath_softc *sc)
         ath9k_ps_restore(sc);
 }
 
+static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
+{
+        struct ieee80211_hw *hw = sc->hw;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath_tx_control txctl;
+        int time_left;
+
+        memset(&txctl, 0, sizeof(txctl));
+        txctl.txq = sc->tx.txq_map[WME_AC_BE];
+
+        memset(tx_info, 0, sizeof(*tx_info));
+        tx_info->band = hw->conf.channel->band;
+        tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
+        tx_info->control.rates[0].idx = 0;
+        tx_info->control.rates[0].count = 1;
+        tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
+        tx_info->control.rates[1].idx = -1;
+
+        init_completion(&sc->paprd_complete);
+        txctl.paprd = BIT(chain);
+
+        if (ath_tx_start(hw, skb, &txctl) != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
+                dev_kfree_skb_any(skb);
+                return false;
+        }
+
+        time_left = wait_for_completion_timeout(&sc->paprd_complete,
+                        msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
+
+        if (!time_left)
+                ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
+                        "Timeout waiting for paprd training on TX chain %d\n",
+                        chain);
+
+        return !!time_left;
+}
+
 void ath_paprd_calibrate(struct work_struct *work)
 {
         struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
@@ -294,27 +384,23 @@ void ath_paprd_calibrate(struct work_struct *work)
         struct ath_hw *ah = sc->sc_ah;
         struct ieee80211_hdr *hdr;
         struct sk_buff *skb = NULL;
-        struct ieee80211_tx_info *tx_info;
-        int band = hw->conf.channel->band;
-        struct ieee80211_supported_band *sband = &sc->sbands[band];
-        struct ath_tx_control txctl;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
-        int qnum, ftype;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ftype;
         int chain_ok = 0;
         int chain;
         int len = 1800;
-        int time_left;
-        int i;
 
         if (!caldata)
                 return;
 
+        if (ar9003_paprd_init_table(ah) < 0)
+                return;
+
         skb = alloc_skb(len, GFP_KERNEL);
         if (!skb)
                 return;
 
-        tx_info = IEEE80211_SKB_CB(skb);
-
         skb_put(skb, len);
         memset(skb->data, 0, len);
         hdr = (struct ieee80211_hdr *)skb->data;
@@ -325,40 +411,25 @@ void ath_paprd_calibrate(struct work_struct *work)
         memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
         memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
 
-        memset(&txctl, 0, sizeof(txctl));
-        qnum = sc->tx.hwq_map[WME_AC_BE];
-        txctl.txq = &sc->tx.txq[qnum];
-
         ath9k_ps_wakeup(sc);
-        ar9003_paprd_init_table(ah);
         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
-                if (!(ah->caps.tx_chainmask & BIT(chain)))
+                if (!(common->tx_chainmask & BIT(chain)))
                         continue;
 
                 chain_ok = 0;
-                memset(tx_info, 0, sizeof(*tx_info));
-                tx_info->band = band;
 
-                for (i = 0; i < 4; i++) {
-                        tx_info->control.rates[i].idx = sband->n_bitrates - 1;
-                        tx_info->control.rates[i].count = 6;
-                }
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Sending PAPRD frame for thermal measurement "
+                        "on chain %d\n", chain);
+                if (!ath_paprd_send_frame(sc, skb, chain))
+                        goto fail_paprd;
 
-                init_completion(&sc->paprd_complete);
                 ar9003_paprd_setup_gain_table(ah, chain);
-                txctl.paprd = BIT(chain);
-                if (ath_tx_start(hw, skb, &txctl) != 0)
-                        break;
 
-                time_left = wait_for_completion_timeout(&sc->paprd_complete,
-                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
-                if (!time_left) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                                  "Timeout waiting for paprd training on "
-                                  "TX chain %d\n",
-                                  chain);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Sending PAPRD training frame on chain %d\n", chain);
+                if (!ath_paprd_send_frame(sc, skb, chain))
                         goto fail_paprd;
-                }
 
                 if (!ar9003_paprd_is_done(ah))
                         break;
@@ -395,7 +466,13 @@ void ath_ani_calibrate(unsigned long data)
         bool shortcal = false;
         bool aniflag = false;
         unsigned int timestamp = jiffies_to_msecs(jiffies);
-        u32 cal_interval, short_cal_interval;
+        u32 cal_interval, short_cal_interval, long_cal_interval;
+        unsigned long flags;
+
+        if (ah->caldata && ah->caldata->nfcal_interference)
+                long_cal_interval = ATH_LONG_CALINTERVAL_INT;
+        else
+                long_cal_interval = ATH_LONG_CALINTERVAL;
 
         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
@@ -407,9 +484,9 @@ void ath_ani_calibrate(unsigned long data)
         ath9k_ps_wakeup(sc);
 
         /* Long calibration runs independently of short calibration. */
-        if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
+        if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
                 longcal = true;
-                ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
+                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -417,8 +494,8 @@ void ath_ani_calibrate(unsigned long data)
         if (!common->ani.caldone) {
                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
                         shortcal = true;
-                        ath_print(common, ATH_DBG_ANI,
-                                  "shortcal @%lu\n", jiffies);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -441,8 +518,12 @@ void ath_ani_calibrate(unsigned long data)
         /* Skip all processing if there's nothing to do. */
         if (longcal || shortcal || aniflag) {
                 /* Call ANI routine if necessary */
-                if (aniflag)
+                if (aniflag) {
+                        spin_lock_irqsave(&common->cc_lock, flags);
                         ath9k_hw_ani_monitor(ah, ah->curchan);
+                        ath_update_survey_stats(sc);
+                        spin_unlock_irqrestore(&common->cc_lock, flags);
+                }
 
                 /* Perform calibration if necessary */
                 if (longcal || shortcal) {
@@ -451,16 +532,6 @@ void ath_ani_calibrate(unsigned long data)
                                                    ah->curchan,
                                                    common->rx_chainmask,
                                                    longcal);
-
-                        if (longcal)
-                                common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
-                                                                     ah->curchan);
-
-                        ath_print(common, ATH_DBG_ANI,
-                                  " calibrate chan %u/%x nf: %d\n",
-                                  ah->curchan->channel,
-                                  ah->curchan->channelFlags,
-                                  common->ani.noise_floor);
                 }
         }
 
@@ -483,49 +554,31 @@ set_timer:
         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
                 if (!ah->caldata->paprd_done)
                         ieee80211_queue_work(sc->hw, &sc->paprd_work);
-                else
+                else if (!ah->paprd_table_write_done)
                         ath_paprd_activate(sc);
         }
 }
 
-/*
- * Update tx/rx chainmask. For legacy association,
- * hard code chainmask to 1x1, for 11n association, use
- * the chainmask configuration, for bt coexistence, use
- * the chainmask configuration even in legacy mode.
- */
-void ath_update_chainmask(struct ath_softc *sc, int is_ht)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
-            (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
-                common->tx_chainmask = ah->caps.tx_chainmask;
-                common->rx_chainmask = ah->caps.rx_chainmask;
-        } else {
-                common->tx_chainmask = 1;
-                common->rx_chainmask = 1;
-        }
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "tx chmask: %d, rx chmask: %d\n",
-                  common->tx_chainmask,
-                  common->rx_chainmask);
-}
-
 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 {
         struct ath_node *an;
-
+        struct ath_hw *ah = sc->sc_ah;
         an = (struct ath_node *)sta->drv_priv;
 
+#ifdef CONFIG_ATH9K_DEBUGFS
+        spin_lock(&sc->nodes_lock);
+        list_add(&an->list, &sc->nodes);
+        spin_unlock(&sc->nodes_lock);
+        an->sta = sta;
+#endif
+        if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
+                sc->sc_flags |= SC_OP_ENABLE_APM;
+
         if (sc->sc_flags & SC_OP_TXAGGR) {
                 ath_tx_node_init(sc, an);
                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
                                      sta->ht_cap.ampdu_factor);
                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
-                an->last_rssi = ATH_RSSI_DUMMY_MARKER;
         }
 }
 
@@ -533,6 +586,13 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 
+#ifdef CONFIG_ATH9K_DEBUGFS
+        spin_lock(&sc->nodes_lock);
+        list_del(&an->list);
+        spin_unlock(&sc->nodes_lock);
+        an->sta = NULL;
+#endif
+
         if (sc->sc_flags & SC_OP_TXAGGR)
                 ath_tx_node_cleanup(sc, an);
 }
@@ -540,22 +600,67 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 void ath_hw_check(struct work_struct *work)
 {
         struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
-        int i;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        unsigned long flags;
+        int busy;
 
         ath9k_ps_wakeup(sc);
+        if (ath9k_hw_check_alive(sc->sc_ah))
+                goto out;
 
-        for (i = 0; i < 3; i++) {
-                if (ath9k_hw_check_alive(sc->sc_ah))
-                        goto out;
+        spin_lock_irqsave(&common->cc_lock, flags);
+        busy = ath_update_survey_stats(sc);
+        spin_unlock_irqrestore(&common->cc_lock, flags);
 
-                msleep(1);
-        }
-        ath_reset(sc, false);
+        ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
+                "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
+        if (busy >= 99) {
+                if (++sc->hw_busy_count >= 3)
+                        ath_reset(sc, true);
+        } else if (busy >= 0)
+                sc->hw_busy_count = 0;
 
 out:
         ath9k_ps_restore(sc);
 }
 
+static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
+{
+        static int count;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+
+        if (pll_sqsum >= 0x40000) {
+                count++;
+                if (count == 3) {
+                        /* Rx is hung for more than 500ms. Reset it */
+                        ath_dbg(common, ATH_DBG_RESET,
+                                "Possible RX hang, resetting");
+                        ath_reset(sc, true);
+                        count = 0;
+                }
+        } else
+                count = 0;
+}
+
+void ath_hw_pll_work(struct work_struct *work)
+{
+        struct ath_softc *sc = container_of(work, struct ath_softc,
+                                            hw_pll_work.work);
+        u32 pll_sqsum;
+
+        if (AR_SREV_9485(sc->sc_ah)) {
+
+                ath9k_ps_wakeup(sc);
+                pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
+                ath9k_ps_restore(sc);
+
+                ath_hw_pll_rx_hang_check(sc, pll_sqsum);
+
+                ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
+        }
+}
+
+
 void ath9k_tasklet(unsigned long data)
 {
         struct ath_softc *sc = (struct ath_softc *)data;
@@ -565,17 +670,37 @@ void ath9k_tasklet(unsigned long data)
         u32 status = sc->intrstatus;
         u32 rxmask;
 
-        ath9k_ps_wakeup(sc);
-
-        if (status & ATH9K_INT_FATAL) {
-                ath_reset(sc, false);
-                ath9k_ps_restore(sc);
+        if ((status & ATH9K_INT_FATAL) ||
+            (status & ATH9K_INT_BB_WATCHDOG)) {
+                ath_reset(sc, true);
                 return;
         }
 
-        if (!ath9k_hw_check_alive(ah))
+        ath9k_ps_wakeup(sc);
+        spin_lock(&sc->sc_pcu_lock);
+
+        /*
+         * Only run the baseband hang check if beacons stop working in AP or
+         * IBSS mode, because it has a high false positive rate. For station
+         * mode it should not be necessary, since the upper layers will detect
+         * this through a beacon miss automatically and the following channel
+         * change will trigger a hardware reset anyway
+         */
+        if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
+            !ath9k_hw_check_alive(ah))
                 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 
+        if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
+                /*
+                 * TSF sync does not look correct; remain awake to sync with
+                 * the next Beacon.
+                 */
+                ath_dbg(common, ATH_DBG_PS,
+                        "TSFOOR - Sync with next Beacon\n");
+                sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
+                                PS_TSFOOR_SYNC;
+        }
+
         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
                           ATH9K_INT_RXORN);
@@ -583,15 +708,12 @@ void ath9k_tasklet(unsigned long data)
                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 
         if (status & rxmask) {
-                spin_lock_bh(&sc->rx.rxflushlock);
-
                 /* Check for high priority Rx first */
                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
                     (status & ATH9K_INT_RXHP))
                         ath_rx_tasklet(sc, 0, true);
 
                 ath_rx_tasklet(sc, 0, false);
-                spin_unlock_bh(&sc->rx.rxflushlock);
         }
 
         if (status & ATH9K_INT_TX) {
@@ -601,22 +723,14 @@ void ath9k_tasklet(unsigned long data)
                         ath_tx_tasklet(sc);
         }
 
-        if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
-                /*
-                 * TSF sync does not look correct; remain awake to sync with
-                 * the next Beacon.
-                 */
-                ath_print(common, ATH_DBG_PS,
-                          "TSFOOR - Sync with next Beacon\n");
-                sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
-        }
-
         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
                 if (status & ATH9K_INT_GENTIMER)
                         ath_gen_timer_isr(sc->sc_ah);
 
         /* re-enable hardware interrupt */
-        ath9k_hw_set_interrupts(ah, ah->imask);
+        ath9k_hw_enable_interrupts(ah);
+
+        spin_unlock(&sc->sc_pcu_lock);
         ath9k_ps_restore(sc);
 }
 
@@ -624,6 +738,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 {
 #define SCHED_INTR (                            \
                 ATH9K_INT_FATAL |               \
+                ATH9K_INT_BB_WATCHDOG |         \
                 ATH9K_INT_RXORN |               \
                 ATH9K_INT_RXEOL |               \
                 ATH9K_INT_RX |                  \
@@ -637,6 +752,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 
         struct ath_softc *sc = dev;
         struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
         enum ath9k_int status;
         bool sched = false;
 
@@ -686,7 +802,12 @@ irqreturn_t ath_isr(int irq, void *dev)
 
         if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
             (status & ATH9K_INT_BB_WATCHDOG)) {
+
+                spin_lock(&common->cc_lock);
+                ath_hw_cycle_counters_update(common);
                 ar9003_hw_bb_watchdog_dbg_info(ah);
+                spin_unlock(&common->cc_lock);
+
                 goto chip_reset;
         }
 
@@ -709,18 +830,22 @@ irqreturn_t ath_isr(int irq, void *dev)
                  * interrupt; otherwise it will continue to
                  * fire.
                  */
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 /*
                  * Let the hal handle the event. We assume
                  * it will clear whatever condition caused
                  * the interrupt.
                  */
-                ath9k_hw_procmibevent(ah);
-                ath9k_hw_set_interrupts(ah, ah->imask);
+                spin_lock(&common->cc_lock);
+                ath9k_hw_proc_mib_event(ah);
+                spin_unlock(&common->cc_lock);
+                ath9k_hw_enable_interrupts(ah);
         }
 
         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                 if (status & ATH9K_INT_TIM_TIMER) {
+                        if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
+                                goto chip_reset;
                         /* Clear RxAbort bit so that we can
                          * receive frames */
                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
@@ -733,8 +858,8 @@ chip_reset:
         ath_debug_stat_interrupt(sc, status);
 
         if (sched) {
-                /* turn off every interrupt except SWBA */
-                ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
+                /* turn off every interrupt */
+                ath9k_hw_disable_interrupts(ah);
                 tasklet_schedule(&sc->intr_tq);
         }
 
@@ -743,88 +868,6 @@ chip_reset:
 #undef SCHED_INTR
 }
 
-static u32 ath_get_extchanmode(struct ath_softc *sc,
-                               struct ieee80211_channel *chan,
-                               enum nl80211_channel_type channel_type)
-{
-        u32 chanmode = 0;
-
-        switch (chan->band) {
-        case IEEE80211_BAND_2GHZ:
-                switch(channel_type) {
-                case NL80211_CHAN_NO_HT:
-                case NL80211_CHAN_HT20:
-                        chanmode = CHANNEL_G_HT20;
-                        break;
-                case NL80211_CHAN_HT40PLUS:
-                        chanmode = CHANNEL_G_HT40PLUS;
-                        break;
-                case NL80211_CHAN_HT40MINUS:
-                        chanmode = CHANNEL_G_HT40MINUS;
-                        break;
-                }
-                break;
-        case IEEE80211_BAND_5GHZ:
-                switch(channel_type) {
-                case NL80211_CHAN_NO_HT:
-                case NL80211_CHAN_HT20:
-                        chanmode = CHANNEL_A_HT20;
-                        break;
-                case NL80211_CHAN_HT40PLUS:
-                        chanmode = CHANNEL_A_HT40PLUS;
-                        break;
-                case NL80211_CHAN_HT40MINUS:
-                        chanmode = CHANNEL_A_HT40MINUS;
-                        break;
-                }
-                break;
-        default:
-                break;
-        }
-
-        return chanmode;
-}
-
-static void ath9k_bss_assoc_info(struct ath_softc *sc,
-                                 struct ieee80211_vif *vif,
-                                 struct ieee80211_bss_conf *bss_conf)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if (bss_conf->assoc) {
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Bss Info ASSOC %d, bssid: %pM\n",
-                           bss_conf->aid, common->curbssid);
-
-                /* New association, store aid */
-                common->curaid = bss_conf->aid;
-                ath9k_hw_write_associd(ah);
-
-                /*
-                 * Request a re-configuration of Beacon related timers
-                 * on the receipt of the first Beacon frame (i.e.,
-                 * after time sync with the AP).
-                 */
-                sc->ps_flags |= PS_BEACON_SYNC;
-
-                /* Configure the beacon */
-                ath_beacon_config(sc, vif);
-
-                /* Reset rssi stats */
-                sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
-
-                sc->sc_flags |= SC_OP_ANI_RUN;
-                ath_start_ani(common);
-        } else {
-                ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
-                common->curaid = 0;
-                /* Stop ANI */
-                sc->sc_flags &= ~SC_OP_ANI_RUN;
-                del_timer_sync(&common->ani.timer);
-        }
-}
-
 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
 {
         struct ath_hw *ah = sc->sc_ah;
@@ -833,30 +876,28 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
         int r;
 
         ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ath9k_hw_configpcipowersave(ah, 0, 0);
 
         if (!ah->curchan)
-                ah->curchan = ath_get_curchannel(sc, sc->hw);
+                ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
+                ath_err(common,
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
-        ath_update_txpow(sc);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                               sc->config.txpowlimit, &sc->curtxpow);
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to restart recv logic\n");
-                return;
+                ath_err(common, "Unable to restart recv logic\n");
+                goto out;
         }
-
         if (sc->sc_flags & SC_OP_BEACONS)
-                ath_beacon_config(sc, NULL);    /* restart beacons */
+                ath_set_beacon(sc);     /* restart beacons */
 
         /* Re-Enable  interrupts */
         ath9k_hw_set_interrupts(ah, ah->imask);
@@ -867,6 +908,11 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
 
         ieee80211_wake_queues(hw);
+        ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
+
+out:
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
 }
 
@@ -877,6 +923,10 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
         int r;
 
         ath9k_ps_wakeup(sc);
+        cancel_delayed_work_sync(&sc->hw_pll_work);
+
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ieee80211_stop_queues(hw);
 
         /*
@@ -889,29 +939,29 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
         }
 
         /* Disable interrupts */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
 
         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
+
         ath_stoprecv(sc);               /* turn off frame recv */
         ath_flushrecv(sc);              /* flush recv queue */
 
         if (!ah->curchan)
-                ah->curchan = ath_get_curchannel(sc, hw);
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
         if (r) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         ath9k_hw_phy_disable(ah);
+
         ath9k_hw_configpcipowersave(ah, 1, 1);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
         ath9k_ps_restore(sc);
-        ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
 }
 
 int ath_reset(struct ath_softc *sc, bool retry_tx)
@@ -921,38 +971,40 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         struct ieee80211_hw *hw = sc->hw;
         int r;
 
+        sc->hw_busy_count = 0;
+
         /* Stop ANI */
         del_timer_sync(&common->ani.timer);
 
+        ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ieee80211_stop_queues(hw);
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath_drain_all_txq(sc, retry_tx);
+
         ath_stoprecv(sc);
         ath_flushrecv(sc);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
         if (r)
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d\n", r);
-        spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d\n", r);
 
         if (ath_startrecv(sc) != 0)
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to start recv logic\n");
+                ath_err(common, "Unable to start recv logic\n");
 
         /*
          * We may be doing a reset in response to a request
          * that changes the channel so update any state that
          * might change as a result.
          */
-        ath_cache_conf_rate(sc, &hw->conf);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                               sc->config.txpowlimit, &sc->curtxpow);
 
-        ath_update_txpow(sc);
-
-        if (sc->sc_flags & SC_OP_BEACONS)
-                ath_beacon_config(sc, NULL);    /* restart beacons */
+        if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
+                ath_set_beacon(sc);     /* restart beacons */
 
         ath9k_hw_set_interrupts(ah, ah->imask);
 
@@ -968,133 +1020,40 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         }
 
         ieee80211_wake_queues(hw);
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         /* Start ANI */
         ath_start_ani(common);
+        ath9k_ps_restore(sc);
 
         return r;
 }
 
-static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
-{
-        int qnum;
-
-        switch (queue) {
-        case 0:
-                qnum = sc->tx.hwq_map[WME_AC_VO];
-                break;
-        case 1:
-                qnum = sc->tx.hwq_map[WME_AC_VI];
-                break;
-        case 2:
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                break;
-        case 3:
-                qnum = sc->tx.hwq_map[WME_AC_BK];
-                break;
-        default:
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                break;
-        }
-
-        return qnum;
-}
-
-int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
-{
-        int qnum;
-
-        switch (queue) {
-        case WME_AC_VO:
-                qnum = 0;
-                break;
-        case WME_AC_VI:
-                qnum = 1;
-                break;
-        case WME_AC_BE:
-                qnum = 2;
-                break;
-        case WME_AC_BK:
-                qnum = 3;
-                break;
-        default:
-                qnum = -1;
-                break;
-        }
-
-        return qnum;
-}
-
-/* XXX: Remove me once we don't depend on ath9k_channel for all
- * this redundant data */
-void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
-                           struct ath9k_channel *ichan)
-{
-        struct ieee80211_channel *chan = hw->conf.channel;
-        struct ieee80211_conf *conf = &hw->conf;
-
-        ichan->channel = chan->center_freq;
-        ichan->chan = chan;
-
-        if (chan->band == IEEE80211_BAND_2GHZ) {
-                ichan->chanmode = CHANNEL_G;
-                ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
-        } else {
-                ichan->chanmode = CHANNEL_A;
-                ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
-        }
-
-        if (conf_is_ht(conf))
-                ichan->chanmode = ath_get_extchanmode(sc, chan,
-                                            conf->channel_type);
-}
-
 /**********************/
 /* mac80211 callbacks */
 /**********************/
 
 static int ath9k_start(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_channel *curchan = hw->conf.channel;
         struct ath9k_channel *init_channel;
         int r;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Starting driver with initial channel: %d MHz\n",
-                  curchan->center_freq);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Starting driver with initial channel: %d MHz\n",
+                curchan->center_freq);
 
-        mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
 
-        if (ath9k_wiphy_started(sc)) {
-                if (sc->chan_idx == curchan->hw_value) {
-                        /*
-                         * Already on the operational channel, the new wiphy
-                         * can be marked active.
-                         */
-                        aphy->state = ATH_WIPHY_ACTIVE;
-                        ieee80211_wake_queues(hw);
-                } else {
-                        /*
-                         * Another wiphy is on another channel, start the new
-                         * wiphy in paused state.
-                         */
-                        aphy->state = ATH_WIPHY_PAUSED;
-                        ieee80211_stop_queues(hw);
-                }
-                mutex_unlock(&sc->mutex);
-                return 0;
-        }
-        aphy->state = ATH_WIPHY_ACTIVE;
+        mutex_lock(&sc->mutex);
 
         /* setup initial channel */
-
         sc->chan_idx = curchan->hw_value;
 
-        init_channel = ath_get_curchannel(sc, hw);
+        init_channel = ath9k_cmn_get_curchannel(hw, ah);
 
         /* Reset SERDES registers */
         ath9k_hw_configpcipowersave(ah, 0, 0);
@@ -1106,23 +1065,22 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * be followed by initialization of the appropriate bits
          * and then setup of the interrupt mask.
          */
-        spin_lock_bh(&sc->sc_resetlock);
+        spin_lock_bh(&sc->sc_pcu_lock);
         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", r,
-                          curchan->center_freq);
-                spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        r, curchan->center_freq);
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 goto mutex_unlock;
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         /*
          * This is needed only to setup initial state
          * but it's best done after a reset.
          */
-        ath_update_txpow(sc);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                        sc->config.txpowlimit, &sc->curtxpow);
 
         /*
          * Setup the hardware after reset:
@@ -1132,11 +1090,12 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * here except setup the interrupt mask.
          */
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to start recv logic\n");
+                ath_err(common, "Unable to start recv logic\n");
                 r = -EIO;
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 goto mutex_unlock;
         }
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         /* Setup our intr mask. */
         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
@@ -1150,15 +1109,13 @@ static int ath9k_start(struct ieee80211_hw *hw)
         else
                 ah->imask |= ATH9K_INT_RX;
 
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
-                ah->imask |= ATH9K_INT_GTT;
+        ah->imask |= ATH9K_INT_GTT;
 
         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
                 ah->imask |= ATH9K_INT_CST;
 
-        ath_cache_conf_rate(sc, &hw->conf);
-
         sc->sc_flags &= ~SC_OP_INVALID;
+        sc->sc_ah->is_monitoring = false;
 
         /* Disable BMISS interrupt when we're not associated */
         ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
@@ -1180,30 +1137,23 @@ static int ath9k_start(struct ieee80211_hw *hw)
                         ath9k_btcoex_timer_resume(sc);
         }
 
+        if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
+                common->bus_ops->extn_synch_en(common);
+
 mutex_unlock:
         mutex_unlock(&sc->mutex);
 
+        ath9k_ps_restore(sc);
+
         return r;
 }
 
-static int ath9k_tx(struct ieee80211_hw *hw,
-                    struct sk_buff *skb)
+static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 {
-        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_tx_control txctl;
-        int padpos, padsize;
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
-        int qnum;
-
-        if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
-                ath_print(common, ATH_DBG_XMIT,
-                          "ath9k: %s: TX in unexpected wiphy state "
-                          "%d\n", wiphy_name(hw->wiphy), aphy->state);
-                goto exit;
-        }
 
         if (sc->ps_enabled) {
                 /*
@@ -1213,8 +1163,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
                 if (ieee80211_is_data(hdr->frame_control) &&
                     !ieee80211_is_nullfunc(hdr->frame_control) &&
                     !ieee80211_has_pm(hdr->frame_control)) {
-                        ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
-                                  "while in PS mode\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Add PM=1 for a TX frame while in PS mode\n");
                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
                 }
         }
@@ -1229,12 +1179,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                         ath9k_hw_setrxabort(sc->sc_ah, 0);
                 if (ieee80211_is_pspoll(hdr->frame_control)) {
-                        ath_print(common, ATH_DBG_PS,
-                                  "Sending PS-Poll to pick a buffered frame\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Sending PS-Poll to pick a buffered frame\n");
                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
                 } else {
-                        ath_print(common, ATH_DBG_PS,
-                                  "Wake up to complete TX\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Wake up to complete TX\n");
                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
                 }
                 /*
@@ -1246,85 +1196,39 @@ static int ath9k_tx(struct ieee80211_hw *hw,
         }
 
         memset(&txctl, 0, sizeof(struct ath_tx_control));
+        txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 
-        /*
-         * As a temporary workaround, assign seq# here; this will likely need
-         * to be cleaned up to work better with Beacon transmission and virtual
-         * BSSes.
-         */
-        if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
-                if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
-                        sc->tx.seq_no += 0x10;
-                hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
-                hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
-        }
-
-        /* Add the padding after the header if this is not already done */
-        padpos = ath9k_cmn_padpos(hdr->frame_control);
-        padsize = padpos & 3;
-        if (padsize && skb->len>padpos) {
-                if (skb_headroom(skb) < padsize)
-                        return -1;
-                skb_push(skb, padsize);
-                memmove(skb->data, skb->data + padsize, padpos);
-        }
-
-        qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
-        txctl.txq = &sc->tx.txq[qnum];
-
-        ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
+        ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
 
         if (ath_tx_start(hw, skb, &txctl) != 0) {
-                ath_print(common, ATH_DBG_XMIT, "TX failed\n");
+                ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
                 goto exit;
         }
 
-        return 0;
+        return;
 exit:
         dev_kfree_skb_any(skb);
-        return 0;
 }
 
 static void ath9k_stop(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
-        int i;
 
         mutex_lock(&sc->mutex);
 
-        aphy->state = ATH_WIPHY_INACTIVE;
-
-        if (led_blink)
-                cancel_delayed_work_sync(&sc->ath_led_blink_work);
-
         cancel_delayed_work_sync(&sc->tx_complete_work);
+        cancel_delayed_work_sync(&sc->hw_pll_work);
         cancel_work_sync(&sc->paprd_work);
         cancel_work_sync(&sc->hw_check_work);
 
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i])
-                        break;
-        }
-
-        if (i == sc->num_sec_wiphy) {
-                cancel_delayed_work_sync(&sc->wiphy_work);
-                cancel_work_sync(&sc->chan_work);
-        }
-
         if (sc->sc_flags & SC_OP_INVALID) {
-                ath_print(common, ATH_DBG_ANY, "Device not present\n");
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&sc->mutex);
                 return;
         }
 
-        if (ath9k_wiphy_started(sc)) {
-                mutex_unlock(&sc->mutex);
-                return; /* another wiphy still in use */
-        }
-
         /* Ensure HW is awake when we try to shut it down. */
         ath9k_ps_wakeup(sc);
 
@@ -1334,9 +1238,14 @@ static void ath9k_stop(struct ieee80211_hw *hw)
                         ath9k_btcoex_timer_pause(sc);
         }
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
+        /* prevent tasklets to enable interrupts once we disable them */
+        ah->imask &= ~ATH9K_INT_GLOBAL;
+
         /* make sure h/w will not generate any interrupt
          * before setting the invalid flag. */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
 
         if (!(sc->sc_flags & SC_OP_INVALID)) {
                 ath_drain_all_txq(sc, false);
@@ -1345,153 +1254,325 @@ static void ath9k_stop(struct ieee80211_hw *hw)
         } else
                 sc->rx.rxlink = NULL;
 
+        if (sc->rx.frag) {
+                dev_kfree_skb_any(sc->rx.frag);
+                sc->rx.frag = NULL;
+        }
+
         /* disable HAL and put h/w to sleep */
         ath9k_hw_disable(ah);
         ath9k_hw_configpcipowersave(ah, 1, 1);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
+        /* we can now sync irq and kill any running tasklets, since we already
+         * disabled interrupts and not holding a spin lock */
+        synchronize_irq(sc->irq);
+        tasklet_kill(&sc->intr_tq);
+        tasklet_kill(&sc->bcon_tasklet);
+
         ath9k_ps_restore(sc);
 
-        /* Finally, put the chip in FULL SLEEP mode */
-        ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
+        sc->ps_idle = true;
+        ath_radio_disable(sc, hw);
 
         sc->sc_flags |= SC_OP_INVALID;
 
         mutex_unlock(&sc->mutex);
 
-        ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
 }
 
-static int ath9k_add_interface(struct ieee80211_hw *hw,
-                               struct ieee80211_vif *vif)
+bool ath9k_uses_beacons(int type)
+{
+        switch (type) {
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_MESH_POINT:
+                return true;
+        default:
+                return false;
+        }
+}
+
+static void ath9k_reclaim_beacon(struct ath_softc *sc,
+                                 struct ieee80211_vif *vif)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
         struct ath_vif *avp = (void *)vif->drv_priv;
-        enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
-        int ret = 0;
 
-        mutex_lock(&sc->mutex);
+        ath9k_set_beaconing_status(sc, false);
+        ath_beacon_return(sc, avp);
+        ath9k_set_beaconing_status(sc, true);
+        sc->sc_flags &= ~SC_OP_BEACONS;
+}
 
-        if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
-            sc->nvifs > 0) {
-                ret = -ENOBUFS;
-                goto out;
-        }
+static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_vif_iter_data *iter_data = data;
+        int i;
+
+        if (iter_data->hw_macaddr)
+                for (i = 0; i < ETH_ALEN; i++)
+                        iter_data->mask[i] &=
+                                ~(iter_data->hw_macaddr[i] ^ mac[i]);
 
         switch (vif->type) {
+        case NL80211_IFTYPE_AP:
+                iter_data->naps++;
+                break;
         case NL80211_IFTYPE_STATION:
-                ic_opmode = NL80211_IFTYPE_STATION;
+                iter_data->nstations++;
                 break;
         case NL80211_IFTYPE_ADHOC:
-        case NL80211_IFTYPE_AP:
+                iter_data->nadhocs++;
+                break;
         case NL80211_IFTYPE_MESH_POINT:
-                if (sc->nbcnvifs >= ATH_BCBUF) {
-                        ret = -ENOBUFS;
-                        goto out;
-                }
-                ic_opmode = vif->type;
+                iter_data->nmeshes++;
+                break;
+        case NL80211_IFTYPE_WDS:
+                iter_data->nwds++;
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                        "Interface type %d not yet supported\n", vif->type);
-                ret = -EOPNOTSUPP;
-                goto out;
+                iter_data->nothers++;
+                break;
         }
+}
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Attach a VIF of type: %d\n", ic_opmode);
+/* Called with sc->mutex held. */
+void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               struct ath9k_vif_iter_data *iter_data)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        /*
+         * Use the hardware MAC address as reference, the hardware uses it
+         * together with the BSSID mask when matching addresses.
+         */
+        memset(iter_data, 0, sizeof(*iter_data));
+        iter_data->hw_macaddr = common->macaddr;
+        memset(&iter_data->mask, 0xff, ETH_ALEN);
 
-        /* Set the VIF opmode */
-        avp->av_opmode = ic_opmode;
-        avp->av_bslot = -1;
+        if (vif)
+                ath9k_vif_iter(iter_data, vif->addr, vif);
 
-        sc->nvifs++;
+        /* Get list of all active MAC addresses */
+        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
+                                                   iter_data);
+}
+
+/* Called with sc->mutex held. */
+static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
+                                          struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_vif_iter_data iter_data;
 
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                ath9k_set_bssid_mask(hw);
+        ath9k_calculate_iter_data(hw, vif, &iter_data);
 
-        if (sc->nvifs > 1)
-                goto out; /* skip global settings for secondary vif */
+        /* Set BSSID mask. */
+        memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
+        ath_hw_setbssidmask(common);
 
-        if (ic_opmode == NL80211_IFTYPE_AP) {
+        /* Set op-mode & TSF */
+        if (iter_data.naps > 0) {
                 ath9k_hw_set_tsfadjust(ah, 1);
                 sc->sc_flags |= SC_OP_TSF_RESET;
+                ah->opmode = NL80211_IFTYPE_AP;
+        } else {
+                ath9k_hw_set_tsfadjust(ah, 0);
+                sc->sc_flags &= ~SC_OP_TSF_RESET;
+
+                if (iter_data.nmeshes)
+                        ah->opmode = NL80211_IFTYPE_MESH_POINT;
+                else if (iter_data.nwds)
+                        ah->opmode = NL80211_IFTYPE_AP;
+                else if (iter_data.nadhocs)
+                        ah->opmode = NL80211_IFTYPE_ADHOC;
+                else
+                        ah->opmode = NL80211_IFTYPE_STATION;
         }
 
-        /* Set the device opmode */
-        ah->opmode = ic_opmode;
-
         /*
          * Enable MIB interrupts when there are hardware phy counters.
-         * Note we only do this (at the moment) for station mode.
          */
-        if ((vif->type == NL80211_IFTYPE_STATION) ||
-            (vif->type == NL80211_IFTYPE_ADHOC) ||
-            (vif->type == NL80211_IFTYPE_MESH_POINT)) {
+        if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
                 if (ah->config.enable_ani)
                         ah->imask |= ATH9K_INT_MIB;
                 ah->imask |= ATH9K_INT_TSFOOR;
+        } else {
+                ah->imask &= ~ATH9K_INT_MIB;
+                ah->imask &= ~ATH9K_INT_TSFOOR;
         }
 
         ath9k_hw_set_interrupts(ah, ah->imask);
 
-        if (vif->type == NL80211_IFTYPE_AP    ||
-            vif->type == NL80211_IFTYPE_ADHOC ||
-            vif->type == NL80211_IFTYPE_MONITOR) {
+        /* Set up ANI */
+        if ((iter_data.naps + iter_data.nadhocs) > 0) {
+                sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
                 sc->sc_flags |= SC_OP_ANI_RUN;
                 ath_start_ani(common);
+        } else {
+                sc->sc_flags &= ~SC_OP_ANI_RUN;
+                del_timer_sync(&common->ani.timer);
         }
+}
+
+/* Called with sc->mutex held, vif counts set up properly. */
+static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
+                                   struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+
+        ath9k_calculate_summary_state(hw, vif);
+
+        if (ath9k_uses_beacons(vif->type)) {
+                int error;
+                /* This may fail because upper levels do not have beacons
+                 * properly configured yet.  That's OK, we assume it
+                 * will be properly configured and then we will be notified
+                 * in the info_changed method and set up beacons properly
+                 * there.
+                 */
+                ath9k_set_beaconing_status(sc, false);
+                error = ath_beacon_alloc(sc, vif);
+                if (!error)
+                        ath_beacon_config(sc, vif);
+                ath9k_set_beaconing_status(sc, true);
+        }
+}
 
+
+static int ath9k_add_interface(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret = 0;
+
+        ath9k_ps_wakeup(sc);
+        mutex_lock(&sc->mutex);
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_STATION:
+        case NL80211_IFTYPE_WDS:
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_MESH_POINT:
+                break;
+        default:
+                ath_err(common, "Interface type %d not yet supported\n",
+                        vif->type);
+                ret = -EOPNOTSUPP;
+                goto out;
+        }
+
+        if (ath9k_uses_beacons(vif->type)) {
+                if (sc->nbcnvifs >= ATH_BCBUF) {
+                        ath_err(common, "Not enough beacon buffers when adding"
+                                " new interface of type: %i\n",
+                                vif->type);
+                        ret = -ENOBUFS;
+                        goto out;
+                }
+        }
+
+        if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
+            ((vif->type == NL80211_IFTYPE_ADHOC) &&
+             sc->nvifs > 0)) {
+                ath_err(common, "Cannot create ADHOC interface when other"
+                        " interfaces already exist.\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attach a VIF of type: %d\n", vif->type);
+
+        sc->nvifs++;
+
+        ath9k_do_vif_add_setup(hw, vif);
 out:
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
         return ret;
 }
 
-static void ath9k_remove_interface(struct ieee80211_hw *hw,
-                                   struct ieee80211_vif *vif)
+static int ath9k_change_interface(struct ieee80211_hw *hw,
+                                  struct ieee80211_vif *vif,
+                                  enum nl80211_iftype new_type,
+                                  bool p2p)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_vif *avp = (void *)vif->drv_priv;
-        int i;
-
-        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
+        int ret = 0;
 
+        ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
 
-        /* Stop ANI */
-        sc->sc_flags &= ~SC_OP_ANI_RUN;
-        del_timer_sync(&common->ani.timer);
-
-        /* Reclaim beacon resources */
-        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
-                ath9k_ps_wakeup(sc);
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                ath9k_ps_restore(sc);
+        /* See if new interface type is valid. */
+        if ((new_type == NL80211_IFTYPE_ADHOC) &&
+            (sc->nvifs > 1)) {
+                ath_err(common, "When using ADHOC, it must be the only"
+                        " interface.\n");
+                ret = -EINVAL;
+                goto out;
         }
 
-        ath_beacon_return(sc, avp);
-        sc->sc_flags &= ~SC_OP_BEACONS;
-
-        for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
-                if (sc->beacon.bslot[i] == vif) {
-                        printk(KERN_DEBUG "%s: vif had allocated beacon "
-                               "slot\n", __func__);
-                        sc->beacon.bslot[i] = NULL;
-                        sc->beacon.bslot_aphy[i] = NULL;
+        if (ath9k_uses_beacons(new_type) &&
+            !ath9k_uses_beacons(vif->type)) {
+                if (sc->nbcnvifs >= ATH_BCBUF) {
+                        ath_err(common, "No beacon slot available\n");
+                        ret = -ENOBUFS;
+                        goto out;
                 }
         }
 
+        /* Clean up old vif stuff */
+        if (ath9k_uses_beacons(vif->type))
+                ath9k_reclaim_beacon(sc, vif);
+
+        /* Add new settings */
+        vif->type = new_type;
+        vif->p2p = p2p;
+
+        ath9k_do_vif_add_setup(hw, vif);
+out:
+        ath9k_ps_restore(sc);
+        mutex_unlock(&sc->mutex);
+        return ret;
+}
+
+static void ath9k_remove_interface(struct ieee80211_hw *hw,
+                                   struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+
+        ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
+
+        ath9k_ps_wakeup(sc);
+        mutex_lock(&sc->mutex);
+
         sc->nvifs--;
 
+        /* Reclaim beacon resources */
+        if (ath9k_uses_beacons(vif->type))
+                ath9k_reclaim_beacon(sc, vif);
+
+        ath9k_calculate_summary_state(hw, NULL);
+
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 }
 
-void ath9k_enable_ps(struct ath_softc *sc)
+static void ath9k_enable_ps(struct ath_softc *sc)
 {
         struct ath_hw *ah = sc->sc_ah;
 
@@ -1505,14 +1586,33 @@ void ath9k_enable_ps(struct ath_softc *sc)
         }
 }
 
+static void ath9k_disable_ps(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+
+        sc->ps_enabled = false;
+        ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
+        if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
+                ath9k_hw_setrxabort(ah, 0);
+                sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
+                                  PS_WAIT_FOR_CAB |
+                                  PS_WAIT_FOR_PSPOLL_DATA |
+                                  PS_WAIT_FOR_TX_ACK);
+                if (ah->imask & ATH9K_INT_TIM_TIMER) {
+                        ah->imask &= ~ATH9K_INT_TIM_TIMER;
+                        ath9k_hw_set_interrupts(ah, ah->imask);
+                }
+        }
+
+}
+
 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ieee80211_conf *conf = &hw->conf;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
-        bool disable_radio;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_conf *conf = &hw->conf;
+        bool disable_radio = false;
 
         mutex_lock(&sc->mutex);
 
@@ -1523,29 +1623,13 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
          * the end.
          */
         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
-                bool enable_radio;
-                bool all_wiphys_idle;
-                bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
-
-                spin_lock_bh(&sc->wiphy_lock);
-                all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
-                ath9k_set_wiphy_idle(aphy, idle);
-
-                enable_radio = (!idle && all_wiphys_idle);
-
-                /*
-                 * After we unlock here its possible another wiphy
-                 * can be re-renabled so to account for that we will
-                 * only disable the radio toward the end of this routine
-                 * if by then all wiphys are still idle.
-                 */
-                spin_unlock_bh(&sc->wiphy_lock);
-
-                if (enable_radio) {
-                        sc->ps_idle = false;
+                sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
+                if (!sc->ps_idle) {
                         ath_radio_enable(sc, hw);
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "not-idle: enabling radio\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "not-idle: enabling radio\n");
+                } else {
+                        disable_radio = true;
                 }
         }
 
@@ -1556,96 +1640,100 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
          */
         if (changed & IEEE80211_CONF_CHANGE_PS) {
-                if (conf->flags & IEEE80211_CONF_PS) {
-                        sc->ps_flags |= PS_ENABLED;
-                        /*
-                         * At this point we know hardware has received an ACK
-                         * of a previously sent null data frame.
-                         */
-                        if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
-                                sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
-                                ath9k_enable_ps(sc);
-                        }
-                } else {
-                        sc->ps_enabled = false;
-                        sc->ps_flags &= ~(PS_ENABLED |
-                                          PS_NULLFUNC_COMPLETED);
-                        ath9k_setpower(sc, ATH9K_PM_AWAKE);
-                        if (!(ah->caps.hw_caps &
-                              ATH9K_HW_CAP_AUTOSLEEP)) {
-                                ath9k_hw_setrxabort(sc->sc_ah, 0);
-                                sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
-                                                  PS_WAIT_FOR_CAB |
-                                                  PS_WAIT_FOR_PSPOLL_DATA |
-                                                  PS_WAIT_FOR_TX_ACK);
-                                if (ah->imask & ATH9K_INT_TIM_TIMER) {
-                                        ah->imask &= ~ATH9K_INT_TIM_TIMER;
-                                        ath9k_hw_set_interrupts(sc->sc_ah,
-                                                        ah->imask);
-                                }
-                        }
-                }
+                unsigned long flags;
+                spin_lock_irqsave(&sc->sc_pm_lock, flags);
+                if (conf->flags & IEEE80211_CONF_PS)
+                        ath9k_enable_ps(sc);
+                else
+                        ath9k_disable_ps(sc);
+                spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
         }
 
         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
                 if (conf->flags & IEEE80211_CONF_MONITOR) {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "HW opmode set to Monitor mode\n");
-                        sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor mode is enabled\n");
+                        sc->sc_ah->is_monitoring = true;
+                } else {
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor mode is disabled\n");
+                        sc->sc_ah->is_monitoring = false;
                 }
         }
 
         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
                 struct ieee80211_channel *curchan = hw->conf.channel;
                 int pos = curchan->hw_value;
+                int old_pos = -1;
+                unsigned long flags;
+
+                if (ah->curchan)
+                        old_pos = ah->curchan - &ah->channels[0];
 
-                aphy->chan_idx = pos;
-                aphy->chan_is_ht = conf_is_ht(conf);
                 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
                         sc->sc_flags |= SC_OP_OFFCHANNEL;
                 else
                         sc->sc_flags &= ~SC_OP_OFFCHANNEL;
 
-                if (aphy->state == ATH_WIPHY_SCAN ||
-                    aphy->state == ATH_WIPHY_ACTIVE)
-                        ath9k_wiphy_pause_all_forced(sc, aphy);
-                else {
-                        /*
-                         * Do not change operational channel based on a paused
-                         * wiphy changes.
-                         */
-                        goto skip_chan_change;
-                }
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Set channel: %d MHz type: %d\n",
+                        curchan->center_freq, conf->channel_type);
 
-                ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
-                          curchan->center_freq);
+                ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
+                                          curchan, conf->channel_type);
 
-                /* XXX: remove me eventualy */
-                ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
+                /* update survey stats for the old channel before switching */
+                spin_lock_irqsave(&common->cc_lock, flags);
+                ath_update_survey_stats(sc);
+                spin_unlock_irqrestore(&common->cc_lock, flags);
 
-                ath_update_chainmask(sc, conf_is_ht(conf));
+                /*
+                 * If the operating channel changes, change the survey in-use flags
+                 * along with it.
+                 * Reset the survey data for the new channel, unless we're switching
+                 * back to the operating channel from an off-channel operation.
+                 */
+                if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
+                    sc->cur_survey != &sc->survey[pos]) {
+
+                        if (sc->cur_survey)
+                                sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
+
+                        sc->cur_survey = &sc->survey[pos];
+
+                        memset(sc->cur_survey, 0, sizeof(struct survey_info));
+                        sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
+                } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
+                        memset(&sc->survey[pos], 0, sizeof(struct survey_info));
+                }
 
                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to set channel\n");
+                        ath_err(common, "Unable to set channel\n");
                         mutex_unlock(&sc->mutex);
                         return -EINVAL;
                 }
+
+                /*
+                 * The most recent snapshot of channel->noisefloor for the old
+                 * channel is only available after the hardware reset. Copy it to
+                 * the survey stats now.
+                 */
+                if (old_pos >= 0)
+                        ath_update_survey_nf(sc, old_pos);
         }
 
-skip_chan_change:
         if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Set power: %d\n", conf->power_level);
                 sc->config.txpowlimit = 2 * conf->power_level;
-                ath_update_txpow(sc);
+                ath9k_ps_wakeup(sc);
+                ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                                       sc->config.txpowlimit, &sc->curtxpow);
+                ath9k_ps_restore(sc);
         }
 
-        spin_lock_bh(&sc->wiphy_lock);
-        disable_radio = ath9k_all_wiphys_idle(sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-
         if (disable_radio) {
-                ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
-                sc->ps_idle = true;
+                ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
                 ath_radio_disable(sc, hw);
         }
 
@@ -1661,6 +1749,7 @@ skip_chan_change:
         FIF_PSPOLL |                            \
         FIF_OTHER_BSS |                         \
         FIF_BCN_PRBRESP_PROMISC |               \
+        FIF_PROBE_REQ |                         \
         FIF_FCSFAIL)
 
 /* FIXME: sc->sc_full_reset ? */
@@ -1669,8 +1758,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
                                    unsigned int *total_flags,
                                    u64 multicast)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         u32 rfilt;
 
         changed_flags &= SUPPORTED_FILTERS;
@@ -1682,46 +1770,92 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
         ath9k_ps_restore(sc);
 
-        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                  "Set HW RX filter: 0x%x\n", rfilt);
+        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                "Set HW RX filter: 0x%x\n", rfilt);
 }
 
 static int ath9k_sta_add(struct ieee80211_hw *hw,
                          struct ieee80211_vif *vif,
                          struct ieee80211_sta *sta)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_node *an = (struct ath_node *) sta->drv_priv;
+        struct ieee80211_key_conf ps_key = { };
 
         ath_node_attach(sc, sta);
 
+        if (vif->type != NL80211_IFTYPE_AP &&
+            vif->type != NL80211_IFTYPE_AP_VLAN)
+                return 0;
+
+        an->ps_key = ath_key_config(common, vif, sta, &ps_key);
+
         return 0;
 }
 
+static void ath9k_del_ps_key(struct ath_softc *sc,
+                             struct ieee80211_vif *vif,
+                             struct ieee80211_sta *sta)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_node *an = (struct ath_node *) sta->drv_priv;
+        struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
+
+        if (!an->ps_key)
+            return;
+
+        ath_key_delete(common, &ps_key);
+}
+
 static int ath9k_sta_remove(struct ieee80211_hw *hw,
                             struct ieee80211_vif *vif,
                             struct ieee80211_sta *sta)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
+        ath9k_del_ps_key(sc, vif, sta);
         ath_node_detach(sc, sta);
 
         return 0;
 }
 
+static void ath9k_sta_notify(struct ieee80211_hw *hw,
+                         struct ieee80211_vif *vif,
+                         enum sta_notify_cmd cmd,
+                         struct ieee80211_sta *sta)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_node *an = (struct ath_node *) sta->drv_priv;
+
+        switch (cmd) {
+        case STA_NOTIFY_SLEEP:
+                an->sleeping = true;
+                if (ath_tx_aggr_sleep(sc, an))
+                        ieee80211_sta_set_tim(sta);
+                break;
+        case STA_NOTIFY_AWAKE:
+                an->sleeping = false;
+                ath_tx_aggr_wakeup(sc, an);
+                break;
+        }
+}
+
 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
                          const struct ieee80211_tx_queue_params *params)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_txq *txq;
         struct ath9k_tx_queue_info qi;
-        int ret = 0, qnum;
+        int ret = 0;
 
         if (queue >= WME_NUM_AC)
                 return 0;
 
+        txq = sc->tx.txq_map[queue];
+
+        ath9k_ps_wakeup(sc);
         mutex_lock(&sc->mutex);
 
         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -1730,23 +1864,22 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
         qi.tqi_cwmin = params->cw_min;
         qi.tqi_cwmax = params->cw_max;
         qi.tqi_burstTime = params->txop;
-        qnum = ath_get_hal_qnum(queue, sc);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Configure tx [queue/halq] [%d/%d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, qnum, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                queue, txq->axq_qnum, params->aifs, params->cw_min,
+                params->cw_max, params->txop);
 
-        ret = ath_txq_update(sc, qnum, &qi);
+        ret = ath_txq_update(sc, txq->axq_qnum, &qi);
         if (ret)
-                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+                ath_err(common, "TXQ Update failed\n");
 
         if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
-                if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
+                if (queue == WME_AC_BE && !ret)
                         ath_beaconq_config(sc);
 
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 
         return ret;
 }
@@ -1757,34 +1890,51 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
                          struct ieee80211_sta *sta,
                          struct ieee80211_key_conf *key)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int ret = 0;
 
-        if (modparam_nohwcrypt)
+        if (ath9k_modparam_nohwcrypt)
                 return -ENOSPC;
 
+        if (vif->type == NL80211_IFTYPE_ADHOC &&
+            (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
+             key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
+            !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
+                /*
+                 * For now, disable hw crypto for the RSN IBSS group keys. This
+                 * could be optimized in the future to use a modified key cache
+                 * design to support per-STA RX GTK, but until that gets
+                 * implemented, use of software crypto for group addressed
+                 * frames is a acceptable to allow RSN IBSS to be used.
+                 */
+                return -EOPNOTSUPP;
+        }
+
         mutex_lock(&sc->mutex);
         ath9k_ps_wakeup(sc);
-        ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
 
         switch (cmd) {
         case SET_KEY:
-                ret = ath9k_cmn_key_config(common, vif, sta, key);
+                if (sta)
+                        ath9k_del_ps_key(sc, vif, sta);
+
+                ret = ath_key_config(common, vif, sta, key);
                 if (ret >= 0) {
                         key->hw_key_idx = ret;
                         /* push IV and Michael MIC generation to stack */
                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
-                        if (key->alg == ALG_TKIP)
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
-                        if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
+                        if (sc->sc_ah->sw_mgmt_crypto &&
+                            key->cipher == WLAN_CIPHER_SUITE_CCMP)
                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
                         ret = 0;
                 }
                 break;
         case DISABLE_KEY:
-                ath9k_cmn_key_delete(common, key);
+                ath_key_delete(common, key);
                 break;
         default:
                 ret = -EINVAL;
@@ -1795,51 +1945,123 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
 
         return ret;
 }
+static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = data;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath_vif *avp = (void *)vif->drv_priv;
+
+        switch (sc->sc_ah->opmode) {
+        case NL80211_IFTYPE_ADHOC:
+                /* There can be only one vif available */
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                common->curaid = bss_conf->aid;
+                ath9k_hw_write_associd(sc->sc_ah);
+                /* configure beacon */
+                if (bss_conf->enable_beacon)
+                        ath_beacon_config(sc, vif);
+                break;
+        case NL80211_IFTYPE_STATION:
+                /*
+                 * Skip iteration if primary station vif's bss info
+                 * was not changed
+                 */
+                if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
+                        break;
+
+                if (bss_conf->assoc) {
+                        sc->sc_flags |= SC_OP_PRIM_STA_VIF;
+                        avp->primary_sta_vif = true;
+                        memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                        common->curaid = bss_conf->aid;
+                        ath9k_hw_write_associd(sc->sc_ah);
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Bss Info ASSOC %d, bssid: %pM\n",
+                                bss_conf->aid, common->curbssid);
+                        ath_beacon_config(sc, vif);
+                        /*
+                         * Request a re-configuration of Beacon related timers
+                         * on the receipt of the first Beacon frame (i.e.,
+                         * after time sync with the AP).
+                         */
+                        sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
+                        /* Reset rssi stats */
+                        sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
+                        sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
+
+                        sc->sc_flags |= SC_OP_ANI_RUN;
+                        ath_start_ani(common);
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath_vif *avp = (void *)vif->drv_priv;
+
+        /* Reconfigure bss info */
+        if (avp->primary_sta_vif && !bss_conf->assoc) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Bss Info DISASSOC %d, bssid %pM\n",
+                        common->curaid, common->curbssid);
+                sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
+                avp->primary_sta_vif = false;
+                memset(common->curbssid, 0, ETH_ALEN);
+                common->curaid = 0;
+        }
+
+        ieee80211_iterate_active_interfaces_atomic(
+                        sc->hw, ath9k_bss_iter, sc);
+
+        /*
+         * None of station vifs are associated.
+         * Clear bssid & aid
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+            !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
+                ath9k_hw_write_associd(sc->sc_ah);
+                /* Stop ANI */
+                sc->sc_flags &= ~SC_OP_ANI_RUN;
+                del_timer_sync(&common->ani.timer);
+        }
+}
 
 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
                                    struct ieee80211_vif *vif,
                                    struct ieee80211_bss_conf *bss_conf,
                                    u32 changed)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_vif *avp = (void *)vif->drv_priv;
         int slottime;
         int error;
 
+        ath9k_ps_wakeup(sc);
         mutex_lock(&sc->mutex);
 
         if (changed & BSS_CHANGED_BSSID) {
-                /* Set BSSID */
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
-                common->curaid = 0;
-                ath9k_hw_write_associd(ah);
-
-                /* Set aggregation protection mode parameters */
-                sc->config.ath_aggr_prot = 0;
+                ath9k_config_bss(sc, vif);
 
-                /* Only legacy IBSS for now */
-                if (vif->type == NL80211_IFTYPE_ADHOC)
-                        ath_update_chainmask(sc, 0);
-
-                ath_print(common, ATH_DBG_CONFIG,
-                          "BSSID: %pM aid: 0x%x\n",
-                          common->curbssid, common->curaid);
-
-                /* need to reconfigure the beacon */
-                sc->sc_flags &= ~SC_OP_BEACONS ;
+                ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
+                        common->curbssid, common->curaid);
         }
 
         /* Enable transmission of beacons (AP, IBSS, MESH) */
         if ((changed & BSS_CHANGED_BEACON) ||
             ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                error = ath_beacon_alloc(aphy, vif);
+                ath9k_set_beaconing_status(sc, false);
+                error = ath_beacon_alloc(sc, vif);
                 if (!error)
                         ath_beacon_config(sc, vif);
+                ath9k_set_beaconing_status(sc, true);
         }
 
         if (changed & BSS_CHANGED_ERP_SLOT) {
@@ -1862,29 +2084,32 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         /* Disable transmission of beacons */
-        if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
+        if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
+            !bss_conf->enable_beacon) {
+                ath9k_set_beaconing_status(sc, false);
+                avp->is_bslot_active = false;
+                ath9k_set_beaconing_status(sc, true);
+        }
 
         if (changed & BSS_CHANGED_BEACON_INT) {
-                sc->beacon_interval = bss_conf->beacon_int;
                 /*
                  * In case of AP mode, the HW TSF has to be reset
                  * when the beacon interval changes.
                  */
                 if (vif->type == NL80211_IFTYPE_AP) {
                         sc->sc_flags |= SC_OP_TSF_RESET;
-                        ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                        error = ath_beacon_alloc(aphy, vif);
+                        ath9k_set_beaconing_status(sc, false);
+                        error = ath_beacon_alloc(sc, vif);
                         if (!error)
                                 ath_beacon_config(sc, vif);
-                } else {
+                        ath9k_set_beaconing_status(sc, true);
+                } else
                         ath_beacon_config(sc, vif);
-                }
         }
 
         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
-                          bss_conf->use_short_preamble);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
+                        bss_conf->use_short_preamble);
                 if (bss_conf->use_short_preamble)
                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
                 else
@@ -1892,8 +2117,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
-                          bss_conf->use_cts_prot);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
+                        bss_conf->use_cts_prot);
                 if (bss_conf->use_cts_prot &&
                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -1901,23 +2126,19 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
         }
 
-        if (changed & BSS_CHANGED_ASSOC) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
-                        bss_conf->assoc);
-                ath9k_bss_assoc_info(sc, vif, bss_conf);
-        }
-
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 }
 
 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
 {
+        struct ath_softc *sc = hw->priv;
         u64 tsf;
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
 
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
         tsf = ath9k_hw_gettsf64(sc->sc_ah);
+        ath9k_ps_restore(sc);
         mutex_unlock(&sc->mutex);
 
         return tsf;
@@ -1925,18 +2146,18 @@ static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
 
 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
         ath9k_hw_settsf64(sc->sc_ah, tsf);
+        ath9k_ps_restore(sc);
         mutex_unlock(&sc->mutex);
 }
 
 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
         mutex_lock(&sc->mutex);
 
@@ -1951,10 +2172,9 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                               struct ieee80211_vif *vif,
                               enum ieee80211_ampdu_mlme_action action,
                               struct ieee80211_sta *sta,
-                              u16 tid, u16 *ssn)
+                              u16 tid, u16 *ssn, u8 buf_size)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         int ret = 0;
 
         local_bh_disable();
@@ -1967,9 +2187,13 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
         case IEEE80211_AMPDU_RX_STOP:
                 break;
         case IEEE80211_AMPDU_TX_START:
+                if (!(sc->sc_flags & SC_OP_TXAGGR))
+                        return -EOPNOTSUPP;
+
                 ath9k_ps_wakeup(sc);
-                ath_tx_aggr_start(sc, sta, tid, ssn);
-                ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+                ret = ath_tx_aggr_start(sc, sta, tid, ssn);
+                if (!ret)
+                        ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
                 ath9k_ps_restore(sc);
                 break;
         case IEEE80211_AMPDU_TX_STOP:
@@ -1984,8 +2208,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                 ath9k_ps_restore(sc);
                 break;
         default:
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unknown AMPDU action\n");
+                ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
         }
 
         local_bh_enable();
@@ -1996,71 +2219,158 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
                              struct survey_info *survey)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ieee80211_conf *conf = &hw->conf;
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *chan;
+        unsigned long flags;
+        int pos;
 
-         if (idx != 0)
+        spin_lock_irqsave(&common->cc_lock, flags);
+        if (idx == 0)
+                ath_update_survey_stats(sc);
+
+        sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
+        if (sband && idx >= sband->n_channels) {
+                idx -= sband->n_channels;
+                sband = NULL;
+        }
+
+        if (!sband)
+                sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
+
+        if (!sband || idx >= sband->n_channels) {
+                spin_unlock_irqrestore(&common->cc_lock, flags);
                 return -ENOENT;
+        }
 
-        survey->channel = conf->channel;
-        survey->filled = SURVEY_INFO_NOISE_DBM;
-        survey->noise = common->ani.noise_floor;
+        chan = &sband->channels[idx];
+        pos = chan->hw_value;
+        memcpy(survey, &sc->survey[pos], sizeof(*survey));
+        survey->channel = chan;
+        spin_unlock_irqrestore(&common->cc_lock, flags);
 
         return 0;
 }
 
-static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
+static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
 
         mutex_lock(&sc->mutex);
-        if (ath9k_wiphy_scanning(sc)) {
-                /*
-                 * There is a race here in mac80211 but fixing it requires
-                 * we revisit how we handle the scan complete callback.
-                 * After mac80211 fixes we will not have configured hardware
-                 * to the home channel nor would we have configured the RX
-                 * filter yet.
-                 */
+        ah->coverage_class = coverage_class;
+        ath9k_hw_init_global_settings(ah);
+        mutex_unlock(&sc->mutex);
+}
+
+static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int timeout = 200; /* ms */
+        int i, j;
+        bool drain_txq;
+
+        mutex_lock(&sc->mutex);
+        cancel_delayed_work_sync(&sc->tx_complete_work);
+
+        if (sc->sc_flags & SC_OP_INVALID) {
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&sc->mutex);
                 return;
         }
 
-        aphy->state = ATH_WIPHY_SCAN;
-        ath9k_wiphy_pause_all_forced(sc, aphy);
-        sc->sc_flags |= SC_OP_SCANNING;
+        if (drop)
+                timeout = 1;
+
+        for (j = 0; j < timeout; j++) {
+                bool npend = false;
+
+                if (j)
+                        usleep_range(1000, 2000);
+
+                for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+                        if (!ATH_TXQ_SETUP(sc, i))
+                                continue;
+
+                        npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
+
+                        if (npend)
+                                break;
+                }
+
+                if (!npend)
+                    goto out;
+        }
+
+        ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+        drain_txq = ath_drain_all_txq(sc, false);
+        spin_unlock_bh(&sc->sc_pcu_lock);
+        if (!drain_txq)
+                ath_reset(sc, false);
+        ath9k_ps_restore(sc);
+        ieee80211_wake_queues(hw);
+
+out:
+        ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
         mutex_unlock(&sc->mutex);
 }
 
-/*
- * XXX: this requires a revisit after the driver
- * scan_complete gets moved to another place/removed in mac80211.
- */
-static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
+static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
+        int i;
 
-        mutex_lock(&sc->mutex);
-        aphy->state = ATH_WIPHY_ACTIVE;
-        sc->sc_flags &= ~SC_OP_SCANNING;
-        mutex_unlock(&sc->mutex);
+        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+                if (!ATH_TXQ_SETUP(sc, i))
+                        continue;
+
+                if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
+                        return true;
+        }
+        return false;
 }
 
-static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
+int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
+        struct ieee80211_vif *vif;
+        struct ath_vif *avp;
+        struct ath_buf *bf;
+        struct ath_tx_status ts;
+        int status;
+
+        vif = sc->beacon.bslot[0];
+        if (!vif)
+                return 0;
 
-        mutex_lock(&sc->mutex);
-        ah->coverage_class = coverage_class;
-        ath9k_hw_init_global_settings(ah);
-        mutex_unlock(&sc->mutex);
+        avp = (void *)vif->drv_priv;
+        if (!avp->is_bslot_active)
+                return 0;
+
+        if (!sc->beacon.tx_processed) {
+                tasklet_disable(&sc->bcon_tasklet);
+
+                bf = avp->av_bcbuf;
+                if (!bf || !bf->bf_mpdu)
+                        goto skip;
+
+                status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
+                if (status == -EINPROGRESS)
+                        goto skip;
+
+                sc->beacon.tx_processed = true;
+                sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
+
+skip:
+                tasklet_enable(&sc->bcon_tasklet);
+        }
+
+        return sc->beacon.tx_last;
 }
 
 struct ieee80211_ops ath9k_ops = {
@@ -2068,11 +2378,13 @@ struct ieee80211_ops ath9k_ops = {
         .start              = ath9k_start,
         .stop               = ath9k_stop,
         .add_interface      = ath9k_add_interface,
+        .change_interface   = ath9k_change_interface,
         .remove_interface   = ath9k_remove_interface,
         .config             = ath9k_config,
         .configure_filter   = ath9k_configure_filter,
         .sta_add            = ath9k_sta_add,
         .sta_remove         = ath9k_sta_remove,
+        .sta_notify         = ath9k_sta_notify,
         .conf_tx            = ath9k_conf_tx,
         .bss_info_changed   = ath9k_bss_info_changed,
         .set_key            = ath9k_set_key,
@@ -2081,8 +2393,9 @@ struct ieee80211_ops ath9k_ops = {
         .reset_tsf          = ath9k_reset_tsf,
         .ampdu_action       = ath9k_ampdu_action,
         .get_survey         = ath9k_get_survey,
-        .sw_scan_start      = ath9k_sw_scan_start,
-        .sw_scan_complete   = ath9k_sw_scan_complete,
         .rfkill_poll        = ath9k_rfkill_poll_state,
         .set_coverage_class = ath9k_set_coverage_class,
+        .flush              = ath9k_flush,
+        .tx_frames_pending  = ath9k_tx_frames_pending,
+        .tx_last_beacon = ath9k_tx_last_beacon,
 };
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index b5b651413e77..3bad0b2cf9a3 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,6 +16,7 @@
 
 #include <linux/nl80211.h>
 #include <linux/pci.h>
+#include <linux/ath9k_platform.h>
 #include "ath9k.h"
 
 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
@@ -29,6 +30,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
+        { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
         { 0 }
 };
 
@@ -42,7 +44,7 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
         *csz = (int)u8tmp;
 
         /*
-         * This check was put in to avoid "unplesant" consequences if
+         * This check was put in to avoid "unpleasant" consequences if
          * the bootrom has not fully initialized all PCI devices.
          * Sometimes the cache line size register is not set
          */
@@ -53,21 +55,35 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
 
 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 {
-        struct ath_hw *ah = (struct ath_hw *) common->ah;
-
-        common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
-
-        if (!ath9k_hw_wait(ah,
-                           AR_EEPROM_STATUS_DATA,
-                           AR_EEPROM_STATUS_DATA_BUSY |
-                           AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
-                           AH_WAIT_TIMEOUT)) {
-                return false;
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        struct ath9k_platform_data *pdata = sc->dev->platform_data;
+
+        if (pdata) {
+                if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
+                        ath_err(common,
+                                "%s: eeprom read failed, offset %08x is out of range\n",
+                                __func__, off);
+                }
+
+                *data = pdata->eeprom_data[off];
+        } else {
+                struct ath_hw *ah = (struct ath_hw *) common->ah;
+
+                common->ops->read(ah, AR5416_EEPROM_OFFSET +
+                                      (off << AR5416_EEPROM_S));
+
+                if (!ath9k_hw_wait(ah,
+                                   AR_EEPROM_STATUS_DATA,
+                                   AR_EEPROM_STATUS_DATA_BUSY |
+                                   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
+                                   AH_WAIT_TIMEOUT)) {
+                        return false;
+                }
+
+                *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
+                           AR_EEPROM_STATUS_DATA_VAL);
         }
 
-        *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
-                   AR_EEPROM_STATUS_DATA_VAL);
-
         return true;
 }
 
@@ -80,7 +96,7 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
         struct pci_dev *pdev = to_pci_dev(sc->dev);
         u8 aspm;
 
-        if (!pdev->is_pcie)
+        if (!pci_is_pcie(pdev))
                 return;
 
         pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
@@ -88,17 +104,28 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
         pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
 }
 
+static void ath_pci_extn_synch_enable(struct ath_common *common)
+{
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        struct pci_dev *pdev = to_pci_dev(sc->dev);
+        u8 lnkctl;
+
+        pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
+        lnkctl |= PCI_EXP_LNKCTL_ES;
+        pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
+}
+
 static const struct ath_bus_ops ath_pci_bus_ops = {
         .ath_bus_type = ATH_PCI,
         .read_cachesize = ath_pci_read_cachesize,
         .eeprom_read = ath_pci_eeprom_read,
         .bt_coex_prep = ath_pci_bt_coex_prep,
+        .extn_synch_en = ath_pci_extn_synch_enable,
 };
 
 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
         void __iomem *mem;
-        struct ath_wiphy *aphy;
         struct ath_softc *sc;
         struct ieee80211_hw *hw;
         u8 csz;
@@ -170,8 +197,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
                 goto err_iomap;
         }
 
-        hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
-                                sizeof(struct ath_softc), &ath9k_ops);
+        hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
         if (!hw) {
                 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
                 ret = -ENOMEM;
@@ -181,11 +207,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         SET_IEEE80211_DEV(hw, &pdev->dev);
         pci_set_drvdata(pdev, hw);
 
-        aphy = hw->priv;
-        sc = (struct ath_softc *) (aphy + 1);
-        aphy->sc = sc;
-        aphy->hw = hw;
-        sc->pri_wiphy = aphy;
+        sc = hw->priv;
         sc->hw = hw;
         sc->dev = &pdev->dev;
         sc->mem = mem;
@@ -232,10 +254,11 @@ err_dma:
 static void ath_pci_remove(struct pci_dev *pdev)
 {
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         void __iomem *mem = sc->mem;
 
+        if (!is_ath9k_unloaded)
+                sc->sc_ah->ah_flags |= AH_UNPLUGGED;
         ath9k_deinit_device(sc);
         free_irq(sc->irq, sc);
         ieee80211_free_hw(sc->hw);
@@ -247,34 +270,29 @@ static void ath_pci_remove(struct pci_dev *pdev)
 
 #ifdef CONFIG_PM
 
-static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+static int ath_pci_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
-        pci_save_state(pdev);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, PCI_D3hot);
+        /* The device has to be moved to FULLSLEEP forcibly.
+         * Otherwise the chip never moved to full sleep,
+         * when no interface is up.
+         */
+        ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 
         return 0;
 }
 
-static int ath_pci_resume(struct pci_dev *pdev)
+static int ath_pci_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         u32 val;
-        int err;
-
-        pci_restore_state(pdev);
-
-        err = pci_enable_device(pdev);
-        if (err)
-                return err;
 
         /*
          * Suspend/Resume resets the PCI configuration space, so we have to
@@ -290,10 +308,37 @@ static int ath_pci_resume(struct pci_dev *pdev)
                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
+          /*
+           * Reset key cache to sane defaults (all entries cleared) instead of
+           * semi-random values after suspend/resume.
+           */
+        ath9k_ps_wakeup(sc);
+        ath9k_init_crypto(sc);
+        ath9k_ps_restore(sc);
+
+        sc->ps_idle = true;
+        ath_radio_disable(sc, hw);
+
         return 0;
 }
 
-#endif /* CONFIG_PM */
+static const struct dev_pm_ops ath9k_pm_ops = {
+        .suspend = ath_pci_suspend,
+        .resume = ath_pci_resume,
+        .freeze = ath_pci_suspend,
+        .thaw = ath_pci_resume,
+        .poweroff = ath_pci_suspend,
+        .restore = ath_pci_resume,
+};
+
+#define ATH9K_PM_OPS    (&ath9k_pm_ops)
+
+#else /* !CONFIG_PM */
+
+#define ATH9K_PM_OPS    NULL
+
+#endif /* !CONFIG_PM */
+
 
 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 
@@ -302,10 +347,7 @@ static struct pci_driver ath_pci_driver = {
         .id_table   = ath_pci_id_table,
         .probe      = ath_pci_probe,
         .remove     = ath_pci_remove,
-#ifdef CONFIG_PM
-        .suspend    = ath_pci_suspend,
-        .resume     = ath_pci_resume,
-#endif /* CONFIG_PM */
+        .driver.pm  = ATH9K_PM_OPS,
 };
 
 int ath_pci_init(void)
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index e724c2c1ae2a..8b380305b0fc 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -37,29 +37,15 @@
 #define AR_PHY_CLC_Q0        0x0000ffd0
 #define AR_PHY_CLC_Q0_S      5
 
-#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
-                int r;                                                  \
-                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
-                        REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
-                        DO_DELAY(regWr);                                \
-                }                                                       \
-        } while (0)
-
-#define ATH9K_IS_MIC_ENABLED(ah)                                        \
-        ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
-
 #define ANTSWAP_AB 0x0001
 #define REDUCE_CHAIN_0 0x00000050
 #define REDUCE_CHAIN_1 0x00000051
 #define AR_PHY_CHIP_ID 0x9818
 
-#define RF_BANK_SETUP(_bank, _iniarray, _col) do {                      \
-                int i;                                                  \
-                for (i = 0; i < (_iniarray)->ia_rows; i++)              \
-                        (_bank)[i] = INI_RA((_iniarray), i, _col);;     \
-        } while (0)
-
 #define AR_PHY_TIMING11_SPUR_FREQ_SD            0x3FF00000
 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S          20
 
+#define AR_PHY_PLL_CONTROL 0x16180
+#define AR_PHY_PLL_MODE 0x16184
+
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index e49be733d546..ba7f36ab0a74 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2004 Video54 Technologies, Inc.
- * Copyright (c) 2004-2009 Atheros Communications, Inc.
+ * Copyright (c) 2004-2011 Atheros Communications, Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -302,7 +302,7 @@ static const struct ath_rate_table ar5416_11ng_ratetable = {
                 [64] = {  RC_INVALID, WLAN_RC_PHY_HT_40_TS, 243000,
                         205100, 20, 20, 8, 64, 65, 65 }, /* 243 Mb */
                 [65] = {  RC_INVALID, WLAN_RC_PHY_HT_40_TS_HGI, 270000,
-                        224700, 20, 20, 8, 64, 65, 65 }, /* 170 Mb */
+                        224700, 20, 20, 8, 64, 65, 65 }, /* 270 Mb */
                 [66] = {  RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 324000,
                         263100, 21, 21, 8, 66, 67, 67 }, /* 324 Mb */
                 [67] = {  RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 360000,
@@ -378,39 +378,9 @@ static const struct ath_rate_table ar5416_11g_ratetable = {
         0,   /* Phy rates allowed initially */
 };
 
-static const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX] = {
-        [ATH9K_MODE_11A] = &ar5416_11a_ratetable,
-        [ATH9K_MODE_11G] = &ar5416_11g_ratetable,
-        [ATH9K_MODE_11NA_HT20] = &ar5416_11na_ratetable,
-        [ATH9K_MODE_11NG_HT20] = &ar5416_11ng_ratetable,
-        [ATH9K_MODE_11NA_HT40PLUS] = &ar5416_11na_ratetable,
-        [ATH9K_MODE_11NA_HT40MINUS] = &ar5416_11na_ratetable,
-        [ATH9K_MODE_11NG_HT40PLUS] = &ar5416_11ng_ratetable,
-        [ATH9K_MODE_11NG_HT40MINUS] = &ar5416_11ng_ratetable,
-};
-
 static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
                                 struct ieee80211_tx_rate *rate);
 
-static inline int8_t median(int8_t a, int8_t b, int8_t c)
-{
-        if (a >= b) {
-                if (b >= c)
-                        return b;
-                else if (a > c)
-                        return c;
-                else
-                        return a;
-        } else {
-                if (a >= c)
-                        return a;
-                else if (b >= c)
-                        return c;
-                else
-                        return b;
-        }
-}
-
 static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
                                    struct ath_rate_priv *ath_rc_priv)
 {
@@ -430,7 +400,7 @@ static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
         }
 }
 
-static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
+static void ath_rc_init_valid_rate_idx(struct ath_rate_priv *ath_rc_priv)
 {
         u8 i;
 
@@ -438,7 +408,7 @@ static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
                 ath_rc_priv->valid_rate_index[i] = 0;
 }
 
-static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv,
+static inline void ath_rc_set_valid_rate_idx(struct ath_rate_priv *ath_rc_priv,
                                            u8 index, int valid_tx_rate)
 {
         BUG_ON(index > ath_rc_priv->rate_table_size);
@@ -519,7 +489,7 @@ static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv,
 
                         ath_rc_priv->valid_phy_rateidx[phy][valid_rate_count] = i;
                         ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                        ath_rc_set_valid_txmask(ath_rc_priv, i, 1);
+                        ath_rc_set_valid_rate_idx(ath_rc_priv, i, 1);
                         hi = i;
                 }
         }
@@ -538,7 +508,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
         for (i = 0; i < rateset->rs_nrates; i++) {
                 for (j = 0; j < rate_table->rate_cnt; j++) {
                         u32 phy = rate_table->info[j].phy;
-                        u16 rate_flags = rate_table->info[i].rate_flags;
+                        u16 rate_flags = rate_table->info[j].rate_flags;
                         u8 rate = rateset->rs_rates[i];
                         u8 dot11rate = rate_table->info[j].dot11rate;
 
@@ -562,7 +532,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
                                 ath_rc_priv->valid_phy_rateidx[phy]
                                         [valid_rate_count] = j;
                                 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                                ath_rc_set_valid_txmask(ath_rc_priv, j, 1);
+                                ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
                                 hi = A_MAX(hi, j);
                         }
                 }
@@ -598,7 +568,7 @@ static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv,
                         ath_rc_priv->valid_phy_rateidx[phy]
                                 [ath_rc_priv->valid_phy_ratecnt[phy]] = j;
                         ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                        ath_rc_set_valid_txmask(ath_rc_priv, j, 1);
+                        ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
                         hi = A_MAX(hi, j);
                 }
         }
@@ -719,7 +689,8 @@ static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table,
 
         if (WLAN_RC_PHY_HT(rate_table->info[rix].phy)) {
                 rate->flags |= IEEE80211_TX_RC_MCS;
-                if (WLAN_RC_PHY_40(rate_table->info[rix].phy))
+                if (WLAN_RC_PHY_40(rate_table->info[rix].phy) &&
+                    conf_is_ht40(&txrc->hw->conf))
                         rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
                 if (WLAN_RC_PHY_SGI(rate_table->info[rix].phy))
                         rate->flags |= IEEE80211_TX_RC_SHORT_GI;
@@ -791,7 +762,7 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
          */
         try_per_rate = 4;
 
-        rate_table = sc->cur_rate_table;
+        rate_table = ath_rc_priv->rate_table;
         rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
 
         /*
@@ -822,7 +793,7 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
 
                 tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
         } else {
-                /* Set the choosen rate. No RTS for first series entry. */
+                /* Set the chosen rate. No RTS for first series entry. */
                 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
                                        try_per_rate, rix, 0);
         }
@@ -884,17 +855,16 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
         ath_rc_rate_set_rtscts(sc, rate_table, tx_info);
 }
 
-static bool ath_rc_update_per(struct ath_softc *sc,
+static void ath_rc_update_per(struct ath_softc *sc,
                               const struct ath_rate_table *rate_table,
                               struct ath_rate_priv *ath_rc_priv,
                                   struct ieee80211_tx_info *tx_info,
                               int tx_rate, int xretries, int retries,
                               u32 now_msec)
 {
-        bool state_change = false;
         int count, n_bad_frames;
         u8 last_per;
-        static u32 nretry_to_per_lookup[10] = {
+        static const u32 nretry_to_per_lookup[10] = {
                 100 * 0 / 1,
                 100 * 1 / 4,
                 100 * 1 / 2,
@@ -1022,8 +992,16 @@ static bool ath_rc_update_per(struct ath_softc *sc,
 
                 }
         }
+}
 
-        return state_change;
+static void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
+                                   int xretries, int retries, u8 per)
+{
+        struct ath_rc_stats *stats = &rc->rcstats[rix];
+
+        stats->xretries += xretries;
+        stats->retries += retries;
+        stats->per = per;
 }
 
 /* Update PER, RSSI and whatever else that the code thinks it is doing.
@@ -1037,8 +1015,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
         u32 now_msec = jiffies_to_msecs(jiffies);
         int rate;
         u8 last_per;
-        bool state_change = false;
-        const struct ath_rate_table *rate_table = sc->cur_rate_table;
+        const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
         int size = ath_rc_priv->rate_table_size;
 
         if ((tx_rate < 0) || (tx_rate > rate_table->rate_cnt))
@@ -1047,9 +1024,9 @@ static void ath_rc_update_ht(struct ath_softc *sc,
         last_per = ath_rc_priv->per[tx_rate];
 
         /* Update PER first */
-        state_change = ath_rc_update_per(sc, rate_table, ath_rc_priv,
-                                         tx_info, tx_rate, xretries,
-                                         retries, now_msec);
+        ath_rc_update_per(sc, rate_table, ath_rc_priv,
+                          tx_info, tx_rate, xretries,
+                          retries, now_msec);
 
         /*
          * If this rate looks bad (high PER) then stop using it for
@@ -1098,7 +1075,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
                 ath_rc_priv->per_down_time = now_msec;
         }
 
-        ath_debug_stat_retries(sc, tx_rate, xretries, retries,
+        ath_debug_stat_retries(ath_rc_priv, tx_rate, xretries, retries,
                                ath_rc_priv->per[tx_rate]);
 
 }
@@ -1107,13 +1084,12 @@ static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
                                 struct ieee80211_tx_rate *rate)
 {
         int rix = 0, i = 0;
-        int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
+        static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
 
         if (!(rate->flags & IEEE80211_TX_RC_MCS))
                 return rate->idx;
 
-        while (rate->idx > mcs_rix_off[i] &&
-              i < sizeof(mcs_rix_off)/sizeof(int)) {
+        while (i < ARRAY_SIZE(mcs_rix_off) && rate->idx > mcs_rix_off[i]) {
                 rix++; i++;
         }
 
@@ -1140,7 +1116,7 @@ static void ath_rc_tx_status(struct ath_softc *sc,
         u8 flags;
         u32 i = 0, rix;
 
-        rate_table = sc->cur_rate_table;
+        rate_table = ath_rc_priv->rate_table;
 
         /*
          * If the first rate is not the final index, there
@@ -1190,39 +1166,23 @@ static void ath_rc_tx_status(struct ath_softc *sc,
 static const
 struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
                                              enum ieee80211_band band,
-                                             bool is_ht,
-                                             bool is_cw_40)
+                                             bool is_ht)
 {
-        int mode = 0;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 
         switch(band) {
         case IEEE80211_BAND_2GHZ:
-                mode = ATH9K_MODE_11G;
                 if (is_ht)
-                        mode = ATH9K_MODE_11NG_HT20;
-                if (is_cw_40)
-                        mode = ATH9K_MODE_11NG_HT40PLUS;
-                break;
+                        return &ar5416_11ng_ratetable;
+                return &ar5416_11g_ratetable;
         case IEEE80211_BAND_5GHZ:
-                mode = ATH9K_MODE_11A;
                 if (is_ht)
-                        mode = ATH9K_MODE_11NA_HT20;
-                if (is_cw_40)
-                        mode = ATH9K_MODE_11NA_HT40PLUS;
-                break;
+                        return &ar5416_11na_ratetable;
+                return &ar5416_11a_ratetable;
         default:
-                ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
+                ath_dbg(common, ATH_DBG_CONFIG, "Invalid band\n");
                 return NULL;
         }
-
-        BUG_ON(mode >= ATH9K_MODE_MAX);
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Choosing rate table for mode: %d\n", mode);
-
-        sc->cur_rate_mode = mode;
-        return hw_rate_table[mode];
 }
 
 static void ath_rc_init(struct ath_softc *sc,
@@ -1246,7 +1206,7 @@ static void ath_rc_init(struct ath_softc *sc,
         }
 
         /* Determine the valid rates */
-        ath_rc_init_valid_txmask(ath_rc_priv);
+        ath_rc_init_valid_rate_idx(ath_rc_priv);
 
         for (i = 0; i < WLAN_RC_PHY_MAX; i++) {
                 for (j = 0; j < MAX_TX_RATE_PHY; j++)
@@ -1293,11 +1253,11 @@ static void ath_rc_init(struct ath_softc *sc,
         ath_rc_priv->max_valid_rate = k;
         ath_rc_sort_validrates(rate_table, ath_rc_priv);
         ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
-        sc->cur_rate_table = rate_table;
+        ath_rc_priv->rate_table = rate_table;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "RC Initialized with capabilities: 0x%x\n",
-                  ath_rc_priv->ht_cap);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "RC Initialized with capabilities: 0x%x\n",
+                ath_rc_priv->ht_cap);
 }
 
 static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1320,10 +1280,35 @@ static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
         return caps;
 }
 
+static bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an,
+                              u8 tidno)
+{
+        struct ath_atx_tid *txtid;
+
+        if (!(sc->sc_flags & SC_OP_TXAGGR))
+                return false;
+
+        txtid = ATH_AN_2_TID(an, tidno);
+
+        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
+                        return true;
+        return false;
+}
+
+
 /***********************************/
 /* mac80211 Rate Control callbacks */
 /***********************************/
 
+static void ath_debug_stat_rc(struct ath_rate_priv *rc, int final_rate)
+{
+        struct ath_rc_stats *stats;
+
+        stats = &rc->rcstats[final_rate];
+        stats->success++;
+}
+
+
 static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
                           struct ieee80211_sta *sta, void *priv_sta,
                           struct sk_buff *skb)
@@ -1332,14 +1317,14 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
         struct ath_rate_priv *ath_rc_priv = priv_sta;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         struct ieee80211_hdr *hdr;
-        int final_ts_idx = 0, tx_status = 0, is_underrun = 0;
+        int final_ts_idx = 0, tx_status = 0;
         int long_retry = 0;
         __le16 fc;
         int i;
 
         hdr = (struct ieee80211_hdr *)skb->data;
         fc = hdr->frame_control;
-        for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
+        for (i = 0; i < sc->hw->max_rates; i++) {
                 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i];
                 if (!rate->count)
                         break;
@@ -1359,32 +1344,23 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
         if (tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED)
                 return;
 
-        /*
-         * If an underrun error is seen assume it as an excessive retry only
-         * if max frame trigger level has been reached (2 KB for singel stream,
-         * and 4 KB for dual stream). Adjust the long retry as if the frame was
-         * tried hw->max_rate_tries times to affect how ratectrl updates PER for
-         * the failed rate. In case of congestion on the bus penalizing these
-         * type of underruns should help hardware actually transmit new frames
-         * successfully by eventually preferring slower rates. This itself
-         * should also alleviate congestion on the bus.
-         */
-        if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
-            (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
-                tx_status = 1;
-                is_underrun = 1;
+        if (!(tx_info->flags & IEEE80211_TX_STAT_AMPDU)) {
+                tx_info->status.ampdu_ack_len =
+                        (tx_info->flags & IEEE80211_TX_STAT_ACK ? 1 : 0);
+                tx_info->status.ampdu_len = 1;
         }
 
-        if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
+        if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
                 tx_status = 1;
 
         ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
-                         (is_underrun) ? sc->hw->max_rate_tries : long_retry);
+                         long_retry);
 
         /* Check if aggregation has to be enabled for this tid */
         if (conf_is_ht(&sc->hw->conf) &&
             !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
-                if (ieee80211_is_data_qos(fc)) {
+                if (ieee80211_is_data_qos(fc) &&
+                    skb_get_queue_mapping(skb) != IEEE80211_AC_VO) {
                         u8 *qc, tid;
                         struct ath_node *an;
 
@@ -1393,12 +1369,13 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
                         an = (struct ath_node *)sta->drv_priv;
 
                         if(ath_tx_aggr_check(sc, an, tid))
-                                ieee80211_start_tx_ba_session(sta, tid);
+                                ieee80211_start_tx_ba_session(sta, tid, 0);
                 }
         }
 
-        ath_debug_stat_rc(sc, ath_rc_get_rateindex(sc->cur_rate_table,
-                &tx_info->status.rates[final_ts_idx]));
+        ath_debug_stat_rc(ath_rc_priv,
+                ath_rc_get_rateindex(ath_rc_priv->rate_table,
+                        &tx_info->status.rates[final_ts_idx]));
 }
 
 static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
@@ -1429,23 +1406,17 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
                 ath_rc_priv->neg_ht_rates.rs_nrates = j;
         }
 
-        is_cw40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
+        is_cw40 = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
 
         if (is_cw40)
-                is_sgi = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
+                is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
         else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
-                is_sgi = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
+                is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
 
         /* Choose rate table first */
 
-        if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) {
-                rate_table = ath_choose_rate_table(sc, sband->band,
-                                      sta->ht_cap.ht_supported, is_cw40);
-        } else {
-                rate_table = hw_rate_table[sc->cur_rate_mode];
-        }
+        rate_table = ath_choose_rate_table(sc, sband->band,
+                              sta->ht_cap.ht_supported);
 
         ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta, is_cw40, is_sgi);
         ath_rc_init(sc, priv_sta, sband, sta, rate_table);
@@ -1459,10 +1430,8 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
         struct ath_rate_priv *ath_rc_priv = priv_sta;
         const struct ath_rate_table *rate_table = NULL;
         bool oper_cw40 = false, oper_sgi;
-        bool local_cw40 = (ath_rc_priv->ht_cap & WLAN_RC_40_FLAG) ?
-                true : false;
-        bool local_sgi = (ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG) ?
-                true : false;
+        bool local_cw40 = !!(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG);
+        bool local_sgi = !!(ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG);
 
         /* FIXME: Handle AP mode later when we support CWM */
 
@@ -1485,24 +1454,109 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
 
                 if ((local_cw40 != oper_cw40) || (local_sgi != oper_sgi)) {
                         rate_table = ath_choose_rate_table(sc, sband->band,
-                                                   sta->ht_cap.ht_supported,
-                                                   oper_cw40);
+                                                   sta->ht_cap.ht_supported);
                         ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta,
                                                    oper_cw40, oper_sgi);
                         ath_rc_init(sc, priv_sta, sband, sta, rate_table);
 
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                                  "Operating HT Bandwidth changed to: %d\n",
-                                  sc->hw->conf.channel_type);
-                        sc->cur_rate_table = hw_rate_table[sc->cur_rate_mode];
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                                "Operating HT Bandwidth changed to: %d\n",
+                                sc->hw->conf.channel_type);
+                }
+        }
+}
+
+#ifdef CONFIG_ATH9K_DEBUGFS
+
+static int ath9k_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
+                                size_t count, loff_t *ppos)
+{
+        struct ath_rate_priv *rc = file->private_data;
+        char *buf;
+        unsigned int len = 0, max;
+        int i = 0;
+        ssize_t retval;
+
+        if (rc->rate_table == NULL)
+                return 0;
+
+        max = 80 + rc->rate_table->rate_cnt * 1024 + 1;
+        buf = kmalloc(max, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += sprintf(buf, "%6s %6s %6s "
+                       "%10s %10s %10s %10s\n",
+                       "HT", "MCS", "Rate",
+                       "Success", "Retries", "XRetries", "PER");
+
+        for (i = 0; i < rc->rate_table->rate_cnt; i++) {
+                u32 ratekbps = rc->rate_table->info[i].ratekbps;
+                struct ath_rc_stats *stats = &rc->rcstats[i];
+                char mcs[5];
+                char htmode[5];
+                int used_mcs = 0, used_htmode = 0;
+
+                if (WLAN_RC_PHY_HT(rc->rate_table->info[i].phy)) {
+                        used_mcs = snprintf(mcs, 5, "%d",
+                                rc->rate_table->info[i].ratecode);
+
+                        if (WLAN_RC_PHY_40(rc->rate_table->info[i].phy))
+                                used_htmode = snprintf(htmode, 5, "HT40");
+                        else if (WLAN_RC_PHY_20(rc->rate_table->info[i].phy))
+                                used_htmode = snprintf(htmode, 5, "HT20");
+                        else
+                                used_htmode = snprintf(htmode, 5, "????");
                 }
+
+                mcs[used_mcs] = '\0';
+                htmode[used_htmode] = '\0';
+
+                len += snprintf(buf + len, max - len,
+                        "%6s %6s %3u.%d: "
+                        "%10u %10u %10u %10u\n",
+                        htmode,
+                        mcs,
+                        ratekbps / 1000,
+                        (ratekbps % 1000) / 100,
+                        stats->success,
+                        stats->retries,
+                        stats->xretries,
+                        stats->per);
         }
+
+        if (len > max)
+                len = max;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+        return retval;
 }
 
+static const struct file_operations fops_rcstat = {
+        .read = read_file_rcstat,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE
+};
+
+static void ath_rate_add_sta_debugfs(void *priv, void *priv_sta,
+                                     struct dentry *dir)
+{
+        struct ath_rate_priv *rc = priv_sta;
+        debugfs_create_file("rc_stats", S_IRUGO, dir, rc, &fops_rcstat);
+}
+
+#endif /* CONFIG_ATH9K_DEBUGFS */
+
 static void *ath_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        return aphy->sc;
+        return hw->priv;
 }
 
 static void ath_rate_free(void *priv)
@@ -1517,13 +1571,11 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
 
         rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
         if (!rate_priv) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to allocate private rc structure\n");
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to allocate private rc structure\n");
                 return NULL;
         }
 
-        rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
-
         return rate_priv;
 }
 
@@ -1545,6 +1597,9 @@ static struct rate_control_ops ath_rate_ops = {
         .free = ath_rate_free,
         .alloc_sta = ath_rate_alloc_sta,
         .free_sta = ath_rate_free_sta,
+#ifdef CONFIG_ATH9K_DEBUGFS
+        .add_sta_debugfs = ath_rate_add_sta_debugfs,
+#endif
 };
 
 int ath_rate_control_register(void)
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index dc1082654501..c3d850207bee 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2004 Sam Leffler, Errno Consulting
  * Copyright (c) 2004 Video54 Technologies, Inc.
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -135,20 +135,21 @@ enum {
 
 /**
  * struct ath_rate_table - Rate Control table
- * @valid: valid for use in rate control
- * @valid_single_stream: valid for use in rate control for
- *      single stream operation
- * @phy: CCK/OFDM
+ * @rate_cnt: total number of rates for the given wireless mode
+ * @mcs_start: MCS rate index offset
+ * @rate_flags: Rate Control flags
+ * @phy: CCK/OFDM/HT20/HT40
  * @ratekbps: rate in Kbits per second
  * @user_ratekbps: user rate in Kbits per second
  * @ratecode: rate that goes into HW descriptors
- * @short_preamble: Mask for enabling short preamble in ratecode for CCK
  * @dot11rate: value that goes into supported
  *      rates info element of MLME
  * @ctrl_rate: Index of next lower basic rate, used for duration computation
- * @max_4ms_framelen: maximum frame length(bytes) for tx duration
+ * @cw40index: Index of rates having 40MHz channel width
+ * @sgi_index: Index of rates having Short Guard Interval
+ * @ht_index: high throughput rates having 40MHz channel width and
+ *      Short Guard Interval
  * @probe_interval: interval for rate control to probe for other rates
- * @rssi_reduce_interval: interval for rate control to reduce rssi
  * @initial_ratemax: initial ratemax value
  */
 struct ath_rate_table {
@@ -175,6 +176,13 @@ struct ath_rateset {
         u8 rs_rates[ATH_RATE_MAX];
 };
 
+struct ath_rc_stats {
+        u32 success;
+        u32 retries;
+        u32 xretries;
+        u8 per;
+};
+
 /**
  * struct ath_rate_priv - Rate Control priv data
  * @state: RC state
@@ -187,7 +195,6 @@ struct ath_rateset {
  * @rate_max_phy: phy index for the max rate
  * @per: PER for every valid rate in %
  * @probe_interval: interval for ratectrl to probe for other rates
- * @prev_data_rix: rate idx of last data frame
  * @ht_cap: HT capabilities
  * @neg_rates: Negotatied rates
  * @neg_ht_rates: Negotiated HT rates
@@ -206,17 +213,13 @@ struct ath_rate_priv {
         u32 probe_time;
         u32 per_down_time;
         u32 probe_interval;
-        u32 prev_data_rix;
-        u32 tx_triglevel_max;
         struct ath_rateset neg_rates;
         struct ath_rateset neg_ht_rates;
-        struct ath_rate_softc *asc;
-};
+        const struct ath_rate_table *rate_table;
 
-#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
-#define ATH_TX_INFO_FRAME_TYPE_PAUSE    (1 << 1)
-#define ATH_TX_INFO_XRETRY              (1 << 3)
-#define ATH_TX_INFO_UNDERRUN            (1 << 4)
+        struct dentry *debugfs_rcstats;
+        struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
+};
 
 enum ath9k_internal_frame_type {
         ATH9K_IFT_NOT_INTERNAL,
@@ -224,7 +227,18 @@ enum ath9k_internal_frame_type {
         ATH9K_IFT_UNPAUSE
 };
 
+#ifdef CONFIG_ATH9K_RATE_CONTROL
 int ath_rate_control_register(void);
 void ath_rate_control_unregister(void);
+#else
+static inline int ath_rate_control_register(void)
+{
+        return 0;
+}
+
+static inline void ath_rate_control_unregister(void)
+{
+}
+#endif
 
 #endif /* RC_H */
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index a3fc987ebab0..07e35e59c9e3 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,31 +19,46 @@
 
 #define SKB_CB_ATHBUF(__skb)    (*((struct ath_buf **)__skb->cb))
 
-static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
+static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
+                                               int mindelta, int main_rssi_avg,
+                                               int alt_rssi_avg, int pkt_count)
 {
-        return sc->ps_enabled &&
-               (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
+        return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
+                (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
+                (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
 }
 
-static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
-                                             struct ieee80211_hdr *hdr)
+static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
+                                        int curr_main_set, int curr_alt_set,
+                                        int alt_rssi_avg, int main_rssi_avg)
 {
-        struct ieee80211_hw *hw = sc->pri_wiphy->hw;
-        int i;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
-                        continue;
-                if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
-                    == 0) {
-                        hw = aphy->hw;
-                        break;
-                }
+        bool result = false;
+        switch (div_group) {
+        case 0:
+                if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
+                        result = true;
+                break;
+        case 1:
+                if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
+                        (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
+                                (alt_rssi_avg >= (main_rssi_avg - 5))) ||
+                        ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
+                        (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
+                                (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
+                                                        (alt_rssi_avg >= 4))
+                        result = true;
+                else
+                        result = false;
+                break;
         }
-        spin_unlock_bh(&sc->wiphy_lock);
-        return hw;
+
+        return result;
+}
+
+static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
+{
+        return sc->ps_enabled &&
+               (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
 }
 
 /*
@@ -87,7 +102,6 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
                 *sc->rx.rxlink = bf->bf_daddr;
 
         sc->rx.rxlink = &ds->ds_link;
-        ath9k_hw_rxena(ah);
 }
 
 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
@@ -110,8 +124,7 @@ static void ath_opmode_init(struct ath_softc *sc)
         ath9k_hw_setrxfilter(ah, rfilt);
 
         /* configure bssid mask */
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                ath_hw_setbssidmask(common);
+        ath_hw_setbssidmask(common);
 
         /* configure operational mode */
         ath9k_hw_setopmode(ah);
@@ -157,7 +170,7 @@ static void ath_rx_addbuffer_edma(struct ath_softc *sc,
         u32 nbuf = 0;
 
         if (list_empty(&sc->rx.rxbuf)) {
-                ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
+                ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
                 return;
         }
 
@@ -222,11 +235,6 @@ static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
         int error = 0, i;
         u32 size;
 
-
-        common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
-                                     ah->caps.rx_status_len,
-                                     min(common->cachelsz, (u16)64));
-
         ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
                                     ah->caps.rx_status_len);
 
@@ -260,7 +268,8 @@ static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
                                                 bf->bf_buf_addr))) {
                                 dev_kfree_skb_any(skb);
                                 bf->bf_mpdu = NULL;
-                                ath_print(common, ATH_DBG_FATAL,
+                                bf->bf_buf_addr = 0;
+                                ath_err(common,
                                         "dma_mapping_error() on RX init\n");
                                 error = -ENOMEM;
                                 goto rx_init_fail;
@@ -288,19 +297,17 @@ static void ath_edma_start_recv(struct ath_softc *sc)
         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
                               sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
 
-        spin_unlock_bh(&sc->rx.rxbuflock);
-
         ath_opmode_init(sc);
 
-        ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_SCANNING));
+        ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+
+        spin_unlock_bh(&sc->rx.rxbuflock);
 }
 
 static void ath_edma_stop_recv(struct ath_softc *sc)
 {
-        spin_lock_bh(&sc->rx.rxbuflock);
         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
-        spin_unlock_bh(&sc->rx.rxbuflock);
 }
 
 int ath_rx_init(struct ath_softc *sc, int nbufs)
@@ -310,27 +317,27 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
         struct ath_buf *bf;
         int error = 0;
 
-        spin_lock_init(&sc->rx.rxflushlock);
+        spin_lock_init(&sc->sc_pcu_lock);
         sc->sc_flags &= ~SC_OP_RXFLUSH;
         spin_lock_init(&sc->rx.rxbuflock);
 
+        common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
+                             sc->sc_ah->caps.rx_status_len;
+
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 return ath_rx_edma_init(sc, nbufs);
         } else {
-                common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
-                                min(common->cachelsz, (u16)64));
-
-                ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
-                                common->cachelsz, common->rx_bufsize);
+                ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
+                        common->cachelsz, common->rx_bufsize);
 
                 /* Initialize rx descriptors */
 
                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
                                 "rx", nbufs, 1, 0);
                 if (error != 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "failed to allocate rx descriptors: %d\n",
-                                  error);
+                        ath_err(common,
+                                "failed to allocate rx descriptors: %d\n",
+                                error);
                         goto err;
                 }
 
@@ -350,12 +357,12 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
                                                         bf->bf_buf_addr))) {
                                 dev_kfree_skb_any(skb);
                                 bf->bf_mpdu = NULL;
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "dma_mapping_error() on RX init\n");
+                                bf->bf_buf_addr = 0;
+                                ath_err(common,
+                                        "dma_mapping_error() on RX init\n");
                                 error = -ENOMEM;
                                 goto err;
                         }
-                        bf->bf_dmacontext = bf->bf_buf_addr;
                 }
                 sc->rx.rxlink = NULL;
         }
@@ -385,6 +392,8 @@ void ath_rx_cleanup(struct ath_softc *sc)
                                                 common->rx_bufsize,
                                                 DMA_FROM_DEVICE);
                                 dev_kfree_skb(skb);
+                                bf->bf_buf_addr = 0;
+                                bf->bf_mpdu = NULL;
                         }
                 }
 
@@ -422,8 +431,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
                 | ATH9K_RX_FILTER_MCAST;
 
-        /* If not a STA, enable processing of Probe Requests */
-        if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
+        if (sc->rx.rxfilter & FIF_PROBE_REQ)
                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 
         /*
@@ -431,32 +439,27 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
          * mode interface or when in monitor mode. AP mode does not need this
          * since it receives all in-BSS frames anyway.
          */
-        if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
-             (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
+        if (sc->sc_ah->is_monitoring)
                 rfilt |= ATH9K_RX_FILTER_PROM;
 
         if (sc->rx.rxfilter & FIF_CONTROL)
                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 
         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+            (sc->nvifs <= 1) &&
             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
         else
                 rfilt |= ATH9K_RX_FILTER_BEACON;
 
-        if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
-            AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
-            (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
             (sc->rx.rxfilter & FIF_PSPOLL))
                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
 
         if (conf_is_ht(&sc->hw->conf))
                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
 
-        if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
-                /* TODO: only needed if more than one BSSID is in use in
-                 * station/adhoc mode */
+        if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
                 /* The following may also be needed for other older chips */
                 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
                         rfilt |= ATH9K_RX_FILTER_PROM;
@@ -496,9 +499,10 @@ int ath_startrecv(struct ath_softc *sc)
         ath9k_hw_rxena(ah);
 
 start_recv:
-        spin_unlock_bh(&sc->rx.rxbuflock);
         ath_opmode_init(sc);
-        ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_SCANNING));
+        ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+
+        spin_unlock_bh(&sc->rx.rxbuflock);
 
         return 0;
 }
@@ -506,29 +510,36 @@ start_recv:
 bool ath_stoprecv(struct ath_softc *sc)
 {
         struct ath_hw *ah = sc->sc_ah;
-        bool stopped;
+        bool stopped, reset = false;
 
-        ath9k_hw_stoppcurecv(ah);
+        spin_lock_bh(&sc->rx.rxbuflock);
+        ath9k_hw_abortpcurecv(ah);
         ath9k_hw_setrxfilter(ah, 0);
-        stopped = ath9k_hw_stopdmarecv(ah);
+        stopped = ath9k_hw_stopdmarecv(ah, &reset);
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                 ath_edma_stop_recv(sc);
         else
                 sc->rx.rxlink = NULL;
+        spin_unlock_bh(&sc->rx.rxbuflock);
 
-        return stopped;
+        if (!(ah->ah_flags & AH_UNPLUGGED) &&
+            unlikely(!stopped)) {
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Could not stop RX, we could be "
+                        "confusing the DMA engine when we start RX up\n");
+                ATH_DBG_WARN_ON_ONCE(!stopped);
+        }
+        return stopped && !reset;
 }
 
 void ath_flushrecv(struct ath_softc *sc)
 {
-        spin_lock_bh(&sc->rx.rxflushlock);
         sc->sc_flags |= SC_OP_RXFLUSH;
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                 ath_rx_tasklet(sc, 1, true);
         ath_rx_tasklet(sc, 1, false);
         sc->sc_flags &= ~SC_OP_RXFLUSH;
-        spin_unlock_bh(&sc->rx.rxflushlock);
 }
 
 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
@@ -572,17 +583,23 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                 return;
 
         mgmt = (struct ieee80211_mgmt *)skb->data;
-        if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
+        if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
+                /* TODO:  This doesn't work well if you have stations
+                 * associated to two different APs because curbssid
+                 * is just the last AP that any of the stations associated
+                 * with.
+                 */
                 return; /* not from our current AP */
+        }
 
         sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
 
         if (sc->ps_flags & PS_BEACON_SYNC) {
                 sc->ps_flags &= ~PS_BEACON_SYNC;
-                ath_print(common, ATH_DBG_PS,
-                          "Reconfigure Beacon timers based on "
-                          "timestamp from the AP\n");
-                ath_beacon_config(sc, NULL);
+                ath_dbg(common, ATH_DBG_PS,
+                        "Reconfigure Beacon timers based on timestamp from the AP\n");
+                ath_set_beacon(sc);
+                sc->ps_flags &= ~PS_TSFOOR_SYNC;
         }
 
         if (ath_beacon_dtim_pending_cab(skb)) {
@@ -593,8 +610,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                  * a backup trigger for returning into NETWORK SLEEP state,
                  * so we are waiting for it as well.
                  */
-                ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
-                          "buffered broadcast/multicast frame(s)\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
                 return;
         }
@@ -606,8 +623,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                  * been delivered.
                  */
                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
-                ath_print(common, ATH_DBG_PS,
-                          "PS wait for CAB frames timed out\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "PS wait for CAB frames timed out\n");
         }
 }
 
@@ -631,16 +648,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
                  * No more broadcast/multicast frames to be received at this
                  * point.
                  */
-                sc->ps_flags &= ~PS_WAIT_FOR_CAB;
-                ath_print(common, ATH_DBG_PS,
-                          "All PS CAB frames received, back to sleep\n");
+                sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
+                ath_dbg(common, ATH_DBG_PS,
+                        "All PS CAB frames received, back to sleep\n");
         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
                    !is_multicast_ether_addr(hdr->addr1) &&
                    !ieee80211_has_morefrags(hdr->frame_control)) {
                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
-                ath_print(common, ATH_DBG_PS,
-                          "Going back to sleep after having received "
-                          "PS-Poll data (0x%lx)\n",
+                ath_dbg(common, ATH_DBG_PS,
+                        "Going back to sleep after having received PS-Poll data (0x%lx)\n",
                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                         PS_WAIT_FOR_CAB |
                                         PS_WAIT_FOR_PSPOLL_DATA |
@@ -648,38 +664,6 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
         }
 }
 
-static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
-                                    struct ath_softc *sc, struct sk_buff *skb,
-                                    struct ieee80211_rx_status *rxs)
-{
-        struct ieee80211_hdr *hdr;
-
-        hdr = (struct ieee80211_hdr *)skb->data;
-
-        /* Send the frame to mac80211 */
-        if (is_multicast_ether_addr(hdr->addr1)) {
-                int i;
-                /*
-                 * Deliver broadcast/multicast frames to all suitable
-                 * virtual wiphys.
-                 */
-                /* TODO: filter based on channel configuration */
-                for (i = 0; i < sc->num_sec_wiphy; i++) {
-                        struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                        struct sk_buff *nskb;
-                        if (aphy == NULL)
-                                continue;
-                        nskb = skb_copy(skb, GFP_ATOMIC);
-                        if (!nskb)
-                                continue;
-                        ieee80211_rx(aphy->hw, nskb);
-                }
-                ieee80211_rx(sc->hw, skb);
-        } else
-                /* Deliver unicast frames based on receiver address */
-                ieee80211_rx(hw, skb);
-}
-
 static bool ath_edma_get_buffers(struct ath_softc *sc,
                                  enum ath9k_rx_qtype qtype)
 {
@@ -829,6 +813,10 @@ static bool ath9k_rx_accept(struct ath_common *common,
                             struct ath_rx_status *rx_stats,
                             bool *decrypt_error)
 {
+#define is_mc_or_valid_tkip_keyix ((is_mc ||                    \
+                (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
+                test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
+
         struct ath_hw *ah = common->ah;
         __le16 fc;
         u8 rx_status_len = ah->caps.rx_status_len;
@@ -845,15 +833,9 @@ static bool ath9k_rx_accept(struct ath_common *common,
         if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
                 return false;
 
-        /*
-         * rs_more indicates chained descriptors which can be used
-         * to link buffers together for a sort of scatter-gather
-         * operation.
-         * reject the frame, we don't support scatter-gather yet and
-         * the frame is probably corrupt anyway
-         */
+        /* Only use error bits from the last fragment */
         if (rx_stats->rs_more)
-                return false;
+                return true;
 
         /*
          * The rx_stats->rs_status will not be set until the end of the
@@ -870,22 +852,28 @@ static bool ath9k_rx_accept(struct ath_common *common,
                 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
                         *decrypt_error = true;
                 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
-                        if (ieee80211_is_ctl(fc))
-                                /*
-                                 * Sometimes, we get invalid
-                                 * MIC failures on valid control frames.
-                                 * Remove these mic errors.
-                                 */
-                                rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
-                        else
+                        bool is_mc;
+                        /*
+                         * The MIC error bit is only valid if the frame
+                         * is not a control frame or fragment, and it was
+                         * decrypted using a valid TKIP key.
+                         */
+                        is_mc = !!is_multicast_ether_addr(hdr->addr1);
+
+                        if (!ieee80211_is_ctl(fc) &&
+                            !ieee80211_has_morefrags(fc) &&
+                            !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
+                            is_mc_or_valid_tkip_keyix)
                                 rxs->flag |= RX_FLAG_MMIC_ERROR;
+                        else
+                                rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
                 }
                 /*
                  * Reject error frames with the exception of
                  * decryption and MIC failures. For monitor mode,
                  * we also ignore the CRC error.
                  */
-                if (ah->opmode == NL80211_IFTYPE_MONITOR) {
+                if (ah->is_monitoring) {
                         if (rx_stats->rs_status &
                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
                               ATH9K_RXERR_CRC))
@@ -939,8 +927,9 @@ static int ath9k_process_rate(struct ath_common *common,
          * No valid hardware bitrate found -- we should not get here
          * because hardware has already validated this frame as OK.
          */
-        ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
-                  "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
+        ath_dbg(common, ATH_DBG_XMIT,
+                "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
+                rx_stats->rs_rate);
 
         return -EINVAL;
 }
@@ -950,32 +939,30 @@ static void ath9k_process_rssi(struct ath_common *common,
                                struct ieee80211_hdr *hdr,
                                struct ath_rx_status *rx_stats)
 {
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = common->ah;
-        struct ieee80211_sta *sta;
-        struct ath_node *an;
-        int last_rssi = ATH_RSSI_DUMMY_MARKER;
+        int last_rssi;
         __le16 fc;
 
-        fc = hdr->frame_control;
+        if ((ah->opmode != NL80211_IFTYPE_STATION) &&
+            (ah->opmode != NL80211_IFTYPE_ADHOC))
+                return;
 
-        rcu_read_lock();
-        /*
-         * XXX: use ieee80211_find_sta! This requires quite a bit of work
-         * under the current ath9k virtual wiphy implementation as we have
-         * no way of tying a vif to wiphy. Typically vifs are attached to
-         * at least one sdata of a wiphy on mac80211 but with ath9k virtual
-         * wiphy you'd have to iterate over every wiphy and each sdata.
-         */
-        sta = ieee80211_find_sta_by_hw(hw, hdr->addr2);
-        if (sta) {
-                an = (struct ath_node *) sta->drv_priv;
-                if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
-                   !rx_stats->rs_moreaggr)
-                        ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
-                last_rssi = an->last_rssi;
+        fc = hdr->frame_control;
+        if (!ieee80211_is_beacon(fc) ||
+            compare_ether_addr(hdr->addr3, common->curbssid)) {
+                /* TODO:  This doesn't work well if you have stations
+                 * associated to two different APs because curbssid
+                 * is just the last AP that any of the stations associated
+                 * with.
+                 */
+                return;
         }
-        rcu_read_unlock();
 
+        if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
+                ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
+
+        last_rssi = sc->last_rssi;
         if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
                 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
                                               ATH_RSSI_EP_MULTIPLIER);
@@ -983,8 +970,7 @@ static void ath9k_process_rssi(struct ath_common *common,
                 rx_stats->rs_rssi = 0;
 
         /* Update Beacon RSSI, this is used by ANI. */
-        if (ieee80211_is_beacon(fc))
-                ah->stats.avgbrssi = rx_stats->rs_rssi;
+        ah->stats.avgbrssi = rx_stats->rs_rssi;
 }
 
 /*
@@ -1008,6 +994,10 @@ static int ath9k_rx_skb_preprocess(struct ath_common *common,
         if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
                 return -EINVAL;
 
+        /* Only use status info from the last fragment */
+        if (rx_stats->rs_more)
+                return 0;
+
         ath9k_process_rssi(common, hw, hdr, rx_stats);
 
         if (ath9k_process_rate(common, hw, rx_stats, rx_status))
@@ -1017,7 +1007,7 @@ static int ath9k_rx_skb_preprocess(struct ath_common *common,
         rx_status->freq = hw->conf.channel->center_freq;
         rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
         rx_status->antenna = rx_stats->rs_antenna;
-        rx_status->flag |= RX_FLAG_TSFT;
+        rx_status->flag |= RX_FLAG_MACTIME_MPDU;
 
         return 0;
 }
@@ -1073,19 +1063,641 @@ static void ath9k_rx_skb_postprocess(struct ath_common *common,
                 rxs->flag &= ~RX_FLAG_DECRYPTED;
 }
 
+static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
+                                      struct ath_hw_antcomb_conf ant_conf,
+                                      int main_rssi_avg)
+{
+        antcomb->quick_scan_cnt = 0;
+
+        if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
+                antcomb->rssi_lna2 = main_rssi_avg;
+        else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
+                antcomb->rssi_lna1 = main_rssi_avg;
+
+        switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
+        case (0x10): /* LNA2 A-B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
+                break;
+        case (0x20): /* LNA1 A-B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
+                break;
+        case (0x21): /* LNA1 LNA2 */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                break;
+        case (0x12): /* LNA2 LNA1 */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                break;
+        case (0x13): /* LNA2 A+B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
+                break;
+        case (0x23): /* LNA1 A+B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
+                                struct ath_hw_antcomb_conf *div_ant_conf,
+                                int main_rssi_avg, int alt_rssi_avg,
+                                int alt_ratio)
+{
+        /* alt_good */
+        switch (antcomb->quick_scan_cnt) {
+        case 0:
+                /* set alt to main, and alt to first conf */
+                div_ant_conf->main_lna_conf = antcomb->main_conf;
+                div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
+                break;
+        case 1:
+                /* set alt to main, and alt to first conf */
+                div_ant_conf->main_lna_conf = antcomb->main_conf;
+                div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
+                antcomb->rssi_first = main_rssi_avg;
+                antcomb->rssi_second = alt_rssi_avg;
+
+                if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
+                        /* main is LNA1 */
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->first_ratio = true;
+                        else
+                                antcomb->first_ratio = false;
+                } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->first_ratio = true;
+                        else
+                                antcomb->first_ratio = false;
+                } else {
+                        if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
+                            (alt_rssi_avg > main_rssi_avg +
+                            ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
+                            (alt_rssi_avg > main_rssi_avg)) &&
+                            (antcomb->total_pkt_count > 50))
+                                antcomb->first_ratio = true;
+                        else
+                                antcomb->first_ratio = false;
+                }
+                break;
+        case 2:
+                antcomb->alt_good = false;
+                antcomb->scan_not_start = false;
+                antcomb->scan = false;
+                antcomb->rssi_first = main_rssi_avg;
+                antcomb->rssi_third = alt_rssi_avg;
+
+                if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
+                        antcomb->rssi_lna1 = alt_rssi_avg;
+                else if (antcomb->second_quick_scan_conf ==
+                         ATH_ANT_DIV_COMB_LNA2)
+                        antcomb->rssi_lna2 = alt_rssi_avg;
+                else if (antcomb->second_quick_scan_conf ==
+                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
+                        if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
+                                antcomb->rssi_lna2 = main_rssi_avg;
+                        else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
+                                antcomb->rssi_lna1 = main_rssi_avg;
+                }
+
+                if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
+                    ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
+                        div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
+                else
+                        div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
+
+                if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->second_ratio = true;
+                        else
+                                antcomb->second_ratio = false;
+                } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->second_ratio = true;
+                        else
+                                antcomb->second_ratio = false;
+                } else {
+                        if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
+                            (alt_rssi_avg > main_rssi_avg +
+                            ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
+                            (alt_rssi_avg > main_rssi_avg)) &&
+                            (antcomb->total_pkt_count > 50))
+                                antcomb->second_ratio = true;
+                        else
+                                antcomb->second_ratio = false;
+                }
+
+                /* set alt to the conf with maximun ratio */
+                if (antcomb->first_ratio && antcomb->second_ratio) {
+                        if (antcomb->rssi_second > antcomb->rssi_third) {
+                                /* first alt*/
+                                if ((antcomb->first_quick_scan_conf ==
+                                    ATH_ANT_DIV_COMB_LNA1) ||
+                                    (antcomb->first_quick_scan_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2))
+                                        /* Set alt LNA1 or LNA2*/
+                                        if (div_ant_conf->main_lna_conf ==
+                                            ATH_ANT_DIV_COMB_LNA2)
+                                                div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA1;
+                                        else
+                                                div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA2;
+                                else
+                                        /* Set alt to A+B or A-B */
+                                        div_ant_conf->alt_lna_conf =
+                                                antcomb->first_quick_scan_conf;
+                        } else if ((antcomb->second_quick_scan_conf ==
+                                   ATH_ANT_DIV_COMB_LNA1) ||
+                                   (antcomb->second_quick_scan_conf ==
+                                   ATH_ANT_DIV_COMB_LNA2)) {
+                                /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        } else {
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf =
+                                        antcomb->second_quick_scan_conf;
+                        }
+                } else if (antcomb->first_ratio) {
+                        /* first alt */
+                        if ((antcomb->first_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA1) ||
+                            (antcomb->first_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA2))
+                                        /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA2;
+                        else
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf =
+                                                antcomb->first_quick_scan_conf;
+                } else if (antcomb->second_ratio) {
+                                /* second alt */
+                        if ((antcomb->second_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA1) ||
+                            (antcomb->second_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA2))
+                                /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        else
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf =
+                                                antcomb->second_quick_scan_conf;
+                } else {
+                        /* main is largest */
+                        if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
+                            (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
+                                /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA2;
+                        else
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf = antcomb->main_conf;
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
+                struct ath_ant_comb *antcomb, int alt_ratio)
+{
+        if (ant_conf->div_group == 0) {
+                /* Adjust the fast_div_bias based on main and alt lna conf */
+                switch ((ant_conf->main_lna_conf << 4) |
+                                ant_conf->alt_lna_conf) {
+                case (0x01): /* A-B LNA2 */
+                        ant_conf->fast_div_bias = 0x3b;
+                        break;
+                case (0x02): /* A-B LNA1 */
+                        ant_conf->fast_div_bias = 0x3d;
+                        break;
+                case (0x03): /* A-B A+B */
+                        ant_conf->fast_div_bias = 0x1;
+                        break;
+                case (0x10): /* LNA2 A-B */
+                        ant_conf->fast_div_bias = 0x7;
+                        break;
+                case (0x12): /* LNA2 LNA1 */
+                        ant_conf->fast_div_bias = 0x2;
+                        break;
+                case (0x13): /* LNA2 A+B */
+                        ant_conf->fast_div_bias = 0x7;
+                        break;
+                case (0x20): /* LNA1 A-B */
+                        ant_conf->fast_div_bias = 0x6;
+                        break;
+                case (0x21): /* LNA1 LNA2 */
+                        ant_conf->fast_div_bias = 0x0;
+                        break;
+                case (0x23): /* LNA1 A+B */
+                        ant_conf->fast_div_bias = 0x6;
+                        break;
+                case (0x30): /* A+B A-B */
+                        ant_conf->fast_div_bias = 0x1;
+                        break;
+                case (0x31): /* A+B LNA2 */
+                        ant_conf->fast_div_bias = 0x3b;
+                        break;
+                case (0x32): /* A+B LNA1 */
+                        ant_conf->fast_div_bias = 0x3d;
+                        break;
+                default:
+                        break;
+                }
+        } else if (ant_conf->div_group == 2) {
+                /* Adjust the fast_div_bias based on main and alt_lna_conf */
+                switch ((ant_conf->main_lna_conf << 4) |
+                                ant_conf->alt_lna_conf) {
+                case (0x01): /* A-B LNA2 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x02): /* A-B LNA1 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x03): /* A-B A+B */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x10): /* LNA2 A-B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x12): /* LNA2 LNA1 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x13): /* LNA2 A+B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x20): /* LNA1 A-B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x21): /* LNA1 LNA2 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x23): /* LNA1 A+B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x30): /* A+B A-B */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x31): /* A+B LNA2 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x32): /* A+B LNA1 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                default:
+                        break;
+                }
+
+        }
+
+}
+
+/* Antenna diversity and combining */
+static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
+{
+        struct ath_hw_antcomb_conf div_ant_conf;
+        struct ath_ant_comb *antcomb = &sc->ant_comb;
+        int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
+        int curr_main_set;
+        int main_rssi = rs->rs_rssi_ctl0;
+        int alt_rssi = rs->rs_rssi_ctl1;
+        int rx_ant_conf,  main_ant_conf;
+        bool short_scan = false;
+
+        rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
+                       ATH_ANT_RX_MASK;
+        main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
+                         ATH_ANT_RX_MASK;
+
+        /* Record packet only when both main_rssi and  alt_rssi is positive */
+        if (main_rssi > 0 && alt_rssi > 0) {
+                antcomb->total_pkt_count++;
+                antcomb->main_total_rssi += main_rssi;
+                antcomb->alt_total_rssi  += alt_rssi;
+                if (main_ant_conf == rx_ant_conf)
+                        antcomb->main_recv_cnt++;
+                else
+                        antcomb->alt_recv_cnt++;
+        }
+
+        /* Short scan check */
+        if (antcomb->scan && antcomb->alt_good) {
+                if (time_after(jiffies, antcomb->scan_start_time +
+                    msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
+                        short_scan = true;
+                else
+                        if (antcomb->total_pkt_count ==
+                            ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
+                                alt_ratio = ((antcomb->alt_recv_cnt * 100) /
+                                            antcomb->total_pkt_count);
+                                if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
+                                        short_scan = true;
+                        }
+        }
+
+        if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
+            rs->rs_moreaggr) && !short_scan)
+                return;
+
+        if (antcomb->total_pkt_count) {
+                alt_ratio = ((antcomb->alt_recv_cnt * 100) /
+                             antcomb->total_pkt_count);
+                main_rssi_avg = (antcomb->main_total_rssi /
+                                 antcomb->total_pkt_count);
+                alt_rssi_avg = (antcomb->alt_total_rssi /
+                                 antcomb->total_pkt_count);
+        }
+
+
+        ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
+        curr_alt_set = div_ant_conf.alt_lna_conf;
+        curr_main_set = div_ant_conf.main_lna_conf;
+
+        antcomb->count++;
+
+        if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
+                if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
+                        ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
+                                                  main_rssi_avg);
+                        antcomb->alt_good = true;
+                } else {
+                        antcomb->alt_good = false;
+                }
+
+                antcomb->count = 0;
+                antcomb->scan = true;
+                antcomb->scan_not_start = true;
+        }
+
+        if (!antcomb->scan) {
+                if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
+                                        alt_ratio, curr_main_set, curr_alt_set,
+                                        alt_rssi_avg, main_rssi_avg)) {
+                        if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
+                                /* Switch main and alt LNA */
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                        } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        }
+
+                        goto div_comb_done;
+                } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
+                           (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
+                        /* Set alt to another LNA */
+                        if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                        else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+
+                        goto div_comb_done;
+                }
+
+                if ((alt_rssi_avg < (main_rssi_avg +
+                                                div_ant_conf.lna1_lna2_delta)))
+                        goto div_comb_done;
+        }
+
+        if (!antcomb->scan_not_start) {
+                switch (curr_alt_set) {
+                case ATH_ANT_DIV_COMB_LNA2:
+                        antcomb->rssi_lna2 = alt_rssi_avg;
+                        antcomb->rssi_lna1 = main_rssi_avg;
+                        antcomb->scan = true;
+                        /* set to A+B */
+                        div_ant_conf.main_lna_conf =
+                                ATH_ANT_DIV_COMB_LNA1;
+                        div_ant_conf.alt_lna_conf  =
+                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                        break;
+                case ATH_ANT_DIV_COMB_LNA1:
+                        antcomb->rssi_lna1 = alt_rssi_avg;
+                        antcomb->rssi_lna2 = main_rssi_avg;
+                        antcomb->scan = true;
+                        /* set to A+B */
+                        div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
+                        div_ant_conf.alt_lna_conf  =
+                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                        break;
+                case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
+                        antcomb->rssi_add = alt_rssi_avg;
+                        antcomb->scan = true;
+                        /* set to A-B */
+                        div_ant_conf.alt_lna_conf =
+                                ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                        break;
+                case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
+                        antcomb->rssi_sub = alt_rssi_avg;
+                        antcomb->scan = false;
+                        if (antcomb->rssi_lna2 >
+                            (antcomb->rssi_lna1 +
+                            ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
+                                /* use LNA2 as main LNA */
+                                if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
+                                    (antcomb->rssi_add > antcomb->rssi_sub)) {
+                                        /* set to A+B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                        div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                                } else if (antcomb->rssi_sub >
+                                           antcomb->rssi_lna1) {
+                                        /* set to A-B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                                } else {
+                                        /* set to LNA1 */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                }
+                        } else {
+                                /* use LNA1 as main LNA */
+                                if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
+                                    (antcomb->rssi_add > antcomb->rssi_sub)) {
+                                        /* set to A+B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                        div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                                } else if (antcomb->rssi_sub >
+                                           antcomb->rssi_lna1) {
+                                        /* set to A-B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                                } else {
+                                        /* set to LNA2 */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                }
+                        }
+                        break;
+                default:
+                        break;
+                }
+        } else {
+                if (!antcomb->alt_good) {
+                        antcomb->scan_not_start = false;
+                        /* Set alt to another LNA */
+                        if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                        } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        }
+                        goto div_comb_done;
+                }
+        }
+
+        ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
+                                           main_rssi_avg, alt_rssi_avg,
+                                           alt_ratio);
+
+        antcomb->quick_scan_cnt++;
+
+div_comb_done:
+        ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
+        ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
+
+        antcomb->scan_start_time = jiffies;
+        antcomb->total_pkt_count = 0;
+        antcomb->main_total_rssi = 0;
+        antcomb->alt_total_rssi = 0;
+        antcomb->main_recv_cnt = 0;
+        antcomb->alt_recv_cnt = 0;
+}
+
 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
 {
         struct ath_buf *bf;
-        struct sk_buff *skb = NULL, *requeue_skb;
+        struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
         struct ieee80211_rx_status *rxs;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         /*
-         * The hw can techncically differ from common->hw when using ath9k
+         * The hw can technically differ from common->hw when using ath9k
          * virtual wiphy so to account for that we iterate over the active
          * wiphys and find the appropriate wiphy and therefore hw.
          */
-        struct ieee80211_hw *hw = NULL;
+        struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_hdr *hdr;
         int retval;
         bool decrypt_error = false;
@@ -1096,6 +1708,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
         u8 rx_status_len = ah->caps.rx_status_len;
         u64 tsf = 0;
         u32 tsf_lower = 0;
+        unsigned long flags;
 
         if (edma)
                 dma_type = DMA_BIDIRECTIONAL;
@@ -1126,10 +1739,17 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 if (!skb)
                         continue;
 
-                hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
-                rxs =  IEEE80211_SKB_RXCB(skb);
+                /*
+                 * Take frame header from the first fragment and RX status from
+                 * the last one.
+                 */
+                if (sc->rx.frag)
+                        hdr_skb = sc->rx.frag;
+                else
+                        hdr_skb = skb;
 
-                hw = ath_get_virt_hw(sc, hdr);
+                hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
+                rxs = IEEE80211_SKB_RXCB(hdr_skb);
 
                 ath_debug_stat_rx(sc, &rs);
 
@@ -1138,12 +1758,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                  * chain it back at the queue without processing it.
                  */
                 if (flush)
-                        goto requeue;
+                        goto requeue_drop_frag;
 
                 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
                                                  rxs, &decrypt_error);
                 if (retval)
-                        goto requeue;
+                        goto requeue_drop_frag;
 
                 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
                 if (rs.rs_tstamp > tsf_lower &&
@@ -1163,7 +1783,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                  * skb and put it at the tail of the sc->rx.rxbuf list for
                  * processing. */
                 if (!requeue_skb)
-                        goto requeue;
+                        goto requeue_drop_frag;
 
                 /* Unmap the frame */
                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
@@ -1174,8 +1794,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 if (ah->caps.rx_status_len)
                         skb_pull(skb, ah->caps.rx_status_len);
 
-                ath9k_rx_skb_postprocess(common, skb, &rs,
-                                         rxs, decrypt_error);
+                if (!rs.rs_more)
+                        ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
+                                                 rxs, decrypt_error);
 
                 /* We will now give hardware our shiny new allocated skb */
                 bf->bf_mpdu = requeue_skb;
@@ -1186,12 +1807,43 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                           bf->bf_buf_addr))) {
                         dev_kfree_skb_any(requeue_skb);
                         bf->bf_mpdu = NULL;
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "dma_mapping_error() on RX\n");
-                        ath_rx_send_to_mac80211(hw, sc, skb, rxs);
+                        bf->bf_buf_addr = 0;
+                        ath_err(common, "dma_mapping_error() on RX\n");
+                        ieee80211_rx(hw, skb);
                         break;
                 }
-                bf->bf_dmacontext = bf->bf_buf_addr;
+
+                if (rs.rs_more) {
+                        /*
+                         * rs_more indicates chained descriptors which can be
+                         * used to link buffers together for a sort of
+                         * scatter-gather operation.
+                         */
+                        if (sc->rx.frag) {
+                                /* too many fragments - cannot handle frame */
+                                dev_kfree_skb_any(sc->rx.frag);
+                                dev_kfree_skb_any(skb);
+                                skb = NULL;
+                        }
+                        sc->rx.frag = skb;
+                        goto requeue;
+                }
+
+                if (sc->rx.frag) {
+                        int space = skb->len - skb_tailroom(hdr_skb);
+
+                        sc->rx.frag = NULL;
+
+                        if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
+                                dev_kfree_skb(skb);
+                                goto requeue_drop_frag;
+                        }
+
+                        skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
+                                                  skb->len);
+                        dev_kfree_skb_any(skb);
+                        skb = hdr_skb;
+                }
 
                 /*
                  * change the default rx antenna if rx diversity chooses the
@@ -1204,14 +1856,25 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                         sc->rx.rxotherant = 0;
                 }
 
-                if (unlikely(ath9k_check_auto_sleep(sc) ||
-                             (sc->ps_flags & (PS_WAIT_FOR_BEACON |
+                spin_lock_irqsave(&sc->sc_pm_lock, flags);
+
+                if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                               PS_WAIT_FOR_CAB |
-                                              PS_WAIT_FOR_PSPOLL_DATA))))
+                                              PS_WAIT_FOR_PSPOLL_DATA)) ||
+                                                ath9k_check_auto_sleep(sc))
                         ath_rx_ps(sc, skb);
+                spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 
-                ath_rx_send_to_mac80211(hw, sc, skb, rxs);
+                if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
+                        ath_ant_comb_scan(sc, &rs);
 
+                ieee80211_rx(hw, skb);
+
+requeue_drop_frag:
+                if (sc->rx.frag) {
+                        dev_kfree_skb_any(sc->rx.frag);
+                        sc->rx.frag = NULL;
+                }
 requeue:
                 if (edma) {
                         list_add_tail(&bf->list, &sc->rx.rxbuf);
@@ -1219,6 +1882,7 @@ requeue:
                 } else {
                         list_move_tail(&bf->list, &sc->rx.rxbuf);
                         ath_rx_buf_link(sc, bf);
+                        ath9k_hw_rxena(ah);
                 }
         } while (1);
 
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index d01c4adab8d6..c18ee9921fb1 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -107,12 +107,6 @@
 #define AR_RXCFG_DMASZ_256B  6
 #define AR_RXCFG_DMASZ_512B  7
 
-#define AR_MIBC              0x0040
-#define AR_MIBC_COW          0x00000001
-#define AR_MIBC_FMC          0x00000002
-#define AR_MIBC_CMC          0x00000004
-#define AR_MIBC_MCS          0x00000008
-
 #define AR_TOPS              0x0044
 #define AR_TOPS_MASK         0x0000FFFF
 
@@ -699,7 +693,7 @@
 #define AR_RC_APB            0x00000002
 #define AR_RC_HOSTIF         0x00000100
 
-#define AR_WA                           0x4004
+#define AR_WA                   (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
 #define AR_WA_BIT6                      (1 << 6)
 #define AR_WA_BIT7                      (1 << 7)
 #define AR_WA_BIT23                     (1 << 23)
@@ -709,6 +703,7 @@
 #define AR_WA_RESET_EN                  (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
 #define AR_WA_ANALOG_SHIFT              (1 << 20)
 #define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
+#define AR_WA_BIT22                     (1 << 22)
 #define AR9285_WA_DEFAULT               0x004a050b
 #define AR9280_WA_DEFAULT               0x0040073b
 #define AR_WA_DEFAULT                   0x0000073f
@@ -717,7 +712,7 @@
 #define AR_PM_STATE                 0x4008
 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
 
-#define AR_HOST_TIMEOUT             0x4018
+#define AR_HOST_TIMEOUT             (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
 #define AR_HOST_TIMEOUT_APB_CNTR    0x0000FFFF
 #define AR_HOST_TIMEOUT_APB_CNTR_S  0
 #define AR_HOST_TIMEOUT_LCL_CNTR    0xFFFF0000
@@ -747,7 +742,8 @@
 #define EEPROM_PROTECT_WP_1024_2047   0x8000
 
 #define AR_SREV \
-        ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020)
+        ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
+                                        ? 0x400c : 0x4020))
 
 #define AR_SREV_ID \
         ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
@@ -792,6 +788,10 @@
 #define AR_SREV_REVISION_9271_11        1
 #define AR_SREV_VERSION_9300            0x1c0
 #define AR_SREV_REVISION_9300_20        2 /* 2.0 and 2.1 */
+#define AR_SREV_VERSION_9485            0x240
+#define AR_SREV_REVISION_9485_10        0
+#define AR_SREV_REVISION_9485_11        1
+#define AR_SREV_VERSION_9340            0x300
 
 #define AR_SREV_5416(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -819,49 +819,23 @@
          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
 #define AR_SREV_9280(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
-#define AR_SREV_9280_10_OR_LATER(_ah) \
+#define AR_SREV_9280_20_OR_LATER(_ah) \
         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
 #define AR_SREV_9280_20(_ah) \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
-                ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))
-#define AR_SREV_9280_20_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
-        ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)))
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
 
 #define AR_SREV_9285(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
-#define AR_SREV_9285_10_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
-#define AR_SREV_9285_11(_ah) \
-        (AR_SREV_9285(ah) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11))
-#define AR_SREV_9285_11_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
-         (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
-                               AR_SREV_REVISION_9285_11)))
-#define AR_SREV_9285_12(_ah) \
-        (AR_SREV_9285(ah) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12))
 #define AR_SREV_9285_12_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
-         (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
-                               AR_SREV_REVISION_9285_12)))
+        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
 
 #define AR_SREV_9287(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
-#define AR_SREV_9287_10_OR_LATER(_ah) \
+#define AR_SREV_9287_11_OR_LATER(_ah) \
         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
-#define AR_SREV_9287_10(_ah) \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_10))
 #define AR_SREV_9287_11(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
-#define AR_SREV_9287_11_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
-         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
-          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_11)))
 #define AR_SREV_9287_12(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
@@ -885,22 +859,36 @@
 
 #define AR_SREV_9300(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
-#define AR_SREV_9300_20(_ah) \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
 #define AR_SREV_9300_20_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
-         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
-          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
+        ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
+
+#define AR_SREV_9485(_ah) \
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
+#define AR_SREV_9485_10(_ah) \
+        (AR_SREV_9485(_ah) && \
+         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
+#define AR_SREV_9485_11(_ah) \
+        (AR_SREV_9485(_ah) && \
+         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
+#define AR_SREV_9485_OR_LATER(_ah) \
+        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
+
+#define AR_SREV_9340(_ah) \
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
 
 #define AR_SREV_9285E_20(_ah) \
     (AR_SREV_9285_12_OR_LATER(_ah) && \
      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
 
+enum ath_usb_dev {
+        AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
+        AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
+        STORAGE_DEVICE = 3,
+};
+
 #define AR_DEVID_7010(_ah) \
-        (((_ah)->hw_version.devid == 0x7010) || \
-         ((_ah)->hw_version.devid == 0x7015) || \
-         ((_ah)->hw_version.devid == 0x9018))
+        (((_ah)->hw_version.usbdev == AR9280_USB) || \
+         ((_ah)->hw_version.usbdev == AR9287_USB))
 
 #define AR_RADIO_SREV_MAJOR                   0xf0
 #define AR_RAD5133_SREV_MAJOR                 0xc0
@@ -929,11 +917,11 @@
 #define AR_INTR_SPURIOUS                      0xFFFFFFFF
 
 
-#define AR_INTR_SYNC_CAUSE_CLR                0x4028
+#define AR_INTR_SYNC_CAUSE                    (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
+#define AR_INTR_SYNC_CAUSE_CLR                (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
 
-#define AR_INTR_SYNC_CAUSE                    0x4028
 
-#define AR_INTR_SYNC_ENABLE                   0x402c
+#define AR_INTR_SYNC_ENABLE                   (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
 #define AR_INTR_SYNC_ENABLE_GPIO              0xFFFC0000
 #define AR_INTR_SYNC_ENABLE_GPIO_S            18
 
@@ -973,24 +961,24 @@ enum {
 
 };
 
-#define AR_INTR_ASYNC_MASK                       0x4030
+#define AR_INTR_ASYNC_MASK                       (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
 #define AR_INTR_ASYNC_MASK_GPIO                  0xFFFC0000
 #define AR_INTR_ASYNC_MASK_GPIO_S                18
 
-#define AR_INTR_SYNC_MASK                        0x4034
+#define AR_INTR_SYNC_MASK                        (AR_SREV_9340(ah) ? 0x401c : 0x4034)
 #define AR_INTR_SYNC_MASK_GPIO                   0xFFFC0000
 #define AR_INTR_SYNC_MASK_GPIO_S                 18
 
-#define AR_INTR_ASYNC_CAUSE_CLR                  0x4038
-#define AR_INTR_ASYNC_CAUSE                      0x4038
+#define AR_INTR_ASYNC_CAUSE_CLR                  (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
+#define AR_INTR_ASYNC_CAUSE                      (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
 
-#define AR_INTR_ASYNC_ENABLE                     0x403c
+#define AR_INTR_ASYNC_ENABLE                     (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
 #define AR_INTR_ASYNC_ENABLE_GPIO                0xFFFC0000
 #define AR_INTR_ASYNC_ENABLE_GPIO_S              18
 
 #define AR_PCIE_SERDES                           0x4040
 #define AR_PCIE_SERDES2                          0x4044
-#define AR_PCIE_PM_CTRL                          0x4014
+#define AR_PCIE_PM_CTRL                          (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
 #define AR_PCIE_PM_CTRL_ENA                      0x00080000
 
 #define AR_NUM_GPIO                              14
@@ -1001,7 +989,7 @@ enum {
 #define AR9300_NUM_GPIO                          17
 #define AR7010_NUM_GPIO                          16
 
-#define AR_GPIO_IN_OUT                           0x4048
+#define AR_GPIO_IN_OUT                           (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
 #define AR_GPIO_IN_VAL                           0x0FFFC000
 #define AR_GPIO_IN_VAL_S                         14
 #define AR928X_GPIO_IN_VAL                       0x000FFC00
@@ -1012,12 +1000,15 @@ enum {
 #define AR9287_GPIO_IN_VAL_S                     11
 #define AR9271_GPIO_IN_VAL                       0xFFFF0000
 #define AR9271_GPIO_IN_VAL_S                     16
-#define AR9300_GPIO_IN_VAL                       0x0001FFFF
-#define AR9300_GPIO_IN_VAL_S                     0
 #define AR7010_GPIO_IN_VAL                       0x0000FFFF
 #define AR7010_GPIO_IN_VAL_S                     0
 
-#define AR_GPIO_OE_OUT                           (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
+#define AR_GPIO_IN                               (AR_SREV_9340(ah) ? 0x402c : 0x404c)
+#define AR9300_GPIO_IN_VAL                       0x0001FFFF
+#define AR9300_GPIO_IN_VAL_S                     0
+
+#define AR_GPIO_OE_OUT                           (AR_SREV_9340(ah) ? 0x4030 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
 #define AR_GPIO_OE_OUT_DRV                       0x3
 #define AR_GPIO_OE_OUT_DRV_NO                    0x0
 #define AR_GPIO_OE_OUT_DRV_LOW                   0x1
@@ -1039,11 +1030,13 @@ enum {
 #define AR7010_GPIO_INT_MASK                     0x52024
 #define AR7010_GPIO_FUNCTION                     0x52028
 
-#define AR_GPIO_INTR_POL                         (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
+#define AR_GPIO_INTR_POL                         (AR_SREV_9340(ah) ? 0x4038 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
 #define AR_GPIO_INTR_POL_VAL                     0x0001FFFF
 #define AR_GPIO_INTR_POL_VAL_S                   0
 
-#define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
+#define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9340(ah) ? 0x403c : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF     0x00000004
 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S       2
 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF    0x00000008
@@ -1061,13 +1054,15 @@ enum {
 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE        0x00010000
 #define AR_GPIO_JTAG_DISABLE                     0x00020000
 
-#define AR_GPIO_INPUT_MUX1                       (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
+#define AR_GPIO_INPUT_MUX1                       (AR_SREV_9340(ah) ? 0x4040 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE             0x000f0000
 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S           16
 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY           0x00000f00
 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S         8
 
-#define AR_GPIO_INPUT_MUX2                       (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
+#define AR_GPIO_INPUT_MUX2                       (AR_SREV_9340(ah) ? 0x4044 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
 #define AR_GPIO_INPUT_MUX2_CLK25                 0x0000000f
 #define AR_GPIO_INPUT_MUX2_CLK25_S               0
 #define AR_GPIO_INPUT_MUX2_RFSILENT              0x000000f0
@@ -1075,13 +1070,18 @@ enum {
 #define AR_GPIO_INPUT_MUX2_RTC_RESET             0x00000f00
 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S           8
 
-#define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
-#define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
-#define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
+#define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9340(ah) ? 0x4048 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
+#define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9340(ah) ? 0x404c : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
+#define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9340(ah) ? 0x4050 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
 
-#define AR_INPUT_STATE                           (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
+#define AR_INPUT_STATE                           (AR_SREV_9340(ah) ? 0x4054 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
 
-#define AR_EEPROM_STATUS_DATA                    (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
+#define AR_EEPROM_STATUS_DATA                    (AR_SREV_9340(ah) ? 0x40c8 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
 #define AR_EEPROM_STATUS_DATA_VAL                0x0000ffff
 #define AR_EEPROM_STATUS_DATA_VAL_S              0
 #define AR_EEPROM_STATUS_DATA_BUSY               0x00010000
@@ -1089,17 +1089,54 @@ enum {
 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS        0x00040000
 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS      0x00080000
 
-#define AR_OBS                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
+#define AR_OBS                  (AR_SREV_9340(ah) ? 0x405c : \
+                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
 
 #define AR_GPIO_PDPU                             (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
 
-#define AR_PCIE_MSI                              (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
+#define AR_PCIE_MSI                             (AR_SREV_9340(ah) ? 0x40d8 : \
+                                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
 #define AR_PCIE_MSI_ENABLE                       0x00000001
 
-#define AR_INTR_PRIO_SYNC_ENABLE  0x40c4
-#define AR_INTR_PRIO_ASYNC_MASK   0x40c8
-#define AR_INTR_PRIO_SYNC_MASK    0x40cc
-#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
+#define AR_INTR_PRIO_SYNC_ENABLE  (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
+#define AR_INTR_PRIO_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
+#define AR_INTR_PRIO_SYNC_MASK    (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
+#define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
+#define AR_ENT_OTP                0x40d8
+#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
+#define AR_ENT_OTP_MPSD         0x00800000
+
+#define AR_CH0_BB_DPLL1          0x16180
+#define AR_CH0_BB_DPLL1_REFDIV   0xF8000000
+#define AR_CH0_BB_DPLL1_REFDIV_S 27
+#define AR_CH0_BB_DPLL1_NINI     0x07FC0000
+#define AR_CH0_BB_DPLL1_NINI_S   18
+#define AR_CH0_BB_DPLL1_NFRAC    0x0003FFFF
+#define AR_CH0_BB_DPLL1_NFRAC_S  0
+
+#define AR_CH0_BB_DPLL2              0x16184
+#define AR_CH0_BB_DPLL2_LOCAL_PLL       0x40000000
+#define AR_CH0_BB_DPLL2_LOCAL_PLL_S     30
+#define AR_CH0_DPLL2_KI              0x3C000000
+#define AR_CH0_DPLL2_KI_S            26
+#define AR_CH0_DPLL2_KD              0x03F80000
+#define AR_CH0_DPLL2_KD_S            19
+#define AR_CH0_BB_DPLL2_EN_NEGTRIG   0x00040000
+#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
+#define AR_CH0_BB_DPLL2_PLL_PWD      0x00010000
+#define AR_CH0_BB_DPLL2_PLL_PWD_S    16
+#define AR_CH0_BB_DPLL2_OUTDIV       0x0000E000
+#define AR_CH0_BB_DPLL2_OUTDIV_S     13
+
+#define AR_CH0_BB_DPLL3          0x16188
+#define AR_CH0_BB_DPLL3_PHASE_SHIFT     0x3F800000
+#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S   23
+
+#define AR_CH0_DDR_DPLL2         0x16244
+#define AR_CH0_DDR_DPLL3         0x16248
+#define AR_CH0_DPLL3_PHASE_SHIFT     0x3F800000
+#define AR_CH0_DPLL3_PHASE_SHIFT_S   23
+#define AR_PHY_CCA_NOM_VAL_2GHZ      -118
 
 #define AR_RTC_9300_PLL_DIV          0x000003ff
 #define AR_RTC_9300_PLL_DIV_S        0
@@ -1137,12 +1174,21 @@ enum {
 #define AR_RTC_PLL_CONTROL \
         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
 
+#define AR_RTC_PLL_CONTROL2     0x703c
+
 #define AR_RTC_PLL_DIV          0x0000001f
 #define AR_RTC_PLL_DIV_S        0
 #define AR_RTC_PLL_DIV2         0x00000020
 #define AR_RTC_PLL_REFDIV_5     0x000000c0
 #define AR_RTC_PLL_CLKSEL       0x00000300
 #define AR_RTC_PLL_CLKSEL_S     8
+#define AR_RTC_PLL_BYPASS       0x00010000
+
+#define PLL3 0x16188
+#define PLL3_DO_MEAS_MASK 0x40000000
+#define PLL4 0x1618c
+#define PLL4_MEAS_DONE    0x8
+#define SQSUM_DVC_MASK 0x007ffff8
 
 #define AR_RTC_RESET \
         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
@@ -1183,7 +1229,8 @@ enum {
 
 /* RTC_DERIVED_* - only for AR9100 */
 
-#define AR_RTC_DERIVED_CLK           (AR_RTC_BASE + 0x0038)
+#define AR_RTC_DERIVED_CLK \
+        (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
 #define AR_RTC_DERIVED_CLK_PERIOD    0x0000fffe
 #define AR_RTC_DERIVED_CLK_PERIOD_S  1
 
@@ -1389,6 +1436,7 @@ enum {
 #define AR_STA_ID1_PCF             0x00100000
 #define AR_STA_ID1_USE_DEFANT      0x00200000
 #define AR_STA_ID1_DEFANT_UPDATE   0x00400000
+#define AR_STA_ID1_AR9100_BA_FIX   0x00400000
 #define AR_STA_ID1_RTS_USE_DEF     0x00800000
 #define AR_STA_ID1_ACKCTS_6MB      0x01000000
 #define AR_STA_ID1_BASE_RATE_11B   0x02000000
@@ -1550,11 +1598,6 @@ enum {
 #define AR_TPC_CHIRP           0x003f0000
 #define AR_TPC_CHIRP_S         0x16
 
-#define AR_TFCNT           0x80ec
-#define AR_RFCNT           0x80f0
-#define AR_RCCNT           0x80f4
-#define AR_CCCNT           0x80f8
-
 #define AR_QUIET1          0x80fc
 #define AR_QUIET1_NEXT_QUIET_S         0
 #define AR_QUIET1_NEXT_QUIET_M         0x0000ffff
@@ -1605,6 +1648,7 @@ enum {
 #define AR_PCU_TBTT_PROTECT        0x00200000
 #define AR_PCU_CLEAR_VMF           0x01000000
 #define AR_PCU_CLEAR_BA_VALID      0x04000000
+#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
 
 #define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
 #define AR_PCU_BT_ANT_PREVENT_RX_S 20
@@ -1665,6 +1709,22 @@ enum {
 #define AR_BTCOEX_WL_WGHT          0xffff0000
 #define AR_BTCOEX_WL_WGHT_S        16
 
+#define AR_BT_COEX_WL_WEIGHTS0     0x8174
+#define AR_BT_COEX_WL_WEIGHTS1     0x81c4
+
+#define AR_BT_COEX_BT_WEIGHTS0     0x83ac
+#define AR_BT_COEX_BT_WEIGHTS1     0x83b0
+#define AR_BT_COEX_BT_WEIGHTS2     0x83b4
+#define AR_BT_COEX_BT_WEIGHTS3     0x83b8
+
+#define AR9300_BT_WGHT                     0xcccc4444
+#define AR9300_STOMP_ALL_WLAN_WGHT0        0xfffffff0
+#define AR9300_STOMP_ALL_WLAN_WGHT1        0xfffffff0
+#define AR9300_STOMP_LOW_WLAN_WGHT0        0x88888880
+#define AR9300_STOMP_LOW_WLAN_WGHT1        0x88888880
+#define AR9300_STOMP_NONE_WLAN_WGHT0       0x00000000
+#define AR9300_STOMP_NONE_WLAN_WGHT1       0x00000000
+
 #define AR_BT_COEX_MODE2           0x817c
 #define AR_BT_BCN_MISS_THRESH      0x000000ff
 #define AR_BT_BCN_MISS_THRESH_S    0
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
deleted file mode 100644
index fd20241f57d8..000000000000
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ /dev/null
@@ -1,752 +0,0 @@
-/*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/slab.h>
-
-#include "ath9k.h"
-
-struct ath9k_vif_iter_data {
-        int count;
-        u8 *addr;
-};
-
-static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
-{
-        struct ath9k_vif_iter_data *iter_data = data;
-        u8 *nbuf;
-
-        nbuf = krealloc(iter_data->addr, (iter_data->count + 1) * ETH_ALEN,
-                        GFP_ATOMIC);
-        if (nbuf == NULL)
-                return;
-
-        memcpy(nbuf + iter_data->count * ETH_ALEN, mac, ETH_ALEN);
-        iter_data->addr = nbuf;
-        iter_data->count++;
-}
-
-void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
-{
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath9k_vif_iter_data iter_data;
-        int i, j;
-        u8 mask[ETH_ALEN];
-
-        /*
-         * Add primary MAC address even if it is not in active use since it
-         * will be configured to the hardware as the starting point and the
-         * BSSID mask will need to be changed if another address is active.
-         */
-        iter_data.addr = kmalloc(ETH_ALEN, GFP_ATOMIC);
-        if (iter_data.addr) {
-                memcpy(iter_data.addr, common->macaddr, ETH_ALEN);
-                iter_data.count = 1;
-        } else
-                iter_data.count = 0;
-
-        /* Get list of all active MAC addresses */
-        spin_lock_bh(&sc->wiphy_lock);
-        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
-                                                   &iter_data);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] == NULL)
-                        continue;
-                ieee80211_iterate_active_interfaces_atomic(
-                        sc->sec_wiphy[i]->hw, ath9k_vif_iter, &iter_data);
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        /* Generate an address mask to cover all active addresses */
-        memset(mask, 0, ETH_ALEN);
-        for (i = 0; i < iter_data.count; i++) {
-                u8 *a1 = iter_data.addr + i * ETH_ALEN;
-                for (j = i + 1; j < iter_data.count; j++) {
-                        u8 *a2 = iter_data.addr + j * ETH_ALEN;
-                        mask[0] |= a1[0] ^ a2[0];
-                        mask[1] |= a1[1] ^ a2[1];
-                        mask[2] |= a1[2] ^ a2[2];
-                        mask[3] |= a1[3] ^ a2[3];
-                        mask[4] |= a1[4] ^ a2[4];
-                        mask[5] |= a1[5] ^ a2[5];
-                }
-        }
-
-        kfree(iter_data.addr);
-
-        /* Invert the mask and configure hardware */
-        common->bssidmask[0] = ~mask[0];
-        common->bssidmask[1] = ~mask[1];
-        common->bssidmask[2] = ~mask[2];
-        common->bssidmask[3] = ~mask[3];
-        common->bssidmask[4] = ~mask[4];
-        common->bssidmask[5] = ~mask[5];
-
-        ath_hw_setbssidmask(common);
-}
-
-int ath9k_wiphy_add(struct ath_softc *sc)
-{
-        int i, error;
-        struct ath_wiphy *aphy;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ieee80211_hw *hw;
-        u8 addr[ETH_ALEN];
-
-        hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy), &ath9k_ops);
-        if (hw == NULL)
-                return -ENOMEM;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] == NULL)
-                        break;
-        }
-
-        if (i == sc->num_sec_wiphy) {
-                /* No empty slot available; increase array length */
-                struct ath_wiphy **n;
-                n = krealloc(sc->sec_wiphy,
-                             (sc->num_sec_wiphy + 1) *
-                             sizeof(struct ath_wiphy *),
-                             GFP_ATOMIC);
-                if (n == NULL) {
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        ieee80211_free_hw(hw);
-                        return -ENOMEM;
-                }
-                n[i] = NULL;
-                sc->sec_wiphy = n;
-                sc->num_sec_wiphy++;
-        }
-
-        SET_IEEE80211_DEV(hw, sc->dev);
-
-        aphy = hw->priv;
-        aphy->sc = sc;
-        aphy->hw = hw;
-        sc->sec_wiphy[i] = aphy;
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        memcpy(addr, common->macaddr, ETH_ALEN);
-        addr[0] |= 0x02; /* Locally managed address */
-        /*
-         * XOR virtual wiphy index into the least significant bits to generate
-         * a different MAC address for each virtual wiphy.
-         */
-        addr[5] ^= i & 0xff;
-        addr[4] ^= (i & 0xff00) >> 8;
-        addr[3] ^= (i & 0xff0000) >> 16;
-
-        SET_IEEE80211_PERM_ADDR(hw, addr);
-
-        ath9k_set_hw_capab(sc, hw);
-
-        error = ieee80211_register_hw(hw);
-
-        if (error == 0) {
-                /* Make sure wiphy scheduler is started (if enabled) */
-                ath9k_wiphy_set_scheduler(sc, sc->wiphy_scheduler_int);
-        }
-
-        return error;
-}
-
-int ath9k_wiphy_del(struct ath_wiphy *aphy)
-{
-        struct ath_softc *sc = aphy->sc;
-        int i;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (aphy == sc->sec_wiphy[i]) {
-                        sc->sec_wiphy[i] = NULL;
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        ieee80211_unregister_hw(aphy->hw);
-                        ieee80211_free_hw(aphy->hw);
-                        return 0;
-                }
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-        return -ENOENT;
-}
-
-static int ath9k_send_nullfunc(struct ath_wiphy *aphy,
-                               struct ieee80211_vif *vif, const u8 *bssid,
-                               int ps)
-{
-        struct ath_softc *sc = aphy->sc;
-        struct ath_tx_control txctl;
-        struct sk_buff *skb;
-        struct ieee80211_hdr *hdr;
-        __le16 fc;
-        struct ieee80211_tx_info *info;
-
-        skb = dev_alloc_skb(24);
-        if (skb == NULL)
-                return -ENOMEM;
-        hdr = (struct ieee80211_hdr *) skb_put(skb, 24);
-        memset(hdr, 0, 24);
-        fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC |
-                         IEEE80211_FCTL_TODS);
-        if (ps)
-                fc |= cpu_to_le16(IEEE80211_FCTL_PM);
-        hdr->frame_control = fc;
-        memcpy(hdr->addr1, bssid, ETH_ALEN);
-        memcpy(hdr->addr2, aphy->hw->wiphy->perm_addr, ETH_ALEN);
-        memcpy(hdr->addr3, bssid, ETH_ALEN);
-
-        info = IEEE80211_SKB_CB(skb);
-        memset(info, 0, sizeof(*info));
-        info->flags = IEEE80211_TX_CTL_REQ_TX_STATUS;
-        info->control.vif = vif;
-        info->control.rates[0].idx = 0;
-        info->control.rates[0].count = 4;
-        info->control.rates[1].idx = -1;
-
-        memset(&txctl, 0, sizeof(struct ath_tx_control));
-        txctl.txq = &sc->tx.txq[sc->tx.hwq_map[WME_AC_VO]];
-        txctl.frame_type = ps ? ATH9K_IFT_PAUSE : ATH9K_IFT_UNPAUSE;
-
-        if (ath_tx_start(aphy->hw, skb, &txctl) != 0)
-                goto exit;
-
-        return 0;
-exit:
-        dev_kfree_skb_any(skb);
-        return -1;
-}
-
-static bool __ath9k_wiphy_pausing(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state == ATH_WIPHY_PAUSING)
-                return true;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_PAUSING)
-                        return true;
-        }
-        return false;
-}
-
-static bool ath9k_wiphy_pausing(struct ath_softc *sc)
-{
-        bool ret;
-        spin_lock_bh(&sc->wiphy_lock);
-        ret = __ath9k_wiphy_pausing(sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-        return ret;
-}
-
-static bool __ath9k_wiphy_scanning(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state == ATH_WIPHY_SCAN)
-                return true;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_SCAN)
-                        return true;
-        }
-        return false;
-}
-
-bool ath9k_wiphy_scanning(struct ath_softc *sc)
-{
-        bool ret;
-        spin_lock_bh(&sc->wiphy_lock);
-        ret = __ath9k_wiphy_scanning(sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-        return ret;
-}
-
-static int __ath9k_wiphy_unpause(struct ath_wiphy *aphy);
-
-/* caller must hold wiphy_lock */
-static void __ath9k_wiphy_unpause_ch(struct ath_wiphy *aphy)
-{
-        if (aphy == NULL)
-                return;
-        if (aphy->chan_idx != aphy->sc->chan_idx)
-                return; /* wiphy not on the selected channel */
-        __ath9k_wiphy_unpause(aphy);
-}
-
-static void ath9k_wiphy_unpause_channel(struct ath_softc *sc)
-{
-        int i;
-        spin_lock_bh(&sc->wiphy_lock);
-        __ath9k_wiphy_unpause_ch(sc->pri_wiphy);
-        for (i = 0; i < sc->num_sec_wiphy; i++)
-                __ath9k_wiphy_unpause_ch(sc->sec_wiphy[i]);
-        spin_unlock_bh(&sc->wiphy_lock);
-}
-
-void ath9k_wiphy_chan_work(struct work_struct *work)
-{
-        struct ath_softc *sc = container_of(work, struct ath_softc, chan_work);
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_wiphy *aphy = sc->next_wiphy;
-
-        if (aphy == NULL)
-                return;
-
-        /*
-         * All pending interfaces paused; ready to change
-         * channels.
-         */
-
-        /* Change channels */
-        mutex_lock(&sc->mutex);
-        /* XXX: remove me eventually */
-        ath9k_update_ichannel(sc, aphy->hw,
-                              &sc->sc_ah->channels[sc->chan_idx]);
-
-        /* sync hw configuration for hw code */
-        common->hw = aphy->hw;
-
-        ath_update_chainmask(sc, sc->chan_is_ht);
-        if (ath_set_channel(sc, aphy->hw,
-                            &sc->sc_ah->channels[sc->chan_idx]) < 0) {
-                printk(KERN_DEBUG "ath9k: Failed to set channel for new "
-                       "virtual wiphy\n");
-                mutex_unlock(&sc->mutex);
-                return;
-        }
-        mutex_unlock(&sc->mutex);
-
-        ath9k_wiphy_unpause_channel(sc);
-}
-
-/*
- * ath9k version of ieee80211_tx_status() for TX frames that are generated
- * internally in the driver.
- */
-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
-        struct ath_wiphy *aphy = hw->priv;
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-
-        if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
-            aphy->state == ATH_WIPHY_PAUSING) {
-                if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
-                        printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
-                               "frame\n", wiphy_name(hw->wiphy));
-                        /*
-                         * The AP did not reply; ignore this to allow us to
-                         * continue.
-                         */
-                }
-                aphy->state = ATH_WIPHY_PAUSED;
-                if (!ath9k_wiphy_pausing(aphy->sc)) {
-                        /*
-                         * Drop from tasklet to work to allow mutex for channel
-                         * change.
-                         */
-                        ieee80211_queue_work(aphy->sc->hw,
-                                   &aphy->sc->chan_work);
-                }
-        }
-
-        dev_kfree_skb(skb);
-}
-
-static void ath9k_mark_paused(struct ath_wiphy *aphy)
-{
-        struct ath_softc *sc = aphy->sc;
-        aphy->state = ATH_WIPHY_PAUSED;
-        if (!__ath9k_wiphy_pausing(sc))
-                ieee80211_queue_work(sc->hw, &sc->chan_work);
-}
-
-static void ath9k_pause_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
-{
-        struct ath_wiphy *aphy = data;
-        struct ath_vif *avp = (void *) vif->drv_priv;
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_STATION:
-                if (!vif->bss_conf.assoc) {
-                        ath9k_mark_paused(aphy);
-                        break;
-                }
-                /* TODO: could avoid this if already in PS mode */
-                if (ath9k_send_nullfunc(aphy, vif, avp->bssid, 1)) {
-                        printk(KERN_DEBUG "%s: failed to send PS nullfunc\n",
-                               __func__);
-                        ath9k_mark_paused(aphy);
-                }
-                break;
-        case NL80211_IFTYPE_AP:
-                /* Beacon transmission is paused by aphy->state change */
-                ath9k_mark_paused(aphy);
-                break;
-        default:
-                break;
-        }
-}
-
-/* caller must hold wiphy_lock */
-static int __ath9k_wiphy_pause(struct ath_wiphy *aphy)
-{
-        ieee80211_stop_queues(aphy->hw);
-        aphy->state = ATH_WIPHY_PAUSING;
-        /*
-         * TODO: handle PAUSING->PAUSED for the case where there are multiple
-         * active vifs (now we do it on the first vif getting ready; should be
-         * on the last)
-         */
-        ieee80211_iterate_active_interfaces_atomic(aphy->hw, ath9k_pause_iter,
-                                                   aphy);
-        return 0;
-}
-
-int ath9k_wiphy_pause(struct ath_wiphy *aphy)
-{
-        int ret;
-        spin_lock_bh(&aphy->sc->wiphy_lock);
-        ret = __ath9k_wiphy_pause(aphy);
-        spin_unlock_bh(&aphy->sc->wiphy_lock);
-        return ret;
-}
-
-static void ath9k_unpause_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
-{
-        struct ath_wiphy *aphy = data;
-        struct ath_vif *avp = (void *) vif->drv_priv;
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_STATION:
-                if (!vif->bss_conf.assoc)
-                        break;
-                ath9k_send_nullfunc(aphy, vif, avp->bssid, 0);
-                break;
-        case NL80211_IFTYPE_AP:
-                /* Beacon transmission is re-enabled by aphy->state change */
-                break;
-        default:
-                break;
-        }
-}
-
-/* caller must hold wiphy_lock */
-static int __ath9k_wiphy_unpause(struct ath_wiphy *aphy)
-{
-        ieee80211_iterate_active_interfaces_atomic(aphy->hw,
-                                                   ath9k_unpause_iter, aphy);
-        aphy->state = ATH_WIPHY_ACTIVE;
-        ieee80211_wake_queues(aphy->hw);
-        return 0;
-}
-
-int ath9k_wiphy_unpause(struct ath_wiphy *aphy)
-{
-        int ret;
-        spin_lock_bh(&aphy->sc->wiphy_lock);
-        ret = __ath9k_wiphy_unpause(aphy);
-        spin_unlock_bh(&aphy->sc->wiphy_lock);
-        return ret;
-}
-
-static void __ath9k_wiphy_mark_all_paused(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state != ATH_WIPHY_INACTIVE)
-                sc->pri_wiphy->state = ATH_WIPHY_PAUSED;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state != ATH_WIPHY_INACTIVE)
-                        sc->sec_wiphy[i]->state = ATH_WIPHY_PAUSED;
-        }
-}
-
-/* caller must hold wiphy_lock */
-static void __ath9k_wiphy_pause_all(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE)
-                __ath9k_wiphy_pause(sc->pri_wiphy);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_ACTIVE)
-                        __ath9k_wiphy_pause(sc->sec_wiphy[i]);
-        }
-}
-
-int ath9k_wiphy_select(struct ath_wiphy *aphy)
-{
-        struct ath_softc *sc = aphy->sc;
-        bool now;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        if (__ath9k_wiphy_scanning(sc)) {
-                /*
-                 * For now, we are using mac80211 sw scan and it expects to
-                 * have full control over channel changes, so avoid wiphy
-                 * scheduling during a scan. This could be optimized if the
-                 * scanning control were moved into the driver.
-                 */
-                spin_unlock_bh(&sc->wiphy_lock);
-                return -EBUSY;
-        }
-        if (__ath9k_wiphy_pausing(sc)) {
-                if (sc->wiphy_select_failures == 0)
-                        sc->wiphy_select_first_fail = jiffies;
-                sc->wiphy_select_failures++;
-                if (time_after(jiffies, sc->wiphy_select_first_fail + HZ / 2))
-                {
-                        printk(KERN_DEBUG "ath9k: Previous wiphy select timed "
-                               "out; disable/enable hw to recover\n");
-                        __ath9k_wiphy_mark_all_paused(sc);
-                        /*
-                         * TODO: this workaround to fix hardware is unlikely to
-                         * be specific to virtual wiphy changes. It can happen
-                         * on normal channel change, too, and as such, this
-                         * should really be made more generic. For example,
-                         * tricker radio disable/enable on GTT interrupt burst
-                         * (say, 10 GTT interrupts received without any TX
-                         * frame being completed)
-                         */
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        ath_radio_disable(sc, aphy->hw);
-                        ath_radio_enable(sc, aphy->hw);
-                        /* Only the primary wiphy hw is used for queuing work */
-                        ieee80211_queue_work(aphy->sc->hw,
-                                   &aphy->sc->chan_work);
-                        return -EBUSY; /* previous select still in progress */
-                }
-                spin_unlock_bh(&sc->wiphy_lock);
-                return -EBUSY; /* previous select still in progress */
-        }
-        sc->wiphy_select_failures = 0;
-
-        /* Store the new channel */
-        sc->chan_idx = aphy->chan_idx;
-        sc->chan_is_ht = aphy->chan_is_ht;
-        sc->next_wiphy = aphy;
-
-        __ath9k_wiphy_pause_all(sc);
-        now = !__ath9k_wiphy_pausing(aphy->sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        if (now) {
-                /* Ready to request channel change immediately */
-                ieee80211_queue_work(aphy->sc->hw, &aphy->sc->chan_work);
-        }
-
-        /*
-         * wiphys will be unpaused in ath9k_tx_status() once channel has been
-         * changed if any wiphy needs time to become paused.
-         */
-
-        return 0;
-}
-
-bool ath9k_wiphy_started(struct ath_softc *sc)
-{
-        int i;
-        spin_lock_bh(&sc->wiphy_lock);
-        if (sc->pri_wiphy->state != ATH_WIPHY_INACTIVE) {
-                spin_unlock_bh(&sc->wiphy_lock);
-                return true;
-        }
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state != ATH_WIPHY_INACTIVE) {
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        return true;
-                }
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-        return false;
-}
-
-static void ath9k_wiphy_pause_chan(struct ath_wiphy *aphy,
-                                   struct ath_wiphy *selected)
-{
-        if (selected->state == ATH_WIPHY_SCAN) {
-                if (aphy == selected)
-                        return;
-                /*
-                 * Pause all other wiphys for the duration of the scan even if
-                 * they are on the current channel now.
-                 */
-        } else if (aphy->chan_idx == selected->chan_idx)
-                return;
-        aphy->state = ATH_WIPHY_PAUSED;
-        ieee80211_stop_queues(aphy->hw);
-}
-
-void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
-                                  struct ath_wiphy *selected)
-{
-        int i;
-        spin_lock_bh(&sc->wiphy_lock);
-        if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE)
-                ath9k_wiphy_pause_chan(sc->pri_wiphy, selected);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_ACTIVE)
-                        ath9k_wiphy_pause_chan(sc->sec_wiphy[i], selected);
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-}
-
-void ath9k_wiphy_work(struct work_struct *work)
-{
-        struct ath_softc *sc = container_of(work, struct ath_softc,
-                                            wiphy_work.work);
-        struct ath_wiphy *aphy = NULL;
-        bool first = true;
-
-        spin_lock_bh(&sc->wiphy_lock);
-
-        if (sc->wiphy_scheduler_int == 0) {
-                /* wiphy scheduler is disabled */
-                spin_unlock_bh(&sc->wiphy_lock);
-                return;
-        }
-
-try_again:
-        sc->wiphy_scheduler_index++;
-        while (sc->wiphy_scheduler_index <= sc->num_sec_wiphy) {
-                aphy = sc->sec_wiphy[sc->wiphy_scheduler_index - 1];
-                if (aphy && aphy->state != ATH_WIPHY_INACTIVE)
-                        break;
-
-                sc->wiphy_scheduler_index++;
-                aphy = NULL;
-        }
-        if (aphy == NULL) {
-                sc->wiphy_scheduler_index = 0;
-                if (sc->pri_wiphy->state == ATH_WIPHY_INACTIVE) {
-                        if (first) {
-                                first = false;
-                                goto try_again;
-                        }
-                        /* No wiphy is ready to be scheduled */
-                } else
-                        aphy = sc->pri_wiphy;
-        }
-
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        if (aphy &&
-            aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN &&
-            ath9k_wiphy_select(aphy)) {
-                printk(KERN_DEBUG "ath9k: Failed to schedule virtual wiphy "
-                       "change\n");
-        }
-
-        ieee80211_queue_delayed_work(sc->hw,
-                                     &sc->wiphy_work,
-                                     sc->wiphy_scheduler_int);
-}
-
-void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int)
-{
-        cancel_delayed_work_sync(&sc->wiphy_work);
-        sc->wiphy_scheduler_int = msecs_to_jiffies(msec_int);
-        if (sc->wiphy_scheduler_int)
-                ieee80211_queue_delayed_work(sc->hw, &sc->wiphy_work,
-                                             sc->wiphy_scheduler_int);
-}
-
-/* caller must hold wiphy_lock */
-bool ath9k_all_wiphys_idle(struct ath_softc *sc)
-{
-        unsigned int i;
-        if (!sc->pri_wiphy->idle)
-                return false;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (!aphy)
-                        continue;
-                if (!aphy->idle)
-                        return false;
-        }
-        return true;
-}
-
-/* caller must hold wiphy_lock */
-void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle)
-{
-        struct ath_softc *sc = aphy->sc;
-
-        aphy->idle = idle;
-        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                  "Marking %s as %s\n",
-                  wiphy_name(aphy->hw->wiphy),
-                  idle ? "idle" : "not-idle");
-}
-/* Only bother starting a queue on an active virtual wiphy */
-bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue)
-{
-        struct ieee80211_hw *hw = sc->pri_wiphy->hw;
-        unsigned int i;
-        bool txq_started = false;
-
-        spin_lock_bh(&sc->wiphy_lock);
-
-        /* Start the primary wiphy */
-        if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE) {
-                ieee80211_wake_queue(hw, skb_queue);
-                txq_started = true;
-                goto unlock;
-        }
-
-        /* Now start the secondary wiphy queues */
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (!aphy)
-                        continue;
-                if (aphy->state != ATH_WIPHY_ACTIVE)
-                        continue;
-
-                hw = aphy->hw;
-                ieee80211_wake_queue(hw, skb_queue);
-                txq_started = true;
-                break;
-        }
-
-unlock:
-        spin_unlock_bh(&sc->wiphy_lock);
-        return txq_started;
-}
-
-/* Go ahead and propagate information to all virtual wiphys, it won't hurt */
-void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue)
-{
-        struct ieee80211_hw *hw = sc->pri_wiphy->hw;
-        unsigned int i;
-
-        spin_lock_bh(&sc->wiphy_lock);
-
-        /* Stop the primary wiphy */
-        ieee80211_stop_queue(hw, skb_queue);
-
-        /* Now stop the secondary wiphy queues */
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (!aphy)
-                        continue;
-                hw = aphy->hw;
-                ieee80211_stop_queue(hw, skb_queue);
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-}
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c
index 6260faa658a2..35422fc1f2ce 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.c
+++ b/drivers/net/wireless/ath/ath9k/wmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -23,20 +23,18 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_ECHO_CMDID";
         case WMI_ACCESS_MEMORY_CMDID:
                 return "WMI_ACCESS_MEMORY_CMDID";
+        case WMI_GET_FW_VERSION:
+                return "WMI_GET_FW_VERSION";
         case WMI_DISABLE_INTR_CMDID:
                 return "WMI_DISABLE_INTR_CMDID";
         case WMI_ENABLE_INTR_CMDID:
                 return "WMI_ENABLE_INTR_CMDID";
-        case WMI_RX_LINK_CMDID:
-                return "WMI_RX_LINK_CMDID";
         case WMI_ATH_INIT_CMDID:
                 return "WMI_ATH_INIT_CMDID";
         case WMI_ABORT_TXQ_CMDID:
                 return "WMI_ABORT_TXQ_CMDID";
         case WMI_STOP_TX_DMA_CMDID:
                 return "WMI_STOP_TX_DMA_CMDID";
-        case WMI_STOP_DMA_RECV_CMDID:
-                return "WMI_STOP_DMA_RECV_CMDID";
         case WMI_ABORT_TX_DMA_CMDID:
                 return "WMI_ABORT_TX_DMA_CMDID";
         case WMI_DRAIN_TXQ_CMDID:
@@ -51,8 +49,6 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_FLUSH_RECV_CMDID";
         case WMI_SET_MODE_CMDID:
                 return "WMI_SET_MODE_CMDID";
-        case WMI_RESET_CMDID:
-                return "WMI_RESET_CMDID";
         case WMI_NODE_CREATE_CMDID:
                 return "WMI_NODE_CREATE_CMDID";
         case WMI_NODE_REMOVE_CMDID:
@@ -61,8 +57,6 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_VAP_REMOVE_CMDID";
         case WMI_VAP_CREATE_CMDID:
                 return "WMI_VAP_CREATE_CMDID";
-        case WMI_BEACON_UPDATE_CMDID:
-                return "WMI_BEACON_UPDATE_CMDID";
         case WMI_REG_READ_CMDID:
                 return "WMI_REG_READ_CMDID";
         case WMI_REG_WRITE_CMDID:
@@ -71,20 +65,22 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_RC_STATE_CHANGE_CMDID";
         case WMI_RC_RATE_UPDATE_CMDID:
                 return "WMI_RC_RATE_UPDATE_CMDID";
-        case WMI_DEBUG_INFO_CMDID:
-                return "WMI_DEBUG_INFO_CMDID";
-        case WMI_HOST_ATTACH:
-                return "WMI_HOST_ATTACH";
         case WMI_TARGET_IC_UPDATE_CMDID:
                 return "WMI_TARGET_IC_UPDATE_CMDID";
-        case WMI_TGT_STATS_CMDID:
-                return "WMI_TGT_STATS_CMDID";
         case WMI_TX_AGGR_ENABLE_CMDID:
                 return "WMI_TX_AGGR_ENABLE_CMDID";
         case WMI_TGT_DETACH_CMDID:
                 return "WMI_TGT_DETACH_CMDID";
-        case WMI_TGT_TXQ_ENABLE_CMDID:
-                return "WMI_TGT_TXQ_ENABLE_CMDID";
+        case WMI_NODE_UPDATE_CMDID:
+                return "WMI_NODE_UPDATE_CMDID";
+        case WMI_INT_STATS_CMDID:
+                return "WMI_INT_STATS_CMDID";
+        case WMI_TX_STATS_CMDID:
+                return "WMI_TX_STATS_CMDID";
+        case WMI_RX_STATS_CMDID:
+                return "WMI_RX_STATS_CMDID";
+        case WMI_BITRATE_MASK_CMDID:
+                return "WMI_BITRATE_MASK_CMDID";
         }
 
         return "Bogus";
@@ -100,9 +96,15 @@ struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv)
 
         wmi->drv_priv = priv;
         wmi->stopped = false;
+        skb_queue_head_init(&wmi->wmi_event_queue);
+        spin_lock_init(&wmi->wmi_lock);
+        spin_lock_init(&wmi->event_lock);
         mutex_init(&wmi->op_mutex);
         mutex_init(&wmi->multi_write_mutex);
         init_completion(&wmi->cmd_wait);
+        INIT_LIST_HEAD(&wmi->pending_tx_events);
+        tasklet_init(&wmi->wmi_event_tasklet, ath9k_wmi_event_tasklet,
+                     (unsigned long)wmi);
 
         return wmi;
 }
@@ -118,59 +120,75 @@ void ath9k_deinit_wmi(struct ath9k_htc_priv *priv)
         kfree(priv->wmi);
 }
 
-void ath9k_wmi_tasklet(unsigned long data)
+void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv)
 {
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
-        struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct wmi_cmd_hdr *hdr;
-        struct wmi_swba *swba_hdr;
-        enum wmi_event_id event;
-        struct sk_buff *skb;
-        void *wmi_event;
         unsigned long flags;
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-        __be32 txrate;
-#endif
 
+        tasklet_kill(&priv->wmi->wmi_event_tasklet);
         spin_lock_irqsave(&priv->wmi->wmi_lock, flags);
-        skb = priv->wmi->wmi_skb;
+        __skb_queue_purge(&priv->wmi->wmi_event_queue);
         spin_unlock_irqrestore(&priv->wmi->wmi_lock, flags);
+}
 
-        hdr = (struct wmi_cmd_hdr *) skb->data;
-        event = be16_to_cpu(hdr->command_id);
-        wmi_event = skb_pull(skb, sizeof(struct wmi_cmd_hdr));
-
-        ath_print(common, ATH_DBG_WMI,
-                  "WMI Event: 0x%x\n", event);
-
-        switch (event) {
-        case WMI_TGT_RDY_EVENTID:
-                break;
-        case WMI_SWBA_EVENTID:
-                swba_hdr = (struct wmi_swba *) wmi_event;
-                ath9k_htc_swba(priv, swba_hdr->beacon_pending);
-                break;
-        case WMI_FATAL_EVENTID:
-                break;
-        case WMI_TXTO_EVENTID:
-                break;
-        case WMI_BMISS_EVENTID:
-                break;
-        case WMI_WLAN_TXCOMP_EVENTID:
-                break;
-        case WMI_DELBA_EVENTID:
-                break;
-        case WMI_TXRATE_EVENTID:
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-                txrate = ((struct wmi_event_txrate *)wmi_event)->txrate;
-                priv->debug.txrate = be32_to_cpu(txrate);
-#endif
-                break;
-        default:
-                break;
-        }
+void ath9k_wmi_event_tasklet(unsigned long data)
+{
+        struct wmi *wmi = (struct wmi *)data;
+        struct ath9k_htc_priv *priv = wmi->drv_priv;
+        struct wmi_cmd_hdr *hdr;
+        void *wmi_event;
+        struct wmi_event_swba *swba;
+        struct sk_buff *skb = NULL;
+        unsigned long flags;
+        u16 cmd_id;
 
-        kfree_skb(skb);
+        do {
+                spin_lock_irqsave(&wmi->wmi_lock, flags);
+                skb = __skb_dequeue(&wmi->wmi_event_queue);
+                if (!skb) {
+                        spin_unlock_irqrestore(&wmi->wmi_lock, flags);
+                        return;
+                }
+                spin_unlock_irqrestore(&wmi->wmi_lock, flags);
+
+                hdr = (struct wmi_cmd_hdr *) skb->data;
+                cmd_id = be16_to_cpu(hdr->command_id);
+                wmi_event = skb_pull(skb, sizeof(struct wmi_cmd_hdr));
+
+                switch (cmd_id) {
+                case WMI_SWBA_EVENTID:
+                        swba = (struct wmi_event_swba *) wmi_event;
+                        ath9k_htc_swba(priv, swba);
+                        break;
+                case WMI_FATAL_EVENTID:
+                        ieee80211_queue_work(wmi->drv_priv->hw,
+                                             &wmi->drv_priv->fatal_work);
+                        break;
+                case WMI_TXSTATUS_EVENTID:
+                        spin_lock_bh(&priv->tx.tx_lock);
+                        if (priv->tx.flags & ATH9K_HTC_OP_TX_DRAIN) {
+                                spin_unlock_bh(&priv->tx.tx_lock);
+                                break;
+                        }
+                        spin_unlock_bh(&priv->tx.tx_lock);
+
+                        ath9k_htc_txstatus(priv, wmi_event);
+                        break;
+                default:
+                        break;
+                }
+
+                kfree_skb(skb);
+        } while (1);
+}
+
+void ath9k_fatal_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   fatal_work);
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+
+        ath_dbg(common, ATH_DBG_FATAL, "FATAL Event received, resetting device\n");
+        ath9k_htc_reset(priv);
 }
 
 static void ath9k_wmi_rsp_callback(struct wmi *wmi, struct sk_buff *skb)
@@ -198,9 +216,9 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb,
 
         if (cmd_id & 0x1000) {
                 spin_lock(&wmi->wmi_lock);
-                wmi->wmi_skb = skb;
+                __skb_queue_tail(&wmi->wmi_event_queue, skb);
                 spin_unlock(&wmi->wmi_lock);
-                tasklet_schedule(&wmi->drv_priv->wmi_tasklet);
+                tasklet_schedule(&wmi->wmi_event_tasklet);
                 return;
         }
 
@@ -259,7 +277,7 @@ static int ath9k_wmi_cmd_issue(struct wmi *wmi,
         hdr->command_id = cpu_to_be16(cmd);
         hdr->seq_no = cpu_to_be16(++wmi->tx_seq_id);
 
-        return htc_send(wmi->htc, skb, wmi->ctrl_epid, NULL);
+        return htc_send_epid(wmi->htc, skb, wmi->ctrl_epid);
 }
 
 int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
@@ -276,7 +294,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
         int time_left, ret = 0;
         unsigned long flags;
 
-        if (wmi->drv_priv->op_flags & OP_UNPLUGGED)
+        if (ah->ah_flags & AH_UNPLUGGED)
                 return 0;
 
         skb = alloc_skb(headroom + cmd_len, GFP_ATOMIC);
@@ -312,9 +330,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
 
         time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout);
         if (!time_left) {
-                ath_print(common, ATH_DBG_WMI,
-                          "Timeout waiting for WMI command: %s\n",
-                          wmi_cmd_to_name(cmd_id));
+                ath_dbg(common, ATH_DBG_WMI,
+                        "Timeout waiting for WMI command: %s\n",
+                        wmi_cmd_to_name(cmd_id));
                 mutex_unlock(&wmi->op_mutex);
                 return -ETIMEDOUT;
         }
@@ -324,8 +342,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
         return 0;
 
 out:
-        ath_print(common, ATH_DBG_WMI,
-                  "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
+        ath_dbg(common, ATH_DBG_WMI,
+                "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
         mutex_unlock(&wmi->op_mutex);
         kfree_skb(skb);
 
diff --git a/drivers/net/wireless/ath/ath9k/wmi.h b/drivers/net/wireless/ath/ath9k/wmi.h
index 765db5faa2d3..fde6da619f30 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.h
+++ b/drivers/net/wireless/ath/ath9k/wmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,7 +17,6 @@
 #ifndef WMI_H
 #define WMI_H
 
-
 struct wmi_event_txrate {
         __be32 txrate;
         struct {
@@ -31,8 +30,52 @@ struct wmi_cmd_hdr {
         __be16 seq_no;
 } __packed;
 
-struct wmi_swba {
+struct wmi_fw_version {
+        __be16 major;
+        __be16 minor;
+
+} __packed;
+
+struct wmi_event_swba {
+        __be64 tsf;
         u8 beacon_pending;
+};
+
+/*
+ * 64 - HTC header - WMI header - 1 / txstatus
+ * And some other hdr. space is also accounted for.
+ * 12 seems to be the magic number.
+ */
+#define HTC_MAX_TX_STATUS 12
+
+#define ATH9K_HTC_TXSTAT_ACK        BIT(0)
+#define ATH9K_HTC_TXSTAT_FILT       BIT(1)
+#define ATH9K_HTC_TXSTAT_RTC_CTS    BIT(2)
+#define ATH9K_HTC_TXSTAT_MCS        BIT(3)
+#define ATH9K_HTC_TXSTAT_CW40       BIT(4)
+#define ATH9K_HTC_TXSTAT_SGI        BIT(5)
+
+/*
+ * Legacy rates are indicated as indices.
+ * HT rates are indicated as dot11 numbers.
+ * This allows us to resrict the rate field
+ * to 4 bits.
+ */
+#define ATH9K_HTC_TXSTAT_RATE       0x0f
+#define ATH9K_HTC_TXSTAT_RATE_S     0
+
+#define ATH9K_HTC_TXSTAT_EPID       0xf0
+#define ATH9K_HTC_TXSTAT_EPID_S     4
+
+struct __wmi_event_txstatus {
+        u8 cookie;
+        u8 ts_rate; /* Also holds EP ID */
+        u8 ts_flags;
+};
+
+struct wmi_event_txstatus {
+        u8 cnt;
+        struct __wmi_event_txstatus txstatus[HTC_MAX_TX_STATUS];
 } __packed;
 
 enum wmi_cmd_id {
@@ -40,13 +83,12 @@ enum wmi_cmd_id {
         WMI_ACCESS_MEMORY_CMDID,
 
         /* Commands to Target */
+        WMI_GET_FW_VERSION,
         WMI_DISABLE_INTR_CMDID,
         WMI_ENABLE_INTR_CMDID,
-        WMI_RX_LINK_CMDID,
         WMI_ATH_INIT_CMDID,
         WMI_ABORT_TXQ_CMDID,
         WMI_STOP_TX_DMA_CMDID,
-        WMI_STOP_DMA_RECV_CMDID,
         WMI_ABORT_TX_DMA_CMDID,
         WMI_DRAIN_TXQ_CMDID,
         WMI_DRAIN_TXQ_ALL_CMDID,
@@ -54,23 +96,22 @@ enum wmi_cmd_id {
         WMI_STOP_RECV_CMDID,
         WMI_FLUSH_RECV_CMDID,
         WMI_SET_MODE_CMDID,
-        WMI_RESET_CMDID,
         WMI_NODE_CREATE_CMDID,
         WMI_NODE_REMOVE_CMDID,
         WMI_VAP_REMOVE_CMDID,
         WMI_VAP_CREATE_CMDID,
-        WMI_BEACON_UPDATE_CMDID,
         WMI_REG_READ_CMDID,
         WMI_REG_WRITE_CMDID,
         WMI_RC_STATE_CHANGE_CMDID,
         WMI_RC_RATE_UPDATE_CMDID,
-        WMI_DEBUG_INFO_CMDID,
-        WMI_HOST_ATTACH,
         WMI_TARGET_IC_UPDATE_CMDID,
-        WMI_TGT_STATS_CMDID,
         WMI_TX_AGGR_ENABLE_CMDID,
         WMI_TGT_DETACH_CMDID,
-        WMI_TGT_TXQ_ENABLE_CMDID,
+        WMI_NODE_UPDATE_CMDID,
+        WMI_INT_STATS_CMDID,
+        WMI_TX_STATS_CMDID,
+        WMI_RX_STATS_CMDID,
+        WMI_BITRATE_MASK_CMDID,
 };
 
 enum wmi_event_id {
@@ -79,9 +120,8 @@ enum wmi_event_id {
         WMI_FATAL_EVENTID,
         WMI_TXTO_EVENTID,
         WMI_BMISS_EVENTID,
-        WMI_WLAN_TXCOMP_EVENTID,
         WMI_DELBA_EVENTID,
-        WMI_TXRATE_EVENTID,
+        WMI_TXSTATUS_EVENTID,
 };
 
 #define MAX_CMD_NUMBER 62
@@ -91,6 +131,12 @@ struct register_write {
         __be32 val;
 };
 
+struct ath9k_htc_tx_event {
+        int count;
+        struct __wmi_event_txstatus txs;
+        struct list_head list;
+};
+
 struct wmi {
         struct ath9k_htc_priv *drv_priv;
         struct htc_target *htc;
@@ -98,12 +144,16 @@ struct wmi {
         struct mutex op_mutex;
         struct completion cmd_wait;
         enum wmi_cmd_id last_cmd_id;
+        struct sk_buff_head wmi_event_queue;
+        struct tasklet_struct wmi_event_tasklet;
         u16 tx_seq_id;
         u8 *cmd_rsp_buf;
         u32 cmd_rsp_len;
         bool stopped;
 
-        struct sk_buff *wmi_skb;
+        struct list_head pending_tx_events;
+        spinlock_t event_lock;
+
         spinlock_t wmi_lock;
 
         atomic_t mwrite_cnt;
@@ -120,7 +170,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
                   u8 *cmd_buf, u32 cmd_len,
                   u8 *rsp_buf, u32 rsp_len,
                   u32 timeout);
-void ath9k_wmi_tasklet(unsigned long data);
+void ath9k_wmi_event_tasklet(unsigned long data);
+void ath9k_fatal_work(struct work_struct *work);
+void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv);
 
 #define WMI_CMD(_wmi_cmd)                                               \
         do {                                                            \
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 4dda14e36227..33443bcaa8d9 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,7 +19,6 @@
 
 #define BITS_PER_BYTE           8
 #define OFDM_PLCP_BITS          22
-#define HT_RC_2_MCS(_rc)        ((_rc) & 0x1f)
 #define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
 #define L_STF                   8
 #define L_LTF                   8
@@ -32,7 +31,6 @@
 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
 
-#define OFDM_SIFS_TIME              16
 
 static u16 bits_per_symbol[][2] = {
         /* 20MHz 40MHz */
@@ -48,19 +46,20 @@ static u16 bits_per_symbol[][2] = {
 
 #define IS_HT_RATE(_rate)     ((_rate) & 0x80)
 
-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
-                                  struct ath_atx_tid *tid,
-                                  struct list_head *bf_head);
+static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+                               struct ath_atx_tid *tid,
+                               struct list_head *bf_head);
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                                 struct ath_txq *txq, struct list_head *bf_q,
                                 struct ath_tx_status *ts, int txok, int sendbar);
 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                              struct list_head *head);
-static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
-static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
-                              struct ath_tx_status *ts, int txok);
-static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
-                             int nbad, int txok, bool update_rc);
+static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
+static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_status *ts, int nframes, int nbad,
+                             int txok, bool update_rc);
+static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
+                              int seqno);
 
 enum {
         MCS_HT20,
@@ -122,7 +121,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
 
 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
-        struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
+        struct ath_txq *txq = tid->ac->txq;
 
         WARN_ON(!tid->paused);
 
@@ -138,23 +137,40 @@ unlock:
         spin_unlock_bh(&txq->axq_lock);
 }
 
+static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        BUILD_BUG_ON(sizeof(struct ath_frame_info) >
+                     sizeof(tx_info->rate_driver_data));
+        return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
+}
+
 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
-        struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
+        struct ath_txq *txq = tid->ac->txq;
         struct ath_buf *bf;
         struct list_head bf_head;
-        INIT_LIST_HEAD(&bf_head);
+        struct ath_tx_status ts;
+        struct ath_frame_info *fi;
 
-        WARN_ON(!tid->paused);
+        INIT_LIST_HEAD(&bf_head);
 
+        memset(&ts, 0, sizeof(ts));
         spin_lock_bh(&txq->axq_lock);
-        tid->paused = false;
 
         while (!list_empty(&tid->buf_q)) {
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
-                BUG_ON(bf_isretried(bf));
                 list_move_tail(&bf->list, &bf_head);
-                ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
+
+                spin_unlock_bh(&txq->axq_lock);
+                fi = get_frame_info(bf->bf_mpdu);
+                if (fi->retries) {
+                        ath_tx_update_baw(sc, tid, fi->seqno);
+                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
+                } else {
+                        ath_tx_send_normal(sc, txq, NULL, &bf_head);
+                }
+                spin_lock_bh(&txq->axq_lock);
         }
 
         spin_unlock_bh(&txq->axq_lock);
@@ -168,27 +184,22 @@ static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
         index  = ATH_BA_INDEX(tid->seq_start, seqno);
         cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
 
-        tid->tx_buf[cindex] = NULL;
+        __clear_bit(cindex, tid->tx_buf);
 
-        while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
+        while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
                 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
                 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
         }
 }
 
 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
-                             struct ath_buf *bf)
+                             u16 seqno)
 {
         int index, cindex;
 
-        if (bf_isretried(bf))
-                return;
-
-        index  = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
+        index  = ATH_BA_INDEX(tid->seq_start, seqno);
         cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
-
-        BUG_ON(tid->tx_buf[cindex] != NULL);
-        tid->tx_buf[cindex] = bf;
+        __set_bit(cindex, tid->tx_buf);
 
         if (index >= ((tid->baw_tail - tid->baw_head) &
                 (ATH_TID_MAX_BUFS - 1))) {
@@ -210,6 +221,7 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
         struct ath_buf *bf;
         struct list_head bf_head;
         struct ath_tx_status ts;
+        struct ath_frame_info *fi;
 
         memset(&ts, 0, sizeof(ts));
         INIT_LIST_HEAD(&bf_head);
@@ -221,8 +233,9 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
                 list_move_tail(&bf->list, &bf_head);
 
-                if (bf_isretried(bf))
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                fi = get_frame_info(bf->bf_mpdu);
+                if (fi->retries)
+                        ath_tx_update_baw(sc, tid, fi->seqno);
 
                 spin_unlock(&txq->axq_lock);
                 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
@@ -234,16 +247,15 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
 }
 
 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
-                             struct ath_buf *bf)
+                             struct sk_buff *skb)
 {
-        struct sk_buff *skb;
+        struct ath_frame_info *fi = get_frame_info(skb);
         struct ieee80211_hdr *hdr;
 
-        bf->bf_state.bf_type |= BUF_RETRY;
-        bf->bf_retries++;
         TX_STAT_INC(txq->axq_qnum, a_retries);
+        if (fi->retries++ > 0)
+                return;
 
-        skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
 }
@@ -284,24 +296,54 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
 
         ATH_TXBUF_RESET(tbf);
 
-        tbf->aphy = bf->aphy;
         tbf->bf_mpdu = bf->bf_mpdu;
         tbf->bf_buf_addr = bf->bf_buf_addr;
         memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
         tbf->bf_state = bf->bf_state;
-        tbf->bf_dmacontext = bf->bf_dmacontext;
 
         return tbf;
 }
 
+static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
+                                struct ath_tx_status *ts, int txok,
+                                int *nframes, int *nbad)
+{
+        struct ath_frame_info *fi;
+        u16 seq_st = 0;
+        u32 ba[WME_BA_BMP_SIZE >> 5];
+        int ba_index;
+        int isaggr = 0;
+
+        *nbad = 0;
+        *nframes = 0;
+
+        isaggr = bf_isaggr(bf);
+        if (isaggr) {
+                seq_st = ts->ts_seqnum;
+                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
+        }
+
+        while (bf) {
+                fi = get_frame_info(bf->bf_mpdu);
+                ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
+
+                (*nframes)++;
+                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
+                        (*nbad)++;
+
+                bf = bf->bf_next;
+        }
+}
+
+
 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                  struct ath_buf *bf, struct list_head *bf_q,
-                                 struct ath_tx_status *ts, int txok)
+                                 struct ath_tx_status *ts, int txok, bool retry)
 {
         struct ath_node *an = NULL;
         struct sk_buff *skb;
         struct ieee80211_sta *sta;
-        struct ieee80211_hw *hw;
+        struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_hdr *hdr;
         struct ieee80211_tx_info *tx_info;
         struct ath_atx_tid *tid = NULL;
@@ -312,19 +354,21 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
         bool rc_update = true;
         struct ieee80211_tx_rate rates[4];
+        struct ath_frame_info *fi;
+        int nframes;
+        u8 tidno;
+        bool clear_filter;
 
         skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
 
         tx_info = IEEE80211_SKB_CB(skb);
-        hw = bf->aphy->hw;
 
         memcpy(rates, tx_info->control.rates, sizeof(rates));
 
         rcu_read_lock();
 
-        /* XXX: use ieee80211_find_sta! */
-        sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
+        sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
         if (!sta) {
                 rcu_read_unlock();
 
@@ -337,7 +381,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                             !bf->bf_stale || bf_next != NULL)
                                 list_move_tail(&bf->list, &bf_head);
 
-                        ath_tx_rc_status(bf, ts, 0, 0, false);
+                        ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
                                 0, 0);
 
@@ -347,14 +391,15 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         }
 
         an = (struct ath_node *)sta->drv_priv;
-        tid = ATH_AN_2_TID(an, bf->bf_tidno);
+        tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+        tid = ATH_AN_2_TID(an, tidno);
 
         /*
          * The hardware occasionally sends a tx status for the wrong TID.
          * In this case, the BA status cannot be considered valid and all
          * subframes need to be retransmitted
          */
-        if (bf->bf_tidno != ts->tid)
+        if (tidno != ts->tid)
                 txok = false;
 
         isaggr = bf_isaggr(bf);
@@ -380,15 +425,16 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         INIT_LIST_HEAD(&bf_pending);
         INIT_LIST_HEAD(&bf_head);
 
-        nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
+        ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
         while (bf) {
-                txfail = txpending = 0;
+                txfail = txpending = sendbar = 0;
                 bf_next = bf->bf_next;
 
                 skb = bf->bf_mpdu;
                 tx_info = IEEE80211_SKB_CB(skb);
+                fi = get_frame_info(skb);
 
-                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
+                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
                         /* transmit completion, subframe is
                          * acked by block ack */
                         acked_cnt++;
@@ -396,23 +442,24 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         /* transmit completion */
                         acked_cnt++;
                 } else {
-                        if (!(tid->state & AGGR_CLEANUP) &&
-                            !bf_last->bf_tx_aborted) {
-                                if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
-                                        ath_tx_set_retry(sc, txq, bf);
-                                        txpending = 1;
-                                } else {
-                                        bf->bf_state.bf_type |= BUF_XRETRY;
-                                        txfail = 1;
-                                        sendbar = 1;
-                                        txfail_cnt++;
-                                }
-                        } else {
+                        if ((tid->state & AGGR_CLEANUP) || !retry) {
                                 /*
                                  * cleanup in progress, just fail
                                  * the un-acked sub-frames
                                  */
                                 txfail = 1;
+                        } else if (fi->retries < ATH_MAX_SW_RETRIES) {
+                                if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
+                                    !an->sleeping)
+                                        ath_tx_set_retry(sc, txq, bf->bf_mpdu);
+
+                                clear_filter = true;
+                                txpending = 1;
+                        } else {
+                                bf->bf_state.bf_type |= BUF_XRETRY;
+                                txfail = 1;
+                                sendbar = 1;
+                                txfail_cnt++;
                         }
                 }
 
@@ -431,27 +478,28 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         list_move_tail(&bf->list, &bf_head);
                 }
 
-                if (!txpending) {
+                if (!txpending || (tid->state & AGGR_CLEANUP)) {
                         /*
                          * complete the acked-ones/xretried ones; update
                          * block-ack window
                          */
                         spin_lock_bh(&txq->axq_lock);
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                        ath_tx_update_baw(sc, tid, fi->seqno);
                         spin_unlock_bh(&txq->axq_lock);
 
                         if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
                                 memcpy(tx_info->control.rates, rates, sizeof(rates));
-                                ath_tx_rc_status(bf, ts, nbad, txok, true);
+                                ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
                                 rc_update = false;
                         } else {
-                                ath_tx_rc_status(bf, ts, nbad, txok, false);
+                                ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
                         }
 
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
                                 !txfail, sendbar);
                 } else {
                         /* retry the un-acked ones */
+                        ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
                         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
                                 if (bf->bf_next == NULL && bf_last->bf_stale) {
                                         struct ath_buf *tbf;
@@ -464,14 +512,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                          */
                                         if (!tbf) {
                                                 spin_lock_bh(&txq->axq_lock);
-                                                ath_tx_update_baw(sc, tid,
-                                                                bf->bf_seqno);
+                                                ath_tx_update_baw(sc, tid, fi->seqno);
                                                 spin_unlock_bh(&txq->axq_lock);
 
                                                 bf->bf_state.bf_type |=
                                                         BUF_XRETRY;
-                                                ath_tx_rc_status(bf, ts, nbad,
-                                                                0, false);
+                                                ath_tx_rc_status(sc, bf, ts, nframes,
+                                                                nbad, 0, false);
                                                 ath_tx_complete_buf(sc, bf, txq,
                                                                     &bf_head,
                                                                     ts, 0, 0);
@@ -503,28 +550,33 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
 
         /* prepend un-acked frames to the beginning of the pending frame queue */
         if (!list_empty(&bf_pending)) {
+                if (an->sleeping)
+                        ieee80211_sta_set_tim(sta);
+
                 spin_lock_bh(&txq->axq_lock);
+                if (clear_filter)
+                        tid->ac->clear_ps_filter = true;
                 list_splice(&bf_pending, &tid->buf_q);
                 ath_tx_queue_tid(txq, tid);
                 spin_unlock_bh(&txq->axq_lock);
         }
 
         if (tid->state & AGGR_CLEANUP) {
+                ath_tx_flush_tid(sc, tid);
+
                 if (tid->baw_head == tid->baw_tail) {
                         tid->state &= ~AGGR_ADDBA_COMPLETE;
                         tid->state &= ~AGGR_CLEANUP;
-
-                        /* send buffered frames as singles */
-                        ath_tx_flush_tid(sc, tid);
                 }
-                rcu_read_unlock();
-                return;
         }
 
         rcu_read_unlock();
 
-        if (needreset)
+        if (needreset) {
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 ath_reset(sc, false);
+                spin_lock_bh(&sc->sc_pcu_lock);
+        }
 }
 
 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
@@ -585,8 +637,8 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
                                  (u32)ATH_AMPDU_LIMIT_MAX);
 
         /*
-         * h/w can accept aggregates upto 16 bit lengths (65535).
-         * The IE, however can hold upto 65536, which shows up here
+         * h/w can accept aggregates up to 16 bit lengths (65535).
+         * The IE, however can hold up to 65536, which shows up here
          * as zero. Ignore 65536 since we  are constrained by hw.
          */
         if (tid->an->maxampdu)
@@ -608,6 +660,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
         u16 minlen;
         u8 flags, rix;
         int width, streams, half_gi, ndelim, mindelim;
+        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
 
         /* Select standard number of delimiters based on frame length alone */
         ndelim = ATH_AGGR_GET_NDELIM(frmlen);
@@ -618,7 +671,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
          * TODO - this could be improved to be dependent on the rate.
          *      The hardware can keep up at lower rates, but not higher rates
          */
-        if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
+        if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
+            !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
                 ndelim += ATH_AGGR_ENCRYPTDELIM;
 
         /*
@@ -662,7 +716,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                                              struct ath_txq *txq,
                                              struct ath_atx_tid *tid,
-                                             struct list_head *bf_q)
+                                             struct list_head *bf_q,
+                                             int *aggr_len)
 {
 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
         struct ath_buf *bf, *bf_first, *bf_prev = NULL;
@@ -670,14 +725,17 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
         u16 aggr_limit = 0, al = 0, bpad = 0,
                 al_delta, h_baw = tid->baw_size / 2;
         enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
+        struct ieee80211_tx_info *tx_info;
+        struct ath_frame_info *fi;
 
         bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
 
         do {
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
+                fi = get_frame_info(bf->bf_mpdu);
 
                 /* do not step over block-ack window */
-                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
+                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
                         status = ATH_AGGR_BAW_CLOSED;
                         break;
                 }
@@ -688,7 +746,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                 }
 
                 /* do not exceed aggregation limit */
-                al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
+                al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
 
                 if (nframes &&
                     (aggr_limit < (al + bpad + al_delta + prev_al))) {
@@ -696,6 +754,11 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                         break;
                 }
 
+                tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
+                if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
+                        !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
+                        break;
+
                 /* do not exceed subframe limit */
                 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
                         status = ATH_AGGR_LIMITED;
@@ -710,14 +773,15 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                  * Get the delimiters needed to meet the MPDU
                  * density for this node.
                  */
-                ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
+                ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
                 bpad = PADBYTES(al_delta) + (ndelim << 2);
 
                 bf->bf_next = NULL;
                 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
 
                 /* link buffers of this frame to the aggregate */
-                ath_tx_addto_baw(sc, tid, bf);
+                if (!fi->retries)
+                        ath_tx_addto_baw(sc, tid, fi->seqno);
                 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
                 list_move_tail(&bf->list, bf_q);
                 if (bf_prev) {
@@ -729,8 +793,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
 
         } while (!list_empty(&tid->buf_q));
 
-        bf_first->bf_al = al;
-        bf_first->bf_nframes = nframes;
+        *aggr_len = al;
 
         return status;
 #undef PADBYTES
@@ -741,7 +804,9 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
 {
         struct ath_buf *bf;
         enum ATH_AGGR_STATUS status;
+        struct ath_frame_info *fi;
         struct list_head bf_q;
+        int aggr_len;
 
         do {
                 if (list_empty(&tid->buf_q))
@@ -749,7 +814,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
 
                 INIT_LIST_HEAD(&bf_q);
 
-                status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
+                status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
 
                 /*
                  * no frames picked up to be aggregated;
@@ -761,19 +826,26 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 bf = list_first_entry(&bf_q, struct ath_buf, list);
                 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
 
+                if (tid->ac->clear_ps_filter) {
+                        tid->ac->clear_ps_filter = false;
+                        ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
+                }
+
                 /* if only one frame, send as non-aggregate */
-                if (bf->bf_nframes == 1) {
+                if (bf == bf->bf_lastbf) {
+                        fi = get_frame_info(bf->bf_mpdu);
+
                         bf->bf_state.bf_type &= ~BUF_AGGR;
                         ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
-                        ath_buf_set_rate(sc, bf);
+                        ath_buf_set_rate(sc, bf, fi->framelen);
                         ath_tx_txqaddbuf(sc, txq, &bf_q);
                         continue;
                 }
 
                 /* setup first desc of aggregate */
                 bf->bf_state.bf_type |= BUF_AGGR;
-                ath_buf_set_rate(sc, bf);
-                ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
+                ath_buf_set_rate(sc, bf, aggr_len);
+                ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
 
                 /* anchor last desc of aggregate */
                 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
@@ -781,34 +853,37 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 ath_tx_txqaddbuf(sc, txq, &bf_q);
                 TX_STAT_INC(txq->axq_qnum, a_aggr);
 
-        } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
+        } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
                  status != ATH_AGGR_BAW_CLOSED);
 }
 
-void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
-                       u16 tid, u16 *ssn)
+int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
+                      u16 tid, u16 *ssn)
 {
         struct ath_atx_tid *txtid;
         struct ath_node *an;
 
         an = (struct ath_node *)sta->drv_priv;
         txtid = ATH_AN_2_TID(an, tid);
+
+        if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
+                return -EAGAIN;
+
         txtid->state |= AGGR_ADDBA_PROGRESS;
         txtid->paused = true;
-        *ssn = txtid->seq_start;
+        *ssn = txtid->seq_start = txtid->seq_next;
+
+        memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
+        txtid->baw_head = txtid->baw_tail = 0;
+
+        return 0;
 }
 
 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
         struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
-        struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
-        struct ath_tx_status ts;
-        struct ath_buf *bf;
-        struct list_head bf_head;
-
-        memset(&ts, 0, sizeof(ts));
-        INIT_LIST_HEAD(&bf_head);
+        struct ath_txq *txq = txtid->ac->txq;
 
         if (txtid->state & AGGR_CLEANUP)
                 return;
@@ -818,30 +893,82 @@ void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
                 return;
         }
 
-        /* drop all software retried frames and mark this TID */
         spin_lock_bh(&txq->axq_lock);
         txtid->paused = true;
-        while (!list_empty(&txtid->buf_q)) {
-                bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
-                if (!bf_isretried(bf)) {
-                        /*
-                         * NB: it's based on the assumption that
-                         * software retried frame will always stay
-                         * at the head of software queue.
-                         */
-                        break;
-                }
-                list_move_tail(&bf->list, &bf_head);
-                ath_tx_update_baw(sc, txtid, bf->bf_seqno);
-                ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
-        }
-        spin_unlock_bh(&txq->axq_lock);
 
-        if (txtid->baw_head != txtid->baw_tail) {
+        /*
+         * If frames are still being transmitted for this TID, they will be
+         * cleaned up during tx completion. To prevent race conditions, this
+         * TID can only be reused after all in-progress subframes have been
+         * completed.
+         */
+        if (txtid->baw_head != txtid->baw_tail)
                 txtid->state |= AGGR_CLEANUP;
-        } else {
+        else
                 txtid->state &= ~AGGR_ADDBA_COMPLETE;
-                ath_tx_flush_tid(sc, txtid);
+        spin_unlock_bh(&txq->axq_lock);
+
+        ath_tx_flush_tid(sc, txtid);
+}
+
+bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
+{
+        struct ath_atx_tid *tid;
+        struct ath_atx_ac *ac;
+        struct ath_txq *txq;
+        bool buffered = false;
+        int tidno;
+
+        for (tidno = 0, tid = &an->tid[tidno];
+             tidno < WME_NUM_TID; tidno++, tid++) {
+
+                if (!tid->sched)
+                        continue;
+
+                ac = tid->ac;
+                txq = ac->txq;
+
+                spin_lock_bh(&txq->axq_lock);
+
+                if (!list_empty(&tid->buf_q))
+                        buffered = true;
+
+                tid->sched = false;
+                list_del(&tid->list);
+
+                if (ac->sched) {
+                        ac->sched = false;
+                        list_del(&ac->list);
+                }
+
+                spin_unlock_bh(&txq->axq_lock);
+        }
+
+        return buffered;
+}
+
+void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
+{
+        struct ath_atx_tid *tid;
+        struct ath_atx_ac *ac;
+        struct ath_txq *txq;
+        int tidno;
+
+        for (tidno = 0, tid = &an->tid[tidno];
+             tidno < WME_NUM_TID; tidno++, tid++) {
+
+                ac = tid->ac;
+                txq = ac->txq;
+
+                spin_lock_bh(&txq->axq_lock);
+                ac->clear_ps_filter = true;
+
+                if (!list_empty(&tid->buf_q) && !tid->paused) {
+                        ath_tx_queue_tid(txq, tid);
+                        ath_txq_schedule(sc, txq);
+                }
+
+                spin_unlock_bh(&txq->axq_lock);
         }
 }
 
@@ -862,20 +989,6 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
         }
 }
 
-bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
-{
-        struct ath_atx_tid *txtid;
-
-        if (!(sc->sc_flags & SC_OP_TXAGGR))
-                return false;
-
-        txtid = ATH_AN_2_TID(an, tidno);
-
-        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
-                        return true;
-        return false;
-}
-
 /********************/
 /* Queue Management */
 /********************/
@@ -902,10 +1015,16 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info qi;
-        int qnum, i;
+        static const int subtype_txq_to_hwq[] = {
+                [WME_AC_BE] = ATH_TXQ_AC_BE,
+                [WME_AC_BK] = ATH_TXQ_AC_BK,
+                [WME_AC_VI] = ATH_TXQ_AC_VI,
+                [WME_AC_VO] = ATH_TXQ_AC_VO,
+        };
+        int axq_qnum, i;
 
         memset(&qi, 0, sizeof(qi));
-        qi.tqi_subtype = subtype;
+        qi.tqi_subtype = subtype_txq_to_hwq[subtype];
         qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
         qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
         qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
@@ -936,40 +1055,40 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
                         qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
                                         TXQ_FLAG_TXDESCINT_ENABLE;
         }
-        qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
-        if (qnum == -1) {
+        axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
+        if (axq_qnum == -1) {
                 /*
                  * NB: don't print a message, this happens
                  * normally on parts with too few tx queues
                  */
                 return NULL;
         }
-        if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "qnum %u out of range, max %u!\n",
-                          qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
-                ath9k_hw_releasetxqueue(ah, qnum);
+        if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
+                ath_err(common, "qnum %u out of range, max %zu!\n",
+                        axq_qnum, ARRAY_SIZE(sc->tx.txq));
+                ath9k_hw_releasetxqueue(ah, axq_qnum);
                 return NULL;
         }
-        if (!ATH_TXQ_SETUP(sc, qnum)) {
-                struct ath_txq *txq = &sc->tx.txq[qnum];
+        if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
+                struct ath_txq *txq = &sc->tx.txq[axq_qnum];
 
-                txq->axq_class = subtype;
-                txq->axq_qnum = qnum;
+                txq->axq_qnum = axq_qnum;
+                txq->mac80211_qnum = -1;
                 txq->axq_link = NULL;
                 INIT_LIST_HEAD(&txq->axq_q);
                 INIT_LIST_HEAD(&txq->axq_acq);
                 spin_lock_init(&txq->axq_lock);
                 txq->axq_depth = 0;
+                txq->axq_ampdu_depth = 0;
                 txq->axq_tx_inprogress = false;
-                sc->tx.txqsetup |= 1<<qnum;
+                sc->tx.txqsetup |= 1<<axq_qnum;
 
                 txq->txq_headidx = txq->txq_tailidx = 0;
                 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
                         INIT_LIST_HEAD(&txq->txq_fifo[i]);
                 INIT_LIST_HEAD(&txq->txq_fifo_pending);
         }
-        return &sc->tx.txq[qnum];
+        return &sc->tx.txq[axq_qnum];
 }
 
 int ath_txq_update(struct ath_softc *sc, int qnum,
@@ -999,8 +1118,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
         qi.tqi_readyTime = qinfo->tqi_readyTime;
 
         if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to update hardware queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to update hardware queue %u!\n", qnum);
                 error = -EIO;
         } else {
                 ath9k_hw_resettxqueue(ah, qnum);
@@ -1012,6 +1131,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
 int ath_cabq_update(struct ath_softc *sc)
 {
         struct ath9k_tx_queue_info qi;
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         int qnum = sc->beacon.cabq->axq_qnum;
 
         ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
@@ -1023,13 +1143,19 @@ int ath_cabq_update(struct ath_softc *sc)
         else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
                 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
 
-        qi.tqi_readyTime = (sc->beacon_interval *
+        qi.tqi_readyTime = (cur_conf->beacon_interval *
                             sc->config.cabqReadytime) / 100;
         ath_txq_update(sc, qnum, &qi);
 
         return 0;
 }
 
+static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
+    return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
+}
+
 /*
  * Drain a given TX queue (could be Beacon or Data)
  *
@@ -1076,8 +1202,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
 
                 lastbf = bf->bf_lastbf;
-                if (!retry_tx)
-                        lastbf->bf_tx_aborted = true;
 
                 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                         list_cut_position(&bf_head,
@@ -1090,11 +1214,13 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
 
                 txq->axq_depth--;
-
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
+                                             retry_tx);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
         }
@@ -1103,15 +1229,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
         txq->axq_tx_inprogress = false;
         spin_unlock_bh(&txq->axq_lock);
 
-        /* flush any pending frames if aggregation is enabled */
-        if (sc->sc_flags & SC_OP_TXAGGR) {
-                if (!retry_tx) {
-                        spin_lock_bh(&txq->axq_lock);
-                        ath_txq_drain_pending_buffers(sc, txq);
-                        spin_unlock_bh(&txq->axq_lock);
-                }
-        }
-
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 spin_lock_bh(&txq->axq_lock);
                 while (!list_empty(&txq->txq_fifo_pending)) {
@@ -1124,7 +1241,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
 
                         if (bf_isampdu(bf))
                                 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
-                                                     &ts, 0);
+                                                     &ts, 0, retry_tx);
                         else
                                 ath_tx_complete_buf(sc, bf, txq, &bf_head,
                                                     &ts, 0, 0);
@@ -1132,9 +1249,18 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
                 spin_unlock_bh(&txq->axq_lock);
         }
+
+        /* flush any pending frames if aggregation is enabled */
+        if (sc->sc_flags & SC_OP_TXAGGR) {
+                if (!retry_tx) {
+                        spin_lock_bh(&txq->axq_lock);
+                        ath_txq_drain_pending_buffers(sc, txq);
+                        spin_unlock_bh(&txq->axq_lock);
+                }
+        }
 }
 
-void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
+bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -1142,39 +1268,36 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
         int i, npend = 0;
 
         if (sc->sc_flags & SC_OP_INVALID)
-                return;
+                return true;
 
-        /* Stop beacon queue */
-        ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
+        ath9k_hw_abort_tx_dma(ah);
 
-        /* Stop data queues */
+        /* Check if any queue remains active */
         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
-                if (ATH_TXQ_SETUP(sc, i)) {
-                        txq = &sc->tx.txq[i];
-                        ath9k_hw_stoptxdma(ah, txq->axq_qnum);
-                        npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
-                }
+                if (!ATH_TXQ_SETUP(sc, i))
+                        continue;
+
+                npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
         }
 
-        if (npend) {
-                int r;
+        if (npend)
+                ath_err(common, "Failed to stop TX DMA!\n");
 
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to stop TX DMA. Resetting hardware!\n");
+        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+                if (!ATH_TXQ_SETUP(sc, i))
+                        continue;
 
-                spin_lock_bh(&sc->sc_resetlock);
-                r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
-                if (r)
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to reset hardware; reset status %d\n",
-                                  r);
-                spin_unlock_bh(&sc->sc_resetlock);
+                /*
+                 * The caller will resume queues with ieee80211_wake_queues.
+                 * Mark the queue as not stopped to prevent ath_tx_complete
+                 * from waking the queue too early.
+                 */
+                txq = &sc->tx.txq[i];
+                txq->stopped = false;
+                ath_draintxq(sc, txq, retry_tx);
         }
 
-        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
-                if (ATH_TXQ_SETUP(sc, i))
-                        ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
-        }
+        return !npend;
 }
 
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
@@ -1183,65 +1306,60 @@ void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
         sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
 }
 
+/* For each axq_acq entry, for each tid, try to schedule packets
+ * for transmit until ampdu_depth has reached min Q depth.
+ */
 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
 {
-        struct ath_atx_ac *ac;
-        struct ath_atx_tid *tid;
+        struct ath_atx_ac *ac, *ac_tmp, *last_ac;
+        struct ath_atx_tid *tid, *last_tid;
 
-        if (list_empty(&txq->axq_acq))
+        if (list_empty(&txq->axq_acq) ||
+            txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
                 return;
 
         ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
-        list_del(&ac->list);
-        ac->sched = false;
-
-        do {
-                if (list_empty(&ac->tid_q))
-                        return;
+        last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
 
-                tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
-                list_del(&tid->list);
-                tid->sched = false;
+        list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
+                last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
+                list_del(&ac->list);
+                ac->sched = false;
 
-                if (tid->paused)
-                        continue;
+                while (!list_empty(&ac->tid_q)) {
+                        tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
+                                               list);
+                        list_del(&tid->list);
+                        tid->sched = false;
 
-                ath_tx_sched_aggr(sc, txq, tid);
+                        if (tid->paused)
+                                continue;
 
-                /*
-                 * add tid to round-robin queue if more frames
-                 * are pending for the tid
-                 */
-                if (!list_empty(&tid->buf_q))
-                        ath_tx_queue_tid(txq, tid);
+                        ath_tx_sched_aggr(sc, txq, tid);
 
-                break;
-        } while (!list_empty(&ac->tid_q));
+                        /*
+                         * add tid to round-robin queue if more frames
+                         * are pending for the tid
+                         */
+                        if (!list_empty(&tid->buf_q))
+                                ath_tx_queue_tid(txq, tid);
 
-        if (!list_empty(&ac->tid_q)) {
-                if (!ac->sched) {
-                        ac->sched = true;
-                        list_add_tail(&ac->list, &txq->axq_acq);
+                        if (tid == last_tid ||
+                            txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
+                                break;
                 }
-        }
-}
 
-int ath_tx_setup(struct ath_softc *sc, int haltype)
-{
-        struct ath_txq *txq;
+                if (!list_empty(&ac->tid_q)) {
+                        if (!ac->sched) {
+                                ac->sched = true;
+                                list_add_tail(&ac->list, &txq->axq_acq);
+                        }
+                }
 
-        if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "HAL AC %u out of range, max %zu!\n",
-                         haltype, ARRAY_SIZE(sc->tx.hwq_map));
-                return 0;
+                if (ac == last_ac ||
+                    txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
+                        return;
         }
-        txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
-        if (txq != NULL) {
-                sc->tx.hwq_map[haltype] = txq->axq_qnum;
-                return 1;
-        } else
-                return 0;
 }
 
 /***********/
@@ -1269,8 +1387,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
 
         bf = list_first_entry(head, struct ath_buf, list);
 
-        ath_print(common, ATH_DBG_QUEUE,
-                  "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
+        ath_dbg(common, ATH_DBG_QUEUE,
+                "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
@@ -1278,49 +1396,49 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                         return;
                 }
                 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "Initializing tx fifo %d which "
-                                  "is non-empty\n",
-                                  txq->txq_headidx);
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Initializing tx fifo %d which is non-empty\n",
+                                txq->txq_headidx);
                 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
                 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
                 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
+                TX_STAT_INC(txq->axq_qnum, puttxbuf);
                 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-                ath_print(common, ATH_DBG_XMIT,
-                          "TXDP[%u] = %llx (%p)\n",
-                          txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
+                ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
+                        txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
         } else {
                 list_splice_tail_init(head, &txq->axq_q);
 
                 if (txq->axq_link == NULL) {
+                        TX_STAT_INC(txq->axq_qnum, puttxbuf);
                         ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-                        ath_print(common, ATH_DBG_XMIT,
-                                        "TXDP[%u] = %llx (%p)\n",
-                                        txq->axq_qnum, ito64(bf->bf_daddr),
-                                        bf->bf_desc);
+                        ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
+                                txq->axq_qnum, ito64(bf->bf_daddr),
+                                bf->bf_desc);
                 } else {
                         *txq->axq_link = bf->bf_daddr;
-                        ath_print(common, ATH_DBG_XMIT,
-                                        "link[%u] (%p)=%llx (%p)\n",
-                                        txq->axq_qnum, txq->axq_link,
-                                        ito64(bf->bf_daddr), bf->bf_desc);
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "link[%u] (%p)=%llx (%p)\n",
+                                txq->axq_qnum, txq->axq_link,
+                                ito64(bf->bf_daddr), bf->bf_desc);
                 }
                 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
                                        &txq->axq_link);
+                TX_STAT_INC(txq->axq_qnum, txstart);
                 ath9k_hw_txstart(ah, txq->axq_qnum);
         }
         txq->axq_depth++;
+        if (bf_is_ampdu_not_probing(bf))
+                txq->axq_ampdu_depth++;
 }
 
 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
-                              struct list_head *bf_head,
-                              struct ath_tx_control *txctl)
+                              struct ath_buf *bf, struct ath_tx_control *txctl)
 {
-        struct ath_buf *bf;
+        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
+        struct list_head bf_head;
 
-        bf = list_first_entry(bf_head, struct ath_buf, list);
         bf->bf_state.bf_type |= BUF_AMPDU;
-        TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
 
         /*
          * Do not queue to h/w when any of the following conditions is true:
@@ -1330,56 +1448,49 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
          * - h/w queue depth exceeds low water mark
          */
         if (!list_empty(&tid->buf_q) || tid->paused ||
-            !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
-            txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
+            !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
+            txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
                 /*
                  * Add this frame to software queue for scheduling later
                  * for aggregation.
                  */
-                list_move_tail(&bf->list, &tid->buf_q);
+                TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
+                list_add_tail(&bf->list, &tid->buf_q);
                 ath_tx_queue_tid(txctl->txq, tid);
                 return;
         }
 
+        INIT_LIST_HEAD(&bf_head);
+        list_add(&bf->list, &bf_head);
+
         /* Add sub-frame to BAW */
-        ath_tx_addto_baw(sc, tid, bf);
+        if (!fi->retries)
+                ath_tx_addto_baw(sc, tid, fi->seqno);
 
         /* Queue to h/w without aggregation */
-        bf->bf_nframes = 1;
+        TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
         bf->bf_lastbf = bf;
-        ath_buf_set_rate(sc, bf);
-        ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
+        ath_buf_set_rate(sc, bf, fi->framelen);
+        ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
 }
 
-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
-                                  struct ath_atx_tid *tid,
-                                  struct list_head *bf_head)
+static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+                               struct ath_atx_tid *tid,
+                               struct list_head *bf_head)
 {
+        struct ath_frame_info *fi;
         struct ath_buf *bf;
 
         bf = list_first_entry(bf_head, struct ath_buf, list);
         bf->bf_state.bf_type &= ~BUF_AMPDU;
 
         /* update starting sequence number for subsequent ADDBA request */
-        INCR(tid->seq_start, IEEE80211_SEQ_MAX);
-
-        bf->bf_nframes = 1;
-        bf->bf_lastbf = bf;
-        ath_buf_set_rate(sc, bf);
-        ath_tx_txqaddbuf(sc, txq, bf_head);
-        TX_STAT_INC(txq->axq_qnum, queued);
-}
-
-static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
-                               struct list_head *bf_head)
-{
-        struct ath_buf *bf;
-
-        bf = list_first_entry(bf_head, struct ath_buf, list);
+        if (tid)
+                INCR(tid->seq_start, IEEE80211_SEQ_MAX);
 
         bf->bf_lastbf = bf;
-        bf->bf_nframes = 1;
-        ath_buf_set_rate(sc, bf);
+        fi = get_frame_info(bf->bf_mpdu);
+        ath_buf_set_rate(sc, bf, fi->framelen);
         ath_tx_txqaddbuf(sc, txq, bf_head);
         TX_STAT_INC(txq->axq_qnum, queued);
 }
@@ -1407,67 +1518,65 @@ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
         return htype;
 }
 
-static int get_hw_crypto_keytype(struct sk_buff *skb)
-{
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-
-        if (tx_info->control.hw_key) {
-                if (tx_info->control.hw_key->alg == ALG_WEP)
-                        return ATH9K_KEY_TYPE_WEP;
-                else if (tx_info->control.hw_key->alg == ALG_TKIP)
-                        return ATH9K_KEY_TYPE_TKIP;
-                else if (tx_info->control.hw_key->alg == ALG_CCMP)
-                        return ATH9K_KEY_TYPE_AES;
-        }
-
-        return ATH9K_KEY_TYPE_CLEAR;
-}
-
-static void assign_aggr_tid_seqno(struct sk_buff *skb,
-                                  struct ath_buf *bf)
+static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
+                             int framelen)
 {
+        struct ath_softc *sc = hw->priv;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_sta *sta = tx_info->control.sta;
+        struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
         struct ieee80211_hdr *hdr;
-        struct ath_node *an;
+        struct ath_frame_info *fi = get_frame_info(skb);
+        struct ath_node *an = NULL;
         struct ath_atx_tid *tid;
-        __le16 fc;
-        u8 *qc;
+        enum ath9k_key_type keytype;
+        u16 seqno = 0;
+        u8 tidno;
 
-        if (!tx_info->control.sta)
-                return;
+        keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
+
+        if (sta)
+                an = (struct ath_node *) sta->drv_priv;
 
-        an = (struct ath_node *)tx_info->control.sta->drv_priv;
         hdr = (struct ieee80211_hdr *)skb->data;
-        fc = hdr->frame_control;
+        if (an && ieee80211_is_data_qos(hdr->frame_control) &&
+                conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
 
-        if (ieee80211_is_data_qos(fc)) {
-                qc = ieee80211_get_qos_ctl(hdr);
-                bf->bf_tidno = qc[0] & 0xf;
+                tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+
+                /*
+                 * Override seqno set by upper layer with the one
+                 * in tx aggregation state.
+                 */
+                tid = ATH_AN_2_TID(an, tidno);
+                seqno = tid->seq_next;
+                hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
+                INCR(tid->seq_next, IEEE80211_SEQ_MAX);
         }
 
-        /*
-         * For HT capable stations, we save tidno for later use.
-         * We also override seqno set by upper layer with the one
-         * in tx aggregation state.
-         */
-        tid = ATH_AN_2_TID(an, bf->bf_tidno);
-        hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
-        bf->bf_seqno = tid->seq_next;
-        INCR(tid->seq_next, IEEE80211_SEQ_MAX);
+        memset(fi, 0, sizeof(*fi));
+        if (hw_key)
+                fi->keyix = hw_key->hw_key_idx;
+        else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
+                fi->keyix = an->ps_key;
+        else
+                fi->keyix = ATH9K_TXKEYIX_INVALID;
+        fi->keytype = keytype;
+        fi->framelen = framelen;
+        fi->seqno = seqno;
 }
 
-static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
+static int setup_tx_flags(struct sk_buff *skb)
 {
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         int flags = 0;
 
-        flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
         flags |= ATH9K_TXDESC_INTREQ;
 
         if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
                 flags |= ATH9K_TXDESC_NOACK;
 
-        if (use_ldpc)
+        if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
                 flags |= ATH9K_TXDESC_LDPC;
 
         return flags;
@@ -1479,13 +1588,11 @@ static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
  * width  - 0 for 20 MHz, 1 for 40 MHz
  * half_gi - to use 4us v/s 3.6 us for symbol time
  */
-static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
+static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
                             int width, int half_gi, bool shortPreamble)
 {
         u32 nbits, nsymbits, duration, nsymbols;
-        int streams, pktlen;
-
-        pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
+        int streams;
 
         /* find number of symbols: PLCP + data */
         streams = HT_RC_2_STREAMS(rix);
@@ -1504,7 +1611,19 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
         return duration;
 }
 
-static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
+u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *curchan = ah->curchan;
+        if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
+                        (curchan->channelFlags & CHANNEL_5GHZ) &&
+                        (chainmask == 0x7) && (rate < 0x90))
+                return 0x3;
+        else
+                return chainmask;
+}
+
+static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath9k_11n_rate_series series[4];
@@ -1544,10 +1663,8 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 
                 rix = rates[i].idx;
                 series[i].Tries = rates[i].count;
-                series[i].ChSel = common->tx_chainmask;
 
-                if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
-                    (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
+                    if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
                         series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
                         flags |= ATH9K_TXDESC_RTSENA;
                 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
@@ -1567,14 +1684,16 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
                         /* MCS rates */
                         series[i].Rate = rix | 0x80;
-                        series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
+                        series[i].ChSel = ath_txchainmask_reduction(sc,
+                                        common->tx_chainmask, series[i].Rate);
+                        series[i].PktDuration = ath_pkt_duration(sc, rix, len,
                                  is_40, is_sgi, is_sp);
                         if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
                                 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
                         continue;
                 }
 
-                /* legcay rates */
+                /* legacy rates */
                 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
                     !(rate->flags & IEEE80211_RATE_ERP_G))
                         phy = WLAN_RC_PHY_CCK;
@@ -1590,12 +1709,18 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                         is_sp = false;
                 }
 
+                if (bf->bf_state.bfs_paprd)
+                        series[i].ChSel = common->tx_chainmask;
+                else
+                        series[i].ChSel = ath_txchainmask_reduction(sc,
+                                        common->tx_chainmask, series[i].Rate);
+
                 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
-                        phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
+                        phy, rate->bitrate * 100, len, rix, is_sp);
         }
 
         /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
-        if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
+        if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
                 flags &= ~ATH9K_TXDESC_RTSENA;
 
         /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
@@ -1608,122 +1733,49 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                                      !is_pspoll, ctsrate,
                                      0, series, 4, flags);
 
-        if (sc->config.ath_aggr_prot && flags)
-                ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
 }
 
-static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
-                                struct sk_buff *skb,
-                                struct ath_tx_control *txctl)
+static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
+                                           struct ath_txq *txq,
+                                           struct sk_buff *skb)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-        int hdrlen;
-        __le16 fc;
-        int padpos, padsize;
-        bool use_ldpc = false;
-
-        tx_info->pad[0] = 0;
-        switch (txctl->frame_type) {
-        case ATH9K_IFT_NOT_INTERNAL:
-                break;
-        case ATH9K_IFT_PAUSE:
-                tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
-                /* fall through */
-        case ATH9K_IFT_UNPAUSE:
-                tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
-                break;
-        }
-        hdrlen = ieee80211_get_hdrlen_from_skb(skb);
-        fc = hdr->frame_control;
-
-        ATH_TXBUF_RESET(bf);
-
-        bf->aphy = aphy;
-        bf->bf_frmlen = skb->len + FCS_LEN;
-        /* Remove the padding size from bf_frmlen, if any */
-        padpos = ath9k_cmn_padpos(hdr->frame_control);
-        padsize = padpos & 3;
-        if (padsize && skb->len>padpos+padsize) {
-                bf->bf_frmlen -= padsize;
-        }
-
-        if (!txctl->paprd && conf_is_ht(&hw->conf)) {
-                bf->bf_state.bf_type |= BUF_HT;
-                if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
-                        use_ldpc = true;
-        }
-
-        bf->bf_state.bfs_paprd = txctl->paprd;
-        if (txctl->paprd)
-                bf->bf_state.bfs_paprd_timestamp = jiffies;
-        bf->bf_flags = setup_tx_flags(skb, use_ldpc);
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_frame_info *fi = get_frame_info(skb);
+        struct ath_buf *bf;
+        struct ath_desc *ds;
+        int frm_type;
 
-        bf->bf_keytype = get_hw_crypto_keytype(skb);
-        if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
-                bf->bf_frmlen += tx_info->control.hw_key->icv_len;
-                bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
-        } else {
-                bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
+        bf = ath_tx_get_buffer(sc);
+        if (!bf) {
+                ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
+                return NULL;
         }
 
-        if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
-            (sc->sc_flags & SC_OP_TXAGGR))
-                assign_aggr_tid_seqno(skb, bf);
+        ATH_TXBUF_RESET(bf);
 
+        bf->bf_flags = setup_tx_flags(skb);
         bf->bf_mpdu = skb;
 
-        bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
-                                           skb->len, DMA_TO_DEVICE);
-        if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
+        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+                                         skb->len, DMA_TO_DEVICE);
+        if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 bf->bf_mpdu = NULL;
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "dma_mapping_error() on TX\n");
-                return -ENOMEM;
+                bf->bf_buf_addr = 0;
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "dma_mapping_error() on TX\n");
+                ath_tx_return_buffer(sc, bf);
+                return NULL;
         }
 
-        bf->bf_buf_addr = bf->bf_dmacontext;
-
-        /* tag if this is a nullfunc frame to enable PS when AP acks it */
-        if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
-                bf->bf_isnullfunc = true;
-                sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
-        } else
-                bf->bf_isnullfunc = false;
-
-        bf->bf_tx_aborted = false;
-
-        return 0;
-}
-
-/* FIXME: tx power */
-static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
-                             struct ath_tx_control *txctl)
-{
-        struct sk_buff *skb = bf->bf_mpdu;
-        struct ieee80211_tx_info *tx_info =  IEEE80211_SKB_CB(skb);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-        struct ath_node *an = NULL;
-        struct list_head bf_head;
-        struct ath_desc *ds;
-        struct ath_atx_tid *tid;
-        struct ath_hw *ah = sc->sc_ah;
-        int frm_type;
-        __le16 fc;
-
         frm_type = get_hw_packet_type(skb);
-        fc = hdr->frame_control;
-
-        INIT_LIST_HEAD(&bf_head);
-        list_add_tail(&bf->list, &bf_head);
 
         ds = bf->bf_desc;
         ath9k_hw_set_desc_link(ah, ds, 0);
 
-        ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
-                               bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
+        ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
+                               fi->keyix, fi->keytype, bf->bf_flags);
 
         ath9k_hw_filltxdesc(ah, ds,
                             skb->len,   /* segment length */
@@ -1731,109 +1783,83 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
                             true,       /* last segment */
                             ds,         /* first descriptor */
                             bf->bf_buf_addr,
-                            txctl->txq->axq_qnum);
-
-        if (bf->bf_state.bfs_paprd)
-                ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
-
-        spin_lock_bh(&txctl->txq->axq_lock);
-
-        if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
-            tx_info->control.sta) {
-                an = (struct ath_node *)tx_info->control.sta->drv_priv;
-                tid = ATH_AN_2_TID(an, bf->bf_tidno);
-
-                if (!ieee80211_is_data_qos(fc)) {
-                        ath_tx_send_normal(sc, txctl->txq, &bf_head);
-                        goto tx_done;
-                }
+                            txq->axq_qnum);
 
-                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
-                        /*
-                         * Try aggregation if it's a unicast data frame
-                         * and the destination is HT capable.
-                         */
-                        ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
-                } else {
-                        /*
-                         * Send this frame as regular when ADDBA
-                         * exchange is neither complete nor pending.
-                         */
-                        ath_tx_send_ht_normal(sc, txctl->txq,
-                                              tid, &bf_head);
-                }
-        } else {
-                ath_tx_send_normal(sc, txctl->txq, &bf_head);
-        }
 
-tx_done:
-        spin_unlock_bh(&txctl->txq->axq_lock);
+        return bf;
 }
 
-/* Upon failure caller should free skb */
-int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
-                 struct ath_tx_control *txctl)
+/* FIXME: tx power */
+static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_control *txctl)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_txq *txq = txctl->txq;
-        struct ath_buf *bf;
-        int q, r;
+        struct sk_buff *skb = bf->bf_mpdu;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+        struct list_head bf_head;
+        struct ath_atx_tid *tid = NULL;
+        u8 tidno;
 
-        bf = ath_tx_get_buffer(sc);
-        if (!bf) {
-                ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
-                return -1;
+        spin_lock_bh(&txctl->txq->axq_lock);
+        if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
+                ieee80211_is_data_qos(hdr->frame_control)) {
+                tidno = ieee80211_get_qos_ctl(hdr)[0] &
+                        IEEE80211_QOS_CTL_TID_MASK;
+                tid = ATH_AN_2_TID(txctl->an, tidno);
+
+                WARN_ON(tid->ac->txq != txctl->txq);
         }
 
-        r = ath_tx_setup_buffer(hw, bf, skb, txctl);
-        if (unlikely(r)) {
-                ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
+        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
+                /*
+                 * Try aggregation if it's a unicast data frame
+                 * and the destination is HT capable.
+                 */
+                ath_tx_send_ampdu(sc, tid, bf, txctl);
+        } else {
+                INIT_LIST_HEAD(&bf_head);
+                list_add_tail(&bf->list, &bf_head);
 
-                /* upon ath_tx_processq() this TX queue will be resumed, we
-                 * guarantee this will happen by knowing beforehand that
-                 * we will at least have to run TX completionon one buffer
-                 * on the queue */
-                spin_lock_bh(&txq->axq_lock);
-                if (!txq->stopped && txq->axq_depth > 1) {
-                        ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-                        txq->stopped = 1;
-                }
-                spin_unlock_bh(&txq->axq_lock);
+                bf->bf_state.bfs_ftype = txctl->frame_type;
+                bf->bf_state.bfs_paprd = txctl->paprd;
 
-                ath_tx_return_buffer(sc, bf);
+                if (bf->bf_state.bfs_paprd)
+                        ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
+                                                   bf->bf_state.bfs_paprd);
 
-                return r;
-        }
+                if (txctl->paprd)
+                        bf->bf_state.bfs_paprd_timestamp = jiffies;
 
-        q = skb_get_queue_mapping(skb);
-        if (q >= 4)
-                q = 0;
+                if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
+                        ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
 
-        spin_lock_bh(&txq->axq_lock);
-        if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
-                ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-                txq->stopped = 1;
+                ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
         }
-        spin_unlock_bh(&txq->axq_lock);
 
-        ath_tx_start_dma(sc, bf, txctl);
-
-        return 0;
+        spin_unlock_bh(&txctl->txq->axq_lock);
 }
 
-void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
+/* Upon failure caller should free skb */
+int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+                 struct ath_tx_control *txctl)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
-        int padpos, padsize;
         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-        struct ath_tx_control txctl;
+        struct ieee80211_sta *sta = info->control.sta;
+        struct ieee80211_vif *vif = info->control.vif;
+        struct ath_softc *sc = hw->priv;
+        struct ath_txq *txq = txctl->txq;
+        struct ath_buf *bf;
+        int padpos, padsize;
+        int frmlen = skb->len + FCS_LEN;
+        int q;
 
-        memset(&txctl, 0, sizeof(struct ath_tx_control));
+        /* NOTE:  sta can be NULL according to net/mac80211.h */
+        if (sta)
+                txctl->an = (struct ath_node *)sta->drv_priv;
+
+        if (info->control.hw_key)
+                frmlen += info->control.hw_key->icv_len;
 
         /*
          * As a temporary workaround, assign seq# here; this will likely need
@@ -1850,30 +1876,42 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
         /* Add the padding after the header if this is not already done */
         padpos = ath9k_cmn_padpos(hdr->frame_control);
         padsize = padpos & 3;
-        if (padsize && skb->len>padpos) {
-                if (skb_headroom(skb) < padsize) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "TX CABQ padding failed\n");
-                        dev_kfree_skb_any(skb);
-                        return;
-                }
+        if (padsize && skb->len > padpos) {
+                if (skb_headroom(skb) < padsize)
+                        return -ENOMEM;
+
                 skb_push(skb, padsize);
                 memmove(skb->data, skb->data + padsize, padpos);
         }
 
-        txctl.txq = sc->beacon.cabq;
+        if ((vif && vif->type != NL80211_IFTYPE_AP &&
+                    vif->type != NL80211_IFTYPE_AP_VLAN) ||
+            !ieee80211_is_data(hdr->frame_control))
+                info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
 
-        ath_print(common, ATH_DBG_XMIT,
-                  "transmitting CABQ packet, skb: %p\n", skb);
+        setup_frame_info(hw, skb, frmlen);
 
-        if (ath_tx_start(hw, skb, &txctl) != 0) {
-                ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
-                goto exit;
+        /*
+         * At this point, the vif, hw_key and sta pointers in the tx control
+         * info are no longer valid (overwritten by the ath_frame_info data.
+         */
+
+        bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
+        if (unlikely(!bf))
+                return -ENOMEM;
+
+        q = skb_get_queue_mapping(skb);
+        spin_lock_bh(&txq->axq_lock);
+        if (txq == sc->tx.txq_map[q] &&
+            ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
+                ieee80211_stop_queue(sc->hw, q);
+                txq->stopped = 1;
         }
+        spin_unlock_bh(&txq->axq_lock);
+
+        ath_tx_start_dma(sc, bf, txctl);
 
-        return;
-exit:
-        dev_kfree_skb_any(skb);
+        return 0;
 }
 
 /*****************/
@@ -1881,7 +1919,7 @@ exit:
 /*****************/
 
 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
-                            struct ath_wiphy *aphy, int tx_flags)
+                            int tx_flags, int ftype, struct ath_txq *txq)
 {
         struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -1889,10 +1927,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
         struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
         int q, padpos, padsize;
 
-        ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
-
-        if (aphy)
-                hw = aphy->hw;
+        ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
 
         if (tx_flags & ATH_TX_BAR)
                 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
@@ -1915,27 +1950,28 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
         if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
                 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
-                ath_print(common, ATH_DBG_PS,
-                          "Going back to sleep after having "
-                          "received TX status (0x%lx)\n",
+                ath_dbg(common, ATH_DBG_PS,
+                        "Going back to sleep after having received TX status (0x%lx)\n",
                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                         PS_WAIT_FOR_CAB |
                                         PS_WAIT_FOR_PSPOLL_DATA |
                                         PS_WAIT_FOR_TX_ACK));
         }
 
-        if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
-                ath9k_tx_status(hw, skb);
-        else {
-                q = skb_get_queue_mapping(skb);
-                if (q >= 4)
-                        q = 0;
-
-                if (--sc->tx.pending_frames[q] < 0)
-                        sc->tx.pending_frames[q] = 0;
+        q = skb_get_queue_mapping(skb);
+        if (txq == sc->tx.txq_map[q]) {
+                spin_lock_bh(&txq->axq_lock);
+                if (WARN_ON(--txq->pending_frames < 0))
+                        txq->pending_frames = 0;
 
-                ieee80211_tx_status(hw, skb);
+                if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
+                        ieee80211_wake_queue(sc->hw, q);
+                        txq->stopped = 0;
+                }
+                spin_unlock_bh(&txq->axq_lock);
         }
+
+        ieee80211_tx_status(hw, skb);
 }
 
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
@@ -1956,19 +1992,25 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                         tx_flags |= ATH_TX_XRETRY;
         }
 
-        dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
+        dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
+        bf->bf_buf_addr = 0;
 
         if (bf->bf_state.bfs_paprd) {
                 if (time_after(jiffies,
-                               bf->bf_state.bfs_paprd_timestamp +
-                               msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
+                                bf->bf_state.bfs_paprd_timestamp +
+                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
                         dev_kfree_skb_any(skb);
                 else
                         complete(&sc->paprd_complete);
         } else {
-                ath_tx_complete(sc, skb, bf->aphy, tx_flags);
-                ath_debug_stat_tx(sc, txq, bf, ts);
+                ath_debug_stat_tx(sc, bf, ts, txq);
+                ath_tx_complete(sc, skb, tx_flags,
+                                bf->bf_state.bfs_ftype, txq);
         }
+        /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
+         * accidentally reference it later.
+         */
+        bf->bf_mpdu = NULL;
 
         /*
          * Return the list of ath_buf of this mpdu to free queue
@@ -1978,42 +2020,15 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
         spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
 }
 
-static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
-                              struct ath_tx_status *ts, int txok)
-{
-        u16 seq_st = 0;
-        u32 ba[WME_BA_BMP_SIZE >> 5];
-        int ba_index;
-        int nbad = 0;
-        int isaggr = 0;
-
-        if (bf->bf_lastbf->bf_tx_aborted)
-                return 0;
-
-        isaggr = bf_isaggr(bf);
-        if (isaggr) {
-                seq_st = ts->ts_seqnum;
-                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
-        }
-
-        while (bf) {
-                ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
-                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
-                        nbad++;
-
-                bf = bf->bf_next;
-        }
-
-        return nbad;
-}
-
-static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
-                             int nbad, int txok, bool update_rc)
+static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_status *ts, int nframes, int nbad,
+                             int txok, bool update_rc)
 {
         struct sk_buff *skb = bf->bf_mpdu;
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-        struct ieee80211_hw *hw = bf->aphy->hw;
+        struct ieee80211_hw *hw = sc->hw;
+        struct ath_hw *ah = sc->sc_ah;
         u8 i, tx_rateindex;
 
         if (txok)
@@ -2024,21 +2039,35 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
 
         if (ts->ts_status & ATH9K_TXERR_FILT)
                 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
-        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
+        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
                 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
 
+                BUG_ON(nbad > nframes);
+
+                tx_info->status.ampdu_len = nframes;
+                tx_info->status.ampdu_ack_len = nframes - nbad;
+        }
+
         if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
             (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
-                if (ieee80211_is_data(hdr->frame_control)) {
-                        if (ts->ts_flags &
-                            (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
-                                tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
-                        if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
-                            (ts->ts_status & ATH9K_TXERR_FIFO))
-                                tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
-                        tx_info->status.ampdu_len = bf->bf_nframes;
-                        tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
-                }
+                /*
+                 * If an underrun error is seen assume it as an excessive
+                 * retry only if max frame trigger level has been reached
+                 * (2 KB for single stream, and 4 KB for dual stream).
+                 * Adjust the long retry as if the frame was tried
+                 * hw->max_rate_tries times to affect how rate control updates
+                 * PER for the failed rate.
+                 * In case of congestion on the bus penalizing this type of
+                 * underruns should help hardware actually transmit new frames
+                 * successfully by eventually preferring slower rates.
+                 * This itself should also alleviate congestion on the bus.
+                 */
+                if (ieee80211_is_data(hdr->frame_control) &&
+                    (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
+                                     ATH9K_TX_DELIM_UNDERRUN)) &&
+                    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
+                        tx_info->status.rates[tx_rateindex].count =
+                                hw->max_rate_tries;
         }
 
         for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
@@ -2049,22 +2078,6 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
         tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
 }
 
-static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
-{
-        int qnum;
-
-        qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
-        if (qnum == -1)
-                return;
-
-        spin_lock_bh(&txq->axq_lock);
-        if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
-                if (ath_mac80211_start_queue(sc, qnum))
-                        txq->stopped = 0;
-        }
-        spin_unlock_bh(&txq->axq_lock);
-}
-
 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 {
         struct ath_hw *ah = sc->sc_ah;
@@ -2076,14 +2089,16 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
         int txok;
         int status;
 
-        ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
-                  txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
-                  txq->axq_link);
+        ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
+                txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
+                txq->axq_link);
 
         for (;;) {
                 spin_lock_bh(&txq->axq_lock);
                 if (list_empty(&txq->axq_q)) {
                         txq->axq_link = NULL;
+                        if (sc->sc_flags & SC_OP_TXAGGR)
+                                ath_txq_schedule(sc, txq);
                         spin_unlock_bh(&txq->axq_lock);
                         break;
                 }
@@ -2118,18 +2133,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                         spin_unlock_bh(&txq->axq_lock);
                         break;
                 }
-
-                /*
-                 * We now know the nullfunc frame has been ACKed so we
-                 * can disable RX.
-                 */
-                if (bf->bf_isnullfunc &&
-                    (ts.ts_status & ATH9K_TX_ACKED)) {
-                        if ((sc->ps_flags & PS_ENABLED))
-                                ath9k_enable_ps(sc);
-                        else
-                                sc->ps_flags |= PS_NULLFUNC_COMPLETED;
-                }
+                TX_STAT_INC(txq->axq_qnum, txprocdesc);
 
                 /*
                  * Remove ath_buf's of the same transmit unit from txq,
@@ -2147,6 +2151,10 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                 txq->axq_tx_inprogress = false;
                 if (bf_held)
                         list_del(&bf_held->list);
+
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
+
                 spin_unlock_bh(&txq->axq_lock);
 
                 if (bf_held)
@@ -2159,17 +2167,17 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                          */
                         if (ts.ts_status & ATH9K_TXERR_XRETRY)
                                 bf->bf_state.bf_type |= BUF_XRETRY;
-                        ath_tx_rc_status(bf, &ts, 0, txok, true);
+                        ath_tx_rc_status(sc, bf, &ts, 1, txok ? 0 : 1, txok, true);
                 }
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
+                                             true);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
 
-                ath_wake_mac80211_queue(sc, txq);
-
                 spin_lock_bh(&txq->axq_lock);
+
                 if (sc->sc_flags & SC_OP_TXAGGR)
                         ath_txq_schedule(sc, txq);
                 spin_unlock_bh(&txq->axq_lock);
@@ -2183,6 +2191,9 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
         struct ath_txq *txq;
         int i;
         bool needreset = false;
+#ifdef CONFIG_ATH9K_DEBUGFS
+        sc->tx_complete_poll_work_seen++;
+#endif
 
         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
                 if (ATH_TXQ_SETUP(sc, i)) {
@@ -2201,11 +2212,9 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
                 }
 
         if (needreset) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
-                          "tx hung, resetting the chip\n");
-                ath9k_ps_wakeup(sc);
-                ath_reset(sc, false);
-                ath9k_ps_restore(sc);
+                ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
+                        "tx hung, resetting the chip\n");
+                ath_reset(sc, true);
         }
 
         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2243,8 +2252,8 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
                 if (status == -EINPROGRESS)
                         break;
                 if (status == -EIO) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "Error processing tx status\n");
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Error processing tx status\n");
                         break;
                 }
 
@@ -2270,45 +2279,38 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
                 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
                 txq->axq_depth--;
                 txq->axq_tx_inprogress = false;
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
 
-                /*
-                 * Make sure null func frame is acked before configuring
-                 * hw into ps mode.
-                 */
-                if (bf->bf_isnullfunc && txok) {
-                        if ((sc->ps_flags & PS_ENABLED))
-                                ath9k_enable_ps(sc);
-                        else
-                                sc->ps_flags |= PS_NULLFUNC_COMPLETED;
-                }
-
                 if (!bf_isampdu(bf)) {
                         if (txs.ts_status & ATH9K_TXERR_XRETRY)
                                 bf->bf_state.bf_type |= BUF_XRETRY;
-                        ath_tx_rc_status(bf, &txs, 0, txok, true);
+                        ath_tx_rc_status(sc, bf, &txs, 1, txok ? 0 : 1, txok, true);
                 }
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
+                                             txok, true);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head,
                                             &txs, txok, 0);
 
-                ath_wake_mac80211_queue(sc, txq);
-
                 spin_lock_bh(&txq->axq_lock);
+
                 if (!list_empty(&txq->txq_fifo_pending)) {
                         INIT_LIST_HEAD(&bf_head);
                         bf = list_first_entry(&txq->txq_fifo_pending,
-                                struct ath_buf, list);
-                        list_cut_position(&bf_head, &txq->txq_fifo_pending,
-                                &bf->bf_lastbf->list);
+                                              struct ath_buf, list);
+                        list_cut_position(&bf_head,
+                                          &txq->txq_fifo_pending,
+                                          &bf->bf_lastbf->list);
                         ath_tx_txqaddbuf(sc, txq, &bf_head);
                 } else if (sc->sc_flags & SC_OP_TXAGGR)
                         ath_txq_schedule(sc, txq);
+
                 spin_unlock_bh(&txq->axq_lock);
         }
 }
@@ -2362,16 +2364,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
         error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
                                   "tx", nbufs, 1, 1);
         if (error != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to allocate tx descriptors: %d\n", error);
+                ath_err(common,
+                        "Failed to allocate tx descriptors: %d\n", error);
                 goto err;
         }
 
         error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
                                   "beacon", ATH_BCBUF, 1, 1);
         if (error != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to allocate beacon descriptors: %d\n", error);
+                ath_err(common,
+                        "Failed to allocate beacon descriptors: %d\n", error);
                 goto err;
         }
 
@@ -2429,7 +2431,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
         for (acno = 0, ac = &an->ac[acno];
              acno < WME_NUM_AC; acno++, ac++) {
                 ac->sched    = false;
-                ac->qnum = sc->tx.hwq_map[acno];
+                ac->txq = sc->tx.txq_map[acno];
                 INIT_LIST_HEAD(&ac->tid_q);
         }
 }
@@ -2439,17 +2441,13 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
         struct ath_atx_ac *ac;
         struct ath_atx_tid *tid;
         struct ath_txq *txq;
-        int i, tidno;
+        int tidno;
 
         for (tidno = 0, tid = &an->tid[tidno];
              tidno < WME_NUM_TID; tidno++, tid++) {
-                i = tid->ac->qnum;
 
-                if (!ATH_TXQ_SETUP(sc, i))
-                        continue;
-
-                txq = &sc->tx.txq[i];
                 ac = tid->ac;
+                txq = ac->txq;
 
                 spin_lock_bh(&txq->axq_lock);
 
diff --git a/drivers/net/wireless/ath/carl9170/Kconfig b/drivers/net/wireless/ath/carl9170/Kconfig
new file mode 100644
index 000000000000..2d1b821b440d
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/Kconfig
@@ -0,0 +1,41 @@
+config CARL9170
+        tristate "Linux Community AR9170 802.11n USB support"
+        depends on USB && MAC80211 && EXPERIMENTAL
+        select FW_LOADER
+        select CRC32
+        help
+          This is another driver for the Atheros "otus" 802.11n USB devices.
+
+          This driver provides more features than the original,
+          but it needs a special firmware (carl9170-1.fw) to do that.
+
+          The firmware can be downloaded from our wiki here:
+          <http://wireless.kernel.org/en/users/Drivers/carl9170>
+
+          If you choose to build a module, it'll be called carl9170.
+
+config CARL9170_LEDS
+        bool "SoftLED Support"
+        depends on CARL9170
+        select MAC80211_LEDS
+        select LEDS_CLASS
+        select NEW_LEDS
+        default y
+        help
+          This option is necessary, if you want your device' LEDs to blink
+
+          Say Y, unless you need the LEDs for firmware debugging.
+
+config CARL9170_DEBUGFS
+        bool "DebugFS Support"
+        depends on CARL9170 && DEBUG_FS && MAC80211_DEBUGFS
+        default n
+        help
+          Export several driver and device internals to user space.
+
+          Say N.
+
+config CARL9170_WPC
+        bool
+        depends on CARL9170 && (INPUT = y || INPUT = CARL9170)
+        default y
diff --git a/drivers/net/wireless/ath/carl9170/Makefile b/drivers/net/wireless/ath/carl9170/Makefile
new file mode 100644
index 000000000000..f64ed76af8ad
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/Makefile
@@ -0,0 +1,4 @@
+carl9170-objs := main.o usb.o cmd.o mac.o phy.o led.o fw.o tx.o rx.o
+carl9170-$(CONFIG_CARL9170_DEBUGFS) += debug.o
+
+obj-$(CONFIG_CARL9170) += carl9170.o
diff --git a/drivers/net/wireless/ath/carl9170/carl9170.h b/drivers/net/wireless/ath/carl9170/carl9170.h
new file mode 100644
index 000000000000..4da01a9f5680
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/carl9170.h
@@ -0,0 +1,637 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * Driver specific definitions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __CARL9170_H
+#define __CARL9170_H
+
+#include <linux/kernel.h>
+#include <linux/firmware.h>
+#include <linux/completion.h>
+#include <linux/spinlock.h>
+#include <net/cfg80211.h>
+#include <net/mac80211.h>
+#include <linux/usb.h>
+#ifdef CONFIG_CARL9170_LEDS
+#include <linux/leds.h>
+#endif /* CONFIG_CARL9170_LEDS */
+#ifdef CONFIG_CARL9170_WPC
+#include <linux/input.h>
+#endif /* CONFIG_CARL9170_WPC */
+#include "eeprom.h"
+#include "wlan.h"
+#include "hw.h"
+#include "fwdesc.h"
+#include "fwcmd.h"
+#include "../regd.h"
+
+#ifdef CONFIG_CARL9170_DEBUGFS
+#include "debug.h"
+#endif /* CONFIG_CARL9170_DEBUGFS */
+
+#define CARL9170FW_NAME "carl9170-1.fw"
+
+#define PAYLOAD_MAX     (CARL9170_MAX_CMD_LEN / 4 - 1)
+
+enum carl9170_rf_init_mode {
+        CARL9170_RFI_NONE,
+        CARL9170_RFI_WARM,
+        CARL9170_RFI_COLD,
+};
+
+#define CARL9170_MAX_RX_BUFFER_SIZE             8192
+
+enum carl9170_device_state {
+        CARL9170_UNKNOWN_STATE,
+        CARL9170_STOPPED,
+        CARL9170_IDLE,
+        CARL9170_STARTED,
+};
+
+#define CARL9170_NUM_TID                16
+#define WME_BA_BMP_SIZE                 64
+#define CARL9170_TX_USER_RATE_TRIES     3
+
+#define WME_AC_BE   2
+#define WME_AC_BK   3
+#define WME_AC_VI   1
+#define WME_AC_VO   0
+
+#define TID_TO_WME_AC(_tid)                             \
+        ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
+         (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
+         (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
+         WME_AC_VO)
+
+#define SEQ_DIFF(_start, _seq) \
+        (((_start) - (_seq)) & 0x0fff)
+#define SEQ_PREV(_seq) \
+        (((_seq) - 1) & 0x0fff)
+#define SEQ_NEXT(_seq) \
+        (((_seq) + 1) & 0x0fff)
+#define BAW_WITHIN(_start, _bawsz, _seqno) \
+        ((((_seqno) - (_start)) & 0xfff) < (_bawsz))
+
+enum carl9170_tid_state {
+        CARL9170_TID_STATE_INVALID,
+        CARL9170_TID_STATE_KILLED,
+        CARL9170_TID_STATE_SHUTDOWN,
+        CARL9170_TID_STATE_SUSPEND,
+        CARL9170_TID_STATE_PROGRESS,
+        CARL9170_TID_STATE_IDLE,
+        CARL9170_TID_STATE_XMIT,
+};
+
+#define CARL9170_BAW_BITS (2 * WME_BA_BMP_SIZE)
+#define CARL9170_BAW_SIZE (BITS_TO_LONGS(CARL9170_BAW_BITS))
+#define CARL9170_BAW_LEN (DIV_ROUND_UP(CARL9170_BAW_BITS, BITS_PER_BYTE))
+
+struct carl9170_sta_tid {
+        /* must be the first entry! */
+        struct list_head list;
+
+        /* temporary list for RCU unlink procedure */
+        struct list_head tmp_list;
+
+        /* lock for the following data structures */
+        spinlock_t lock;
+
+        unsigned int counter;
+        enum carl9170_tid_state state;
+        u8 tid;         /* TID number ( 0 - 15 ) */
+        u16 max;        /* max. AMPDU size */
+
+        u16 snx;        /* awaiting _next_ frame */
+        u16 hsn;        /* highest _queued_ sequence */
+        u16 bsn;        /* base of the tx/agg bitmap */
+        unsigned long bitmap[CARL9170_BAW_SIZE];
+
+        /* Preaggregation reorder queue */
+        struct sk_buff_head queue;
+};
+
+#define CARL9170_QUEUE_TIMEOUT          256
+#define CARL9170_BUMP_QUEUE             1000
+#define CARL9170_TX_TIMEOUT             2500
+#define CARL9170_JANITOR_DELAY          128
+#define CARL9170_QUEUE_STUCK_TIMEOUT    5500
+
+#define CARL9170_NUM_TX_AGG_MAX         30
+
+/*
+ * Tradeoff between stability/latency and speed.
+ *
+ * AR9170_TXQ_DEPTH is devised by dividing the amount of available
+ * tx buffers with the size of a full ethernet frame + overhead.
+ *
+ * Naturally: The higher the limit, the faster the device CAN send.
+ * However, even a slight over-commitment at the wrong time and the
+ * hardware is doomed to send all already-queued frames at suboptimal
+ * rates. This in turn leads to an enormous amount of unsuccessful
+ * retries => Latency goes up, whereas the throughput goes down. CRASH!
+ */
+#define CARL9170_NUM_TX_LIMIT_HARD      ((AR9170_TXQ_DEPTH * 3) / 2)
+#define CARL9170_NUM_TX_LIMIT_SOFT      (AR9170_TXQ_DEPTH)
+
+struct carl9170_tx_queue_stats {
+        unsigned int count;
+        unsigned int limit;
+        unsigned int len;
+};
+
+struct carl9170_vif {
+        unsigned int id;
+        struct ieee80211_vif *vif;
+};
+
+struct carl9170_vif_info {
+        struct list_head list;
+        bool active;
+        unsigned int id;
+        struct sk_buff *beacon;
+        bool enable_beacon;
+};
+
+#define AR9170_NUM_RX_URBS      16
+#define AR9170_NUM_RX_URBS_MUL  2
+#define AR9170_NUM_TX_URBS      8
+#define AR9170_NUM_RX_URBS_POOL (AR9170_NUM_RX_URBS_MUL * AR9170_NUM_RX_URBS)
+
+enum carl9170_device_features {
+        CARL9170_WPS_BUTTON             = BIT(0),
+        CARL9170_ONE_LED                = BIT(1),
+};
+
+#ifdef CONFIG_CARL9170_LEDS
+struct ar9170;
+
+struct carl9170_led {
+        struct ar9170 *ar;
+        struct led_classdev l;
+        char name[32];
+        unsigned int toggled;
+        bool last_state;
+        bool registered;
+};
+#endif /* CONFIG_CARL9170_LEDS */
+
+enum carl9170_restart_reasons {
+        CARL9170_RR_NO_REASON = 0,
+        CARL9170_RR_FATAL_FIRMWARE_ERROR,
+        CARL9170_RR_TOO_MANY_FIRMWARE_ERRORS,
+        CARL9170_RR_WATCHDOG,
+        CARL9170_RR_STUCK_TX,
+        CARL9170_RR_UNRESPONSIVE_DEVICE,
+        CARL9170_RR_COMMAND_TIMEOUT,
+        CARL9170_RR_TOO_MANY_PHY_ERRORS,
+        CARL9170_RR_LOST_RSP,
+        CARL9170_RR_INVALID_RSP,
+        CARL9170_RR_USER_REQUEST,
+
+        __CARL9170_RR_LAST,
+};
+
+enum carl9170_erp_modes {
+        CARL9170_ERP_INVALID,
+        CARL9170_ERP_AUTO,
+        CARL9170_ERP_MAC80211,
+        CARL9170_ERP_OFF,
+        CARL9170_ERP_CTS,
+        CARL9170_ERP_RTS,
+        __CARL9170_ERP_NUM,
+};
+
+struct ar9170 {
+        struct ath_common common;
+        struct ieee80211_hw *hw;
+        struct mutex mutex;
+        enum carl9170_device_state state;
+        spinlock_t state_lock;
+        enum carl9170_restart_reasons last_reason;
+        bool registered;
+
+        /* USB */
+        struct usb_device *udev;
+        struct usb_interface *intf;
+        struct usb_anchor rx_anch;
+        struct usb_anchor rx_work;
+        struct usb_anchor rx_pool;
+        struct usb_anchor tx_wait;
+        struct usb_anchor tx_anch;
+        struct usb_anchor tx_cmd;
+        struct usb_anchor tx_err;
+        struct tasklet_struct usb_tasklet;
+        atomic_t tx_cmd_urbs;
+        atomic_t tx_anch_urbs;
+        atomic_t rx_anch_urbs;
+        atomic_t rx_work_urbs;
+        atomic_t rx_pool_urbs;
+        kernel_ulong_t features;
+
+        /* firmware settings */
+        struct completion fw_load_wait;
+        struct completion fw_boot_wait;
+        struct {
+                const struct carl9170fw_desc_head *desc;
+                const struct firmware *fw;
+                unsigned int offset;
+                unsigned int address;
+                unsigned int cmd_bufs;
+                unsigned int api_version;
+                unsigned int vif_num;
+                unsigned int err_counter;
+                unsigned int bug_counter;
+                u32 beacon_addr;
+                unsigned int beacon_max_len;
+                bool rx_stream;
+                bool tx_stream;
+                bool rx_filter;
+                unsigned int mem_blocks;
+                unsigned int mem_block_size;
+                unsigned int rx_size;
+                unsigned int tx_seq_table;
+        } fw;
+
+        /* interface configuration combinations */
+        struct ieee80211_iface_limit if_comb_limits[1];
+        struct ieee80211_iface_combination if_combs[1];
+
+        /* reset / stuck frames/queue detection */
+        struct work_struct restart_work;
+        struct work_struct ping_work;
+        unsigned int restart_counter;
+        unsigned long queue_stop_timeout[__AR9170_NUM_TXQ];
+        unsigned long max_queue_stop_timeout[__AR9170_NUM_TXQ];
+        bool needs_full_reset;
+        atomic_t pending_restarts;
+
+        /* interface mode settings */
+        struct list_head vif_list;
+        unsigned long vif_bitmap;
+        unsigned int vifs;
+        struct carl9170_vif vif_priv[AR9170_MAX_VIRTUAL_MAC];
+
+        /* beaconing */
+        spinlock_t beacon_lock;
+        unsigned int global_pretbtt;
+        unsigned int global_beacon_int;
+        struct carl9170_vif_info *beacon_iter;
+        unsigned int beacon_enabled;
+
+        /* cryptographic engine */
+        u64 usedkeys;
+        bool rx_software_decryption;
+        bool disable_offload;
+
+        /* filter settings */
+        u64 cur_mc_hash;
+        u32 cur_filter;
+        unsigned int filter_state;
+        unsigned int rx_filter_caps;
+        bool sniffer_enabled;
+
+        /* MAC */
+        enum carl9170_erp_modes erp_mode;
+
+        /* PHY */
+        struct ieee80211_channel *channel;
+        int noise[4];
+        unsigned int chan_fail;
+        unsigned int total_chan_fail;
+        u8 heavy_clip;
+        u8 ht_settings;
+
+        /* power calibration data */
+        u8 power_5G_leg[4];
+        u8 power_2G_cck[4];
+        u8 power_2G_ofdm[4];
+        u8 power_5G_ht20[8];
+        u8 power_5G_ht40[8];
+        u8 power_2G_ht20[8];
+        u8 power_2G_ht40[8];
+
+#ifdef CONFIG_CARL9170_LEDS
+        /* LED */
+        struct delayed_work led_work;
+        struct carl9170_led leds[AR9170_NUM_LEDS];
+#endif /* CONFIG_CARL9170_LEDS */
+
+        /* qos queue settings */
+        spinlock_t tx_stats_lock;
+        struct carl9170_tx_queue_stats tx_stats[__AR9170_NUM_TXQ];
+        struct ieee80211_tx_queue_params edcf[5];
+        struct completion tx_flush;
+
+        /* CMD */
+        int cmd_seq;
+        int readlen;
+        u8 *readbuf;
+        spinlock_t cmd_lock;
+        struct completion cmd_wait;
+        union {
+                __le32 cmd_buf[PAYLOAD_MAX + 1];
+                struct carl9170_cmd cmd;
+                struct carl9170_rsp rsp;
+        };
+
+        /* statistics */
+        unsigned int tx_dropped;
+        unsigned int tx_ack_failures;
+        unsigned int tx_fcs_errors;
+        unsigned int rx_dropped;
+
+        /* EEPROM */
+        struct ar9170_eeprom eeprom;
+
+        /* tx queuing */
+        struct sk_buff_head tx_pending[__AR9170_NUM_TXQ];
+        struct sk_buff_head tx_status[__AR9170_NUM_TXQ];
+        struct delayed_work tx_janitor;
+        unsigned long tx_janitor_last_run;
+        bool tx_schedule;
+
+        /* tx ampdu */
+        struct work_struct ampdu_work;
+        spinlock_t tx_ampdu_list_lock;
+        struct carl9170_sta_tid *tx_ampdu_iter;
+        struct list_head tx_ampdu_list;
+        atomic_t tx_ampdu_upload;
+        atomic_t tx_ampdu_scheduler;
+        atomic_t tx_total_pending;
+        atomic_t tx_total_queued;
+        unsigned int tx_ampdu_list_len;
+        int current_density;
+        int current_factor;
+        bool tx_ampdu_schedule;
+
+        /* internal memory management */
+        spinlock_t mem_lock;
+        unsigned long *mem_bitmap;
+        atomic_t mem_free_blocks;
+        atomic_t mem_allocs;
+
+        /* rxstream mpdu merge */
+        struct ar9170_rx_head rx_plcp;
+        bool rx_has_plcp;
+        struct sk_buff *rx_failover;
+        int rx_failover_missing;
+
+#ifdef CONFIG_CARL9170_WPC
+        struct {
+                bool pbc_state;
+                struct input_dev *pbc;
+                char name[32];
+                char phys[32];
+        } wps;
+#endif /* CONFIG_CARL9170_WPC */
+
+#ifdef CONFIG_CARL9170_DEBUGFS
+        struct carl9170_debug debug;
+        struct dentry *debug_dir;
+#endif /* CONFIG_CARL9170_DEBUGFS */
+
+        /* PSM */
+        struct work_struct ps_work;
+        struct {
+                unsigned int dtim_counter;
+                unsigned long last_beacon;
+                unsigned long last_action;
+                unsigned long last_slept;
+                unsigned int sleep_ms;
+                unsigned int off_override;
+                bool state;
+        } ps;
+};
+
+enum carl9170_ps_off_override_reasons {
+        PS_OFF_VIF      = BIT(0),
+        PS_OFF_BCN      = BIT(1),
+        PS_OFF_5GHZ     = BIT(2),
+};
+
+struct carl9170_ba_stats {
+        u8 ampdu_len;
+        u8 ampdu_ack_len;
+        bool clear;
+        bool req;
+};
+
+struct carl9170_sta_info {
+        bool ht_sta;
+        bool sleeping;
+        atomic_t pending_frames;
+        unsigned int ampdu_max_len;
+        struct carl9170_sta_tid *agg[CARL9170_NUM_TID];
+        struct carl9170_ba_stats stats[CARL9170_NUM_TID];
+};
+
+struct carl9170_tx_info {
+        unsigned long timeout;
+        struct ar9170 *ar;
+        struct kref ref;
+};
+
+#define CHK_DEV_STATE(a, s)     (((struct ar9170 *)a)->state >= (s))
+#define IS_INITIALIZED(a)       (CHK_DEV_STATE(a, CARL9170_STOPPED))
+#define IS_ACCEPTING_CMD(a)     (CHK_DEV_STATE(a, CARL9170_IDLE))
+#define IS_STARTED(a)           (CHK_DEV_STATE(a, CARL9170_STARTED))
+
+static inline void __carl9170_set_state(struct ar9170 *ar,
+        enum carl9170_device_state newstate)
+{
+        ar->state = newstate;
+}
+
+static inline void carl9170_set_state(struct ar9170 *ar,
+        enum carl9170_device_state newstate)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ar->state_lock, flags);
+        __carl9170_set_state(ar, newstate);
+        spin_unlock_irqrestore(&ar->state_lock, flags);
+}
+
+static inline void carl9170_set_state_when(struct ar9170 *ar,
+        enum carl9170_device_state min, enum carl9170_device_state newstate)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ar->state_lock, flags);
+        if (CHK_DEV_STATE(ar, min))
+                __carl9170_set_state(ar, newstate);
+        spin_unlock_irqrestore(&ar->state_lock, flags);
+}
+
+/* exported interface */
+void *carl9170_alloc(size_t priv_size);
+int carl9170_register(struct ar9170 *ar);
+void carl9170_unregister(struct ar9170 *ar);
+void carl9170_free(struct ar9170 *ar);
+void carl9170_restart(struct ar9170 *ar, const enum carl9170_restart_reasons r);
+void carl9170_ps_check(struct ar9170 *ar);
+
+/* USB back-end */
+int carl9170_usb_open(struct ar9170 *ar);
+void carl9170_usb_stop(struct ar9170 *ar);
+void carl9170_usb_tx(struct ar9170 *ar, struct sk_buff *skb);
+void carl9170_usb_handle_tx_err(struct ar9170 *ar);
+int carl9170_exec_cmd(struct ar9170 *ar, const enum carl9170_cmd_oids,
+                      u32 plen, void *payload, u32 rlen, void *resp);
+int __carl9170_exec_cmd(struct ar9170 *ar, struct carl9170_cmd *cmd,
+                        const bool free_buf);
+int carl9170_usb_restart(struct ar9170 *ar);
+void carl9170_usb_reset(struct ar9170 *ar);
+
+/* MAC */
+int carl9170_init_mac(struct ar9170 *ar);
+int carl9170_set_qos(struct ar9170 *ar);
+int carl9170_update_multicast(struct ar9170 *ar, const u64 mc_hast);
+int carl9170_mod_virtual_mac(struct ar9170 *ar, const unsigned int id,
+                             const u8 *mac);
+int carl9170_set_operating_mode(struct ar9170 *ar);
+int carl9170_set_beacon_timers(struct ar9170 *ar);
+int carl9170_set_dyn_sifs_ack(struct ar9170 *ar);
+int carl9170_set_rts_cts_rate(struct ar9170 *ar);
+int carl9170_set_ampdu_settings(struct ar9170 *ar);
+int carl9170_set_slot_time(struct ar9170 *ar);
+int carl9170_set_mac_rates(struct ar9170 *ar);
+int carl9170_set_hwretry_limit(struct ar9170 *ar, const u32 max_retry);
+int carl9170_update_beacon(struct ar9170 *ar, const bool submit);
+int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac,
+        const u8 ktype, const u8 keyidx, const u8 *keydata, const int keylen);
+int carl9170_disable_key(struct ar9170 *ar, const u8 id);
+
+/* RX */
+void carl9170_rx(struct ar9170 *ar, void *buf, unsigned int len);
+void carl9170_handle_command_response(struct ar9170 *ar, void *buf, u32 len);
+
+/* TX */
+void carl9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
+void carl9170_tx_janitor(struct work_struct *work);
+void carl9170_tx_process_status(struct ar9170 *ar,
+                                const struct carl9170_rsp *cmd);
+void carl9170_tx_status(struct ar9170 *ar, struct sk_buff *skb,
+                        const bool success);
+void carl9170_tx_callback(struct ar9170 *ar, struct sk_buff *skb);
+void carl9170_tx_drop(struct ar9170 *ar, struct sk_buff *skb);
+void carl9170_tx_scheduler(struct ar9170 *ar);
+void carl9170_tx_get_skb(struct sk_buff *skb);
+int carl9170_tx_put_skb(struct sk_buff *skb);
+
+/* LEDs */
+#ifdef CONFIG_CARL9170_LEDS
+int carl9170_led_register(struct ar9170 *ar);
+void carl9170_led_unregister(struct ar9170 *ar);
+#endif /* CONFIG_CARL9170_LEDS */
+int carl9170_led_init(struct ar9170 *ar);
+int carl9170_led_set_state(struct ar9170 *ar, const u32 led_state);
+
+/* PHY / RF */
+int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
+        enum nl80211_channel_type bw, enum carl9170_rf_init_mode rfi);
+int carl9170_get_noisefloor(struct ar9170 *ar);
+
+/* FW */
+int carl9170_parse_firmware(struct ar9170 *ar);
+int carl9170_fw_fix_eeprom(struct ar9170 *ar);
+
+extern struct ieee80211_rate __carl9170_ratetable[];
+extern int modparam_noht;
+
+static inline struct ar9170 *carl9170_get_priv(struct carl9170_vif *carl_vif)
+{
+        return container_of(carl_vif, struct ar9170,
+                            vif_priv[carl_vif->id]);
+}
+
+static inline struct ieee80211_hdr *carl9170_get_hdr(struct sk_buff *skb)
+{
+        return (void *)((struct _carl9170_tx_superframe *)
+                skb->data)->frame_data;
+}
+
+static inline u16 get_seq_h(struct ieee80211_hdr *hdr)
+{
+        return le16_to_cpu(hdr->seq_ctrl) >> 4;
+}
+
+static inline u16 carl9170_get_seq(struct sk_buff *skb)
+{
+        return get_seq_h(carl9170_get_hdr(skb));
+}
+
+static inline u16 get_tid_h(struct ieee80211_hdr *hdr)
+{
+        return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
+}
+
+static inline u16 carl9170_get_tid(struct sk_buff *skb)
+{
+        return get_tid_h(carl9170_get_hdr(skb));
+}
+
+static inline struct ieee80211_vif *
+carl9170_get_vif(struct carl9170_vif_info *priv)
+{
+        return container_of((void *)priv, struct ieee80211_vif, drv_priv);
+}
+
+/* Protected by ar->mutex or RCU */
+static inline struct ieee80211_vif *carl9170_get_main_vif(struct ar9170 *ar)
+{
+        struct carl9170_vif_info *cvif;
+
+        list_for_each_entry_rcu(cvif, &ar->vif_list, list) {
+                if (cvif->active)
+                        return carl9170_get_vif(cvif);
+        }
+
+        return NULL;
+}
+
+static inline bool is_main_vif(struct ar9170 *ar, struct ieee80211_vif *vif)
+{
+        bool ret;
+
+        rcu_read_lock();
+        ret = (carl9170_get_main_vif(ar) == vif);
+        rcu_read_unlock();
+        return ret;
+}
+
+#endif /* __CARL9170_H */
diff --git a/drivers/net/wireless/ath/carl9170/cmd.c b/drivers/net/wireless/ath/carl9170/cmd.c
new file mode 100644
index 000000000000..cdfc94c371b4
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/cmd.c
@@ -0,0 +1,188 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * Basic HW register/memory/command access functions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "carl9170.h"
+#include "cmd.h"
+
+int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
+{
+        const __le32 buf[2] = {
+                cpu_to_le32(reg),
+                cpu_to_le32(val),
+        };
+        int err;
+
+        err = carl9170_exec_cmd(ar, CARL9170_CMD_WREG, sizeof(buf),
+                                (u8 *) buf, 0, NULL);
+        if (err) {
+                if (net_ratelimit()) {
+                        wiphy_err(ar->hw->wiphy, "writing reg %#x "
+                                "(val %#x) failed (%d)\n", reg, val, err);
+                }
+        }
+        return err;
+}
+
+int carl9170_read_mreg(struct ar9170 *ar, const int nregs,
+                       const u32 *regs, u32 *out)
+{
+        int i, err;
+        __le32 *offs, *res;
+
+        /* abuse "out" for the register offsets, must be same length */
+        offs = (__le32 *)out;
+        for (i = 0; i < nregs; i++)
+                offs[i] = cpu_to_le32(regs[i]);
+
+        /* also use the same buffer for the input */
+        res = (__le32 *)out;
+
+        err = carl9170_exec_cmd(ar, CARL9170_CMD_RREG,
+                                4 * nregs, (u8 *)offs,
+                                4 * nregs, (u8 *)res);
+        if (err) {
+                if (net_ratelimit()) {
+                        wiphy_err(ar->hw->wiphy, "reading regs failed (%d)\n",
+                                  err);
+                }
+                return err;
+        }
+
+        /* convert result to cpu endian */
+        for (i = 0; i < nregs; i++)
+                out[i] = le32_to_cpu(res[i]);
+
+        return 0;
+}
+
+int carl9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val)
+{
+        return carl9170_read_mreg(ar, 1, &reg, val);
+}
+
+int carl9170_echo_test(struct ar9170 *ar, const u32 v)
+{
+        u32 echores;
+        int err;
+
+        err = carl9170_exec_cmd(ar, CARL9170_CMD_ECHO,
+                                4, (u8 *)&v,
+                                4, (u8 *)&echores);
+        if (err)
+                return err;
+
+        if (v != echores) {
+                wiphy_info(ar->hw->wiphy, "wrong echo %x != %x", v, echores);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+struct carl9170_cmd *carl9170_cmd_buf(struct ar9170 *ar,
+        const enum carl9170_cmd_oids cmd, const unsigned int len)
+{
+        struct carl9170_cmd *tmp;
+
+        tmp = kzalloc(sizeof(struct carl9170_cmd_head) + len, GFP_ATOMIC);
+        if (tmp) {
+                tmp->hdr.cmd = cmd;
+                tmp->hdr.len = len;
+        }
+
+        return tmp;
+}
+
+int carl9170_reboot(struct ar9170 *ar)
+{
+        struct carl9170_cmd *cmd;
+        int err;
+
+        cmd = carl9170_cmd_buf(ar, CARL9170_CMD_REBOOT_ASYNC, 0);
+        if (!cmd)
+                return -ENOMEM;
+
+        err = __carl9170_exec_cmd(ar, (struct carl9170_cmd *)cmd, true);
+        return err;
+}
+
+int carl9170_mac_reset(struct ar9170 *ar)
+{
+        return carl9170_exec_cmd(ar, CARL9170_CMD_SWRST,
+                                 0, NULL, 0, NULL);
+}
+
+int carl9170_bcn_ctrl(struct ar9170 *ar, const unsigned int vif_id,
+                       const u32 mode, const u32 addr, const u32 len)
+{
+        struct carl9170_cmd *cmd;
+
+        cmd = carl9170_cmd_buf(ar, CARL9170_CMD_BCN_CTRL_ASYNC,
+                               sizeof(struct carl9170_bcn_ctrl_cmd));
+        if (!cmd)
+                return -ENOMEM;
+
+        cmd->bcn_ctrl.vif_id = cpu_to_le32(vif_id);
+        cmd->bcn_ctrl.mode = cpu_to_le32(mode);
+        cmd->bcn_ctrl.bcn_addr = cpu_to_le32(addr);
+        cmd->bcn_ctrl.bcn_len = cpu_to_le32(len);
+
+        return __carl9170_exec_cmd(ar, cmd, true);
+}
+
+int carl9170_powersave(struct ar9170 *ar, const bool ps)
+{
+        struct carl9170_cmd *cmd;
+        u32 state;
+
+        cmd = carl9170_cmd_buf(ar, CARL9170_CMD_PSM_ASYNC,
+                               sizeof(struct carl9170_psm));
+        if (!cmd)
+                return -ENOMEM;
+
+        if (ps) {
+                /* Sleep until next TBTT */
+                state = CARL9170_PSM_SLEEP | 1;
+        } else {
+                /* wake up immediately */
+                state = 1;
+        }
+
+        cmd->psm.state = cpu_to_le32(state);
+        return __carl9170_exec_cmd(ar, cmd, true);
+}
diff --git a/drivers/net/wireless/ath/carl9170/cmd.h b/drivers/net/wireless/ath/carl9170/cmd.h
new file mode 100644
index 000000000000..568174c71b94
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/cmd.h
@@ -0,0 +1,173 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * Basic HW register/memory/command access functions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __CMD_H
+#define __CMD_H
+
+#include "carl9170.h"
+
+/* basic HW access */
+int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val);
+int carl9170_read_reg(struct ar9170 *ar, const u32 reg, u32 *val);
+int carl9170_read_mreg(struct ar9170 *ar, const int nregs,
+                       const u32 *regs, u32 *out);
+int carl9170_echo_test(struct ar9170 *ar, u32 v);
+int carl9170_reboot(struct ar9170 *ar);
+int carl9170_mac_reset(struct ar9170 *ar);
+int carl9170_powersave(struct ar9170 *ar, const bool power_on);
+int carl9170_bcn_ctrl(struct ar9170 *ar, const unsigned int vif_id,
+                       const u32 mode, const u32 addr, const u32 len);
+
+static inline int carl9170_flush_cab(struct ar9170 *ar,
+                                     const unsigned int vif_id)
+{
+        return carl9170_bcn_ctrl(ar, vif_id, CARL9170_BCN_CTRL_DRAIN, 0, 0);
+}
+
+static inline int carl9170_rx_filter(struct ar9170 *ar,
+                                     const unsigned int _rx_filter)
+{
+        __le32 rx_filter = cpu_to_le32(_rx_filter);
+
+        return carl9170_exec_cmd(ar, CARL9170_CMD_RX_FILTER,
+                                sizeof(rx_filter), (u8 *)&rx_filter,
+                                0, NULL);
+}
+
+struct carl9170_cmd *carl9170_cmd_buf(struct ar9170 *ar,
+        const enum carl9170_cmd_oids cmd, const unsigned int len);
+
+/*
+ * Macros to facilitate writing multiple registers in a single
+ * write-combining USB command. Note that when the first group
+ * fails the whole thing will fail without any others attempted,
+ * but you won't know which write in the group failed.
+ */
+#define carl9170_regwrite_begin(ar)                                     \
+do {                                                                    \
+        int __nreg = 0, __err = 0;                                      \
+        struct ar9170 *__ar = ar;
+
+#define carl9170_regwrite(r, v) do {                                    \
+        __ar->cmd_buf[2 * __nreg + 1] = cpu_to_le32(r);                 \
+        __ar->cmd_buf[2 * __nreg + 2] = cpu_to_le32(v);                 \
+        __nreg++;                                                       \
+        if ((__nreg >= PAYLOAD_MAX/2)) {                                \
+                if (IS_ACCEPTING_CMD(__ar))                             \
+                        __err = carl9170_exec_cmd(__ar,                 \
+                                CARL9170_CMD_WREG, 8 * __nreg,          \
+                                (u8 *) &__ar->cmd_buf[1], 0, NULL);     \
+                else                                                    \
+                        goto __regwrite_out;                            \
+                                                                        \
+                __nreg = 0;                                             \
+                if (__err)                                              \
+                        goto __regwrite_out;                            \
+        }                                                               \
+} while (0)
+
+#define carl9170_regwrite_finish()                                      \
+__regwrite_out :                                                        \
+        if (__err == 0 && __nreg) {                                     \
+                if (IS_ACCEPTING_CMD(__ar))                             \
+                        __err = carl9170_exec_cmd(__ar,                 \
+                                CARL9170_CMD_WREG, 8 * __nreg,          \
+                                (u8 *) &__ar->cmd_buf[1], 0, NULL);     \
+                __nreg = 0;                                             \
+        }
+
+#define carl9170_regwrite_result()                                      \
+        __err;                                                          \
+} while (0);
+
+
+#define carl9170_async_regwrite_get_buf()                               \
+do {                                                                    \
+        __nreg = 0;                                                     \
+        __cmd = carl9170_cmd_buf(__carl, CARL9170_CMD_WREG_ASYNC,       \
+                                 CARL9170_MAX_CMD_PAYLOAD_LEN);         \
+        if (__cmd == NULL) {                                            \
+                __err = -ENOMEM;                                        \
+                goto __async_regwrite_out;                              \
+        }                                                               \
+} while (0);
+
+#define carl9170_async_regwrite_begin(carl)                             \
+do {                                                                    \
+        struct ar9170 *__carl = carl;                                   \
+        struct carl9170_cmd *__cmd;                                     \
+        unsigned int __nreg;                                            \
+        int  __err = 0;                                                 \
+        carl9170_async_regwrite_get_buf();                              \
+
+#define carl9170_async_regwrite_flush()                                 \
+do {                                                                    \
+        if (__cmd == NULL || __nreg == 0)                               \
+                break;                                                  \
+                                                                        \
+        if (IS_ACCEPTING_CMD(__carl) && __nreg) {                       \
+                __cmd->hdr.len = 8 * __nreg;                            \
+                __err = __carl9170_exec_cmd(__carl, __cmd, true);       \
+                __cmd = NULL;                                           \
+                break;                                                  \
+        }                                                               \
+        goto __async_regwrite_out;                                      \
+} while (0)
+
+#define carl9170_async_regwrite(r, v) do {                              \
+        if (__cmd == NULL)                                              \
+                carl9170_async_regwrite_get_buf();                      \
+        __cmd->wreg.regs[__nreg].addr = cpu_to_le32(r);                 \
+        __cmd->wreg.regs[__nreg].val = cpu_to_le32(v);                  \
+        __nreg++;                                                       \
+        if ((__nreg >= PAYLOAD_MAX / 2))                                \
+                carl9170_async_regwrite_flush();                        \
+} while (0)
+
+#define carl9170_async_regwrite_finish() do {                           \
+__async_regwrite_out :                                                  \
+        if (__cmd != NULL && __err == 0)                                \
+                carl9170_async_regwrite_flush();                        \
+        kfree(__cmd);                                                   \
+} while (0)                                                             \
+
+#define carl9170_async_regwrite_result()                                \
+        __err;                                                          \
+} while (0);
+
+#endif /* __CMD_H */
diff --git a/drivers/net/wireless/ath/carl9170/debug.c b/drivers/net/wireless/ath/carl9170/debug.c
new file mode 100644
index 000000000000..0ac1124c2a0b
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/debug.c
@@ -0,0 +1,902 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * debug(fs) probing
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2008-2009 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include <linux/vmalloc.h>
+#include "carl9170.h"
+#include "cmd.h"
+
+#define ADD(buf, off, max, fmt, args...)                                \
+        off += snprintf(&buf[off], max - off, fmt, ##args);
+
+static int carl9170_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+struct carl9170_debugfs_fops {
+        unsigned int read_bufsize;
+        mode_t attr;
+        char *(*read)(struct ar9170 *ar, char *buf, size_t bufsize,
+                      ssize_t *len);
+        ssize_t (*write)(struct ar9170 *aru, const char *buf, size_t size);
+        const struct file_operations fops;
+
+        enum carl9170_device_state req_dev_state;
+};
+
+static ssize_t carl9170_debugfs_read(struct file *file, char __user *userbuf,
+                                     size_t count, loff_t *ppos)
+{
+        struct carl9170_debugfs_fops *dfops;
+        struct ar9170 *ar;
+        char *buf = NULL, *res_buf = NULL;
+        ssize_t ret = 0;
+        int err = 0;
+
+        if (!count)
+                return 0;
+
+        ar = file->private_data;
+
+        if (!ar)
+                return -ENODEV;
+        dfops = container_of(file->f_op, struct carl9170_debugfs_fops, fops);
+
+        if (!dfops->read)
+                return -ENOSYS;
+
+        if (dfops->read_bufsize) {
+                buf = vmalloc(dfops->read_bufsize);
+                if (!buf)
+                        return -ENOMEM;
+        }
+
+        mutex_lock(&ar->mutex);
+        if (!CHK_DEV_STATE(ar, dfops->req_dev_state)) {
+                err = -ENODEV;
+                res_buf = buf;
+                goto out_free;
+        }
+
+        res_buf = dfops->read(ar, buf, dfops->read_bufsize, &ret);
+
+        if (ret > 0)
+                err = simple_read_from_buffer(userbuf, count, ppos,
+                                              res_buf, ret);
+        else
+                err = ret;
+
+        WARN_ON_ONCE(dfops->read_bufsize && (res_buf != buf));
+
+out_free:
+        vfree(res_buf);
+        mutex_unlock(&ar->mutex);
+        return err;
+}
+
+static ssize_t carl9170_debugfs_write(struct file *file,
+        const char __user *userbuf, size_t count, loff_t *ppos)
+{
+        struct carl9170_debugfs_fops *dfops;
+        struct ar9170 *ar;
+        char *buf = NULL;
+        int err = 0;
+
+        if (!count)
+                return 0;
+
+        if (count > PAGE_SIZE)
+                return -E2BIG;
+
+        ar = file->private_data;
+
+        if (!ar)
+                return -ENODEV;
+        dfops = container_of(file->f_op, struct carl9170_debugfs_fops, fops);
+
+        if (!dfops->write)
+                return -ENOSYS;
+
+        buf = vmalloc(count);
+        if (!buf)
+                return -ENOMEM;
+
+        if (copy_from_user(buf, userbuf, count)) {
+                err = -EFAULT;
+                goto out_free;
+        }
+
+        if (mutex_trylock(&ar->mutex) == 0) {
+                err = -EAGAIN;
+                goto out_free;
+        }
+
+        if (!CHK_DEV_STATE(ar, dfops->req_dev_state)) {
+                err = -ENODEV;
+                goto out_unlock;
+        }
+
+        err = dfops->write(ar, buf, count);
+        if (err)
+                goto out_unlock;
+
+out_unlock:
+        mutex_unlock(&ar->mutex);
+
+out_free:
+        vfree(buf);
+        return err;
+}
+
+#define __DEBUGFS_DECLARE_FILE(name, _read, _write, _read_bufsize,      \
+                               _attr, _dstate)                          \
+static const struct carl9170_debugfs_fops carl_debugfs_##name ##_ops = {\
+        .read_bufsize = _read_bufsize,                                  \
+        .read = _read,                                                  \
+        .write = _write,                                                \
+        .attr = _attr,                                                  \
+        .req_dev_state = _dstate,                                       \
+        .fops = {                                                       \
+                .open   = carl9170_debugfs_open,                        \
+                .read   = carl9170_debugfs_read,                        \
+                .write  = carl9170_debugfs_write,                       \
+                .owner  = THIS_MODULE                                   \
+        },                                                              \
+}
+
+#define DEBUGFS_DECLARE_FILE(name, _read, _write, _read_bufsize, _attr) \
+        __DEBUGFS_DECLARE_FILE(name, _read, _write, _read_bufsize,      \
+                               _attr, CARL9170_STARTED)                 \
+
+#define DEBUGFS_DECLARE_RO_FILE(name, _read_bufsize)                    \
+        DEBUGFS_DECLARE_FILE(name, carl9170_debugfs_##name ##_read,     \
+                             NULL, _read_bufsize, S_IRUSR)
+
+#define DEBUGFS_DECLARE_WO_FILE(name)                                   \
+        DEBUGFS_DECLARE_FILE(name, NULL, carl9170_debugfs_##name ##_write,\
+                             0, S_IWUSR)
+
+#define DEBUGFS_DECLARE_RW_FILE(name, _read_bufsize)                    \
+        DEBUGFS_DECLARE_FILE(name, carl9170_debugfs_##name ##_read,     \
+                             carl9170_debugfs_##name ##_write,          \
+                             _read_bufsize, S_IRUSR | S_IWUSR)
+
+#define __DEBUGFS_DECLARE_RW_FILE(name, _read_bufsize, _dstate)         \
+        __DEBUGFS_DECLARE_FILE(name, carl9170_debugfs_##name ##_read,   \
+                             carl9170_debugfs_##name ##_write,          \
+                             _read_bufsize, S_IRUSR | S_IWUSR, _dstate)
+
+#define DEBUGFS_READONLY_FILE(name, _read_bufsize, fmt, value...)       \
+static char *carl9170_debugfs_ ##name ## _read(struct ar9170 *ar,       \
+                                             char *buf, size_t buf_size,\
+                                             ssize_t *len)              \
+{                                                                       \
+        ADD(buf, *len, buf_size, fmt "\n", ##value);                    \
+        return buf;                                                     \
+}                                                                       \
+DEBUGFS_DECLARE_RO_FILE(name, _read_bufsize)
+
+static char *carl9170_debugfs_mem_usage_read(struct ar9170 *ar, char *buf,
+                                             size_t bufsize, ssize_t *len)
+{
+        ADD(buf, *len, bufsize, "jar: [");
+
+        spin_lock_bh(&ar->mem_lock);
+
+        *len += bitmap_scnprintf(&buf[*len], bufsize - *len,
+                                  ar->mem_bitmap, ar->fw.mem_blocks);
+
+        ADD(buf, *len, bufsize, "]\n");
+
+        ADD(buf, *len, bufsize, "cookies: used:%3d / total:%3d, allocs:%d\n",
+            bitmap_weight(ar->mem_bitmap, ar->fw.mem_blocks),
+            ar->fw.mem_blocks, atomic_read(&ar->mem_allocs));
+
+        ADD(buf, *len, bufsize, "memory: free:%3d (%3d KiB) / total:%3d KiB)\n",
+            atomic_read(&ar->mem_free_blocks),
+            (atomic_read(&ar->mem_free_blocks) * ar->fw.mem_block_size) / 1024,
+            (ar->fw.mem_blocks * ar->fw.mem_block_size) / 1024);
+
+        spin_unlock_bh(&ar->mem_lock);
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(mem_usage, 512);
+
+static char *carl9170_debugfs_qos_stat_read(struct ar9170 *ar, char *buf,
+                                            size_t bufsize, ssize_t *len)
+{
+        ADD(buf, *len, bufsize, "%s QoS AC\n", modparam_noht ? "Hardware" :
+            "Software");
+
+        ADD(buf, *len, bufsize, "[     VO            VI       "
+                                 "     BE            BK      ]\n");
+
+        spin_lock_bh(&ar->tx_stats_lock);
+        ADD(buf, *len, bufsize, "[length/limit  length/limit  "
+                                 "length/limit  length/limit ]\n"
+                                "[   %3d/%3d       %3d/%3d    "
+                                 "   %3d/%3d       %3d/%3d   ]\n\n",
+            ar->tx_stats[0].len, ar->tx_stats[0].limit,
+            ar->tx_stats[1].len, ar->tx_stats[1].limit,
+            ar->tx_stats[2].len, ar->tx_stats[2].limit,
+            ar->tx_stats[3].len, ar->tx_stats[3].limit);
+
+        ADD(buf, *len, bufsize, "[    total         total     "
+                                 "    total         total    ]\n"
+                                "[%10d    %10d    %10d    %10d   ]\n\n",
+            ar->tx_stats[0].count, ar->tx_stats[1].count,
+            ar->tx_stats[2].count, ar->tx_stats[3].count);
+
+        spin_unlock_bh(&ar->tx_stats_lock);
+
+        ADD(buf, *len, bufsize, "[  pend/waittx   pend/waittx "
+                                 "  pend/waittx   pend/waittx]\n"
+                                "[   %3d/%3d       %3d/%3d    "
+                                 "   %3d/%3d       %3d/%3d   ]\n\n",
+            skb_queue_len(&ar->tx_pending[0]),
+            skb_queue_len(&ar->tx_status[0]),
+            skb_queue_len(&ar->tx_pending[1]),
+            skb_queue_len(&ar->tx_status[1]),
+            skb_queue_len(&ar->tx_pending[2]),
+            skb_queue_len(&ar->tx_status[2]),
+            skb_queue_len(&ar->tx_pending[3]),
+            skb_queue_len(&ar->tx_status[3]));
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(qos_stat, 512);
+
+static void carl9170_debugfs_format_frame(struct ar9170 *ar,
+        struct sk_buff *skb, const char *prefix, char *buf,
+        ssize_t *off, ssize_t bufsize)
+{
+        struct _carl9170_tx_superframe *txc = (void *) skb->data;
+        struct ieee80211_tx_info *txinfo = IEEE80211_SKB_CB(skb);
+        struct carl9170_tx_info *arinfo = (void *) txinfo->rate_driver_data;
+        struct ieee80211_hdr *hdr = (void *) txc->frame_data;
+
+        ADD(buf, *off, bufsize, "%s %p, c:%2x, DA:%pM, sq:%4d, mc:%.4x, "
+            "pc:%.8x, to:%d ms\n", prefix, skb, txc->s.cookie,
+            ieee80211_get_DA(hdr), get_seq_h(hdr),
+            le16_to_cpu(txc->f.mac_control), le32_to_cpu(txc->f.phy_control),
+            jiffies_to_msecs(jiffies - arinfo->timeout));
+}
+
+
+static char *carl9170_debugfs_ampdu_state_read(struct ar9170 *ar, char *buf,
+                                               size_t bufsize, ssize_t *len)
+{
+        struct carl9170_sta_tid *iter;
+        struct sk_buff *skb;
+        int cnt = 0, fc;
+        int offset;
+
+        rcu_read_lock();
+        list_for_each_entry_rcu(iter, &ar->tx_ampdu_list, list) {
+
+                spin_lock_bh(&iter->lock);
+                ADD(buf, *len, bufsize, "Entry: #%2d TID:%1d, BSN:%4d, "
+                    "SNX:%4d, HSN:%4d, BAW:%2d, state:%1d, toggles:%d\n",
+                    cnt, iter->tid, iter->bsn, iter->snx, iter->hsn,
+                    iter->max, iter->state, iter->counter);
+
+                ADD(buf, *len, bufsize, "\tWindow:  [");
+
+                *len += bitmap_scnprintf(&buf[*len], bufsize - *len,
+                        iter->bitmap, CARL9170_BAW_BITS);
+
+#define BM_STR_OFF(offset)                                      \
+        ((CARL9170_BAW_BITS - (offset) - 1) / 4 +               \
+         (CARL9170_BAW_BITS - (offset) - 1) / 32 + 1)
+
+                ADD(buf, *len, bufsize, ",W]\n");
+
+                offset = BM_STR_OFF(0);
+                ADD(buf, *len, bufsize, "\tBase Seq: %*s\n", offset, "T");
+
+                offset = BM_STR_OFF(SEQ_DIFF(iter->snx, iter->bsn));
+                ADD(buf, *len, bufsize, "\tNext Seq: %*s\n", offset, "W");
+
+                offset = BM_STR_OFF(((int)iter->hsn - (int)iter->bsn) %
+                                     CARL9170_BAW_BITS);
+                ADD(buf, *len, bufsize, "\tLast Seq: %*s\n", offset, "N");
+
+                ADD(buf, *len, bufsize, "\tPre-Aggregation reorder buffer: "
+                    " currently queued:%d\n", skb_queue_len(&iter->queue));
+
+                fc = 0;
+                skb_queue_walk(&iter->queue, skb) {
+                        char prefix[32];
+
+                        snprintf(prefix, sizeof(prefix), "\t\t%3d :", fc);
+                        carl9170_debugfs_format_frame(ar, skb, prefix, buf,
+                                                      len, bufsize);
+
+                        fc++;
+                }
+                spin_unlock_bh(&iter->lock);
+                cnt++;
+        }
+        rcu_read_unlock();
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(ampdu_state, 8000);
+
+static void carl9170_debugfs_queue_dump(struct ar9170 *ar, char *buf,
+        ssize_t *len, size_t bufsize, struct sk_buff_head *queue)
+{
+        struct sk_buff *skb;
+        char prefix[16];
+        int fc = 0;
+
+        spin_lock_bh(&queue->lock);
+        skb_queue_walk(queue, skb) {
+                snprintf(prefix, sizeof(prefix), "%3d :", fc);
+                carl9170_debugfs_format_frame(ar, skb, prefix, buf,
+                                              len, bufsize);
+                fc++;
+        }
+        spin_unlock_bh(&queue->lock);
+}
+
+#define DEBUGFS_QUEUE_DUMP(q, qi)                                       \
+static char *carl9170_debugfs_##q ##_##qi ##_read(struct ar9170 *ar,    \
+        char *buf, size_t bufsize, ssize_t *len)                        \
+{                                                                       \
+        carl9170_debugfs_queue_dump(ar, buf, len, bufsize, &ar->q[qi]); \
+        return buf;                                                     \
+}                                                                       \
+DEBUGFS_DECLARE_RO_FILE(q##_##qi, 8000);
+
+static char *carl9170_debugfs_sta_psm_read(struct ar9170 *ar, char *buf,
+                                           size_t bufsize, ssize_t *len)
+{
+        ADD(buf, *len, bufsize, "psm state: %s\n", (ar->ps.off_override ?
+            "FORCE CAM" : (ar->ps.state ? "PSM" : "CAM")));
+
+        ADD(buf, *len, bufsize, "sleep duration: %d ms.\n", ar->ps.sleep_ms);
+        ADD(buf, *len, bufsize, "last power-state transition: %d ms ago.\n",
+            jiffies_to_msecs(jiffies - ar->ps.last_action));
+        ADD(buf, *len, bufsize, "last CAM->PSM transition: %d ms ago.\n",
+            jiffies_to_msecs(jiffies - ar->ps.last_slept));
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(sta_psm, 160);
+
+static char *carl9170_debugfs_tx_stuck_read(struct ar9170 *ar, char *buf,
+                                            size_t bufsize, ssize_t *len)
+{
+        int i;
+
+        for (i = 0; i < ar->hw->queues; i++) {
+                ADD(buf, *len, bufsize, "TX queue [%d]: %10d max:%10d ms.\n",
+                    i, ieee80211_queue_stopped(ar->hw, i) ?
+                    jiffies_to_msecs(jiffies - ar->queue_stop_timeout[i]) : 0,
+                    jiffies_to_msecs(ar->max_queue_stop_timeout[i]));
+
+                ar->max_queue_stop_timeout[i] = 0;
+        }
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(tx_stuck, 180);
+
+static char *carl9170_debugfs_phy_noise_read(struct ar9170 *ar, char *buf,
+                                             size_t bufsize, ssize_t *len)
+{
+        int err;
+
+        err = carl9170_get_noisefloor(ar);
+        if (err) {
+                *len = err;
+                return buf;
+        }
+
+        ADD(buf, *len, bufsize, "Chain 0: %10d dBm, ext. chan.:%10d dBm\n",
+            ar->noise[0], ar->noise[2]);
+        ADD(buf, *len, bufsize, "Chain 2: %10d dBm, ext. chan.:%10d dBm\n",
+            ar->noise[1], ar->noise[3]);
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(phy_noise, 180);
+
+static char *carl9170_debugfs_vif_dump_read(struct ar9170 *ar, char *buf,
+                                            size_t bufsize, ssize_t *len)
+{
+        struct carl9170_vif_info *iter;
+        int i = 0;
+
+        ADD(buf, *len, bufsize, "registered VIFs:%d \\ %d\n",
+            ar->vifs, ar->fw.vif_num);
+
+        ADD(buf, *len, bufsize, "VIF bitmap: [");
+
+        *len += bitmap_scnprintf(&buf[*len], bufsize - *len,
+                                 &ar->vif_bitmap, ar->fw.vif_num);
+
+        ADD(buf, *len, bufsize, "]\n");
+
+        rcu_read_lock();
+        list_for_each_entry_rcu(iter, &ar->vif_list, list) {
+                struct ieee80211_vif *vif = carl9170_get_vif(iter);
+                ADD(buf, *len, bufsize, "\t%d = [%s VIF, id:%d, type:%x "
+                    " mac:%pM %s]\n", i, (carl9170_get_main_vif(ar) == vif ?
+                    "Master" : " Slave"), iter->id, vif->type, vif->addr,
+                    iter->enable_beacon ? "beaconing " : "");
+                i++;
+        }
+        rcu_read_unlock();
+
+        return buf;
+}
+DEBUGFS_DECLARE_RO_FILE(vif_dump, 8000);
+
+#define UPDATE_COUNTER(ar, name)        ({                              \
+        u32 __tmp[ARRAY_SIZE(name##_regs)];                             \
+        unsigned int __i, __err = -ENODEV;                              \
+                                                                        \
+        for (__i = 0; __i < ARRAY_SIZE(name##_regs); __i++) {           \
+                __tmp[__i] = name##_regs[__i].reg;                      \
+                ar->debug.stats.name##_counter[__i] = 0;                \
+        }                                                               \
+                                                                        \
+        if (IS_STARTED(ar))                                             \
+                __err = carl9170_read_mreg(ar, ARRAY_SIZE(name##_regs), \
+                        __tmp, ar->debug.stats.name##_counter);         \
+        (__err); })
+
+#define TALLY_SUM_UP(ar, name)  do {                                    \
+        unsigned int __i;                                               \
+                                                                        \
+        for (__i = 0; __i < ARRAY_SIZE(name##_regs); __i++) {           \
+                ar->debug.stats.name##_sum[__i] +=                      \
+                        ar->debug.stats.name##_counter[__i];            \
+        }                                                               \
+} while (0)
+
+#define DEBUGFS_HW_TALLY_FILE(name, f)                                  \
+static char *carl9170_debugfs_##name ## _read(struct ar9170 *ar,        \
+         char *dum, size_t bufsize, ssize_t *ret)                       \
+{                                                                       \
+        char *buf;                                                      \
+        int i, max_len, err;                                            \
+                                                                        \
+        max_len = ARRAY_SIZE(name##_regs) * 80;                         \
+        buf = vmalloc(max_len);                                         \
+        if (!buf)                                                       \
+                return NULL;                                            \
+                                                                        \
+        err = UPDATE_COUNTER(ar, name);                                 \
+        if (err) {                                                      \
+                *ret = err;                                             \
+                return buf;                                             \
+        }                                                               \
+                                                                        \
+        TALLY_SUM_UP(ar, name);                                         \
+                                                                        \
+        for (i = 0; i < ARRAY_SIZE(name##_regs); i++) {                 \
+                ADD(buf, *ret, max_len, "%22s = %" f "[+%" f "]\n",     \
+                    name##_regs[i].nreg, ar->debug.stats.name ##_sum[i],\
+                    ar->debug.stats.name ##_counter[i]);                \
+        }                                                               \
+                                                                        \
+        return buf;                                                     \
+}                                                                       \
+DEBUGFS_DECLARE_RO_FILE(name, 0);
+
+#define DEBUGFS_HW_REG_FILE(name, f)                                    \
+static char *carl9170_debugfs_##name ## _read(struct ar9170 *ar,        \
+        char *dum, size_t bufsize, ssize_t *ret)                        \
+{                                                                       \
+        char *buf;                                                      \
+        int i, max_len, err;                                            \
+                                                                        \
+        max_len = ARRAY_SIZE(name##_regs) * 80;                         \
+        buf = vmalloc(max_len);                                         \
+        if (!buf)                                                       \
+                return NULL;                                            \
+                                                                        \
+        err = UPDATE_COUNTER(ar, name);                                 \
+        if (err) {                                                      \
+                *ret = err;                                             \
+                return buf;                                             \
+        }                                                               \
+                                                                        \
+        for (i = 0; i < ARRAY_SIZE(name##_regs); i++) {                 \
+                ADD(buf, *ret, max_len, "%22s = %" f "\n",              \
+                    name##_regs[i].nreg,                                \
+                    ar->debug.stats.name##_counter[i]);                 \
+        }                                                               \
+                                                                        \
+        return buf;                                                     \
+}                                                                       \
+DEBUGFS_DECLARE_RO_FILE(name, 0);
+
+static ssize_t carl9170_debugfs_hw_ioread32_write(struct ar9170 *ar,
+        const char *buf, size_t count)
+{
+        int err = 0, i, n = 0, max_len = 32, res;
+        unsigned int reg, tmp;
+
+        if (!count)
+                return 0;
+
+        if (count > max_len)
+                return -E2BIG;
+
+        res = sscanf(buf, "0x%X %d", &reg, &n);
+        if (res < 1) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        if (res == 1)
+                n = 1;
+
+        if (n > 15) {
+                err = -EMSGSIZE;
+                goto out;
+        }
+
+        if ((reg >= 0x280000) || ((reg + (n << 2)) >= 0x280000)) {
+                err = -EADDRNOTAVAIL;
+                goto out;
+        }
+
+        if (reg & 3) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        for (i = 0; i < n; i++) {
+                err = carl9170_read_reg(ar, reg + (i << 2), &tmp);
+                if (err)
+                        goto out;
+
+                ar->debug.ring[ar->debug.ring_tail].reg = reg + (i << 2);
+                ar->debug.ring[ar->debug.ring_tail].value = tmp;
+                ar->debug.ring_tail++;
+                ar->debug.ring_tail %= CARL9170_DEBUG_RING_SIZE;
+        }
+
+out:
+        return err ? err : count;
+}
+
+static char *carl9170_debugfs_hw_ioread32_read(struct ar9170 *ar, char *buf,
+                                               size_t bufsize, ssize_t *ret)
+{
+        int i = 0;
+
+        while (ar->debug.ring_head != ar->debug.ring_tail) {
+                ADD(buf, *ret, bufsize, "%.8x = %.8x\n",
+                    ar->debug.ring[ar->debug.ring_head].reg,
+                    ar->debug.ring[ar->debug.ring_head].value);
+
+                ar->debug.ring_head++;
+                ar->debug.ring_head %= CARL9170_DEBUG_RING_SIZE;
+
+                if (i++ == 64)
+                        break;
+        }
+        ar->debug.ring_head = ar->debug.ring_tail;
+        return buf;
+}
+DEBUGFS_DECLARE_RW_FILE(hw_ioread32, CARL9170_DEBUG_RING_SIZE * 40);
+
+static ssize_t carl9170_debugfs_bug_write(struct ar9170 *ar, const char *buf,
+                                          size_t count)
+{
+        int err;
+
+        if (count < 1)
+                return -EINVAL;
+
+        switch (buf[0]) {
+        case 'F':
+                ar->needs_full_reset = true;
+                break;
+
+        case 'R':
+                if (!IS_STARTED(ar)) {
+                        err = -EAGAIN;
+                        goto out;
+                }
+
+                ar->needs_full_reset = false;
+                break;
+
+        case 'M':
+                err = carl9170_mac_reset(ar);
+                if (err < 0)
+                        count = err;
+
+                goto out;
+
+        case 'P':
+                err = carl9170_set_channel(ar, ar->hw->conf.channel,
+                        ar->hw->conf.channel_type, CARL9170_RFI_COLD);
+                if (err < 0)
+                        count = err;
+
+                goto out;
+
+        default:
+                return -EINVAL;
+        }
+
+        carl9170_restart(ar, CARL9170_RR_USER_REQUEST);
+
+out:
+        return count;
+}
+
+static char *carl9170_debugfs_bug_read(struct ar9170 *ar, char *buf,
+                                       size_t bufsize, ssize_t *ret)
+{
+        ADD(buf, *ret, bufsize, "[P]hy reinit, [R]estart, [F]ull usb reset, "
+            "[M]ac reset\n");
+        ADD(buf, *ret, bufsize, "firmware restarts:%d, last reason:%d\n",
+                ar->restart_counter, ar->last_reason);
+        ADD(buf, *ret, bufsize, "phy reinit errors:%d (%d)\n",
+                ar->total_chan_fail, ar->chan_fail);
+        ADD(buf, *ret, bufsize, "reported firmware errors:%d\n",
+                ar->fw.err_counter);
+        ADD(buf, *ret, bufsize, "reported firmware BUGs:%d\n",
+                ar->fw.bug_counter);
+        ADD(buf, *ret, bufsize, "pending restart requests:%d\n",
+                atomic_read(&ar->pending_restarts));
+        return buf;
+}
+__DEBUGFS_DECLARE_RW_FILE(bug, 400, CARL9170_STOPPED);
+
+static const char *erp_modes[] = {
+        [CARL9170_ERP_INVALID] = "INVALID",
+        [CARL9170_ERP_AUTO] = "Automatic",
+        [CARL9170_ERP_MAC80211] = "Set by MAC80211",
+        [CARL9170_ERP_OFF] = "Force Off",
+        [CARL9170_ERP_RTS] = "Force RTS",
+        [CARL9170_ERP_CTS] = "Force CTS"
+};
+
+static char *carl9170_debugfs_erp_read(struct ar9170 *ar, char *buf,
+                                       size_t bufsize, ssize_t *ret)
+{
+        ADD(buf, *ret, bufsize, "ERP Setting: (%d) -> %s\n", ar->erp_mode,
+            erp_modes[ar->erp_mode]);
+        return buf;
+}
+
+static ssize_t carl9170_debugfs_erp_write(struct ar9170 *ar, const char *buf,
+                                          size_t count)
+{
+        int res, val;
+
+        if (count < 1)
+                return -EINVAL;
+
+        res = sscanf(buf, "%d", &val);
+        if (res != 1)
+                return -EINVAL;
+
+        if (!((val > CARL9170_ERP_INVALID) &&
+              (val < __CARL9170_ERP_NUM)))
+                return -EINVAL;
+
+        ar->erp_mode = val;
+        return count;
+}
+
+DEBUGFS_DECLARE_RW_FILE(erp, 80);
+
+static ssize_t carl9170_debugfs_hw_iowrite32_write(struct ar9170 *ar,
+        const char *buf, size_t count)
+{
+        int err = 0, max_len = 22, res;
+        u32 reg, val;
+
+        if (!count)
+                return 0;
+
+        if (count > max_len)
+                return -E2BIG;
+
+        res = sscanf(buf, "0x%X 0x%X", &reg, &val);
+        if (res != 2) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        if (reg <= 0x100000 || reg >= 0x280000) {
+                err = -EADDRNOTAVAIL;
+                goto out;
+        }
+
+        if (reg & 3) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        err = carl9170_write_reg(ar, reg, val);
+        if (err)
+                goto out;
+
+out:
+        return err ? err : count;
+}
+DEBUGFS_DECLARE_WO_FILE(hw_iowrite32);
+
+DEBUGFS_HW_TALLY_FILE(hw_tx_tally, "u");
+DEBUGFS_HW_TALLY_FILE(hw_rx_tally, "u");
+DEBUGFS_HW_TALLY_FILE(hw_phy_errors, "u");
+DEBUGFS_HW_REG_FILE(hw_wlan_queue, ".8x");
+DEBUGFS_HW_REG_FILE(hw_pta_queue, ".8x");
+DEBUGFS_HW_REG_FILE(hw_ampdu_info, ".8x");
+DEBUGFS_QUEUE_DUMP(tx_status, 0);
+DEBUGFS_QUEUE_DUMP(tx_status, 1);
+DEBUGFS_QUEUE_DUMP(tx_status, 2);
+DEBUGFS_QUEUE_DUMP(tx_status, 3);
+DEBUGFS_QUEUE_DUMP(tx_pending, 0);
+DEBUGFS_QUEUE_DUMP(tx_pending, 1);
+DEBUGFS_QUEUE_DUMP(tx_pending, 2);
+DEBUGFS_QUEUE_DUMP(tx_pending, 3);
+DEBUGFS_READONLY_FILE(usb_tx_anch_urbs, 20, "%d",
+                      atomic_read(&ar->tx_anch_urbs));
+DEBUGFS_READONLY_FILE(usb_rx_anch_urbs, 20, "%d",
+                      atomic_read(&ar->rx_anch_urbs));
+DEBUGFS_READONLY_FILE(usb_rx_work_urbs, 20, "%d",
+                      atomic_read(&ar->rx_work_urbs));
+DEBUGFS_READONLY_FILE(usb_rx_pool_urbs, 20, "%d",
+                      atomic_read(&ar->rx_pool_urbs));
+
+DEBUGFS_READONLY_FILE(tx_total_queued, 20, "%d",
+                      atomic_read(&ar->tx_total_queued));
+DEBUGFS_READONLY_FILE(tx_ampdu_scheduler, 20, "%d",
+                      atomic_read(&ar->tx_ampdu_scheduler));
+
+DEBUGFS_READONLY_FILE(tx_total_pending, 20, "%d",
+                      atomic_read(&ar->tx_total_pending));
+
+DEBUGFS_READONLY_FILE(tx_ampdu_list_len, 20, "%d",
+                      ar->tx_ampdu_list_len);
+
+DEBUGFS_READONLY_FILE(tx_ampdu_upload, 20, "%d",
+                      atomic_read(&ar->tx_ampdu_upload));
+
+DEBUGFS_READONLY_FILE(tx_janitor_last_run, 64, "last run:%d ms ago",
+        jiffies_to_msecs(jiffies - ar->tx_janitor_last_run));
+
+DEBUGFS_READONLY_FILE(tx_dropped, 20, "%d", ar->tx_dropped);
+
+DEBUGFS_READONLY_FILE(rx_dropped, 20, "%d", ar->rx_dropped);
+
+DEBUGFS_READONLY_FILE(sniffer_enabled, 20, "%d", ar->sniffer_enabled);
+DEBUGFS_READONLY_FILE(rx_software_decryption, 20, "%d",
+                      ar->rx_software_decryption);
+DEBUGFS_READONLY_FILE(ampdu_factor, 20, "%d",
+                      ar->current_factor);
+DEBUGFS_READONLY_FILE(ampdu_density, 20, "%d",
+                      ar->current_density);
+
+DEBUGFS_READONLY_FILE(beacon_int, 20, "%d TU", ar->global_beacon_int);
+DEBUGFS_READONLY_FILE(pretbtt, 20, "%d TU", ar->global_pretbtt);
+
+void carl9170_debugfs_register(struct ar9170 *ar)
+{
+        ar->debug_dir = debugfs_create_dir(KBUILD_MODNAME,
+                ar->hw->wiphy->debugfsdir);
+
+#define DEBUGFS_ADD(name)                                               \
+        debugfs_create_file(#name, carl_debugfs_##name ##_ops.attr,     \
+                            ar->debug_dir, ar,                          \
+                            &carl_debugfs_##name ## _ops.fops);
+
+        DEBUGFS_ADD(usb_tx_anch_urbs);
+        DEBUGFS_ADD(usb_rx_pool_urbs);
+        DEBUGFS_ADD(usb_rx_anch_urbs);
+        DEBUGFS_ADD(usb_rx_work_urbs);
+
+        DEBUGFS_ADD(tx_total_queued);
+        DEBUGFS_ADD(tx_total_pending);
+        DEBUGFS_ADD(tx_dropped);
+        DEBUGFS_ADD(tx_stuck);
+        DEBUGFS_ADD(tx_ampdu_upload);
+        DEBUGFS_ADD(tx_ampdu_scheduler);
+        DEBUGFS_ADD(tx_ampdu_list_len);
+
+        DEBUGFS_ADD(rx_dropped);
+        DEBUGFS_ADD(sniffer_enabled);
+        DEBUGFS_ADD(rx_software_decryption);
+
+        DEBUGFS_ADD(mem_usage);
+        DEBUGFS_ADD(qos_stat);
+        DEBUGFS_ADD(sta_psm);
+        DEBUGFS_ADD(ampdu_state);
+
+        DEBUGFS_ADD(hw_tx_tally);
+        DEBUGFS_ADD(hw_rx_tally);
+        DEBUGFS_ADD(hw_phy_errors);
+        DEBUGFS_ADD(phy_noise);
+
+        DEBUGFS_ADD(hw_wlan_queue);
+        DEBUGFS_ADD(hw_pta_queue);
+        DEBUGFS_ADD(hw_ampdu_info);
+
+        DEBUGFS_ADD(ampdu_density);
+        DEBUGFS_ADD(ampdu_factor);
+
+        DEBUGFS_ADD(tx_janitor_last_run);
+
+        DEBUGFS_ADD(tx_status_0);
+        DEBUGFS_ADD(tx_status_1);
+        DEBUGFS_ADD(tx_status_2);
+        DEBUGFS_ADD(tx_status_3);
+
+        DEBUGFS_ADD(tx_pending_0);
+        DEBUGFS_ADD(tx_pending_1);
+        DEBUGFS_ADD(tx_pending_2);
+        DEBUGFS_ADD(tx_pending_3);
+
+        DEBUGFS_ADD(hw_ioread32);
+        DEBUGFS_ADD(hw_iowrite32);
+        DEBUGFS_ADD(bug);
+
+        DEBUGFS_ADD(erp);
+
+        DEBUGFS_ADD(vif_dump);
+
+        DEBUGFS_ADD(beacon_int);
+        DEBUGFS_ADD(pretbtt);
+
+#undef DEBUGFS_ADD
+}
+
+void carl9170_debugfs_unregister(struct ar9170 *ar)
+{
+        debugfs_remove_recursive(ar->debug_dir);
+}
diff --git a/drivers/net/wireless/ath/carl9170/debug.h b/drivers/net/wireless/ath/carl9170/debug.h
new file mode 100644
index 000000000000..ea4b97524122
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/debug.h
@@ -0,0 +1,134 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * debug header
+ *
+ * Copyright 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#include "eeprom.h"
+#include "wlan.h"
+#include "hw.h"
+#include "fwdesc.h"
+#include "fwcmd.h"
+#include "../regd.h"
+
+struct hw_stat_reg_entry {
+        u32 reg;
+        char nreg[32];
+};
+
+#define STAT_MAC_REG(reg)       \
+        { (AR9170_MAC_REG_##reg), #reg }
+
+#define STAT_PTA_REG(reg)       \
+        { (AR9170_PTA_REG_##reg), #reg }
+
+#define STAT_USB_REG(reg)       \
+        { (AR9170_USB_REG_##reg), #reg }
+
+static const struct hw_stat_reg_entry hw_rx_tally_regs[] = {
+        STAT_MAC_REG(RX_CRC32),         STAT_MAC_REG(RX_CRC16),
+        STAT_MAC_REG(RX_TIMEOUT_COUNT), STAT_MAC_REG(RX_ERR_DECRYPTION_UNI),
+        STAT_MAC_REG(RX_ERR_DECRYPTION_MUL), STAT_MAC_REG(RX_MPDU),
+        STAT_MAC_REG(RX_DROPPED_MPDU),  STAT_MAC_REG(RX_DEL_MPDU),
+};
+
+static const struct hw_stat_reg_entry hw_phy_errors_regs[] = {
+        STAT_MAC_REG(RX_PHY_MISC_ERROR), STAT_MAC_REG(RX_PHY_XR_ERROR),
+        STAT_MAC_REG(RX_PHY_OFDM_ERROR), STAT_MAC_REG(RX_PHY_CCK_ERROR),
+        STAT_MAC_REG(RX_PHY_HT_ERROR), STAT_MAC_REG(RX_PHY_TOTAL),
+};
+
+static const struct hw_stat_reg_entry hw_tx_tally_regs[] = {
+        STAT_MAC_REG(TX_TOTAL),         STAT_MAC_REG(TX_UNDERRUN),
+        STAT_MAC_REG(TX_RETRY),
+};
+
+static const struct hw_stat_reg_entry hw_wlan_queue_regs[] = {
+        STAT_MAC_REG(DMA_STATUS),       STAT_MAC_REG(DMA_TRIGGER),
+        STAT_MAC_REG(DMA_TXQ0_ADDR),    STAT_MAC_REG(DMA_TXQ0_CURR_ADDR),
+        STAT_MAC_REG(DMA_TXQ1_ADDR),    STAT_MAC_REG(DMA_TXQ1_CURR_ADDR),
+        STAT_MAC_REG(DMA_TXQ2_ADDR),    STAT_MAC_REG(DMA_TXQ2_CURR_ADDR),
+        STAT_MAC_REG(DMA_TXQ3_ADDR),    STAT_MAC_REG(DMA_TXQ3_CURR_ADDR),
+        STAT_MAC_REG(DMA_RXQ_ADDR),     STAT_MAC_REG(DMA_RXQ_CURR_ADDR),
+};
+
+static const struct hw_stat_reg_entry hw_ampdu_info_regs[] = {
+        STAT_MAC_REG(AMPDU_DENSITY),    STAT_MAC_REG(AMPDU_FACTOR),
+};
+
+static const struct hw_stat_reg_entry hw_pta_queue_regs[] = {
+        STAT_PTA_REG(DN_CURR_ADDRH),    STAT_PTA_REG(DN_CURR_ADDRL),
+        STAT_PTA_REG(UP_CURR_ADDRH),    STAT_PTA_REG(UP_CURR_ADDRL),
+        STAT_PTA_REG(DMA_STATUS),       STAT_PTA_REG(DMA_MODE_CTRL),
+};
+
+#define DEFINE_TALLY(name)                                      \
+        u32 name##_sum[ARRAY_SIZE(name##_regs)],                \
+            name##_counter[ARRAY_SIZE(name##_regs)]             \
+
+#define DEFINE_STAT(name)                                       \
+        u32 name##_counter[ARRAY_SIZE(name##_regs)]             \
+
+struct ath_stats {
+        DEFINE_TALLY(hw_tx_tally);
+        DEFINE_TALLY(hw_rx_tally);
+        DEFINE_TALLY(hw_phy_errors);
+        DEFINE_STAT(hw_wlan_queue);
+        DEFINE_STAT(hw_pta_queue);
+        DEFINE_STAT(hw_ampdu_info);
+};
+
+struct carl9170_debug_mem_rbe {
+        u32 reg;
+        u32 value;
+};
+
+#define CARL9170_DEBUG_RING_SIZE                        64
+
+struct carl9170_debug {
+        struct ath_stats stats;
+        struct carl9170_debug_mem_rbe ring[CARL9170_DEBUG_RING_SIZE];
+        struct mutex ring_lock;
+        unsigned int ring_head, ring_tail;
+        struct delayed_work update_tally;
+};
+
+struct ar9170;
+
+void carl9170_debugfs_register(struct ar9170 *ar);
+void carl9170_debugfs_unregister(struct ar9170 *ar);
+#endif /* __DEBUG_H */
diff --git a/drivers/net/wireless/ath/ar9170/eeprom.h b/drivers/net/wireless/ath/carl9170/eeprom.h
index 6c4663883423..7cff40ac7759 100644
--- a/drivers/net/wireless/ath/ar9170/eeprom.h
+++ b/drivers/net/wireless/ath/carl9170/eeprom.h
@@ -1,5 +1,5 @@
 /*
- * Atheros AR9170 driver
+ * Shared Atheros AR9170 Header
  *
  * EEPROM layout
  *
@@ -35,8 +35,10 @@
  *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#ifndef __AR9170_EEPROM_H
-#define __AR9170_EEPROM_H
+#ifndef __CARL9170_SHARED_EEPROM_H
+#define __CARL9170_SHARED_EEPROM_H
+
+#define AR9170_EEPROM_START             0x1600
 
 #define AR5416_MAX_CHAINS               2
 #define AR5416_MODAL_SPURS              5
@@ -121,7 +123,6 @@ struct ar9170_calctl_data {
                 control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 } __packed;
 
-
 struct ar9170_eeprom {
         __le16  length;
         __le16  checksum;
@@ -176,4 +177,40 @@ struct ar9170_eeprom {
         __le16  subsystem_id;
 } __packed;
 
-#endif /* __AR9170_EEPROM_H */
+#define AR9170_LED_MODE_POWER_ON                0x0001
+#define AR9170_LED_MODE_RESERVED                0x0002
+#define AR9170_LED_MODE_DISABLE_STATE           0x0004
+#define AR9170_LED_MODE_OFF_IN_PSM              0x0008
+
+/* AR9170_LED_MODE BIT is set */
+#define AR9170_LED_MODE_FREQUENCY_S             4
+#define AR9170_LED_MODE_FREQUENCY               0x0030
+#define AR9170_LED_MODE_FREQUENCY_1HZ           0x0000
+#define AR9170_LED_MODE_FREQUENCY_0_5HZ         0x0010
+#define AR9170_LED_MODE_FREQUENCY_0_25HZ        0x0020
+#define AR9170_LED_MODE_FREQUENCY_0_125HZ       0x0030
+
+/* AR9170_LED_MODE BIT is not set */
+#define AR9170_LED_MODE_CONN_STATE_S            4
+#define AR9170_LED_MODE_CONN_STATE              0x0030
+#define AR9170_LED_MODE_CONN_STATE_FORCE_OFF    0x0000
+#define AR9170_LED_MODE_CONN_STATE_FORCE_ON     0x0010
+/* Idle off / Active on */
+#define AR9170_LED_MODE_CONN_STATE_IOFF_AON     0x0020
+/* Idle on / Active off */
+#define AR9170_LED_MODE_CONN_STATE_ION_AOFF     0x0010
+
+#define AR9170_LED_MODE_MODE                    0x0040
+#define AR9170_LED_MODE_RESERVED2               0x0080
+
+#define AR9170_LED_MODE_TON_SCAN_S              8
+#define AR9170_LED_MODE_TON_SCAN                0x0f00
+
+#define AR9170_LED_MODE_TOFF_SCAN_S             12
+#define AR9170_LED_MODE_TOFF_SCAN               0xf000
+
+struct ar9170_led_mode {
+        __le16 led;
+};
+
+#endif /* __CARL9170_SHARED_EEPROM_H */
diff --git a/drivers/net/wireless/ath/carl9170/fw.c b/drivers/net/wireless/ath/carl9170/fw.c
new file mode 100644
index 000000000000..221957c5d373
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/fw.c
@@ -0,0 +1,435 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * firmware parser
+ *
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ */
+
+#include <linux/kernel.h>
+#include <linux/firmware.h>
+#include <linux/crc32.h>
+#include "carl9170.h"
+#include "fwcmd.h"
+#include "version.h"
+
+#define MAKE_STR(symbol) #symbol
+#define TO_STR(symbol) MAKE_STR(symbol)
+#define CARL9170FW_API_VER_STR TO_STR(CARL9170FW_API_MAX_VER)
+MODULE_VERSION(CARL9170FW_API_VER_STR ":" CARL9170FW_VERSION_GIT);
+
+static const u8 otus_magic[4] = { OTUS_MAGIC };
+
+static const void *carl9170_fw_find_desc(struct ar9170 *ar, const u8 descid[4],
+        const unsigned int len, const u8 compatible_revision)
+{
+        const struct carl9170fw_desc_head *iter;
+
+        carl9170fw_for_each_hdr(iter, ar->fw.desc) {
+                if (carl9170fw_desc_cmp(iter, descid, len,
+                                        compatible_revision))
+                        return (void *)iter;
+        }
+
+        /* needed to find the LAST desc */
+        if (carl9170fw_desc_cmp(iter, descid, len,
+                                compatible_revision))
+                return (void *)iter;
+
+        return NULL;
+}
+
+static int carl9170_fw_verify_descs(struct ar9170 *ar,
+        const struct carl9170fw_desc_head *head, unsigned int max_len)
+{
+        const struct carl9170fw_desc_head *pos;
+        unsigned long pos_addr, end_addr;
+        unsigned int pos_length;
+
+        if (max_len < sizeof(*pos))
+                return -ENODATA;
+
+        max_len = min_t(unsigned int, CARL9170FW_DESC_MAX_LENGTH, max_len);
+
+        pos = head;
+        pos_addr = (unsigned long) pos;
+        end_addr = pos_addr + max_len;
+
+        while (pos_addr < end_addr) {
+                if (pos_addr + sizeof(*head) > end_addr)
+                        return -E2BIG;
+
+                pos_length = le16_to_cpu(pos->length);
+
+                if (pos_length < sizeof(*head))
+                        return -EBADMSG;
+
+                if (pos_length > max_len)
+                        return -EOVERFLOW;
+
+                if (pos_addr + pos_length > end_addr)
+                        return -EMSGSIZE;
+
+                if (carl9170fw_desc_cmp(pos, LAST_MAGIC,
+                                        CARL9170FW_LAST_DESC_SIZE,
+                                        CARL9170FW_LAST_DESC_CUR_VER))
+                        return 0;
+
+                pos_addr += pos_length;
+                pos = (void *)pos_addr;
+                max_len -= pos_length;
+        }
+        return -EINVAL;
+}
+
+static void carl9170_fw_info(struct ar9170 *ar)
+{
+        const struct carl9170fw_motd_desc *motd_desc;
+        unsigned int str_ver_len;
+        u32 fw_date;
+
+        dev_info(&ar->udev->dev, "driver   API: %s 2%03d-%02d-%02d [%d-%d]\n",
+                CARL9170FW_VERSION_GIT, CARL9170FW_VERSION_YEAR,
+                CARL9170FW_VERSION_MONTH, CARL9170FW_VERSION_DAY,
+                CARL9170FW_API_MIN_VER, CARL9170FW_API_MAX_VER);
+
+        motd_desc = carl9170_fw_find_desc(ar, MOTD_MAGIC,
+                sizeof(*motd_desc), CARL9170FW_MOTD_DESC_CUR_VER);
+
+        if (motd_desc) {
+                str_ver_len = strnlen(motd_desc->release,
+                        CARL9170FW_MOTD_RELEASE_LEN);
+
+                fw_date = le32_to_cpu(motd_desc->fw_year_month_day);
+
+                dev_info(&ar->udev->dev, "firmware API: %.*s 2%03d-%02d-%02d\n",
+                         str_ver_len, motd_desc->release,
+                         CARL9170FW_GET_YEAR(fw_date),
+                         CARL9170FW_GET_MONTH(fw_date),
+                         CARL9170FW_GET_DAY(fw_date));
+
+                strlcpy(ar->hw->wiphy->fw_version, motd_desc->release,
+                        sizeof(ar->hw->wiphy->fw_version));
+        }
+}
+
+static bool valid_dma_addr(const u32 address)
+{
+        if (address >= AR9170_SRAM_OFFSET &&
+            address < (AR9170_SRAM_OFFSET + AR9170_SRAM_SIZE))
+                return true;
+
+        return false;
+}
+
+static bool valid_cpu_addr(const u32 address)
+{
+        if (valid_dma_addr(address) || (address >= AR9170_PRAM_OFFSET &&
+            address < (AR9170_PRAM_OFFSET + AR9170_PRAM_SIZE)))
+                return true;
+
+        return false;
+}
+
+static int carl9170_fw(struct ar9170 *ar, const __u8 *data, size_t len)
+{
+        const struct carl9170fw_otus_desc *otus_desc;
+        const struct carl9170fw_chk_desc *chk_desc;
+        const struct carl9170fw_last_desc *last_desc;
+        const struct carl9170fw_txsq_desc *txsq_desc;
+        u16 if_comb_types;
+
+        last_desc = carl9170_fw_find_desc(ar, LAST_MAGIC,
+                sizeof(*last_desc), CARL9170FW_LAST_DESC_CUR_VER);
+        if (!last_desc)
+                return -EINVAL;
+
+        otus_desc = carl9170_fw_find_desc(ar, OTUS_MAGIC,
+                sizeof(*otus_desc), CARL9170FW_OTUS_DESC_CUR_VER);
+        if (!otus_desc) {
+                dev_err(&ar->udev->dev, "failed to find compatible firmware "
+                        "descriptor.\n");
+                return -ENODATA;
+        }
+
+        chk_desc = carl9170_fw_find_desc(ar, CHK_MAGIC,
+                sizeof(*chk_desc), CARL9170FW_CHK_DESC_CUR_VER);
+
+        if (chk_desc) {
+                unsigned long fin, diff;
+                unsigned int dsc_len;
+                u32 crc32;
+
+                dsc_len = min_t(unsigned int, len,
+                        (unsigned long)chk_desc - (unsigned long)otus_desc);
+
+                fin = (unsigned long) last_desc + sizeof(*last_desc);
+                diff = fin - (unsigned long) otus_desc;
+
+                if (diff < len)
+                        len -= diff;
+
+                if (len < 256)
+                        return -EIO;
+
+                crc32 = crc32_le(~0, data, len);
+                if (cpu_to_le32(crc32) != chk_desc->fw_crc32) {
+                        dev_err(&ar->udev->dev, "fw checksum test failed.\n");
+                        return -ENOEXEC;
+                }
+
+                crc32 = crc32_le(crc32, (void *)otus_desc, dsc_len);
+                if (cpu_to_le32(crc32) != chk_desc->hdr_crc32) {
+                        dev_err(&ar->udev->dev, "descriptor check failed.\n");
+                        return -EINVAL;
+                }
+        } else {
+                dev_warn(&ar->udev->dev, "Unprotected firmware image.\n");
+        }
+
+#define SUPP(feat)                                              \
+        (carl9170fw_supports(otus_desc->feature_set, feat))
+
+        if (!SUPP(CARL9170FW_DUMMY_FEATURE)) {
+                dev_err(&ar->udev->dev, "invalid firmware descriptor "
+                        "format detected.\n");
+                return -EINVAL;
+        }
+
+        ar->fw.api_version = otus_desc->api_ver;
+
+        if (ar->fw.api_version < CARL9170FW_API_MIN_VER ||
+            ar->fw.api_version > CARL9170FW_API_MAX_VER) {
+                dev_err(&ar->udev->dev, "unsupported firmware api version.\n");
+                return -EINVAL;
+        }
+
+        if (!SUPP(CARL9170FW_COMMAND_PHY) || SUPP(CARL9170FW_UNUSABLE) ||
+            !SUPP(CARL9170FW_HANDLE_BACK_REQ)) {
+                dev_err(&ar->udev->dev, "firmware does support "
+                        "mandatory features.\n");
+                return -ECANCELED;
+        }
+
+        if (ilog2(le32_to_cpu(otus_desc->feature_set)) >=
+                __CARL9170FW_FEATURE_NUM) {
+                dev_warn(&ar->udev->dev, "driver does not support all "
+                         "firmware features.\n");
+        }
+
+        if (!SUPP(CARL9170FW_COMMAND_CAM)) {
+                dev_info(&ar->udev->dev, "crypto offloading is disabled "
+                         "by firmware.\n");
+                ar->disable_offload = true;
+        }
+
+        if (SUPP(CARL9170FW_PSM))
+                ar->hw->flags |= IEEE80211_HW_SUPPORTS_PS;
+
+        if (!SUPP(CARL9170FW_USB_INIT_FIRMWARE)) {
+                dev_err(&ar->udev->dev, "firmware does not provide "
+                        "mandatory interfaces.\n");
+                return -EINVAL;
+        }
+
+        if (SUPP(CARL9170FW_MINIBOOT))
+                ar->fw.offset = le16_to_cpu(otus_desc->miniboot_size);
+        else
+                ar->fw.offset = 0;
+
+        if (SUPP(CARL9170FW_USB_DOWN_STREAM)) {
+                ar->hw->extra_tx_headroom += sizeof(struct ar9170_stream);
+                ar->fw.tx_stream = true;
+        }
+
+        if (SUPP(CARL9170FW_USB_UP_STREAM))
+                ar->fw.rx_stream = true;
+
+        if (SUPP(CARL9170FW_RX_FILTER)) {
+                ar->fw.rx_filter = true;
+                ar->rx_filter_caps = FIF_FCSFAIL | FIF_PLCPFAIL |
+                        FIF_CONTROL | FIF_PSPOLL | FIF_OTHER_BSS |
+                        FIF_PROMISC_IN_BSS;
+        }
+
+        if (SUPP(CARL9170FW_WOL))
+                device_set_wakeup_enable(&ar->udev->dev, true);
+
+        if_comb_types = BIT(NL80211_IFTYPE_STATION) |
+                        BIT(NL80211_IFTYPE_P2P_CLIENT);
+
+        ar->fw.vif_num = otus_desc->vif_num;
+        ar->fw.cmd_bufs = otus_desc->cmd_bufs;
+        ar->fw.address = le32_to_cpu(otus_desc->fw_address);
+        ar->fw.rx_size = le16_to_cpu(otus_desc->rx_max_frame_len);
+        ar->fw.mem_blocks = min_t(unsigned int, otus_desc->tx_descs, 0xfe);
+        atomic_set(&ar->mem_free_blocks, ar->fw.mem_blocks);
+        ar->fw.mem_block_size = le16_to_cpu(otus_desc->tx_frag_len);
+
+        if (ar->fw.vif_num >= AR9170_MAX_VIRTUAL_MAC || !ar->fw.vif_num ||
+            ar->fw.mem_blocks < 16 || !ar->fw.cmd_bufs ||
+            ar->fw.mem_block_size < 64 || ar->fw.mem_block_size > 512 ||
+            ar->fw.rx_size > 32768 || ar->fw.rx_size < 4096 ||
+            !valid_cpu_addr(ar->fw.address)) {
+                dev_err(&ar->udev->dev, "firmware shows obvious signs of "
+                        "malicious tampering.\n");
+                return -EINVAL;
+        }
+
+        ar->fw.beacon_addr = le32_to_cpu(otus_desc->bcn_addr);
+        ar->fw.beacon_max_len = le16_to_cpu(otus_desc->bcn_len);
+
+        if (valid_dma_addr(ar->fw.beacon_addr) && ar->fw.beacon_max_len >=
+            AR9170_MAC_BCN_LENGTH_MAX) {
+                ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC);
+
+                if (SUPP(CARL9170FW_WLANTX_CAB)) {
+                        if_comb_types |=
+                                BIT(NL80211_IFTYPE_AP) |
+                                BIT(NL80211_IFTYPE_P2P_GO);
+                }
+        }
+
+        ar->if_comb_limits[0].max = ar->fw.vif_num;
+        ar->if_comb_limits[0].types = if_comb_types;
+
+        ar->if_combs[0].num_different_channels = 1;
+        ar->if_combs[0].max_interfaces = ar->fw.vif_num;
+        ar->if_combs[0].limits = ar->if_comb_limits;
+        ar->if_combs[0].n_limits = ARRAY_SIZE(ar->if_comb_limits);
+
+        ar->hw->wiphy->iface_combinations = ar->if_combs;
+        ar->hw->wiphy->n_iface_combinations = ARRAY_SIZE(ar->if_combs);
+
+        ar->hw->wiphy->interface_modes |= if_comb_types;
+
+        txsq_desc = carl9170_fw_find_desc(ar, TXSQ_MAGIC,
+                sizeof(*txsq_desc), CARL9170FW_TXSQ_DESC_CUR_VER);
+
+        if (txsq_desc) {
+                ar->fw.tx_seq_table = le32_to_cpu(txsq_desc->seq_table_addr);
+                if (!valid_cpu_addr(ar->fw.tx_seq_table))
+                        return -EINVAL;
+        } else {
+                ar->fw.tx_seq_table = 0;
+        }
+
+#undef SUPPORTED
+        return 0;
+}
+
+static struct carl9170fw_desc_head *
+carl9170_find_fw_desc(struct ar9170 *ar, const __u8 *fw_data, const size_t len)
+
+{
+        int scan = 0, found = 0;
+
+        if (!carl9170fw_size_check(len)) {
+                dev_err(&ar->udev->dev, "firmware size is out of bound.\n");
+                return NULL;
+        }
+
+        while (scan < len - sizeof(struct carl9170fw_desc_head)) {
+                if (fw_data[scan++] == otus_magic[found])
+                        found++;
+                else
+                        found = 0;
+
+                if (scan >= len)
+                        break;
+
+                if (found == sizeof(otus_magic))
+                        break;
+        }
+
+        if (found != sizeof(otus_magic))
+                return NULL;
+
+        return (void *)&fw_data[scan - found];
+}
+
+int carl9170_fw_fix_eeprom(struct ar9170 *ar)
+{
+        const struct carl9170fw_fix_desc *fix_desc = NULL;
+        unsigned int i, n, off;
+        u32 *data = (void *)&ar->eeprom;
+
+        fix_desc = carl9170_fw_find_desc(ar, FIX_MAGIC,
+                sizeof(*fix_desc), CARL9170FW_FIX_DESC_CUR_VER);
+
+        if (!fix_desc)
+                return 0;
+
+        n = (le16_to_cpu(fix_desc->head.length) - sizeof(*fix_desc)) /
+            sizeof(struct carl9170fw_fix_entry);
+
+        for (i = 0; i < n; i++) {
+                off = le32_to_cpu(fix_desc->data[i].address) -
+                      AR9170_EEPROM_START;
+
+                if (off >= sizeof(struct ar9170_eeprom) || (off & 3)) {
+                        dev_err(&ar->udev->dev, "Skip invalid entry %d\n", i);
+                        continue;
+                }
+
+                data[off / sizeof(*data)] &=
+                        le32_to_cpu(fix_desc->data[i].mask);
+                data[off / sizeof(*data)] |=
+                        le32_to_cpu(fix_desc->data[i].value);
+        }
+
+        return 0;
+}
+
+int carl9170_parse_firmware(struct ar9170 *ar)
+{
+        const struct carl9170fw_desc_head *fw_desc = NULL;
+        const struct firmware *fw = ar->fw.fw;
+        unsigned long header_offset = 0;
+        int err;
+
+        if (WARN_ON(!fw))
+                return -EINVAL;
+
+        fw_desc = carl9170_find_fw_desc(ar, fw->data, fw->size);
+
+        if (!fw_desc) {
+                dev_err(&ar->udev->dev, "unsupported firmware.\n");
+                return -ENODATA;
+        }
+
+        header_offset = (unsigned long)fw_desc - (unsigned long)fw->data;
+
+        err = carl9170_fw_verify_descs(ar, fw_desc, fw->size - header_offset);
+        if (err) {
+                dev_err(&ar->udev->dev, "damaged firmware (%d).\n", err);
+                return err;
+        }
+
+        ar->fw.desc = fw_desc;
+
+        carl9170_fw_info(ar);
+
+        err = carl9170_fw(ar, fw->data, fw->size);
+        if (err) {
+                dev_err(&ar->udev->dev, "failed to parse firmware (%d).\n",
+                        err);
+                return err;
+        }
+
+        return 0;
+}
diff --git a/drivers/net/wireless/ath/carl9170/fwcmd.h b/drivers/net/wireless/ath/carl9170/fwcmd.h
new file mode 100644
index 000000000000..30449d21b762
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/fwcmd.h
@@ -0,0 +1,290 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * Firmware command interface definitions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_FWCMD_H
+#define __CARL9170_SHARED_FWCMD_H
+
+#define CARL9170_MAX_CMD_LEN            64
+#define CARL9170_MAX_CMD_PAYLOAD_LEN    60
+
+#define CARL9170FW_API_MIN_VER          1
+#define CARL9170FW_API_MAX_VER          1
+
+enum carl9170_cmd_oids {
+        CARL9170_CMD_RREG               = 0x00,
+        CARL9170_CMD_WREG               = 0x01,
+        CARL9170_CMD_ECHO               = 0x02,
+        CARL9170_CMD_SWRST              = 0x03,
+        CARL9170_CMD_REBOOT             = 0x04,
+        CARL9170_CMD_BCN_CTRL           = 0x05,
+        CARL9170_CMD_READ_TSF           = 0x06,
+        CARL9170_CMD_RX_FILTER          = 0x07,
+
+        /* CAM */
+        CARL9170_CMD_EKEY               = 0x10,
+        CARL9170_CMD_DKEY               = 0x11,
+
+        /* RF / PHY */
+        CARL9170_CMD_FREQUENCY          = 0x20,
+        CARL9170_CMD_RF_INIT            = 0x21,
+        CARL9170_CMD_SYNTH              = 0x22,
+        CARL9170_CMD_FREQ_START         = 0x23,
+        CARL9170_CMD_PSM                = 0x24,
+
+        /* Asychronous command flag */
+        CARL9170_CMD_ASYNC_FLAG         = 0x40,
+        CARL9170_CMD_WREG_ASYNC         = (CARL9170_CMD_WREG |
+                                           CARL9170_CMD_ASYNC_FLAG),
+        CARL9170_CMD_REBOOT_ASYNC       = (CARL9170_CMD_REBOOT |
+                                           CARL9170_CMD_ASYNC_FLAG),
+        CARL9170_CMD_BCN_CTRL_ASYNC     = (CARL9170_CMD_BCN_CTRL |
+                                           CARL9170_CMD_ASYNC_FLAG),
+        CARL9170_CMD_PSM_ASYNC          = (CARL9170_CMD_PSM |
+                                           CARL9170_CMD_ASYNC_FLAG),
+
+        /* responses and traps */
+        CARL9170_RSP_FLAG               = 0xc0,
+        CARL9170_RSP_PRETBTT            = 0xc0,
+        CARL9170_RSP_TXCOMP             = 0xc1,
+        CARL9170_RSP_BEACON_CONFIG      = 0xc2,
+        CARL9170_RSP_ATIM               = 0xc3,
+        CARL9170_RSP_WATCHDOG           = 0xc6,
+        CARL9170_RSP_TEXT               = 0xca,
+        CARL9170_RSP_HEXDUMP            = 0xcc,
+        CARL9170_RSP_RADAR              = 0xcd,
+        CARL9170_RSP_GPIO               = 0xce,
+        CARL9170_RSP_BOOT               = 0xcf,
+};
+
+struct carl9170_set_key_cmd {
+        __le16          user;
+        __le16          keyId;
+        __le16          type;
+        u8              macAddr[6];
+        u32             key[4];
+} __packed __aligned(4);
+#define CARL9170_SET_KEY_CMD_SIZE               28
+
+struct carl9170_disable_key_cmd {
+        __le16          user;
+        __le16          padding;
+} __packed __aligned(4);
+#define CARL9170_DISABLE_KEY_CMD_SIZE           4
+
+struct carl9170_u32_list {
+        u32     vals[0];
+} __packed;
+
+struct carl9170_reg_list {
+        __le32          regs[0];
+} __packed;
+
+struct carl9170_write_reg {
+        struct {
+                __le32          addr;
+                __le32          val;
+        } regs[0] __packed;
+} __packed;
+
+#define CARL9170FW_PHY_HT_ENABLE                0x4
+#define CARL9170FW_PHY_HT_DYN2040               0x8
+#define CARL9170FW_PHY_HT_EXT_CHAN_OFF          0x3
+#define CARL9170FW_PHY_HT_EXT_CHAN_OFF_S        2
+
+struct carl9170_rf_init {
+        __le32          freq;
+        u8              ht_settings;
+        u8              padding2[3];
+        __le32          delta_slope_coeff_exp;
+        __le32          delta_slope_coeff_man;
+        __le32          delta_slope_coeff_exp_shgi;
+        __le32          delta_slope_coeff_man_shgi;
+        __le32          finiteLoopCount;
+} __packed;
+#define CARL9170_RF_INIT_SIZE           28
+
+struct carl9170_rf_init_result {
+        __le32          ret;            /* AR9170_PHY_REG_AGC_CONTROL */
+} __packed;
+#define CARL9170_RF_INIT_RESULT_SIZE    4
+
+#define CARL9170_PSM_SLEEP              0x1000
+#define CARL9170_PSM_SOFTWARE           0
+#define CARL9170_PSM_WAKE               0 /* internally used. */
+#define CARL9170_PSM_COUNTER            0xfff
+#define CARL9170_PSM_COUNTER_S          0
+
+struct carl9170_psm {
+        __le32          state;
+} __packed;
+#define CARL9170_PSM_SIZE               4
+
+struct carl9170_rx_filter_cmd {
+        __le32          rx_filter;
+} __packed;
+#define CARL9170_RX_FILTER_CMD_SIZE     4
+
+#define CARL9170_RX_FILTER_BAD          0x01
+#define CARL9170_RX_FILTER_OTHER_RA     0x02
+#define CARL9170_RX_FILTER_DECRY_FAIL   0x04
+#define CARL9170_RX_FILTER_CTL_OTHER    0x08
+#define CARL9170_RX_FILTER_CTL_PSPOLL   0x10
+#define CARL9170_RX_FILTER_CTL_BACKR    0x20
+#define CARL9170_RX_FILTER_MGMT         0x40
+#define CARL9170_RX_FILTER_DATA         0x80
+#define CARL9170_RX_FILTER_EVERYTHING   (~0)
+
+struct carl9170_bcn_ctrl_cmd {
+        __le32          vif_id;
+        __le32          mode;
+        __le32          bcn_addr;
+        __le32          bcn_len;
+} __packed;
+#define CARL9170_BCN_CTRL_CMD_SIZE      16
+
+#define CARL9170_BCN_CTRL_DRAIN 0
+#define CARL9170_BCN_CTRL_CAB_TRIGGER   1
+
+struct carl9170_cmd_head {
+        union {
+                struct {
+                        u8      len;
+                        u8      cmd;
+                        u8      seq;
+                        u8      ext;
+                } __packed;
+
+                u32 hdr_data;
+        } __packed;
+} __packed;
+
+struct carl9170_cmd {
+        struct carl9170_cmd_head hdr;
+        union {
+                struct carl9170_set_key_cmd     setkey;
+                struct carl9170_disable_key_cmd disablekey;
+                struct carl9170_u32_list        echo;
+                struct carl9170_reg_list        rreg;
+                struct carl9170_write_reg       wreg;
+                struct carl9170_rf_init         rf_init;
+                struct carl9170_psm             psm;
+                struct carl9170_bcn_ctrl_cmd    bcn_ctrl;
+                struct carl9170_rx_filter_cmd   rx_filter;
+                u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
+        } __packed;
+} __packed __aligned(4);
+
+#define CARL9170_TX_STATUS_QUEUE        3
+#define CARL9170_TX_STATUS_QUEUE_S      0
+#define CARL9170_TX_STATUS_RIX_S        2
+#define CARL9170_TX_STATUS_RIX          (3 << CARL9170_TX_STATUS_RIX_S)
+#define CARL9170_TX_STATUS_TRIES_S      4
+#define CARL9170_TX_STATUS_TRIES        (7 << CARL9170_TX_STATUS_TRIES_S)
+#define CARL9170_TX_STATUS_SUCCESS      0x80
+
+#ifdef __CARL9170FW__
+/*
+ * NOTE:
+ * Both structs [carl9170_tx_status and _carl9170_tx_status]
+ * need to be "bit for bit" in sync.
+ */
+struct carl9170_tx_status {
+        /*
+         * Beware of compiler bugs in all gcc pre 4.4!
+         */
+
+        u8 cookie;
+        u8 queue:2;
+        u8 rix:2;
+        u8 tries:3;
+        u8 success:1;
+} __packed;
+#endif /* __CARL9170FW__ */
+
+struct _carl9170_tx_status {
+        /*
+         * This version should be immune to all alignment bugs.
+         */
+
+        u8 cookie;
+        u8 info;
+} __packed;
+#define CARL9170_TX_STATUS_SIZE         2
+
+#define CARL9170_RSP_TX_STATUS_NUM      (CARL9170_MAX_CMD_PAYLOAD_LEN / \
+                                         sizeof(struct _carl9170_tx_status))
+
+#define CARL9170_TX_MAX_RATE_TRIES      7
+
+#define CARL9170_TX_MAX_RATES           4
+#define CARL9170_TX_MAX_RETRY_RATES     (CARL9170_TX_MAX_RATES - 1)
+#define CARL9170_ERR_MAGIC              "ERR:"
+#define CARL9170_BUG_MAGIC              "BUG:"
+
+struct carl9170_gpio {
+        __le32 gpio;
+} __packed;
+#define CARL9170_GPIO_SIZE              4
+
+struct carl9170_tsf_rsp {
+        union {
+                __le32 tsf[2];
+                __le64 tsf_64;
+        } __packed;
+} __packed;
+#define CARL9170_TSF_RSP_SIZE           8
+
+struct carl9170_rsp {
+        struct carl9170_cmd_head hdr;
+
+        union {
+                struct carl9170_rf_init_result  rf_init_res;
+                struct carl9170_u32_list        rreg_res;
+                struct carl9170_u32_list        echo;
+#ifdef __CARL9170FW__
+                struct carl9170_tx_status       tx_status[0];
+#endif /* __CARL9170FW__ */
+                struct _carl9170_tx_status      _tx_status[0];
+                struct carl9170_gpio            gpio;
+                struct carl9170_tsf_rsp         tsf;
+                struct carl9170_psm             psm;
+                u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
+        } __packed;
+} __packed __aligned(4);
+
+#endif /* __CARL9170_SHARED_FWCMD_H */
diff --git a/drivers/net/wireless/ath/carl9170/fwdesc.h b/drivers/net/wireless/ath/carl9170/fwdesc.h
new file mode 100644
index 000000000000..921066822dd5
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/fwdesc.h
@@ -0,0 +1,257 @@
+/*
+ * Shared CARL9170 Header
+ *
+ * Firmware descriptor format
+ *
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ */
+
+#ifndef __CARL9170_SHARED_FWDESC_H
+#define __CARL9170_SHARED_FWDESC_H
+
+/* NOTE: Don't mess with the order of the flags! */
+enum carl9170fw_feature_list {
+        /* Always set */
+        CARL9170FW_DUMMY_FEATURE,
+
+        /*
+         * Indicates that this image has special boot block which prevents
+         * legacy drivers to drive the firmware.
+         */
+        CARL9170FW_MINIBOOT,
+
+        /* usb registers are initialized by the firmware */
+        CARL9170FW_USB_INIT_FIRMWARE,
+
+        /* command traps & notifications are send through EP2 */
+        CARL9170FW_USB_RESP_EP2,
+
+        /* usb download (app -> fw) stream */
+        CARL9170FW_USB_DOWN_STREAM,
+
+        /* usb upload (fw -> app) stream */
+        CARL9170FW_USB_UP_STREAM,
+
+        /* unusable - reserved to flag non-functional debug firmwares */
+        CARL9170FW_UNUSABLE,
+
+        /* AR9170_CMD_RF_INIT, AR9170_CMD_FREQ_START, AR9170_CMD_FREQUENCY */
+        CARL9170FW_COMMAND_PHY,
+
+        /* AR9170_CMD_EKEY, AR9170_CMD_DKEY */
+        CARL9170FW_COMMAND_CAM,
+
+        /* Firmware has a software Content After Beacon Queueing mechanism */
+        CARL9170FW_WLANTX_CAB,
+
+        /* The firmware is capable of responding to incoming BAR frames */
+        CARL9170FW_HANDLE_BACK_REQ,
+
+        /* GPIO Interrupt | CARL9170_RSP_GPIO */
+        CARL9170FW_GPIO_INTERRUPT,
+
+        /* Firmware PSM support | CARL9170_CMD_PSM */
+        CARL9170FW_PSM,
+
+        /* Firmware RX filter | CARL9170_CMD_RX_FILTER */
+        CARL9170FW_RX_FILTER,
+
+        /* Wake up on WLAN */
+        CARL9170FW_WOL,
+
+        /* KEEP LAST */
+        __CARL9170FW_FEATURE_NUM
+};
+
+#define OTUS_MAGIC      "OTAR"
+#define MOTD_MAGIC      "MOTD"
+#define FIX_MAGIC       "FIX\0"
+#define DBG_MAGIC       "DBG\0"
+#define CHK_MAGIC       "CHK\0"
+#define TXSQ_MAGIC      "TXSQ"
+#define LAST_MAGIC      "LAST"
+
+#define CARL9170FW_SET_DAY(d) (((d) - 1) % 31)
+#define CARL9170FW_SET_MONTH(m) ((((m) - 1) % 12) * 31)
+#define CARL9170FW_SET_YEAR(y) (((y) - 10) * 372)
+
+#define CARL9170FW_GET_DAY(d) (((d) % 31) + 1)
+#define CARL9170FW_GET_MONTH(m) ((((m) / 31) % 12) + 1)
+#define CARL9170FW_GET_YEAR(y) ((y) / 372 + 10)
+
+#define CARL9170FW_MAGIC_SIZE                   4
+
+struct carl9170fw_desc_head {
+        u8      magic[CARL9170FW_MAGIC_SIZE];
+        __le16 length;
+        u8 min_ver;
+        u8 cur_ver;
+} __packed;
+#define CARL9170FW_DESC_HEAD_SIZE                       \
+        (sizeof(struct carl9170fw_desc_head))
+
+#define CARL9170FW_OTUS_DESC_MIN_VER            6
+#define CARL9170FW_OTUS_DESC_CUR_VER            6
+struct carl9170fw_otus_desc {
+        struct carl9170fw_desc_head head;
+        __le32 feature_set;
+        __le32 fw_address;
+        __le32 bcn_addr;
+        __le16 bcn_len;
+        __le16 miniboot_size;
+        __le16 tx_frag_len;
+        __le16 rx_max_frame_len;
+        u8 tx_descs;
+        u8 cmd_bufs;
+        u8 api_ver;
+        u8 vif_num;
+} __packed;
+#define CARL9170FW_OTUS_DESC_SIZE                       \
+        (sizeof(struct carl9170fw_otus_desc))
+
+#define CARL9170FW_MOTD_STRING_LEN                      24
+#define CARL9170FW_MOTD_RELEASE_LEN                     20
+#define CARL9170FW_MOTD_DESC_MIN_VER                    1
+#define CARL9170FW_MOTD_DESC_CUR_VER                    2
+struct carl9170fw_motd_desc {
+        struct carl9170fw_desc_head head;
+        __le32 fw_year_month_day;
+        char desc[CARL9170FW_MOTD_STRING_LEN];
+        char release[CARL9170FW_MOTD_RELEASE_LEN];
+} __packed;
+#define CARL9170FW_MOTD_DESC_SIZE                       \
+        (sizeof(struct carl9170fw_motd_desc))
+
+#define CARL9170FW_FIX_DESC_MIN_VER                     1
+#define CARL9170FW_FIX_DESC_CUR_VER                     2
+struct carl9170fw_fix_entry {
+        __le32 address;
+        __le32 mask;
+        __le32 value;
+} __packed;
+
+struct carl9170fw_fix_desc {
+        struct carl9170fw_desc_head head;
+        struct carl9170fw_fix_entry data[0];
+} __packed;
+#define CARL9170FW_FIX_DESC_SIZE                        \
+        (sizeof(struct carl9170fw_fix_desc))
+
+#define CARL9170FW_DBG_DESC_MIN_VER                     1
+#define CARL9170FW_DBG_DESC_CUR_VER                     3
+struct carl9170fw_dbg_desc {
+        struct carl9170fw_desc_head head;
+
+        __le32 bogoclock_addr;
+        __le32 counter_addr;
+        __le32 rx_total_addr;
+        __le32 rx_overrun_addr;
+        __le32 rx_filter;
+
+        /* Put your debugging definitions here */
+} __packed;
+#define CARL9170FW_DBG_DESC_SIZE                        \
+        (sizeof(struct carl9170fw_dbg_desc))
+
+#define CARL9170FW_CHK_DESC_MIN_VER                     1
+#define CARL9170FW_CHK_DESC_CUR_VER                     2
+struct carl9170fw_chk_desc {
+        struct carl9170fw_desc_head head;
+        __le32 fw_crc32;
+        __le32 hdr_crc32;
+} __packed;
+#define CARL9170FW_CHK_DESC_SIZE                        \
+        (sizeof(struct carl9170fw_chk_desc))
+
+#define CARL9170FW_TXSQ_DESC_MIN_VER                    1
+#define CARL9170FW_TXSQ_DESC_CUR_VER                    1
+struct carl9170fw_txsq_desc {
+        struct carl9170fw_desc_head head;
+
+        __le32 seq_table_addr;
+} __packed;
+#define CARL9170FW_TXSQ_DESC_SIZE                       \
+        (sizeof(struct carl9170fw_txsq_desc))
+
+#define CARL9170FW_LAST_DESC_MIN_VER                    1
+#define CARL9170FW_LAST_DESC_CUR_VER                    2
+struct carl9170fw_last_desc {
+        struct carl9170fw_desc_head head;
+} __packed;
+#define CARL9170FW_LAST_DESC_SIZE                       \
+        (sizeof(struct carl9170fw_fix_desc))
+
+#define CARL9170FW_DESC_MAX_LENGTH                      8192
+
+#define CARL9170FW_FILL_DESC(_magic, _length, _min_ver, _cur_ver)       \
+        .head = {                                                       \
+                .magic = _magic,                                        \
+                .length = cpu_to_le16(_length),                         \
+                .min_ver = _min_ver,                                    \
+                .cur_ver = _cur_ver,                                    \
+        }
+
+static inline void carl9170fw_fill_desc(struct carl9170fw_desc_head *head,
+                                         u8 magic[CARL9170FW_MAGIC_SIZE],
+                                         __le16 length, u8 min_ver, u8 cur_ver)
+{
+        head->magic[0] = magic[0];
+        head->magic[1] = magic[1];
+        head->magic[2] = magic[2];
+        head->magic[3] = magic[3];
+
+        head->length = length;
+        head->min_ver = min_ver;
+        head->cur_ver = cur_ver;
+}
+
+#define carl9170fw_for_each_hdr(desc, fw_desc)                          \
+        for (desc = fw_desc;                                            \
+             memcmp(desc->magic, LAST_MAGIC, CARL9170FW_MAGIC_SIZE) &&  \
+             le16_to_cpu(desc->length) >= CARL9170FW_DESC_HEAD_SIZE &&  \
+             le16_to_cpu(desc->length) < CARL9170FW_DESC_MAX_LENGTH;    \
+             desc = (void *)((unsigned long)desc + le16_to_cpu(desc->length)))
+
+#define CHECK_HDR_VERSION(head, _min_ver)                               \
+        (((head)->cur_ver < _min_ver) || ((head)->min_ver > _min_ver))  \
+
+static inline bool carl9170fw_supports(__le32 list, u8 feature)
+{
+        return le32_to_cpu(list) & BIT(feature);
+}
+
+static inline bool carl9170fw_desc_cmp(const struct carl9170fw_desc_head *head,
+                                       const u8 descid[CARL9170FW_MAGIC_SIZE],
+                                       u16 min_len, u8 compatible_revision)
+{
+        if (descid[0] == head->magic[0] && descid[1] == head->magic[1] &&
+            descid[2] == head->magic[2] && descid[3] == head->magic[3] &&
+            !CHECK_HDR_VERSION(head, compatible_revision) &&
+            (le16_to_cpu(head->length) >= min_len))
+                return true;
+
+        return false;
+}
+
+#define CARL9170FW_MIN_SIZE     32
+#define CARL9170FW_MAX_SIZE     16384
+
+static inline bool carl9170fw_size_check(unsigned int len)
+{
+        return (len <= CARL9170FW_MAX_SIZE && len >= CARL9170FW_MIN_SIZE);
+}
+
+#endif /* __CARL9170_SHARED_FWDESC_H */
diff --git a/drivers/net/wireless/ath/carl9170/hw.h b/drivers/net/wireless/ath/carl9170/hw.h
new file mode 100644
index 000000000000..4e30762dd903
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/hw.h
@@ -0,0 +1,769 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * Register map, hardware-specific definitions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_HW_H
+#define __CARL9170_SHARED_HW_H
+
+/* High Speed UART */
+#define AR9170_UART_REG_BASE                    0x1c0000
+
+/* Definitions of interrupt registers */
+#define AR9170_UART_REG_RX_BUFFER               (AR9170_UART_REG_BASE + 0x000)
+#define AR9170_UART_REG_TX_HOLDING              (AR9170_UART_REG_BASE + 0x004)
+#define AR9170_UART_REG_FIFO_CONTROL            (AR9170_UART_REG_BASE + 0x010)
+#define         AR9170_UART_FIFO_CTRL_RESET_RX_FIFO     0x02
+#define         AR9170_UART_FIFO_CTRL_RESET_TX_FIFO     0x04
+
+#define AR9170_UART_REG_LINE_CONTROL            (AR9170_UART_REG_BASE + 0x014)
+#define AR9170_UART_REG_MODEM_CONTROL           (AR9170_UART_REG_BASE + 0x018)
+#define         AR9170_UART_MODEM_CTRL_DTR_BIT          0x01
+#define         AR9170_UART_MODEM_CTRL_RTS_BIT          0x02
+#define         AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK       0x10
+#define         AR9170_UART_MODEM_CTRL_AUTO_RTS         0x20
+#define         AR9170_UART_MODEM_CTRL_AUTO_CTR         0x40
+
+#define AR9170_UART_REG_LINE_STATUS             (AR9170_UART_REG_BASE + 0x01c)
+#define         AR9170_UART_LINE_STS_RX_DATA_READY      0x01
+#define         AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN  0x02
+#define         AR9170_UART_LINE_STS_RX_BREAK_IND       0x10
+#define         AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY 0x20
+#define         AR9170_UART_LINE_STS_TRANSMITTER_EMPTY  0x40
+
+#define AR9170_UART_REG_MODEM_STATUS            (AR9170_UART_REG_BASE + 0x020)
+#define         AR9170_UART_MODEM_STS_CTS_CHANGE        0x01
+#define         AR9170_UART_MODEM_STS_DSR_CHANGE        0x02
+#define         AR9170_UART_MODEM_STS_DCD_CHANGE        0x08
+#define         AR9170_UART_MODEM_STS_CTS_COMPL         0x10
+#define         AR9170_UART_MODEM_STS_DSR_COMPL         0x20
+#define         AR9170_UART_MODEM_STS_DCD_COMPL         0x80
+
+#define AR9170_UART_REG_SCRATCH                 (AR9170_UART_REG_BASE + 0x024)
+#define AR9170_UART_REG_DIVISOR_LSB             (AR9170_UART_REG_BASE + 0x028)
+#define AR9170_UART_REG_DIVISOR_MSB             (AR9170_UART_REG_BASE + 0x02c)
+#define AR9170_UART_REG_WORD_RX_BUFFER          (AR9170_UART_REG_BASE + 0x034)
+#define AR9170_UART_REG_WORD_TX_HOLDING         (AR9170_UART_REG_BASE + 0x038)
+#define AR9170_UART_REG_FIFO_COUNT              (AR9170_UART_REG_BASE + 0x03c)
+#define AR9170_UART_REG_REMAINDER               (AR9170_UART_REG_BASE + 0x04c)
+
+/* Timer */
+#define AR9170_TIMER_REG_BASE                   0x1c1000
+
+#define AR9170_TIMER_REG_WATCH_DOG              (AR9170_TIMER_REG_BASE + 0x000)
+#define AR9170_TIMER_REG_TIMER0                 (AR9170_TIMER_REG_BASE + 0x010)
+#define AR9170_TIMER_REG_TIMER1                 (AR9170_TIMER_REG_BASE + 0x014)
+#define AR9170_TIMER_REG_TIMER2                 (AR9170_TIMER_REG_BASE + 0x018)
+#define AR9170_TIMER_REG_TIMER3                 (AR9170_TIMER_REG_BASE + 0x01c)
+#define AR9170_TIMER_REG_TIMER4                 (AR9170_TIMER_REG_BASE + 0x020)
+#define AR9170_TIMER_REG_CONTROL                (AR9170_TIMER_REG_BASE + 0x024)
+#define         AR9170_TIMER_CTRL_DISABLE_CLOCK         0x100
+
+#define AR9170_TIMER_REG_INTERRUPT              (AR9170_TIMER_REG_BASE + 0x028)
+#define         AR9170_TIMER_INT_TIMER0                 0x001
+#define         AR9170_TIMER_INT_TIMER1                 0x002
+#define         AR9170_TIMER_INT_TIMER2                 0x004
+#define         AR9170_TIMER_INT_TIMER3                 0x008
+#define         AR9170_TIMER_INT_TIMER4                 0x010
+#define         AR9170_TIMER_INT_TICK_TIMER             0x100
+
+#define AR9170_TIMER_REG_TICK_TIMER             (AR9170_TIMER_REG_BASE + 0x030)
+#define AR9170_TIMER_REG_CLOCK_LOW              (AR9170_TIMER_REG_BASE + 0x040)
+#define AR9170_TIMER_REG_CLOCK_HIGH             (AR9170_TIMER_REG_BASE + 0x044)
+
+#define AR9170_MAC_REG_BASE                     0x1c3000
+
+#define AR9170_MAC_REG_POWER_STATE_CTRL         (AR9170_MAC_REG_BASE + 0x500)
+#define         AR9170_MAC_POWER_STATE_CTRL_RESET       0x20
+
+#define AR9170_MAC_REG_MAC_POWER_STATE_CTRL     (AR9170_MAC_REG_BASE + 0x50c)
+
+#define AR9170_MAC_REG_INT_CTRL                 (AR9170_MAC_REG_BASE + 0x510)
+#define         AR9170_MAC_INT_TXC                      BIT(0)
+#define         AR9170_MAC_INT_RXC                      BIT(1)
+#define         AR9170_MAC_INT_RETRY_FAIL               BIT(2)
+#define         AR9170_MAC_INT_WAKEUP                   BIT(3)
+#define         AR9170_MAC_INT_ATIM                     BIT(4)
+#define         AR9170_MAC_INT_DTIM                     BIT(5)
+#define         AR9170_MAC_INT_CFG_BCN                  BIT(6)
+#define         AR9170_MAC_INT_ABORT                    BIT(7)
+#define         AR9170_MAC_INT_QOS                      BIT(8)
+#define         AR9170_MAC_INT_MIMO_PS                  BIT(9)
+#define         AR9170_MAC_INT_KEY_GEN                  BIT(10)
+#define         AR9170_MAC_INT_DECRY_NOUSER             BIT(11)
+#define         AR9170_MAC_INT_RADAR                    BIT(12)
+#define         AR9170_MAC_INT_QUIET_FRAME              BIT(13)
+#define         AR9170_MAC_INT_PRETBTT                  BIT(14)
+
+#define AR9170_MAC_REG_TSF_L                    (AR9170_MAC_REG_BASE + 0x514)
+#define AR9170_MAC_REG_TSF_H                    (AR9170_MAC_REG_BASE + 0x518)
+
+#define AR9170_MAC_REG_ATIM_WINDOW              (AR9170_MAC_REG_BASE + 0x51c)
+#define         AR9170_MAC_ATIM_PERIOD_S                0
+#define         AR9170_MAC_ATIM_PERIOD                  0x0000ffff
+
+#define AR9170_MAC_REG_BCN_PERIOD               (AR9170_MAC_REG_BASE + 0x520)
+#define         AR9170_MAC_BCN_PERIOD_S                 0
+#define         AR9170_MAC_BCN_PERIOD                   0x0000ffff
+#define         AR9170_MAC_BCN_DTIM_S                   16
+#define         AR9170_MAC_BCN_DTIM                     0x00ff0000
+#define         AR9170_MAC_BCN_AP_MODE                  BIT(24)
+#define         AR9170_MAC_BCN_IBSS_MODE                BIT(25)
+#define         AR9170_MAC_BCN_PWR_MGT                  BIT(26)
+#define         AR9170_MAC_BCN_STA_PS                   BIT(27)
+
+#define AR9170_MAC_REG_PRETBTT                  (AR9170_MAC_REG_BASE + 0x524)
+#define         AR9170_MAC_PRETBTT_S                    0
+#define         AR9170_MAC_PRETBTT                      0x0000ffff
+#define         AR9170_MAC_PRETBTT2_S                   16
+#define         AR9170_MAC_PRETBTT2                     0xffff0000
+
+#define AR9170_MAC_REG_MAC_ADDR_L               (AR9170_MAC_REG_BASE + 0x610)
+#define AR9170_MAC_REG_MAC_ADDR_H               (AR9170_MAC_REG_BASE + 0x614)
+#define AR9170_MAC_REG_BSSID_L                  (AR9170_MAC_REG_BASE + 0x618)
+#define AR9170_MAC_REG_BSSID_H                  (AR9170_MAC_REG_BASE + 0x61c)
+
+#define AR9170_MAC_REG_GROUP_HASH_TBL_L         (AR9170_MAC_REG_BASE + 0x624)
+#define AR9170_MAC_REG_GROUP_HASH_TBL_H         (AR9170_MAC_REG_BASE + 0x628)
+
+#define AR9170_MAC_REG_RX_TIMEOUT               (AR9170_MAC_REG_BASE + 0x62c)
+
+#define AR9170_MAC_REG_BASIC_RATE               (AR9170_MAC_REG_BASE + 0x630)
+#define AR9170_MAC_REG_MANDATORY_RATE           (AR9170_MAC_REG_BASE + 0x634)
+#define AR9170_MAC_REG_RTS_CTS_RATE             (AR9170_MAC_REG_BASE + 0x638)
+#define AR9170_MAC_REG_BACKOFF_PROTECT          (AR9170_MAC_REG_BASE + 0x63c)
+#define AR9170_MAC_REG_RX_THRESHOLD             (AR9170_MAC_REG_BASE + 0x640)
+#define AR9170_MAC_REG_AFTER_PNP                (AR9170_MAC_REG_BASE + 0x648)
+#define AR9170_MAC_REG_RX_PE_DELAY              (AR9170_MAC_REG_BASE + 0x64c)
+
+#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK         (AR9170_MAC_REG_BASE + 0x658)
+#define AR9170_MAC_REG_SNIFFER                  (AR9170_MAC_REG_BASE + 0x674)
+#define         AR9170_MAC_SNIFFER_ENABLE_PROMISC       BIT(0)
+#define         AR9170_MAC_SNIFFER_DEFAULTS             0x02000000
+#define AR9170_MAC_REG_ENCRYPTION               (AR9170_MAC_REG_BASE + 0x678)
+#define         AR9170_MAC_ENCRYPTION_RX_SOFTWARE       BIT(3)
+#define         AR9170_MAC_ENCRYPTION_DEFAULTS          0x70
+
+#define AR9170_MAC_REG_MISC_680                 (AR9170_MAC_REG_BASE + 0x680)
+#define AR9170_MAC_REG_MISC_684                 (AR9170_MAC_REG_BASE + 0x684)
+#define AR9170_MAC_REG_TX_UNDERRUN              (AR9170_MAC_REG_BASE + 0x688)
+
+#define AR9170_MAC_REG_FRAMETYPE_FILTER         (AR9170_MAC_REG_BASE + 0x68c)
+#define         AR9170_MAC_FTF_ASSOC_REQ                BIT(0)
+#define         AR9170_MAC_FTF_ASSOC_RESP               BIT(1)
+#define         AR9170_MAC_FTF_REASSOC_REQ              BIT(2)
+#define         AR9170_MAC_FTF_REASSOC_RESP             BIT(3)
+#define         AR9170_MAC_FTF_PRB_REQ                  BIT(4)
+#define         AR9170_MAC_FTF_PRB_RESP                 BIT(5)
+#define         AR9170_MAC_FTF_BIT6                     BIT(6)
+#define         AR9170_MAC_FTF_BIT7                     BIT(7)
+#define         AR9170_MAC_FTF_BEACON                   BIT(8)
+#define         AR9170_MAC_FTF_ATIM                     BIT(9)
+#define         AR9170_MAC_FTF_DEASSOC                  BIT(10)
+#define         AR9170_MAC_FTF_AUTH                     BIT(11)
+#define         AR9170_MAC_FTF_DEAUTH                   BIT(12)
+#define         AR9170_MAC_FTF_BIT13                    BIT(13)
+#define         AR9170_MAC_FTF_BIT14                    BIT(14)
+#define         AR9170_MAC_FTF_BIT15                    BIT(15)
+#define         AR9170_MAC_FTF_BAR                      BIT(24)
+#define         AR9170_MAC_FTF_BA                       BIT(25)
+#define         AR9170_MAC_FTF_PSPOLL                   BIT(26)
+#define         AR9170_MAC_FTF_RTS                      BIT(27)
+#define         AR9170_MAC_FTF_CTS                      BIT(28)
+#define         AR9170_MAC_FTF_ACK                      BIT(29)
+#define         AR9170_MAC_FTF_CFE                      BIT(30)
+#define         AR9170_MAC_FTF_CFE_ACK                  BIT(31)
+#define         AR9170_MAC_FTF_DEFAULTS                 0x0500ffff
+#define         AR9170_MAC_FTF_MONITOR                  0xff00ffff
+
+#define AR9170_MAC_REG_ACK_EXTENSION            (AR9170_MAC_REG_BASE + 0x690)
+#define AR9170_MAC_REG_ACK_TPC                  (AR9170_MAC_REG_BASE + 0x694)
+#define AR9170_MAC_REG_EIFS_AND_SIFS            (AR9170_MAC_REG_BASE + 0x698)
+#define AR9170_MAC_REG_RX_TIMEOUT_COUNT         (AR9170_MAC_REG_BASE + 0x69c)
+#define AR9170_MAC_REG_RX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6a0)
+#define AR9170_MAC_REG_RX_CRC32                 (AR9170_MAC_REG_BASE + 0x6a4)
+#define AR9170_MAC_REG_RX_CRC16                 (AR9170_MAC_REG_BASE + 0x6a8)
+#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI    (AR9170_MAC_REG_BASE + 0x6ac)
+#define AR9170_MAC_REG_RX_OVERRUN               (AR9170_MAC_REG_BASE + 0x6b0)
+#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL    (AR9170_MAC_REG_BASE + 0x6bc)
+#define AR9170_MAC_REG_TX_BLOCKACKS             (AR9170_MAC_REG_BASE + 0x6c0)
+#define AR9170_MAC_REG_NAV_COUNT                (AR9170_MAC_REG_BASE + 0x6c4)
+#define AR9170_MAC_REG_BACKOFF_STATUS           (AR9170_MAC_REG_BASE + 0x6c8)
+#define AR9170_MAC_REG_TX_RETRY                 (AR9170_MAC_REG_BASE + 0x6cc)
+
+#define AR9170_MAC_REG_TX_COMPLETE              (AR9170_MAC_REG_BASE + 0x6d4)
+
+#define AR9170_MAC_REG_CHANNEL_BUSY             (AR9170_MAC_REG_BASE + 0x6e8)
+#define AR9170_MAC_REG_EXT_BUSY                 (AR9170_MAC_REG_BASE + 0x6ec)
+
+#define AR9170_MAC_REG_SLOT_TIME                (AR9170_MAC_REG_BASE + 0x6f0)
+#define AR9170_MAC_REG_TX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6f4)
+#define AR9170_MAC_REG_ACK_FC                   (AR9170_MAC_REG_BASE + 0x6f8)
+
+#define AR9170_MAC_REG_CAM_MODE                 (AR9170_MAC_REG_BASE + 0x700)
+#define         AR9170_MAC_CAM_IBSS                     0xe0
+#define         AR9170_MAC_CAM_AP                       0xa1
+#define         AR9170_MAC_CAM_STA                      0x2
+#define         AR9170_MAC_CAM_AP_WDS                   0x3
+#define         AR9170_MAC_CAM_DEFAULTS                 (0xf << 24)
+#define         AR9170_MAC_CAM_HOST_PENDING             0x80000000
+
+#define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L      (AR9170_MAC_REG_BASE + 0x704)
+#define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H      (AR9170_MAC_REG_BASE + 0x708)
+
+#define AR9170_MAC_REG_CAM_ADDR                 (AR9170_MAC_REG_BASE + 0x70c)
+#define         AR9170_MAC_CAM_ADDR_WRITE               0x80000000
+#define AR9170_MAC_REG_CAM_DATA0                (AR9170_MAC_REG_BASE + 0x720)
+#define AR9170_MAC_REG_CAM_DATA1                (AR9170_MAC_REG_BASE + 0x724)
+#define AR9170_MAC_REG_CAM_DATA2                (AR9170_MAC_REG_BASE + 0x728)
+#define AR9170_MAC_REG_CAM_DATA3                (AR9170_MAC_REG_BASE + 0x72c)
+
+#define AR9170_MAC_REG_CAM_DBG0                 (AR9170_MAC_REG_BASE + 0x730)
+#define AR9170_MAC_REG_CAM_DBG1                 (AR9170_MAC_REG_BASE + 0x734)
+#define AR9170_MAC_REG_CAM_DBG2                 (AR9170_MAC_REG_BASE + 0x738)
+#define AR9170_MAC_REG_CAM_STATE                (AR9170_MAC_REG_BASE + 0x73c)
+#define         AR9170_MAC_CAM_STATE_READ_PENDING       0x40000000
+#define         AR9170_MAC_CAM_STATE_WRITE_PENDING      0x80000000
+
+#define AR9170_MAC_REG_CAM_TXKEY                (AR9170_MAC_REG_BASE + 0x740)
+#define AR9170_MAC_REG_CAM_RXKEY                (AR9170_MAC_REG_BASE + 0x750)
+
+#define AR9170_MAC_REG_CAM_TX_ENC_TYPE          (AR9170_MAC_REG_BASE + 0x760)
+#define AR9170_MAC_REG_CAM_RX_ENC_TYPE          (AR9170_MAC_REG_BASE + 0x770)
+#define AR9170_MAC_REG_CAM_TX_SERACH_HIT        (AR9170_MAC_REG_BASE + 0x780)
+#define AR9170_MAC_REG_CAM_RX_SERACH_HIT        (AR9170_MAC_REG_BASE + 0x790)
+
+#define AR9170_MAC_REG_AC0_CW                   (AR9170_MAC_REG_BASE + 0xb00)
+#define AR9170_MAC_REG_AC1_CW                   (AR9170_MAC_REG_BASE + 0xb04)
+#define AR9170_MAC_REG_AC2_CW                   (AR9170_MAC_REG_BASE + 0xb08)
+#define AR9170_MAC_REG_AC3_CW                   (AR9170_MAC_REG_BASE + 0xb0c)
+#define AR9170_MAC_REG_AC4_CW                   (AR9170_MAC_REG_BASE + 0xb10)
+#define AR9170_MAC_REG_AC2_AC1_AC0_AIFS         (AR9170_MAC_REG_BASE + 0xb14)
+#define AR9170_MAC_REG_AC4_AC3_AC2_AIFS         (AR9170_MAC_REG_BASE + 0xb18)
+#define AR9170_MAC_REG_TXOP_ACK_EXTENSION       (AR9170_MAC_REG_BASE + 0xb1c)
+#define AR9170_MAC_REG_TXOP_ACK_INTERVAL        (AR9170_MAC_REG_BASE + 0xb20)
+#define AR9170_MAC_REG_CONTENTION_POINT         (AR9170_MAC_REG_BASE + 0xb24)
+#define AR9170_MAC_REG_RETRY_MAX                (AR9170_MAC_REG_BASE + 0xb28)
+#define AR9170_MAC_REG_TID_CFACK_CFEND_RATE     (AR9170_MAC_REG_BASE + 0xb2c)
+#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND      (AR9170_MAC_REG_BASE + 0xb30)
+#define AR9170_MAC_REG_TKIP_TSC                 (AR9170_MAC_REG_BASE + 0xb34)
+#define AR9170_MAC_REG_TXOP_DURATION            (AR9170_MAC_REG_BASE + 0xb38)
+#define AR9170_MAC_REG_TX_QOS_THRESHOLD         (AR9170_MAC_REG_BASE + 0xb3c)
+#define AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA (AR9170_MAC_REG_BASE + 0xb40)
+#define         AR9170_MAC_VIRTUAL_CCA_Q0               BIT(15)
+#define         AR9170_MAC_VIRTUAL_CCA_Q1               BIT(16)
+#define         AR9170_MAC_VIRTUAL_CCA_Q2               BIT(17)
+#define         AR9170_MAC_VIRTUAL_CCA_Q3               BIT(18)
+#define         AR9170_MAC_VIRTUAL_CCA_Q4               BIT(19)
+#define         AR9170_MAC_VIRTUAL_CCA_ALL              (0xf8000)
+
+#define AR9170_MAC_REG_AC1_AC0_TXOP             (AR9170_MAC_REG_BASE + 0xb44)
+#define AR9170_MAC_REG_AC3_AC2_TXOP             (AR9170_MAC_REG_BASE + 0xb48)
+
+#define AR9170_MAC_REG_AMPDU_COUNT              (AR9170_MAC_REG_BASE + 0xb88)
+#define AR9170_MAC_REG_MPDU_COUNT               (AR9170_MAC_REG_BASE + 0xb8c)
+
+#define AR9170_MAC_REG_AMPDU_FACTOR             (AR9170_MAC_REG_BASE + 0xb9c)
+#define         AR9170_MAC_AMPDU_FACTOR                 0x7f0000
+#define         AR9170_MAC_AMPDU_FACTOR_S               16
+#define AR9170_MAC_REG_AMPDU_DENSITY            (AR9170_MAC_REG_BASE + 0xba0)
+#define         AR9170_MAC_AMPDU_DENSITY                0x7
+#define         AR9170_MAC_AMPDU_DENSITY_S              0
+
+#define AR9170_MAC_REG_FCS_SELECT               (AR9170_MAC_REG_BASE + 0xbb0)
+#define         AR9170_MAC_FCS_SWFCS                    0x1
+#define         AR9170_MAC_FCS_FIFO_PROT                0x4
+
+#define AR9170_MAC_REG_RTS_CTS_TPC              (AR9170_MAC_REG_BASE + 0xbb4)
+#define AR9170_MAC_REG_CFEND_QOSNULL_TPC        (AR9170_MAC_REG_BASE + 0xbb8)
+
+#define AR9170_MAC_REG_ACK_TABLE                (AR9170_MAC_REG_BASE + 0xc00)
+#define AR9170_MAC_REG_RX_CONTROL               (AR9170_MAC_REG_BASE + 0xc40)
+#define         AR9170_MAC_RX_CTRL_DEAGG                0x1
+#define         AR9170_MAC_RX_CTRL_SHORT_FILTER         0x2
+#define         AR9170_MAC_RX_CTRL_SA_DA_SEARCH         0x20
+#define         AR9170_MAC_RX_CTRL_PASS_TO_HOST         BIT(28)
+#define         AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER       BIT(30)
+
+#define AR9170_MAC_REG_RX_CONTROL_1             (AR9170_MAC_REG_BASE + 0xc44)
+
+#define AR9170_MAC_REG_AMPDU_RX_THRESH          (AR9170_MAC_REG_BASE + 0xc50)
+
+#define AR9170_MAC_REG_RX_MPDU                  (AR9170_MAC_REG_BASE + 0xca0)
+#define AR9170_MAC_REG_RX_DROPPED_MPDU          (AR9170_MAC_REG_BASE + 0xca4)
+#define AR9170_MAC_REG_RX_DEL_MPDU              (AR9170_MAC_REG_BASE + 0xca8)
+#define AR9170_MAC_REG_RX_PHY_MISC_ERROR        (AR9170_MAC_REG_BASE + 0xcac)
+#define AR9170_MAC_REG_RX_PHY_XR_ERROR          (AR9170_MAC_REG_BASE + 0xcb0)
+#define AR9170_MAC_REG_RX_PHY_OFDM_ERROR        (AR9170_MAC_REG_BASE + 0xcb4)
+#define AR9170_MAC_REG_RX_PHY_CCK_ERROR         (AR9170_MAC_REG_BASE + 0xcb8)
+#define AR9170_MAC_REG_RX_PHY_HT_ERROR          (AR9170_MAC_REG_BASE + 0xcbc)
+#define AR9170_MAC_REG_RX_PHY_TOTAL             (AR9170_MAC_REG_BASE + 0xcc0)
+
+#define AR9170_MAC_REG_DMA_TXQ_ADDR             (AR9170_MAC_REG_BASE + 0xd00)
+#define AR9170_MAC_REG_DMA_TXQ_CURR_ADDR        (AR9170_MAC_REG_BASE + 0xd04)
+#define AR9170_MAC_REG_DMA_TXQ0_ADDR            (AR9170_MAC_REG_BASE + 0xd00)
+#define AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd04)
+#define AR9170_MAC_REG_DMA_TXQ1_ADDR            (AR9170_MAC_REG_BASE + 0xd08)
+#define AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd0c)
+#define AR9170_MAC_REG_DMA_TXQ2_ADDR            (AR9170_MAC_REG_BASE + 0xd10)
+#define AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd14)
+#define AR9170_MAC_REG_DMA_TXQ3_ADDR            (AR9170_MAC_REG_BASE + 0xd18)
+#define AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd1c)
+#define AR9170_MAC_REG_DMA_TXQ4_ADDR            (AR9170_MAC_REG_BASE + 0xd20)
+#define AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd24)
+#define AR9170_MAC_REG_DMA_RXQ_ADDR             (AR9170_MAC_REG_BASE + 0xd28)
+#define AR9170_MAC_REG_DMA_RXQ_CURR_ADDR        (AR9170_MAC_REG_BASE + 0xd2c)
+
+#define AR9170_MAC_REG_DMA_TRIGGER              (AR9170_MAC_REG_BASE + 0xd30)
+#define         AR9170_DMA_TRIGGER_TXQ0                 BIT(0)
+#define         AR9170_DMA_TRIGGER_TXQ1                 BIT(1)
+#define         AR9170_DMA_TRIGGER_TXQ2                 BIT(2)
+#define         AR9170_DMA_TRIGGER_TXQ3                 BIT(3)
+#define         AR9170_DMA_TRIGGER_TXQ4                 BIT(4)
+#define         AR9170_DMA_TRIGGER_RXQ                  BIT(8)
+
+#define AR9170_MAC_REG_DMA_WLAN_STATUS          (AR9170_MAC_REG_BASE + 0xd38)
+#define AR9170_MAC_REG_DMA_STATUS               (AR9170_MAC_REG_BASE + 0xd3c)
+
+#define AR9170_MAC_REG_TXRX_MPI                 (AR9170_MAC_REG_BASE + 0xd7c)
+#define         AR9170_MAC_TXRX_MPI_TX_MPI_MASK         0x0000000f
+#define         AR9170_MAC_TXRX_MPI_TX_TO_MASK          0x0000fff0
+#define         AR9170_MAC_TXRX_MPI_RX_MPI_MASK         0x000f0000
+#define         AR9170_MAC_TXRX_MPI_RX_TO_MASK          0xfff00000
+
+#define AR9170_MAC_REG_BCN_ADDR                 (AR9170_MAC_REG_BASE + 0xd84)
+#define AR9170_MAC_REG_BCN_LENGTH               (AR9170_MAC_REG_BASE + 0xd88)
+#define         AR9170_MAC_BCN_LENGTH_MAX               256
+
+#define AR9170_MAC_REG_BCN_STATUS               (AR9170_MAC_REG_BASE + 0xd8c)
+
+#define AR9170_MAC_REG_BCN_PLCP                 (AR9170_MAC_REG_BASE + 0xd90)
+#define AR9170_MAC_REG_BCN_CTRL                 (AR9170_MAC_REG_BASE + 0xd94)
+#define         AR9170_BCN_CTRL_READY                   0x01
+#define         AR9170_BCN_CTRL_LOCK                    0x02
+
+#define AR9170_MAC_REG_BCN_CURR_ADDR            (AR9170_MAC_REG_BASE + 0xd98)
+#define AR9170_MAC_REG_BCN_COUNT                (AR9170_MAC_REG_BASE + 0xd9c)
+
+
+#define AR9170_MAC_REG_BCN_HT1                  (AR9170_MAC_REG_BASE + 0xda0)
+#define AR9170_MAC_REG_BCN_HT2                  (AR9170_MAC_REG_BASE + 0xda4)
+
+#define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR       (AR9170_MAC_REG_BASE + 0xdc0)
+
+/* Random number generator */
+#define AR9170_RAND_REG_BASE                    0x1d0000
+
+#define AR9170_RAND_REG_NUM                     (AR9170_RAND_REG_BASE + 0x000)
+#define AR9170_RAND_REG_MODE                    (AR9170_RAND_REG_BASE + 0x004)
+#define         AR9170_RAND_MODE_MANUAL                 0x000
+#define         AR9170_RAND_MODE_FREE                   0x001
+
+/* GPIO */
+#define AR9170_GPIO_REG_BASE                    0x1d0100
+#define AR9170_GPIO_REG_PORT_TYPE               (AR9170_GPIO_REG_BASE + 0x000)
+#define AR9170_GPIO_REG_PORT_DATA               (AR9170_GPIO_REG_BASE + 0x004)
+#define         AR9170_GPIO_PORT_LED_0                  1
+#define         AR9170_GPIO_PORT_LED_1                  2
+/* WPS Button GPIO for TP-Link TL-WN821N */
+#define         AR9170_GPIO_PORT_WPS_BUTTON_PRESSED     4
+
+/* Memory Controller */
+#define AR9170_MC_REG_BASE                      0x1d1000
+
+#define AR9170_MC_REG_FLASH_WAIT_STATE          (AR9170_MC_REG_BASE + 0x000)
+#define AR9170_MC_REG_SEEPROM_WP0               (AR9170_MC_REG_BASE + 0x400)
+#define AR9170_MC_REG_SEEPROM_WP1               (AR9170_MC_REG_BASE + 0x404)
+#define AR9170_MC_REG_SEEPROM_WP2               (AR9170_MC_REG_BASE + 0x408)
+
+/* Interrupt Controller */
+#define AR9170_MAX_INT_SRC                      9
+#define AR9170_INT_REG_BASE                     0x1d2000
+
+#define AR9170_INT_REG_FLAG                     (AR9170_INT_REG_BASE + 0x000)
+#define AR9170_INT_REG_FIQ_MASK                 (AR9170_INT_REG_BASE + 0x004)
+#define AR9170_INT_REG_IRQ_MASK                 (AR9170_INT_REG_BASE + 0x008)
+/* INT_REG_FLAG, INT_REG_FIQ_MASK and INT_REG_IRQ_MASK */
+#define         AR9170_INT_FLAG_WLAN                    0x001
+#define         AR9170_INT_FLAG_PTAB_BIT                0x002
+#define         AR9170_INT_FLAG_SE_BIT                  0x004
+#define         AR9170_INT_FLAG_UART_BIT                0x008
+#define         AR9170_INT_FLAG_TIMER_BIT               0x010
+#define         AR9170_INT_FLAG_EXT_BIT                 0x020
+#define         AR9170_INT_FLAG_SW_BIT                  0x040
+#define         AR9170_INT_FLAG_USB_BIT                 0x080
+#define         AR9170_INT_FLAG_ETHERNET_BIT            0x100
+
+#define AR9170_INT_REG_PRIORITY1                (AR9170_INT_REG_BASE + 0x00c)
+#define AR9170_INT_REG_PRIORITY2                (AR9170_INT_REG_BASE + 0x010)
+#define AR9170_INT_REG_PRIORITY3                (AR9170_INT_REG_BASE + 0x014)
+#define AR9170_INT_REG_EXT_INT_CONTROL          (AR9170_INT_REG_BASE + 0x018)
+#define AR9170_INT_REG_SW_INT_CONTROL           (AR9170_INT_REG_BASE + 0x01c)
+#define         AR9170_INT_SW_INT_ENABLE                0x1
+
+#define AR9170_INT_REG_FIQ_ENCODE               (AR9170_INT_REG_BASE + 0x020)
+#define AR9170_INT_INT_IRQ_ENCODE               (AR9170_INT_REG_BASE + 0x024)
+
+/* Power Management */
+#define AR9170_PWR_REG_BASE                     0x1d4000
+
+#define AR9170_PWR_REG_POWER_STATE              (AR9170_PWR_REG_BASE + 0x000)
+
+#define AR9170_PWR_REG_RESET                    (AR9170_PWR_REG_BASE + 0x004)
+#define         AR9170_PWR_RESET_COMMIT_RESET_MASK      BIT(0)
+#define         AR9170_PWR_RESET_WLAN_MASK              BIT(1)
+#define         AR9170_PWR_RESET_DMA_MASK               BIT(2)
+#define         AR9170_PWR_RESET_BRIDGE_MASK            BIT(3)
+#define         AR9170_PWR_RESET_AHB_MASK               BIT(9)
+#define         AR9170_PWR_RESET_BB_WARM_RESET          BIT(10)
+#define         AR9170_PWR_RESET_BB_COLD_RESET          BIT(11)
+#define         AR9170_PWR_RESET_ADDA_CLK_COLD_RESET    BIT(12)
+#define         AR9170_PWR_RESET_PLL                    BIT(13)
+#define         AR9170_PWR_RESET_USB_PLL                BIT(14)
+
+#define AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
+#define         AR9170_PWR_CLK_AHB_40MHZ                0
+#define         AR9170_PWR_CLK_AHB_20_22MHZ             1
+#define         AR9170_PWR_CLK_AHB_40_44MHZ             2
+#define         AR9170_PWR_CLK_AHB_80_88MHZ             3
+#define         AR9170_PWR_CLK_DAC_160_INV_DLY          0x70
+
+#define AR9170_PWR_REG_CHIP_REVISION            (AR9170_PWR_REG_BASE + 0x010)
+#define AR9170_PWR_REG_PLL_ADDAC                (AR9170_PWR_REG_BASE + 0x014)
+#define         AR9170_PWR_PLL_ADDAC_DIV_S              2
+#define         AR9170_PWR_PLL_ADDAC_DIV                0xffc
+#define AR9170_PWR_REG_WATCH_DOG_MAGIC          (AR9170_PWR_REG_BASE + 0x020)
+
+/* Faraday USB Controller */
+#define AR9170_USB_REG_BASE                     0x1e1000
+
+#define AR9170_USB_REG_MAIN_CTRL                (AR9170_USB_REG_BASE + 0x000)
+#define         AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP      BIT(0)
+#define         AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT  BIT(2)
+#define         AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND      BIT(3)
+#define         AR9170_USB_MAIN_CTRL_RESET              BIT(4)
+#define         AR9170_USB_MAIN_CTRL_CHIP_ENABLE        BIT(5)
+#define         AR9170_USB_MAIN_CTRL_HIGHSPEED          BIT(6)
+
+#define AR9170_USB_REG_DEVICE_ADDRESS           (AR9170_USB_REG_BASE + 0x001)
+#define         AR9170_USB_DEVICE_ADDRESS_CONFIGURE     BIT(7)
+
+#define AR9170_USB_REG_TEST                     (AR9170_USB_REG_BASE + 0x002)
+#define AR9170_USB_REG_PHY_TEST_SELECT          (AR9170_USB_REG_BASE + 0x008)
+#define AR9170_USB_REG_CX_CONFIG_STATUS         (AR9170_USB_REG_BASE + 0x00b)
+#define AR9170_USB_REG_EP0_DATA                 (AR9170_USB_REG_BASE + 0x00c)
+#define AR9170_USB_REG_EP0_DATA1                (AR9170_USB_REG_BASE + 0x00c)
+#define AR9170_USB_REG_EP0_DATA2                (AR9170_USB_REG_BASE + 0x00d)
+
+#define AR9170_USB_REG_INTR_MASK_BYTE_0         (AR9170_USB_REG_BASE + 0x011)
+#define AR9170_USB_REG_INTR_MASK_BYTE_1         (AR9170_USB_REG_BASE + 0x012)
+#define AR9170_USB_REG_INTR_MASK_BYTE_2         (AR9170_USB_REG_BASE + 0x013)
+#define AR9170_USB_REG_INTR_MASK_BYTE_3         (AR9170_USB_REG_BASE + 0x014)
+#define AR9170_USB_REG_INTR_MASK_BYTE_4         (AR9170_USB_REG_BASE + 0x015)
+#define         AR9170_USB_INTR_DISABLE_OUT_INT         (BIT(7) | BIT(6))
+
+#define AR9170_USB_REG_INTR_MASK_BYTE_5         (AR9170_USB_REG_BASE + 0x016)
+#define AR9170_USB_REG_INTR_MASK_BYTE_6         (AR9170_USB_REG_BASE + 0x017)
+#define         AR9170_USB_INTR_DISABLE_IN_INT          BIT(6)
+
+#define AR9170_USB_REG_INTR_MASK_BYTE_7         (AR9170_USB_REG_BASE + 0x018)
+
+#define AR9170_USB_REG_INTR_GROUP               (AR9170_USB_REG_BASE + 0x020)
+
+#define AR9170_USB_REG_INTR_SOURCE_0            (AR9170_USB_REG_BASE + 0x021)
+#define         AR9170_USB_INTR_SRC0_SETUP              BIT(0)
+#define         AR9170_USB_INTR_SRC0_IN                 BIT(1)
+#define         AR9170_USB_INTR_SRC0_OUT                BIT(2)
+#define         AR9170_USB_INTR_SRC0_FAIL               BIT(3) /* ??? */
+#define         AR9170_USB_INTR_SRC0_END                BIT(4) /* ??? */
+#define         AR9170_USB_INTR_SRC0_ABORT              BIT(7)
+
+#define AR9170_USB_REG_INTR_SOURCE_1            (AR9170_USB_REG_BASE + 0x022)
+#define AR9170_USB_REG_INTR_SOURCE_2            (AR9170_USB_REG_BASE + 0x023)
+#define AR9170_USB_REG_INTR_SOURCE_3            (AR9170_USB_REG_BASE + 0x024)
+#define AR9170_USB_REG_INTR_SOURCE_4            (AR9170_USB_REG_BASE + 0x025)
+#define AR9170_USB_REG_INTR_SOURCE_5            (AR9170_USB_REG_BASE + 0x026)
+#define AR9170_USB_REG_INTR_SOURCE_6            (AR9170_USB_REG_BASE + 0x027)
+#define AR9170_USB_REG_INTR_SOURCE_7            (AR9170_USB_REG_BASE + 0x028)
+#define         AR9170_USB_INTR_SRC7_USB_RESET          BIT(1)
+#define         AR9170_USB_INTR_SRC7_USB_SUSPEND        BIT(2)
+#define         AR9170_USB_INTR_SRC7_USB_RESUME         BIT(3)
+#define         AR9170_USB_INTR_SRC7_ISO_SEQ_ERR        BIT(4)
+#define         AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT      BIT(5)
+#define         AR9170_USB_INTR_SRC7_TX0BYTE            BIT(6)
+#define         AR9170_USB_INTR_SRC7_RX0BYTE            BIT(7)
+
+#define AR9170_USB_REG_IDLE_COUNT               (AR9170_USB_REG_BASE + 0x02f)
+
+#define AR9170_USB_REG_EP_MAP                   (AR9170_USB_REG_BASE + 0x030)
+#define AR9170_USB_REG_EP1_MAP                  (AR9170_USB_REG_BASE + 0x030)
+#define AR9170_USB_REG_EP2_MAP                  (AR9170_USB_REG_BASE + 0x031)
+#define AR9170_USB_REG_EP3_MAP                  (AR9170_USB_REG_BASE + 0x032)
+#define AR9170_USB_REG_EP4_MAP                  (AR9170_USB_REG_BASE + 0x033)
+#define AR9170_USB_REG_EP5_MAP                  (AR9170_USB_REG_BASE + 0x034)
+#define AR9170_USB_REG_EP6_MAP                  (AR9170_USB_REG_BASE + 0x035)
+#define AR9170_USB_REG_EP7_MAP                  (AR9170_USB_REG_BASE + 0x036)
+#define AR9170_USB_REG_EP8_MAP                  (AR9170_USB_REG_BASE + 0x037)
+#define AR9170_USB_REG_EP9_MAP                  (AR9170_USB_REG_BASE + 0x038)
+#define AR9170_USB_REG_EP10_MAP                 (AR9170_USB_REG_BASE + 0x039)
+
+#define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH      (AR9170_USB_REG_BASE + 0x03f)
+#define         AR9170_USB_EP_IN_TOGGLE                 0x10
+
+#define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW       (AR9170_USB_REG_BASE + 0x03e)
+
+#define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH     (AR9170_USB_REG_BASE + 0x05f)
+#define         AR9170_USB_EP_OUT_TOGGLE                0x10
+
+#define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW      (AR9170_USB_REG_BASE + 0x05e)
+
+#define AR9170_USB_REG_EP3_BYTE_COUNT_HIGH      (AR9170_USB_REG_BASE + 0x0ae)
+#define AR9170_USB_REG_EP3_BYTE_COUNT_LOW       (AR9170_USB_REG_BASE + 0x0be)
+#define AR9170_USB_REG_EP4_BYTE_COUNT_HIGH      (AR9170_USB_REG_BASE + 0x0af)
+#define AR9170_USB_REG_EP4_BYTE_COUNT_LOW       (AR9170_USB_REG_BASE + 0x0bf)
+
+#define AR9170_USB_REG_FIFO_MAP                 (AR9170_USB_REG_BASE + 0x080)
+#define AR9170_USB_REG_FIFO0_MAP                (AR9170_USB_REG_BASE + 0x080)
+#define AR9170_USB_REG_FIFO1_MAP                (AR9170_USB_REG_BASE + 0x081)
+#define AR9170_USB_REG_FIFO2_MAP                (AR9170_USB_REG_BASE + 0x082)
+#define AR9170_USB_REG_FIFO3_MAP                (AR9170_USB_REG_BASE + 0x083)
+#define AR9170_USB_REG_FIFO4_MAP                (AR9170_USB_REG_BASE + 0x084)
+#define AR9170_USB_REG_FIFO5_MAP                (AR9170_USB_REG_BASE + 0x085)
+#define AR9170_USB_REG_FIFO6_MAP                (AR9170_USB_REG_BASE + 0x086)
+#define AR9170_USB_REG_FIFO7_MAP                (AR9170_USB_REG_BASE + 0x087)
+#define AR9170_USB_REG_FIFO8_MAP                (AR9170_USB_REG_BASE + 0x088)
+#define AR9170_USB_REG_FIFO9_MAP                (AR9170_USB_REG_BASE + 0x089)
+
+#define AR9170_USB_REG_FIFO_CONFIG              (AR9170_USB_REG_BASE + 0x090)
+#define AR9170_USB_REG_FIFO0_CONFIG             (AR9170_USB_REG_BASE + 0x090)
+#define AR9170_USB_REG_FIFO1_CONFIG             (AR9170_USB_REG_BASE + 0x091)
+#define AR9170_USB_REG_FIFO2_CONFIG             (AR9170_USB_REG_BASE + 0x092)
+#define AR9170_USB_REG_FIFO3_CONFIG             (AR9170_USB_REG_BASE + 0x093)
+#define AR9170_USB_REG_FIFO4_CONFIG             (AR9170_USB_REG_BASE + 0x094)
+#define AR9170_USB_REG_FIFO5_CONFIG             (AR9170_USB_REG_BASE + 0x095)
+#define AR9170_USB_REG_FIFO6_CONFIG             (AR9170_USB_REG_BASE + 0x096)
+#define AR9170_USB_REG_FIFO7_CONFIG             (AR9170_USB_REG_BASE + 0x097)
+#define AR9170_USB_REG_FIFO8_CONFIG             (AR9170_USB_REG_BASE + 0x098)
+#define AR9170_USB_REG_FIFO9_CONFIG             (AR9170_USB_REG_BASE + 0x099)
+
+#define AR9170_USB_REG_EP3_DATA                 (AR9170_USB_REG_BASE + 0x0f8)
+#define AR9170_USB_REG_EP4_DATA                 (AR9170_USB_REG_BASE + 0x0fc)
+
+#define AR9170_USB_REG_FIFO_SIZE                (AR9170_USB_REG_BASE + 0x100)
+#define AR9170_USB_REG_DMA_CTL                  (AR9170_USB_REG_BASE + 0x108)
+#define         AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE     BIT(0)
+#define         AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE   BIT(1)
+#define         AR9170_USB_DMA_CTL_HIGH_SPEED           BIT(2)
+#define         AR9170_USB_DMA_CTL_UP_PACKET_MODE       BIT(3)
+#define         AR9170_USB_DMA_CTL_UP_STREAM_S          4
+#define         AR9170_USB_DMA_CTL_UP_STREAM            (BIT(4) | BIT(5))
+#define         AR9170_USB_DMA_CTL_UP_STREAM_4K         (0)
+#define         AR9170_USB_DMA_CTL_UP_STREAM_8K         BIT(4)
+#define         AR9170_USB_DMA_CTL_UP_STREAM_16K        BIT(5)
+#define         AR9170_USB_DMA_CTL_UP_STREAM_32K        (BIT(4) | BIT(5))
+#define         AR9170_USB_DMA_CTL_DOWN_STREAM          BIT(6)
+
+#define AR9170_USB_REG_DMA_STATUS               (AR9170_USB_REG_BASE + 0x10c)
+#define         AR9170_USB_DMA_STATUS_UP_IDLE           BIT(8)
+#define         AR9170_USB_DMA_STATUS_DN_IDLE           BIT(16)
+
+#define AR9170_USB_REG_MAX_AGG_UPLOAD           (AR9170_USB_REG_BASE + 0x110)
+#define AR9170_USB_REG_UPLOAD_TIME_CTL          (AR9170_USB_REG_BASE + 0x114)
+
+#define AR9170_USB_REG_WAKE_UP                  (AR9170_USB_REG_BASE + 0x120)
+#define         AR9170_USB_WAKE_UP_WAKE                 BIT(0)
+
+#define AR9170_USB_REG_CBUS_CTRL                (AR9170_USB_REG_BASE + 0x1f0)
+#define         AR9170_USB_CBUS_CTRL_BUFFER_END         (BIT(1))
+
+/* PCI/USB to AHB Bridge */
+#define AR9170_PTA_REG_BASE                     0x1e2000
+
+#define AR9170_PTA_REG_CMD                      (AR9170_PTA_REG_BASE + 0x000)
+#define AR9170_PTA_REG_PARAM1                   (AR9170_PTA_REG_BASE + 0x004)
+#define AR9170_PTA_REG_PARAM2                   (AR9170_PTA_REG_BASE + 0x008)
+#define AR9170_PTA_REG_PARAM3                   (AR9170_PTA_REG_BASE + 0x00c)
+#define AR9170_PTA_REG_RSP                      (AR9170_PTA_REG_BASE + 0x010)
+#define AR9170_PTA_REG_STATUS1                  (AR9170_PTA_REG_BASE + 0x014)
+#define AR9170_PTA_REG_STATUS2                  (AR9170_PTA_REG_BASE + 0x018)
+#define AR9170_PTA_REG_STATUS3                  (AR9170_PTA_REG_BASE + 0x01c)
+#define AR9170_PTA_REG_AHB_INT_FLAG             (AR9170_PTA_REG_BASE + 0x020)
+#define AR9170_PTA_REG_AHB_INT_MASK             (AR9170_PTA_REG_BASE + 0x024)
+#define AR9170_PTA_REG_AHB_INT_ACK              (AR9170_PTA_REG_BASE + 0x028)
+#define AR9170_PTA_REG_AHB_SCRATCH1             (AR9170_PTA_REG_BASE + 0x030)
+#define AR9170_PTA_REG_AHB_SCRATCH2             (AR9170_PTA_REG_BASE + 0x034)
+#define AR9170_PTA_REG_AHB_SCRATCH3             (AR9170_PTA_REG_BASE + 0x038)
+#define AR9170_PTA_REG_AHB_SCRATCH4             (AR9170_PTA_REG_BASE + 0x03c)
+
+#define AR9170_PTA_REG_SHARE_MEM_CTRL           (AR9170_PTA_REG_BASE + 0x124)
+
+/*
+ * PCI to AHB Bridge
+ */
+
+#define AR9170_PTA_REG_INT_FLAG                 (AR9170_PTA_REG_BASE + 0x100)
+#define         AR9170_PTA_INT_FLAG_DN                  0x01
+#define         AR9170_PTA_INT_FLAG_UP                  0x02
+#define         AR9170_PTA_INT_FLAG_CMD                 0x04
+
+#define AR9170_PTA_REG_INT_MASK                 (AR9170_PTA_REG_BASE + 0x104)
+#define AR9170_PTA_REG_DN_DMA_ADDRL             (AR9170_PTA_REG_BASE + 0x108)
+#define AR9170_PTA_REG_DN_DMA_ADDRH             (AR9170_PTA_REG_BASE + 0x10c)
+#define AR9170_PTA_REG_UP_DMA_ADDRL             (AR9170_PTA_REG_BASE + 0x110)
+#define AR9170_PTA_REG_UP_DMA_ADDRH             (AR9170_PTA_REG_BASE + 0x114)
+#define AR9170_PTA_REG_DN_PEND_TIME             (AR9170_PTA_REG_BASE + 0x118)
+#define AR9170_PTA_REG_UP_PEND_TIME             (AR9170_PTA_REG_BASE + 0x11c)
+#define AR9170_PTA_REG_CONTROL                  (AR9170_PTA_REG_BASE + 0x120)
+#define         AR9170_PTA_CTRL_4_BEAT_BURST            0x00
+#define         AR9170_PTA_CTRL_8_BEAT_BURST            0x01
+#define         AR9170_PTA_CTRL_16_BEAT_BURST           0x02
+#define         AR9170_PTA_CTRL_LOOPBACK_MODE           0x10
+
+#define AR9170_PTA_REG_MEM_CTRL                 (AR9170_PTA_REG_BASE + 0x124)
+#define AR9170_PTA_REG_MEM_ADDR                 (AR9170_PTA_REG_BASE + 0x128)
+#define AR9170_PTA_REG_DN_DMA_TRIGGER           (AR9170_PTA_REG_BASE + 0x12c)
+#define AR9170_PTA_REG_UP_DMA_TRIGGER           (AR9170_PTA_REG_BASE + 0x130)
+#define AR9170_PTA_REG_DMA_STATUS               (AR9170_PTA_REG_BASE + 0x134)
+#define AR9170_PTA_REG_DN_CURR_ADDRL            (AR9170_PTA_REG_BASE + 0x138)
+#define AR9170_PTA_REG_DN_CURR_ADDRH            (AR9170_PTA_REG_BASE + 0x13c)
+#define AR9170_PTA_REG_UP_CURR_ADDRL            (AR9170_PTA_REG_BASE + 0x140)
+#define AR9170_PTA_REG_UP_CURR_ADDRH            (AR9170_PTA_REG_BASE + 0x144)
+#define AR9170_PTA_REG_DMA_MODE_CTRL            (AR9170_PTA_REG_BASE + 0x148)
+#define         AR9170_PTA_DMA_MODE_CTRL_RESET          BIT(0)
+#define         AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB    BIT(1)
+
+/* Protocol Controller Module */
+#define AR9170_MAC_REG_PC_REG_BASE              (AR9170_MAC_REG_BASE + 0xe00)
+
+
+#define AR9170_NUM_LEDS                         2
+
+/* CAM */
+#define AR9170_CAM_MAX_USER                     64
+#define AR9170_CAM_MAX_KEY_LENGTH               16
+
+#define AR9170_SRAM_OFFSET              0x100000
+#define AR9170_SRAM_SIZE                0x18000
+
+#define AR9170_PRAM_OFFSET              0x200000
+#define AR9170_PRAM_SIZE                0x8000
+
+enum cpu_clock {
+        AHB_STATIC_40MHZ = 0,
+        AHB_GMODE_22MHZ = 1,
+        AHB_AMODE_20MHZ = 1,
+        AHB_GMODE_44MHZ = 2,
+        AHB_AMODE_40MHZ = 2,
+        AHB_GMODE_88MHZ = 3,
+        AHB_AMODE_80MHZ = 3
+};
+
+/* USB endpoints */
+enum ar9170_usb_ep {
+        /*
+         * Control EP is always EP 0 (USB SPEC)
+         *
+         * The weird thing is: the original firmware has a few
+         * comments that suggest that the actual EP numbers
+         * are in the 1 to 10 range?!
+         */
+        AR9170_USB_EP_CTRL              = 0,
+
+        AR9170_USB_EP_TX,
+        AR9170_USB_EP_RX,
+        AR9170_USB_EP_IRQ,
+        AR9170_USB_EP_CMD,
+        AR9170_USB_NUM_EXTRA_EP         = 4,
+
+        __AR9170_USB_NUM_EP,
+
+        __AR9170_USB_NUM_MAX_EP         = 10
+};
+
+enum ar9170_usb_fifo {
+        __AR9170_USB_NUM_MAX_FIFO       = 10
+};
+
+enum ar9170_tx_queues {
+        AR9170_TXQ0     = 0,
+        AR9170_TXQ1,
+        AR9170_TXQ2,
+        AR9170_TXQ3,
+        AR9170_TXQ_SPECIAL,
+
+        /* keep last */
+        __AR9170_NUM_TX_QUEUES = 5
+};
+
+#define AR9170_TX_STREAM_TAG            0x697e
+#define AR9170_RX_STREAM_TAG            0x4e00
+#define AR9170_RX_STREAM_MAX_SIZE       0xffff
+
+struct ar9170_stream {
+        __le16 length;
+        __le16 tag;
+
+        u8 payload[0];
+} __packed __aligned(4);
+#define AR9170_STREAM_LEN                               4
+
+#define AR9170_MAX_ACKTABLE_ENTRIES                     8
+#define AR9170_MAX_VIRTUAL_MAC                          7
+
+#define AR9170_USB_EP_CTRL_MAX                          64
+#define AR9170_USB_EP_TX_MAX                            512
+#define AR9170_USB_EP_RX_MAX                            512
+#define AR9170_USB_EP_IRQ_MAX                           64
+#define AR9170_USB_EP_CMD_MAX                           64
+
+/* Trigger PRETBTT interrupt 6 Kus earlier */
+#define CARL9170_PRETBTT_KUS                            6
+
+#define AR5416_MAX_RATE_POWER                           63
+
+#define SET_VAL(reg, value, newvalue)                                   \
+        (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))
+
+#define SET_CONSTVAL(reg, newvalue)                                     \
+        (((newvalue) << reg##_S) & reg)
+
+#define MOD_VAL(reg, value, newvalue)                                   \
+        (((value) & ~reg) | (((newvalue) << reg##_S) & reg))
+
+#define GET_VAL(reg, value)                                             \
+        (((value) & reg) >> reg##_S)
+
+#endif  /* __CARL9170_SHARED_HW_H */
diff --git a/drivers/net/wireless/ath/ar9170/led.c b/drivers/net/wireless/ath/carl9170/led.c
index 832d90087f8a..4bb2cbd8bd9b 100644
--- a/drivers/net/wireless/ath/ar9170/led.c
+++ b/drivers/net/wireless/ath/carl9170/led.c
@@ -1,9 +1,10 @@
 /*
- * Atheros AR9170 driver
+ * Atheros CARL9170 driver
  *
  * LED handling
  *
  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparer <chunkeey@googlemail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -36,58 +37,62 @@
  *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ar9170.h"
+#include "carl9170.h"
 #include "cmd.h"
 
-int ar9170_set_leds_state(struct ar9170 *ar, u32 led_state)
+int carl9170_led_set_state(struct ar9170 *ar, const u32 led_state)
 {
-        return ar9170_write_reg(ar, AR9170_GPIO_REG_DATA, led_state);
+        return carl9170_write_reg(ar, AR9170_GPIO_REG_PORT_DATA, led_state);
 }
 
-int ar9170_init_leds(struct ar9170 *ar)
+int carl9170_led_init(struct ar9170 *ar)
 {
         int err;
 
         /* disable LEDs */
         /* GPIO [0/1 mode: output, 2/3: input] */
-        err = ar9170_write_reg(ar, AR9170_GPIO_REG_PORT_TYPE, 3);
+        err = carl9170_write_reg(ar, AR9170_GPIO_REG_PORT_TYPE, 3);
         if (err)
                 goto out;
 
         /* GPIO 0/1 value: off */
-        err = ar9170_set_leds_state(ar, 0);
+        err = carl9170_led_set_state(ar, 0);
 
 out:
         return err;
 }
 
-#ifdef CONFIG_AR9170_LEDS
-static void ar9170_update_leds(struct work_struct *work)
+#ifdef CONFIG_CARL9170_LEDS
+static void carl9170_led_update(struct work_struct *work)
 {
         struct ar9170 *ar = container_of(work, struct ar9170, led_work.work);
-        int i, tmp, blink_delay = 1000;
+        int i, tmp = 300, blink_delay = 1000;
         u32 led_val = 0;
         bool rerun = false;
 
-        if (unlikely(!IS_ACCEPTING_CMD(ar)))
-                return ;
+        if (!IS_ACCEPTING_CMD(ar))
+                return;
 
         mutex_lock(&ar->mutex);
-        for (i = 0; i < AR9170_NUM_LEDS; i++)
-                if (ar->leds[i].registered && ar->leds[i].toggled) {
-                        led_val |= 1 << i;
+        for (i = 0; i < AR9170_NUM_LEDS; i++) {
+                if (ar->leds[i].registered) {
+                        if (ar->leds[i].last_state ||
+                            ar->leds[i].toggled) {
 
-                        tmp = 70 + 200 / (ar->leds[i].toggled);
-                        if (tmp < blink_delay)
-                                blink_delay = tmp;
+                                if (ar->leds[i].toggled)
+                                        tmp = 70 + 200 / (ar->leds[i].toggled);
 
-                        if (ar->leds[i].toggled > 1)
-                                ar->leds[i].toggled = 0;
+                                if (tmp < blink_delay)
+                                        blink_delay = tmp;
 
-                        rerun = true;
+                                led_val |= 1 << i;
+                                ar->leds[i].toggled = 0;
+                                rerun = true;
+                        }
                 }
+        }
 
-        ar9170_set_leds_state(ar, led_val);
+        carl9170_led_set_state(ar, led_val);
         mutex_unlock(&ar->mutex);
 
         if (!rerun)
@@ -98,14 +103,14 @@ static void ar9170_update_leds(struct work_struct *work)
                                      msecs_to_jiffies(blink_delay));
 }
 
-static void ar9170_led_brightness_set(struct led_classdev *led,
-                                      enum led_brightness brightness)
+static void carl9170_led_set_brightness(struct led_classdev *led,
+                                        enum led_brightness brightness)
 {
-        struct ar9170_led *arl = container_of(led, struct ar9170_led, l);
+        struct carl9170_led *arl = container_of(led, struct carl9170_led, l);
         struct ar9170 *ar = arl->ar;
 
-        if (unlikely(!arl->registered))
-                return ;
+        if (!arl->registered)
+                return;
 
         if (arl->last_state != !!brightness) {
                 arl->toggled++;
@@ -116,32 +121,33 @@ static void ar9170_led_brightness_set(struct led_classdev *led,
                 ieee80211_queue_delayed_work(ar->hw, &ar->led_work, HZ/10);
 }
 
-static int ar9170_register_led(struct ar9170 *ar, int i, char *name,
-                               char *trigger)
+static int carl9170_led_register_led(struct ar9170 *ar, int i, char *name,
+                                     char *trigger)
 {
         int err;
 
         snprintf(ar->leds[i].name, sizeof(ar->leds[i].name),
-                 "ar9170-%s::%s", wiphy_name(ar->hw->wiphy), name);
+                 "carl9170-%s::%s", wiphy_name(ar->hw->wiphy), name);
 
         ar->leds[i].ar = ar;
         ar->leds[i].l.name = ar->leds[i].name;
-        ar->leds[i].l.brightness_set = ar9170_led_brightness_set;
+        ar->leds[i].l.brightness_set = carl9170_led_set_brightness;
         ar->leds[i].l.brightness = 0;
         ar->leds[i].l.default_trigger = trigger;
 
         err = led_classdev_register(wiphy_dev(ar->hw->wiphy),
                                     &ar->leds[i].l);
-        if (err)
+        if (err) {
                 wiphy_err(ar->hw->wiphy, "failed to register %s LED (%d).\n",
-                          ar->leds[i].name, err);
-        else
+                        ar->leds[i].name, err);
+        } else {
                 ar->leds[i].registered = true;
+        }
 
         return err;
 }
 
-void ar9170_unregister_leds(struct ar9170 *ar)
+void carl9170_led_unregister(struct ar9170 *ar)
 {
         int i;
 
@@ -155,27 +161,30 @@ void ar9170_unregister_leds(struct ar9170 *ar)
         cancel_delayed_work_sync(&ar->led_work);
 }
 
-int ar9170_register_leds(struct ar9170 *ar)
+int carl9170_led_register(struct ar9170 *ar)
 {
         int err;
 
-        INIT_DELAYED_WORK(&ar->led_work, ar9170_update_leds);
+        INIT_DELAYED_WORK(&ar->led_work, carl9170_led_update);
 
-        err = ar9170_register_led(ar, 0, "tx",
-                                  ieee80211_get_tx_led_name(ar->hw));
+        err = carl9170_led_register_led(ar, 0, "tx",
+                                        ieee80211_get_tx_led_name(ar->hw));
         if (err)
                 goto fail;
 
-        err = ar9170_register_led(ar, 1, "assoc",
-                                 ieee80211_get_assoc_led_name(ar->hw));
+        if (ar->features & CARL9170_ONE_LED)
+                return 0;
+
+        err = carl9170_led_register_led(ar, 1, "assoc",
+                                        ieee80211_get_assoc_led_name(ar->hw));
         if (err)
                 goto fail;
 
         return 0;
 
 fail:
-        ar9170_unregister_leds(ar);
+        carl9170_led_unregister(ar);
         return err;
 }
 
-#endif /* CONFIG_AR9170_LEDS */
+#endif /* CONFIG_CARL9170_LEDS */
diff --git a/drivers/net/wireless/ath/carl9170/mac.c b/drivers/net/wireless/ath/carl9170/mac.c
new file mode 100644
index 000000000000..385cf508479b
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/mac.c
@@ -0,0 +1,616 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * MAC programming
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <asm/unaligned.h>
+
+#include "carl9170.h"
+#include "cmd.h"
+
+int carl9170_set_dyn_sifs_ack(struct ar9170 *ar)
+{
+        u32 val;
+
+        if (conf_is_ht40(&ar->hw->conf))
+                val = 0x010a;
+        else {
+                if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
+                        val = 0x105;
+                else
+                        val = 0x104;
+        }
+
+        return carl9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val);
+}
+
+int carl9170_set_rts_cts_rate(struct ar9170 *ar)
+{
+        u32 rts_rate, cts_rate;
+
+        if (conf_is_ht(&ar->hw->conf)) {
+                /* 12 mbit OFDM */
+                rts_rate = 0x1da;
+                cts_rate = 0x10a;
+        } else {
+                if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
+                        /* 11 mbit CCK */
+                        rts_rate = 033;
+                        cts_rate = 003;
+                } else {
+                        /* 6 mbit OFDM */
+                        rts_rate = 0x1bb;
+                        cts_rate = 0x10b;
+                }
+        }
+
+        return carl9170_write_reg(ar, AR9170_MAC_REG_RTS_CTS_RATE,
+                                  rts_rate | (cts_rate) << 16);
+}
+
+int carl9170_set_slot_time(struct ar9170 *ar)
+{
+        struct ieee80211_vif *vif;
+        u32 slottime = 20;
+
+        rcu_read_lock();
+        vif = carl9170_get_main_vif(ar);
+        if (!vif) {
+                rcu_read_unlock();
+                return 0;
+        }
+
+        if ((ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ) ||
+            vif->bss_conf.use_short_slot)
+                slottime = 9;
+
+        rcu_read_unlock();
+
+        return carl9170_write_reg(ar, AR9170_MAC_REG_SLOT_TIME,
+                                  slottime << 10);
+}
+
+int carl9170_set_mac_rates(struct ar9170 *ar)
+{
+        struct ieee80211_vif *vif;
+        u32 basic, mandatory;
+
+        rcu_read_lock();
+        vif = carl9170_get_main_vif(ar);
+
+        if (!vif) {
+                rcu_read_unlock();
+                return 0;
+        }
+
+        basic = (vif->bss_conf.basic_rates & 0xf);
+        basic |= (vif->bss_conf.basic_rates & 0xff0) << 4;
+        rcu_read_unlock();
+
+        if (ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ)
+                mandatory = 0xff00; /* OFDM 6/9/12/18/24/36/48/54 */
+        else
+                mandatory = 0xff0f; /* OFDM (6/9../54) + CCK (1/2/5.5/11) */
+
+        carl9170_regwrite_begin(ar);
+        carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, basic);
+        carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, mandatory);
+        carl9170_regwrite_finish();
+
+        return carl9170_regwrite_result();
+}
+
+int carl9170_set_qos(struct ar9170 *ar)
+{
+        carl9170_regwrite_begin(ar);
+
+        carl9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
+                          (ar->edcf[0].cw_max << 16));
+        carl9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
+                          (ar->edcf[1].cw_max << 16));
+        carl9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
+                          (ar->edcf[2].cw_max << 16));
+        carl9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
+                          (ar->edcf[3].cw_max << 16));
+        carl9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
+                          (ar->edcf[4].cw_max << 16));
+
+        carl9170_regwrite(AR9170_MAC_REG_AC2_AC1_AC0_AIFS,
+                          ((ar->edcf[0].aifs * 9 + 10)) |
+                          ((ar->edcf[1].aifs * 9 + 10) << 12) |
+                          ((ar->edcf[2].aifs * 9 + 10) << 24));
+        carl9170_regwrite(AR9170_MAC_REG_AC4_AC3_AC2_AIFS,
+                          ((ar->edcf[2].aifs * 9 + 10) >> 8) |
+                          ((ar->edcf[3].aifs * 9 + 10) << 4) |
+                          ((ar->edcf[4].aifs * 9 + 10) << 16));
+
+        carl9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
+                          ar->edcf[0].txop | ar->edcf[1].txop << 16);
+        carl9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
+                          ar->edcf[2].txop | ar->edcf[3].txop << 16 |
+                          ar->edcf[4].txop << 24);
+
+        carl9170_regwrite_finish();
+
+        return carl9170_regwrite_result();
+}
+
+int carl9170_init_mac(struct ar9170 *ar)
+{
+        carl9170_regwrite_begin(ar);
+
+        /* switch MAC to OTUS interface */
+        carl9170_regwrite(0x1c3600, 0x3);
+
+        carl9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
+
+        carl9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0x0);
+
+        carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
+                          AR9170_MAC_FTF_MONITOR);
+
+        /* enable MMIC */
+        carl9170_regwrite(AR9170_MAC_REG_SNIFFER,
+                        AR9170_MAC_SNIFFER_DEFAULTS);
+
+        carl9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
+
+        carl9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
+        carl9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
+        carl9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
+
+        /* CF-END & CF-ACK rate => 24M OFDM */
+        carl9170_regwrite(AR9170_MAC_REG_TID_CFACK_CFEND_RATE, 0x59900000);
+
+        /* NAV protects ACK only (in TXOP) */
+        carl9170_regwrite(AR9170_MAC_REG_TXOP_DURATION, 0x201);
+
+        /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
+        /* OTUS set AM to 0x1 */
+        carl9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
+
+        carl9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
+
+        /* Aggregation MAX number and timeout */
+        carl9170_regwrite(AR9170_MAC_REG_AMPDU_FACTOR, 0x8000a);
+        carl9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, 0x140a07);
+
+        carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
+                          AR9170_MAC_FTF_DEFAULTS);
+
+        carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL,
+                          AR9170_MAC_RX_CTRL_DEAGG |
+                          AR9170_MAC_RX_CTRL_SHORT_FILTER);
+
+        /* rate sets */
+        carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
+        carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
+        carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x0030033);
+
+        /* MIMO response control */
+        carl9170_regwrite(AR9170_MAC_REG_ACK_TPC, 0x4003c1e);
+
+        carl9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
+
+        /* set PHY register read timeout (??) */
+        carl9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
+
+        /* Disable Rx TimeOut, workaround for BB. */
+        carl9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
+
+        /* Set WLAN DMA interrupt mode: generate int per packet */
+        carl9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
+
+        carl9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
+                        AR9170_MAC_FCS_FIFO_PROT);
+
+        /* Disables the CF_END frame, undocumented register */
+        carl9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
+                        0x141e0f48);
+
+        /* reset group hash table */
+        carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, 0xffffffff);
+        carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, 0xffffffff);
+
+        /* disable PRETBTT interrupt */
+        carl9170_regwrite(AR9170_MAC_REG_PRETBTT, 0x0);
+        carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, 0x0);
+
+        carl9170_regwrite_finish();
+
+        return carl9170_regwrite_result();
+}
+
+static int carl9170_set_mac_reg(struct ar9170 *ar,
+                                const u32 reg, const u8 *mac)
+{
+        static const u8 zero[ETH_ALEN] = { 0 };
+
+        if (!mac)
+                mac = zero;
+
+        carl9170_regwrite_begin(ar);
+
+        carl9170_regwrite(reg, get_unaligned_le32(mac));
+        carl9170_regwrite(reg + 4, get_unaligned_le16(mac + 4));
+
+        carl9170_regwrite_finish();
+
+        return carl9170_regwrite_result();
+}
+
+int carl9170_mod_virtual_mac(struct ar9170 *ar, const unsigned int id,
+                             const u8 *mac)
+{
+        if (WARN_ON(id >= ar->fw.vif_num))
+                return -EINVAL;
+
+        return carl9170_set_mac_reg(ar,
+                AR9170_MAC_REG_ACK_TABLE + (id - 1) * 8, mac);
+}
+
+int carl9170_update_multicast(struct ar9170 *ar, const u64 mc_hash)
+{
+        int err;
+
+        carl9170_regwrite_begin(ar);
+        carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, mc_hash >> 32);
+        carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, mc_hash);
+        carl9170_regwrite_finish();
+        err = carl9170_regwrite_result();
+        if (err)
+                return err;
+
+        ar->cur_mc_hash = mc_hash;
+        return 0;
+}
+
+int carl9170_set_operating_mode(struct ar9170 *ar)
+{
+        struct ieee80211_vif *vif;
+        struct ath_common *common = &ar->common;
+        u8 *mac_addr, *bssid;
+        u32 cam_mode = AR9170_MAC_CAM_DEFAULTS;
+        u32 enc_mode = AR9170_MAC_ENCRYPTION_DEFAULTS;
+        u32 rx_ctrl = AR9170_MAC_RX_CTRL_DEAGG |
+                      AR9170_MAC_RX_CTRL_SHORT_FILTER;
+        u32 sniffer = AR9170_MAC_SNIFFER_DEFAULTS;
+        int err = 0;
+
+        rcu_read_lock();
+        vif = carl9170_get_main_vif(ar);
+
+        if (vif) {
+                mac_addr = common->macaddr;
+                bssid = common->curbssid;
+
+                switch (vif->type) {
+                case NL80211_IFTYPE_MESH_POINT:
+                case NL80211_IFTYPE_ADHOC:
+                        cam_mode |= AR9170_MAC_CAM_IBSS;
+                        break;
+                case NL80211_IFTYPE_AP:
+                        cam_mode |= AR9170_MAC_CAM_AP;
+
+                        /* iwlagn 802.11n STA Workaround */
+                        rx_ctrl |= AR9170_MAC_RX_CTRL_PASS_TO_HOST;
+                        break;
+                case NL80211_IFTYPE_WDS:
+                        cam_mode |= AR9170_MAC_CAM_AP_WDS;
+                        rx_ctrl |= AR9170_MAC_RX_CTRL_PASS_TO_HOST;
+                        break;
+                case NL80211_IFTYPE_STATION:
+                        cam_mode |= AR9170_MAC_CAM_STA;
+                        rx_ctrl |= AR9170_MAC_RX_CTRL_PASS_TO_HOST;
+                        break;
+                default:
+                        WARN(1, "Unsupported operation mode %x\n", vif->type);
+                        err = -EOPNOTSUPP;
+                        break;
+                }
+        } else {
+                mac_addr = NULL;
+                bssid = NULL;
+        }
+        rcu_read_unlock();
+
+        if (err)
+                return err;
+
+        if (ar->rx_software_decryption)
+                enc_mode |= AR9170_MAC_ENCRYPTION_RX_SOFTWARE;
+
+        if (ar->sniffer_enabled) {
+                rx_ctrl |= AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER;
+                sniffer |= AR9170_MAC_SNIFFER_ENABLE_PROMISC;
+                enc_mode |= AR9170_MAC_ENCRYPTION_RX_SOFTWARE;
+        }
+
+        err = carl9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr);
+        if (err)
+                return err;
+
+        err = carl9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid);
+        if (err)
+                return err;
+
+        carl9170_regwrite_begin(ar);
+        carl9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
+        carl9170_regwrite(AR9170_MAC_REG_CAM_MODE, cam_mode);
+        carl9170_regwrite(AR9170_MAC_REG_ENCRYPTION, enc_mode);
+        carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL, rx_ctrl);
+        carl9170_regwrite_finish();
+
+        return carl9170_regwrite_result();
+}
+
+int carl9170_set_hwretry_limit(struct ar9170 *ar, const unsigned int max_retry)
+{
+        u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111);
+
+        return carl9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
+}
+
+int carl9170_set_beacon_timers(struct ar9170 *ar)
+{
+        struct ieee80211_vif *vif;
+        u32 v = 0;
+        u32 pretbtt = 0;
+
+        rcu_read_lock();
+        vif = carl9170_get_main_vif(ar);
+
+        if (vif) {
+                struct carl9170_vif_info *mvif;
+                mvif = (void *) vif->drv_priv;
+
+                if (mvif->enable_beacon && !WARN_ON(!ar->beacon_enabled)) {
+                        ar->global_beacon_int = vif->bss_conf.beacon_int /
+                                                ar->beacon_enabled;
+
+                        SET_VAL(AR9170_MAC_BCN_DTIM, v,
+                                vif->bss_conf.dtim_period);
+
+                        switch (vif->type) {
+                        case NL80211_IFTYPE_MESH_POINT:
+                        case NL80211_IFTYPE_ADHOC:
+                                v |= AR9170_MAC_BCN_IBSS_MODE;
+                                break;
+                        case NL80211_IFTYPE_AP:
+                                v |= AR9170_MAC_BCN_AP_MODE;
+                                break;
+                        default:
+                                WARN_ON_ONCE(1);
+                                break;
+                        }
+                } else if (vif->type == NL80211_IFTYPE_STATION) {
+                        ar->global_beacon_int = vif->bss_conf.beacon_int;
+
+                        SET_VAL(AR9170_MAC_BCN_DTIM, v,
+                                ar->hw->conf.ps_dtim_period);
+
+                        v |= AR9170_MAC_BCN_STA_PS |
+                             AR9170_MAC_BCN_PWR_MGT;
+                }
+
+                if (ar->global_beacon_int) {
+                        if (ar->global_beacon_int < 15) {
+                                rcu_read_unlock();
+                                return -ERANGE;
+                        }
+
+                        ar->global_pretbtt = ar->global_beacon_int -
+                                        CARL9170_PRETBTT_KUS;
+                } else {
+                        ar->global_pretbtt = 0;
+                }
+        } else {
+                ar->global_beacon_int = 0;
+                ar->global_pretbtt = 0;
+        }
+
+        rcu_read_unlock();
+
+        SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int);
+        SET_VAL(AR9170_MAC_PRETBTT, pretbtt, ar->global_pretbtt);
+        SET_VAL(AR9170_MAC_PRETBTT2, pretbtt, ar->global_pretbtt);
+
+        carl9170_regwrite_begin(ar);
+        carl9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
+        carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
+        carl9170_regwrite_finish();
+        return carl9170_regwrite_result();
+}
+
+int carl9170_update_beacon(struct ar9170 *ar, const bool submit)
+{
+        struct sk_buff *skb = NULL;
+        struct carl9170_vif_info *cvif;
+        struct ieee80211_tx_info *txinfo;
+        __le32 *data, *old = NULL;
+        u32 word, off, addr, len;
+        int i = 0, err = 0;
+
+        rcu_read_lock();
+        cvif = rcu_dereference(ar->beacon_iter);
+retry:
+        if (ar->vifs == 0 || !cvif)
+                goto out_unlock;
+
+        list_for_each_entry_continue_rcu(cvif, &ar->vif_list, list) {
+                if (cvif->active && cvif->enable_beacon)
+                        goto found;
+        }
+
+        if (!ar->beacon_enabled || i++)
+                goto out_unlock;
+
+        goto retry;
+
+found:
+        rcu_assign_pointer(ar->beacon_iter, cvif);
+
+        skb = ieee80211_beacon_get_tim(ar->hw, carl9170_get_vif(cvif),
+                NULL, NULL);
+
+        if (!skb) {
+                err = -ENOMEM;
+                goto err_free;
+        }
+
+        txinfo = IEEE80211_SKB_CB(skb);
+        if (txinfo->control.rates[0].flags & IEEE80211_TX_RC_MCS) {
+                err = -EINVAL;
+                goto err_free;
+        }
+
+        spin_lock_bh(&ar->beacon_lock);
+        data = (__le32 *)skb->data;
+        if (cvif->beacon)
+                old = (__le32 *)cvif->beacon->data;
+
+        off = cvif->id * AR9170_MAC_BCN_LENGTH_MAX;
+        addr = ar->fw.beacon_addr + off;
+        len = roundup(skb->len + FCS_LEN, 4);
+
+        if ((off + len) > ar->fw.beacon_max_len) {
+                if (net_ratelimit()) {
+                        wiphy_err(ar->hw->wiphy, "beacon does not "
+                                  "fit into device memory!\n");
+                }
+                err = -EINVAL;
+                goto err_unlock;
+        }
+
+        if (len > AR9170_MAC_BCN_LENGTH_MAX) {
+                if (net_ratelimit()) {
+                        wiphy_err(ar->hw->wiphy, "no support for beacons "
+                                "bigger than %d (yours:%d).\n",
+                                 AR9170_MAC_BCN_LENGTH_MAX, len);
+                }
+
+                err = -EMSGSIZE;
+                goto err_unlock;
+        }
+
+        i = txinfo->control.rates[0].idx;
+        if (txinfo->band != IEEE80211_BAND_2GHZ)
+                i += 4;
+
+        word = __carl9170_ratetable[i].hw_value & 0xf;
+        if (i < 4)
+                word |= ((skb->len + FCS_LEN) << (3 + 16)) + 0x0400;
+        else
+                word |= ((skb->len + FCS_LEN) << 16) + 0x0010;
+
+        carl9170_async_regwrite_begin(ar);
+        carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP, word);
+
+        for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
+                /*
+                 * XXX: This accesses beyond skb data for up
+                 *      to the last 3 bytes!!
+                 */
+
+                if (old && (data[i] == old[i]))
+                        continue;
+
+                word = le32_to_cpu(data[i]);
+                carl9170_async_regwrite(addr + 4 * i, word);
+        }
+        carl9170_async_regwrite_finish();
+
+        dev_kfree_skb_any(cvif->beacon);
+        cvif->beacon = NULL;
+
+        err = carl9170_async_regwrite_result();
+        if (!err)
+                cvif->beacon = skb;
+        spin_unlock_bh(&ar->beacon_lock);
+        if (err)
+                goto err_free;
+
+        if (submit) {
+                err = carl9170_bcn_ctrl(ar, cvif->id,
+                                        CARL9170_BCN_CTRL_CAB_TRIGGER,
+                                        addr, skb->len + FCS_LEN);
+
+                if (err)
+                        goto err_free;
+        }
+out_unlock:
+        rcu_read_unlock();
+        return 0;
+
+err_unlock:
+        spin_unlock_bh(&ar->beacon_lock);
+
+err_free:
+        rcu_read_unlock();
+        dev_kfree_skb_any(skb);
+        return err;
+}
+
+int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac,
+                        const u8 ktype, const u8 keyidx, const u8 *keydata,
+                        const int keylen)
+{
+        struct carl9170_set_key_cmd key = { };
+        static const u8 bcast[ETH_ALEN] = {
+                0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+        mac = mac ? : bcast;
+
+        key.user = cpu_to_le16(id);
+        key.keyId = cpu_to_le16(keyidx);
+        key.type = cpu_to_le16(ktype);
+        memcpy(&key.macAddr, mac, ETH_ALEN);
+        if (keydata)
+                memcpy(&key.key, keydata, keylen);
+
+        return carl9170_exec_cmd(ar, CARL9170_CMD_EKEY,
+                sizeof(key), (u8 *)&key, 0, NULL);
+}
+
+int carl9170_disable_key(struct ar9170 *ar, const u8 id)
+{
+        struct carl9170_disable_key_cmd key = { };
+
+        key.user = cpu_to_le16(id);
+
+        return carl9170_exec_cmd(ar, CARL9170_CMD_DKEY,
+                sizeof(key), (u8 *)&key, 0, NULL);
+}
diff --git a/drivers/net/wireless/ath/carl9170/main.c b/drivers/net/wireless/ath/carl9170/main.c
new file mode 100644
index 000000000000..54d093c2ab44
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/main.c
@@ -0,0 +1,1831 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * mac80211 interaction code
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <linux/random.h>
+#include <net/mac80211.h>
+#include <net/cfg80211.h>
+#include "hw.h"
+#include "carl9170.h"
+#include "cmd.h"
+
+static int modparam_nohwcrypt;
+module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
+MODULE_PARM_DESC(nohwcrypt, "Disable hardware crypto offload.");
+
+int modparam_noht;
+module_param_named(noht, modparam_noht, int, S_IRUGO);
+MODULE_PARM_DESC(noht, "Disable MPDU aggregation.");
+
+#define RATE(_bitrate, _hw_rate, _txpidx, _flags) {     \
+        .bitrate        = (_bitrate),                   \
+        .flags          = (_flags),                     \
+        .hw_value       = (_hw_rate) | (_txpidx) << 4,  \
+}
+
+struct ieee80211_rate __carl9170_ratetable[] = {
+        RATE(10, 0, 0, 0),
+        RATE(20, 1, 1, IEEE80211_RATE_SHORT_PREAMBLE),
+        RATE(55, 2, 2, IEEE80211_RATE_SHORT_PREAMBLE),
+        RATE(110, 3, 3, IEEE80211_RATE_SHORT_PREAMBLE),
+        RATE(60, 0xb, 0, 0),
+        RATE(90, 0xf, 0, 0),
+        RATE(120, 0xa, 0, 0),
+        RATE(180, 0xe, 0, 0),
+        RATE(240, 0x9, 0, 0),
+        RATE(360, 0xd, 1, 0),
+        RATE(480, 0x8, 2, 0),
+        RATE(540, 0xc, 3, 0),
+};
+#undef RATE
+
+#define carl9170_g_ratetable    (__carl9170_ratetable + 0)
+#define carl9170_g_ratetable_size       12
+#define carl9170_a_ratetable    (__carl9170_ratetable + 4)
+#define carl9170_a_ratetable_size       8
+
+/*
+ * NB: The hw_value is used as an index into the carl9170_phy_freq_params
+ *     array in phy.c so that we don't have to do frequency lookups!
+ */
+#define CHAN(_freq, _idx) {             \
+        .center_freq    = (_freq),      \
+        .hw_value       = (_idx),       \
+        .max_power      = 18, /* XXX */ \
+}
+
+static struct ieee80211_channel carl9170_2ghz_chantable[] = {
+        CHAN(2412,  0),
+        CHAN(2417,  1),
+        CHAN(2422,  2),
+        CHAN(2427,  3),
+        CHAN(2432,  4),
+        CHAN(2437,  5),
+        CHAN(2442,  6),
+        CHAN(2447,  7),
+        CHAN(2452,  8),
+        CHAN(2457,  9),
+        CHAN(2462, 10),
+        CHAN(2467, 11),
+        CHAN(2472, 12),
+        CHAN(2484, 13),
+};
+
+static struct ieee80211_channel carl9170_5ghz_chantable[] = {
+        CHAN(4920, 14),
+        CHAN(4940, 15),
+        CHAN(4960, 16),
+        CHAN(4980, 17),
+        CHAN(5040, 18),
+        CHAN(5060, 19),
+        CHAN(5080, 20),
+        CHAN(5180, 21),
+        CHAN(5200, 22),
+        CHAN(5220, 23),
+        CHAN(5240, 24),
+        CHAN(5260, 25),
+        CHAN(5280, 26),
+        CHAN(5300, 27),
+        CHAN(5320, 28),
+        CHAN(5500, 29),
+        CHAN(5520, 30),
+        CHAN(5540, 31),
+        CHAN(5560, 32),
+        CHAN(5580, 33),
+        CHAN(5600, 34),
+        CHAN(5620, 35),
+        CHAN(5640, 36),
+        CHAN(5660, 37),
+        CHAN(5680, 38),
+        CHAN(5700, 39),
+        CHAN(5745, 40),
+        CHAN(5765, 41),
+        CHAN(5785, 42),
+        CHAN(5805, 43),
+        CHAN(5825, 44),
+        CHAN(5170, 45),
+        CHAN(5190, 46),
+        CHAN(5210, 47),
+        CHAN(5230, 48),
+};
+#undef CHAN
+
+#define CARL9170_HT_CAP                                                 \
+{                                                                       \
+        .ht_supported   = true,                                         \
+        .cap            = IEEE80211_HT_CAP_MAX_AMSDU |                  \
+                          IEEE80211_HT_CAP_SUP_WIDTH_20_40 |            \
+                          IEEE80211_HT_CAP_SGI_40 |                     \
+                          IEEE80211_HT_CAP_DSSSCCK40 |                  \
+                          IEEE80211_HT_CAP_SM_PS,                       \
+        .ampdu_factor   = IEEE80211_HT_MAX_AMPDU_64K,                   \
+        .ampdu_density  = IEEE80211_HT_MPDU_DENSITY_8,                  \
+        .mcs            = {                                             \
+                .rx_mask = { 0xff, 0xff, 0, 0, 0x1, 0, 0, 0, 0, 0, },   \
+                .rx_highest = cpu_to_le16(300),                         \
+                .tx_params = IEEE80211_HT_MCS_TX_DEFINED,               \
+        },                                                              \
+}
+
+static struct ieee80211_supported_band carl9170_band_2GHz = {
+        .channels       = carl9170_2ghz_chantable,
+        .n_channels     = ARRAY_SIZE(carl9170_2ghz_chantable),
+        .bitrates       = carl9170_g_ratetable,
+        .n_bitrates     = carl9170_g_ratetable_size,
+        .ht_cap         = CARL9170_HT_CAP,
+};
+
+static struct ieee80211_supported_band carl9170_band_5GHz = {
+        .channels       = carl9170_5ghz_chantable,
+        .n_channels     = ARRAY_SIZE(carl9170_5ghz_chantable),
+        .bitrates       = carl9170_a_ratetable,
+        .n_bitrates     = carl9170_a_ratetable_size,
+        .ht_cap         = CARL9170_HT_CAP,
+};
+
+static void carl9170_ampdu_gc(struct ar9170 *ar)
+{
+        struct carl9170_sta_tid *tid_info;
+        LIST_HEAD(tid_gc);
+
+        rcu_read_lock();
+        list_for_each_entry_rcu(tid_info, &ar->tx_ampdu_list, list) {
+                spin_lock_bh(&ar->tx_ampdu_list_lock);
+                if (tid_info->state == CARL9170_TID_STATE_SHUTDOWN) {
+                        tid_info->state = CARL9170_TID_STATE_KILLED;
+                        list_del_rcu(&tid_info->list);
+                        ar->tx_ampdu_list_len--;
+                        list_add_tail(&tid_info->tmp_list, &tid_gc);
+                }
+                spin_unlock_bh(&ar->tx_ampdu_list_lock);
+
+        }
+        rcu_assign_pointer(ar->tx_ampdu_iter, tid_info);
+        rcu_read_unlock();
+
+        synchronize_rcu();
+
+        while (!list_empty(&tid_gc)) {
+                struct sk_buff *skb;
+                tid_info = list_first_entry(&tid_gc, struct carl9170_sta_tid,
+                                            tmp_list);
+
+                while ((skb = __skb_dequeue(&tid_info->queue)))
+                        carl9170_tx_status(ar, skb, false);
+
+                list_del_init(&tid_info->tmp_list);
+                kfree(tid_info);
+        }
+}
+
+static void carl9170_flush(struct ar9170 *ar, bool drop_queued)
+{
+        if (drop_queued) {
+                int i;
+
+                /*
+                 * We can only drop frames which have not been uploaded
+                 * to the device yet.
+                 */
+
+                for (i = 0; i < ar->hw->queues; i++) {
+                        struct sk_buff *skb;
+
+                        while ((skb = skb_dequeue(&ar->tx_pending[i]))) {
+                                struct ieee80211_tx_info *info;
+
+                                info = IEEE80211_SKB_CB(skb);
+                                if (info->flags & IEEE80211_TX_CTL_AMPDU)
+                                        atomic_dec(&ar->tx_ampdu_upload);
+
+                                carl9170_tx_status(ar, skb, false);
+                        }
+                }
+        }
+
+        /* Wait for all other outstanding frames to timeout. */
+        if (atomic_read(&ar->tx_total_queued))
+                WARN_ON(wait_for_completion_timeout(&ar->tx_flush, HZ) == 0);
+}
+
+static void carl9170_flush_ba(struct ar9170 *ar)
+{
+        struct sk_buff_head free;
+        struct carl9170_sta_tid *tid_info;
+        struct sk_buff *skb;
+
+        __skb_queue_head_init(&free);
+
+        rcu_read_lock();
+        spin_lock_bh(&ar->tx_ampdu_list_lock);
+        list_for_each_entry_rcu(tid_info, &ar->tx_ampdu_list, list) {
+                if (tid_info->state > CARL9170_TID_STATE_SUSPEND) {
+                        tid_info->state = CARL9170_TID_STATE_SUSPEND;
+
+                        spin_lock(&tid_info->lock);
+                        while ((skb = __skb_dequeue(&tid_info->queue)))
+                                __skb_queue_tail(&free, skb);
+                        spin_unlock(&tid_info->lock);
+                }
+        }
+        spin_unlock_bh(&ar->tx_ampdu_list_lock);
+        rcu_read_unlock();
+
+        while ((skb = __skb_dequeue(&free)))
+                carl9170_tx_status(ar, skb, false);
+}
+
+static void carl9170_zap_queues(struct ar9170 *ar)
+{
+        struct carl9170_vif_info *cvif;
+        unsigned int i;
+
+        carl9170_ampdu_gc(ar);
+
+        carl9170_flush_ba(ar);
+        carl9170_flush(ar, true);
+
+        for (i = 0; i < ar->hw->queues; i++) {
+                spin_lock_bh(&ar->tx_status[i].lock);
+                while (!skb_queue_empty(&ar->tx_status[i])) {
+                        struct sk_buff *skb;
+
+                        skb = skb_peek(&ar->tx_status[i]);
+                        carl9170_tx_get_skb(skb);
+                        spin_unlock_bh(&ar->tx_status[i].lock);
+                        carl9170_tx_drop(ar, skb);
+                        spin_lock_bh(&ar->tx_status[i].lock);
+                        carl9170_tx_put_skb(skb);
+                }
+                spin_unlock_bh(&ar->tx_status[i].lock);
+        }
+
+        BUILD_BUG_ON(CARL9170_NUM_TX_LIMIT_SOFT < 1);
+        BUILD_BUG_ON(CARL9170_NUM_TX_LIMIT_HARD < CARL9170_NUM_TX_LIMIT_SOFT);
+        BUILD_BUG_ON(CARL9170_NUM_TX_LIMIT_HARD >= CARL9170_BAW_BITS);
+
+        /* reinitialize queues statistics */
+        memset(&ar->tx_stats, 0, sizeof(ar->tx_stats));
+        for (i = 0; i < ar->hw->queues; i++)
+                ar->tx_stats[i].limit = CARL9170_NUM_TX_LIMIT_HARD;
+
+        for (i = 0; i < DIV_ROUND_UP(ar->fw.mem_blocks, BITS_PER_LONG); i++)
+                ar->mem_bitmap[i] = 0;
+
+        rcu_read_lock();
+        list_for_each_entry_rcu(cvif, &ar->vif_list, list) {
+                spin_lock_bh(&ar->beacon_lock);
+                dev_kfree_skb_any(cvif->beacon);
+                cvif->beacon = NULL;
+                spin_unlock_bh(&ar->beacon_lock);
+        }
+        rcu_read_unlock();
+
+        atomic_set(&ar->tx_ampdu_upload, 0);
+        atomic_set(&ar->tx_ampdu_scheduler, 0);
+        atomic_set(&ar->tx_total_pending, 0);
+        atomic_set(&ar->tx_total_queued, 0);
+        atomic_set(&ar->mem_free_blocks, ar->fw.mem_blocks);
+}
+
+#define CARL9170_FILL_QUEUE(queue, ai_fs, cwmin, cwmax, _txop)          \
+do {                                                                    \
+        queue.aifs = ai_fs;                                             \
+        queue.cw_min = cwmin;                                           \
+        queue.cw_max = cwmax;                                           \
+        queue.txop = _txop;                                             \
+} while (0)
+
+static int carl9170_op_start(struct ieee80211_hw *hw)
+{
+        struct ar9170 *ar = hw->priv;
+        int err, i;
+
+        mutex_lock(&ar->mutex);
+
+        carl9170_zap_queues(ar);
+
+        /* reset QoS defaults */
+        CARL9170_FILL_QUEUE(ar->edcf[0], 3, 15, 1023,  0); /* BEST EFFORT */
+        CARL9170_FILL_QUEUE(ar->edcf[1], 2, 7,    15, 94); /* VIDEO */
+        CARL9170_FILL_QUEUE(ar->edcf[2], 2, 3,     7, 47); /* VOICE */
+        CARL9170_FILL_QUEUE(ar->edcf[3], 7, 15, 1023,  0); /* BACKGROUND */
+        CARL9170_FILL_QUEUE(ar->edcf[4], 2, 3,     7,  0); /* SPECIAL */
+
+        ar->current_factor = ar->current_density = -1;
+        /* "The first key is unique." */
+        ar->usedkeys = 1;
+        ar->filter_state = 0;
+        ar->ps.last_action = jiffies;
+        ar->ps.last_slept = jiffies;
+        ar->erp_mode = CARL9170_ERP_AUTO;
+        ar->rx_software_decryption = false;
+        ar->disable_offload = false;
+
+        for (i = 0; i < ar->hw->queues; i++) {
+                ar->queue_stop_timeout[i] = jiffies;
+                ar->max_queue_stop_timeout[i] = 0;
+        }
+
+        atomic_set(&ar->mem_allocs, 0);
+
+        err = carl9170_usb_open(ar);
+        if (err)
+                goto out;
+
+        err = carl9170_init_mac(ar);
+        if (err)
+                goto out;
+
+        err = carl9170_set_qos(ar);
+        if (err)
+                goto out;
+
+        if (ar->fw.rx_filter) {
+                err = carl9170_rx_filter(ar, CARL9170_RX_FILTER_OTHER_RA |
+                        CARL9170_RX_FILTER_CTL_OTHER | CARL9170_RX_FILTER_BAD);
+                if (err)
+                        goto out;
+        }
+
+        err = carl9170_write_reg(ar, AR9170_MAC_REG_DMA_TRIGGER,
+                                 AR9170_DMA_TRIGGER_RXQ);
+        if (err)
+                goto out;
+
+        /* Clear key-cache */
+        for (i = 0; i < AR9170_CAM_MAX_USER + 4; i++) {
+                err = carl9170_upload_key(ar, i, NULL, AR9170_ENC_ALG_NONE,
+                                          0, NULL, 0);
+                if (err)
+                        goto out;
+
+                err = carl9170_upload_key(ar, i, NULL, AR9170_ENC_ALG_NONE,
+                                          1, NULL, 0);
+                if (err)
+                        goto out;
+
+                if (i < AR9170_CAM_MAX_USER) {
+                        err = carl9170_disable_key(ar, i);
+                        if (err)
+                                goto out;
+                }
+        }
+
+        carl9170_set_state_when(ar, CARL9170_IDLE, CARL9170_STARTED);
+
+        ieee80211_wake_queues(ar->hw);
+        err = 0;
+
+out:
+        mutex_unlock(&ar->mutex);
+        return err;
+}
+
+static void carl9170_cancel_worker(struct ar9170 *ar)
+{
+        cancel_delayed_work_sync(&ar->tx_janitor);
+#ifdef CONFIG_CARL9170_LEDS
+        cancel_delayed_work_sync(&ar->led_work);
+#endif /* CONFIG_CARL9170_LEDS */
+        cancel_work_sync(&ar->ps_work);
+        cancel_work_sync(&ar->ping_work);
+        cancel_work_sync(&ar->ampdu_work);
+}
+
+static void carl9170_op_stop(struct ieee80211_hw *hw)
+{
+        struct ar9170 *ar = hw->priv;
+
+        carl9170_set_state_when(ar, CARL9170_STARTED, CARL9170_IDLE);
+
+        ieee80211_stop_queues(ar->hw);
+
+        mutex_lock(&ar->mutex);
+        if (IS_ACCEPTING_CMD(ar)) {
+                rcu_assign_pointer(ar->beacon_iter, NULL);
+
+                carl9170_led_set_state(ar, 0);
+
+                /* stop DMA */
+                carl9170_write_reg(ar, AR9170_MAC_REG_DMA_TRIGGER, 0);
+                carl9170_usb_stop(ar);
+        }
+
+        carl9170_zap_queues(ar);
+        mutex_unlock(&ar->mutex);
+
+        carl9170_cancel_worker(ar);
+}
+
+static void carl9170_restart_work(struct work_struct *work)
+{
+        struct ar9170 *ar = container_of(work, struct ar9170,
+                                         restart_work);
+        int err;
+
+        ar->usedkeys = 0;
+        ar->filter_state = 0;
+        carl9170_cancel_worker(ar);
+
+        mutex_lock(&ar->mutex);
+        err = carl9170_usb_restart(ar);
+        if (net_ratelimit()) {
+                if (err) {
+                        dev_err(&ar->udev->dev, "Failed to restart device "
+                                " (%d).\n", err);
+                 } else {
+                        dev_info(&ar->udev->dev, "device restarted "
+                                 "successfully.\n");
+                }
+        }
+
+        carl9170_zap_queues(ar);
+        mutex_unlock(&ar->mutex);
+        if (!err) {
+                ar->restart_counter++;
+                atomic_set(&ar->pending_restarts, 0);
+
+                ieee80211_restart_hw(ar->hw);
+        } else {
+                /*
+                 * The reset was unsuccessful and the device seems to
+                 * be dead. But there's still one option: a low-level
+                 * usb subsystem reset...
+                 */
+
+                carl9170_usb_reset(ar);
+        }
+}
+
+void carl9170_restart(struct ar9170 *ar, const enum carl9170_restart_reasons r)
+{
+        carl9170_set_state_when(ar, CARL9170_STARTED, CARL9170_IDLE);
+
+        /*
+         * Sometimes, an error can trigger several different reset events.
+         * By ignoring these *surplus* reset events, the device won't be
+         * killed again, right after it has recovered.
+         */
+        if (atomic_inc_return(&ar->pending_restarts) > 1) {
+                dev_dbg(&ar->udev->dev, "ignoring restart (%d)\n", r);
+                return;
+        }
+
+        ieee80211_stop_queues(ar->hw);
+
+        dev_err(&ar->udev->dev, "restart device (%d)\n", r);
+
+        if (!WARN_ON(r == CARL9170_RR_NO_REASON) ||
+            !WARN_ON(r >= __CARL9170_RR_LAST))
+                ar->last_reason = r;
+
+        if (!ar->registered)
+                return;
+
+        if (IS_ACCEPTING_CMD(ar) && !ar->needs_full_reset)
+                ieee80211_queue_work(ar->hw, &ar->restart_work);
+        else
+                carl9170_usb_reset(ar);
+
+        /*
+         * At this point, the device instance might have vanished/disabled.
+         * So, don't put any code which access the ar9170 struct
+         * without proper protection.
+         */
+}
+
+static void carl9170_ping_work(struct work_struct *work)
+{
+        struct ar9170 *ar = container_of(work, struct ar9170, ping_work);
+        int err;
+
+        if (!IS_STARTED(ar))
+                return;
+
+        mutex_lock(&ar->mutex);
+        err = carl9170_echo_test(ar, 0xdeadbeef);
+        if (err)
+                carl9170_restart(ar, CARL9170_RR_UNRESPONSIVE_DEVICE);
+        mutex_unlock(&ar->mutex);
+}
+
+static int carl9170_init_interface(struct ar9170 *ar,
+                                   struct ieee80211_vif *vif)
+{
+        struct ath_common *common = &ar->common;
+        int err;
+
+        if (!vif) {
+                WARN_ON_ONCE(IS_STARTED(ar));
+                return 0;
+        }
+
+        memcpy(common->macaddr, vif->addr, ETH_ALEN);
+
+        if (modparam_nohwcrypt ||
+            ((vif->type != NL80211_IFTYPE_STATION) &&
+             (vif->type != NL80211_IFTYPE_AP))) {
+                ar->rx_software_decryption = true;
+                ar->disable_offload = true;
+        }
+
+        err = carl9170_set_operating_mode(ar);
+        return err;
+}
+
+static int carl9170_op_add_interface(struct ieee80211_hw *hw,
+                                     struct ieee80211_vif *vif)
+{
+        struct carl9170_vif_info *vif_priv = (void *) vif->drv_priv;
+        struct ieee80211_vif *main_vif;
+        struct ar9170 *ar = hw->priv;
+        int vif_id = -1, err = 0;
+
+        mutex_lock(&ar->mutex);
+        rcu_read_lock();
+        if (vif_priv->active) {
+                /*
+                 * Skip the interface structure initialization,
+                 * if the vif survived the _restart call.
+                 */
+                vif_id = vif_priv->id;
+                vif_priv->enable_beacon = false;
+
+                spin_lock_bh(&ar->beacon_lock);
+                dev_kfree_skb_any(vif_priv->beacon);
+                vif_priv->beacon = NULL;
+                spin_unlock_bh(&ar->beacon_lock);
+
+                goto init;
+        }
+
+        main_vif = carl9170_get_main_vif(ar);
+
+        if (main_vif) {
+                switch (main_vif->type) {
+                case NL80211_IFTYPE_STATION:
+                        if (vif->type == NL80211_IFTYPE_STATION)
+                                break;
+
+                        err = -EBUSY;
+                        rcu_read_unlock();
+
+                        goto unlock;
+
+                case NL80211_IFTYPE_AP:
+                        if ((vif->type == NL80211_IFTYPE_STATION) ||
+                            (vif->type == NL80211_IFTYPE_WDS) ||
+                            (vif->type == NL80211_IFTYPE_AP))
+                                break;
+
+                        err = -EBUSY;
+                        rcu_read_unlock();
+                        goto unlock;
+
+                default:
+                        rcu_read_unlock();
+                        goto unlock;
+                }
+        }
+
+        vif_id = bitmap_find_free_region(&ar->vif_bitmap, ar->fw.vif_num, 0);
+
+        if (vif_id < 0) {
+                rcu_read_unlock();
+
+                err = -ENOSPC;
+                goto unlock;
+        }
+
+        BUG_ON(ar->vif_priv[vif_id].id != vif_id);
+
+        vif_priv->active = true;
+        vif_priv->id = vif_id;
+        vif_priv->enable_beacon = false;
+        ar->vifs++;
+        list_add_tail_rcu(&vif_priv->list, &ar->vif_list);
+        rcu_assign_pointer(ar->vif_priv[vif_id].vif, vif);
+
+init:
+        if (carl9170_get_main_vif(ar) == vif) {
+                rcu_assign_pointer(ar->beacon_iter, vif_priv);
+                rcu_read_unlock();
+
+                err = carl9170_init_interface(ar, vif);
+                if (err)
+                        goto unlock;
+        } else {
+                rcu_read_unlock();
+                err = carl9170_mod_virtual_mac(ar, vif_id, vif->addr);
+
+                if (err)
+                        goto unlock;
+        }
+
+        if (ar->fw.tx_seq_table) {
+                err = carl9170_write_reg(ar, ar->fw.tx_seq_table + vif_id * 4,
+                                         0);
+                if (err)
+                        goto unlock;
+        }
+
+unlock:
+        if (err && (vif_id >= 0)) {
+                vif_priv->active = false;
+                bitmap_release_region(&ar->vif_bitmap, vif_id, 0);
+                ar->vifs--;
+                rcu_assign_pointer(ar->vif_priv[vif_id].vif, NULL);
+                list_del_rcu(&vif_priv->list);
+                mutex_unlock(&ar->mutex);
+                synchronize_rcu();
+        } else {
+                if (ar->vifs > 1)
+                        ar->ps.off_override |= PS_OFF_VIF;
+
+                mutex_unlock(&ar->mutex);
+        }
+
+        return err;
+}
+
+static void carl9170_op_remove_interface(struct ieee80211_hw *hw,
+                                         struct ieee80211_vif *vif)
+{
+        struct carl9170_vif_info *vif_priv = (void *) vif->drv_priv;
+        struct ieee80211_vif *main_vif;
+        struct ar9170 *ar = hw->priv;
+        unsigned int id;
+
+        mutex_lock(&ar->mutex);
+
+        if (WARN_ON_ONCE(!vif_priv->active))
+                goto unlock;
+
+        ar->vifs--;
+
+        rcu_read_lock();
+        main_vif = carl9170_get_main_vif(ar);
+
+        id = vif_priv->id;
+
+        vif_priv->active = false;
+        WARN_ON(vif_priv->enable_beacon);
+        vif_priv->enable_beacon = false;
+        list_del_rcu(&vif_priv->list);
+        rcu_assign_pointer(ar->vif_priv[id].vif, NULL);
+
+        if (vif == main_vif) {
+                rcu_read_unlock();
+
+                if (ar->vifs) {
+                        WARN_ON(carl9170_init_interface(ar,
+                                        carl9170_get_main_vif(ar)));
+                } else {
+                        carl9170_set_operating_mode(ar);
+                }
+        } else {
+                rcu_read_unlock();
+
+                WARN_ON(carl9170_mod_virtual_mac(ar, id, NULL));
+        }
+
+        carl9170_update_beacon(ar, false);
+        carl9170_flush_cab(ar, id);
+
+        spin_lock_bh(&ar->beacon_lock);
+        dev_kfree_skb_any(vif_priv->beacon);
+        vif_priv->beacon = NULL;
+        spin_unlock_bh(&ar->beacon_lock);
+
+        bitmap_release_region(&ar->vif_bitmap, id, 0);
+
+        carl9170_set_beacon_timers(ar);
+
+        if (ar->vifs == 1)
+                ar->ps.off_override &= ~PS_OFF_VIF;
+
+unlock:
+        mutex_unlock(&ar->mutex);
+
+        synchronize_rcu();
+}
+
+void carl9170_ps_check(struct ar9170 *ar)
+{
+        ieee80211_queue_work(ar->hw, &ar->ps_work);
+}
+
+/* caller must hold ar->mutex */
+static int carl9170_ps_update(struct ar9170 *ar)
+{
+        bool ps = false;
+        int err = 0;
+
+        if (!ar->ps.off_override)
+                ps = (ar->hw->conf.flags & IEEE80211_CONF_PS);
+
+        if (ps != ar->ps.state) {
+                err = carl9170_powersave(ar, ps);
+                if (err)
+                        return err;
+
+                if (ar->ps.state && !ps) {
+                        ar->ps.sleep_ms = jiffies_to_msecs(jiffies -
+                                ar->ps.last_action);
+                }
+
+                if (ps)
+                        ar->ps.last_slept = jiffies;
+
+                ar->ps.last_action = jiffies;
+                ar->ps.state = ps;
+        }
+
+        return 0;
+}
+
+static void carl9170_ps_work(struct work_struct *work)
+{
+        struct ar9170 *ar = container_of(work, struct ar9170,
+                                         ps_work);
+        mutex_lock(&ar->mutex);
+        if (IS_STARTED(ar))
+                WARN_ON_ONCE(carl9170_ps_update(ar) != 0);
+        mutex_unlock(&ar->mutex);
+}
+
+
+static int carl9170_op_config(struct ieee80211_hw *hw, u32 changed)
+{
+        struct ar9170 *ar = hw->priv;
+        int err = 0;
+
+        mutex_lock(&ar->mutex);
+        if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {
+                /* TODO */
+                err = 0;
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_PS) {
+                err = carl9170_ps_update(ar);
+                if (err)
+                        goto out;
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                /* TODO */
+                err = 0;
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_SMPS) {
+                /* TODO */
+                err = 0;
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+                /* adjust slot time for 5 GHz */
+                err = carl9170_set_slot_time(ar);
+                if (err)
+                        goto out;
+
+                err = carl9170_set_channel(ar, hw->conf.channel,
+                        hw->conf.channel_type, CARL9170_RFI_NONE);
+                if (err)
+                        goto out;
+
+                err = carl9170_set_dyn_sifs_ack(ar);
+                if (err)
+                        goto out;
+
+                err = carl9170_set_rts_cts_rate(ar);
+                if (err)
+                        goto out;
+        }
+
+out:
+        mutex_unlock(&ar->mutex);
+        return err;
+}
+
+static u64 carl9170_op_prepare_multicast(struct ieee80211_hw *hw,
+                                         struct netdev_hw_addr_list *mc_list)
+{
+        struct netdev_hw_addr *ha;
+        u64 mchash;
+
+        /* always get broadcast frames */
+        mchash = 1ULL << (0xff >> 2);
+
+        netdev_hw_addr_list_for_each(ha, mc_list)
+                mchash |= 1ULL << (ha->addr[5] >> 2);
+
+        return mchash;
+}
+
+static void carl9170_op_configure_filter(struct ieee80211_hw *hw,
+                                         unsigned int changed_flags,
+                                         unsigned int *new_flags,
+                                         u64 multicast)
+{
+        struct ar9170 *ar = hw->priv;
+
+        /* mask supported flags */
+        *new_flags &= FIF_ALLMULTI | ar->rx_filter_caps;
+
+        if (!IS_ACCEPTING_CMD(ar))
+                return;
+
+        mutex_lock(&ar->mutex);
+
+        ar->filter_state = *new_flags;
+        /*
+         * We can support more by setting the sniffer bit and
+         * then checking the error flags, later.
+         */
+
+        if (*new_flags & FIF_ALLMULTI)
+                multicast = ~0ULL;
+
+        if (multicast != ar->cur_mc_hash)
+                WARN_ON(carl9170_update_multicast(ar, multicast));
+
+        if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
+                ar->sniffer_enabled = !!(*new_flags &
+                        (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS));
+
+                WARN_ON(carl9170_set_operating_mode(ar));
+        }
+
+        if (ar->fw.rx_filter && changed_flags & ar->rx_filter_caps) {
+                u32 rx_filter = 0;
+
+                if (!(*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)))
+                        rx_filter |= CARL9170_RX_FILTER_BAD;
+
+                if (!(*new_flags & FIF_CONTROL))
+                        rx_filter |= CARL9170_RX_FILTER_CTL_OTHER;
+
+                if (!(*new_flags & FIF_PSPOLL))
+                        rx_filter |= CARL9170_RX_FILTER_CTL_PSPOLL;
+
+                if (!(*new_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))) {
+                        rx_filter |= CARL9170_RX_FILTER_OTHER_RA;
+                        rx_filter |= CARL9170_RX_FILTER_DECRY_FAIL;
+                }
+
+                WARN_ON(carl9170_rx_filter(ar, rx_filter));
+        }
+
+        mutex_unlock(&ar->mutex);
+}
+
+
+static void carl9170_op_bss_info_changed(struct ieee80211_hw *hw,
+                                         struct ieee80211_vif *vif,
+                                         struct ieee80211_bss_conf *bss_conf,
+                                         u32 changed)
+{
+        struct ar9170 *ar = hw->priv;
+        struct ath_common *common = &ar->common;
+        int err = 0;
+        struct carl9170_vif_info *vif_priv;
+        struct ieee80211_vif *main_vif;
+
+        mutex_lock(&ar->mutex);
+        vif_priv = (void *) vif->drv_priv;
+        main_vif = carl9170_get_main_vif(ar);
+        if (WARN_ON(!main_vif))
+                goto out;
+
+        if (changed & BSS_CHANGED_BEACON_ENABLED) {
+                struct carl9170_vif_info *iter;
+                int i = 0;
+
+                vif_priv->enable_beacon = bss_conf->enable_beacon;
+                rcu_read_lock();
+                list_for_each_entry_rcu(iter, &ar->vif_list, list) {
+                        if (iter->active && iter->enable_beacon)
+                                i++;
+
+                }
+                rcu_read_unlock();
+
+                ar->beacon_enabled = i;
+        }
+
+        if (changed & BSS_CHANGED_BEACON) {
+                err = carl9170_update_beacon(ar, false);
+                if (err)
+                        goto out;
+        }
+
+        if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON |
+                       BSS_CHANGED_BEACON_INT)) {
+
+                if (main_vif != vif) {
+                        bss_conf->beacon_int = main_vif->bss_conf.beacon_int;
+                        bss_conf->dtim_period = main_vif->bss_conf.dtim_period;
+                }
+
+                /*
+                 * Therefore a hard limit for the broadcast traffic should
+                 * prevent false alarms.
+                 */
+                if (vif->type != NL80211_IFTYPE_STATION &&
+                    (bss_conf->beacon_int * bss_conf->dtim_period >=
+                     (CARL9170_QUEUE_STUCK_TIMEOUT / 2))) {
+                        err = -EINVAL;
+                        goto out;
+                }
+
+                err = carl9170_set_beacon_timers(ar);
+                if (err)
+                        goto out;
+        }
+
+        if (changed & BSS_CHANGED_HT) {
+                /* TODO */
+                err = 0;
+                if (err)
+                        goto out;
+        }
+
+        if (main_vif != vif)
+                goto out;
+
+        /*
+         * The following settings can only be changed by the
+         * master interface.
+         */
+
+        if (changed & BSS_CHANGED_BSSID) {
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                err = carl9170_set_operating_mode(ar);
+                if (err)
+                        goto out;
+        }
+
+        if (changed & BSS_CHANGED_ASSOC) {
+                ar->common.curaid = bss_conf->aid;
+                err = carl9170_set_beacon_timers(ar);
+                if (err)
+                        goto out;
+        }
+
+        if (changed & BSS_CHANGED_ERP_SLOT) {
+                err = carl9170_set_slot_time(ar);
+                if (err)
+                        goto out;
+        }
+
+        if (changed & BSS_CHANGED_BASIC_RATES) {
+                err = carl9170_set_mac_rates(ar);
+                if (err)
+                        goto out;
+        }
+
+out:
+        WARN_ON_ONCE(err && IS_STARTED(ar));
+        mutex_unlock(&ar->mutex);
+}
+
+static u64 carl9170_op_get_tsf(struct ieee80211_hw *hw)
+{
+        struct ar9170 *ar = hw->priv;
+        struct carl9170_tsf_rsp tsf;
+        int err;
+
+        mutex_lock(&ar->mutex);
+        err = carl9170_exec_cmd(ar, CARL9170_CMD_READ_TSF,
+                                0, NULL, sizeof(tsf), &tsf);
+        mutex_unlock(&ar->mutex);
+        if (WARN_ON(err))
+                return 0;
+
+        return le64_to_cpu(tsf.tsf_64);
+}
+
+static int carl9170_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+                               struct ieee80211_vif *vif,
+                               struct ieee80211_sta *sta,
+                               struct ieee80211_key_conf *key)
+{
+        struct ar9170 *ar = hw->priv;
+        int err = 0, i;
+        u8 ktype;
+
+        if (ar->disable_offload || !vif)
+                return -EOPNOTSUPP;
+
+        /*
+         * We have to fall back to software encryption, whenever
+         * the user choose to participates in an IBSS or is connected
+         * to more than one network.
+         *
+         * This is very unfortunate, because some machines cannot handle
+         * the high througput speed in 802.11n networks.
+         */
+
+        if (!is_main_vif(ar, vif))
+                goto err_softw;
+
+        /*
+         * While the hardware supports *catch-all* key, for offloading
+         * group-key en-/de-cryption. The way of how the hardware
+         * decides which keyId maps to which key, remains a mystery...
+         */
+        if ((vif->type != NL80211_IFTYPE_STATION &&
+             vif->type != NL80211_IFTYPE_ADHOC) &&
+            !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
+                return -EOPNOTSUPP;
+
+        switch (key->cipher) {
+        case WLAN_CIPHER_SUITE_WEP40:
+                ktype = AR9170_ENC_ALG_WEP64;
+                break;
+        case WLAN_CIPHER_SUITE_WEP104:
+                ktype = AR9170_ENC_ALG_WEP128;
+                break;
+        case WLAN_CIPHER_SUITE_TKIP:
+                ktype = AR9170_ENC_ALG_TKIP;
+                break;
+        case WLAN_CIPHER_SUITE_CCMP:
+                ktype = AR9170_ENC_ALG_AESCCMP;
+                break;
+        default:
+                return -EOPNOTSUPP;
+        }
+
+        mutex_lock(&ar->mutex);
+        if (cmd == SET_KEY) {
+                if (!IS_STARTED(ar)) {
+                        err = -EOPNOTSUPP;
+                        goto out;
+                }
+
+                if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
+                        sta = NULL;
+
+                        i = 64 + key->keyidx;
+                } else {
+                        for (i = 0; i < 64; i++)
+                                if (!(ar->usedkeys & BIT(i)))
+                                        break;
+                        if (i == 64)
+                                goto err_softw;
+                }
+
+                key->hw_key_idx = i;
+
+                err = carl9170_upload_key(ar, i, sta ? sta->addr : NULL,
+                                          ktype, 0, key->key,
+                                          min_t(u8, 16, key->keylen));
+                if (err)
+                        goto out;
+
+                if (key->cipher == WLAN_CIPHER_SUITE_TKIP) {
+                        err = carl9170_upload_key(ar, i, sta ? sta->addr :
+                                                  NULL, ktype, 1,
+                                                  key->key + 16, 16);
+                        if (err)
+                                goto out;
+
+                        /*
+                         * hardware is not capable generating MMIC
+                         * of fragmented frames!
+                         */
+                        key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+                }
+
+                if (i < 64)
+                        ar->usedkeys |= BIT(i);
+
+                key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
+        } else {
+                if (!IS_STARTED(ar)) {
+                        /* The device is gone... together with the key ;-) */
+                        err = 0;
+                        goto out;
+                }
+
+                if (key->hw_key_idx < 64) {
+                        ar->usedkeys &= ~BIT(key->hw_key_idx);
+                } else {
+                        err = carl9170_upload_key(ar, key->hw_key_idx, NULL,
+                                                  AR9170_ENC_ALG_NONE, 0,
+                                                  NULL, 0);
+                        if (err)
+                                goto out;
+
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP) {
+                                err = carl9170_upload_key(ar, key->hw_key_idx,
+                                                          NULL,
+                                                          AR9170_ENC_ALG_NONE,
+                                                          1, NULL, 0);
+                                if (err)
+                                        goto out;
+                        }
+
+                }
+
+                err = carl9170_disable_key(ar, key->hw_key_idx);
+                if (err)
+                        goto out;
+        }
+
+out:
+        mutex_unlock(&ar->mutex);
+        return err;
+
+err_softw:
+        if (!ar->rx_software_decryption) {
+                ar->rx_software_decryption = true;
+                carl9170_set_operating_mode(ar);
+        }
+        mutex_unlock(&ar->mutex);
+        return -ENOSPC;
+}
+
+static int carl9170_op_sta_add(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               struct ieee80211_sta *sta)
+{
+        struct carl9170_sta_info *sta_info = (void *) sta->drv_priv;
+        unsigned int i;
+
+        atomic_set(&sta_info->pending_frames, 0);
+
+        if (sta->ht_cap.ht_supported) {
+                if (sta->ht_cap.ampdu_density > 6) {
+                        /*
+                         * HW does support 16us AMPDU density.
+                         * No HT-Xmit for station.
+                         */
+
+                        return 0;
+                }
+
+                for (i = 0; i < CARL9170_NUM_TID; i++)
+                        rcu_assign_pointer(sta_info->agg[i], NULL);
+
+                sta_info->ampdu_max_len = 1 << (3 + sta->ht_cap.ampdu_factor);
+                sta_info->ht_sta = true;
+        }
+
+        return 0;
+}
+
+static int carl9170_op_sta_remove(struct ieee80211_hw *hw,
+                                struct ieee80211_vif *vif,
+                                struct ieee80211_sta *sta)
+{
+        struct ar9170 *ar = hw->priv;
+        struct carl9170_sta_info *sta_info = (void *) sta->drv_priv;
+        unsigned int i;
+        bool cleanup = false;
+
+        if (sta->ht_cap.ht_supported) {
+
+                sta_info->ht_sta = false;
+
+                rcu_read_lock();
+                for (i = 0; i < CARL9170_NUM_TID; i++) {
+                        struct carl9170_sta_tid *tid_info;
+
+                        tid_info = rcu_dereference(sta_info->agg[i]);
+                        rcu_assign_pointer(sta_info->agg[i], NULL);
+
+                        if (!tid_info)
+                                continue;
+
+                        spin_lock_bh(&ar->tx_ampdu_list_lock);
+                        if (tid_info->state > CARL9170_TID_STATE_SHUTDOWN)
+                                tid_info->state = CARL9170_TID_STATE_SHUTDOWN;
+                        spin_unlock_bh(&ar->tx_ampdu_list_lock);
+                        cleanup = true;
+                }
+                rcu_read_unlock();
+
+                if (cleanup)
+                        carl9170_ampdu_gc(ar);
+        }
+
+        return 0;
+}
+
+static int carl9170_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
+                               const struct ieee80211_tx_queue_params *param)
+{
+        struct ar9170 *ar = hw->priv;
+        int ret;
+
+        mutex_lock(&ar->mutex);
+        if (queue < ar->hw->queues) {
+                memcpy(&ar->edcf[ar9170_qmap[queue]], param, sizeof(*param));
+                ret = carl9170_set_qos(ar);
+        } else {
+                ret = -EINVAL;
+        }
+
+        mutex_unlock(&ar->mutex);
+        return ret;
+}
+
+static void carl9170_ampdu_work(struct work_struct *work)
+{
+        struct ar9170 *ar = container_of(work, struct ar9170,
+                                         ampdu_work);
+
+        if (!IS_STARTED(ar))
+                return;
+
+        mutex_lock(&ar->mutex);
+        carl9170_ampdu_gc(ar);
+        mutex_unlock(&ar->mutex);
+}
+
+static int carl9170_op_ampdu_action(struct ieee80211_hw *hw,
+                                    struct ieee80211_vif *vif,
+                                    enum ieee80211_ampdu_mlme_action action,
+                                    struct ieee80211_sta *sta,
+                                    u16 tid, u16 *ssn, u8 buf_size)
+{
+        struct ar9170 *ar = hw->priv;
+        struct carl9170_sta_info *sta_info = (void *) sta->drv_priv;
+        struct carl9170_sta_tid *tid_info;
+
+        if (modparam_noht)
+                return -EOPNOTSUPP;
+
+        switch (action) {
+        case IEEE80211_AMPDU_TX_START:
+                if (!sta_info->ht_sta)
+                        return -EOPNOTSUPP;
+
+                rcu_read_lock();
+                if (rcu_dereference(sta_info->agg[tid])) {
+                        rcu_read_unlock();
+                        return -EBUSY;
+                }
+
+                tid_info = kzalloc(sizeof(struct carl9170_sta_tid),
+                                   GFP_ATOMIC);
+                if (!tid_info) {
+                        rcu_read_unlock();
+                        return -ENOMEM;
+                }
+
+                tid_info->hsn = tid_info->bsn = tid_info->snx = (*ssn);
+                tid_info->state = CARL9170_TID_STATE_PROGRESS;
+                tid_info->tid = tid;
+                tid_info->max = sta_info->ampdu_max_len;
+
+                INIT_LIST_HEAD(&tid_info->list);
+                INIT_LIST_HEAD(&tid_info->tmp_list);
+                skb_queue_head_init(&tid_info->queue);
+                spin_lock_init(&tid_info->lock);
+
+                spin_lock_bh(&ar->tx_ampdu_list_lock);
+                ar->tx_ampdu_list_len++;
+                list_add_tail_rcu(&tid_info->list, &ar->tx_ampdu_list);
+                rcu_assign_pointer(sta_info->agg[tid], tid_info);
+                spin_unlock_bh(&ar->tx_ampdu_list_lock);
+                rcu_read_unlock();
+
+                ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+                break;
+
+        case IEEE80211_AMPDU_TX_STOP:
+                rcu_read_lock();
+                tid_info = rcu_dereference(sta_info->agg[tid]);
+                if (tid_info) {
+                        spin_lock_bh(&ar->tx_ampdu_list_lock);
+                        if (tid_info->state > CARL9170_TID_STATE_SHUTDOWN)
+                                tid_info->state = CARL9170_TID_STATE_SHUTDOWN;
+                        spin_unlock_bh(&ar->tx_ampdu_list_lock);
+                }
+
+                rcu_assign_pointer(sta_info->agg[tid], NULL);
+                rcu_read_unlock();
+
+                ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+                ieee80211_queue_work(ar->hw, &ar->ampdu_work);
+                break;
+
+        case IEEE80211_AMPDU_TX_OPERATIONAL:
+                rcu_read_lock();
+                tid_info = rcu_dereference(sta_info->agg[tid]);
+
+                sta_info->stats[tid].clear = true;
+                sta_info->stats[tid].req = false;
+
+                if (tid_info) {
+                        bitmap_zero(tid_info->bitmap, CARL9170_BAW_SIZE);
+                        tid_info->state = CARL9170_TID_STATE_IDLE;
+                }
+                rcu_read_unlock();
+
+                if (WARN_ON_ONCE(!tid_info))
+                        return -EFAULT;
+
+                break;
+
+        case IEEE80211_AMPDU_RX_START:
+        case IEEE80211_AMPDU_RX_STOP:
+                /* Handled by hardware */
+                break;
+
+        default:
+                return -EOPNOTSUPP;
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_CARL9170_WPC
+static int carl9170_register_wps_button(struct ar9170 *ar)
+{
+        struct input_dev *input;
+        int err;
+
+        if (!(ar->features & CARL9170_WPS_BUTTON))
+                return 0;
+
+        input = input_allocate_device();
+        if (!input)
+                return -ENOMEM;
+
+        snprintf(ar->wps.name, sizeof(ar->wps.name), "%s WPS Button",
+                 wiphy_name(ar->hw->wiphy));
+
+        snprintf(ar->wps.phys, sizeof(ar->wps.phys),
+                 "ieee80211/%s/input0", wiphy_name(ar->hw->wiphy));
+
+        input->name = ar->wps.name;
+        input->phys = ar->wps.phys;
+        input->id.bustype = BUS_USB;
+        input->dev.parent = &ar->hw->wiphy->dev;
+
+        input_set_capability(input, EV_KEY, KEY_WPS_BUTTON);
+
+        err = input_register_device(input);
+        if (err) {
+                input_free_device(input);
+                return err;
+        }
+
+        ar->wps.pbc = input;
+        return 0;
+}
+#endif /* CONFIG_CARL9170_WPC */
+
+static int carl9170_op_get_survey(struct ieee80211_hw *hw, int idx,
+                                struct survey_info *survey)
+{
+        struct ar9170 *ar = hw->priv;
+        int err;
+
+        if (idx != 0)
+                return -ENOENT;
+
+        mutex_lock(&ar->mutex);
+        err = carl9170_get_noisefloor(ar);
+        mutex_unlock(&ar->mutex);
+        if (err)
+                return err;
+
+        survey->channel = ar->channel;
+        survey->filled = SURVEY_INFO_NOISE_DBM;
+        survey->noise = ar->noise[0];
+        return 0;
+}
+
+static void carl9170_op_flush(struct ieee80211_hw *hw, bool drop)
+{
+        struct ar9170 *ar = hw->priv;
+        unsigned int vid;
+
+        mutex_lock(&ar->mutex);
+        for_each_set_bit(vid, &ar->vif_bitmap, ar->fw.vif_num)
+                carl9170_flush_cab(ar, vid);
+
+        carl9170_flush(ar, drop);
+        mutex_unlock(&ar->mutex);
+}
+
+static int carl9170_op_get_stats(struct ieee80211_hw *hw,
+                                 struct ieee80211_low_level_stats *stats)
+{
+        struct ar9170 *ar = hw->priv;
+
+        memset(stats, 0, sizeof(*stats));
+        stats->dot11ACKFailureCount = ar->tx_ack_failures;
+        stats->dot11FCSErrorCount = ar->tx_fcs_errors;
+        return 0;
+}
+
+static void carl9170_op_sta_notify(struct ieee80211_hw *hw,
+                                   struct ieee80211_vif *vif,
+                                   enum sta_notify_cmd cmd,
+                                   struct ieee80211_sta *sta)
+{
+        struct carl9170_sta_info *sta_info = (void *) sta->drv_priv;
+
+        switch (cmd) {
+        case STA_NOTIFY_SLEEP:
+                sta_info->sleeping = true;
+                if (atomic_read(&sta_info->pending_frames))
+                        ieee80211_sta_block_awake(hw, sta, true);
+                break;
+
+        case STA_NOTIFY_AWAKE:
+                sta_info->sleeping = false;
+                break;
+        }
+}
+
+static const struct ieee80211_ops carl9170_ops = {
+        .start                  = carl9170_op_start,
+        .stop                   = carl9170_op_stop,
+        .tx                     = carl9170_op_tx,
+        .flush                  = carl9170_op_flush,
+        .add_interface          = carl9170_op_add_interface,
+        .remove_interface       = carl9170_op_remove_interface,
+        .config                 = carl9170_op_config,
+        .prepare_multicast      = carl9170_op_prepare_multicast,
+        .configure_filter       = carl9170_op_configure_filter,
+        .conf_tx                = carl9170_op_conf_tx,
+        .bss_info_changed       = carl9170_op_bss_info_changed,
+        .get_tsf                = carl9170_op_get_tsf,
+        .set_key                = carl9170_op_set_key,
+        .sta_add                = carl9170_op_sta_add,
+        .sta_remove             = carl9170_op_sta_remove,
+        .sta_notify             = carl9170_op_sta_notify,
+        .get_survey             = carl9170_op_get_survey,
+        .get_stats              = carl9170_op_get_stats,
+        .ampdu_action           = carl9170_op_ampdu_action,
+};
+
+void *carl9170_alloc(size_t priv_size)
+{
+        struct ieee80211_hw *hw;
+        struct ar9170 *ar;
+        struct sk_buff *skb;
+        int i;
+
+        /*
+         * this buffer is used for rx stream reconstruction.
+         * Under heavy load this device (or the transport layer?)
+         * tends to split the streams into separate rx descriptors.
+         */
+
+        skb = __dev_alloc_skb(AR9170_RX_STREAM_MAX_SIZE, GFP_KERNEL);
+        if (!skb)
+                goto err_nomem;
+
+        hw = ieee80211_alloc_hw(priv_size, &carl9170_ops);
+        if (!hw)
+                goto err_nomem;
+
+        ar = hw->priv;
+        ar->hw = hw;
+        ar->rx_failover = skb;
+
+        memset(&ar->rx_plcp, 0, sizeof(struct ar9170_rx_head));
+        ar->rx_has_plcp = false;
+
+        /*
+         * Here's a hidden pitfall!
+         *
+         * All 4 AC queues work perfectly well under _legacy_ operation.
+         * However as soon as aggregation is enabled, the traffic flow
+         * gets very bumpy. Therefore we have to _switch_ to a
+         * software AC with a single HW queue.
+         */
+        hw->queues = __AR9170_NUM_TXQ;
+
+        mutex_init(&ar->mutex);
+        spin_lock_init(&ar->beacon_lock);
+        spin_lock_init(&ar->cmd_lock);
+        spin_lock_init(&ar->tx_stats_lock);
+        spin_lock_init(&ar->tx_ampdu_list_lock);
+        spin_lock_init(&ar->mem_lock);
+        spin_lock_init(&ar->state_lock);
+        atomic_set(&ar->pending_restarts, 0);
+        ar->vifs = 0;
+        for (i = 0; i < ar->hw->queues; i++) {
+                skb_queue_head_init(&ar->tx_status[i]);
+                skb_queue_head_init(&ar->tx_pending[i]);
+        }
+        INIT_WORK(&ar->ps_work, carl9170_ps_work);
+        INIT_WORK(&ar->ping_work, carl9170_ping_work);
+        INIT_WORK(&ar->restart_work, carl9170_restart_work);
+        INIT_WORK(&ar->ampdu_work, carl9170_ampdu_work);
+        INIT_DELAYED_WORK(&ar->tx_janitor, carl9170_tx_janitor);
+        INIT_LIST_HEAD(&ar->tx_ampdu_list);
+        rcu_assign_pointer(ar->tx_ampdu_iter,
+                           (struct carl9170_sta_tid *) &ar->tx_ampdu_list);
+
+        bitmap_zero(&ar->vif_bitmap, ar->fw.vif_num);
+        INIT_LIST_HEAD(&ar->vif_list);
+        init_completion(&ar->tx_flush);
+
+        /* firmware decides which modes we support */
+        hw->wiphy->interface_modes = 0;
+
+        hw->flags |= IEEE80211_HW_RX_INCLUDES_FCS |
+                     IEEE80211_HW_REPORTS_TX_ACK_STATUS |
+                     IEEE80211_HW_SUPPORTS_PS |
+                     IEEE80211_HW_PS_NULLFUNC_STACK |
+                     IEEE80211_HW_SIGNAL_DBM;
+
+        if (!modparam_noht) {
+                /*
+                 * see the comment above, why we allow the user
+                 * to disable HT by a module parameter.
+                 */
+                hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
+        }
+
+        hw->extra_tx_headroom = sizeof(struct _carl9170_tx_superframe);
+        hw->sta_data_size = sizeof(struct carl9170_sta_info);
+        hw->vif_data_size = sizeof(struct carl9170_vif_info);
+
+        hw->max_rates = CARL9170_TX_MAX_RATES;
+        hw->max_rate_tries = CARL9170_TX_USER_RATE_TRIES;
+
+        for (i = 0; i < ARRAY_SIZE(ar->noise); i++)
+                ar->noise[i] = -95; /* ATH_DEFAULT_NOISE_FLOOR */
+
+        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        return ar;
+
+err_nomem:
+        kfree_skb(skb);
+        return ERR_PTR(-ENOMEM);
+}
+
+static int carl9170_read_eeprom(struct ar9170 *ar)
+{
+#define RW      8       /* number of words to read at once */
+#define RB      (sizeof(u32) * RW)
+        u8 *eeprom = (void *)&ar->eeprom;
+        __le32 offsets[RW];
+        int i, j, err;
+
+        BUILD_BUG_ON(sizeof(ar->eeprom) & 3);
+
+        BUILD_BUG_ON(RB > CARL9170_MAX_CMD_LEN - 4);
+#ifndef __CHECKER__
+        /* don't want to handle trailing remains */
+        BUILD_BUG_ON(sizeof(ar->eeprom) % RB);
+#endif
+
+        for (i = 0; i < sizeof(ar->eeprom)/RB; i++) {
+                for (j = 0; j < RW; j++)
+                        offsets[j] = cpu_to_le32(AR9170_EEPROM_START +
+                                                 RB * i + 4 * j);
+
+                err = carl9170_exec_cmd(ar, CARL9170_CMD_RREG,
+                                        RB, (u8 *) &offsets,
+                                        RB, eeprom + RB * i);
+                if (err)
+                        return err;
+        }
+
+#undef RW
+#undef RB
+        return 0;
+}
+
+static int carl9170_parse_eeprom(struct ar9170 *ar)
+{
+        struct ath_regulatory *regulatory = &ar->common.regulatory;
+        unsigned int rx_streams, tx_streams, tx_params = 0;
+        int bands = 0;
+
+        if (ar->eeprom.length == cpu_to_le16(0xffff))
+                return -ENODATA;
+
+        rx_streams = hweight8(ar->eeprom.rx_mask);
+        tx_streams = hweight8(ar->eeprom.tx_mask);
+
+        if (rx_streams != tx_streams) {
+                tx_params = IEEE80211_HT_MCS_TX_RX_DIFF;
+
+                WARN_ON(!(tx_streams >= 1 && tx_streams <=
+                        IEEE80211_HT_MCS_TX_MAX_STREAMS));
+
+                tx_params = (tx_streams - 1) <<
+                            IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
+
+                carl9170_band_2GHz.ht_cap.mcs.tx_params |= tx_params;
+                carl9170_band_5GHz.ht_cap.mcs.tx_params |= tx_params;
+        }
+
+        if (ar->eeprom.operating_flags & AR9170_OPFLAG_2GHZ) {
+                ar->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
+                        &carl9170_band_2GHz;
+                bands++;
+        }
+        if (ar->eeprom.operating_flags & AR9170_OPFLAG_5GHZ) {
+                ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
+                        &carl9170_band_5GHz;
+                bands++;
+        }
+
+        /*
+         * I measured this, a bandswitch takes roughly
+         * 135 ms and a frequency switch about 80.
+         *
+         * FIXME: measure these values again once EEPROM settings
+         *        are used, that will influence them!
+         */
+        if (bands == 2)
+                ar->hw->channel_change_time = 135 * 1000;
+        else
+                ar->hw->channel_change_time = 80 * 1000;
+
+        regulatory->current_rd = le16_to_cpu(ar->eeprom.reg_domain[0]);
+        regulatory->current_rd_ext = le16_to_cpu(ar->eeprom.reg_domain[1]);
+
+        /* second part of wiphy init */
+        SET_IEEE80211_PERM_ADDR(ar->hw, ar->eeprom.mac_address);
+
+        return bands ? 0 : -EINVAL;
+}
+
+static int carl9170_reg_notifier(struct wiphy *wiphy,
+                                 struct regulatory_request *request)
+{
+        struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
+        struct ar9170 *ar = hw->priv;
+
+        return ath_reg_notifier_apply(wiphy, request, &ar->common.regulatory);
+}
+
+int carl9170_register(struct ar9170 *ar)
+{
+        struct ath_regulatory *regulatory = &ar->common.regulatory;
+        int err = 0, i;
+
+        if (WARN_ON(ar->mem_bitmap))
+                return -EINVAL;
+
+        ar->mem_bitmap = kzalloc(roundup(ar->fw.mem_blocks, BITS_PER_LONG) *
+                                 sizeof(unsigned long), GFP_KERNEL);
+
+        if (!ar->mem_bitmap)
+                return -ENOMEM;
+
+        /* try to read EEPROM, init MAC addr */
+        err = carl9170_read_eeprom(ar);
+        if (err)
+                return err;
+
+        err = carl9170_fw_fix_eeprom(ar);
+        if (err)
+                return err;
+
+        err = carl9170_parse_eeprom(ar);
+        if (err)
+                return err;
+
+        err = ath_regd_init(regulatory, ar->hw->wiphy,
+                            carl9170_reg_notifier);
+        if (err)
+                return err;
+
+        if (modparam_noht) {
+                carl9170_band_2GHz.ht_cap.ht_supported = false;
+                carl9170_band_5GHz.ht_cap.ht_supported = false;
+        }
+
+        for (i = 0; i < ar->fw.vif_num; i++) {
+                ar->vif_priv[i].id = i;
+                ar->vif_priv[i].vif = NULL;
+        }
+
+        err = ieee80211_register_hw(ar->hw);
+        if (err)
+                return err;
+
+        /* mac80211 interface is now registered */
+        ar->registered = true;
+
+        if (!ath_is_world_regd(regulatory))
+                regulatory_hint(ar->hw->wiphy, regulatory->alpha2);
+
+#ifdef CONFIG_CARL9170_DEBUGFS
+        carl9170_debugfs_register(ar);
+#endif /* CONFIG_CARL9170_DEBUGFS */
+
+        err = carl9170_led_init(ar);
+        if (err)
+                goto err_unreg;
+
+#ifdef CONFIG_CARL9170_LEDS
+        err = carl9170_led_register(ar);
+        if (err)
+                goto err_unreg;
+#endif /* CONFIG_CARL9170_LEDS */
+
+#ifdef CONFIG_CARL9170_WPC
+        err = carl9170_register_wps_button(ar);
+        if (err)
+                goto err_unreg;
+#endif /* CONFIG_CARL9170_WPC */
+
+        dev_info(&ar->udev->dev, "Atheros AR9170 is registered as '%s'\n",
+                 wiphy_name(ar->hw->wiphy));
+
+        return 0;
+
+err_unreg:
+        carl9170_unregister(ar);
+        return err;
+}
+
+void carl9170_unregister(struct ar9170 *ar)
+{
+        if (!ar->registered)
+                return;
+
+        ar->registered = false;
+
+#ifdef CONFIG_CARL9170_LEDS
+        carl9170_led_unregister(ar);
+#endif /* CONFIG_CARL9170_LEDS */
+
+#ifdef CONFIG_CARL9170_DEBUGFS
+        carl9170_debugfs_unregister(ar);
+#endif /* CONFIG_CARL9170_DEBUGFS */
+
+#ifdef CONFIG_CARL9170_WPC
+        if (ar->wps.pbc) {
+                input_unregister_device(ar->wps.pbc);
+                ar->wps.pbc = NULL;
+        }
+#endif /* CONFIG_CARL9170_WPC */
+
+        carl9170_cancel_worker(ar);
+        cancel_work_sync(&ar->restart_work);
+
+        ieee80211_unregister_hw(ar->hw);
+}
+
+void carl9170_free(struct ar9170 *ar)
+{
+        WARN_ON(ar->registered);
+        WARN_ON(IS_INITIALIZED(ar));
+
+        kfree_skb(ar->rx_failover);
+        ar->rx_failover = NULL;
+
+        kfree(ar->mem_bitmap);
+        ar->mem_bitmap = NULL;
+
+        mutex_destroy(&ar->mutex);
+
+        ieee80211_free_hw(ar->hw);
+}
diff --git a/drivers/net/wireless/ath/ar9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c
index 0dbfcf79ac96..b6ae0e179c8d 100644
--- a/drivers/net/wireless/ath/ar9170/phy.c
+++ b/drivers/net/wireless/ath/carl9170/phy.c
@@ -1,5 +1,5 @@
 /*
- * Atheros AR9170 driver
+ * Atheros CARL9170 driver
  *
  * PHY and RF code
  *
@@ -37,33 +37,34 @@
  */
 
 #include <linux/bitrev.h>
-#include "ar9170.h"
+#include "carl9170.h"
 #include "cmd.h"
+#include "phy.h"
 
-static int ar9170_init_power_cal(struct ar9170 *ar)
+static int carl9170_init_power_cal(struct ar9170 *ar)
 {
-        ar9170_regwrite_begin(ar);
-
-        ar9170_regwrite(0x1bc000 + 0x993c, 0x7f);
-        ar9170_regwrite(0x1bc000 + 0x9934, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0x9938, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa234, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa238, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa38c, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa390, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa3cc, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa3d0, 0x3f3f3f3f);
-        ar9170_regwrite(0x1bc000 + 0xa3d4, 0x3f3f3f3f);
-
-        ar9170_regwrite_finish();
-        return ar9170_regwrite_result();
+        carl9170_regwrite_begin(ar);
+
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f);
+        carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f);
+
+        carl9170_regwrite_finish();
+        return carl9170_regwrite_result();
 }
 
-struct ar9170_phy_init {
+struct carl9170_phy_init {
         u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20;
 };
 
-static struct ar9170_phy_init ar5416_phy_init[] = {
+static struct carl9170_phy_init ar5416_phy_init[] = {
         { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
         { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, },
         { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
@@ -84,11 +85,12 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
         { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, },
         { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, },
         { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, },
-        { 0x1c5850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, },
+        { 0x1c5850, 0x6c48b4e4, 0x6d48b4e4, 0x6d48b0e4, 0x6c48b0e4, },
         { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, },
         { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, },
-        { 0x1c585c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, },
+        { 0x1c585c, 0x31395c5e, 0x3139605e, 0x3139605e, 0x31395c5e, },
         { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, },
+        { 0x1c5864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, },
         { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, },
         { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, },
         { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
@@ -130,9 +132,10 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
         { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, },
         { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, },
         { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, },
+        { 0x1c59bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, },
         { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, },
         { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, },
-        { 0x1c59c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, },
+        { 0x1c59c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, },
         { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, },
         { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, },
         { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
@@ -400,7 +403,7 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
  * look up a certain register in ar5416_phy_init[] and return the init. value
  * for the band and bandwidth given. Return 0 if register address not found.
  */
-static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
+static u32 carl9170_def_val(u32 reg, bool is_2ghz, bool is_40mhz)
 {
         unsigned int i;
         for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
@@ -424,116 +427,127 @@ static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
 
 /*
  * initialize some phy regs from eeprom values in modal_header[]
- * acc. to band and bandwith
+ * acc. to band and bandwidth
  */
-static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
+static int carl9170_init_phy_from_eeprom(struct ar9170 *ar,
                                 bool is_2ghz, bool is_40mhz)
 {
         static const u8 xpd2pd[16] = {
                 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
-                0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
+                0x2, 0x3, 0x7, 0x2, 0xb, 0x2, 0x2, 0x2
         };
-        u32 defval, newval;
         /* pointer to the modal_header acc. to band */
         struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
+        u32 val;
 
-        ar9170_regwrite_begin(ar);
+        carl9170_regwrite_begin(ar);
 
         /* ant common control (index 0) */
-        newval = le32_to_cpu(m->antCtrlCommon);
-        ar9170_regwrite(0x1c5964, newval);
+        carl9170_regwrite(AR9170_PHY_REG_SWITCH_COM,
+                le32_to_cpu(m->antCtrlCommon));
 
         /* ant control chain 0 (index 1) */
-        newval = le32_to_cpu(m->antCtrlChain[0]);
-        ar9170_regwrite(0x1c5960, newval);
+        carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_0,
+                le32_to_cpu(m->antCtrlChain[0]));
 
         /* ant control chain 2 (index 2) */
-        newval = le32_to_cpu(m->antCtrlChain[1]);
-        ar9170_regwrite(0x1c7960, newval);
+        carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_2,
+                le32_to_cpu(m->antCtrlChain[1]));
 
         /* SwSettle (index 3) */
         if (!is_40mhz) {
-                defval = ar9170_get_default_phy_reg_val(0x1c5844,
-                                                        is_2ghz, is_40mhz);
-                newval = (defval & ~0x3f80) |
-                        ((m->switchSettling & 0x7f) << 7);
-                ar9170_regwrite(0x1c5844, newval);
+                val = carl9170_def_val(AR9170_PHY_REG_SETTLING,
+                                     is_2ghz, is_40mhz);
+                SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling);
+                carl9170_regwrite(AR9170_PHY_REG_SETTLING, val);
         }
 
         /* adcDesired, pdaDesired (index 4) */
-        defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
-        newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
-                ((u8)m->adcDesiredSize);
-        ar9170_regwrite(0x1c5850, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_DESIRED_SZ, is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize);
+        SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize);
+        carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val);
 
         /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
-        defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
-        newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
-                (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
-        ar9170_regwrite(0x1c5834, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_RF_CTL4, is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff);
+        SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff);
+        SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn);
+        SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn);
+        carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val);
 
         /* TxEndToRxOn (index 6) */
-        defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
-        newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
-        ar9170_regwrite(0x1c5828, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_RF_CTL3, is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn);
+        carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val);
 
         /* thresh62 (index 7) */
-        defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
-        newval = (defval & ~0x7f000) | (m->thresh62 << 12);
-        ar9170_regwrite(0x1c8864, newval);
+        val = carl9170_def_val(0x1c8864, is_2ghz, is_40mhz);
+        val = (val & ~0x7f000) | (m->thresh62 << 12);
+        carl9170_regwrite(0x1c8864, val);
 
         /* tx/rx attenuation chain 0 (index 8) */
-        defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
-        newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
-        ar9170_regwrite(0x1c5848, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_RXGAIN, is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]);
+        carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val);
 
         /* tx/rx attenuation chain 2 (index 9) */
-        defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
-        newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
-        ar9170_regwrite(0x1c7848, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_RXGAIN_CHAIN_2,
+                               is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]);
+        carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val);
 
         /* tx/rx margin chain 0 (index 10) */
-        defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
-        newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
+        val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ, is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[0]);
         /* bsw margin chain 0 for 5GHz only */
         if (!is_2ghz)
-                newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
-        ar9170_regwrite(0x1c620c, newval);
+                SET_VAL(AR9170_PHY_GAIN_2GHZ_BSW_MARGIN, val, m->bswMargin[0]);
+        carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val);
 
         /* tx/rx margin chain 2 (index 11) */
-        defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
-        newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
-        ar9170_regwrite(0x1c820c, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2,
+                               is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[1]);
+        carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val);
 
         /* iqCall, iqCallq chain 0 (index 12) */
-        defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
-        newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
-                ((u8)m->iqCalQCh[0] & 0x1f);
-        ar9170_regwrite(0x1c5920, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(0),
+                               is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[0]);
+        SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[0]);
+        carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val);
 
         /* iqCall, iqCallq chain 2 (index 13) */
-        defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
-        newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
-                ((u8)m->iqCalQCh[1] & 0x1f);
-        ar9170_regwrite(0x1c7920, newval);
+        val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(2),
+                               is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[1]);
+        SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[1]);
+        carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val);
 
         /* xpd gain mask (index 14) */
-        defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
-        newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
-        ar9170_regwrite(0x1c6258, newval);
-        ar9170_regwrite_finish();
-
-        return ar9170_regwrite_result();
+        val = carl9170_def_val(AR9170_PHY_REG_TPCRG1, is_2ghz, is_40mhz);
+        SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_1, val,
+                xpd2pd[m->xpdGain & 0xf] & 3);
+        SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_2, val,
+                xpd2pd[m->xpdGain & 0xf] >> 2);
+        carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val);
+
+        carl9170_regwrite(AR9170_PHY_REG_RX_CHAINMASK, ar->eeprom.rx_mask);
+        carl9170_regwrite(AR9170_PHY_REG_CAL_CHAINMASK, ar->eeprom.rx_mask);
+
+        carl9170_regwrite_finish();
+        return carl9170_regwrite_result();
 }
 
-int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
+static int carl9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
 {
         int i, err;
         u32 val;
         bool is_2ghz = band == IEEE80211_BAND_2GHZ;
         bool is_40mhz = conf_is_ht40(&ar->hw->conf);
 
-        ar9170_regwrite_begin(ar);
+        carl9170_regwrite_begin(ar);
 
         for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
                 if (is_40mhz) {
@@ -548,215 +562,155 @@ int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
                                 val = ar5416_phy_init[i]._5ghz_20;
                 }
 
-                ar9170_regwrite(ar5416_phy_init[i].reg, val);
+                carl9170_regwrite(ar5416_phy_init[i].reg, val);
         }
 
-        ar9170_regwrite_finish();
-        err = ar9170_regwrite_result();
+        carl9170_regwrite_finish();
+        err = carl9170_regwrite_result();
         if (err)
                 return err;
 
-        err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
+        err = carl9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
         if (err)
                 return err;
 
-        err = ar9170_init_power_cal(ar);
+        err = carl9170_init_power_cal(ar);
         if (err)
                 return err;
 
         /* XXX: remove magic! */
         if (is_2ghz)
-                err = ar9170_write_reg(ar, 0x1d4014, 0x5163);
+                err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5163);
         else
-                err = ar9170_write_reg(ar, 0x1d4014, 0x5143);
+                err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5143);
 
         return err;
 }
 
-struct ar9170_rf_init {
+struct carl9170_rf_initvals {
         u32 reg, _5ghz, _2ghz;
 };
 
-static struct ar9170_rf_init ar9170_rf_init[] = {
-     /* bank 0 */
-     { 0x1c58b0,  0x1e5795e5,  0x1e5795e5},
-     { 0x1c58e0,  0x02008020,  0x02008020},
-     /* bank 1 */
-     { 0x1c58b0,  0x02108421,  0x02108421},
-     { 0x1c58ec,  0x00000008,  0x00000008},
-     /* bank 2 */
-     { 0x1c58b0,  0x0e73ff17,  0x0e73ff17},
-     { 0x1c58e0,  0x00000420,  0x00000420},
-     /* bank 3 */
-     { 0x1c58f0,  0x01400018,  0x01c00018},
-     /* bank 4 */
-     { 0x1c58b0,  0x000001a1,  0x000001a1},
-     { 0x1c58e8,  0x00000001,  0x00000001},
-     /* bank 5 */
-     { 0x1c58b0,  0x00000013,  0x00000013},
-     { 0x1c58e4,  0x00000002,  0x00000002},
-     /* bank 6 */
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00004000,  0x00004000},
-     { 0x1c58b0,  0x00006c00,  0x00006c00},
-     { 0x1c58b0,  0x00002c00,  0x00002c00},
-     { 0x1c58b0,  0x00004800,  0x00004800},
-     { 0x1c58b0,  0x00004000,  0x00004000},
-     { 0x1c58b0,  0x00006000,  0x00006000},
-     { 0x1c58b0,  0x00001000,  0x00001000},
-     { 0x1c58b0,  0x00004000,  0x00004000},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00087c00,  0x00087c00},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00005400,  0x00005400},
-     { 0x1c58b0,  0x00000c00,  0x00000c00},
-     { 0x1c58b0,  0x00001800,  0x00001800},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00006c00,  0x00006c00},
-     { 0x1c58b0,  0x00006c00,  0x00006c00},
-     { 0x1c58b0,  0x00007c00,  0x00007c00},
-     { 0x1c58b0,  0x00002c00,  0x00002c00},
-     { 0x1c58b0,  0x00003c00,  0x00003c00},
-     { 0x1c58b0,  0x00003800,  0x00003800},
-     { 0x1c58b0,  0x00001c00,  0x00001c00},
-     { 0x1c58b0,  0x00000800,  0x00000800},
-     { 0x1c58b0,  0x00000408,  0x00000408},
-     { 0x1c58b0,  0x00004c15,  0x00004c15},
-     { 0x1c58b0,  0x00004188,  0x00004188},
-     { 0x1c58b0,  0x0000201e,  0x0000201e},
-     { 0x1c58b0,  0x00010408,  0x00010408},
-     { 0x1c58b0,  0x00000801,  0x00000801},
-     { 0x1c58b0,  0x00000c08,  0x00000c08},
-     { 0x1c58b0,  0x0000181e,  0x0000181e},
-     { 0x1c58b0,  0x00001016,  0x00001016},
-     { 0x1c58b0,  0x00002800,  0x00002800},
-     { 0x1c58b0,  0x00004010,  0x00004010},
-     { 0x1c58b0,  0x0000081c,  0x0000081c},
-     { 0x1c58b0,  0x00000115,  0x00000115},
-     { 0x1c58b0,  0x00000015,  0x00000015},
-     { 0x1c58b0,  0x00000066,  0x00000066},
-     { 0x1c58b0,  0x0000001c,  0x0000001c},
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00000004,  0x00000004},
-     { 0x1c58b0,  0x00000015,  0x00000015},
-     { 0x1c58b0,  0x0000001f,  0x0000001f},
-     { 0x1c58e0,  0x00000000,  0x00000400},
-     /* bank 7 */
-     { 0x1c58b0,  0x000000a0,  0x000000a0},
-     { 0x1c58b0,  0x00000000,  0x00000000},
-     { 0x1c58b0,  0x00000040,  0x00000040},
-     { 0x1c58f0,  0x0000001c,  0x0000001c},
+static struct carl9170_rf_initvals carl9170_rf_initval[] = {
+        /* bank 0 */
+        { 0x1c58b0, 0x1e5795e5, 0x1e5795e5},
+        { 0x1c58e0, 0x02008020, 0x02008020},
+        /* bank 1 */
+        { 0x1c58b0, 0x02108421, 0x02108421},
+        { 0x1c58ec, 0x00000008, 0x00000008},
+        /* bank 2 */
+        { 0x1c58b0, 0x0e73ff17, 0x0e73ff17},
+        { 0x1c58e0, 0x00000420, 0x00000420},
+        /* bank 3 */
+        { 0x1c58f0, 0x01400018, 0x01c00018},
+        /* bank 4 */
+        { 0x1c58b0, 0x000001a1, 0x000001a1},
+        { 0x1c58e8, 0x00000001, 0x00000001},
+        /* bank 5 */
+        { 0x1c58b0, 0x00000013, 0x00000013},
+        { 0x1c58e4, 0x00000002, 0x00000002},
+        /* bank 6 */
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00004000, 0x00004000},
+        { 0x1c58b0, 0x00006c00, 0x00006c00},
+        { 0x1c58b0, 0x00002c00, 0x00002c00},
+        { 0x1c58b0, 0x00004800, 0x00004800},
+        { 0x1c58b0, 0x00004000, 0x00004000},
+        { 0x1c58b0, 0x00006000, 0x00006000},
+        { 0x1c58b0, 0x00001000, 0x00001000},
+        { 0x1c58b0, 0x00004000, 0x00004000},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00087c00, 0x00087c00},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00005400, 0x00005400},
+        { 0x1c58b0, 0x00000c00, 0x00000c00},
+        { 0x1c58b0, 0x00001800, 0x00001800},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00006c00, 0x00006c00},
+        { 0x1c58b0, 0x00006c00, 0x00006c00},
+        { 0x1c58b0, 0x00007c00, 0x00007c00},
+        { 0x1c58b0, 0x00002c00, 0x00002c00},
+        { 0x1c58b0, 0x00003c00, 0x00003c00},
+        { 0x1c58b0, 0x00003800, 0x00003800},
+        { 0x1c58b0, 0x00001c00, 0x00001c00},
+        { 0x1c58b0, 0x00000800, 0x00000800},
+        { 0x1c58b0, 0x00000408, 0x00000408},
+        { 0x1c58b0, 0x00004c15, 0x00004c15},
+        { 0x1c58b0, 0x00004188, 0x00004188},
+        { 0x1c58b0, 0x0000201e, 0x0000201e},
+        { 0x1c58b0, 0x00010408, 0x00010408},
+        { 0x1c58b0, 0x00000801, 0x00000801},
+        { 0x1c58b0, 0x00000c08, 0x00000c08},
+        { 0x1c58b0, 0x0000181e, 0x0000181e},
+        { 0x1c58b0, 0x00001016, 0x00001016},
+        { 0x1c58b0, 0x00002800, 0x00002800},
+        { 0x1c58b0, 0x00004010, 0x00004010},
+        { 0x1c58b0, 0x0000081c, 0x0000081c},
+        { 0x1c58b0, 0x00000115, 0x00000115},
+        { 0x1c58b0, 0x00000015, 0x00000015},
+        { 0x1c58b0, 0x00000066, 0x00000066},
+        { 0x1c58b0, 0x0000001c, 0x0000001c},
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00000004, 0x00000004},
+        { 0x1c58b0, 0x00000015, 0x00000015},
+        { 0x1c58b0, 0x0000001f, 0x0000001f},
+        { 0x1c58e0, 0x00000000, 0x00000400},
+        /* bank 7 */
+        { 0x1c58b0, 0x000000a0, 0x000000a0},
+        { 0x1c58b0, 0x00000000, 0x00000000},
+        { 0x1c58b0, 0x00000040, 0x00000040},
+        { 0x1c58f0, 0x0000001c, 0x0000001c},
 };
 
-static int ar9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
+static int carl9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
 {
         int err, i;
 
-        ar9170_regwrite_begin(ar);
+        carl9170_regwrite_begin(ar);
 
-        for (i = 0; i < ARRAY_SIZE(ar9170_rf_init); i++)
-                ar9170_regwrite(ar9170_rf_init[i].reg,
-                                band5ghz ? ar9170_rf_init[i]._5ghz
-                                         : ar9170_rf_init[i]._2ghz);
+        for (i = 0; i < ARRAY_SIZE(carl9170_rf_initval); i++)
+                carl9170_regwrite(carl9170_rf_initval[i].reg,
+                                  band5ghz ? carl9170_rf_initval[i]._5ghz
+                                           : carl9170_rf_initval[i]._2ghz);
 
-        ar9170_regwrite_finish();
-        err = ar9170_regwrite_result();
+        carl9170_regwrite_finish();
+        err = carl9170_regwrite_result();
         if (err)
                 wiphy_err(ar->hw->wiphy, "rf init failed\n");
-        return err;
-}
-
-static int ar9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
-                                    u32 freq, enum ar9170_bw bw)
-{
-        int err;
-        u32 d0, d1, td0, td1, fd0, fd1;
-        u8 chansel;
-        u8 refsel0 = 1, refsel1 = 0;
-        u8 lf_synth = 0;
-
-        switch (bw) {
-        case AR9170_BW_40_ABOVE:
-                freq += 10;
-                break;
-        case AR9170_BW_40_BELOW:
-                freq -= 10;
-                break;
-        case AR9170_BW_20:
-                break;
-        case __AR9170_NUM_BW:
-                BUG();
-        }
-
-        if (band5ghz) {
-                if (freq % 10) {
-                        chansel = (freq - 4800) / 5;
-                } else {
-                        chansel = ((freq - 4800) / 10) * 2;
-                        refsel0 = 0;
-                        refsel1 = 1;
-                }
-                chansel = byte_rev_table[chansel];
-        } else {
-                if (freq == 2484) {
-                        chansel = 10 + (freq - 2274) / 5;
-                        lf_synth = 1;
-                } else
-                        chansel = 16 + (freq - 2272) / 5;
-                chansel *= 4;
-                chansel = byte_rev_table[chansel];
-        }
-
-        d1 =    chansel;
-        d0 =    0x21 |
-                refsel0 << 3 |
-                refsel1 << 2 |
-                lf_synth << 1;
-        td0 =   d0 & 0x1f;
-        td1 =   d1 & 0x1f;
-        fd0 =   td1 << 5 | td0;
 
-        td0 =   (d0 >> 5) & 0x7;
-        td1 =   (d1 >> 5) & 0x7;
-        fd1 =   td1 << 5 | td0;
-
-        ar9170_regwrite_begin(ar);
-
-        ar9170_regwrite(0x1c58b0, fd0);
-        ar9170_regwrite(0x1c58e8, fd1);
-
-        ar9170_regwrite_finish();
-        err = ar9170_regwrite_result();
-        if (err)
-                return err;
-
-        msleep(10);
-
-        return 0;
+        return err;
 }
 
-struct ar9170_phy_freq_params {
+struct carl9170_phy_freq_params {
         u8 coeff_exp;
         u16 coeff_man;
         u8 coeff_exp_shgi;
         u16 coeff_man_shgi;
 };
 
-struct ar9170_phy_freq_entry {
+enum carl9170_bw {
+        CARL9170_BW_20,
+        CARL9170_BW_40_BELOW,
+        CARL9170_BW_40_ABOVE,
+
+        __CARL9170_NUM_BW,
+};
+
+struct carl9170_phy_freq_entry {
         u16 freq;
-        struct ar9170_phy_freq_params params[__AR9170_NUM_BW];
+        struct carl9170_phy_freq_params params[__CARL9170_NUM_BW];
 };
 
 /* NB: must be in sync with channel tables in main! */
-static const struct ar9170_phy_freq_entry ar9170_phy_freq_params[] = {
+static const struct carl9170_phy_freq_entry carl9170_phy_freq_params[] = {
 /*
  *      freq,
  *              20MHz,
@@ -1010,65 +964,96 @@ static const struct ar9170_phy_freq_entry ar9170_phy_freq_params[] = {
         } },
 };
 
-static const struct ar9170_phy_freq_params *
-ar9170_get_hw_dyn_params(struct ieee80211_channel *channel,
-                         enum ar9170_bw bw)
+static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
+                                      u32 freq, enum carl9170_bw bw)
 {
-        unsigned int chanidx = 0;
-        u16 freq = 2412;
+        int err;
+        u32 d0, d1, td0, td1, fd0, fd1;
+        u8 chansel;
+        u8 refsel0 = 1, refsel1 = 0;
+        u8 lf_synth = 0;
 
-        if (channel) {
-                chanidx = channel->hw_value;
-                freq = channel->center_freq;
+        switch (bw) {
+        case CARL9170_BW_40_ABOVE:
+                freq += 10;
+                break;
+        case CARL9170_BW_40_BELOW:
+                freq -= 10;
+                break;
+        case CARL9170_BW_20:
+                break;
+        default:
+                BUG();
+                return -ENOSYS;
         }
 
-        BUG_ON(chanidx >= ARRAY_SIZE(ar9170_phy_freq_params));
-
-        BUILD_BUG_ON(__AR9170_NUM_BW != 3);
+        if (band5ghz) {
+                if (freq % 10) {
+                        chansel = (freq - 4800) / 5;
+                } else {
+                        chansel = ((freq - 4800) / 10) * 2;
+                        refsel0 = 0;
+                        refsel1 = 1;
+                }
+                chansel = byte_rev_table[chansel];
+        } else {
+                if (freq == 2484) {
+                        chansel = 10 + (freq - 2274) / 5;
+                        lf_synth = 1;
+                } else
+                        chansel = 16 + (freq - 2272) / 5;
+                chansel *= 4;
+                chansel = byte_rev_table[chansel];
+        }
 
-        WARN_ON(ar9170_phy_freq_params[chanidx].freq != freq);
+        d1 =    chansel;
+        d0 =    0x21 |
+                refsel0 << 3 |
+                refsel1 << 2 |
+                lf_synth << 1;
+        td0 =   d0 & 0x1f;
+        td1 =   d1 & 0x1f;
+        fd0 =   td1 << 5 | td0;
 
-        return &ar9170_phy_freq_params[chanidx].params[bw];
-}
+        td0 =   (d0 >> 5) & 0x7;
+        td1 =   (d1 >> 5) & 0x7;
+        fd1 =   td1 << 5 | td0;
 
+        carl9170_regwrite_begin(ar);
 
-int ar9170_init_rf(struct ar9170 *ar)
-{
-        const struct ar9170_phy_freq_params *freqpar;
-        __le32 cmd[7];
-        int err;
+        carl9170_regwrite(0x1c58b0, fd0);
+        carl9170_regwrite(0x1c58e8, fd1);
 
-        err = ar9170_init_rf_banks_0_7(ar, false);
+        carl9170_regwrite_finish();
+        err = carl9170_regwrite_result();
         if (err)
                 return err;
 
-        err = ar9170_init_rf_bank4_pwr(ar, false, 2412, AR9170_BW_20);
-        if (err)
-                return err;
+        return 0;
+}
 
-        freqpar = ar9170_get_hw_dyn_params(NULL, AR9170_BW_20);
+static const struct carl9170_phy_freq_params *
+carl9170_get_hw_dyn_params(struct ieee80211_channel *channel,
+                           enum carl9170_bw bw)
+{
+        unsigned int chanidx = 0;
+        u16 freq = 2412;
 
-        cmd[0] = cpu_to_le32(2412 * 1000);
-        cmd[1] = cpu_to_le32(0);
-        cmd[2] = cpu_to_le32(1);
-        cmd[3] = cpu_to_le32(freqpar->coeff_exp);
-        cmd[4] = cpu_to_le32(freqpar->coeff_man);
-        cmd[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
-        cmd[6] = cpu_to_le32(freqpar->coeff_man_shgi);
+        if (channel) {
+                chanidx = channel->hw_value;
+                freq = channel->center_freq;
+        }
 
-        /* RF_INIT echoes the command back to us */
-        err = ar->exec_cmd(ar, AR9170_CMD_RF_INIT,
-                           sizeof(cmd), (u8 *)cmd,
-                           sizeof(cmd), (u8 *)cmd);
-        if (err)
-                return err;
+        BUG_ON(chanidx >= ARRAY_SIZE(carl9170_phy_freq_params));
+
+        BUILD_BUG_ON(__CARL9170_NUM_BW != 3);
 
-        msleep(1000);
+        WARN_ON(carl9170_phy_freq_params[chanidx].freq != freq);
 
-        return ar9170_echo_test(ar, 0xaabbccdd);
+        return &carl9170_phy_freq_params[chanidx].params[bw];
 }
 
-static int ar9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
+static int carl9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
 {
         int idx = nfreqs - 2;
 
@@ -1081,7 +1066,7 @@ static int ar9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
         return 0;
 }
 
-static s32 ar9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
+static s32 carl9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
 {
         /* nothing to interpolate, it's horizontal */
         if (y2 == y1)
@@ -1100,14 +1085,13 @@ static s32 ar9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
         return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1));
 }
 
-static u8 ar9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
+static u8 carl9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
 {
 #define SHIFT           8
         s32 y;
 
-        y = ar9170_interpolate_s32(x << SHIFT,
-                                   x1 << SHIFT, y1 << SHIFT,
-                                   x2 << SHIFT, y2 << SHIFT);
+        y = carl9170_interpolate_s32(x << SHIFT, x1 << SHIFT,
+                y1 << SHIFT, x2 << SHIFT, y2 << SHIFT);
 
         /*
          * XXX: unwrap this expression
@@ -1118,23 +1102,21 @@ static u8 ar9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
 #undef SHIFT
 }
 
-static u8 ar9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array)
+static u8 carl9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array)
 {
         int i;
 
-        for (i = 0; i < 3; i++)
+        for (i = 0; i < 3; i++) {
                 if (x <= x_array[i + 1])
                         break;
+        }
 
-        return ar9170_interpolate_u8(x,
-                                     x_array[i],
-                                     y_array[i],
-                                     x_array[i + 1],
-                                     y_array[i + 1]);
+        return carl9170_interpolate_u8(x, x_array[i], y_array[i],
+                x_array[i + 1], y_array[i + 1]);
 }
 
-static int ar9170_set_freq_cal_data(struct ar9170 *ar,
-                                    struct ieee80211_channel *channel)
+static int carl9170_set_freq_cal_data(struct ar9170 *ar,
+        struct ieee80211_channel *channel)
 {
         u8 *cal_freq_pier;
         u8 vpds[2][AR5416_PD_GAIN_ICEPTS];
@@ -1168,9 +1150,9 @@ static int ar9170_set_freq_cal_data(struct ar9170 *ar,
         if (i < 0)
                 return -EINVAL;
 
-        idx = ar9170_find_freq_idx(i, cal_freq_pier, f);
+        idx = carl9170_find_freq_idx(i, cal_freq_pier, f);
 
-        ar9170_regwrite_begin(ar);
+        carl9170_regwrite_begin(ar);
 
         for (chain = 0; chain < AR5416_MAX_CHAINS; chain++) {
                 for (i = 0; i < AR5416_PD_GAIN_ICEPTS; i++) {
@@ -1193,13 +1175,13 @@ static int ar9170_set_freq_cal_data(struct ar9170 *ar,
                         }
 
                         for (j = 0; j < 2; j++) {
-                                vpds[j][i] = ar9170_interpolate_u8(f,
+                                vpds[j][i] = carl9170_interpolate_u8(f,
                                         cal_freq_pier[idx],
                                         cal_pier_data->vpd_pdg[j][i],
                                         cal_freq_pier[idx + 1],
                                         cal_pier_data[1].vpd_pdg[j][i]);
 
-                                pwrs[j][i] = ar9170_interpolate_u8(f,
+                                pwrs[j][i] = carl9170_interpolate_u8(f,
                                         cal_freq_pier[idx],
                                         cal_pier_data->pwr_pdg[j][i],
                                         cal_freq_pier[idx + 1],
@@ -1209,34 +1191,33 @@ static int ar9170_set_freq_cal_data(struct ar9170 *ar,
 
                 for (i = 0; i < 76; i++) {
                         if (i < 25) {
-                                tmp = ar9170_interpolate_val(i, &pwrs[0][0],
-                                                             &vpds[0][0]);
+                                tmp = carl9170_interpolate_val(i, &pwrs[0][0],
+                                                               &vpds[0][0]);
                         } else {
-                                tmp = ar9170_interpolate_val(i - 12,
-                                                             &pwrs[1][0],
-                                                             &vpds[1][0]);
+                                tmp = carl9170_interpolate_val(i - 12,
+                                                               &pwrs[1][0],
+                                                               &vpds[1][0]);
                         }
 
                         phy_data |= tmp << ((i & 3) << 3);
                         if ((i & 3) == 3) {
-                                ar9170_regwrite(0x1c6280 + chain * 0x1000 +
-                                                (i & ~3), phy_data);
+                                carl9170_regwrite(0x1c6280 + chain * 0x1000 +
+                                                  (i & ~3), phy_data);
                                 phy_data = 0;
                         }
                 }
 
                 for (i = 19; i < 32; i++)
-                        ar9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
-                                        0x0);
+                        carl9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
+                                          0x0);
         }
 
-        ar9170_regwrite_finish();
-        return ar9170_regwrite_result();
+        carl9170_regwrite_finish();
+        return carl9170_regwrite_result();
 }
 
-static u8 ar9170_get_max_edge_power(struct ar9170 *ar,
-                                    struct ar9170_calctl_edges edges[],
-                                    u32 freq)
+static u8 carl9170_get_max_edge_power(struct ar9170 *ar,
+        u32 freq, struct ar9170_calctl_edges edges[])
 {
         int i;
         u8 rc = AR5416_MAX_RATE_POWER;
@@ -1277,9 +1258,8 @@ static u8 ar9170_get_max_edge_power(struct ar9170 *ar,
         return rc;
 }
 
-static u8 ar9170_get_heavy_clip(struct ar9170 *ar,
-                                struct ar9170_calctl_edges edges[],
-                                u32 freq, enum ar9170_bw bw)
+static u8 carl9170_get_heavy_clip(struct ar9170 *ar, u32 freq,
+        enum carl9170_bw bw, struct ar9170_calctl_edges edges[])
 {
         u8 f;
         int i;
@@ -1290,7 +1270,7 @@ static u8 ar9170_get_heavy_clip(struct ar9170 *ar,
         else
                 f = (freq - 4800) / 5;
 
-        if (bw == AR9170_BW_40_BELOW || bw == AR9170_BW_40_ABOVE)
+        if (bw == CARL9170_BW_40_BELOW || bw == CARL9170_BW_40_ABOVE)
                 rc |= 0xf0;
 
         for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
@@ -1310,7 +1290,7 @@ static u8 ar9170_get_heavy_clip(struct ar9170 *ar,
  * calculate the conformance test limits and the heavy clip parameter
  * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706)
  */
-static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
+static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw)
 {
         u8 ctl_grp; /* CTL group */
         u8 ctl_idx; /* CTL index */
@@ -1341,7 +1321,7 @@ static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
 
 #define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n])
 
-        ar->phy_heavy_clip = 0;
+        ar->heavy_clip = 0;
 
         /*
          * TODO: investigate the differences between OTUS'
@@ -1378,31 +1358,32 @@ static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
                 if (ctl_idx < AR5416_NUM_CTLS) {
                         int f_off = 0;
 
-                        /* determine heav clip parameter from
-                           the 11G edges array */
+                        /*
+                         * determine heavy clip parameter
+                         * from the 11G edges array
+                         */
                         if (modes[i].ctl_mode == CTL_11G) {
-                                ar->phy_heavy_clip =
-                                        ar9170_get_heavy_clip(ar,
-                                                              EDGES(ctl_idx, 1),
-                                                              freq, bw);
+                                ar->heavy_clip =
+                                        carl9170_get_heavy_clip(ar,
+                                                freq, bw, EDGES(ctl_idx, 1));
                         }
 
                         /* adjust freq for 40MHz */
                         if (modes[i].ctl_mode == CTL_2GHT40 ||
                             modes[i].ctl_mode == CTL_5GHT40) {
-                                if (bw == AR9170_BW_40_BELOW)
+                                if (bw == CARL9170_BW_40_BELOW)
                                         f_off = -10;
                                 else
                                         f_off = 10;
                         }
 
                         modes[i].max_power =
-                                ar9170_get_max_edge_power(ar, EDGES(ctl_idx, 1),
-                                                          freq+f_off);
+                                carl9170_get_max_edge_power(ar,
+                                        freq+f_off, EDGES(ctl_idx, 1));
 
                         /*
                          * TODO: check if the regulatory max. power is
-                         *  controlled by cfg80211 for DFS
+                         * controlled by cfg80211 for DFS.
                          * (hpmain applies it to max_power itself for DFS freq)
                          */
 
@@ -1410,9 +1391,8 @@ static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
                         /*
                          * Workaround in otus driver, hpmain.c, line 3906:
                          * if no data for 5GHT20 are found, take the
-                         * legacy 5G value.
-                         * We extend this here to fallback from any other *HT or
-                         * 11G, too.
+                         * legacy 5G value. We extend this here to fallback
+                         * from any other HT* or 11G, too.
                          */
                         int k = i;
 
@@ -1433,22 +1413,22 @@ static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
                 }
         }
 
-        if (ar->phy_heavy_clip & 0xf0) {
+        if (ar->heavy_clip & 0xf0) {
                 ar->power_2G_ht40[0]--;
                 ar->power_2G_ht40[1]--;
                 ar->power_2G_ht40[2]--;
         }
-        if (ar->phy_heavy_clip & 0xf) {
+        if (ar->heavy_clip & 0xf) {
                 ar->power_2G_ht20[0]++;
                 ar->power_2G_ht20[1]++;
                 ar->power_2G_ht20[2]++;
         }
 
-
 #undef EDGES
 }
 
-static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
+static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
+                                  enum carl9170_bw bw)
 {
         struct ar9170_calibration_target_power_legacy *ctpl;
         struct ar9170_calibration_target_power_ht *ctph;
@@ -1495,19 +1475,14 @@ static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
                         pwr_freqs[n] = ctpl[n].freq;
                 }
                 ntargets = n;
-                idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
+                idx = carl9170_find_freq_idx(ntargets, pwr_freqs, f);
                 for (n = 0; n < 4; n++)
-                        ctpres[n] = ar9170_interpolate_u8(
-                                        f,
-                                        ctpl[idx + 0].freq,
-                                        ctpl[idx + 0].power[n],
-                                        ctpl[idx + 1].freq,
-                                        ctpl[idx + 1].power[n]);
+                        ctpres[n] = carl9170_interpolate_u8(f,
+                                ctpl[idx + 0].freq, ctpl[idx + 0].power[n],
+                                ctpl[idx + 1].freq, ctpl[idx + 1].power[n]);
         }
 
-        /*
-         * HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40
-         */
+        /* HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40 */
         for (i = 0; i < 4; i++) {
                 switch (i) {
                 case 0: /* 5 GHz HT 20 */
@@ -1540,22 +1515,18 @@ static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
                         pwr_freqs[n] = ctph[n].freq;
                 }
                 ntargets = n;
-                idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
+                idx = carl9170_find_freq_idx(ntargets, pwr_freqs, f);
                 for (n = 0; n < 8; n++)
-                        ctpres[n] = ar9170_interpolate_u8(
-                                        f,
-                                        ctph[idx + 0].freq,
-                                        ctph[idx + 0].power[n],
-                                        ctph[idx + 1].freq,
-                                        ctph[idx + 1].power[n]);
+                        ctpres[n] = carl9170_interpolate_u8(f,
+                                ctph[idx + 0].freq, ctph[idx + 0].power[n],
+                                ctph[idx + 1].freq, ctph[idx + 1].power[n]);
         }
 
-
         /* calc. conformance test limits and apply to ar->power*[] */
-        ar9170_calc_ctl(ar, freq, bw);
+        carl9170_calc_ctl(ar, freq, bw);
 
         /* set ACK/CTS TX power */
-        ar9170_regwrite_begin(ar);
+        carl9170_regwrite_begin(ar);
 
         if (ar->eeprom.tx_mask != 1)
                 ackchains = AR9170_TX_PHY_TXCHAIN_2;
@@ -1567,97 +1538,160 @@ static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
         else
                 ackpower = ar->power_5G_leg[0] & 0x3f;
 
-        ar9170_regwrite(0x1c3694, ackpower << 20 | ackchains << 26);
-        ar9170_regwrite(0x1c3bb4, ackpower << 5 | ackchains << 11 |
-                                  ackpower << 21 | ackchains << 27);
+        carl9170_regwrite(AR9170_MAC_REG_ACK_TPC,
+                          0x3c1e | ackpower << 20 | ackchains << 26);
+        carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC,
+                          ackpower << 5 | ackchains << 11 |
+                          ackpower << 21 | ackchains << 27);
 
-        ar9170_regwrite_finish();
-        return ar9170_regwrite_result();
-}
+        carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC,
+                          ackpower << 5 | ackchains << 11 |
+                          ackpower << 21 | ackchains << 27);
 
-static int ar9170_calc_noise_dbm(u32 raw_noise)
-{
-        if (raw_noise & 0x100)
-                return ~((raw_noise & 0x0ff) >> 1);
-        else
-                return (raw_noise & 0xff) >> 1;
+        carl9170_regwrite_finish();
+        return carl9170_regwrite_result();
 }
 
-int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
-                       enum ar9170_rf_init_mode rfi, enum ar9170_bw bw)
+int carl9170_get_noisefloor(struct ar9170 *ar)
 {
-        const struct ar9170_phy_freq_params *freqpar;
-        u32 cmd, tmp, offs;
-        __le32 vals[8];
-        int i, err;
-        bool bandswitch;
+        static const u32 phy_regs[] = {
+                AR9170_PHY_REG_CCA, AR9170_PHY_REG_CH2_CCA,
+                AR9170_PHY_REG_EXT_CCA, AR9170_PHY_REG_CH2_EXT_CCA };
+        u32 phy_res[ARRAY_SIZE(phy_regs)];
+        int err, i;
 
-        /* clear BB heavy clip enable */
-        err = ar9170_write_reg(ar, 0x1c59e0, 0x200);
+        BUILD_BUG_ON(ARRAY_SIZE(phy_regs) != ARRAY_SIZE(ar->noise));
+
+        err = carl9170_read_mreg(ar, ARRAY_SIZE(phy_regs), phy_regs, phy_res);
         if (err)
                 return err;
 
+        for (i = 0; i < 2; i++) {
+                ar->noise[i] = sign_extend32(GET_VAL(
+                        AR9170_PHY_CCA_MIN_PWR, phy_res[i]), 8);
+
+                ar->noise[i + 2] = sign_extend32(GET_VAL(
+                        AR9170_PHY_EXT_CCA_MIN_PWR, phy_res[i + 2]), 8);
+        }
+
+        return 0;
+}
+
+static enum carl9170_bw nl80211_to_carl(enum nl80211_channel_type type)
+{
+        switch (type) {
+        case NL80211_CHAN_NO_HT:
+        case NL80211_CHAN_HT20:
+                return CARL9170_BW_20;
+        case NL80211_CHAN_HT40MINUS:
+                return CARL9170_BW_40_BELOW;
+        case NL80211_CHAN_HT40PLUS:
+                return CARL9170_BW_40_ABOVE;
+        default:
+                BUG();
+        }
+}
+
+int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
+                         enum nl80211_channel_type _bw,
+                         enum carl9170_rf_init_mode rfi)
+{
+        const struct carl9170_phy_freq_params *freqpar;
+        struct carl9170_rf_init_result rf_res;
+        struct carl9170_rf_init rf;
+        u32 cmd, tmp, offs = 0, new_ht = 0;
+        int err;
+        enum carl9170_bw bw;
+        bool warm_reset;
+        struct ieee80211_channel *old_channel = NULL;
+
+        bw = nl80211_to_carl(_bw);
+
+        if (conf_is_ht(&ar->hw->conf))
+                new_ht |= CARL9170FW_PHY_HT_ENABLE;
+
+        if (conf_is_ht40(&ar->hw->conf))
+                new_ht |= CARL9170FW_PHY_HT_DYN2040;
+
         /* may be NULL at first setup */
-        if (ar->channel)
-                bandswitch = ar->channel->band != channel->band;
-        else
-                bandswitch = true;
+        if (ar->channel) {
+                old_channel = ar->channel;
+                warm_reset = (old_channel->band != channel->band) ||
+                             (old_channel->center_freq ==
+                              channel->center_freq) ||
+                             (ar->ht_settings != new_ht);
+
+                ar->channel = NULL;
+        } else {
+                warm_reset = true;
+        }
 
         /* HW workaround */
         if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] &&
             channel->center_freq <= 2417)
-                bandswitch = true;
-
-        err = ar->exec_cmd(ar, AR9170_CMD_FREQ_START, 0, NULL, 0, NULL);
-        if (err)
-                return err;
+                warm_reset = true;
 
-        if (rfi != AR9170_RFI_NONE || bandswitch) {
-                u32 val = 0x400;
+        if (rfi != CARL9170_RFI_NONE || warm_reset) {
+                u32 val;
 
-                if (rfi == AR9170_RFI_COLD)
-                        val = 0x800;
+                if (rfi == CARL9170_RFI_COLD)
+                        val = AR9170_PWR_RESET_BB_COLD_RESET;
+                else
+                        val = AR9170_PWR_RESET_BB_WARM_RESET;
 
                 /* warm/cold reset BB/ADDA */
-                err = ar9170_write_reg(ar, 0x1d4004, val);
+                err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, val);
                 if (err)
                         return err;
 
-                err = ar9170_write_reg(ar, 0x1d4004, 0x0);
+                err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, 0x0);
                 if (err)
                         return err;
 
-                err = ar9170_init_phy(ar, channel->band);
+                err = carl9170_init_phy(ar, channel->band);
                 if (err)
                         return err;
 
-                err = ar9170_init_rf_banks_0_7(ar,
+                err = carl9170_init_rf_banks_0_7(ar,
                         channel->band == IEEE80211_BAND_5GHZ);
                 if (err)
                         return err;
 
-                cmd = AR9170_CMD_RF_INIT;
+                cmd = CARL9170_CMD_RF_INIT;
         } else {
-                cmd = AR9170_CMD_FREQUENCY;
+                cmd = CARL9170_CMD_FREQUENCY;
         }
 
-        err = ar9170_init_rf_bank4_pwr(ar,
+        err = carl9170_exec_cmd(ar, CARL9170_CMD_FREQ_START, 0, NULL, 0, NULL);
+        if (err)
+                return err;
+
+        err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
+                                 0x200);
+        if (err)
+                return err;
+
+        err = carl9170_init_rf_bank4_pwr(ar,
                 channel->band == IEEE80211_BAND_5GHZ,
                 channel->center_freq, bw);
         if (err)
                 return err;
 
+        tmp = AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 |
+              AR9170_PHY_TURBO_FC_HT_EN;
+
         switch (bw) {
-        case AR9170_BW_20:
-                tmp = 0x240;
-                offs = 0;
+        case CARL9170_BW_20:
                 break;
-        case AR9170_BW_40_BELOW:
-                tmp = 0x2c4;
+        case CARL9170_BW_40_BELOW:
+                tmp |= AR9170_PHY_TURBO_FC_DYN2040_EN |
+                       AR9170_PHY_TURBO_FC_SHORT_GI_40;
                 offs = 3;
                 break;
-        case AR9170_BW_40_ABOVE:
-                tmp = 0x2d4;
+        case CARL9170_BW_40_ABOVE:
+                tmp |= AR9170_PHY_TURBO_FC_DYN2040_EN |
+                       AR9170_PHY_TURBO_FC_SHORT_GI_40 |
+                       AR9170_PHY_TURBO_FC_DYN2040_PRI_CH;
                 offs = 1;
                 break;
         default:
@@ -1666,54 +1700,96 @@ int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
         }
 
         if (ar->eeprom.tx_mask != 1)
-                tmp |= 0x100;
+                tmp |= AR9170_PHY_TURBO_FC_WALSH;
 
-        err = ar9170_write_reg(ar, 0x1c5804, tmp);
+        err = carl9170_write_reg(ar, AR9170_PHY_REG_TURBO, tmp);
         if (err)
                 return err;
 
-        err = ar9170_set_freq_cal_data(ar, channel);
+        err = carl9170_set_freq_cal_data(ar, channel);
         if (err)
                 return err;
 
-        err = ar9170_set_power_cal(ar, channel->center_freq, bw);
+        err = carl9170_set_power_cal(ar, channel->center_freq, bw);
         if (err)
                 return err;
 
-        freqpar = ar9170_get_hw_dyn_params(channel, bw);
+        freqpar = carl9170_get_hw_dyn_params(channel, bw);
+
+        rf.ht_settings = new_ht;
+        if (conf_is_ht40(&ar->hw->conf))
+                SET_VAL(CARL9170FW_PHY_HT_EXT_CHAN_OFF, rf.ht_settings, offs);
 
-        vals[0] = cpu_to_le32(channel->center_freq * 1000);
-        vals[1] = cpu_to_le32(conf_is_ht40(&ar->hw->conf));
-        vals[2] = cpu_to_le32(offs << 2 | 1);
-        vals[3] = cpu_to_le32(freqpar->coeff_exp);
-        vals[4] = cpu_to_le32(freqpar->coeff_man);
-        vals[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
-        vals[6] = cpu_to_le32(freqpar->coeff_man_shgi);
-        vals[7] = cpu_to_le32(1000);
+        rf.freq = cpu_to_le32(channel->center_freq * 1000);
+        rf.delta_slope_coeff_exp = cpu_to_le32(freqpar->coeff_exp);
+        rf.delta_slope_coeff_man = cpu_to_le32(freqpar->coeff_man);
+        rf.delta_slope_coeff_exp_shgi = cpu_to_le32(freqpar->coeff_exp_shgi);
+        rf.delta_slope_coeff_man_shgi = cpu_to_le32(freqpar->coeff_man_shgi);
 
-        err = ar->exec_cmd(ar, cmd, sizeof(vals), (u8 *)vals,
-                           sizeof(vals), (u8 *)vals);
+        if (rfi != CARL9170_RFI_NONE)
+                rf.finiteLoopCount = cpu_to_le32(2000);
+        else
+                rf.finiteLoopCount = cpu_to_le32(1000);
+
+        err = carl9170_exec_cmd(ar, cmd, sizeof(rf), &rf,
+                                sizeof(rf_res), &rf_res);
         if (err)
                 return err;
 
-        if (ar->phy_heavy_clip) {
-                err = ar9170_write_reg(ar, 0x1c59e0,
-                                       0x200 | ar->phy_heavy_clip);
-                if (err) {
-                        if (ar9170_nag_limiter(ar))
-                                wiphy_err(ar->hw->wiphy,
-                                          "failed to set heavy clip\n");
+        err = le32_to_cpu(rf_res.ret);
+        if (err != 0) {
+                ar->chan_fail++;
+                ar->total_chan_fail++;
+
+                wiphy_err(ar->hw->wiphy, "channel change: %d -> %d "
+                          "failed (%d).\n", old_channel ?
+                          old_channel->center_freq : -1, channel->center_freq,
+                          err);
+
+                if ((rfi == CARL9170_RFI_COLD) || (ar->chan_fail > 3)) {
+                        /*
+                         * We have tried very hard to change to _another_
+                         * channel and we've failed to do so!
+                         * Chances are that the PHY/RF is no longer
+                         * operable (due to corruptions/fatal events/bugs?)
+                         * and we need to reset at a higher level.
+                         */
+                        carl9170_restart(ar, CARL9170_RR_TOO_MANY_PHY_ERRORS);
+                        return 0;
                 }
+
+                err = carl9170_set_channel(ar, channel, _bw,
+                                           CARL9170_RFI_COLD);
+                if (err)
+                        return err;
+        } else {
+                ar->chan_fail = 0;
         }
 
-        for (i = 0; i < 2; i++) {
-                ar->noise[i] = ar9170_calc_noise_dbm(
-                                (le32_to_cpu(vals[2 + i]) >> 19) & 0x1ff);
+        err = carl9170_get_noisefloor(ar);
+        if (err)
+                return err;
+
+        if (ar->heavy_clip) {
+                err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
+                                         0x200 | ar->heavy_clip);
+                if (err) {
+                        if (net_ratelimit()) {
+                                wiphy_err(ar->hw->wiphy, "failed to set "
+                                       "heavy clip\n");
+                        }
 
-                ar->noise[i + 2] = ar9170_calc_noise_dbm(
-                                    (le32_to_cpu(vals[5 + i]) >> 23) & 0x1ff);
+                        return err;
+                }
         }
 
+        /* FIXME: PSM does not work in 5GHz Band */
+        if (channel->band == IEEE80211_BAND_5GHZ)
+                ar->ps.off_override |= PS_OFF_5GHZ;
+        else
+                ar->ps.off_override &= ~PS_OFF_5GHZ;
+
         ar->channel = channel;
+        ar->ht_settings = new_ht;
         return 0;
 }
diff --git a/drivers/net/wireless/ath/carl9170/phy.h b/drivers/net/wireless/ath/carl9170/phy.h
new file mode 100644
index 000000000000..024fb42bc787
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/phy.h
@@ -0,0 +1,564 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * PHY register map
+ *
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_PHY_H
+#define __CARL9170_SHARED_PHY_H
+
+#define AR9170_PHY_REG_BASE                     (0x1bc000 + 0x9800)
+#define AR9170_PHY_REG(_n)                      (AR9170_PHY_REG_BASE + \
+                                                 ((_n) << 2))
+
+#define AR9170_PHY_REG_TEST                     (AR9170_PHY_REG_BASE + 0x0000)
+#define         AR9170_PHY_TEST_AGC_CLR                 0x10000000
+#define         AR9170_PHY_TEST_RFSILENT_BB             0x00002000
+
+#define AR9170_PHY_REG_TURBO                    (AR9170_PHY_REG_BASE + 0x0004)
+#define         AR9170_PHY_TURBO_FC_TURBO_MODE          0x00000001
+#define         AR9170_PHY_TURBO_FC_TURBO_SHORT         0x00000002
+#define         AR9170_PHY_TURBO_FC_DYN2040_EN          0x00000004
+#define         AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY    0x00000008
+#define         AR9170_PHY_TURBO_FC_DYN2040_PRI_CH      0x00000010
+/* For 25 MHz channel spacing -- not used but supported by hw */
+#define         AR9170_PHY_TURBO_FC_DYN2040_EXT_CH      0x00000020
+#define         AR9170_PHY_TURBO_FC_HT_EN               0x00000040
+#define         AR9170_PHY_TURBO_FC_SHORT_GI_40         0x00000080
+#define         AR9170_PHY_TURBO_FC_WALSH               0x00000100
+#define         AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1      0x00000200
+#define         AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO     0x00000800
+
+#define AR9170_PHY_REG_TEST2                    (AR9170_PHY_REG_BASE + 0x0008)
+
+#define AR9170_PHY_REG_TIMING2                  (AR9170_PHY_REG_BASE + 0x0010)
+#define         AR9170_PHY_TIMING2_USE_FORCE            0x00001000
+#define         AR9170_PHY_TIMING2_FORCE                0x00000fff
+#define         AR9170_PHY_TIMING2_FORCE_S                       0
+
+#define AR9170_PHY_REG_TIMING3                  (AR9170_PHY_REG_BASE + 0x0014)
+#define         AR9170_PHY_TIMING3_DSC_EXP              0x0001e000
+#define         AR9170_PHY_TIMING3_DSC_EXP_S            13
+#define         AR9170_PHY_TIMING3_DSC_MAN              0xfffe0000
+#define         AR9170_PHY_TIMING3_DSC_MAN_S            17
+
+#define AR9170_PHY_REG_CHIP_ID                  (AR9170_PHY_REG_BASE + 0x0018)
+#define         AR9170_PHY_CHIP_ID_REV_0                0x80
+#define         AR9170_PHY_CHIP_ID_REV_1                0x81
+#define         AR9170_PHY_CHIP_ID_9160_REV_0           0xb0
+
+#define AR9170_PHY_REG_ACTIVE                   (AR9170_PHY_REG_BASE + 0x001c)
+#define         AR9170_PHY_ACTIVE_EN                    0x00000001
+#define         AR9170_PHY_ACTIVE_DIS                   0x00000000
+
+#define AR9170_PHY_REG_RF_CTL2                  (AR9170_PHY_REG_BASE + 0x0024)
+#define         AR9170_PHY_RF_CTL2_TX_END_DATA_START    0x000000ff
+#define         AR9170_PHY_RF_CTL2_TX_END_DATA_START_S  0
+#define         AR9170_PHY_RF_CTL2_TX_END_PA_ON         0x0000ff00
+#define         AR9170_PHY_RF_CTL2_TX_END_PA_ON_S       8
+
+#define AR9170_PHY_REG_RF_CTL3                  (AR9170_PHY_REG_BASE + 0x0028)
+#define         AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON   0x00ff0000
+#define         AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 16
+
+#define AR9170_PHY_REG_ADC_CTL                  (AR9170_PHY_REG_BASE + 0x002c)
+#define         AR9170_PHY_ADC_CTL_OFF_INBUFGAIN        0x00000003
+#define         AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S      0
+#define         AR9170_PHY_ADC_CTL_OFF_PWDDAC           0x00002000
+#define         AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP       0x00004000
+#define         AR9170_PHY_ADC_CTL_OFF_PWDADC           0x00008000
+#define         AR9170_PHY_ADC_CTL_ON_INBUFGAIN         0x00030000
+#define         AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S       16
+
+#define AR9170_PHY_REG_ADC_SERIAL_CTL           (AR9170_PHY_REG_BASE + 0x0030)
+#define         AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC  0x00000000
+#define         AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO  0x00000001
+
+#define AR9170_PHY_REG_RF_CTL4                  (AR9170_PHY_REG_BASE + 0x0034)
+#define         AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF      0xff000000
+#define         AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S    24
+#define         AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF      0x00ff0000
+#define         AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S    16
+#define         AR9170_PHY_RF_CTL4_FRAME_XPAB_ON        0x0000ff00
+#define         AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S      8
+#define         AR9170_PHY_RF_CTL4_FRAME_XPAA_ON        0x000000ff
+#define         AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S      0
+
+#define AR9170_PHY_REG_TSTDAC_CONST             (AR9170_PHY_REG_BASE + 0x003c)
+
+#define AR9170_PHY_REG_SETTLING                 (AR9170_PHY_REG_BASE + 0x0044)
+#define         AR9170_PHY_SETTLING_SWITCH              0x00003f80
+#define         AR9170_PHY_SETTLING_SWITCH_S            7
+
+#define AR9170_PHY_REG_RXGAIN                   (AR9170_PHY_REG_BASE + 0x0048)
+#define AR9170_PHY_REG_RXGAIN_CHAIN_2           (AR9170_PHY_REG_BASE + 0x2048)
+#define         AR9170_PHY_RXGAIN_TXRX_ATTEN            0x0003f000
+#define         AR9170_PHY_RXGAIN_TXRX_ATTEN_S          12
+#define         AR9170_PHY_RXGAIN_TXRX_RF_MAX           0x007c0000
+#define         AR9170_PHY_RXGAIN_TXRX_RF_MAX_S         18
+
+#define AR9170_PHY_REG_DESIRED_SZ               (AR9170_PHY_REG_BASE + 0x0050)
+#define         AR9170_PHY_DESIRED_SZ_ADC               0x000000ff
+#define         AR9170_PHY_DESIRED_SZ_ADC_S             0
+#define         AR9170_PHY_DESIRED_SZ_PGA               0x0000ff00
+#define         AR9170_PHY_DESIRED_SZ_PGA_S             8
+#define         AR9170_PHY_DESIRED_SZ_TOT_DES           0x0ff00000
+#define         AR9170_PHY_DESIRED_SZ_TOT_DES_S         20
+
+#define AR9170_PHY_REG_FIND_SIG                 (AR9170_PHY_REG_BASE + 0x0058)
+#define         AR9170_PHY_FIND_SIG_FIRSTEP             0x0003f000
+#define         AR9170_PHY_FIND_SIG_FIRSTEP_S           12
+#define         AR9170_PHY_FIND_SIG_FIRPWR              0x03fc0000
+#define         AR9170_PHY_FIND_SIG_FIRPWR_S            18
+
+#define AR9170_PHY_REG_AGC_CTL1                 (AR9170_PHY_REG_BASE + 0x005c)
+#define         AR9170_PHY_AGC_CTL1_COARSE_LOW          0x00007f80
+#define         AR9170_PHY_AGC_CTL1_COARSE_LOW_S        7
+#define         AR9170_PHY_AGC_CTL1_COARSE_HIGH         0x003f8000
+#define         AR9170_PHY_AGC_CTL1_COARSE_HIGH_S       15
+
+#define AR9170_PHY_REG_AGC_CONTROL              (AR9170_PHY_REG_BASE + 0x0060)
+#define         AR9170_PHY_AGC_CONTROL_CAL              0x00000001
+#define         AR9170_PHY_AGC_CONTROL_NF               0x00000002
+#define         AR9170_PHY_AGC_CONTROL_ENABLE_NF        0x00008000
+#define         AR9170_PHY_AGC_CONTROL_FLTR_CAL         0x00010000
+#define         AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF     0x00020000
+
+#define AR9170_PHY_REG_CCA                      (AR9170_PHY_REG_BASE + 0x0064)
+#define         AR9170_PHY_CCA_MIN_PWR                  0x0ff80000
+#define         AR9170_PHY_CCA_MIN_PWR_S                19
+#define         AR9170_PHY_CCA_THRESH62                 0x0007f000
+#define         AR9170_PHY_CCA_THRESH62_S               12
+
+#define AR9170_PHY_REG_SFCORR                   (AR9170_PHY_REG_BASE + 0x0068)
+#define         AR9170_PHY_SFCORR_M2COUNT_THR           0x0000001f
+#define         AR9170_PHY_SFCORR_M2COUNT_THR_S         0
+#define         AR9170_PHY_SFCORR_M1_THRESH             0x00fe0000
+#define         AR9170_PHY_SFCORR_M1_THRESH_S           17
+#define         AR9170_PHY_SFCORR_M2_THRESH             0x7f000000
+#define         AR9170_PHY_SFCORR_M2_THRESH_S           24
+
+#define AR9170_PHY_REG_SFCORR_LOW               (AR9170_PHY_REG_BASE + 0x006c)
+#define         AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
+#define         AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW   0x00003f00
+#define         AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
+#define         AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW     0x001fc000
+#define         AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S   14
+#define         AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW     0x0fe00000
+#define         AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S   21
+
+#define AR9170_PHY_REG_SLEEP_CTR_CONTROL        (AR9170_PHY_REG_BASE + 0x0070)
+#define AR9170_PHY_REG_SLEEP_CTR_LIMIT          (AR9170_PHY_REG_BASE + 0x0074)
+#define AR9170_PHY_REG_SLEEP_SCAL               (AR9170_PHY_REG_BASE + 0x0078)
+
+#define AR9170_PHY_REG_PLL_CTL                  (AR9170_PHY_REG_BASE + 0x007c)
+#define         AR9170_PHY_PLL_CTL_40                   0xaa
+#define         AR9170_PHY_PLL_CTL_40_5413              0x04
+#define         AR9170_PHY_PLL_CTL_44                   0xab
+#define         AR9170_PHY_PLL_CTL_44_2133              0xeb
+#define         AR9170_PHY_PLL_CTL_40_2133              0xea
+
+#define AR9170_PHY_REG_BIN_MASK_1               (AR9170_PHY_REG_BASE + 0x0100)
+#define AR9170_PHY_REG_BIN_MASK_2               (AR9170_PHY_REG_BASE + 0x0104)
+#define AR9170_PHY_REG_BIN_MASK_3               (AR9170_PHY_REG_BASE + 0x0108)
+#define AR9170_PHY_REG_MASK_CTL                 (AR9170_PHY_REG_BASE + 0x010c)
+
+/* analogue power on time (100ns) */
+#define AR9170_PHY_REG_RX_DELAY                 (AR9170_PHY_REG_BASE + 0x0114)
+#define AR9170_PHY_REG_SEARCH_START_DELAY       (AR9170_PHY_REG_BASE + 0x0118)
+#define         AR9170_PHY_RX_DELAY_DELAY               0x00003fff
+
+#define AR9170_PHY_REG_TIMING_CTRL4(_i)         (AR9170_PHY_REG_BASE + \
+                                                (0x0120 + ((_i) << 12)))
+#define         AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF         0x01f
+#define         AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S       0
+#define         AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF         0x7e0
+#define         AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S       5
+#define         AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE           0x800
+#define         AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX     0xf000
+#define         AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S   12
+#define         AR9170_PHY_TIMING_CTRL4_DO_IQCAL                0x10000
+#define         AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI        0x80000000
+#define         AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER      0x40000000
+#define         AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK        0x20000000
+#define         AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK       0x10000000
+
+#define AR9170_PHY_REG_TIMING5                  (AR9170_PHY_REG_BASE + 0x0124)
+#define         AR9170_PHY_TIMING5_CYCPWR_THR1          0x000000fe
+#define         AR9170_PHY_TIMING5_CYCPWR_THR1_S        1
+
+#define AR9170_PHY_REG_POWER_TX_RATE1           (AR9170_PHY_REG_BASE + 0x0134)
+#define AR9170_PHY_REG_POWER_TX_RATE2           (AR9170_PHY_REG_BASE + 0x0138)
+#define AR9170_PHY_REG_POWER_TX_RATE_MAX        (AR9170_PHY_REG_BASE + 0x013c)
+#define         AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
+
+#define AR9170_PHY_REG_FRAME_CTL                (AR9170_PHY_REG_BASE + 0x0144)
+#define         AR9170_PHY_FRAME_CTL_TX_CLIP            0x00000038
+#define         AR9170_PHY_FRAME_CTL_TX_CLIP_S          3
+
+#define AR9170_PHY_REG_SPUR_REG                 (AR9170_PHY_REG_BASE + 0x014c)
+#define         AR9170_PHY_SPUR_REG_MASK_RATE_CNTL      (0xff << 18)
+#define         AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S    18
+#define         AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM     0x20000
+#define         AR9170_PHY_SPUR_REG_MASK_RATE_SELECT    (0xff << 9)
+#define         AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S  9
+#define         AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI        0x100
+#define         AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH    0x7f
+#define         AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S  0
+
+#define AR9170_PHY_REG_RADAR_EXT                (AR9170_PHY_REG_BASE + 0x0140)
+#define         AR9170_PHY_RADAR_EXT_ENA                0x00004000
+
+#define AR9170_PHY_REG_RADAR_0                  (AR9170_PHY_REG_BASE + 0x0154)
+#define         AR9170_PHY_RADAR_0_ENA                  0x00000001
+#define         AR9170_PHY_RADAR_0_FFT_ENA              0x80000000
+/* inband pulse threshold */
+#define         AR9170_PHY_RADAR_0_INBAND               0x0000003e
+#define         AR9170_PHY_RADAR_0_INBAND_S             1
+/* pulse RSSI threshold */
+#define         AR9170_PHY_RADAR_0_PRSSI                0x00000fc0
+#define         AR9170_PHY_RADAR_0_PRSSI_S              6
+/* pulse height threshold */
+#define         AR9170_PHY_RADAR_0_HEIGHT               0x0003f000
+#define         AR9170_PHY_RADAR_0_HEIGHT_S             12
+/* radar RSSI threshold */
+#define         AR9170_PHY_RADAR_0_RRSSI                0x00fc0000
+#define         AR9170_PHY_RADAR_0_RRSSI_S              18
+/* radar firepower threshold */
+#define         AR9170_PHY_RADAR_0_FIRPWR               0x7f000000
+#define         AR9170_PHY_RADAR_0_FIRPWR_S             24
+
+#define AR9170_PHY_REG_RADAR_1                  (AR9170_PHY_REG_BASE + 0x0158)
+#define         AR9170_PHY_RADAR_1_RELPWR_ENA           0x00800000
+#define         AR9170_PHY_RADAR_1_USE_FIR128           0x00400000
+#define         AR9170_PHY_RADAR_1_RELPWR_THRESH        0x003f0000
+#define         AR9170_PHY_RADAR_1_RELPWR_THRESH_S      16
+#define         AR9170_PHY_RADAR_1_BLOCK_CHECK          0x00008000
+#define         AR9170_PHY_RADAR_1_MAX_RRSSI            0x00004000
+#define         AR9170_PHY_RADAR_1_RELSTEP_CHECK        0x00002000
+#define         AR9170_PHY_RADAR_1_RELSTEP_THRESH       0x00001f00
+#define         AR9170_PHY_RADAR_1_RELSTEP_THRESH_S     8
+#define         AR9170_PHY_RADAR_1_MAXLEN               0x000000ff
+#define         AR9170_PHY_RADAR_1_MAXLEN_S             0
+
+#define AR9170_PHY_REG_SWITCH_CHAIN_0           (AR9170_PHY_REG_BASE + 0x0160)
+#define AR9170_PHY_REG_SWITCH_CHAIN_2           (AR9170_PHY_REG_BASE + 0x2160)
+
+#define AR9170_PHY_REG_SWITCH_COM               (AR9170_PHY_REG_BASE + 0x0164)
+
+#define AR9170_PHY_REG_CCA_THRESHOLD            (AR9170_PHY_REG_BASE + 0x0168)
+
+#define AR9170_PHY_REG_SIGMA_DELTA              (AR9170_PHY_REG_BASE + 0x016c)
+#define         AR9170_PHY_SIGMA_DELTA_ADC_SEL          0x00000003
+#define         AR9170_PHY_SIGMA_DELTA_ADC_SEL_S        0
+#define         AR9170_PHY_SIGMA_DELTA_FILT2            0x000000f8
+#define         AR9170_PHY_SIGMA_DELTA_FILT2_S          3
+#define         AR9170_PHY_SIGMA_DELTA_FILT1            0x00001f00
+#define         AR9170_PHY_SIGMA_DELTA_FILT1_S          8
+#define         AR9170_PHY_SIGMA_DELTA_ADC_CLIP         0x01ffe000
+#define         AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S       13
+
+#define AR9170_PHY_REG_RESTART                  (AR9170_PHY_REG_BASE + 0x0170)
+#define         AR9170_PHY_RESTART_DIV_GC               0x001c0000
+#define         AR9170_PHY_RESTART_DIV_GC_S             18
+
+#define AR9170_PHY_REG_RFBUS_REQ                (AR9170_PHY_REG_BASE + 0x017c)
+#define         AR9170_PHY_RFBUS_REQ_EN                 0x00000001
+
+#define AR9170_PHY_REG_TIMING7                  (AR9170_PHY_REG_BASE + 0x0180)
+#define AR9170_PHY_REG_TIMING8                  (AR9170_PHY_REG_BASE + 0x0184)
+#define         AR9170_PHY_TIMING8_PILOT_MASK_2         0x000fffff
+#define         AR9170_PHY_TIMING8_PILOT_MASK_2_S       0
+
+#define AR9170_PHY_REG_BIN_MASK2_1              (AR9170_PHY_REG_BASE + 0x0188)
+#define AR9170_PHY_REG_BIN_MASK2_2              (AR9170_PHY_REG_BASE + 0x018c)
+#define AR9170_PHY_REG_BIN_MASK2_3              (AR9170_PHY_REG_BASE + 0x0190)
+#define AR9170_PHY_REG_BIN_MASK2_4              (AR9170_PHY_REG_BASE + 0x0194)
+#define         AR9170_PHY_BIN_MASK2_4_MASK_4           0x00003fff
+#define         AR9170_PHY_BIN_MASK2_4_MASK_4_S         0
+
+#define AR9170_PHY_REG_TIMING9                  (AR9170_PHY_REG_BASE + 0x0198)
+#define AR9170_PHY_REG_TIMING10                 (AR9170_PHY_REG_BASE + 0x019c)
+#define         AR9170_PHY_TIMING10_PILOT_MASK_2        0x000fffff
+#define         AR9170_PHY_TIMING10_PILOT_MASK_2_S      0
+
+#define AR9170_PHY_REG_TIMING11                 (AR9170_PHY_REG_BASE + 0x01a0)
+#define         AR9170_PHY_TIMING11_SPUR_DELTA_PHASE    0x000fffff
+#define         AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S  0
+#define         AR9170_PHY_TIMING11_SPUR_FREQ_SD        0x3ff00000
+#define         AR9170_PHY_TIMING11_SPUR_FREQ_SD_S      20
+#define         AR9170_PHY_TIMING11_USE_SPUR_IN_AGC     0x40000000
+#define         AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
+
+#define AR9170_PHY_REG_RX_CHAINMASK             (AR9170_PHY_REG_BASE + 0x01a4)
+#define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \
+                                                 0x01b4 + ((_i) << 12))
+#define         AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE             0x40000000
+#define         AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE        0x80000000
+
+#define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL      (AR9170_PHY_REG_BASE + 0x01ac)
+#define         AR9170_PHY_9285_ANT_DIV_CTL_ALL         0x7f000000
+#define         AR9170_PHY_9285_ANT_DIV_CTL             0x01000000
+#define         AR9170_PHY_9285_ANT_DIV_CTL_S           24
+#define         AR9170_PHY_9285_ANT_DIV_ALT_LNACONF     0x06000000
+#define         AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S   25
+#define         AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF    0x18000000
+#define         AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S  27
+#define         AR9170_PHY_9285_ANT_DIV_ALT_GAINTB      0x20000000
+#define         AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S    29
+#define         AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB     0x40000000
+#define         AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S   30
+#define         AR9170_PHY_9285_ANT_DIV_LNA1            2
+#define         AR9170_PHY_9285_ANT_DIV_LNA2            1
+#define         AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2  3
+#define         AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
+#define         AR9170_PHY_9285_ANT_DIV_GAINTB_0        0
+#define         AR9170_PHY_9285_ANT_DIV_GAINTB_1        1
+
+#define AR9170_PHY_REG_EXT_CCA0                 (AR9170_PHY_REG_BASE + 0x01b8)
+#define         AR9170_PHY_REG_EXT_CCA0_THRESH62        0x000000ff
+#define         AR9170_PHY_REG_EXT_CCA0_THRESH62_S      0
+
+#define AR9170_PHY_REG_EXT_CCA                  (AR9170_PHY_REG_BASE + 0x01bc)
+#define         AR9170_PHY_EXT_CCA_CYCPWR_THR1          0x0000fe00
+#define         AR9170_PHY_EXT_CCA_CYCPWR_THR1_S        9
+#define         AR9170_PHY_EXT_CCA_THRESH62             0x007f0000
+#define         AR9170_PHY_EXT_CCA_THRESH62_S           16
+#define         AR9170_PHY_EXT_CCA_MIN_PWR              0xff800000
+#define         AR9170_PHY_EXT_CCA_MIN_PWR_S            23
+
+#define AR9170_PHY_REG_SFCORR_EXT               (AR9170_PHY_REG_BASE + 0x01c0)
+#define         AR9170_PHY_SFCORR_EXT_M1_THRESH         0x0000007f
+#define         AR9170_PHY_SFCORR_EXT_M1_THRESH_S       0
+#define         AR9170_PHY_SFCORR_EXT_M2_THRESH         0x00003f80
+#define         AR9170_PHY_SFCORR_EXT_M2_THRESH_S       7
+#define         AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW     0x001fc000
+#define         AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S   14
+#define         AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW     0x0fe00000
+#define         AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S   21
+#define         AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S     28
+
+#define AR9170_PHY_REG_HALFGI                   (AR9170_PHY_REG_BASE + 0x01d0)
+#define         AR9170_PHY_HALFGI_DSC_MAN               0x0007fff0
+#define         AR9170_PHY_HALFGI_DSC_MAN_S             4
+#define         AR9170_PHY_HALFGI_DSC_EXP               0x0000000f
+#define         AR9170_PHY_HALFGI_DSC_EXP_S             0
+
+#define AR9170_PHY_REG_CHANNEL_MASK_01_30       (AR9170_PHY_REG_BASE + 0x01d4)
+#define AR9170_PHY_REG_CHANNEL_MASK_31_60       (AR9170_PHY_REG_BASE + 0x01d8)
+
+#define AR9170_PHY_REG_CHAN_INFO_MEMORY         (AR9170_PHY_REG_BASE + 0x01dc)
+#define         AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK        0x0001
+
+#define AR9170_PHY_REG_HEAVY_CLIP_ENABLE        (AR9170_PHY_REG_BASE + 0x01e0)
+#define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS   (AR9170_PHY_REG_BASE + 0x01ec)
+#define         AR9170_PHY_RIFS_INIT_DELAY              0x03ff0000
+
+#define AR9170_PHY_REG_CALMODE                  (AR9170_PHY_REG_BASE + 0x01f0)
+#define         AR9170_PHY_CALMODE_IQ                   0x00000000
+#define         AR9170_PHY_CALMODE_ADC_GAIN             0x00000001
+#define         AR9170_PHY_CALMODE_ADC_DC_PER           0x00000002
+#define         AR9170_PHY_CALMODE_ADC_DC_INIT          0x00000003
+
+#define AR9170_PHY_REG_REFCLKDLY                (AR9170_PHY_REG_BASE + 0x01f4)
+#define AR9170_PHY_REG_REFCLKPD                 (AR9170_PHY_REG_BASE + 0x01f8)
+
+
+#define AR9170_PHY_REG_CAL_MEAS_0(_i)           (AR9170_PHY_REG_BASE + \
+                                                 0x0410 + ((_i) << 12))
+#define AR9170_PHY_REG_CAL_MEAS_1(_i)           (AR9170_PHY_REG_BASE + \
+                                                 0x0414 \ + ((_i) << 12))
+#define AR9170_PHY_REG_CAL_MEAS_2(_i)           (AR9170_PHY_REG_BASE + \
+                                                 0x0418 + ((_i) << 12))
+#define AR9170_PHY_REG_CAL_MEAS_3(_i)           (AR9170_PHY_REG_BASE + \
+                                                 0x041c + ((_i) << 12))
+
+#define AR9170_PHY_REG_CURRENT_RSSI             (AR9170_PHY_REG_BASE + 0x041c)
+
+#define AR9170_PHY_REG_RFBUS_GRANT              (AR9170_PHY_REG_BASE + 0x0420)
+#define         AR9170_PHY_RFBUS_GRANT_EN               0x00000001
+
+#define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF      (AR9170_PHY_REG_BASE + 0x04f4)
+#define         AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT      320
+
+#define AR9170_PHY_REG_CHAN_INFO_GAIN           (AR9170_PHY_REG_BASE + 0x04fc)
+
+#define AR9170_PHY_REG_MODE                     (AR9170_PHY_REG_BASE + 0x0a00)
+#define         AR9170_PHY_MODE_ASYNCFIFO               0x80
+#define         AR9170_PHY_MODE_AR2133                  0x08
+#define         AR9170_PHY_MODE_AR5111                  0x00
+#define         AR9170_PHY_MODE_AR5112                  0x08
+#define         AR9170_PHY_MODE_DYNAMIC                 0x04
+#define         AR9170_PHY_MODE_RF2GHZ                  0x02
+#define         AR9170_PHY_MODE_RF5GHZ                  0x00
+#define         AR9170_PHY_MODE_CCK                     0x01
+#define         AR9170_PHY_MODE_OFDM                    0x00
+#define         AR9170_PHY_MODE_DYN_CCK_DISABLE         0x100
+
+#define AR9170_PHY_REG_CCK_TX_CTRL              (AR9170_PHY_REG_BASE + 0x0a04)
+#define         AR9170_PHY_CCK_TX_CTRL_JAPAN                    0x00000010
+#define         AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK         0x0000000c
+#define         AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S       2
+
+#define AR9170_PHY_REG_CCK_DETECT               (AR9170_PHY_REG_BASE + 0x0a08)
+#define         AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003f
+#define         AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
+/* [12:6] settling time for antenna switch */
+#define         AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001fc0
+#define         AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S         6
+#define         AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV    0x2000
+#define         AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S  13
+
+#define AR9170_PHY_REG_GAIN_2GHZ                (AR9170_PHY_REG_BASE + 0x0a0c)
+#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2        (AR9170_PHY_REG_BASE + 0x2a0c)
+#define         AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN        0x00fc0000
+#define         AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S      18
+#define         AR9170_PHY_GAIN_2GHZ_BSW_MARGIN         0x00003c00
+#define         AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S       10
+#define         AR9170_PHY_GAIN_2GHZ_BSW_ATTEN          0x0000001f
+#define         AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S        0
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN     0x003e0000
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S   17
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN     0x0001f000
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S   12
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN2_DB         0x00000fc0
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S       6
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN1_DB         0x0000003f
+#define         AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S       0
+
+#define AR9170_PHY_REG_CCK_RXCTRL4              (AR9170_PHY_REG_BASE + 0x0a1c)
+#define         AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT   0x01f80000
+#define         AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
+
+#define AR9170_PHY_REG_DAG_CTRLCCK              (AR9170_PHY_REG_BASE + 0x0a28)
+#define         AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR      0x00000200
+#define         AR9170_REG_DAG_CTRLCCK_RSSI_THR         0x0001fc00
+#define         AR9170_REG_DAG_CTRLCCK_RSSI_THR_S       10
+
+#define AR9170_PHY_REG_FORCE_CLKEN_CCK          (AR9170_PHY_REG_BASE + 0x0a2c)
+#define         AR9170_FORCE_CLKEN_CCK_MRC_MUX          0x00000040
+
+#define AR9170_PHY_REG_POWER_TX_RATE3           (AR9170_PHY_REG_BASE + 0x0a34)
+#define AR9170_PHY_REG_POWER_TX_RATE4           (AR9170_PHY_REG_BASE + 0x0a38)
+
+#define AR9170_PHY_REG_SCRM_SEQ_XR              (AR9170_PHY_REG_BASE + 0x0a3c)
+#define AR9170_PHY_REG_HEADER_DETECT_XR         (AR9170_PHY_REG_BASE + 0x0a40)
+#define AR9170_PHY_REG_CHIRP_DETECTED_XR        (AR9170_PHY_REG_BASE + 0x0a44)
+#define AR9170_PHY_REG_BLUETOOTH                (AR9170_PHY_REG_BASE + 0x0a54)
+
+#define AR9170_PHY_REG_TPCRG1                   (AR9170_PHY_REG_BASE + 0x0a58)
+#define         AR9170_PHY_TPCRG1_NUM_PD_GAIN           0x0000c000
+#define         AR9170_PHY_TPCRG1_NUM_PD_GAIN_S         14
+#define         AR9170_PHY_TPCRG1_PD_GAIN_1             0x00030000
+#define         AR9170_PHY_TPCRG1_PD_GAIN_1_S           16
+#define         AR9170_PHY_TPCRG1_PD_GAIN_2             0x000c0000
+#define         AR9170_PHY_TPCRG1_PD_GAIN_2_S           18
+#define         AR9170_PHY_TPCRG1_PD_GAIN_3             0x00300000
+#define         AR9170_PHY_TPCRG1_PD_GAIN_3_S           20
+#define         AR9170_PHY_TPCRG1_PD_CAL_ENABLE         0x00400000
+#define         AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S       22
+
+#define AR9170_PHY_REG_TX_PWRCTRL4              (AR9170_PHY_REG_BASE + 0x0a64)
+#define         AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID      0x00000001
+#define         AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S    0
+#define         AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT        0x000001fe
+#define         AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S      1
+
+#define AR9170_PHY_REG_ANALOG_SWAP              (AR9170_PHY_REG_BASE + 0x0a68)
+#define         AR9170_PHY_ANALOG_SWAP_AB               0x0001
+#define         AR9170_PHY_ANALOG_SWAP_ALT_CHAIN        0x00000040
+
+#define AR9170_PHY_REG_TPCRG5                   (AR9170_PHY_REG_BASE + 0x0a6c)
+#define         AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP       0x0000000f
+#define         AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S     0
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1    0x000003f0
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S  4
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2    0x0000fc00
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S  10
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3    0x003f0000
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S  16
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4    0x0fc00000
+#define         AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S  22
+
+#define AR9170_PHY_REG_TX_PWRCTRL6_0            (AR9170_PHY_REG_BASE + 0x0a70)
+#define AR9170_PHY_REG_TX_PWRCTRL6_1            (AR9170_PHY_REG_BASE + 0x1a70)
+#define         AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE      0x03000000
+#define         AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S    24
+
+#define AR9170_PHY_REG_TX_PWRCTRL7              (AR9170_PHY_REG_BASE + 0x0a74)
+#define         AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN      0x01f80000
+#define         AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S    19
+
+#define AR9170_PHY_REG_TX_PWRCTRL9              (AR9170_PHY_REG_BASE + 0x0a7c)
+#define         AR9170_PHY_TX_DESIRED_SCALE_CCK         0x00007c00
+#define         AR9170_PHY_TX_DESIRED_SCALE_CCK_S       10
+#define         AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL   0x80000000
+#define         AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
+
+#define AR9170_PHY_REG_TX_GAIN_TBL1             (AR9170_PHY_REG_BASE + 0x0b00)
+#define         AR9170_PHY_TX_GAIN                      0x0007f000
+#define         AR9170_PHY_TX_GAIN_S                    12
+
+/* Carrier leak calibration control, do it after AGC calibration */
+#define AR9170_PHY_REG_CL_CAL_CTL               (AR9170_PHY_REG_BASE + 0x0b58)
+#define         AR9170_PHY_CL_CAL_ENABLE                0x00000002
+#define         AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE   0x00000001
+
+#define AR9170_PHY_REG_POWER_TX_RATE5           (AR9170_PHY_REG_BASE + 0x0b8c)
+#define AR9170_PHY_REG_POWER_TX_RATE6           (AR9170_PHY_REG_BASE + 0x0b90)
+
+#define AR9170_PHY_REG_CH0_TX_PWRCTRL11         (AR9170_PHY_REG_BASE + 0x0b98)
+#define AR9170_PHY_REG_CH1_TX_PWRCTRL11         (AR9170_PHY_REG_BASE + 0x1b98)
+#define         AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP        0x0000fc00
+#define         AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S      10
+
+#define AR9170_PHY_REG_CAL_CHAINMASK            (AR9170_PHY_REG_BASE + 0x0b9c)
+#define AR9170_PHY_REG_VIT_MASK2_M_46_61        (AR9170_PHY_REG_BASE + 0x0ba0)
+#define AR9170_PHY_REG_MASK2_M_31_45            (AR9170_PHY_REG_BASE + 0x0ba4)
+#define AR9170_PHY_REG_MASK2_M_16_30            (AR9170_PHY_REG_BASE + 0x0ba8)
+#define AR9170_PHY_REG_MASK2_M_00_15            (AR9170_PHY_REG_BASE + 0x0bac)
+#define AR9170_PHY_REG_PILOT_MASK_01_30         (AR9170_PHY_REG_BASE + 0x0bb0)
+#define AR9170_PHY_REG_PILOT_MASK_31_60         (AR9170_PHY_REG_BASE + 0x0bb4)
+#define AR9170_PHY_REG_MASK2_P_15_01            (AR9170_PHY_REG_BASE + 0x0bb8)
+#define AR9170_PHY_REG_MASK2_P_30_16            (AR9170_PHY_REG_BASE + 0x0bbc)
+#define AR9170_PHY_REG_MASK2_P_45_31            (AR9170_PHY_REG_BASE + 0x0bc0)
+#define AR9170_PHY_REG_MASK2_P_61_45            (AR9170_PHY_REG_BASE + 0x0bc4)
+#define AR9170_PHY_REG_POWER_TX_SUB             (AR9170_PHY_REG_BASE + 0x0bc8)
+#define AR9170_PHY_REG_POWER_TX_RATE7           (AR9170_PHY_REG_BASE + 0x0bcc)
+#define AR9170_PHY_REG_POWER_TX_RATE8           (AR9170_PHY_REG_BASE + 0x0bd0)
+#define AR9170_PHY_REG_POWER_TX_RATE9           (AR9170_PHY_REG_BASE + 0x0bd4)
+#define AR9170_PHY_REG_XPA_CFG                  (AR9170_PHY_REG_BASE + 0x0bd8)
+#define         AR9170_PHY_FORCE_XPA_CFG                0x000000001
+#define         AR9170_PHY_FORCE_XPA_CFG_S              0
+
+#define AR9170_PHY_REG_CH1_CCA                  (AR9170_PHY_REG_BASE + 0x1064)
+#define         AR9170_PHY_CH1_CCA_MIN_PWR              0x0ff80000
+#define         AR9170_PHY_CH1_CCA_MIN_PWR_S            19
+
+#define AR9170_PHY_REG_CH2_CCA                  (AR9170_PHY_REG_BASE + 0x2064)
+#define         AR9170_PHY_CH2_CCA_MIN_PWR              0x0ff80000
+#define         AR9170_PHY_CH2_CCA_MIN_PWR_S            19
+
+#define AR9170_PHY_REG_CH1_EXT_CCA              (AR9170_PHY_REG_BASE + 0x11bc)
+#define         AR9170_PHY_CH1_EXT_CCA_MIN_PWR          0xff800000
+#define         AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S        23
+
+#define AR9170_PHY_REG_CH2_EXT_CCA              (AR9170_PHY_REG_BASE + 0x21bc)
+#define         AR9170_PHY_CH2_EXT_CCA_MIN_PWR          0xff800000
+#define         AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S        23
+
+#endif  /* __CARL9170_SHARED_PHY_H */
diff --git a/drivers/net/wireless/ath/carl9170/rx.c b/drivers/net/wireless/ath/carl9170/rx.c
new file mode 100644
index 000000000000..ec21ea9fd8d5
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/rx.c
@@ -0,0 +1,938 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * 802.11 & command trap routines
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <linux/crc32.h>
+#include <net/mac80211.h>
+#include "carl9170.h"
+#include "hw.h"
+#include "cmd.h"
+
+static void carl9170_dbg_message(struct ar9170 *ar, const char *buf, u32 len)
+{
+        bool restart = false;
+        enum carl9170_restart_reasons reason = CARL9170_RR_NO_REASON;
+
+        if (len > 3) {
+                if (memcmp(buf, CARL9170_ERR_MAGIC, 3) == 0) {
+                        ar->fw.err_counter++;
+                        if (ar->fw.err_counter > 3) {
+                                restart = true;
+                                reason = CARL9170_RR_TOO_MANY_FIRMWARE_ERRORS;
+                        }
+                }
+
+                if (memcmp(buf, CARL9170_BUG_MAGIC, 3) == 0) {
+                        ar->fw.bug_counter++;
+                        restart = true;
+                        reason = CARL9170_RR_FATAL_FIRMWARE_ERROR;
+                }
+        }
+
+        wiphy_info(ar->hw->wiphy, "FW: %.*s\n", len, buf);
+
+        if (restart)
+                carl9170_restart(ar, reason);
+}
+
+static void carl9170_handle_ps(struct ar9170 *ar, struct carl9170_rsp *rsp)
+{
+        u32 ps;
+        bool new_ps;
+
+        ps = le32_to_cpu(rsp->psm.state);
+
+        new_ps = (ps & CARL9170_PSM_COUNTER) != CARL9170_PSM_WAKE;
+        if (ar->ps.state != new_ps) {
+                if (!new_ps) {
+                        ar->ps.sleep_ms = jiffies_to_msecs(jiffies -
+                                ar->ps.last_action);
+                }
+
+                ar->ps.last_action = jiffies;
+
+                ar->ps.state = new_ps;
+        }
+}
+
+static int carl9170_check_sequence(struct ar9170 *ar, unsigned int seq)
+{
+        if (ar->cmd_seq < -1)
+                return 0;
+
+        /*
+         * Initialize Counter
+         */
+        if (ar->cmd_seq < 0)
+                ar->cmd_seq = seq;
+
+        /*
+         * The sequence is strictly monotonic increasing and it never skips!
+         *
+         * Therefore we can safely assume that whenever we received an
+         * unexpected sequence we have lost some valuable data.
+         */
+        if (seq != ar->cmd_seq) {
+                int count;
+
+                count = (seq - ar->cmd_seq) % ar->fw.cmd_bufs;
+
+                wiphy_err(ar->hw->wiphy, "lost %d command responses/traps! "
+                          "w:%d g:%d\n", count, ar->cmd_seq, seq);
+
+                carl9170_restart(ar, CARL9170_RR_LOST_RSP);
+                return -EIO;
+        }
+
+        ar->cmd_seq = (ar->cmd_seq + 1) % ar->fw.cmd_bufs;
+        return 0;
+}
+
+static void carl9170_cmd_callback(struct ar9170 *ar, u32 len, void *buffer)
+{
+        /*
+         * Some commands may have a variable response length
+         * and we cannot predict the correct length in advance.
+         * So we only check if we provided enough space for the data.
+         */
+        if (unlikely(ar->readlen != (len - 4))) {
+                dev_warn(&ar->udev->dev, "received invalid command response:"
+                         "got %d, instead of %d\n", len - 4, ar->readlen);
+                print_hex_dump_bytes("carl9170 cmd:", DUMP_PREFIX_OFFSET,
+                        ar->cmd_buf, (ar->cmd.hdr.len + 4) & 0x3f);
+                print_hex_dump_bytes("carl9170 rsp:", DUMP_PREFIX_OFFSET,
+                        buffer, len);
+                /*
+                 * Do not complete. The command times out,
+                 * and we get a stack trace from there.
+                 */
+                carl9170_restart(ar, CARL9170_RR_INVALID_RSP);
+        }
+
+        spin_lock(&ar->cmd_lock);
+        if (ar->readbuf) {
+                if (len >= 4)
+                        memcpy(ar->readbuf, buffer + 4, len - 4);
+
+                ar->readbuf = NULL;
+        }
+        complete(&ar->cmd_wait);
+        spin_unlock(&ar->cmd_lock);
+}
+
+void carl9170_handle_command_response(struct ar9170 *ar, void *buf, u32 len)
+{
+        struct carl9170_rsp *cmd = (void *) buf;
+        struct ieee80211_vif *vif;
+
+        if (carl9170_check_sequence(ar, cmd->hdr.seq))
+                return;
+
+        if ((cmd->hdr.cmd & CARL9170_RSP_FLAG) != CARL9170_RSP_FLAG) {
+                if (!(cmd->hdr.cmd & CARL9170_CMD_ASYNC_FLAG))
+                        carl9170_cmd_callback(ar, len, buf);
+
+                return;
+        }
+
+        if (unlikely(cmd->hdr.len != (len - 4))) {
+                if (net_ratelimit()) {
+                        wiphy_err(ar->hw->wiphy, "FW: received over-/under"
+                                "sized event %x (%d, but should be %d).\n",
+                               cmd->hdr.cmd, cmd->hdr.len, len - 4);
+
+                        print_hex_dump_bytes("dump:", DUMP_PREFIX_NONE,
+                                             buf, len);
+                }
+
+                return;
+        }
+
+        /* hardware event handlers */
+        switch (cmd->hdr.cmd) {
+        case CARL9170_RSP_PRETBTT:
+                /* pre-TBTT event */
+                rcu_read_lock();
+                vif = carl9170_get_main_vif(ar);
+
+                if (!vif) {
+                        rcu_read_unlock();
+                        break;
+                }
+
+                switch (vif->type) {
+                case NL80211_IFTYPE_STATION:
+                        carl9170_handle_ps(ar, cmd);
+                        break;
+
+                case NL80211_IFTYPE_AP:
+                case NL80211_IFTYPE_ADHOC:
+                        carl9170_update_beacon(ar, true);
+                        break;
+
+                default:
+                        break;
+                }
+                rcu_read_unlock();
+
+                break;
+
+
+        case CARL9170_RSP_TXCOMP:
+                /* TX status notification */
+                carl9170_tx_process_status(ar, cmd);
+                break;
+
+        case CARL9170_RSP_BEACON_CONFIG:
+                /*
+                 * (IBSS) beacon send notification
+                 * bytes: 04 c2 XX YY B4 B3 B2 B1
+                 *
+                 * XX always 80
+                 * YY always 00
+                 * B1-B4 "should" be the number of send out beacons.
+                 */
+                break;
+
+        case CARL9170_RSP_ATIM:
+                /* End of Atim Window */
+                break;
+
+        case CARL9170_RSP_WATCHDOG:
+                /* Watchdog Interrupt */
+                carl9170_restart(ar, CARL9170_RR_WATCHDOG);
+                break;
+
+        case CARL9170_RSP_TEXT:
+                /* firmware debug */
+                carl9170_dbg_message(ar, (char *)buf + 4, len - 4);
+                break;
+
+        case CARL9170_RSP_HEXDUMP:
+                wiphy_dbg(ar->hw->wiphy, "FW: HD %d\n", len - 4);
+                print_hex_dump_bytes("FW:", DUMP_PREFIX_NONE,
+                                     (char *)buf + 4, len - 4);
+                break;
+
+        case CARL9170_RSP_RADAR:
+                if (!net_ratelimit())
+                        break;
+
+                wiphy_info(ar->hw->wiphy, "FW: RADAR! Please report this "
+                       "incident to linux-wireless@vger.kernel.org !\n");
+                break;
+
+        case CARL9170_RSP_GPIO:
+#ifdef CONFIG_CARL9170_WPC
+                if (ar->wps.pbc) {
+                        bool state = !!(cmd->gpio.gpio & cpu_to_le32(
+                                AR9170_GPIO_PORT_WPS_BUTTON_PRESSED));
+
+                        if (state != ar->wps.pbc_state) {
+                                ar->wps.pbc_state = state;
+                                input_report_key(ar->wps.pbc, KEY_WPS_BUTTON,
+                                                 state);
+                                input_sync(ar->wps.pbc);
+                        }
+                }
+#endif /* CONFIG_CARL9170_WPC */
+                break;
+
+        case CARL9170_RSP_BOOT:
+                complete(&ar->fw_boot_wait);
+                break;
+
+        default:
+                wiphy_err(ar->hw->wiphy, "FW: received unhandled event %x\n",
+                        cmd->hdr.cmd);
+                print_hex_dump_bytes("dump:", DUMP_PREFIX_NONE, buf, len);
+                break;
+        }
+}
+
+static int carl9170_rx_mac_status(struct ar9170 *ar,
+        struct ar9170_rx_head *head, struct ar9170_rx_macstatus *mac,
+        struct ieee80211_rx_status *status)
+{
+        struct ieee80211_channel *chan;
+        u8 error, decrypt;
+
+        BUILD_BUG_ON(sizeof(struct ar9170_rx_head) != 12);
+        BUILD_BUG_ON(sizeof(struct ar9170_rx_macstatus) != 4);
+
+        error = mac->error;
+
+        if (error & AR9170_RX_ERROR_WRONG_RA) {
+                if (!ar->sniffer_enabled)
+                        return -EINVAL;
+        }
+
+        if (error & AR9170_RX_ERROR_PLCP) {
+                if (!(ar->filter_state & FIF_PLCPFAIL))
+                        return -EINVAL;
+
+                status->flag |= RX_FLAG_FAILED_PLCP_CRC;
+        }
+
+        if (error & AR9170_RX_ERROR_FCS) {
+                ar->tx_fcs_errors++;
+
+                if (!(ar->filter_state & FIF_FCSFAIL))
+                        return -EINVAL;
+
+                status->flag |= RX_FLAG_FAILED_FCS_CRC;
+        }
+
+        decrypt = ar9170_get_decrypt_type(mac);
+        if (!(decrypt & AR9170_RX_ENC_SOFTWARE) &&
+            decrypt != AR9170_ENC_ALG_NONE) {
+                if ((decrypt == AR9170_ENC_ALG_TKIP) &&
+                    (error & AR9170_RX_ERROR_MMIC))
+                        status->flag |= RX_FLAG_MMIC_ERROR;
+
+                status->flag |= RX_FLAG_DECRYPTED;
+        }
+
+        if (error & AR9170_RX_ERROR_DECRYPT && !ar->sniffer_enabled)
+                return -ENODATA;
+
+        error &= ~(AR9170_RX_ERROR_MMIC |
+                   AR9170_RX_ERROR_FCS |
+                   AR9170_RX_ERROR_WRONG_RA |
+                   AR9170_RX_ERROR_DECRYPT |
+                   AR9170_RX_ERROR_PLCP);
+
+        /* drop any other error frames */
+        if (unlikely(error)) {
+                /* TODO: update netdevice's RX dropped/errors statistics */
+
+                if (net_ratelimit())
+                        wiphy_dbg(ar->hw->wiphy, "received frame with "
+                               "suspicious error code (%#x).\n", error);
+
+                return -EINVAL;
+        }
+
+        chan = ar->channel;
+        if (chan) {
+                status->band = chan->band;
+                status->freq = chan->center_freq;
+        }
+
+        switch (mac->status & AR9170_RX_STATUS_MODULATION) {
+        case AR9170_RX_STATUS_MODULATION_CCK:
+                if (mac->status & AR9170_RX_STATUS_SHORT_PREAMBLE)
+                        status->flag |= RX_FLAG_SHORTPRE;
+                switch (head->plcp[0]) {
+                case AR9170_RX_PHY_RATE_CCK_1M:
+                        status->rate_idx = 0;
+                        break;
+                case AR9170_RX_PHY_RATE_CCK_2M:
+                        status->rate_idx = 1;
+                        break;
+                case AR9170_RX_PHY_RATE_CCK_5M:
+                        status->rate_idx = 2;
+                        break;
+                case AR9170_RX_PHY_RATE_CCK_11M:
+                        status->rate_idx = 3;
+                        break;
+                default:
+                        if (net_ratelimit()) {
+                                wiphy_err(ar->hw->wiphy, "invalid plcp cck "
+                                       "rate (%x).\n", head->plcp[0]);
+                        }
+
+                        return -EINVAL;
+                }
+                break;
+
+        case AR9170_RX_STATUS_MODULATION_DUPOFDM:
+        case AR9170_RX_STATUS_MODULATION_OFDM:
+                switch (head->plcp[0] & 0xf) {
+                case AR9170_TXRX_PHY_RATE_OFDM_6M:
+                        status->rate_idx = 0;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_9M:
+                        status->rate_idx = 1;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_12M:
+                        status->rate_idx = 2;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_18M:
+                        status->rate_idx = 3;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_24M:
+                        status->rate_idx = 4;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_36M:
+                        status->rate_idx = 5;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_48M:
+                        status->rate_idx = 6;
+                        break;
+                case AR9170_TXRX_PHY_RATE_OFDM_54M:
+                        status->rate_idx = 7;
+                        break;
+                default:
+                        if (net_ratelimit()) {
+                                wiphy_err(ar->hw->wiphy, "invalid plcp ofdm "
+                                        "rate (%x).\n", head->plcp[0]);
+                        }
+
+                        return -EINVAL;
+                }
+                if (status->band == IEEE80211_BAND_2GHZ)
+                        status->rate_idx += 4;
+                break;
+
+        case AR9170_RX_STATUS_MODULATION_HT:
+                if (head->plcp[3] & 0x80)
+                        status->flag |= RX_FLAG_40MHZ;
+                if (head->plcp[6] & 0x80)
+                        status->flag |= RX_FLAG_SHORT_GI;
+
+                status->rate_idx = clamp(0, 75, head->plcp[3] & 0x7f);
+                status->flag |= RX_FLAG_HT;
+                break;
+
+        default:
+                BUG();
+                return -ENOSYS;
+        }
+
+        return 0;
+}
+
+static void carl9170_rx_phy_status(struct ar9170 *ar,
+        struct ar9170_rx_phystatus *phy, struct ieee80211_rx_status *status)
+{
+        int i;
+
+        BUILD_BUG_ON(sizeof(struct ar9170_rx_phystatus) != 20);
+
+        for (i = 0; i < 3; i++)
+                if (phy->rssi[i] != 0x80)
+                        status->antenna |= BIT(i);
+
+        /* post-process RSSI */
+        for (i = 0; i < 7; i++)
+                if (phy->rssi[i] & 0x80)
+                        phy->rssi[i] = ((phy->rssi[i] & 0x7f) + 1) & 0x7f;
+
+        /* TODO: we could do something with phy_errors */
+        status->signal = ar->noise[0] + phy->rssi_combined;
+}
+
+static struct sk_buff *carl9170_rx_copy_data(u8 *buf, int len)
+{
+        struct sk_buff *skb;
+        int reserved = 0;
+        struct ieee80211_hdr *hdr = (void *) buf;
+
+        if (ieee80211_is_data_qos(hdr->frame_control)) {
+                u8 *qc = ieee80211_get_qos_ctl(hdr);
+                reserved += NET_IP_ALIGN;
+
+                if (*qc & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
+                        reserved += NET_IP_ALIGN;
+        }
+
+        if (ieee80211_has_a4(hdr->frame_control))
+                reserved += NET_IP_ALIGN;
+
+        reserved = 32 + (reserved & NET_IP_ALIGN);
+
+        skb = dev_alloc_skb(len + reserved);
+        if (likely(skb)) {
+                skb_reserve(skb, reserved);
+                memcpy(skb_put(skb, len), buf, len);
+        }
+
+        return skb;
+}
+
+static u8 *carl9170_find_ie(u8 *data, unsigned int len, u8 ie)
+{
+        struct ieee80211_mgmt *mgmt = (void *)data;
+        u8 *pos, *end;
+
+        pos = (u8 *)mgmt->u.beacon.variable;
+        end = data + len;
+        while (pos < end) {
+                if (pos + 2 + pos[1] > end)
+                        return NULL;
+
+                if (pos[0] == ie)
+                        return pos;
+
+                pos += 2 + pos[1];
+        }
+        return NULL;
+}
+
+/*
+ * NOTE:
+ *
+ * The firmware is in charge of waking up the device just before
+ * the AP is expected to transmit the next beacon.
+ *
+ * This leaves the driver with the important task of deciding when
+ * to set the PHY back to bed again.
+ */
+static void carl9170_ps_beacon(struct ar9170 *ar, void *data, unsigned int len)
+{
+        struct ieee80211_hdr *hdr = (void *) data;
+        struct ieee80211_tim_ie *tim_ie;
+        u8 *tim;
+        u8 tim_len;
+        bool cam;
+
+        if (likely(!(ar->hw->conf.flags & IEEE80211_CONF_PS)))
+                return;
+
+        /* check if this really is a beacon */
+        if (!ieee80211_is_beacon(hdr->frame_control))
+                return;
+
+        /* min. beacon length + FCS_LEN */
+        if (len <= 40 + FCS_LEN)
+                return;
+
+        /* and only beacons from the associated BSSID, please */
+        if (compare_ether_addr(hdr->addr3, ar->common.curbssid) ||
+            !ar->common.curaid)
+                return;
+
+        ar->ps.last_beacon = jiffies;
+
+        tim = carl9170_find_ie(data, len - FCS_LEN, WLAN_EID_TIM);
+        if (!tim)
+                return;
+
+        if (tim[1] < sizeof(*tim_ie))
+                return;
+
+        tim_len = tim[1];
+        tim_ie = (struct ieee80211_tim_ie *) &tim[2];
+
+        if (!WARN_ON_ONCE(!ar->hw->conf.ps_dtim_period))
+                ar->ps.dtim_counter = (tim_ie->dtim_count - 1) %
+                        ar->hw->conf.ps_dtim_period;
+
+        /* Check whenever the PHY can be turned off again. */
+
+        /* 1. What about buffered unicast traffic for our AID? */
+        cam = ieee80211_check_tim(tim_ie, tim_len, ar->common.curaid);
+
+        /* 2. Maybe the AP wants to send multicast/broadcast data? */
+        cam |= !!(tim_ie->bitmap_ctrl & 0x01);
+
+        if (!cam) {
+                /* back to low-power land. */
+                ar->ps.off_override &= ~PS_OFF_BCN;
+                carl9170_ps_check(ar);
+        } else {
+                /* force CAM */
+                ar->ps.off_override |= PS_OFF_BCN;
+        }
+}
+
+static bool carl9170_ampdu_check(struct ar9170 *ar, u8 *buf, u8 ms)
+{
+        __le16 fc;
+
+        if ((ms & AR9170_RX_STATUS_MPDU) == AR9170_RX_STATUS_MPDU_SINGLE) {
+                /*
+                 * This frame is not part of an aMPDU.
+                 * Therefore it is not subjected to any
+                 * of the following content restrictions.
+                 */
+                return true;
+        }
+
+        /*
+         * "802.11n - 7.4a.3 A-MPDU contents" describes in which contexts
+         * certain frame types can be part of an aMPDU.
+         *
+         * In order to keep the processing cost down, I opted for a
+         * stateless filter solely based on the frame control field.
+         */
+
+        fc = ((struct ieee80211_hdr *)buf)->frame_control;
+        if (ieee80211_is_data_qos(fc) && ieee80211_is_data_present(fc))
+                return true;
+
+        if (ieee80211_is_ack(fc) || ieee80211_is_back(fc) ||
+            ieee80211_is_back_req(fc))
+                return true;
+
+        if (ieee80211_is_action(fc))
+                return true;
+
+        return false;
+}
+
+/*
+ * If the frame alignment is right (or the kernel has
+ * CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS), and there
+ * is only a single MPDU in the USB frame, then we could
+ * submit to mac80211 the SKB directly. However, since
+ * there may be multiple packets in one SKB in stream
+ * mode, and we need to observe the proper ordering,
+ * this is non-trivial.
+ */
+
+static void carl9170_handle_mpdu(struct ar9170 *ar, u8 *buf, int len)
+{
+        struct ar9170_rx_head *head;
+        struct ar9170_rx_macstatus *mac;
+        struct ar9170_rx_phystatus *phy = NULL;
+        struct ieee80211_rx_status status;
+        struct sk_buff *skb;
+        int mpdu_len;
+        u8 mac_status;
+
+        if (!IS_STARTED(ar))
+                return;
+
+        if (unlikely(len < sizeof(*mac)))
+                goto drop;
+
+        mpdu_len = len - sizeof(*mac);
+
+        mac = (void *)(buf + mpdu_len);
+        mac_status = mac->status;
+        switch (mac_status & AR9170_RX_STATUS_MPDU) {
+        case AR9170_RX_STATUS_MPDU_FIRST:
+                /* Aggregated MPDUs start with an PLCP header */
+                if (likely(mpdu_len >= sizeof(struct ar9170_rx_head))) {
+                        head = (void *) buf;
+
+                        /*
+                         * The PLCP header needs to be cached for the
+                         * following MIDDLE + LAST A-MPDU packets.
+                         *
+                         * So, if you are wondering why all frames seem
+                         * to share a common RX status information,
+                         * then you have the answer right here...
+                         */
+                        memcpy(&ar->rx_plcp, (void *) buf,
+                               sizeof(struct ar9170_rx_head));
+
+                        mpdu_len -= sizeof(struct ar9170_rx_head);
+                        buf += sizeof(struct ar9170_rx_head);
+
+                        ar->rx_has_plcp = true;
+                } else {
+                        if (net_ratelimit()) {
+                                wiphy_err(ar->hw->wiphy, "plcp info "
+                                        "is clipped.\n");
+                        }
+
+                        goto drop;
+                }
+                break;
+
+        case AR9170_RX_STATUS_MPDU_LAST:
+                /*
+                 * The last frame of an A-MPDU has an extra tail
+                 * which does contain the phy status of the whole
+                 * aggregate.
+                 */
+
+                if (likely(mpdu_len >= sizeof(struct ar9170_rx_phystatus))) {
+                        mpdu_len -= sizeof(struct ar9170_rx_phystatus);
+                        phy = (void *)(buf + mpdu_len);
+                } else {
+                        if (net_ratelimit()) {
+                                wiphy_err(ar->hw->wiphy, "frame tail "
+                                        "is clipped.\n");
+                        }
+
+                        goto drop;
+                }
+
+        case AR9170_RX_STATUS_MPDU_MIDDLE:
+                /*  These are just data + mac status */
+                if (unlikely(!ar->rx_has_plcp)) {
+                        if (!net_ratelimit())
+                                return;
+
+                        wiphy_err(ar->hw->wiphy, "rx stream does not start "
+                                        "with a first_mpdu frame tag.\n");
+
+                        goto drop;
+                }
+
+                head = &ar->rx_plcp;
+                break;
+
+        case AR9170_RX_STATUS_MPDU_SINGLE:
+                /* single mpdu has both: plcp (head) and phy status (tail) */
+                head = (void *) buf;
+
+                mpdu_len -= sizeof(struct ar9170_rx_head);
+                mpdu_len -= sizeof(struct ar9170_rx_phystatus);
+
+                buf += sizeof(struct ar9170_rx_head);
+                phy = (void *)(buf + mpdu_len);
+                break;
+
+        default:
+                BUG_ON(1);
+                break;
+        }
+
+        /* FC + DU + RA + FCS */
+        if (unlikely(mpdu_len < (2 + 2 + ETH_ALEN + FCS_LEN)))
+                goto drop;
+
+        memset(&status, 0, sizeof(status));
+        if (unlikely(carl9170_rx_mac_status(ar, head, mac, &status)))
+                goto drop;
+
+        if (!carl9170_ampdu_check(ar, buf, mac_status))
+                goto drop;
+
+        if (phy)
+                carl9170_rx_phy_status(ar, phy, &status);
+
+        carl9170_ps_beacon(ar, buf, mpdu_len);
+
+        skb = carl9170_rx_copy_data(buf, mpdu_len);
+        if (!skb)
+                goto drop;
+
+        memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
+        ieee80211_rx(ar->hw, skb);
+        return;
+
+drop:
+        ar->rx_dropped++;
+}
+
+static void carl9170_rx_untie_cmds(struct ar9170 *ar, const u8 *respbuf,
+                                   const unsigned int resplen)
+{
+        struct carl9170_rsp *cmd;
+        int i = 0;
+
+        while (i < resplen) {
+                cmd = (void *) &respbuf[i];
+
+                i += cmd->hdr.len + 4;
+                if (unlikely(i > resplen))
+                        break;
+
+                carl9170_handle_command_response(ar, cmd, cmd->hdr.len + 4);
+        }
+
+        if (unlikely(i != resplen)) {
+                if (!net_ratelimit())
+                        return;
+
+                wiphy_err(ar->hw->wiphy, "malformed firmware trap:\n");
+                print_hex_dump_bytes("rxcmd:", DUMP_PREFIX_OFFSET,
+                                     respbuf, resplen);
+        }
+}
+
+static void __carl9170_rx(struct ar9170 *ar, u8 *buf, unsigned int len)
+{
+        unsigned int i = 0;
+
+        /* weird thing, but this is the same in the original driver */
+        while (len > 2 && i < 12 && buf[0] == 0xff && buf[1] == 0xff) {
+                i += 2;
+                len -= 2;
+                buf += 2;
+        }
+
+        if (unlikely(len < 4))
+                return;
+
+        /* found the 6 * 0xffff marker? */
+        if (i == 12)
+                carl9170_rx_untie_cmds(ar, buf, len);
+        else
+                carl9170_handle_mpdu(ar, buf, len);
+}
+
+static void carl9170_rx_stream(struct ar9170 *ar, void *buf, unsigned int len)
+{
+        unsigned int tlen, wlen = 0, clen = 0;
+        struct ar9170_stream *rx_stream;
+        u8 *tbuf;
+
+        tbuf = buf;
+        tlen = len;
+
+        while (tlen >= 4) {
+                rx_stream = (void *) tbuf;
+                clen = le16_to_cpu(rx_stream->length);
+                wlen = ALIGN(clen, 4);
+
+                /* check if this is stream has a valid tag.*/
+                if (rx_stream->tag != cpu_to_le16(AR9170_RX_STREAM_TAG)) {
+                        /*
+                         * TODO: handle the highly unlikely event that the
+                         * corrupted stream has the TAG at the right position.
+                         */
+
+                        /* check if the frame can be repaired. */
+                        if (!ar->rx_failover_missing) {
+
+                                /* this is not "short read". */
+                                if (net_ratelimit()) {
+                                        wiphy_err(ar->hw->wiphy,
+                                                "missing tag!\n");
+                                }
+
+                                __carl9170_rx(ar, tbuf, tlen);
+                                return;
+                        }
+
+                        if (ar->rx_failover_missing > tlen) {
+                                if (net_ratelimit()) {
+                                        wiphy_err(ar->hw->wiphy,
+                                                "possible multi "
+                                                "stream corruption!\n");
+                                        goto err_telluser;
+                                } else {
+                                        goto err_silent;
+                                }
+                        }
+
+                        memcpy(skb_put(ar->rx_failover, tlen), tbuf, tlen);
+                        ar->rx_failover_missing -= tlen;
+
+                        if (ar->rx_failover_missing <= 0) {
+                                /*
+                                 * nested carl9170_rx_stream call!
+                                 *
+                                 * termination is guaranteed, even when the
+                                 * combined frame also have an element with
+                                 * a bad tag.
+                                 */
+
+                                ar->rx_failover_missing = 0;
+                                carl9170_rx_stream(ar, ar->rx_failover->data,
+                                                   ar->rx_failover->len);
+
+                                skb_reset_tail_pointer(ar->rx_failover);
+                                skb_trim(ar->rx_failover, 0);
+                        }
+
+                        return;
+                }
+
+                /* check if stream is clipped */
+                if (wlen > tlen - 4) {
+                        if (ar->rx_failover_missing) {
+                                /* TODO: handle double stream corruption. */
+                                if (net_ratelimit()) {
+                                        wiphy_err(ar->hw->wiphy, "double rx "
+                                                "stream corruption!\n");
+                                        goto err_telluser;
+                                } else {
+                                        goto err_silent;
+                                }
+                        }
+
+                        /*
+                         * save incomplete data set.
+                         * the firmware will resend the missing bits when
+                         * the rx - descriptor comes round again.
+                         */
+
+                        memcpy(skb_put(ar->rx_failover, tlen), tbuf, tlen);
+                        ar->rx_failover_missing = clen - tlen;
+                        return;
+                }
+                __carl9170_rx(ar, rx_stream->payload, clen);
+
+                tbuf += wlen + 4;
+                tlen -= wlen + 4;
+        }
+
+        if (tlen) {
+                if (net_ratelimit()) {
+                        wiphy_err(ar->hw->wiphy, "%d bytes of unprocessed "
+                                "data left in rx stream!\n", tlen);
+                }
+
+                goto err_telluser;
+        }
+
+        return;
+
+err_telluser:
+        wiphy_err(ar->hw->wiphy, "damaged RX stream data [want:%d, "
+                "data:%d, rx:%d, pending:%d ]\n", clen, wlen, tlen,
+                ar->rx_failover_missing);
+
+        if (ar->rx_failover_missing)
+                print_hex_dump_bytes("rxbuf:", DUMP_PREFIX_OFFSET,
+                                     ar->rx_failover->data,
+                                     ar->rx_failover->len);
+
+        print_hex_dump_bytes("stream:", DUMP_PREFIX_OFFSET,
+                             buf, len);
+
+        wiphy_err(ar->hw->wiphy, "please check your hardware and cables, if "
+                "you see this message frequently.\n");
+
+err_silent:
+        if (ar->rx_failover_missing) {
+                skb_reset_tail_pointer(ar->rx_failover);
+                skb_trim(ar->rx_failover, 0);
+                ar->rx_failover_missing = 0;
+        }
+}
+
+void carl9170_rx(struct ar9170 *ar, void *buf, unsigned int len)
+{
+        if (ar->fw.rx_stream)
+                carl9170_rx_stream(ar, buf, len);
+        else
+                __carl9170_rx(ar, buf, len);
+}
diff --git a/drivers/net/wireless/ath/carl9170/tx.c b/drivers/net/wireless/ath/carl9170/tx.c
new file mode 100644
index 000000000000..e94084fcf6f5
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/tx.c
@@ -0,0 +1,1440 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * 802.11 xmit & status routines
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <net/mac80211.h>
+#include "carl9170.h"
+#include "hw.h"
+#include "cmd.h"
+
+static inline unsigned int __carl9170_get_queue(struct ar9170 *ar,
+                                                unsigned int queue)
+{
+        if (unlikely(modparam_noht)) {
+                return queue;
+        } else {
+                /*
+                 * This is just another workaround, until
+                 * someone figures out how to get QoS and
+                 * AMPDU to play nicely together.
+                 */
+
+                return 2;               /* AC_BE */
+        }
+}
+
+static inline unsigned int carl9170_get_queue(struct ar9170 *ar,
+                                              struct sk_buff *skb)
+{
+        return __carl9170_get_queue(ar, skb_get_queue_mapping(skb));
+}
+
+static bool is_mem_full(struct ar9170 *ar)
+{
+        return (DIV_ROUND_UP(IEEE80211_MAX_FRAME_LEN, ar->fw.mem_block_size) >
+                atomic_read(&ar->mem_free_blocks));
+}
+
+static void carl9170_tx_accounting(struct ar9170 *ar, struct sk_buff *skb)
+{
+        int queue, i;
+        bool mem_full;
+
+        atomic_inc(&ar->tx_total_queued);
+
+        queue = skb_get_queue_mapping(skb);
+        spin_lock_bh(&ar->tx_stats_lock);
+
+        /*
+         * The driver has to accept the frame, regardless if the queue is
+         * full to the brim, or not. We have to do the queuing internally,
+         * since mac80211 assumes that a driver which can operate with
+         * aggregated frames does not reject frames for this reason.
+         */
+        ar->tx_stats[queue].len++;
+        ar->tx_stats[queue].count++;
+
+        mem_full = is_mem_full(ar);
+        for (i = 0; i < ar->hw->queues; i++) {
+                if (mem_full || ar->tx_stats[i].len >= ar->tx_stats[i].limit) {
+                        ieee80211_stop_queue(ar->hw, i);
+                        ar->queue_stop_timeout[i] = jiffies;
+                }
+        }
+
+        spin_unlock_bh(&ar->tx_stats_lock);
+}
+
+/* needs rcu_read_lock */
+static struct ieee80211_sta *__carl9170_get_tx_sta(struct ar9170 *ar,
+                                                   struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super = (void *) skb->data;
+        struct ieee80211_hdr *hdr = (void *) super->frame_data;
+        struct ieee80211_vif *vif;
+        unsigned int vif_id;
+
+        vif_id = (super->s.misc & CARL9170_TX_SUPER_MISC_VIF_ID) >>
+                 CARL9170_TX_SUPER_MISC_VIF_ID_S;
+
+        if (WARN_ON_ONCE(vif_id >= AR9170_MAX_VIRTUAL_MAC))
+                return NULL;
+
+        vif = rcu_dereference(ar->vif_priv[vif_id].vif);
+        if (unlikely(!vif))
+                return NULL;
+
+        /*
+         * Normally we should use wrappers like ieee80211_get_DA to get
+         * the correct peer ieee80211_sta.
+         *
+         * But there is a problem with indirect traffic (broadcasts, or
+         * data which is designated for other stations) in station mode.
+         * The frame will be directed to the AP for distribution and not
+         * to the actual destination.
+         */
+
+        return ieee80211_find_sta(vif, hdr->addr1);
+}
+
+static void carl9170_tx_ps_unblock(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct ieee80211_sta *sta;
+        struct carl9170_sta_info *sta_info;
+
+        rcu_read_lock();
+        sta = __carl9170_get_tx_sta(ar, skb);
+        if (unlikely(!sta))
+                goto out_rcu;
+
+        sta_info = (struct carl9170_sta_info *) sta->drv_priv;
+        if (atomic_dec_return(&sta_info->pending_frames) == 0)
+                ieee80211_sta_block_awake(ar->hw, sta, false);
+
+out_rcu:
+        rcu_read_unlock();
+}
+
+static void carl9170_tx_accounting_free(struct ar9170 *ar, struct sk_buff *skb)
+{
+        int queue;
+
+        queue = skb_get_queue_mapping(skb);
+
+        spin_lock_bh(&ar->tx_stats_lock);
+
+        ar->tx_stats[queue].len--;
+
+        if (!is_mem_full(ar)) {
+                unsigned int i;
+                for (i = 0; i < ar->hw->queues; i++) {
+                        if (ar->tx_stats[i].len >= CARL9170_NUM_TX_LIMIT_SOFT)
+                                continue;
+
+                        if (ieee80211_queue_stopped(ar->hw, i)) {
+                                unsigned long tmp;
+
+                                tmp = jiffies - ar->queue_stop_timeout[i];
+                                if (tmp > ar->max_queue_stop_timeout[i])
+                                        ar->max_queue_stop_timeout[i] = tmp;
+                        }
+
+                        ieee80211_wake_queue(ar->hw, i);
+                }
+        }
+
+        spin_unlock_bh(&ar->tx_stats_lock);
+
+        if (atomic_dec_and_test(&ar->tx_total_queued))
+                complete(&ar->tx_flush);
+}
+
+static int carl9170_alloc_dev_space(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super = (void *) skb->data;
+        unsigned int chunks;
+        int cookie = -1;
+
+        atomic_inc(&ar->mem_allocs);
+
+        chunks = DIV_ROUND_UP(skb->len, ar->fw.mem_block_size);
+        if (unlikely(atomic_sub_return(chunks, &ar->mem_free_blocks) < 0)) {
+                atomic_add(chunks, &ar->mem_free_blocks);
+                return -ENOSPC;
+        }
+
+        spin_lock_bh(&ar->mem_lock);
+        cookie = bitmap_find_free_region(ar->mem_bitmap, ar->fw.mem_blocks, 0);
+        spin_unlock_bh(&ar->mem_lock);
+
+        if (unlikely(cookie < 0)) {
+                atomic_add(chunks, &ar->mem_free_blocks);
+                return -ENOSPC;
+        }
+
+        super = (void *) skb->data;
+
+        /*
+         * Cookie #0 serves two special purposes:
+         *  1. The firmware might use it generate BlockACK frames
+         *     in responds of an incoming BlockAckReqs.
+         *
+         *  2. Prevent double-free bugs.
+         */
+        super->s.cookie = (u8) cookie + 1;
+        return 0;
+}
+
+static void carl9170_release_dev_space(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super = (void *) skb->data;
+        int cookie;
+
+        /* make a local copy of the cookie */
+        cookie = super->s.cookie;
+        /* invalidate cookie */
+        super->s.cookie = 0;
+
+        /*
+         * Do a out-of-bounds check on the cookie:
+         *
+         *  * cookie "0" is reserved and won't be assigned to any
+         *    out-going frame. Internally however, it is used to
+         *    mark no longer/un-accounted frames and serves as a
+         *    cheap way of preventing frames from being freed
+         *    twice by _accident_. NB: There is a tiny race...
+         *
+         *  * obviously, cookie number is limited by the amount
+         *    of available memory blocks, so the number can
+         *    never execeed the mem_blocks count.
+         */
+        if (unlikely(WARN_ON_ONCE(cookie == 0) ||
+            WARN_ON_ONCE(cookie > ar->fw.mem_blocks)))
+                return;
+
+        atomic_add(DIV_ROUND_UP(skb->len, ar->fw.mem_block_size),
+                   &ar->mem_free_blocks);
+
+        spin_lock_bh(&ar->mem_lock);
+        bitmap_release_region(ar->mem_bitmap, cookie - 1, 0);
+        spin_unlock_bh(&ar->mem_lock);
+}
+
+/* Called from any context */
+static void carl9170_tx_release(struct kref *ref)
+{
+        struct ar9170 *ar;
+        struct carl9170_tx_info *arinfo;
+        struct ieee80211_tx_info *txinfo;
+        struct sk_buff *skb;
+
+        arinfo = container_of(ref, struct carl9170_tx_info, ref);
+        txinfo = container_of((void *) arinfo, struct ieee80211_tx_info,
+                              rate_driver_data);
+        skb = container_of((void *) txinfo, struct sk_buff, cb);
+
+        ar = arinfo->ar;
+        if (WARN_ON_ONCE(!ar))
+                return;
+
+        BUILD_BUG_ON(
+            offsetof(struct ieee80211_tx_info, status.ampdu_ack_len) != 23);
+
+        memset(&txinfo->status.ampdu_ack_len, 0,
+               sizeof(struct ieee80211_tx_info) -
+               offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
+
+        if (atomic_read(&ar->tx_total_queued))
+                ar->tx_schedule = true;
+
+        if (txinfo->flags & IEEE80211_TX_CTL_AMPDU) {
+                if (!atomic_read(&ar->tx_ampdu_upload))
+                        ar->tx_ampdu_schedule = true;
+
+                if (txinfo->flags & IEEE80211_TX_STAT_AMPDU) {
+                        struct _carl9170_tx_superframe *super;
+
+                        super = (void *)skb->data;
+                        txinfo->status.ampdu_len = super->s.rix;
+                        txinfo->status.ampdu_ack_len = super->s.cnt;
+                } else if (txinfo->flags & IEEE80211_TX_STAT_ACK) {
+                        /*
+                         * drop redundant tx_status reports:
+                         *
+                         * 1. ampdu_ack_len of the final tx_status does
+                         *    include the feedback of this particular frame.
+                         *
+                         * 2. tx_status_irqsafe only queues up to 128
+                         *    tx feedback reports and discards the rest.
+                         *
+                         * 3. minstrel_ht is picky, it only accepts
+                         *    reports of frames with the TX_STATUS_AMPDU flag.
+                         */
+
+                        dev_kfree_skb_any(skb);
+                        return;
+                } else {
+                        /*
+                         * Frame has failed, but we want to keep it in
+                         * case it was lost due to a power-state
+                         * transition.
+                         */
+                }
+        }
+
+        skb_pull(skb, sizeof(struct _carl9170_tx_superframe));
+        ieee80211_tx_status_irqsafe(ar->hw, skb);
+}
+
+void carl9170_tx_get_skb(struct sk_buff *skb)
+{
+        struct carl9170_tx_info *arinfo = (void *)
+                (IEEE80211_SKB_CB(skb))->rate_driver_data;
+        kref_get(&arinfo->ref);
+}
+
+int carl9170_tx_put_skb(struct sk_buff *skb)
+{
+        struct carl9170_tx_info *arinfo = (void *)
+                (IEEE80211_SKB_CB(skb))->rate_driver_data;
+
+        return kref_put(&arinfo->ref, carl9170_tx_release);
+}
+
+/* Caller must hold the tid_info->lock & rcu_read_lock */
+static void carl9170_tx_shift_bm(struct ar9170 *ar,
+        struct carl9170_sta_tid *tid_info, u16 seq)
+{
+        u16 off;
+
+        off = SEQ_DIFF(seq, tid_info->bsn);
+
+        if (WARN_ON_ONCE(off >= CARL9170_BAW_BITS))
+                return;
+
+        /*
+         * Sanity check. For each MPDU we set the bit in bitmap and
+         * clear it once we received the tx_status.
+         * But if the bit is already cleared then we've been bitten
+         * by a bug.
+         */
+        WARN_ON_ONCE(!test_and_clear_bit(off, tid_info->bitmap));
+
+        off = SEQ_DIFF(tid_info->snx, tid_info->bsn);
+        if (WARN_ON_ONCE(off >= CARL9170_BAW_BITS))
+                return;
+
+        if (!bitmap_empty(tid_info->bitmap, off))
+                off = find_first_bit(tid_info->bitmap, off);
+
+        tid_info->bsn += off;
+        tid_info->bsn &= 0x0fff;
+
+        bitmap_shift_right(tid_info->bitmap, tid_info->bitmap,
+                           off, CARL9170_BAW_BITS);
+}
+
+static void carl9170_tx_status_process_ampdu(struct ar9170 *ar,
+        struct sk_buff *skb, struct ieee80211_tx_info *txinfo)
+{
+        struct _carl9170_tx_superframe *super = (void *) skb->data;
+        struct ieee80211_hdr *hdr = (void *) super->frame_data;
+        struct ieee80211_sta *sta;
+        struct carl9170_sta_info *sta_info;
+        struct carl9170_sta_tid *tid_info;
+        u8 tid;
+
+        if (!(txinfo->flags & IEEE80211_TX_CTL_AMPDU) ||
+            txinfo->flags & IEEE80211_TX_CTL_INJECTED ||
+           (!(super->f.mac_control & cpu_to_le16(AR9170_TX_MAC_AGGR))))
+                return;
+
+        rcu_read_lock();
+        sta = __carl9170_get_tx_sta(ar, skb);
+        if (unlikely(!sta))
+                goto out_rcu;
+
+        tid = get_tid_h(hdr);
+
+        sta_info = (void *) sta->drv_priv;
+        tid_info = rcu_dereference(sta_info->agg[tid]);
+        if (!tid_info)
+                goto out_rcu;
+
+        spin_lock_bh(&tid_info->lock);
+        if (likely(tid_info->state >= CARL9170_TID_STATE_IDLE))
+                carl9170_tx_shift_bm(ar, tid_info, get_seq_h(hdr));
+
+        if (sta_info->stats[tid].clear) {
+                sta_info->stats[tid].clear = false;
+                sta_info->stats[tid].req = false;
+                sta_info->stats[tid].ampdu_len = 0;
+                sta_info->stats[tid].ampdu_ack_len = 0;
+        }
+
+        sta_info->stats[tid].ampdu_len++;
+        if (txinfo->status.rates[0].count == 1)
+                sta_info->stats[tid].ampdu_ack_len++;
+
+        if (!(txinfo->flags & IEEE80211_TX_STAT_ACK))
+                sta_info->stats[tid].req = true;
+
+        if (super->f.mac_control & cpu_to_le16(AR9170_TX_MAC_IMM_BA)) {
+                super->s.rix = sta_info->stats[tid].ampdu_len;
+                super->s.cnt = sta_info->stats[tid].ampdu_ack_len;
+                txinfo->flags |= IEEE80211_TX_STAT_AMPDU;
+                if (sta_info->stats[tid].req)
+                        txinfo->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
+
+                sta_info->stats[tid].clear = true;
+        }
+        spin_unlock_bh(&tid_info->lock);
+
+out_rcu:
+        rcu_read_unlock();
+}
+
+void carl9170_tx_status(struct ar9170 *ar, struct sk_buff *skb,
+                        const bool success)
+{
+        struct ieee80211_tx_info *txinfo;
+
+        carl9170_tx_accounting_free(ar, skb);
+
+        txinfo = IEEE80211_SKB_CB(skb);
+
+        if (success)
+                txinfo->flags |= IEEE80211_TX_STAT_ACK;
+        else
+                ar->tx_ack_failures++;
+
+        if (txinfo->flags & IEEE80211_TX_CTL_AMPDU)
+                carl9170_tx_status_process_ampdu(ar, skb, txinfo);
+
+        carl9170_tx_ps_unblock(ar, skb);
+        carl9170_tx_put_skb(skb);
+}
+
+/* This function may be called form any context */
+void carl9170_tx_callback(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct ieee80211_tx_info *txinfo = IEEE80211_SKB_CB(skb);
+
+        atomic_dec(&ar->tx_total_pending);
+
+        if (txinfo->flags & IEEE80211_TX_CTL_AMPDU)
+                atomic_dec(&ar->tx_ampdu_upload);
+
+        if (carl9170_tx_put_skb(skb))
+                tasklet_hi_schedule(&ar->usb_tasklet);
+}
+
+static struct sk_buff *carl9170_get_queued_skb(struct ar9170 *ar, u8 cookie,
+                                               struct sk_buff_head *queue)
+{
+        struct sk_buff *skb;
+
+        spin_lock_bh(&queue->lock);
+        skb_queue_walk(queue, skb) {
+                struct _carl9170_tx_superframe *txc = (void *) skb->data;
+
+                if (txc->s.cookie != cookie)
+                        continue;
+
+                __skb_unlink(skb, queue);
+                spin_unlock_bh(&queue->lock);
+
+                carl9170_release_dev_space(ar, skb);
+                return skb;
+        }
+        spin_unlock_bh(&queue->lock);
+
+        return NULL;
+}
+
+static void carl9170_tx_fill_rateinfo(struct ar9170 *ar, unsigned int rix,
+        unsigned int tries, struct ieee80211_tx_info *txinfo)
+{
+        unsigned int i;
+
+        for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
+                if (txinfo->status.rates[i].idx < 0)
+                        break;
+
+                if (i == rix) {
+                        txinfo->status.rates[i].count = tries;
+                        i++;
+                        break;
+                }
+        }
+
+        for (; i < IEEE80211_TX_MAX_RATES; i++) {
+                txinfo->status.rates[i].idx = -1;
+                txinfo->status.rates[i].count = 0;
+        }
+}
+
+static void carl9170_check_queue_stop_timeout(struct ar9170 *ar)
+{
+        int i;
+        struct sk_buff *skb;
+        struct ieee80211_tx_info *txinfo;
+        struct carl9170_tx_info *arinfo;
+        bool restart = false;
+
+        for (i = 0; i < ar->hw->queues; i++) {
+                spin_lock_bh(&ar->tx_status[i].lock);
+
+                skb = skb_peek(&ar->tx_status[i]);
+
+                if (!skb)
+                        goto next;
+
+                txinfo = IEEE80211_SKB_CB(skb);
+                arinfo = (void *) txinfo->rate_driver_data;
+
+                if (time_is_before_jiffies(arinfo->timeout +
+                    msecs_to_jiffies(CARL9170_QUEUE_STUCK_TIMEOUT)) == true)
+                        restart = true;
+
+next:
+                spin_unlock_bh(&ar->tx_status[i].lock);
+        }
+
+        if (restart) {
+                /*
+                 * At least one queue has been stuck for long enough.
+                 * Give the device a kick and hope it gets back to
+                 * work.
+                 *
+                 * possible reasons may include:
+                 *  - frames got lost/corrupted (bad connection to the device)
+                 *  - stalled rx processing/usb controller hiccups
+                 *  - firmware errors/bugs
+                 *  - every bug you can think of.
+                 *  - all bugs you can't...
+                 *  - ...
+                 */
+                carl9170_restart(ar, CARL9170_RR_STUCK_TX);
+        }
+}
+
+static void carl9170_tx_ampdu_timeout(struct ar9170 *ar)
+{
+        struct carl9170_sta_tid *iter;
+        struct sk_buff *skb;
+        struct ieee80211_tx_info *txinfo;
+        struct carl9170_tx_info *arinfo;
+        struct ieee80211_sta *sta;
+
+        rcu_read_lock();
+        list_for_each_entry_rcu(iter, &ar->tx_ampdu_list, list) {
+                if (iter->state < CARL9170_TID_STATE_IDLE)
+                        continue;
+
+                spin_lock_bh(&iter->lock);
+                skb = skb_peek(&iter->queue);
+                if (!skb)
+                        goto unlock;
+
+                txinfo = IEEE80211_SKB_CB(skb);
+                arinfo = (void *)txinfo->rate_driver_data;
+                if (time_is_after_jiffies(arinfo->timeout +
+                    msecs_to_jiffies(CARL9170_QUEUE_TIMEOUT)))
+                        goto unlock;
+
+                sta = __carl9170_get_tx_sta(ar, skb);
+                if (WARN_ON(!sta))
+                        goto unlock;
+
+                ieee80211_stop_tx_ba_session(sta, iter->tid);
+unlock:
+                spin_unlock_bh(&iter->lock);
+
+        }
+        rcu_read_unlock();
+}
+
+void carl9170_tx_janitor(struct work_struct *work)
+{
+        struct ar9170 *ar = container_of(work, struct ar9170,
+                                         tx_janitor.work);
+        if (!IS_STARTED(ar))
+                return;
+
+        ar->tx_janitor_last_run = jiffies;
+
+        carl9170_check_queue_stop_timeout(ar);
+        carl9170_tx_ampdu_timeout(ar);
+
+        if (!atomic_read(&ar->tx_total_queued))
+                return;
+
+        ieee80211_queue_delayed_work(ar->hw, &ar->tx_janitor,
+                msecs_to_jiffies(CARL9170_TX_TIMEOUT));
+}
+
+static void __carl9170_tx_process_status(struct ar9170 *ar,
+        const uint8_t cookie, const uint8_t info)
+{
+        struct sk_buff *skb;
+        struct ieee80211_tx_info *txinfo;
+        unsigned int r, t, q;
+        bool success = true;
+
+        q = ar9170_qmap[info & CARL9170_TX_STATUS_QUEUE];
+
+        skb = carl9170_get_queued_skb(ar, cookie, &ar->tx_status[q]);
+        if (!skb) {
+                /*
+                 * We have lost the race to another thread.
+                 */
+
+                return ;
+        }
+
+        txinfo = IEEE80211_SKB_CB(skb);
+
+        if (!(info & CARL9170_TX_STATUS_SUCCESS))
+                success = false;
+
+        r = (info & CARL9170_TX_STATUS_RIX) >> CARL9170_TX_STATUS_RIX_S;
+        t = (info & CARL9170_TX_STATUS_TRIES) >> CARL9170_TX_STATUS_TRIES_S;
+
+        carl9170_tx_fill_rateinfo(ar, r, t, txinfo);
+        carl9170_tx_status(ar, skb, success);
+}
+
+void carl9170_tx_process_status(struct ar9170 *ar,
+                                const struct carl9170_rsp *cmd)
+{
+        unsigned int i;
+
+        for (i = 0;  i < cmd->hdr.ext; i++) {
+                if (WARN_ON(i > ((cmd->hdr.len / 2) + 1))) {
+                        print_hex_dump_bytes("UU:", DUMP_PREFIX_NONE,
+                                             (void *) cmd, cmd->hdr.len + 4);
+                        break;
+                }
+
+                __carl9170_tx_process_status(ar, cmd->_tx_status[i].cookie,
+                                             cmd->_tx_status[i].info);
+        }
+}
+
+static __le32 carl9170_tx_physet(struct ar9170 *ar,
+        struct ieee80211_tx_info *info, struct ieee80211_tx_rate *txrate)
+{
+        struct ieee80211_rate *rate = NULL;
+        u32 power, chains;
+        __le32 tmp;
+
+        tmp = cpu_to_le32(0);
+
+        if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
+                tmp |= cpu_to_le32(AR9170_TX_PHY_BW_40MHZ <<
+                        AR9170_TX_PHY_BW_S);
+        /* this works because 40 MHz is 2 and dup is 3 */
+        if (txrate->flags & IEEE80211_TX_RC_DUP_DATA)
+                tmp |= cpu_to_le32(AR9170_TX_PHY_BW_40MHZ_DUP <<
+                        AR9170_TX_PHY_BW_S);
+
+        if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
+                tmp |= cpu_to_le32(AR9170_TX_PHY_SHORT_GI);
+
+        if (txrate->flags & IEEE80211_TX_RC_MCS) {
+                u32 r = txrate->idx;
+                u8 *txpower;
+
+                /* heavy clip control */
+                tmp |= cpu_to_le32((r & 0x7) <<
+                        AR9170_TX_PHY_TX_HEAVY_CLIP_S);
+
+                if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
+                        if (info->band == IEEE80211_BAND_5GHZ)
+                                txpower = ar->power_5G_ht40;
+                        else
+                                txpower = ar->power_2G_ht40;
+                } else {
+                        if (info->band == IEEE80211_BAND_5GHZ)
+                                txpower = ar->power_5G_ht20;
+                        else
+                                txpower = ar->power_2G_ht20;
+                }
+
+                power = txpower[r & 7];
+
+                /* +1 dBm for HT40 */
+                if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
+                        power += 2;
+
+                r <<= AR9170_TX_PHY_MCS_S;
+                BUG_ON(r & ~AR9170_TX_PHY_MCS);
+
+                tmp |= cpu_to_le32(r & AR9170_TX_PHY_MCS);
+                tmp |= cpu_to_le32(AR9170_TX_PHY_MOD_HT);
+
+                /*
+                 * green field preamble does not work.
+                 *
+                 * if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
+                 * tmp |= cpu_to_le32(AR9170_TX_PHY_GREENFIELD);
+                 */
+        } else {
+                u8 *txpower;
+                u32 mod;
+                u32 phyrate;
+                u8 idx = txrate->idx;
+
+                if (info->band != IEEE80211_BAND_2GHZ) {
+                        idx += 4;
+                        txpower = ar->power_5G_leg;
+                        mod = AR9170_TX_PHY_MOD_OFDM;
+                } else {
+                        if (idx < 4) {
+                                txpower = ar->power_2G_cck;
+                                mod = AR9170_TX_PHY_MOD_CCK;
+                        } else {
+                                mod = AR9170_TX_PHY_MOD_OFDM;
+                                txpower = ar->power_2G_ofdm;
+                        }
+                }
+
+                rate = &__carl9170_ratetable[idx];
+
+                phyrate = rate->hw_value & 0xF;
+                power = txpower[(rate->hw_value & 0x30) >> 4];
+                phyrate <<= AR9170_TX_PHY_MCS_S;
+
+                tmp |= cpu_to_le32(mod);
+                tmp |= cpu_to_le32(phyrate);
+
+                /*
+                 * short preamble seems to be broken too.
+                 *
+                 * if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
+                 *      tmp |= cpu_to_le32(AR9170_TX_PHY_SHORT_PREAMBLE);
+                 */
+        }
+        power <<= AR9170_TX_PHY_TX_PWR_S;
+        power &= AR9170_TX_PHY_TX_PWR;
+        tmp |= cpu_to_le32(power);
+
+        /* set TX chains */
+        if (ar->eeprom.tx_mask == 1) {
+                chains = AR9170_TX_PHY_TXCHAIN_1;
+        } else {
+                chains = AR9170_TX_PHY_TXCHAIN_2;
+
+                /* >= 36M legacy OFDM - use only one chain */
+                if (rate && rate->bitrate >= 360 &&
+                    !(txrate->flags & IEEE80211_TX_RC_MCS))
+                        chains = AR9170_TX_PHY_TXCHAIN_1;
+        }
+        tmp |= cpu_to_le32(chains << AR9170_TX_PHY_TXCHAIN_S);
+
+        return tmp;
+}
+
+static bool carl9170_tx_rts_check(struct ar9170 *ar,
+                                  struct ieee80211_tx_rate *rate,
+                                  bool ampdu, bool multi)
+{
+        switch (ar->erp_mode) {
+        case CARL9170_ERP_AUTO:
+                if (ampdu)
+                        break;
+
+        case CARL9170_ERP_MAC80211:
+                if (!(rate->flags & IEEE80211_TX_RC_USE_RTS_CTS))
+                        break;
+
+        case CARL9170_ERP_RTS:
+                if (likely(!multi))
+                        return true;
+
+        default:
+                break;
+        }
+
+        return false;
+}
+
+static bool carl9170_tx_cts_check(struct ar9170 *ar,
+                                  struct ieee80211_tx_rate *rate)
+{
+        switch (ar->erp_mode) {
+        case CARL9170_ERP_AUTO:
+        case CARL9170_ERP_MAC80211:
+                if (!(rate->flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
+                        break;
+
+        case CARL9170_ERP_CTS:
+                return true;
+
+        default:
+                break;
+        }
+
+        return false;
+}
+
+static int carl9170_tx_prepare(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct ieee80211_hdr *hdr;
+        struct _carl9170_tx_superframe *txc;
+        struct carl9170_vif_info *cvif;
+        struct ieee80211_tx_info *info;
+        struct ieee80211_tx_rate *txrate;
+        struct ieee80211_sta *sta;
+        struct carl9170_tx_info *arinfo;
+        unsigned int hw_queue;
+        int i;
+        __le16 mac_tmp;
+        u16 len;
+        bool ampdu, no_ack;
+
+        BUILD_BUG_ON(sizeof(*arinfo) > sizeof(info->rate_driver_data));
+        BUILD_BUG_ON(sizeof(struct _carl9170_tx_superdesc) !=
+                     CARL9170_TX_SUPERDESC_LEN);
+
+        BUILD_BUG_ON(sizeof(struct _ar9170_tx_hwdesc) !=
+                     AR9170_TX_HWDESC_LEN);
+
+        BUILD_BUG_ON(IEEE80211_TX_MAX_RATES < CARL9170_TX_MAX_RATES);
+
+        BUILD_BUG_ON(AR9170_MAX_VIRTUAL_MAC >
+                ((CARL9170_TX_SUPER_MISC_VIF_ID >>
+                 CARL9170_TX_SUPER_MISC_VIF_ID_S) + 1));
+
+        hw_queue = ar9170_qmap[carl9170_get_queue(ar, skb)];
+
+        hdr = (void *)skb->data;
+        info = IEEE80211_SKB_CB(skb);
+        len = skb->len;
+
+        /*
+         * Note: If the frame was sent through a monitor interface,
+         * the ieee80211_vif pointer can be NULL.
+         */
+        if (likely(info->control.vif))
+                cvif = (void *) info->control.vif->drv_priv;
+        else
+                cvif = NULL;
+
+        sta = info->control.sta;
+
+        txc = (void *)skb_push(skb, sizeof(*txc));
+        memset(txc, 0, sizeof(*txc));
+
+        SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, txc->s.misc, hw_queue);
+
+        if (likely(cvif))
+                SET_VAL(CARL9170_TX_SUPER_MISC_VIF_ID, txc->s.misc, cvif->id);
+
+        if (unlikely(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM))
+                txc->s.misc |= CARL9170_TX_SUPER_MISC_CAB;
+
+        if (unlikely(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
+                txc->s.misc |= CARL9170_TX_SUPER_MISC_ASSIGN_SEQ;
+
+        if (unlikely(ieee80211_is_probe_resp(hdr->frame_control)))
+                txc->s.misc |= CARL9170_TX_SUPER_MISC_FILL_IN_TSF;
+
+        mac_tmp = cpu_to_le16(AR9170_TX_MAC_HW_DURATION |
+                              AR9170_TX_MAC_BACKOFF);
+        mac_tmp |= cpu_to_le16((hw_queue << AR9170_TX_MAC_QOS_S) &
+                               AR9170_TX_MAC_QOS);
+
+        no_ack = !!(info->flags & IEEE80211_TX_CTL_NO_ACK);
+        if (unlikely(no_ack))
+                mac_tmp |= cpu_to_le16(AR9170_TX_MAC_NO_ACK);
+
+        if (info->control.hw_key) {
+                len += info->control.hw_key->icv_len;
+
+                switch (info->control.hw_key->cipher) {
+                case WLAN_CIPHER_SUITE_WEP40:
+                case WLAN_CIPHER_SUITE_WEP104:
+                case WLAN_CIPHER_SUITE_TKIP:
+                        mac_tmp |= cpu_to_le16(AR9170_TX_MAC_ENCR_RC4);
+                        break;
+                case WLAN_CIPHER_SUITE_CCMP:
+                        mac_tmp |= cpu_to_le16(AR9170_TX_MAC_ENCR_AES);
+                        break;
+                default:
+                        WARN_ON(1);
+                        goto err_out;
+                }
+        }
+
+        ampdu = !!(info->flags & IEEE80211_TX_CTL_AMPDU);
+        if (ampdu) {
+                unsigned int density, factor;
+
+                if (unlikely(!sta || !cvif))
+                        goto err_out;
+
+                factor = min_t(unsigned int, 1u, sta->ht_cap.ampdu_factor);
+                density = sta->ht_cap.ampdu_density;
+
+                if (density) {
+                        /*
+                         * Watch out!
+                         *
+                         * Otus uses slightly different density values than
+                         * those from the 802.11n spec.
+                         */
+
+                        density = max_t(unsigned int, density + 1, 7u);
+                }
+
+                SET_VAL(CARL9170_TX_SUPER_AMPDU_DENSITY,
+                        txc->s.ampdu_settings, density);
+
+                SET_VAL(CARL9170_TX_SUPER_AMPDU_FACTOR,
+                        txc->s.ampdu_settings, factor);
+
+                for (i = 0; i < CARL9170_TX_MAX_RATES; i++) {
+                        txrate = &info->control.rates[i];
+                        if (txrate->idx >= 0) {
+                                txc->s.ri[i] =
+                                        CARL9170_TX_SUPER_RI_AMPDU;
+
+                                if (WARN_ON(!(txrate->flags &
+                                              IEEE80211_TX_RC_MCS))) {
+                                        /*
+                                         * Not sure if it's even possible
+                                         * to aggregate non-ht rates with
+                                         * this HW.
+                                         */
+                                        goto err_out;
+                                }
+                                continue;
+                        }
+
+                        txrate->idx = 0;
+                        txrate->count = ar->hw->max_rate_tries;
+                }
+
+                mac_tmp |= cpu_to_le16(AR9170_TX_MAC_AGGR);
+        }
+
+        /*
+         * NOTE: For the first rate, the ERP & AMPDU flags are directly
+         * taken from mac_control. For all fallback rate, the firmware
+         * updates the mac_control flags from the rate info field.
+         */
+        for (i = 1; i < CARL9170_TX_MAX_RATES; i++) {
+                txrate = &info->control.rates[i];
+                if (txrate->idx < 0)
+                        break;
+
+                SET_VAL(CARL9170_TX_SUPER_RI_TRIES, txc->s.ri[i],
+                        txrate->count);
+
+                if (carl9170_tx_rts_check(ar, txrate, ampdu, no_ack))
+                        txc->s.ri[i] |= (AR9170_TX_MAC_PROT_RTS <<
+                                CARL9170_TX_SUPER_RI_ERP_PROT_S);
+                else if (carl9170_tx_cts_check(ar, txrate))
+                        txc->s.ri[i] |= (AR9170_TX_MAC_PROT_CTS <<
+                                CARL9170_TX_SUPER_RI_ERP_PROT_S);
+
+                txc->s.rr[i - 1] = carl9170_tx_physet(ar, info, txrate);
+        }
+
+        txrate = &info->control.rates[0];
+        SET_VAL(CARL9170_TX_SUPER_RI_TRIES, txc->s.ri[0], txrate->count);
+
+        if (carl9170_tx_rts_check(ar, txrate, ampdu, no_ack))
+                mac_tmp |= cpu_to_le16(AR9170_TX_MAC_PROT_RTS);
+        else if (carl9170_tx_cts_check(ar, txrate))
+                mac_tmp |= cpu_to_le16(AR9170_TX_MAC_PROT_CTS);
+
+        txc->s.len = cpu_to_le16(skb->len);
+        txc->f.length = cpu_to_le16(len + FCS_LEN);
+        txc->f.mac_control = mac_tmp;
+        txc->f.phy_control = carl9170_tx_physet(ar, info, txrate);
+
+        arinfo = (void *)info->rate_driver_data;
+        arinfo->timeout = jiffies;
+        arinfo->ar = ar;
+        kref_init(&arinfo->ref);
+        return 0;
+
+err_out:
+        skb_pull(skb, sizeof(*txc));
+        return -EINVAL;
+}
+
+static void carl9170_set_immba(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super;
+
+        super = (void *) skb->data;
+        super->f.mac_control |= cpu_to_le16(AR9170_TX_MAC_IMM_BA);
+}
+
+static void carl9170_set_ampdu_params(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super;
+        int tmp;
+
+        super = (void *) skb->data;
+
+        tmp = (super->s.ampdu_settings & CARL9170_TX_SUPER_AMPDU_DENSITY) <<
+                CARL9170_TX_SUPER_AMPDU_DENSITY_S;
+
+        /*
+         * If you haven't noticed carl9170_tx_prepare has already filled
+         * in all ampdu spacing & factor parameters.
+         * Now it's the time to check whenever the settings have to be
+         * updated by the firmware, or if everything is still the same.
+         *
+         * There's no sane way to handle different density values with
+         * this hardware, so we may as well just do the compare in the
+         * driver.
+         */
+
+        if (tmp != ar->current_density) {
+                ar->current_density = tmp;
+                super->s.ampdu_settings |=
+                        CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY;
+        }
+
+        tmp = (super->s.ampdu_settings & CARL9170_TX_SUPER_AMPDU_FACTOR) <<
+                CARL9170_TX_SUPER_AMPDU_FACTOR_S;
+
+        if (tmp != ar->current_factor) {
+                ar->current_factor = tmp;
+                super->s.ampdu_settings |=
+                        CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR;
+        }
+}
+
+static bool carl9170_tx_rate_check(struct ar9170 *ar, struct sk_buff *_dest,
+                                   struct sk_buff *_src)
+{
+        struct _carl9170_tx_superframe *dest, *src;
+
+        dest = (void *) _dest->data;
+        src = (void *) _src->data;
+
+        /*
+         * The mac80211 rate control algorithm expects that all MPDUs in
+         * an AMPDU share the same tx vectors.
+         * This is not really obvious right now, because the hardware
+         * does the AMPDU setup according to its own rulebook.
+         * Our nicely assembled, strictly monotonic increasing mpdu
+         * chains will be broken up, mashed back together...
+         */
+
+        return (dest->f.phy_control == src->f.phy_control);
+}
+
+static void carl9170_tx_ampdu(struct ar9170 *ar)
+{
+        struct sk_buff_head agg;
+        struct carl9170_sta_tid *tid_info;
+        struct sk_buff *skb, *first;
+        unsigned int i = 0, done_ampdus = 0;
+        u16 seq, queue, tmpssn;
+
+        atomic_inc(&ar->tx_ampdu_scheduler);
+        ar->tx_ampdu_schedule = false;
+
+        if (atomic_read(&ar->tx_ampdu_upload))
+                return;
+
+        if (!ar->tx_ampdu_list_len)
+                return;
+
+        __skb_queue_head_init(&agg);
+
+        rcu_read_lock();
+        tid_info = rcu_dereference(ar->tx_ampdu_iter);
+        if (WARN_ON_ONCE(!tid_info)) {
+                rcu_read_unlock();
+                return;
+        }
+
+retry:
+        list_for_each_entry_continue_rcu(tid_info, &ar->tx_ampdu_list, list) {
+                i++;
+
+                if (tid_info->state < CARL9170_TID_STATE_PROGRESS)
+                        continue;
+
+                queue = TID_TO_WME_AC(tid_info->tid);
+
+                spin_lock_bh(&tid_info->lock);
+                if (tid_info->state != CARL9170_TID_STATE_XMIT)
+                        goto processed;
+
+                tid_info->counter++;
+                first = skb_peek(&tid_info->queue);
+                tmpssn = carl9170_get_seq(first);
+                seq = tid_info->snx;
+
+                if (unlikely(tmpssn != seq)) {
+                        tid_info->state = CARL9170_TID_STATE_IDLE;
+
+                        goto processed;
+                }
+
+                while ((skb = skb_peek(&tid_info->queue))) {
+                        /* strict 0, 1, ..., n - 1, n frame sequence order */
+                        if (unlikely(carl9170_get_seq(skb) != seq))
+                                break;
+
+                        /* don't upload more than AMPDU FACTOR allows. */
+                        if (unlikely(SEQ_DIFF(tid_info->snx, tid_info->bsn) >=
+                            (tid_info->max - 1)))
+                                break;
+
+                        if (!carl9170_tx_rate_check(ar, skb, first))
+                                break;
+
+                        atomic_inc(&ar->tx_ampdu_upload);
+                        tid_info->snx = seq = SEQ_NEXT(seq);
+                        __skb_unlink(skb, &tid_info->queue);
+
+                        __skb_queue_tail(&agg, skb);
+
+                        if (skb_queue_len(&agg) >= CARL9170_NUM_TX_AGG_MAX)
+                                break;
+                }
+
+                if (skb_queue_empty(&tid_info->queue) ||
+                    carl9170_get_seq(skb_peek(&tid_info->queue)) !=
+                    tid_info->snx) {
+                        /*
+                         * stop TID, if A-MPDU frames are still missing,
+                         * or whenever the queue is empty.
+                         */
+
+                        tid_info->state = CARL9170_TID_STATE_IDLE;
+                }
+                done_ampdus++;
+
+processed:
+                spin_unlock_bh(&tid_info->lock);
+
+                if (skb_queue_empty(&agg))
+                        continue;
+
+                /* apply ampdu spacing & factor settings */
+                carl9170_set_ampdu_params(ar, skb_peek(&agg));
+
+                /* set aggregation push bit */
+                carl9170_set_immba(ar, skb_peek_tail(&agg));
+
+                spin_lock_bh(&ar->tx_pending[queue].lock);
+                skb_queue_splice_tail_init(&agg, &ar->tx_pending[queue]);
+                spin_unlock_bh(&ar->tx_pending[queue].lock);
+                ar->tx_schedule = true;
+        }
+        if ((done_ampdus++ == 0) && (i++ == 0))
+                goto retry;
+
+        rcu_assign_pointer(ar->tx_ampdu_iter, tid_info);
+        rcu_read_unlock();
+}
+
+static struct sk_buff *carl9170_tx_pick_skb(struct ar9170 *ar,
+                                            struct sk_buff_head *queue)
+{
+        struct sk_buff *skb;
+        struct ieee80211_tx_info *info;
+        struct carl9170_tx_info *arinfo;
+
+        BUILD_BUG_ON(sizeof(*arinfo) > sizeof(info->rate_driver_data));
+
+        spin_lock_bh(&queue->lock);
+        skb = skb_peek(queue);
+        if (unlikely(!skb))
+                goto err_unlock;
+
+        if (carl9170_alloc_dev_space(ar, skb))
+                goto err_unlock;
+
+        __skb_unlink(skb, queue);
+        spin_unlock_bh(&queue->lock);
+
+        info = IEEE80211_SKB_CB(skb);
+        arinfo = (void *) info->rate_driver_data;
+
+        arinfo->timeout = jiffies;
+        return skb;
+
+err_unlock:
+        spin_unlock_bh(&queue->lock);
+        return NULL;
+}
+
+void carl9170_tx_drop(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super;
+        uint8_t q = 0;
+
+        ar->tx_dropped++;
+
+        super = (void *)skb->data;
+        SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, q,
+                ar9170_qmap[carl9170_get_queue(ar, skb)]);
+        __carl9170_tx_process_status(ar, super->s.cookie, q);
+}
+
+static bool carl9170_tx_ps_drop(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct ieee80211_sta *sta;
+        struct carl9170_sta_info *sta_info;
+
+        rcu_read_lock();
+        sta = __carl9170_get_tx_sta(ar, skb);
+        if (!sta)
+                goto out_rcu;
+
+        sta_info = (void *) sta->drv_priv;
+        if (unlikely(sta_info->sleeping)) {
+                struct ieee80211_tx_info *tx_info;
+
+                rcu_read_unlock();
+
+                tx_info = IEEE80211_SKB_CB(skb);
+                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
+                        atomic_dec(&ar->tx_ampdu_upload);
+
+                tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
+                carl9170_tx_status(ar, skb, false);
+                return true;
+        }
+
+out_rcu:
+        rcu_read_unlock();
+        return false;
+}
+
+static void carl9170_tx(struct ar9170 *ar)
+{
+        struct sk_buff *skb;
+        unsigned int i, q;
+        bool schedule_garbagecollector = false;
+
+        ar->tx_schedule = false;
+
+        if (unlikely(!IS_STARTED(ar)))
+                return;
+
+        carl9170_usb_handle_tx_err(ar);
+
+        for (i = 0; i < ar->hw->queues; i++) {
+                while (!skb_queue_empty(&ar->tx_pending[i])) {
+                        skb = carl9170_tx_pick_skb(ar, &ar->tx_pending[i]);
+                        if (unlikely(!skb))
+                                break;
+
+                        if (unlikely(carl9170_tx_ps_drop(ar, skb)))
+                                continue;
+
+                        atomic_inc(&ar->tx_total_pending);
+
+                        q = __carl9170_get_queue(ar, i);
+                        /*
+                         * NB: tx_status[i] vs. tx_status[q],
+                         * TODO: Move into pick_skb or alloc_dev_space.
+                         */
+                        skb_queue_tail(&ar->tx_status[q], skb);
+
+                        /*
+                         * increase ref count to "2".
+                         * Ref counting is the easiest way to solve the
+                         * race between the urb's completion routine:
+                         *      carl9170_tx_callback
+                         * and wlan tx status functions:
+                         *      carl9170_tx_status/janitor.
+                         */
+                        carl9170_tx_get_skb(skb);
+
+                        carl9170_usb_tx(ar, skb);
+                        schedule_garbagecollector = true;
+                }
+        }
+
+        if (!schedule_garbagecollector)
+                return;
+
+        ieee80211_queue_delayed_work(ar->hw, &ar->tx_janitor,
+                msecs_to_jiffies(CARL9170_TX_TIMEOUT));
+}
+
+static bool carl9170_tx_ampdu_queue(struct ar9170 *ar,
+        struct ieee80211_sta *sta, struct sk_buff *skb)
+{
+        struct _carl9170_tx_superframe *super = (void *) skb->data;
+        struct carl9170_sta_info *sta_info;
+        struct carl9170_sta_tid *agg;
+        struct sk_buff *iter;
+        u16 tid, seq, qseq, off;
+        bool run = false;
+
+        tid = carl9170_get_tid(skb);
+        seq = carl9170_get_seq(skb);
+        sta_info = (void *) sta->drv_priv;
+
+        rcu_read_lock();
+        agg = rcu_dereference(sta_info->agg[tid]);
+
+        if (!agg)
+                goto err_unlock_rcu;
+
+        spin_lock_bh(&agg->lock);
+        if (unlikely(agg->state < CARL9170_TID_STATE_IDLE))
+                goto err_unlock;
+
+        /* check if sequence is within the BA window */
+        if (unlikely(!BAW_WITHIN(agg->bsn, CARL9170_BAW_BITS, seq)))
+                goto err_unlock;
+
+        if (WARN_ON_ONCE(!BAW_WITHIN(agg->snx, CARL9170_BAW_BITS, seq)))
+                goto err_unlock;
+
+        off = SEQ_DIFF(seq, agg->bsn);
+        if (WARN_ON_ONCE(test_and_set_bit(off, agg->bitmap)))
+                goto err_unlock;
+
+        if (likely(BAW_WITHIN(agg->hsn, CARL9170_BAW_BITS, seq))) {
+                __skb_queue_tail(&agg->queue, skb);
+                agg->hsn = seq;
+                goto queued;
+        }
+
+        skb_queue_reverse_walk(&agg->queue, iter) {
+                qseq = carl9170_get_seq(iter);
+
+                if (BAW_WITHIN(qseq, CARL9170_BAW_BITS, seq)) {
+                        __skb_queue_after(&agg->queue, iter, skb);
+                        goto queued;
+                }
+        }
+
+        __skb_queue_head(&agg->queue, skb);
+queued:
+
+        if (unlikely(agg->state != CARL9170_TID_STATE_XMIT)) {
+                if (agg->snx == carl9170_get_seq(skb_peek(&agg->queue))) {
+                        agg->state = CARL9170_TID_STATE_XMIT;
+                        run = true;
+                }
+        }
+
+        spin_unlock_bh(&agg->lock);
+        rcu_read_unlock();
+
+        return run;
+
+err_unlock:
+        spin_unlock_bh(&agg->lock);
+
+err_unlock_rcu:
+        rcu_read_unlock();
+        super->f.mac_control &= ~cpu_to_le16(AR9170_TX_MAC_AGGR);
+        carl9170_tx_status(ar, skb, false);
+        ar->tx_dropped++;
+        return false;
+}
+
+void carl9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct ar9170 *ar = hw->priv;
+        struct ieee80211_tx_info *info;
+        struct ieee80211_sta *sta;
+        bool run;
+
+        if (unlikely(!IS_STARTED(ar)))
+                goto err_free;
+
+        info = IEEE80211_SKB_CB(skb);
+        sta = info->control.sta;
+
+        if (unlikely(carl9170_tx_prepare(ar, skb)))
+                goto err_free;
+
+        carl9170_tx_accounting(ar, skb);
+        /*
+         * from now on, one has to use carl9170_tx_status to free
+         * all ressouces which are associated with the frame.
+         */
+
+        if (sta) {
+                struct carl9170_sta_info *stai = (void *) sta->drv_priv;
+                atomic_inc(&stai->pending_frames);
+        }
+
+        if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+                run = carl9170_tx_ampdu_queue(ar, sta, skb);
+                if (run)
+                        carl9170_tx_ampdu(ar);
+
+        } else {
+                unsigned int queue = skb_get_queue_mapping(skb);
+
+                skb_queue_tail(&ar->tx_pending[queue], skb);
+        }
+
+        carl9170_tx(ar);
+        return;
+
+err_free:
+        ar->tx_dropped++;
+        dev_kfree_skb_any(skb);
+}
+
+void carl9170_tx_scheduler(struct ar9170 *ar)
+{
+
+        if (ar->tx_ampdu_schedule)
+                carl9170_tx_ampdu(ar);
+
+        if (ar->tx_schedule)
+                carl9170_tx(ar);
+}
diff --git a/drivers/net/wireless/ath/carl9170/usb.c b/drivers/net/wireless/ath/carl9170/usb.c
new file mode 100644
index 000000000000..333b69ef2ae2
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/usb.c
@@ -0,0 +1,1175 @@
+/*
+ * Atheros CARL9170 driver
+ *
+ * USB - frontend
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/usb.h>
+#include <linux/firmware.h>
+#include <linux/etherdevice.h>
+#include <linux/device.h>
+#include <net/mac80211.h>
+#include "carl9170.h"
+#include "cmd.h"
+#include "hw.h"
+#include "fwcmd.h"
+
+MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
+MODULE_AUTHOR("Christian Lamparter <chunkeey@googlemail.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Atheros AR9170 802.11n USB wireless");
+MODULE_FIRMWARE(CARL9170FW_NAME);
+MODULE_ALIAS("ar9170usb");
+MODULE_ALIAS("arusb_lnx");
+
+/*
+ * Note:
+ *
+ * Always update our wiki's device list (located at:
+ * http://wireless.kernel.org/en/users/Drivers/ar9170/devices ),
+ * whenever you add a new device.
+ */
+static struct usb_device_id carl9170_usb_ids[] = {
+        /* Atheros 9170 */
+        { USB_DEVICE(0x0cf3, 0x9170) },
+        /* Atheros TG121N */
+        { USB_DEVICE(0x0cf3, 0x1001) },
+        /* TP-Link TL-WN821N v2 */
+        { USB_DEVICE(0x0cf3, 0x1002), .driver_info = CARL9170_WPS_BUTTON |
+                 CARL9170_ONE_LED },
+        /* 3Com Dual Band 802.11n USB Adapter */
+        { USB_DEVICE(0x0cf3, 0x1010) },
+        /* H3C Dual Band 802.11n USB Adapter */
+        { USB_DEVICE(0x0cf3, 0x1011) },
+        /* Cace Airpcap NX */
+        { USB_DEVICE(0xcace, 0x0300) },
+        /* D-Link DWA 160 A1 */
+        { USB_DEVICE(0x07d1, 0x3c10) },
+        /* D-Link DWA 160 A2 */
+        { USB_DEVICE(0x07d1, 0x3a09) },
+        /* D-Link DWA 130 D */
+        { USB_DEVICE(0x07d1, 0x3a0f) },
+        /* Netgear WNA1000 */
+        { USB_DEVICE(0x0846, 0x9040) },
+        /* Netgear WNDA3100 (v1) */
+        { USB_DEVICE(0x0846, 0x9010) },
+        /* Netgear WN111 v2 */
+        { USB_DEVICE(0x0846, 0x9001), .driver_info = CARL9170_ONE_LED },
+        /* Zydas ZD1221 */
+        { USB_DEVICE(0x0ace, 0x1221) },
+        /* Proxim ORiNOCO 802.11n USB */
+        { USB_DEVICE(0x1435, 0x0804) },
+        /* WNC Generic 11n USB Dongle */
+        { USB_DEVICE(0x1435, 0x0326) },
+        /* ZyXEL NWD271N */
+        { USB_DEVICE(0x0586, 0x3417) },
+        /* Z-Com UB81 BG */
+        { USB_DEVICE(0x0cde, 0x0023) },
+        /* Z-Com UB82 ABG */
+        { USB_DEVICE(0x0cde, 0x0026) },
+        /* Sphairon Homelink 1202 */
+        { USB_DEVICE(0x0cde, 0x0027) },
+        /* Arcadyan WN7512 */
+        { USB_DEVICE(0x083a, 0xf522) },
+        /* Planex GWUS300 */
+        { USB_DEVICE(0x2019, 0x5304) },
+        /* IO-Data WNGDNUS2 */
+        { USB_DEVICE(0x04bb, 0x093f) },
+        /* NEC WL300NU-G */
+        { USB_DEVICE(0x0409, 0x0249) },
+        /* NEC WL300NU-AG */
+        { USB_DEVICE(0x0409, 0x02b4) },
+        /* AVM FRITZ!WLAN USB Stick N */
+        { USB_DEVICE(0x057c, 0x8401) },
+        /* AVM FRITZ!WLAN USB Stick N 2.4 */
+        { USB_DEVICE(0x057c, 0x8402) },
+        /* Qwest/Actiontec 802AIN Wireless N USB Network Adapter */
+        { USB_DEVICE(0x1668, 0x1200) },
+        /* Airlive X.USB a/b/g/n */
+        { USB_DEVICE(0x1b75, 0x9170) },
+
+        /* terminate */
+        {}
+};
+MODULE_DEVICE_TABLE(usb, carl9170_usb_ids);
+
+static void carl9170_usb_submit_data_urb(struct ar9170 *ar)
+{
+        struct urb *urb;
+        int err;
+
+        if (atomic_inc_return(&ar->tx_anch_urbs) > AR9170_NUM_TX_URBS)
+                goto err_acc;
+
+        urb = usb_get_from_anchor(&ar->tx_wait);
+        if (!urb)
+                goto err_acc;
+
+        usb_anchor_urb(urb, &ar->tx_anch);
+
+        err = usb_submit_urb(urb, GFP_ATOMIC);
+        if (unlikely(err)) {
+                if (net_ratelimit()) {
+                        dev_err(&ar->udev->dev, "tx submit failed (%d)\n",
+                                urb->status);
+                }
+
+                usb_unanchor_urb(urb);
+                usb_anchor_urb(urb, &ar->tx_err);
+        }
+
+        usb_free_urb(urb);
+
+        if (likely(err == 0))
+                return;
+
+err_acc:
+        atomic_dec(&ar->tx_anch_urbs);
+}
+
+static void carl9170_usb_tx_data_complete(struct urb *urb)
+{
+        struct ar9170 *ar = usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
+
+        if (WARN_ON_ONCE(!ar)) {
+                dev_kfree_skb_irq(urb->context);
+                return;
+        }
+
+        atomic_dec(&ar->tx_anch_urbs);
+
+        switch (urb->status) {
+        /* everything is fine */
+        case 0:
+                carl9170_tx_callback(ar, (void *)urb->context);
+                break;
+
+        /* disconnect */
+        case -ENOENT:
+        case -ECONNRESET:
+        case -ENODEV:
+        case -ESHUTDOWN:
+                /*
+                 * Defer the frame clean-up to the tasklet worker.
+                 * This is necessary, because carl9170_tx_drop
+                 * does not work in an irqsave context.
+                 */
+                usb_anchor_urb(urb, &ar->tx_err);
+                return;
+
+        /* a random transmission error has occurred? */
+        default:
+                if (net_ratelimit()) {
+                        dev_err(&ar->udev->dev, "tx failed (%d)\n",
+                                urb->status);
+                }
+
+                usb_anchor_urb(urb, &ar->tx_err);
+                break;
+        }
+
+        if (likely(IS_STARTED(ar)))
+                carl9170_usb_submit_data_urb(ar);
+}
+
+static int carl9170_usb_submit_cmd_urb(struct ar9170 *ar)
+{
+        struct urb *urb;
+        int err;
+
+        if (atomic_inc_return(&ar->tx_cmd_urbs) != 1) {
+                atomic_dec(&ar->tx_cmd_urbs);
+                return 0;
+        }
+
+        urb = usb_get_from_anchor(&ar->tx_cmd);
+        if (!urb) {
+                atomic_dec(&ar->tx_cmd_urbs);
+                return 0;
+        }
+
+        usb_anchor_urb(urb, &ar->tx_anch);
+        err = usb_submit_urb(urb, GFP_ATOMIC);
+        if (unlikely(err)) {
+                usb_unanchor_urb(urb);
+                atomic_dec(&ar->tx_cmd_urbs);
+        }
+        usb_free_urb(urb);
+
+        return err;
+}
+
+static void carl9170_usb_cmd_complete(struct urb *urb)
+{
+        struct ar9170 *ar = urb->context;
+        int err = 0;
+
+        if (WARN_ON_ONCE(!ar))
+                return;
+
+        atomic_dec(&ar->tx_cmd_urbs);
+
+        switch (urb->status) {
+        /* everything is fine */
+        case 0:
+                break;
+
+        /* disconnect */
+        case -ENOENT:
+        case -ECONNRESET:
+        case -ENODEV:
+        case -ESHUTDOWN:
+                return;
+
+        default:
+                err = urb->status;
+                break;
+        }
+
+        if (!IS_INITIALIZED(ar))
+                return;
+
+        if (err)
+                dev_err(&ar->udev->dev, "submit cmd cb failed (%d).\n", err);
+
+        err = carl9170_usb_submit_cmd_urb(ar);
+        if (err)
+                dev_err(&ar->udev->dev, "submit cmd failed (%d).\n", err);
+}
+
+static void carl9170_usb_rx_irq_complete(struct urb *urb)
+{
+        struct ar9170 *ar = urb->context;
+
+        if (WARN_ON_ONCE(!ar))
+                return;
+
+        switch (urb->status) {
+        /* everything is fine */
+        case 0:
+                break;
+
+        /* disconnect */
+        case -ENOENT:
+        case -ECONNRESET:
+        case -ENODEV:
+        case -ESHUTDOWN:
+                return;
+
+        default:
+                goto resubmit;
+        }
+
+        carl9170_handle_command_response(ar, urb->transfer_buffer,
+                                         urb->actual_length);
+
+resubmit:
+        usb_anchor_urb(urb, &ar->rx_anch);
+        if (unlikely(usb_submit_urb(urb, GFP_ATOMIC)))
+                usb_unanchor_urb(urb);
+}
+
+static int carl9170_usb_submit_rx_urb(struct ar9170 *ar, gfp_t gfp)
+{
+        struct urb *urb;
+        int err = 0, runs = 0;
+
+        while ((atomic_read(&ar->rx_anch_urbs) < AR9170_NUM_RX_URBS) &&
+                (runs++ < AR9170_NUM_RX_URBS)) {
+                err = -ENOSPC;
+                urb = usb_get_from_anchor(&ar->rx_pool);
+                if (urb) {
+                        usb_anchor_urb(urb, &ar->rx_anch);
+                        err = usb_submit_urb(urb, gfp);
+                        if (unlikely(err)) {
+                                usb_unanchor_urb(urb);
+                                usb_anchor_urb(urb, &ar->rx_pool);
+                        } else {
+                                atomic_dec(&ar->rx_pool_urbs);
+                                atomic_inc(&ar->rx_anch_urbs);
+                        }
+                        usb_free_urb(urb);
+                }
+        }
+
+        return err;
+}
+
+static void carl9170_usb_rx_work(struct ar9170 *ar)
+{
+        struct urb *urb;
+        int i;
+
+        for (i = 0; i < AR9170_NUM_RX_URBS_POOL; i++) {
+                urb = usb_get_from_anchor(&ar->rx_work);
+                if (!urb)
+                        break;
+
+                atomic_dec(&ar->rx_work_urbs);
+                if (IS_INITIALIZED(ar)) {
+                        carl9170_rx(ar, urb->transfer_buffer,
+                                    urb->actual_length);
+                }
+
+                usb_anchor_urb(urb, &ar->rx_pool);
+                atomic_inc(&ar->rx_pool_urbs);
+
+                usb_free_urb(urb);
+
+                carl9170_usb_submit_rx_urb(ar, GFP_ATOMIC);
+        }
+}
+
+void carl9170_usb_handle_tx_err(struct ar9170 *ar)
+{
+        struct urb *urb;
+
+        while ((urb = usb_get_from_anchor(&ar->tx_err))) {
+                struct sk_buff *skb = (void *)urb->context;
+
+                carl9170_tx_drop(ar, skb);
+                carl9170_tx_callback(ar, skb);
+                usb_free_urb(urb);
+        }
+}
+
+static void carl9170_usb_tasklet(unsigned long data)
+{
+        struct ar9170 *ar = (struct ar9170 *) data;
+
+        if (!IS_INITIALIZED(ar))
+                return;
+
+        carl9170_usb_rx_work(ar);
+
+        /*
+         * Strictly speaking: The tx scheduler is not part of the USB system.
+         * But the rx worker returns frames back to the mac80211-stack and
+         * this is the _perfect_ place to generate the next transmissions.
+         */
+        if (IS_STARTED(ar))
+                carl9170_tx_scheduler(ar);
+}
+
+static void carl9170_usb_rx_complete(struct urb *urb)
+{
+        struct ar9170 *ar = (struct ar9170 *)urb->context;
+        int err;
+
+        if (WARN_ON_ONCE(!ar))
+                return;
+
+        atomic_dec(&ar->rx_anch_urbs);
+
+        switch (urb->status) {
+        case 0:
+                /* rx path */
+                usb_anchor_urb(urb, &ar->rx_work);
+                atomic_inc(&ar->rx_work_urbs);
+                break;
+
+        case -ENOENT:
+        case -ECONNRESET:
+        case -ENODEV:
+        case -ESHUTDOWN:
+                /* handle disconnect events*/
+                return;
+
+        default:
+                /* handle all other errors */
+                usb_anchor_urb(urb, &ar->rx_pool);
+                atomic_inc(&ar->rx_pool_urbs);
+                break;
+        }
+
+        err = carl9170_usb_submit_rx_urb(ar, GFP_ATOMIC);
+        if (unlikely(err)) {
+                /*
+                 * usb_submit_rx_urb reported a problem.
+                 * In case this is due to a rx buffer shortage,
+                 * elevate the tasklet worker priority to
+                 * the highest available level.
+                 */
+                tasklet_hi_schedule(&ar->usb_tasklet);
+
+                if (atomic_read(&ar->rx_anch_urbs) == 0) {
+                        /*
+                         * The system is too slow to cope with
+                         * the enormous workload. We have simply
+                         * run out of active rx urbs and this
+                         * unfortunately leads to an unpredictable
+                         * device.
+                         */
+
+                        ieee80211_queue_work(ar->hw, &ar->ping_work);
+                }
+        } else {
+                /*
+                 * Using anything less than _high_ priority absolutely
+                 * kills the rx performance my UP-System...
+                 */
+                tasklet_hi_schedule(&ar->usb_tasklet);
+        }
+}
+
+static struct urb *carl9170_usb_alloc_rx_urb(struct ar9170 *ar, gfp_t gfp)
+{
+        struct urb *urb;
+        void *buf;
+
+        buf = kmalloc(ar->fw.rx_size, gfp);
+        if (!buf)
+                return NULL;
+
+        urb = usb_alloc_urb(0, gfp);
+        if (!urb) {
+                kfree(buf);
+                return NULL;
+        }
+
+        usb_fill_bulk_urb(urb, ar->udev, usb_rcvbulkpipe(ar->udev,
+                          AR9170_USB_EP_RX), buf, ar->fw.rx_size,
+                          carl9170_usb_rx_complete, ar);
+
+        urb->transfer_flags |= URB_FREE_BUFFER;
+
+        return urb;
+}
+
+static int carl9170_usb_send_rx_irq_urb(struct ar9170 *ar)
+{
+        struct urb *urb = NULL;
+        void *ibuf;
+        int err = -ENOMEM;
+
+        urb = usb_alloc_urb(0, GFP_KERNEL);
+        if (!urb)
+                goto out;
+
+        ibuf = kmalloc(AR9170_USB_EP_CTRL_MAX, GFP_KERNEL);
+        if (!ibuf)
+                goto out;
+
+        usb_fill_int_urb(urb, ar->udev, usb_rcvintpipe(ar->udev,
+                         AR9170_USB_EP_IRQ), ibuf, AR9170_USB_EP_CTRL_MAX,
+                         carl9170_usb_rx_irq_complete, ar, 1);
+
+        urb->transfer_flags |= URB_FREE_BUFFER;
+
+        usb_anchor_urb(urb, &ar->rx_anch);
+        err = usb_submit_urb(urb, GFP_KERNEL);
+        if (err)
+                usb_unanchor_urb(urb);
+
+out:
+        usb_free_urb(urb);
+        return err;
+}
+
+static int carl9170_usb_init_rx_bulk_urbs(struct ar9170 *ar)
+{
+        struct urb *urb;
+        int i, err = -EINVAL;
+
+        /*
+         * The driver actively maintains a second shadow
+         * pool for inactive, but fully-prepared rx urbs.
+         *
+         * The pool should help the driver to master huge
+         * workload spikes without running the risk of
+         * undersupplying the hardware or wasting time by
+         * processing rx data (streams) inside the urb
+         * completion (hardirq context).
+         */
+        for (i = 0; i < AR9170_NUM_RX_URBS_POOL; i++) {
+                urb = carl9170_usb_alloc_rx_urb(ar, GFP_KERNEL);
+                if (!urb) {
+                        err = -ENOMEM;
+                        goto err_out;
+                }
+
+                usb_anchor_urb(urb, &ar->rx_pool);
+                atomic_inc(&ar->rx_pool_urbs);
+                usb_free_urb(urb);
+        }
+
+        err = carl9170_usb_submit_rx_urb(ar, GFP_KERNEL);
+        if (err)
+                goto err_out;
+
+        /* the device now waiting for the firmware. */
+        carl9170_set_state_when(ar, CARL9170_STOPPED, CARL9170_IDLE);
+        return 0;
+
+err_out:
+
+        usb_scuttle_anchored_urbs(&ar->rx_pool);
+        usb_scuttle_anchored_urbs(&ar->rx_work);
+        usb_kill_anchored_urbs(&ar->rx_anch);
+        return err;
+}
+
+static int carl9170_usb_flush(struct ar9170 *ar)
+{
+        struct urb *urb;
+        int ret, err = 0;
+
+        while ((urb = usb_get_from_anchor(&ar->tx_wait))) {
+                struct sk_buff *skb = (void *)urb->context;
+                carl9170_tx_drop(ar, skb);
+                carl9170_tx_callback(ar, skb);
+                usb_free_urb(urb);
+        }
+
+        ret = usb_wait_anchor_empty_timeout(&ar->tx_cmd, 1000);
+        if (ret == 0)
+                err = -ETIMEDOUT;
+
+        /* lets wait a while until the tx - queues are dried out */
+        ret = usb_wait_anchor_empty_timeout(&ar->tx_anch, 1000);
+        if (ret == 0)
+                err = -ETIMEDOUT;
+
+        usb_kill_anchored_urbs(&ar->tx_anch);
+        carl9170_usb_handle_tx_err(ar);
+
+        return err;
+}
+
+static void carl9170_usb_cancel_urbs(struct ar9170 *ar)
+{
+        int err;
+
+        carl9170_set_state(ar, CARL9170_UNKNOWN_STATE);
+
+        err = carl9170_usb_flush(ar);
+        if (err)
+                dev_err(&ar->udev->dev, "stuck tx urbs!\n");
+
+        usb_poison_anchored_urbs(&ar->tx_anch);
+        carl9170_usb_handle_tx_err(ar);
+        usb_poison_anchored_urbs(&ar->rx_anch);
+
+        tasklet_kill(&ar->usb_tasklet);
+
+        usb_scuttle_anchored_urbs(&ar->rx_work);
+        usb_scuttle_anchored_urbs(&ar->rx_pool);
+        usb_scuttle_anchored_urbs(&ar->tx_cmd);
+}
+
+int __carl9170_exec_cmd(struct ar9170 *ar, struct carl9170_cmd *cmd,
+                        const bool free_buf)
+{
+        struct urb *urb;
+        int err = 0;
+
+        if (!IS_INITIALIZED(ar)) {
+                err = -EPERM;
+                goto err_free;
+        }
+
+        if (WARN_ON(cmd->hdr.len > CARL9170_MAX_CMD_LEN - 4)) {
+                err = -EINVAL;
+                goto err_free;
+        }
+
+        urb = usb_alloc_urb(0, GFP_ATOMIC);
+        if (!urb) {
+                err = -ENOMEM;
+                goto err_free;
+        }
+
+        usb_fill_int_urb(urb, ar->udev, usb_sndintpipe(ar->udev,
+                AR9170_USB_EP_CMD), cmd, cmd->hdr.len + 4,
+                carl9170_usb_cmd_complete, ar, 1);
+
+        if (free_buf)
+                urb->transfer_flags |= URB_FREE_BUFFER;
+
+        usb_anchor_urb(urb, &ar->tx_cmd);
+        usb_free_urb(urb);
+
+        return carl9170_usb_submit_cmd_urb(ar);
+
+err_free:
+        if (free_buf)
+                kfree(cmd);
+
+        return err;
+}
+
+int carl9170_exec_cmd(struct ar9170 *ar, const enum carl9170_cmd_oids cmd,
+        unsigned int plen, void *payload, unsigned int outlen, void *out)
+{
+        int err = -ENOMEM;
+
+        if (!IS_ACCEPTING_CMD(ar))
+                return -EIO;
+
+        if (!(cmd & CARL9170_CMD_ASYNC_FLAG))
+                might_sleep();
+
+        ar->cmd.hdr.len = plen;
+        ar->cmd.hdr.cmd = cmd;
+        /* writing multiple regs fills this buffer already */
+        if (plen && payload != (u8 *)(ar->cmd.data))
+                memcpy(ar->cmd.data, payload, plen);
+
+        spin_lock_bh(&ar->cmd_lock);
+        ar->readbuf = (u8 *)out;
+        ar->readlen = outlen;
+        spin_unlock_bh(&ar->cmd_lock);
+
+        err = __carl9170_exec_cmd(ar, &ar->cmd, false);
+
+        if (!(cmd & CARL9170_CMD_ASYNC_FLAG)) {
+                err = wait_for_completion_timeout(&ar->cmd_wait, HZ);
+                if (err == 0) {
+                        err = -ETIMEDOUT;
+                        goto err_unbuf;
+                }
+
+                if (ar->readlen != outlen) {
+                        err = -EMSGSIZE;
+                        goto err_unbuf;
+                }
+        }
+
+        return 0;
+
+err_unbuf:
+        /* Maybe the device was removed in the moment we were waiting? */
+        if (IS_STARTED(ar)) {
+                dev_err(&ar->udev->dev, "no command feedback "
+                        "received (%d).\n", err);
+
+                /* provide some maybe useful debug information */
+                print_hex_dump_bytes("carl9170 cmd: ", DUMP_PREFIX_NONE,
+                                     &ar->cmd, plen + 4);
+
+                carl9170_restart(ar, CARL9170_RR_COMMAND_TIMEOUT);
+        }
+
+        /* invalidate to avoid completing the next command prematurely */
+        spin_lock_bh(&ar->cmd_lock);
+        ar->readbuf = NULL;
+        ar->readlen = 0;
+        spin_unlock_bh(&ar->cmd_lock);
+
+        return err;
+}
+
+void carl9170_usb_tx(struct ar9170 *ar, struct sk_buff *skb)
+{
+        struct urb *urb;
+        struct ar9170_stream *tx_stream;
+        void *data;
+        unsigned int len;
+
+        if (!IS_STARTED(ar))
+                goto err_drop;
+
+        urb = usb_alloc_urb(0, GFP_ATOMIC);
+        if (!urb)
+                goto err_drop;
+
+        if (ar->fw.tx_stream) {
+                tx_stream = (void *) (skb->data - sizeof(*tx_stream));
+
+                len = skb->len + sizeof(*tx_stream);
+                tx_stream->length = cpu_to_le16(len);
+                tx_stream->tag = cpu_to_le16(AR9170_TX_STREAM_TAG);
+                data = tx_stream;
+        } else {
+                data = skb->data;
+                len = skb->len;
+        }
+
+        usb_fill_bulk_urb(urb, ar->udev, usb_sndbulkpipe(ar->udev,
+                AR9170_USB_EP_TX), data, len,
+                carl9170_usb_tx_data_complete, skb);
+
+        urb->transfer_flags |= URB_ZERO_PACKET;
+
+        usb_anchor_urb(urb, &ar->tx_wait);
+
+        usb_free_urb(urb);
+
+        carl9170_usb_submit_data_urb(ar);
+        return;
+
+err_drop:
+        carl9170_tx_drop(ar, skb);
+        carl9170_tx_callback(ar, skb);
+}
+
+static void carl9170_release_firmware(struct ar9170 *ar)
+{
+        if (ar->fw.fw) {
+                release_firmware(ar->fw.fw);
+                memset(&ar->fw, 0, sizeof(ar->fw));
+        }
+}
+
+void carl9170_usb_stop(struct ar9170 *ar)
+{
+        int ret;
+
+        carl9170_set_state_when(ar, CARL9170_IDLE, CARL9170_STOPPED);
+
+        ret = carl9170_usb_flush(ar);
+        if (ret)
+                dev_err(&ar->udev->dev, "kill pending tx urbs.\n");
+
+        usb_poison_anchored_urbs(&ar->tx_anch);
+        carl9170_usb_handle_tx_err(ar);
+
+        /* kill any pending command */
+        spin_lock_bh(&ar->cmd_lock);
+        ar->readlen = 0;
+        spin_unlock_bh(&ar->cmd_lock);
+        complete_all(&ar->cmd_wait);
+
+        /* This is required to prevent an early completion on _start */
+        INIT_COMPLETION(ar->cmd_wait);
+
+        /*
+         * Note:
+         * So far we freed all tx urbs, but we won't dare to touch any rx urbs.
+         * Else we would end up with a unresponsive device...
+         */
+}
+
+int carl9170_usb_open(struct ar9170 *ar)
+{
+        usb_unpoison_anchored_urbs(&ar->tx_anch);
+
+        carl9170_set_state_when(ar, CARL9170_STOPPED, CARL9170_IDLE);
+        return 0;
+}
+
+static int carl9170_usb_load_firmware(struct ar9170 *ar)
+{
+        const u8 *data;
+        u8 *buf;
+        unsigned int transfer;
+        size_t len;
+        u32 addr;
+        int err = 0;
+
+        buf = kmalloc(4096, GFP_KERNEL);
+        if (!buf) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+
+        data = ar->fw.fw->data;
+        len = ar->fw.fw->size;
+        addr = ar->fw.address;
+
+        /* this removes the miniboot image */
+        data += ar->fw.offset;
+        len -= ar->fw.offset;
+
+        while (len) {
+                transfer = min_t(unsigned int, len, 4096u);
+                memcpy(buf, data, transfer);
+
+                err = usb_control_msg(ar->udev, usb_sndctrlpipe(ar->udev, 0),
+                                      0x30 /* FW DL */, 0x40 | USB_DIR_OUT,
+                                      addr >> 8, 0, buf, transfer, 100);
+
+                if (err < 0) {
+                        kfree(buf);
+                        goto err_out;
+                }
+
+                len -= transfer;
+                data += transfer;
+                addr += transfer;
+        }
+        kfree(buf);
+
+        err = usb_control_msg(ar->udev, usb_sndctrlpipe(ar->udev, 0),
+                              0x31 /* FW DL COMPLETE */,
+                              0x40 | USB_DIR_OUT, 0, 0, NULL, 0, 200);
+
+        if (wait_for_completion_timeout(&ar->fw_boot_wait, HZ) == 0) {
+                err = -ETIMEDOUT;
+                goto err_out;
+        }
+
+        err = carl9170_echo_test(ar, 0x4a110123);
+        if (err)
+                goto err_out;
+
+        /* now, start the command response counter */
+        ar->cmd_seq = -1;
+
+        return 0;
+
+err_out:
+        dev_err(&ar->udev->dev, "firmware upload failed (%d).\n", err);
+        return err;
+}
+
+int carl9170_usb_restart(struct ar9170 *ar)
+{
+        int err = 0;
+
+        if (ar->intf->condition != USB_INTERFACE_BOUND)
+                return 0;
+
+        /*
+         * Disable the command response sequence counter check.
+         * We already know that the device/firmware is in a bad state.
+         * So, no extra points are awarded to anyone who reminds the
+         * driver about that.
+         */
+        ar->cmd_seq = -2;
+
+        err = carl9170_reboot(ar);
+
+        carl9170_usb_stop(ar);
+
+        if (err)
+                goto err_out;
+
+        tasklet_schedule(&ar->usb_tasklet);
+
+        /* The reboot procedure can take quite a while to complete. */
+        msleep(1100);
+
+        err = carl9170_usb_open(ar);
+        if (err)
+                goto err_out;
+
+        err = carl9170_usb_load_firmware(ar);
+        if (err)
+                goto err_out;
+
+        return 0;
+
+err_out:
+        carl9170_usb_cancel_urbs(ar);
+        return err;
+}
+
+void carl9170_usb_reset(struct ar9170 *ar)
+{
+        /*
+         * This is the last resort to get the device going again
+         * without any *user replugging action*.
+         *
+         * But there is a catch: usb_reset really is like a physical
+         * *reconnect*. The mac80211 state will be lost in the process.
+         * Therefore a userspace application, which is monitoring
+         * the link must step in.
+         */
+        carl9170_usb_cancel_urbs(ar);
+
+        carl9170_usb_stop(ar);
+
+        usb_queue_reset_device(ar->intf);
+}
+
+static int carl9170_usb_init_device(struct ar9170 *ar)
+{
+        int err;
+
+        /*
+         * The carl9170 firmware let's the driver know when it's
+         * ready for action. But we have to be prepared to gracefully
+         * handle all spurious [flushed] messages after each (re-)boot.
+         * Thus the command response counter remains disabled until it
+         * can be safely synchronized.
+         */
+        ar->cmd_seq = -2;
+
+        err = carl9170_usb_send_rx_irq_urb(ar);
+        if (err)
+                goto err_out;
+
+        err = carl9170_usb_init_rx_bulk_urbs(ar);
+        if (err)
+                goto err_unrx;
+
+        err = carl9170_usb_open(ar);
+        if (err)
+                goto err_unrx;
+
+        mutex_lock(&ar->mutex);
+        err = carl9170_usb_load_firmware(ar);
+        mutex_unlock(&ar->mutex);
+        if (err)
+                goto err_stop;
+
+        return 0;
+
+err_stop:
+        carl9170_usb_stop(ar);
+
+err_unrx:
+        carl9170_usb_cancel_urbs(ar);
+
+err_out:
+        return err;
+}
+
+static void carl9170_usb_firmware_failed(struct ar9170 *ar)
+{
+        struct device *parent = ar->udev->dev.parent;
+        struct usb_device *udev;
+
+        /*
+         * Store a copy of the usb_device pointer locally.
+         * This is because device_release_driver initiates
+         * carl9170_usb_disconnect, which in turn frees our
+         * driver context (ar).
+         */
+        udev = ar->udev;
+
+        complete(&ar->fw_load_wait);
+
+        /* unbind anything failed */
+        if (parent)
+                device_lock(parent);
+
+        device_release_driver(&udev->dev);
+        if (parent)
+                device_unlock(parent);
+
+        usb_put_dev(udev);
+}
+
+static void carl9170_usb_firmware_finish(struct ar9170 *ar)
+{
+        int err;
+
+        err = carl9170_parse_firmware(ar);
+        if (err)
+                goto err_freefw;
+
+        err = carl9170_usb_init_device(ar);
+        if (err)
+                goto err_freefw;
+
+        err = carl9170_register(ar);
+
+        carl9170_usb_stop(ar);
+        if (err)
+                goto err_unrx;
+
+        complete(&ar->fw_load_wait);
+        usb_put_dev(ar->udev);
+        return;
+
+err_unrx:
+        carl9170_usb_cancel_urbs(ar);
+
+err_freefw:
+        carl9170_release_firmware(ar);
+        carl9170_usb_firmware_failed(ar);
+}
+
+static void carl9170_usb_firmware_step2(const struct firmware *fw,
+                                        void *context)
+{
+        struct ar9170 *ar = context;
+
+        if (fw) {
+                ar->fw.fw = fw;
+                carl9170_usb_firmware_finish(ar);
+                return;
+        }
+
+        dev_err(&ar->udev->dev, "firmware not found.\n");
+        carl9170_usb_firmware_failed(ar);
+}
+
+static int carl9170_usb_probe(struct usb_interface *intf,
+                              const struct usb_device_id *id)
+{
+        struct ar9170 *ar;
+        struct usb_device *udev;
+        int err;
+
+        err = usb_reset_device(interface_to_usbdev(intf));
+        if (err)
+                return err;
+
+        ar = carl9170_alloc(sizeof(*ar));
+        if (IS_ERR(ar))
+                return PTR_ERR(ar);
+
+        udev = interface_to_usbdev(intf);
+        usb_get_dev(udev);
+        ar->udev = udev;
+        ar->intf = intf;
+        ar->features = id->driver_info;
+
+        usb_set_intfdata(intf, ar);
+        SET_IEEE80211_DEV(ar->hw, &intf->dev);
+
+        init_usb_anchor(&ar->rx_anch);
+        init_usb_anchor(&ar->rx_pool);
+        init_usb_anchor(&ar->rx_work);
+        init_usb_anchor(&ar->tx_wait);
+        init_usb_anchor(&ar->tx_anch);
+        init_usb_anchor(&ar->tx_cmd);
+        init_usb_anchor(&ar->tx_err);
+        init_completion(&ar->cmd_wait);
+        init_completion(&ar->fw_boot_wait);
+        init_completion(&ar->fw_load_wait);
+        tasklet_init(&ar->usb_tasklet, carl9170_usb_tasklet,
+                     (unsigned long)ar);
+
+        atomic_set(&ar->tx_cmd_urbs, 0);
+        atomic_set(&ar->tx_anch_urbs, 0);
+        atomic_set(&ar->rx_work_urbs, 0);
+        atomic_set(&ar->rx_anch_urbs, 0);
+        atomic_set(&ar->rx_pool_urbs, 0);
+
+        usb_get_dev(ar->udev);
+
+        carl9170_set_state(ar, CARL9170_STOPPED);
+
+        return request_firmware_nowait(THIS_MODULE, 1, CARL9170FW_NAME,
+                &ar->udev->dev, GFP_KERNEL, ar, carl9170_usb_firmware_step2);
+}
+
+static void carl9170_usb_disconnect(struct usb_interface *intf)
+{
+        struct ar9170 *ar = usb_get_intfdata(intf);
+        struct usb_device *udev;
+
+        if (WARN_ON(!ar))
+                return;
+
+        udev = ar->udev;
+        wait_for_completion(&ar->fw_load_wait);
+
+        if (IS_INITIALIZED(ar)) {
+                carl9170_reboot(ar);
+                carl9170_usb_stop(ar);
+        }
+
+        carl9170_usb_cancel_urbs(ar);
+        carl9170_unregister(ar);
+
+        usb_set_intfdata(intf, NULL);
+
+        carl9170_release_firmware(ar);
+        carl9170_free(ar);
+        usb_put_dev(udev);
+}
+
+#ifdef CONFIG_PM
+static int carl9170_usb_suspend(struct usb_interface *intf,
+                                pm_message_t message)
+{
+        struct ar9170 *ar = usb_get_intfdata(intf);
+
+        if (!ar)
+                return -ENODEV;
+
+        carl9170_usb_cancel_urbs(ar);
+
+        return 0;
+}
+
+static int carl9170_usb_resume(struct usb_interface *intf)
+{
+        struct ar9170 *ar = usb_get_intfdata(intf);
+        int err;
+
+        if (!ar)
+                return -ENODEV;
+
+        usb_unpoison_anchored_urbs(&ar->rx_anch);
+        carl9170_set_state(ar, CARL9170_STOPPED);
+
+        /*
+         * The USB documentation demands that [for suspend] all traffic
+         * to and from the device has to stop. This would be fine, but
+         * there's a catch: the device[usb phy] does not come back.
+         *
+         * Upon resume the firmware will "kill" itself and the
+         * boot-code sorts out the magic voodoo.
+         * Not very nice, but there's not much what could go wrong.
+         */
+        msleep(1100);
+
+        err = carl9170_usb_init_device(ar);
+        if (err)
+                goto err_unrx;
+
+        return 0;
+
+err_unrx:
+        carl9170_usb_cancel_urbs(ar);
+
+        return err;
+}
+#endif /* CONFIG_PM */
+
+static struct usb_driver carl9170_driver = {
+        .name = KBUILD_MODNAME,
+        .probe = carl9170_usb_probe,
+        .disconnect = carl9170_usb_disconnect,
+        .id_table = carl9170_usb_ids,
+        .soft_unbind = 1,
+#ifdef CONFIG_PM
+        .suspend = carl9170_usb_suspend,
+        .resume = carl9170_usb_resume,
+        .reset_resume = carl9170_usb_resume,
+#endif /* CONFIG_PM */
+};
+
+static int __init carl9170_usb_init(void)
+{
+        return usb_register(&carl9170_driver);
+}
+
+static void __exit carl9170_usb_exit(void)
+{
+        usb_deregister(&carl9170_driver);
+}
+
+module_init(carl9170_usb_init);
+module_exit(carl9170_usb_exit);
diff --git a/drivers/net/wireless/ath/carl9170/version.h b/drivers/net/wireless/ath/carl9170/version.h
new file mode 100644
index 000000000000..15095c035169
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/version.h
@@ -0,0 +1,7 @@
+#ifndef __CARL9170_SHARED_VERSION_H
+#define __CARL9170_SHARED_VERSION_H
+#define CARL9170FW_VERSION_YEAR 11
+#define CARL9170FW_VERSION_MONTH 1
+#define CARL9170FW_VERSION_DAY 22
+#define CARL9170FW_VERSION_GIT "1.9.2"
+#endif /* __CARL9170_SHARED_VERSION_H */
diff --git a/drivers/net/wireless/ath/carl9170/wlan.h b/drivers/net/wireless/ath/carl9170/wlan.h
new file mode 100644
index 000000000000..9e1324b67e08
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/wlan.h
@@ -0,0 +1,438 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * RX/TX meta descriptor format
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_WLAN_H
+#define __CARL9170_SHARED_WLAN_H
+
+#include "fwcmd.h"
+
+#define AR9170_RX_PHY_RATE_CCK_1M               0x0a
+#define AR9170_RX_PHY_RATE_CCK_2M               0x14
+#define AR9170_RX_PHY_RATE_CCK_5M               0x37
+#define AR9170_RX_PHY_RATE_CCK_11M              0x6e
+
+#define AR9170_ENC_ALG_NONE                     0x0
+#define AR9170_ENC_ALG_WEP64                    0x1
+#define AR9170_ENC_ALG_TKIP                     0x2
+#define AR9170_ENC_ALG_AESCCMP                  0x4
+#define AR9170_ENC_ALG_WEP128                   0x5
+#define AR9170_ENC_ALG_WEP256                   0x6
+#define AR9170_ENC_ALG_CENC                     0x7
+
+#define AR9170_RX_ENC_SOFTWARE                  0x8
+
+#define AR9170_RX_STATUS_MODULATION             0x03
+#define AR9170_RX_STATUS_MODULATION_S           0
+#define AR9170_RX_STATUS_MODULATION_CCK         0x00
+#define AR9170_RX_STATUS_MODULATION_OFDM        0x01
+#define AR9170_RX_STATUS_MODULATION_HT          0x02
+#define AR9170_RX_STATUS_MODULATION_DUPOFDM     0x03
+
+/* depends on modulation */
+#define AR9170_RX_STATUS_SHORT_PREAMBLE         0x08
+#define AR9170_RX_STATUS_GREENFIELD             0x08
+
+#define AR9170_RX_STATUS_MPDU                   0x30
+#define AR9170_RX_STATUS_MPDU_S                 4
+#define AR9170_RX_STATUS_MPDU_SINGLE            0x00
+#define AR9170_RX_STATUS_MPDU_FIRST             0x20
+#define AR9170_RX_STATUS_MPDU_MIDDLE            0x30
+#define AR9170_RX_STATUS_MPDU_LAST              0x10
+
+#define AR9170_RX_STATUS_CONT_AGGR              0x40
+#define AR9170_RX_STATUS_TOTAL_ERROR            0x80
+
+#define AR9170_RX_ERROR_RXTO                    0x01
+#define AR9170_RX_ERROR_OVERRUN                 0x02
+#define AR9170_RX_ERROR_DECRYPT                 0x04
+#define AR9170_RX_ERROR_FCS                     0x08
+#define AR9170_RX_ERROR_WRONG_RA                0x10
+#define AR9170_RX_ERROR_PLCP                    0x20
+#define AR9170_RX_ERROR_MMIC                    0x40
+
+/* these are either-or */
+#define AR9170_TX_MAC_PROT_RTS                  0x0001
+#define AR9170_TX_MAC_PROT_CTS                  0x0002
+#define AR9170_TX_MAC_PROT                      0x0003
+
+#define AR9170_TX_MAC_NO_ACK                    0x0004
+/* if unset, MAC will only do SIFS space before frame */
+#define AR9170_TX_MAC_BACKOFF                   0x0008
+#define AR9170_TX_MAC_BURST                     0x0010
+#define AR9170_TX_MAC_AGGR                      0x0020
+
+/* encryption is a two-bit field */
+#define AR9170_TX_MAC_ENCR_NONE                 0x0000
+#define AR9170_TX_MAC_ENCR_RC4                  0x0040
+#define AR9170_TX_MAC_ENCR_CENC                 0x0080
+#define AR9170_TX_MAC_ENCR_AES                  0x00c0
+
+#define AR9170_TX_MAC_MMIC                      0x0100
+#define AR9170_TX_MAC_HW_DURATION               0x0200
+#define AR9170_TX_MAC_QOS_S                     10
+#define AR9170_TX_MAC_QOS                       0x0c00
+#define AR9170_TX_MAC_DISABLE_TXOP              0x1000
+#define AR9170_TX_MAC_TXOP_RIFS                 0x2000
+#define AR9170_TX_MAC_IMM_BA                    0x4000
+
+/* either-or */
+#define AR9170_TX_PHY_MOD_CCK                   0x00000000
+#define AR9170_TX_PHY_MOD_OFDM                  0x00000001
+#define AR9170_TX_PHY_MOD_HT                    0x00000002
+
+/* depends on modulation */
+#define AR9170_TX_PHY_SHORT_PREAMBLE            0x00000004
+#define AR9170_TX_PHY_GREENFIELD                0x00000004
+
+#define AR9170_TX_PHY_BW_S                      3
+#define AR9170_TX_PHY_BW                        (3 << AR9170_TX_PHY_BW_SHIFT)
+#define AR9170_TX_PHY_BW_20MHZ                  0
+#define AR9170_TX_PHY_BW_40MHZ                  2
+#define AR9170_TX_PHY_BW_40MHZ_DUP              3
+
+#define AR9170_TX_PHY_TX_HEAVY_CLIP_S           6
+#define AR9170_TX_PHY_TX_HEAVY_CLIP             (7 << \
+                                                 AR9170_TX_PHY_TX_HEAVY_CLIP_S)
+
+#define AR9170_TX_PHY_TX_PWR_S                  9
+#define AR9170_TX_PHY_TX_PWR                    (0x3f << \
+                                                 AR9170_TX_PHY_TX_PWR_S)
+
+#define AR9170_TX_PHY_TXCHAIN_S                 15
+#define AR9170_TX_PHY_TXCHAIN                   (7 << \
+                                                 AR9170_TX_PHY_TXCHAIN_S)
+#define AR9170_TX_PHY_TXCHAIN_1                 1
+/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
+#define AR9170_TX_PHY_TXCHAIN_2                 5
+
+#define AR9170_TX_PHY_MCS_S                     18
+#define AR9170_TX_PHY_MCS                       (0x7f << \
+                                                 AR9170_TX_PHY_MCS_S)
+
+#define AR9170_TX_PHY_RATE_CCK_1M               0x0
+#define AR9170_TX_PHY_RATE_CCK_2M               0x1
+#define AR9170_TX_PHY_RATE_CCK_5M               0x2
+#define AR9170_TX_PHY_RATE_CCK_11M              0x3
+
+/* same as AR9170_RX_PHY_RATE */
+#define AR9170_TXRX_PHY_RATE_OFDM_6M            0xb
+#define AR9170_TXRX_PHY_RATE_OFDM_9M            0xf
+#define AR9170_TXRX_PHY_RATE_OFDM_12M           0xa
+#define AR9170_TXRX_PHY_RATE_OFDM_18M           0xe
+#define AR9170_TXRX_PHY_RATE_OFDM_24M           0x9
+#define AR9170_TXRX_PHY_RATE_OFDM_36M           0xd
+#define AR9170_TXRX_PHY_RATE_OFDM_48M           0x8
+#define AR9170_TXRX_PHY_RATE_OFDM_54M           0xc
+
+#define AR9170_TXRX_PHY_RATE_HT_MCS0            0x0
+#define AR9170_TXRX_PHY_RATE_HT_MCS1            0x1
+#define AR9170_TXRX_PHY_RATE_HT_MCS2            0x2
+#define AR9170_TXRX_PHY_RATE_HT_MCS3            0x3
+#define AR9170_TXRX_PHY_RATE_HT_MCS4            0x4
+#define AR9170_TXRX_PHY_RATE_HT_MCS5            0x5
+#define AR9170_TXRX_PHY_RATE_HT_MCS6            0x6
+#define AR9170_TXRX_PHY_RATE_HT_MCS7            0x7
+#define AR9170_TXRX_PHY_RATE_HT_MCS8            0x8
+#define AR9170_TXRX_PHY_RATE_HT_MCS9            0x9
+#define AR9170_TXRX_PHY_RATE_HT_MCS10           0xa
+#define AR9170_TXRX_PHY_RATE_HT_MCS11           0xb
+#define AR9170_TXRX_PHY_RATE_HT_MCS12           0xc
+#define AR9170_TXRX_PHY_RATE_HT_MCS13           0xd
+#define AR9170_TXRX_PHY_RATE_HT_MCS14           0xe
+#define AR9170_TXRX_PHY_RATE_HT_MCS15           0xf
+
+#define AR9170_TX_PHY_SHORT_GI                  0x80000000
+
+#ifdef __CARL9170FW__
+struct ar9170_tx_hw_mac_control {
+        union {
+                struct {
+                        /*
+                         * Beware of compiler bugs in all gcc pre 4.4!
+                         */
+
+                        u8 erp_prot:2;
+                        u8 no_ack:1;
+                        u8 backoff:1;
+                        u8 burst:1;
+                        u8 ampdu:1;
+
+                        u8 enc_mode:2;
+
+                        u8 hw_mmic:1;
+                        u8 hw_duration:1;
+
+                        u8 qos_queue:2;
+
+                        u8 disable_txop:1;
+                        u8 txop_rifs:1;
+
+                        u8 ba_end:1;
+                        u8 probe:1;
+                } __packed;
+
+                __le16 set;
+        } __packed;
+} __packed;
+
+struct ar9170_tx_hw_phy_control {
+        union {
+                struct {
+                        /*
+                         * Beware of compiler bugs in all gcc pre 4.4!
+                         */
+
+                        u8 modulation:2;
+                        u8 preamble:1;
+                        u8 bandwidth:2;
+                        u8:1;
+                        u8 heavy_clip:3;
+                        u8 tx_power:6;
+                        u8 chains:3;
+                        u8 mcs:7;
+                        u8:6;
+                        u8 short_gi:1;
+                } __packed;
+
+                __le32 set;
+        } __packed;
+} __packed;
+
+struct ar9170_tx_rate_info {
+        u8 tries:3;
+        u8 erp_prot:2;
+        u8 ampdu:1;
+        u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
+} __packed;
+
+struct carl9170_tx_superdesc {
+        __le16 len;
+        u8 rix;
+        u8 cnt;
+        u8 cookie;
+        u8 ampdu_density:3;
+        u8 ampdu_factor:2;
+        u8 ampdu_commit_density:1;
+        u8 ampdu_commit_factor:1;
+        u8 ampdu_unused_bit:1;
+        u8 queue:2;
+        u8 assign_seq:1;
+        u8 vif_id:3;
+        u8 fill_in_tsf:1;
+        u8 cab:1;
+        u8 padding2;
+        struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES];
+        struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
+} __packed;
+
+struct ar9170_tx_hwdesc {
+        __le16 length;
+        struct ar9170_tx_hw_mac_control mac;
+        struct ar9170_tx_hw_phy_control phy;
+} __packed;
+
+struct ar9170_tx_frame {
+        struct ar9170_tx_hwdesc hdr;
+
+        union {
+                struct ieee80211_hdr i3e;
+                u8 payload[0];
+        } data;
+} __packed;
+
+struct carl9170_tx_superframe {
+        struct carl9170_tx_superdesc s;
+        struct ar9170_tx_frame f;
+} __packed;
+
+#endif /* __CARL9170FW__ */
+
+struct _ar9170_tx_hwdesc {
+        __le16 length;
+        __le16 mac_control;
+        __le32 phy_control;
+} __packed;
+
+#define CARL9170_TX_SUPER_AMPDU_DENSITY_S               0
+#define CARL9170_TX_SUPER_AMPDU_DENSITY                 0x7
+#define CARL9170_TX_SUPER_AMPDU_FACTOR                  0x18
+#define CARL9170_TX_SUPER_AMPDU_FACTOR_S                3
+#define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY          0x20
+#define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S        5
+#define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR           0x40
+#define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S         6
+
+#define CARL9170_TX_SUPER_MISC_QUEUE                    0x3
+#define CARL9170_TX_SUPER_MISC_QUEUE_S                  0
+#define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ               0x4
+#define CARL9170_TX_SUPER_MISC_VIF_ID                   0x38
+#define CARL9170_TX_SUPER_MISC_VIF_ID_S                 3
+#define CARL9170_TX_SUPER_MISC_FILL_IN_TSF              0x40
+#define CARL9170_TX_SUPER_MISC_CAB                      0x80
+
+#define CARL9170_TX_SUPER_RI_TRIES                      0x7
+#define CARL9170_TX_SUPER_RI_TRIES_S                    0
+#define CARL9170_TX_SUPER_RI_ERP_PROT                   0x18
+#define CARL9170_TX_SUPER_RI_ERP_PROT_S                 3
+#define CARL9170_TX_SUPER_RI_AMPDU                      0x20
+#define CARL9170_TX_SUPER_RI_AMPDU_S                    5
+
+struct _carl9170_tx_superdesc {
+        __le16 len;
+        u8 rix;
+        u8 cnt;
+        u8 cookie;
+        u8 ampdu_settings;
+        u8 misc;
+        u8 padding;
+        u8 ri[CARL9170_TX_MAX_RATES];
+        __le32 rr[CARL9170_TX_MAX_RETRY_RATES];
+} __packed;
+
+struct _carl9170_tx_superframe {
+        struct _carl9170_tx_superdesc s;
+        struct _ar9170_tx_hwdesc f;
+        u8 frame_data[0];
+} __packed;
+
+#define CARL9170_TX_SUPERDESC_LEN               24
+#define AR9170_TX_HWDESC_LEN                    8
+#define CARL9170_TX_SUPERFRAME_LEN              (CARL9170_TX_SUPERDESC_LEN + \
+                                                 AR9170_TX_HWDESC_LEN)
+
+struct ar9170_rx_head {
+        u8 plcp[12];
+} __packed;
+
+#define AR9170_RX_HEAD_LEN                      12
+
+struct ar9170_rx_phystatus {
+        union {
+                struct {
+                        u8 rssi_ant0, rssi_ant1, rssi_ant2,
+                                rssi_ant0x, rssi_ant1x, rssi_ant2x,
+                                rssi_combined;
+                } __packed;
+                u8 rssi[7];
+        } __packed;
+
+        u8 evm_stream0[6], evm_stream1[6];
+        u8 phy_err;
+} __packed;
+
+#define AR9170_RX_PHYSTATUS_LEN                 20
+
+struct ar9170_rx_macstatus {
+        u8 SAidx, DAidx;
+        u8 error;
+        u8 status;
+} __packed;
+
+#define AR9170_RX_MACSTATUS_LEN                 4
+
+struct ar9170_rx_frame_single {
+        struct ar9170_rx_head phy_head;
+        struct ieee80211_hdr i3e;
+        struct ar9170_rx_phystatus phy_tail;
+        struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame_head {
+        struct ar9170_rx_head phy_head;
+        struct ieee80211_hdr i3e;
+        struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame_middle {
+        struct ieee80211_hdr i3e;
+        struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame_tail {
+        struct ieee80211_hdr i3e;
+        struct ar9170_rx_phystatus phy_tail;
+        struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame {
+        union {
+                struct ar9170_rx_frame_single single;
+                struct ar9170_rx_frame_head head;
+                struct ar9170_rx_frame_middle middle;
+                struct ar9170_rx_frame_tail tail;
+        } __packed;
+} __packed;
+
+static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
+{
+        return (t->SAidx & 0xc0) >> 4 |
+               (t->DAidx & 0xc0) >> 6;
+}
+
+enum ar9170_txq {
+        AR9170_TXQ_BE,
+
+        AR9170_TXQ_VI,
+        AR9170_TXQ_VO,
+        AR9170_TXQ_BK,
+
+        __AR9170_NUM_TXQ,
+};
+
+/*
+ * This is an workaround for several undocumented bugs.
+ * Don't mess with the QoS/AC <-> HW Queue map, if you don't
+ * know what you are doing.
+ *
+ * Known problems [hardware]:
+ *  * The MAC does not aggregate frames on anything other
+ *    than the first HW queue.
+ *  * when an AMPDU is placed [in the first hw queue] and
+ *    additional frames are already queued on a different
+ *    hw queue, the MAC will ALWAYS freeze.
+ *
+ * In a nutshell: The hardware can either do QoS or
+ * Aggregation but not both at the same time. As a
+ * result, this makes the device pretty much useless
+ * for any serious 802.11n setup.
+ */
+static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };
+
+#define AR9170_TXQ_DEPTH                        32
+
+#endif /* __CARL9170_SHARED_WLAN_H */
diff --git a/drivers/net/wireless/ath/debug.c b/drivers/net/wireless/ath/debug.c
index 53e77bd131b9..5367b1086e09 100644
--- a/drivers/net/wireless/ath/debug.c
+++ b/drivers/net/wireless/ath/debug.c
@@ -15,18 +15,32 @@
  */
 
 #include "ath.h"
-#include "debug.h"
 
-void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
+const char *ath_opmode_to_string(enum nl80211_iftype opmode)
 {
-        va_list args;
-
-        if (likely(!(common->debug_mask & dbg_mask)))
-                return;
-
-        va_start(args, fmt);
-        printk(KERN_DEBUG "ath: ");
-        vprintk(fmt, args);
-        va_end(args);
+        switch (opmode) {
+        case NL80211_IFTYPE_UNSPECIFIED:
+                return "UNSPEC";
+        case NL80211_IFTYPE_ADHOC:
+                return "ADHOC";
+        case NL80211_IFTYPE_STATION:
+                return "STATION";
+        case NL80211_IFTYPE_AP:
+                return "AP";
+        case NL80211_IFTYPE_AP_VLAN:
+                return "AP-VLAN";
+        case NL80211_IFTYPE_WDS:
+                return "WDS";
+        case NL80211_IFTYPE_MONITOR:
+                return "MONITOR";
+        case NL80211_IFTYPE_MESH_POINT:
+                return "MESH";
+        case NL80211_IFTYPE_P2P_CLIENT:
+                return "P2P-CLIENT";
+        case NL80211_IFTYPE_P2P_GO:
+                return "P2P-GO";
+        default:
+                return "UNKNOWN";
+        }
 }
-EXPORT_SYMBOL(ath_print);
+EXPORT_SYMBOL(ath_opmode_to_string);
diff --git a/drivers/net/wireless/ath/debug.h b/drivers/net/wireless/ath/debug.h
deleted file mode 100644
index 873bf526e11f..000000000000
--- a/drivers/net/wireless/ath/debug.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef ATH_DEBUG_H
-#define ATH_DEBUG_H
-
-#include "ath.h"
-
-/**
- * enum ath_debug_level - atheros wireless debug level
- *
- * @ATH_DBG_RESET: reset processing
- * @ATH_DBG_QUEUE: hardware queue management
- * @ATH_DBG_EEPROM: eeprom processing
- * @ATH_DBG_CALIBRATE: periodic calibration
- * @ATH_DBG_INTERRUPT: interrupt processing
- * @ATH_DBG_REGULATORY: regulatory processing
- * @ATH_DBG_ANI: adaptive noise immunitive processing
- * @ATH_DBG_XMIT: basic xmit operation
- * @ATH_DBG_BEACON: beacon handling
- * @ATH_DBG_CONFIG: configuration of the hardware
- * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
- * @ATH_DBG_PS: power save processing
- * @ATH_DBG_HWTIMER: hardware timer handling
- * @ATH_DBG_BTCOEX: bluetooth coexistance
- * @ATH_DBG_ANY: enable all debugging
- *
- * The debug level is used to control the amount and type of debugging output
- * we want to see. Each driver has its own method for enabling debugging and
- * modifying debug level states -- but this is typically done through a
- * module parameter 'debug' along with a respective 'debug' debugfs file
- * entry.
- */
-enum ATH_DEBUG {
-        ATH_DBG_RESET           = 0x00000001,
-        ATH_DBG_QUEUE           = 0x00000002,
-        ATH_DBG_EEPROM          = 0x00000004,
-        ATH_DBG_CALIBRATE       = 0x00000008,
-        ATH_DBG_INTERRUPT       = 0x00000010,
-        ATH_DBG_REGULATORY      = 0x00000020,
-        ATH_DBG_ANI             = 0x00000040,
-        ATH_DBG_XMIT            = 0x00000080,
-        ATH_DBG_BEACON          = 0x00000100,
-        ATH_DBG_CONFIG          = 0x00000200,
-        ATH_DBG_FATAL           = 0x00000400,
-        ATH_DBG_PS              = 0x00000800,
-        ATH_DBG_HWTIMER         = 0x00001000,
-        ATH_DBG_BTCOEX          = 0x00002000,
-        ATH_DBG_WMI             = 0x00004000,
-        ATH_DBG_ANY             = 0xffffffff
-};
-
-#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
-
-#ifdef CONFIG_ATH_DEBUG
-void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
-        __attribute__ ((format (printf, 3, 4)));
-#else
-static inline void __attribute__ ((format (printf, 3, 4)))
-ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
-{
-}
-#endif /* CONFIG_ATH_DEBUG */
-
-#endif /* ATH_DEBUG_H */
diff --git a/drivers/net/wireless/ath/hw.c b/drivers/net/wireless/ath/hw.c
index a8f81ea09f14..3f508e59f146 100644
--- a/drivers/net/wireless/ath/hw.c
+++ b/drivers/net/wireless/ath/hw.c
@@ -43,7 +43,7 @@
  * set of  ~ ( MAC XOR BSSID ) for all bssids we handle.
  *
  * When you do this you are essentially computing the common bits of all your
- * BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with
+ * BSSes. Later it is assumed the hardware will "and" (&) the BSSID mask with
  * the MAC address to obtain the relevant bits and compare the result with
  * (frame's BSSID & mask) to see if they match.
  *
@@ -71,8 +71,8 @@
  *             On loop iteration for BSSID-02:
  *             bssid_mask &= ~(0001   ^   1001)
  *             bssid_mask =   (1010)  & ~(0001 ^ 1001)
- *             bssid_mask =   (1010)  & ~(1001)
- *             bssid_mask =   (1010)  &  (0110)
+ *             bssid_mask =   (1010)  & ~(1000)
+ *             bssid_mask =   (1010)  &  (0111)
  *             bssid_mask =   0010
  *
  * A bssid_mask of 0010 means "only pay attention to the second least
@@ -86,7 +86,7 @@
  * IFRAME-01:  0110
  *
  * An easy eye-inspeciton of this already should tell you that this frame
- * will not pass our check. This is beacuse the bssid_mask tells the
+ * will not pass our check. This is because the bssid_mask tells the
  * hardware to only look at the second least significant bit and the
  * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
  * as 1, which does not match 0.
@@ -102,11 +102,9 @@
  *
  * IFRAME-02:  0001 (we should allow)
  *
- *     allow = (0001 & 1010) == 1010
- *
  *     allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
  *  --> allow = (0001 & 0010) ==  (0010 & 0001) ? 1 :0;
- *  --> allow = (0010) == (0010)
+ *  --> allow = (0000) == (0000)
  *  --> allow = 1
  *
  * Other examples:
@@ -124,3 +122,62 @@ void ath_hw_setbssidmask(struct ath_common *common)
         REG_WRITE(ah, get_unaligned_le16(common->bssidmask + 4), AR_BSSMSKU);
 }
 EXPORT_SYMBOL(ath_hw_setbssidmask);
+
+
+/**
+ * ath_hw_cycle_counters_update - common function to update cycle counters
+ *
+ * @common: the ath_common struct for the device.
+ *
+ * This function is used to update all cycle counters in one place.
+ * It has to be called while holding common->cc_lock!
+ */
+void ath_hw_cycle_counters_update(struct ath_common *common)
+{
+        u32 cycles, busy, rx, tx;
+        void *ah = common->ah;
+
+        /* freeze */
+        REG_WRITE(ah, AR_MIBC_FMC, AR_MIBC);
+
+        /* read */
+        cycles = REG_READ(ah, AR_CCCNT);
+        busy = REG_READ(ah, AR_RCCNT);
+        rx = REG_READ(ah, AR_RFCNT);
+        tx = REG_READ(ah, AR_TFCNT);
+
+        /* clear */
+        REG_WRITE(ah, 0, AR_CCCNT);
+        REG_WRITE(ah, 0, AR_RFCNT);
+        REG_WRITE(ah, 0, AR_RCCNT);
+        REG_WRITE(ah, 0, AR_TFCNT);
+
+        /* unfreeze */
+        REG_WRITE(ah, 0, AR_MIBC);
+
+        /* update all cycle counters here */
+        common->cc_ani.cycles += cycles;
+        common->cc_ani.rx_busy += busy;
+        common->cc_ani.rx_frame += rx;
+        common->cc_ani.tx_frame += tx;
+
+        common->cc_survey.cycles += cycles;
+        common->cc_survey.rx_busy += busy;
+        common->cc_survey.rx_frame += rx;
+        common->cc_survey.tx_frame += tx;
+}
+EXPORT_SYMBOL(ath_hw_cycle_counters_update);
+
+int32_t ath_hw_get_listen_time(struct ath_common *common)
+{
+        struct ath_cycle_counters *cc = &common->cc_ani;
+        int32_t listen_time;
+
+        listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) /
+                      (common->clockrate * 1000);
+
+        memset(cc, 0, sizeof(*cc));
+
+        return listen_time;
+}
+EXPORT_SYMBOL(ath_hw_get_listen_time);
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
new file mode 100644
index 000000000000..a61ef3d6d89c
--- /dev/null
+++ b/drivers/net/wireless/ath/key.c
@@ -0,0 +1,604 @@
+/*
+ * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2010 Bruno Randolf <br1@einfach.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <asm/unaligned.h>
+#include <net/mac80211.h>
+
+#include "ath.h"
+#include "reg.h"
+
+#define REG_READ                        (common->ops->read)
+#define REG_WRITE(_ah, _reg, _val)      (common->ops->write)(_ah, _val, _reg)
+#define ENABLE_REGWRITE_BUFFER(_ah)                     \
+        if (common->ops->enable_write_buffer)           \
+                common->ops->enable_write_buffer((_ah));
+
+#define REGWRITE_BUFFER_FLUSH(_ah)                      \
+        if (common->ops->write_flush)                   \
+                common->ops->write_flush((_ah));
+
+
+#define IEEE80211_WEP_NKID      4       /* number of key ids */
+
+/************************/
+/* Key Cache Management */
+/************************/
+
+bool ath_hw_keyreset(struct ath_common *common, u16 entry)
+{
+        u32 keyType;
+        void *ah = common->ah;
+
+        if (entry >= common->keymax) {
+                ath_err(common, "keycache entry %u out of range\n", entry);
+                return false;
+        }
+
+        keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
+
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
+        REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
+        REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
+        REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
+        REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
+        REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
+        REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
+        REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
+
+        if (keyType == AR_KEYTABLE_TYPE_TKIP) {
+                u16 micentry = entry + 64;
+
+                REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
+                REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
+                REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
+                REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
+                if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) {
+                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
+                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
+                                  AR_KEYTABLE_TYPE_CLR);
+                }
+
+        }
+
+        REGWRITE_BUFFER_FLUSH(ah);
+
+        return true;
+}
+EXPORT_SYMBOL(ath_hw_keyreset);
+
+static bool ath_hw_keysetmac(struct ath_common *common,
+                             u16 entry, const u8 *mac)
+{
+        u32 macHi, macLo;
+        u32 unicast_flag = AR_KEYTABLE_VALID;
+        void *ah = common->ah;
+
+        if (entry >= common->keymax) {
+                ath_err(common, "keycache entry %u out of range\n", entry);
+                return false;
+        }
+
+        if (mac != NULL) {
+                /*
+                 * AR_KEYTABLE_VALID indicates that the address is a unicast
+                 * address, which must match the transmitter address for
+                 * decrypting frames.
+                 * Not setting this bit allows the hardware to use the key
+                 * for multicast frame decryption.
+                 */
+                if (mac[0] & 0x01)
+                        unicast_flag = 0;
+
+                macHi = (mac[5] << 8) | mac[4];
+                macLo = (mac[3] << 24) |
+                        (mac[2] << 16) |
+                        (mac[1] << 8) |
+                        mac[0];
+                macLo >>= 1;
+                macLo |= (macHi & 1) << 31;
+                macHi >>= 1;
+        } else {
+                macLo = macHi = 0;
+        }
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
+        REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
+
+        REGWRITE_BUFFER_FLUSH(ah);
+
+        return true;
+}
+
+static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
+                                      const struct ath_keyval *k,
+                                      const u8 *mac)
+{
+        void *ah = common->ah;
+        u32 key0, key1, key2, key3, key4;
+        u32 keyType;
+
+        if (entry >= common->keymax) {
+                ath_err(common, "keycache entry %u out of range\n", entry);
+                return false;
+        }
+
+        switch (k->kv_type) {
+        case ATH_CIPHER_AES_OCB:
+                keyType = AR_KEYTABLE_TYPE_AES;
+                break;
+        case ATH_CIPHER_AES_CCM:
+                if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) {
+                        ath_dbg(common, ATH_DBG_ANY,
+                                "AES-CCM not supported by this mac rev\n");
+                        return false;
+                }
+                keyType = AR_KEYTABLE_TYPE_CCM;
+                break;
+        case ATH_CIPHER_TKIP:
+                keyType = AR_KEYTABLE_TYPE_TKIP;
+                if (entry + 64 >= common->keymax) {
+                        ath_dbg(common, ATH_DBG_ANY,
+                                "entry %u inappropriate for TKIP\n", entry);
+                        return false;
+                }
+                break;
+        case ATH_CIPHER_WEP:
+                if (k->kv_len < WLAN_KEY_LEN_WEP40) {
+                        ath_dbg(common, ATH_DBG_ANY,
+                                "WEP key length %u too small\n", k->kv_len);
+                        return false;
+                }
+                if (k->kv_len <= WLAN_KEY_LEN_WEP40)
+                        keyType = AR_KEYTABLE_TYPE_40;
+                else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
+                        keyType = AR_KEYTABLE_TYPE_104;
+                else
+                        keyType = AR_KEYTABLE_TYPE_128;
+                break;
+        case ATH_CIPHER_CLR:
+                keyType = AR_KEYTABLE_TYPE_CLR;
+                break;
+        default:
+                ath_err(common, "cipher %u not supported\n", k->kv_type);
+                return false;
+        }
+
+        key0 = get_unaligned_le32(k->kv_val + 0);
+        key1 = get_unaligned_le16(k->kv_val + 4);
+        key2 = get_unaligned_le32(k->kv_val + 6);
+        key3 = get_unaligned_le16(k->kv_val + 10);
+        key4 = get_unaligned_le32(k->kv_val + 12);
+        if (k->kv_len <= WLAN_KEY_LEN_WEP104)
+                key4 &= 0xff;
+
+        /*
+         * Note: Key cache registers access special memory area that requires
+         * two 32-bit writes to actually update the values in the internal
+         * memory. Consequently, the exact order and pairs used here must be
+         * maintained.
+         */
+
+        if (keyType == AR_KEYTABLE_TYPE_TKIP) {
+                u16 micentry = entry + 64;
+
+                /*
+                 * Write inverted key[47:0] first to avoid Michael MIC errors
+                 * on frames that could be sent or received at the same time.
+                 * The correct key will be written in the end once everything
+                 * else is ready.
+                 */
+                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
+                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
+
+                /* Write key[95:48] */
+                REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
+                REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
+
+                /* Write key[127:96] and key type */
+                REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
+                REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
+
+                /* Write MAC address for the entry */
+                (void) ath_hw_keysetmac(common, entry, mac);
+
+                if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) {
+                        /*
+                         * TKIP uses two key cache entries:
+                         * Michael MIC TX/RX keys in the same key cache entry
+                         * (idx = main index + 64):
+                         * key0 [31:0] = RX key [31:0]
+                         * key1 [15:0] = TX key [31:16]
+                         * key1 [31:16] = reserved
+                         * key2 [31:0] = RX key [63:32]
+                         * key3 [15:0] = TX key [15:0]
+                         * key3 [31:16] = reserved
+                         * key4 [31:0] = TX key [63:32]
+                         */
+                        u32 mic0, mic1, mic2, mic3, mic4;
+
+                        mic0 = get_unaligned_le32(k->kv_mic + 0);
+                        mic2 = get_unaligned_le32(k->kv_mic + 4);
+                        mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
+                        mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
+                        mic4 = get_unaligned_le32(k->kv_txmic + 4);
+
+                        ENABLE_REGWRITE_BUFFER(ah);
+
+                        /* Write RX[31:0] and TX[31:16] */
+                        REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
+                        REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
+
+                        /* Write RX[63:32] and TX[15:0] */
+                        REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
+                        REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
+
+                        /* Write TX[63:32] and keyType(reserved) */
+                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
+                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
+                                  AR_KEYTABLE_TYPE_CLR);
+
+                        REGWRITE_BUFFER_FLUSH(ah);
+
+                } else {
+                        /*
+                         * TKIP uses four key cache entries (two for group
+                         * keys):
+                         * Michael MIC TX/RX keys are in different key cache
+                         * entries (idx = main index + 64 for TX and
+                         * main index + 32 + 96 for RX):
+                         * key0 [31:0] = TX/RX MIC key [31:0]
+                         * key1 [31:0] = reserved
+                         * key2 [31:0] = TX/RX MIC key [63:32]
+                         * key3 [31:0] = reserved
+                         * key4 [31:0] = reserved
+                         *
+                         * Upper layer code will call this function separately
+                         * for TX and RX keys when these registers offsets are
+                         * used.
+                         */
+                        u32 mic0, mic2;
+
+                        mic0 = get_unaligned_le32(k->kv_mic + 0);
+                        mic2 = get_unaligned_le32(k->kv_mic + 4);
+
+                        ENABLE_REGWRITE_BUFFER(ah);
+
+                        /* Write MIC key[31:0] */
+                        REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
+                        REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
+
+                        /* Write MIC key[63:32] */
+                        REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
+                        REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
+
+                        /* Write TX[63:32] and keyType(reserved) */
+                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
+                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
+                                  AR_KEYTABLE_TYPE_CLR);
+
+                        REGWRITE_BUFFER_FLUSH(ah);
+                }
+
+                ENABLE_REGWRITE_BUFFER(ah);
+
+                /* MAC address registers are reserved for the MIC entry */
+                REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
+                REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
+
+                /*
+                 * Write the correct (un-inverted) key[47:0] last to enable
+                 * TKIP now that all other registers are set with correct
+                 * values.
+                 */
+                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
+                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
+
+                REGWRITE_BUFFER_FLUSH(ah);
+        } else {
+                ENABLE_REGWRITE_BUFFER(ah);
+
+                /* Write key[47:0] */
+                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
+                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
+
+                /* Write key[95:48] */
+                REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
+                REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
+
+                /* Write key[127:96] and key type */
+                REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
+                REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
+
+                REGWRITE_BUFFER_FLUSH(ah);
+
+                /* Write MAC address for the entry */
+                (void) ath_hw_keysetmac(common, entry, mac);
+        }
+
+        return true;
+}
+
+static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
+                           struct ath_keyval *hk, const u8 *addr,
+                           bool authenticator)
+{
+        const u8 *key_rxmic;
+        const u8 *key_txmic;
+
+        key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
+        key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
+
+        if (addr == NULL) {
+                /*
+                 * Group key installation - only two key cache entries are used
+                 * regardless of splitmic capability since group key is only
+                 * used either for TX or RX.
+                 */
+                if (authenticator) {
+                        memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
+                        memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
+                } else {
+                        memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
+                        memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
+                }
+                return ath_hw_set_keycache_entry(common, keyix, hk, addr);
+        }
+        if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) {
+                /* TX and RX keys share the same key cache entry. */
+                memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
+                memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
+                return ath_hw_set_keycache_entry(common, keyix, hk, addr);
+        }
+
+        /* Separate key cache entries for TX and RX */
+
+        /* TX key goes at first index, RX key at +32. */
+        memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
+        if (!ath_hw_set_keycache_entry(common, keyix, hk, NULL)) {
+                /* TX MIC entry failed. No need to proceed further */
+                ath_err(common, "Setting TX MIC Key Failed\n");
+                return 0;
+        }
+
+        memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
+        /* XXX delete tx key on failure? */
+        return ath_hw_set_keycache_entry(common, keyix + 32, hk, addr);
+}
+
+static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
+{
+        int i;
+
+        for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
+                if (test_bit(i, common->keymap) ||
+                    test_bit(i + 64, common->keymap))
+                        continue; /* At least one part of TKIP key allocated */
+                if (!(common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) &&
+                    (test_bit(i + 32, common->keymap) ||
+                     test_bit(i + 64 + 32, common->keymap)))
+                        continue; /* At least one part of TKIP key allocated */
+
+                /* Found a free slot for a TKIP key */
+                return i;
+        }
+        return -1;
+}
+
+static int ath_reserve_key_cache_slot(struct ath_common *common,
+                                      u32 cipher)
+{
+        int i;
+
+        if (cipher == WLAN_CIPHER_SUITE_TKIP)
+                return ath_reserve_key_cache_slot_tkip(common);
+
+        /* First, try to find slots that would not be available for TKIP. */
+        if (!(common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED)) {
+                for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
+                        if (!test_bit(i, common->keymap) &&
+                            (test_bit(i + 32, common->keymap) ||
+                             test_bit(i + 64, common->keymap) ||
+                             test_bit(i + 64 + 32, common->keymap)))
+                                return i;
+                        if (!test_bit(i + 32, common->keymap) &&
+                            (test_bit(i, common->keymap) ||
+                             test_bit(i + 64, common->keymap) ||
+                             test_bit(i + 64 + 32, common->keymap)))
+                                return i + 32;
+                        if (!test_bit(i + 64, common->keymap) &&
+                            (test_bit(i , common->keymap) ||
+                             test_bit(i + 32, common->keymap) ||
+                             test_bit(i + 64 + 32, common->keymap)))
+                                return i + 64;
+                        if (!test_bit(i + 64 + 32, common->keymap) &&
+                            (test_bit(i, common->keymap) ||
+                             test_bit(i + 32, common->keymap) ||
+                             test_bit(i + 64, common->keymap)))
+                                return i + 64 + 32;
+                }
+        } else {
+                for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
+                        if (!test_bit(i, common->keymap) &&
+                            test_bit(i + 64, common->keymap))
+                                return i;
+                        if (test_bit(i, common->keymap) &&
+                            !test_bit(i + 64, common->keymap))
+                                return i + 64;
+                }
+        }
+
+        /* No partially used TKIP slots, pick any available slot */
+        for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
+                /* Do not allow slots that could be needed for TKIP group keys
+                 * to be used. This limitation could be removed if we know that
+                 * TKIP will not be used. */
+                if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
+                        continue;
+                if (!(common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED)) {
+                        if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
+                                continue;
+                        if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
+                                continue;
+                }
+
+                if (!test_bit(i, common->keymap))
+                        return i; /* Found a free slot for a key */
+        }
+
+        /* No free slot found */
+        return -1;
+}
+
+/*
+ * Configure encryption in the HW.
+ */
+int ath_key_config(struct ath_common *common,
+                          struct ieee80211_vif *vif,
+                          struct ieee80211_sta *sta,
+                          struct ieee80211_key_conf *key)
+{
+        struct ath_keyval hk;
+        const u8 *mac = NULL;
+        u8 gmac[ETH_ALEN];
+        int ret = 0;
+        int idx;
+
+        memset(&hk, 0, sizeof(hk));
+
+        switch (key->cipher) {
+        case 0:
+                hk.kv_type = ATH_CIPHER_CLR;
+                break;
+        case WLAN_CIPHER_SUITE_WEP40:
+        case WLAN_CIPHER_SUITE_WEP104:
+                hk.kv_type = ATH_CIPHER_WEP;
+                break;
+        case WLAN_CIPHER_SUITE_TKIP:
+                hk.kv_type = ATH_CIPHER_TKIP;
+                break;
+        case WLAN_CIPHER_SUITE_CCMP:
+                hk.kv_type = ATH_CIPHER_AES_CCM;
+                break;
+        default:
+                return -EOPNOTSUPP;
+        }
+
+        hk.kv_len = key->keylen;
+        if (key->keylen)
+                memcpy(hk.kv_val, key->key, key->keylen);
+
+        if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
+                switch (vif->type) {
+                case NL80211_IFTYPE_AP:
+                        memcpy(gmac, vif->addr, ETH_ALEN);
+                        gmac[0] |= 0x01;
+                        mac = gmac;
+                        idx = ath_reserve_key_cache_slot(common, key->cipher);
+                        break;
+                case NL80211_IFTYPE_ADHOC:
+                        if (!sta) {
+                                idx = key->keyidx;
+                                break;
+                        }
+                        memcpy(gmac, sta->addr, ETH_ALEN);
+                        gmac[0] |= 0x01;
+                        mac = gmac;
+                        idx = ath_reserve_key_cache_slot(common, key->cipher);
+                        break;
+                default:
+                        idx = key->keyidx;
+                        break;
+                }
+        } else if (key->keyidx) {
+                if (WARN_ON(!sta))
+                        return -EOPNOTSUPP;
+                mac = sta->addr;
+
+                if (vif->type != NL80211_IFTYPE_AP) {
+                        /* Only keyidx 0 should be used with unicast key, but
+                         * allow this for client mode for now. */
+                        idx = key->keyidx;
+                } else
+                        return -EIO;
+        } else {
+                if (WARN_ON(!sta))
+                        return -EOPNOTSUPP;
+                mac = sta->addr;
+
+                idx = ath_reserve_key_cache_slot(common, key->cipher);
+        }
+
+        if (idx < 0)
+                return -ENOSPC; /* no free key cache entries */
+
+        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
+                ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
+                                      vif->type == NL80211_IFTYPE_AP);
+        else
+                ret = ath_hw_set_keycache_entry(common, idx, &hk, mac);
+
+        if (!ret)
+                return -EIO;
+
+        set_bit(idx, common->keymap);
+        if (key->cipher == WLAN_CIPHER_SUITE_TKIP) {
+                set_bit(idx + 64, common->keymap);
+                set_bit(idx, common->tkip_keymap);
+                set_bit(idx + 64, common->tkip_keymap);
+                if (!(common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED)) {
+                        set_bit(idx + 32, common->keymap);
+                        set_bit(idx + 64 + 32, common->keymap);
+                        set_bit(idx + 32, common->tkip_keymap);
+                        set_bit(idx + 64 + 32, common->tkip_keymap);
+                }
+        }
+
+        return idx;
+}
+EXPORT_SYMBOL(ath_key_config);
+
+/*
+ * Delete Key.
+ */
+void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
+{
+        ath_hw_keyreset(common, key->hw_key_idx);
+        if (key->hw_key_idx < IEEE80211_WEP_NKID)
+                return;
+
+        clear_bit(key->hw_key_idx, common->keymap);
+        if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
+                return;
+
+        clear_bit(key->hw_key_idx + 64, common->keymap);
+
+        clear_bit(key->hw_key_idx, common->tkip_keymap);
+        clear_bit(key->hw_key_idx + 64, common->tkip_keymap);
+
+        if (!(common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED)) {
+                ath_hw_keyreset(common, key->hw_key_idx + 32);
+                clear_bit(key->hw_key_idx + 32, common->keymap);
+                clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
+
+                clear_bit(key->hw_key_idx + 32, common->tkip_keymap);
+                clear_bit(key->hw_key_idx + 64 + 32, common->tkip_keymap);
+        }
+}
+EXPORT_SYMBOL(ath_key_delete);
diff --git a/drivers/net/wireless/ath/main.c b/drivers/net/wireless/ath/main.c
index 487193f1de1a..c325202fdc5f 100644
--- a/drivers/net/wireless/ath/main.c
+++ b/drivers/net/wireless/ath/main.c
@@ -56,3 +56,23 @@ struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
         return skb;
 }
 EXPORT_SYMBOL(ath_rxbuf_alloc);
+
+int ath_printk(const char *level, struct ath_common *common,
+               const char *fmt, ...)
+{
+        struct va_format vaf;
+        va_list args;
+        int rtn;
+
+        va_start(args, fmt);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        rtn = printk("%sath: %pV", level, &vaf);
+
+        va_end(args);
+
+        return rtn;
+}
+EXPORT_SYMBOL(ath_printk);
diff --git a/drivers/net/wireless/ath/reg.h b/drivers/net/wireless/ath/reg.h
index dfe1fbec24f5..298e53f3fa48 100644
--- a/drivers/net/wireless/ath/reg.h
+++ b/drivers/net/wireless/ath/reg.h
@@ -17,6 +17,12 @@
 #ifndef ATH_REGISTERS_H
 #define ATH_REGISTERS_H
 
+#define AR_MIBC                 0x0040
+#define AR_MIBC_COW             0x00000001
+#define AR_MIBC_FMC             0x00000002
+#define AR_MIBC_CMC             0x00000004
+#define AR_MIBC_MCS             0x00000008
+
 /*
  * BSSID mask registers. See ath_hw_set_bssid_mask()
  * for detailed documentation about these registers.
@@ -24,4 +30,32 @@
 #define AR_BSSMSKL              0x80e0
 #define AR_BSSMSKU              0x80e4
 
+#define AR_TFCNT                0x80ec
+#define AR_RFCNT                0x80f0
+#define AR_RCCNT                0x80f4
+#define AR_CCCNT                0x80f8
+
+#define AR_KEYTABLE_0           0x8800
+#define AR_KEYTABLE(_n)         (AR_KEYTABLE_0 + ((_n)*32))
+#define AR_KEY_CACHE_SIZE       128
+#define AR_RSVD_KEYTABLE_ENTRIES 4
+#define AR_KEY_TYPE             0x00000007
+#define AR_KEYTABLE_TYPE_40     0x00000000
+#define AR_KEYTABLE_TYPE_104    0x00000001
+#define AR_KEYTABLE_TYPE_128    0x00000003
+#define AR_KEYTABLE_TYPE_TKIP   0x00000004
+#define AR_KEYTABLE_TYPE_AES    0x00000005
+#define AR_KEYTABLE_TYPE_CCM    0x00000006
+#define AR_KEYTABLE_TYPE_CLR    0x00000007
+#define AR_KEYTABLE_ANT         0x00000008
+#define AR_KEYTABLE_VALID       0x00008000
+#define AR_KEYTABLE_KEY0(_n)    (AR_KEYTABLE(_n) + 0)
+#define AR_KEYTABLE_KEY1(_n)    (AR_KEYTABLE(_n) + 4)
+#define AR_KEYTABLE_KEY2(_n)    (AR_KEYTABLE(_n) + 8)
+#define AR_KEYTABLE_KEY3(_n)    (AR_KEYTABLE(_n) + 12)
+#define AR_KEYTABLE_KEY4(_n)    (AR_KEYTABLE(_n) + 16)
+#define AR_KEYTABLE_TYPE(_n)    (AR_KEYTABLE(_n) + 20)
+#define AR_KEYTABLE_MAC0(_n)    (AR_KEYTABLE(_n) + 24)
+#define AR_KEYTABLE_MAC1(_n)    (AR_KEYTABLE(_n) + 28)
+
 #endif /* ATH_REGISTERS_H */
diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c
index 3f4244f56ce5..028310f263c8 100644
--- a/drivers/net/wireless/ath/regd.c
+++ b/drivers/net/wireless/ath/regd.c
@@ -97,8 +97,8 @@ static const struct ieee80211_regdomain ath_world_regdom_66_69 = {
         }
 };
 
-/* Can be used by 0x67, 0x6A and 0x68 */
-static const struct ieee80211_regdomain ath_world_regdom_67_68_6A = {
+/* Can be used by 0x67, 0x68, 0x6A and 0x6C */
+static const struct ieee80211_regdomain ath_world_regdom_67_68_6A_6C = {
         .n_reg_rules = 4,
         .alpha2 =  "99",
         .reg_rules = {
@@ -151,13 +151,21 @@ ieee80211_regdomain *ath_world_regdomain(struct ath_regulatory *reg)
         case 0x67:
         case 0x68:
         case 0x6A:
-                return &ath_world_regdom_67_68_6A;
+        case 0x6C:
+                return &ath_world_regdom_67_68_6A_6C;
         default:
                 WARN_ON(1);
                 return ath_default_world_regdomain();
         }
 }
 
+bool ath_is_49ghz_allowed(u16 regdomain)
+{
+        /* possibly more */
+        return regdomain == MKK9_MKKC;
+}
+EXPORT_SYMBOL(ath_is_49ghz_allowed);
+
 /* Frequency is one where radar detection is required */
 static bool ath_is_radar_freq(u16 center_freq)
 {
@@ -261,7 +269,7 @@ ath_reg_apply_active_scan_flags(struct wiphy *wiphy,
         }
 
         /*
-         * If a country IE has been recieved check its rule for this
+         * If a country IE has been received check its rule for this
          * channel first before enabling active scan. The passive scan
          * would have been enforced by the initial processing of our
          * custom regulatory domain.
@@ -326,6 +334,7 @@ static void ath_reg_apply_world_flags(struct wiphy *wiphy,
         case 0x63:
         case 0x66:
         case 0x67:
+        case 0x6C:
                 ath_reg_apply_beaconing_flags(wiphy, initiator);
                 break;
         case 0x68:
@@ -342,6 +351,14 @@ int ath_reg_notifier_apply(struct wiphy *wiphy,
         /* We always apply this */
         ath_reg_apply_radar_flags(wiphy);
 
+        /*
+         * This would happen when we have sent a custom regulatory request
+         * a world regulatory domain and the scheduler hasn't yet processed
+         * any pending requests in the queue.
+         */
+        if (!request)
+                return 0;
+
         switch (request->initiator) {
         case NL80211_REGDOM_SET_BY_DRIVER:
         case NL80211_REGDOM_SET_BY_CORE:
@@ -461,7 +478,7 @@ ath_regd_init_wiphy(struct ath_regulatory *reg,
                 wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
         } else {
                 /*
-                 * This gets applied in the case of the absense of CRDA,
+                 * This gets applied in the case of the absence of CRDA,
                  * it's our own custom world regulatory domain, similar to
                  * cfg80211's but we enable passive scanning.
                  */
diff --git a/drivers/net/wireless/ath/regd.h b/drivers/net/wireless/ath/regd.h
index 345dd9721b41..172f63f671cf 100644
--- a/drivers/net/wireless/ath/regd.h
+++ b/drivers/net/wireless/ath/regd.h
@@ -250,6 +250,7 @@ enum CountryCode {
 };
 
 bool ath_is_world_regd(struct ath_regulatory *reg);
+bool ath_is_49ghz_allowed(u16 redomain);
 int ath_regd_init(struct ath_regulatory *reg, struct wiphy *wiphy,
                   int (*reg_notifier)(struct wiphy *wiphy,
                   struct regulatory_request *request));
diff --git a/drivers/net/wireless/ath/regd_common.h b/drivers/net/wireless/ath/regd_common.h
index 248c670fdfbe..24b53839fc3a 100644
--- a/drivers/net/wireless/ath/regd_common.h
+++ b/drivers/net/wireless/ath/regd_common.h
@@ -86,6 +86,7 @@ enum EnumRd {
         WOR9_WORLD = 0x69,
         WORA_WORLD = 0x6A,
         WORB_WORLD = 0x6B,
+        WORC_WORLD = 0x6C,
 
         MKK3_MKKB = 0x80,
         MKK3_MKKA2 = 0x81,
@@ -195,6 +196,7 @@ static struct reg_dmn_pair_mapping regDomainPairs[] = {
         {APL9_WORLD, CTL_ETSI, CTL_ETSI},
 
         {APL3_FCCA, CTL_FCC, CTL_FCC},
+        {APL7_FCCA, CTL_FCC, CTL_FCC},
         {APL1_ETSIC, CTL_FCC, CTL_ETSI},
         {APL2_ETSIC, CTL_FCC, CTL_ETSI},
         {APL2_APLD, CTL_FCC, NO_CTL},
@@ -281,6 +283,7 @@ static struct reg_dmn_pair_mapping regDomainPairs[] = {
         {WOR9_WORLD, NO_CTL, NO_CTL},
         {WORA_WORLD, NO_CTL, NO_CTL},
         {WORB_WORLD, NO_CTL, NO_CTL},
+        {WORC_WORLD, NO_CTL, NO_CTL},
 };
 
 static struct country_code_to_enum_rd allCountries[] = {