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-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c1233
1 files changed, 583 insertions, 650 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 498aa28ea9e6..126a4eab35f3 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -27,11 +27,17 @@
27 27
28#include <linux/pci.h> /* To determine if a card is pci-e */ 28#include <linux/pci.h> /* To determine if a card is pci-e */
29#include <linux/log2.h> 29#include <linux/log2.h>
30#include <linux/platform_device.h>
30#include "ath5k.h" 31#include "ath5k.h"
31#include "reg.h" 32#include "reg.h"
32#include "base.h" 33#include "base.h"
33#include "debug.h" 34#include "debug.h"
34 35
36
37/******************\
38* Helper functions *
39\******************/
40
35/* 41/*
36 * Check if a register write has been completed 42 * Check if a register write has been completed
37 */ 43 */
@@ -53,146 +59,272 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
53 return (i <= 0) ? -EAGAIN : 0; 59 return (i <= 0) ? -EAGAIN : 0;
54} 60}
55 61
62
63/*************************\
64* Clock related functions *
65\*************************/
66
56/** 67/**
57 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 68 * ath5k_hw_htoclock - Translate usec to hw clock units
58 * 69 *
59 * @ah: the &struct ath5k_hw 70 * @ah: The &struct ath5k_hw
60 * @channel: the currently set channel upon reset 71 * @usec: value in microseconds
61 * 72 */
62 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 73unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
63 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset(). 74{
75 struct ath_common *common = ath5k_hw_common(ah);
76 return usec * common->clockrate;
77}
78
79/**
80 * ath5k_hw_clocktoh - Translate hw clock units to usec
81 * @clock: value in hw clock units
82 */
83unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
84{
85 struct ath_common *common = ath5k_hw_common(ah);
86 return clock / common->clockrate;
87}
88
89/**
90 * ath5k_hw_init_core_clock - Initialize core clock
64 * 91 *
65 * Since delta slope is floating point we split it on its exponent and 92 * @ah The &struct ath5k_hw
66 * mantissa and provide these values on hw.
67 * 93 *
68 * For more infos i think this patent is related 94 * Initialize core clock parameters (usec, usec32, latencies etc).
69 * http://www.freepatentsonline.com/7184495.html
70 */ 95 */
71static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 96static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
72 struct ieee80211_channel *channel)
73{ 97{
74 /* Get exponent and mantissa and set it */ 98 struct ieee80211_channel *channel = ah->ah_current_channel;
75 u32 coef_scaled, coef_exp, coef_man, 99 struct ath_common *common = ath5k_hw_common(ah);
76 ds_coef_exp, ds_coef_man, clock; 100 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
77
78 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
79 !(channel->hw_value & CHANNEL_OFDM));
80
81 /* Get coefficient
82 * ALGO: coef = (5 * clock / carrier_freq) / 2
83 * we scale coef by shifting clock value by 24 for
84 * better precision since we use integers */
85 /* TODO: Half/quarter rate */
86 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
87 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
88
89 /* Get exponent
90 * ALGO: coef_exp = 14 - highest set bit position */
91 coef_exp = ilog2(coef_scaled);
92
93 /* Doesn't make sense if it's zero*/
94 if (!coef_scaled || !coef_exp)
95 return -EINVAL;
96 101
97 /* Note: we've shifted coef_scaled by 24 */ 102 /*
98 coef_exp = 14 - (coef_exp - 24); 103 * Set core clock frequency
104 */
105 if (channel->hw_value & CHANNEL_5GHZ)
106 clock = 40; /* 802.11a */
107 else if (channel->hw_value & CHANNEL_CCK)
108 clock = 22; /* 802.11b */
109 else
110 clock = 44; /* 802.11g */
99 111
112 /* Use clock multiplier for non-default
113 * bwmode */
114 switch (ah->ah_bwmode) {
115 case AR5K_BWMODE_40MHZ:
116 clock *= 2;
117 break;
118 case AR5K_BWMODE_10MHZ:
119 clock /= 2;
120 break;
121 case AR5K_BWMODE_5MHZ:
122 clock /= 4;
123 break;
124 default:
125 break;
126 }
127
128 common->clockrate = clock;
100 129
101 /* Get mantissa (significant digits) 130 /*
102 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 131 * Set USEC parameters
103 coef_man = coef_scaled + 132 */
104 (1 << (24 - coef_exp - 1)); 133 /* Set USEC counter on PCU*/
134 usec = clock - 1;
135 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
105 136
106 /* Calculate delta slope coefficient exponent 137 /* Set usec duration on DCU */
107 * and mantissa (remove scaling) and set them on hw */ 138 if (ah->ah_version != AR5K_AR5210)
108 ds_coef_man = coef_man >> (24 - coef_exp); 139 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
109 ds_coef_exp = coef_exp - 16; 140 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
141 clock);
110 142
111 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 143 /* Set 32MHz USEC counter */
112 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 144 if ((ah->ah_radio == AR5K_RF5112) ||
113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 145 (ah->ah_radio == AR5K_RF5413) ||
114 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 146 (ah->ah_radio == AR5K_RF2316) ||
147 (ah->ah_radio == AR5K_RF2317))
148 /* Remain on 40MHz clock ? */
149 sclock = 40 - 1;
150 else
151 sclock = 32 - 1;
152 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
115 153
116 return 0; 154 /*
117} 155 * Set tx/rx latencies
156 */
157 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
158 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
159 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
118 160
161 /*
162 * Set default Tx frame to Tx data start delay
163 */
164 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
119 165
120/* 166 /*
121 * index into rates for control rates, we can set it up like this because 167 * 5210 initvals don't include usec settings
122 * this is only used for AR5212 and we know it supports G mode 168 * so we need to use magic values here for
123 */ 169 * tx/rx latencies
124static const unsigned int control_rates[] = 170 */
125 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }; 171 if (ah->ah_version == AR5K_AR5210) {
172 /* same for turbo */
173 txlat = AR5K_INIT_TX_LATENCY_5210;
174 rxlat = AR5K_INIT_RX_LATENCY_5210;
175 }
126 176
127/** 177 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
128 * ath5k_hw_write_rate_duration - fill rate code to duration table 178 /* 5311 has different tx/rx latency masks
129 * 179 * from 5211, since we deal 5311 the same
130 * @ah: the &struct ath5k_hw 180 * as 5211 when setting initvals, shift
131 * @mode: one of enum ath5k_driver_mode 181 * values here to their proper locations
132 * 182 *
133 * Write the rate code to duration table upon hw reset. This is a helper for 183 * Note: Initvals indicate tx/rx/ latencies
134 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on 184 * are the same for turbo mode */
135 * the hardware, based on current mode, for each rate. The rates which are 185 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
136 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 186 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
137 * different rate code so we write their value twice (one for long preample 187 } else
138 * and one for short). 188 switch (ah->ah_bwmode) {
189 case AR5K_BWMODE_10MHZ:
190 txlat = AR5K_REG_SM(txlat * 2,
191 AR5K_USEC_TX_LATENCY_5211);
192 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
193 AR5K_USEC_RX_LATENCY_5211);
194 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
195 break;
196 case AR5K_BWMODE_5MHZ:
197 txlat = AR5K_REG_SM(txlat * 4,
198 AR5K_USEC_TX_LATENCY_5211);
199 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
200 AR5K_USEC_RX_LATENCY_5211);
201 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
202 break;
203 case AR5K_BWMODE_40MHZ:
204 txlat = AR5K_INIT_TX_LAT_MIN;
205 rxlat = AR5K_REG_SM(rxlat / 2,
206 AR5K_USEC_RX_LATENCY_5211);
207 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
208 break;
209 default:
210 break;
211 }
212
213 usec_reg = (usec | sclock | txlat | rxlat);
214 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
215
216 /* On 5112 set tx frane to tx data start delay */
217 if (ah->ah_radio == AR5K_RF5112) {
218 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
219 AR5K_PHY_RF_CTL2_TXF2TXD_START,
220 txf2txs);
221 }
222}
223
224/*
225 * If there is an external 32KHz crystal available, use it
226 * as ref. clock instead of 32/40MHz clock and baseband clocks
227 * to save power during sleep or restore normal 32/40MHz
228 * operation.
139 * 229 *
140 * Note: Band doesn't matter here, if we set the values for OFDM it works 230 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
141 * on both a and g modes. So all we have to do is set values for all g rates 231 * 123 - 127) require delay on access.
142 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
143 * quarter rate mode, we need to use another set of bitrates (that's why we
144 * need the mode parameter) but we don't handle these proprietary modes yet.
145 */ 232 */
146static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, 233static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
147 unsigned int mode)
148{ 234{
149 struct ath5k_softc *sc = ah->ah_sc; 235 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
150 struct ieee80211_rate *rate; 236 u32 scal, spending;
151 unsigned int i; 237
238 /* Only set 32KHz settings if we have an external
239 * 32KHz crystal present */
240 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
241 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
242 enable) {
152 243
153 /* Write rate duration table */ 244 /* 1 usec/cycle */
154 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) { 245 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
155 u32 reg; 246 /* Set up tsf increment on each cycle */
156 u16 tx_time; 247 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
157 248
158 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]]; 249 /* Set baseband sleep control registers
250 * and sleep control rate */
251 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
159 252
160 /* Set ACK timeout */ 253 if ((ah->ah_radio == AR5K_RF5112) ||
161 reg = AR5K_RATE_DUR(rate->hw_value); 254 (ah->ah_radio == AR5K_RF5413) ||
255 (ah->ah_radio == AR5K_RF2316) ||
256 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
257 spending = 0x14;
258 else
259 spending = 0x18;
260 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
162 261
163 /* An ACK frame consists of 10 bytes. If you add the FCS, 262 if ((ah->ah_radio == AR5K_RF5112) ||
164 * which ieee80211_generic_frame_duration() adds, 263 (ah->ah_radio == AR5K_RF5413) ||
165 * its 14 bytes. Note we use the control rate and not the 264 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
166 * actual rate for this rate. See mac80211 tx.c 265 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
167 * ieee80211_duration() for a brief description of 266 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
168 * what rate we should choose to TX ACKs. */ 267 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
169 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw, 268 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
170 sc->vif, 10, rate)); 269 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
270 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
271 } else {
272 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
273 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
274 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
275 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
276 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
277 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
278 }
171 279
172 ath5k_hw_reg_write(ah, tx_time, reg); 280 /* Enable sleep clock operation */
281 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
282 AR5K_PCICFG_SLEEP_CLOCK_EN);
173 283
174 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 284 } else {
175 continue;
176 285
177 /* 286 /* Disable sleep clock operation and
178 * We're not distinguishing short preamble here, 287 * restore default parameters */
179 * This is true, all we'll get is a longer value here 288 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
180 * which is not necessarilly bad. We could use 289 AR5K_PCICFG_SLEEP_CLOCK_EN);
181 * export ieee80211_frame_duration() but that needs to be 290
182 * fixed first to be properly used by mac802111 drivers: 291 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
183 * 292 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
184 * - remove erp stuff and let the routine figure ofdm 293
185 * erp rates 294 /* Set DAC/ADC delays */
186 * - remove passing argument ieee80211_local as 295 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
187 * drivers don't have access to it 296 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
188 * - move drivers using ieee80211_generic_frame_duration() 297
189 * to this 298 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
190 */ 299 scal = AR5K_PHY_SCAL_32MHZ_2417;
191 ath5k_hw_reg_write(ah, tx_time, 300 else if (ee->ee_is_hb63)
192 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 301 scal = AR5K_PHY_SCAL_32MHZ_HB63;
302 else
303 scal = AR5K_PHY_SCAL_32MHZ;
304 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
305
306 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
307 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
308
309 if ((ah->ah_radio == AR5K_RF5112) ||
310 (ah->ah_radio == AR5K_RF5413) ||
311 (ah->ah_radio == AR5K_RF2316) ||
312 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
313 spending = 0x14;
314 else
315 spending = 0x18;
316 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
317
318 /* Set up tsf increment on each cycle */
319 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
193 } 320 }
194} 321}
195 322
323
324/*********************\
325* Reset/Sleep control *
326\*********************/
327
196/* 328/*
197 * Reset chipset 329 * Reset chipset
198 */ 330 */
@@ -236,6 +368,64 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
236} 368}
237 369
238/* 370/*
371 * Reset AHB chipset
372 * AR5K_RESET_CTL_PCU flag resets WMAC
373 * AR5K_RESET_CTL_BASEBAND flag resets WBB
374 */
375static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
376{
377 u32 mask = flags ? flags : ~0U;
378 volatile u32 *reg;
379 u32 regval;
380 u32 val = 0;
381
382 /* ah->ah_mac_srev is not available at this point yet */
383 if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
384 reg = (u32 *) AR5K_AR2315_RESET;
385 if (mask & AR5K_RESET_CTL_PCU)
386 val |= AR5K_AR2315_RESET_WMAC;
387 if (mask & AR5K_RESET_CTL_BASEBAND)
388 val |= AR5K_AR2315_RESET_BB_WARM;
389 } else {
390 reg = (u32 *) AR5K_AR5312_RESET;
391 if (to_platform_device(ah->ah_sc->dev)->id == 0) {
392 if (mask & AR5K_RESET_CTL_PCU)
393 val |= AR5K_AR5312_RESET_WMAC0;
394 if (mask & AR5K_RESET_CTL_BASEBAND)
395 val |= AR5K_AR5312_RESET_BB0_COLD |
396 AR5K_AR5312_RESET_BB0_WARM;
397 } else {
398 if (mask & AR5K_RESET_CTL_PCU)
399 val |= AR5K_AR5312_RESET_WMAC1;
400 if (mask & AR5K_RESET_CTL_BASEBAND)
401 val |= AR5K_AR5312_RESET_BB1_COLD |
402 AR5K_AR5312_RESET_BB1_WARM;
403 }
404 }
405
406 /* Put BB/MAC into reset */
407 regval = __raw_readl(reg);
408 __raw_writel(regval | val, reg);
409 regval = __raw_readl(reg);
410 udelay(100);
411
412 /* Bring BB/MAC out of reset */
413 __raw_writel(regval & ~val, reg);
414 regval = __raw_readl(reg);
415
416 /*
417 * Reset configuration register (for hw byte-swap). Note that this
418 * is only set for big endian. We do the necessary magic in
419 * AR5K_INIT_CFG.
420 */
421 if ((flags & AR5K_RESET_CTL_PCU) == 0)
422 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
423
424 return 0;
425}
426
427
428/*
239 * Sleep control 429 * Sleep control
240 */ 430 */
241static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 431static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
@@ -326,7 +516,7 @@ commit:
326 * register). After this MAC and Baseband are 516 * register). After this MAC and Baseband are
327 * disabled and a full reset is needed to come 517 * disabled and a full reset is needed to come
328 * back. This way we save as much power as possible 518 * back. This way we save as much power as possible
329 * without puting the card on full sleep. 519 * without putting the card on full sleep.
330 */ 520 */
331int ath5k_hw_on_hold(struct ath5k_hw *ah) 521int ath5k_hw_on_hold(struct ath5k_hw *ah)
332{ 522{
@@ -334,6 +524,9 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
334 u32 bus_flags; 524 u32 bus_flags;
335 int ret; 525 int ret;
336 526
527 if (ath5k_get_bus_type(ah) == ATH_AHB)
528 return 0;
529
337 /* Make sure device is awake */ 530 /* Make sure device is awake */
338 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 531 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
339 if (ret) { 532 if (ret) {
@@ -344,12 +537,12 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
344 /* 537 /*
345 * Put chipset on warm reset... 538 * Put chipset on warm reset...
346 * 539 *
347 * Note: puting PCI core on warm reset on PCI-E cards 540 * Note: putting PCI core on warm reset on PCI-E cards
348 * results card to hang and always return 0xffff... so 541 * results card to hang and always return 0xffff... so
349 * we ingore that flag for PCI-E cards. On PCI cards 542 * we ingore that flag for PCI-E cards. On PCI cards
350 * this flag gets cleared after 64 PCI clocks. 543 * this flag gets cleared after 64 PCI clocks.
351 */ 544 */
352 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 545 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
353 546
354 if (ah->ah_version == AR5K_AR5210) { 547 if (ah->ah_version == AR5K_AR5210) {
355 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 548 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
@@ -378,7 +571,6 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
378 571
379/* 572/*
380 * Bring up MAC + PHY Chips and program PLL 573 * Bring up MAC + PHY Chips and program PLL
381 * TODO: Half/Quarter rate support
382 */ 574 */
383int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 575int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
384{ 576{
@@ -390,22 +582,24 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
390 mode = 0; 582 mode = 0;
391 clock = 0; 583 clock = 0;
392 584
393 /* Wakeup the device */ 585 if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
394 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 586 /* Wakeup the device */
395 if (ret) { 587 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
396 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 588 if (ret) {
397 return ret; 589 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
590 return ret;
591 }
398 } 592 }
399 593
400 /* 594 /*
401 * Put chipset on warm reset... 595 * Put chipset on warm reset...
402 * 596 *
403 * Note: puting PCI core on warm reset on PCI-E cards 597 * Note: putting PCI core on warm reset on PCI-E cards
404 * results card to hang and always return 0xffff... so 598 * results card to hang and always return 0xffff... so
405 * we ingore that flag for PCI-E cards. On PCI cards 599 * we ingore that flag for PCI-E cards. On PCI cards
406 * this flag gets cleared after 64 PCI clocks. 600 * this flag gets cleared after 64 PCI clocks.
407 */ 601 */
408 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 602 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
409 603
410 if (ah->ah_version == AR5K_AR5210) { 604 if (ah->ah_version == AR5K_AR5210) {
411 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 605 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
@@ -413,8 +607,12 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
413 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 607 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
414 mdelay(2); 608 mdelay(2);
415 } else { 609 } else {
416 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 610 if (ath5k_get_bus_type(ah) == ATH_AHB)
417 AR5K_RESET_CTL_BASEBAND | bus_flags); 611 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
612 AR5K_RESET_CTL_BASEBAND);
613 else
614 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
615 AR5K_RESET_CTL_BASEBAND | bus_flags);
418 } 616 }
419 617
420 if (ret) { 618 if (ret) {
@@ -429,9 +627,15 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
429 return ret; 627 return ret;
430 } 628 }
431 629
432 /* ...clear reset control register and pull device out of 630 /* ...reset configuration regiter on Wisoc ...
433 * warm reset */ 631 * ...clear reset control register and pull device out of
434 if (ath5k_hw_nic_reset(ah, 0)) { 632 * warm reset on others */
633 if (ath5k_get_bus_type(ah) == ATH_AHB)
634 ret = ath5k_hw_wisoc_reset(ah, 0);
635 else
636 ret = ath5k_hw_nic_reset(ah, 0);
637
638 if (ret) {
435 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); 639 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
436 return -EIO; 640 return -EIO;
437 } 641 }
@@ -466,7 +670,8 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
466 * CCK headers) operation. We need to test 670 * CCK headers) operation. We need to test
467 * this, 5211 might support ofdm-only g after 671 * this, 5211 might support ofdm-only g after
468 * all, there are also initial register values 672 * all, there are also initial register values
469 * in the code for g mode (see initvals.c). */ 673 * in the code for g mode (see initvals.c).
674 */
470 if (ah->ah_version == AR5K_AR5211) 675 if (ah->ah_version == AR5K_AR5211)
471 mode |= AR5K_PHY_MODE_MOD_OFDM; 676 mode |= AR5K_PHY_MODE_MOD_OFDM;
472 else 677 else
@@ -479,6 +684,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
479 } else if (flags & CHANNEL_5GHZ) { 684 } else if (flags & CHANNEL_5GHZ) {
480 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 685 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
481 686
687 /* Different PLL setting for 5413 */
482 if (ah->ah_radio == AR5K_RF5413) 688 if (ah->ah_radio == AR5K_RF5413)
483 clock = AR5K_PHY_PLL_40MHZ_5413; 689 clock = AR5K_PHY_PLL_40MHZ_5413;
484 else 690 else
@@ -496,12 +702,29 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
496 return -EINVAL; 702 return -EINVAL;
497 } 703 }
498 704
499 if (flags & CHANNEL_TURBO) 705 /*XXX: Can bwmode be used with dynamic mode ?
500 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 706 * (I don't think it supports 44MHz) */
707 /* On 2425 initvals TURBO_SHORT is not pressent */
708 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
709 turbo = AR5K_PHY_TURBO_MODE |
710 (ah->ah_radio == AR5K_RF2425) ? 0 :
711 AR5K_PHY_TURBO_SHORT;
712 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
713 if (ah->ah_radio == AR5K_RF5413) {
714 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
715 AR5K_PHY_MODE_HALF_RATE :
716 AR5K_PHY_MODE_QUARTER_RATE;
717 } else if (ah->ah_version == AR5K_AR5212) {
718 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
719 AR5K_PHY_PLL_HALF_RATE :
720 AR5K_PHY_PLL_QUARTER_RATE;
721 }
722 }
723
501 } else { /* Reset the device */ 724 } else { /* Reset the device */
502 725
503 /* ...enable Atheros turbo mode if requested */ 726 /* ...enable Atheros turbo mode if requested */
504 if (flags & CHANNEL_TURBO) 727 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
505 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 728 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
506 AR5K_PHY_TURBO); 729 AR5K_PHY_TURBO);
507 } 730 }
@@ -522,107 +745,10 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
522 return 0; 745 return 0;
523} 746}
524 747
525/*
526 * If there is an external 32KHz crystal available, use it
527 * as ref. clock instead of 32/40MHz clock and baseband clocks
528 * to save power during sleep or restore normal 32/40MHz
529 * operation.
530 *
531 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
532 * 123 - 127) require delay on access.
533 */
534static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
535{
536 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
537 u32 scal, spending, usec32;
538
539 /* Only set 32KHz settings if we have an external
540 * 32KHz crystal present */
541 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
542 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
543 enable) {
544
545 /* 1 usec/cycle */
546 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
547 /* Set up tsf increment on each cycle */
548 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
549
550 /* Set baseband sleep control registers
551 * and sleep control rate */
552 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
553
554 if ((ah->ah_radio == AR5K_RF5112) ||
555 (ah->ah_radio == AR5K_RF5413) ||
556 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
557 spending = 0x14;
558 else
559 spending = 0x18;
560 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
561
562 if ((ah->ah_radio == AR5K_RF5112) ||
563 (ah->ah_radio == AR5K_RF5413) ||
564 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
565 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
566 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
567 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
568 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
569 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
570 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
571 } else {
572 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
573 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
574 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
575 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
576 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
577 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
578 }
579
580 /* Enable sleep clock operation */
581 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
582 AR5K_PCICFG_SLEEP_CLOCK_EN);
583
584 } else {
585
586 /* Disable sleep clock operation and
587 * restore default parameters */
588 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
589 AR5K_PCICFG_SLEEP_CLOCK_EN);
590
591 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
592 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
593
594 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
595 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
596
597 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
598 scal = AR5K_PHY_SCAL_32MHZ_2417;
599 else if (ee->ee_is_hb63)
600 scal = AR5K_PHY_SCAL_32MHZ_HB63;
601 else
602 scal = AR5K_PHY_SCAL_32MHZ;
603 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
604
605 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
606 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
607 748
608 if ((ah->ah_radio == AR5K_RF5112) || 749/**************************************\
609 (ah->ah_radio == AR5K_RF5413) || 750* Post-initvals register modifications *
610 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 751\**************************************/
611 spending = 0x14;
612 else
613 spending = 0x18;
614 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
615
616 if ((ah->ah_radio == AR5K_RF5112) ||
617 (ah->ah_radio == AR5K_RF5413))
618 usec32 = 39;
619 else
620 usec32 = 31;
621 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
622
623 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
624 }
625}
626 752
627/* TODO: Half/Quarter rate */ 753/* TODO: Half/Quarter rate */
628static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, 754static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
@@ -663,22 +789,10 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
663 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 789 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
664 AR5K_TXCFG_DCU_DBL_BUF_DIS); 790 AR5K_TXCFG_DCU_DBL_BUF_DIS);
665 791
666 /* Set DAC/ADC delays */
667 if (ah->ah_version == AR5K_AR5212) {
668 u32 scal;
669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
670 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
671 scal = AR5K_PHY_SCAL_32MHZ_2417;
672 else if (ee->ee_is_hb63)
673 scal = AR5K_PHY_SCAL_32MHZ_HB63;
674 else
675 scal = AR5K_PHY_SCAL_32MHZ;
676 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
677 }
678
679 /* Set fast ADC */ 792 /* Set fast ADC */
680 if ((ah->ah_radio == AR5K_RF5413) || 793 if ((ah->ah_radio == AR5K_RF5413) ||
681 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 794 (ah->ah_radio == AR5K_RF2317) ||
795 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
682 u32 fast_adc = true; 796 u32 fast_adc = true;
683 797
684 if (channel->center_freq == 2462 || 798 if (channel->center_freq == 2462 ||
@@ -706,33 +820,68 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
706 } 820 }
707 821
708 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 822 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
709 u32 usec_reg;
710 /* 5311 has different tx/rx latency masks
711 * from 5211, since we deal 5311 the same
712 * as 5211 when setting initvals, shift
713 * values here to their proper locations */
714 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
715 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
716 AR5K_USEC_32 |
717 AR5K_USEC_TX_LATENCY_5211 |
718 AR5K_REG_SM(29,
719 AR5K_USEC_RX_LATENCY_5210)),
720 AR5K_USEC_5211);
721 /* Clear QCU/DCU clock gating register */ 823 /* Clear QCU/DCU clock gating register */
722 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); 824 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
723 /* Set DAC/ADC delays */ 825 /* Set DAC/ADC delays */
724 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); 826 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
827 AR5K_PHY_SCAL);
725 /* Enable PCU FIFO corruption ECO */ 828 /* Enable PCU FIFO corruption ECO */
726 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 829 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
727 AR5K_DIAG_SW_ECO_ENABLE); 830 AR5K_DIAG_SW_ECO_ENABLE);
728 } 831 }
832
833 if (ah->ah_bwmode) {
834 /* Increase PHY switch and AGC settling time
835 * on turbo mode (ath5k_hw_commit_eeprom_settings
836 * will override settling time if available) */
837 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
838
839 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
840 AR5K_PHY_SETTLING_AGC,
841 AR5K_AGC_SETTLING_TURBO);
842
843 /* XXX: Initvals indicate we only increase
844 * switch time on AR5212, 5211 and 5210
845 * only change agc time (bug?) */
846 if (ah->ah_version == AR5K_AR5212)
847 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
848 AR5K_PHY_SETTLING_SWITCH,
849 AR5K_SWITCH_SETTLING_TURBO);
850
851 if (ah->ah_version == AR5K_AR5210) {
852 /* Set Frame Control Register */
853 ath5k_hw_reg_write(ah,
854 (AR5K_PHY_FRAME_CTL_INI |
855 AR5K_PHY_TURBO_MODE |
856 AR5K_PHY_TURBO_SHORT | 0x2020),
857 AR5K_PHY_FRAME_CTL_5210);
858 }
859 /* On 5413 PHY force window length for half/quarter rate*/
860 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
861 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
862 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
863 AR5K_PHY_FRAME_CTL_WIN_LEN,
864 3);
865 }
866 } else if (ah->ah_version == AR5K_AR5210) {
867 /* Set Frame Control Register for normal operation */
868 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
869 AR5K_PHY_FRAME_CTL_5210);
870 }
729} 871}
730 872
731static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, 873static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
732 struct ieee80211_channel *channel, u8 ee_mode) 874 struct ieee80211_channel *channel)
733{ 875{
734 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 876 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
735 s16 cck_ofdm_pwr_delta; 877 s16 cck_ofdm_pwr_delta;
878 u8 ee_mode;
879
880 /* TODO: Add support for AR5210 EEPROM */
881 if (ah->ah_version == AR5K_AR5210)
882 return;
883
884 ee_mode = ath5k_eeprom_mode_from_channel(channel);
736 885
737 /* Adjust power delta for channel 14 */ 886 /* Adjust power delta for channel 14 */
738 if (channel->center_freq == 2484) 887 if (channel->center_freq == 2484)
@@ -772,7 +921,7 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
772 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), 921 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
773 AR5K_PHY_NFTHRES); 922 AR5K_PHY_NFTHRES);
774 923
775 if ((channel->hw_value & CHANNEL_TURBO) && 924 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
776 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) { 925 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
777 /* Switch settling time (Turbo) */ 926 /* Switch settling time (Turbo) */
778 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 927 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
@@ -870,143 +1019,175 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
870 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); 1019 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
871} 1020}
872 1021
873/* 1022
874 * Main reset function 1023/*********************\
875 */ 1024* Main reset function *
1025\*********************/
1026
876int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1027int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
877 struct ieee80211_channel *channel, bool change_channel) 1028 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
878{ 1029{
879 struct ath_common *common = ath5k_hw_common(ah); 1030 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
880 u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo; 1031 u8 mode;
881 u32 phy_tst1;
882 u8 mode, freq, ee_mode;
883 int i, ret; 1032 int i, ret;
884 1033
885 ee_mode = 0;
886 staid1_flags = 0;
887 tsf_up = 0; 1034 tsf_up = 0;
888 tsf_lo = 0; 1035 tsf_lo = 0;
889 freq = 0;
890 mode = 0; 1036 mode = 0;
891 1037
892 /* 1038 /*
893 * Save some registers before a reset 1039 * Sanity check for fast flag
1040 * Fast channel change only available
1041 * on AR2413/AR5413.
894 */ 1042 */
895 /*DCU/Antenna selection not available on 5210*/ 1043 if (fast && (ah->ah_radio != AR5K_RF2413) &&
896 if (ah->ah_version != AR5K_AR5210) { 1044 (ah->ah_radio != AR5K_RF5413))
1045 fast = 0;
897 1046
898 switch (channel->hw_value & CHANNEL_MODES) { 1047 /* Disable sleep clock operation
899 case CHANNEL_A: 1048 * to avoid register access delay on certain
900 mode = AR5K_MODE_11A; 1049 * PHY registers */
901 freq = AR5K_INI_RFGAIN_5GHZ; 1050 if (ah->ah_version == AR5K_AR5212)
902 ee_mode = AR5K_EEPROM_MODE_11A; 1051 ath5k_hw_set_sleep_clock(ah, false);
903 break; 1052
904 case CHANNEL_G: 1053 /*
905 mode = AR5K_MODE_11G; 1054 * Stop PCU
906 freq = AR5K_INI_RFGAIN_2GHZ; 1055 */
907 ee_mode = AR5K_EEPROM_MODE_11G; 1056 ath5k_hw_stop_rx_pcu(ah);
908 break; 1057
909 case CHANNEL_B: 1058 /*
910 mode = AR5K_MODE_11B; 1059 * Stop DMA
911 freq = AR5K_INI_RFGAIN_2GHZ; 1060 *
912 ee_mode = AR5K_EEPROM_MODE_11B; 1061 * Note: If DMA didn't stop continue
913 break; 1062 * since only a reset will fix it.
914 case CHANNEL_T: 1063 */
915 mode = AR5K_MODE_11A_TURBO; 1064 ret = ath5k_hw_dma_stop(ah);
916 freq = AR5K_INI_RFGAIN_5GHZ; 1065
917 ee_mode = AR5K_EEPROM_MODE_11A; 1066 /* RF Bus grant won't work if we have pending
918 break; 1067 * frames */
919 case CHANNEL_TG: 1068 if (ret && fast) {
920 if (ah->ah_version == AR5K_AR5211) { 1069 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
921 ATH5K_ERR(ah->ah_sc, 1070 "DMA didn't stop, falling back to normal reset\n");
922 "TurboG mode not available on 5211"); 1071 fast = 0;
923 return -EINVAL; 1072 /* Non fatal, just continue with
924 } 1073 * normal reset */
925 mode = AR5K_MODE_11G_TURBO; 1074 ret = 0;
926 freq = AR5K_INI_RFGAIN_2GHZ; 1075 }
927 ee_mode = AR5K_EEPROM_MODE_11G; 1076
928 break; 1077 switch (channel->hw_value & CHANNEL_MODES) {
929 case CHANNEL_XR: 1078 case CHANNEL_A:
930 if (ah->ah_version == AR5K_AR5211) { 1079 mode = AR5K_MODE_11A;
931 ATH5K_ERR(ah->ah_sc, 1080 break;
932 "XR mode not available on 5211"); 1081 case CHANNEL_G:
933 return -EINVAL; 1082
934 } 1083 if (ah->ah_version <= AR5K_AR5211) {
935 mode = AR5K_MODE_XR;
936 freq = AR5K_INI_RFGAIN_5GHZ;
937 ee_mode = AR5K_EEPROM_MODE_11A;
938 break;
939 default:
940 ATH5K_ERR(ah->ah_sc, 1084 ATH5K_ERR(ah->ah_sc,
941 "invalid channel: %d\n", channel->center_freq); 1085 "G mode not available on 5210/5211");
942 return -EINVAL; 1086 return -EINVAL;
943 } 1087 }
944 1088
945 if (change_channel) { 1089 mode = AR5K_MODE_11G;
946 /* 1090 break;
947 * Save frame sequence count 1091 case CHANNEL_B:
948 * For revs. after Oahu, only save
949 * seq num for DCU 0 (Global seq num)
950 */
951 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
952 1092
953 for (i = 0; i < 10; i++) 1093 if (ah->ah_version < AR5K_AR5211) {
954 s_seq[i] = ath5k_hw_reg_read(ah, 1094 ATH5K_ERR(ah->ah_sc,
955 AR5K_QUEUE_DCU_SEQNUM(i)); 1095 "B mode not available on 5210");
1096 return -EINVAL;
1097 }
956 1098
957 } else { 1099 mode = AR5K_MODE_11B;
958 s_seq[0] = ath5k_hw_reg_read(ah, 1100 break;
959 AR5K_QUEUE_DCU_SEQNUM(0)); 1101 case CHANNEL_XR:
960 } 1102 if (ah->ah_version == AR5K_AR5211) {
1103 ATH5K_ERR(ah->ah_sc,
1104 "XR mode not available on 5211");
1105 return -EINVAL;
1106 }
1107 mode = AR5K_MODE_XR;
1108 break;
1109 default:
1110 ATH5K_ERR(ah->ah_sc,
1111 "invalid channel: %d\n", channel->center_freq);
1112 return -EINVAL;
1113 }
961 1114
962 /* TSF accelerates on AR5211 durring reset 1115 /*
963 * As a workaround save it here and restore 1116 * If driver requested fast channel change and DMA has stopped
964 * it later so that it's back in time after 1117 * go on. If it fails continue with a normal reset.
965 * reset. This way it'll get re-synced on the 1118 */
966 * next beacon without breaking ad-hoc. 1119 if (fast) {
967 * 1120 ret = ath5k_hw_phy_init(ah, channel, mode, true);
968 * On AR5212 TSF is almost preserved across a 1121 if (ret) {
969 * reset so it stays back in time anyway and 1122 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
970 * we don't have to save/restore it. 1123 "fast chan change failed, falling back to normal reset\n");
971 * 1124 /* Non fatal, can happen eg.
972 * XXX: Since this breaks power saving we have 1125 * on mode change */
973 * to disable power saving until we receive the 1126 ret = 0;
974 * next beacon, so we can resync beacon timers */ 1127 } else {
975 if (ah->ah_version == AR5K_AR5211) { 1128 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
976 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 1129 "fast chan change successful\n");
977 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 1130 return 0;
978 }
979 } 1131 }
1132 }
1133
1134 /*
1135 * Save some registers before a reset
1136 */
1137 if (ah->ah_version != AR5K_AR5210) {
1138 /*
1139 * Save frame sequence count
1140 * For revs. after Oahu, only save
1141 * seq num for DCU 0 (Global seq num)
1142 */
1143 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
980 1144
981 if (ah->ah_version == AR5K_AR5212) { 1145 for (i = 0; i < 10; i++)
982 /* Restore normal 32/40MHz clock operation 1146 s_seq[i] = ath5k_hw_reg_read(ah,
983 * to avoid register access delay on certain 1147 AR5K_QUEUE_DCU_SEQNUM(i));
984 * PHY registers */
985 ath5k_hw_set_sleep_clock(ah, false);
986 1148
987 /* Since we are going to write rf buffer 1149 } else {
988 * check if we have any pending gain_F 1150 s_seq[0] = ath5k_hw_reg_read(ah,
989 * optimization settings */ 1151 AR5K_QUEUE_DCU_SEQNUM(0));
990 if (change_channel && ah->ah_rf_banks != NULL) 1152 }
991 ath5k_hw_gainf_calibrate(ah); 1153
1154 /* TSF accelerates on AR5211 during reset
1155 * As a workaround save it here and restore
1156 * it later so that it's back in time after
1157 * reset. This way it'll get re-synced on the
1158 * next beacon without breaking ad-hoc.
1159 *
1160 * On AR5212 TSF is almost preserved across a
1161 * reset so it stays back in time anyway and
1162 * we don't have to save/restore it.
1163 *
1164 * XXX: Since this breaks power saving we have
1165 * to disable power saving until we receive the
1166 * next beacon, so we can resync beacon timers */
1167 if (ah->ah_version == AR5K_AR5211) {
1168 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1169 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
992 } 1170 }
993 } 1171 }
994 1172
1173
995 /*GPIOs*/ 1174 /*GPIOs*/
996 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & 1175 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
997 AR5K_PCICFG_LEDSTATE; 1176 AR5K_PCICFG_LEDSTATE;
998 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 1177 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
999 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 1178 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1000 1179
1001 /* AR5K_STA_ID1 flags, only preserve antenna 1180
1002 * settings and ack/cts rate mode */ 1181 /*
1003 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 1182 * Since we are going to write rf buffer
1004 (AR5K_STA_ID1_DEFAULT_ANTENNA | 1183 * check if we have any pending gain_F
1005 AR5K_STA_ID1_DESC_ANTENNA | 1184 * optimization settings
1006 AR5K_STA_ID1_RTS_DEF_ANTENNA | 1185 */
1007 AR5K_STA_ID1_ACKCTS_6MB | 1186 if (ah->ah_version == AR5K_AR5212 &&
1008 AR5K_STA_ID1_BASE_RATE_11B | 1187 (ah->ah_radio <= AR5K_RF5112)) {
1009 AR5K_STA_ID1_SELFGEN_DEF_ANT); 1188 if (!fast && ah->ah_rf_banks != NULL)
1189 ath5k_hw_gainf_calibrate(ah);
1190 }
1010 1191
1011 /* Wakeup the device */ 1192 /* Wakeup the device */
1012 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false); 1193 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
@@ -1021,121 +1202,42 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1021 AR5K_PHY(0)); 1202 AR5K_PHY(0));
1022 1203
1023 /* Write initial settings */ 1204 /* Write initial settings */
1024 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 1205 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1025 if (ret) 1206 if (ret)
1026 return ret; 1207 return ret;
1027 1208
1209 /* Initialize core clock settings */
1210 ath5k_hw_init_core_clock(ah);
1211
1028 /* 1212 /*
1029 * 5211/5212 Specific 1213 * Tweak initval settings for revised
1214 * chipsets and add some more config
1215 * bits
1030 */ 1216 */
1031 if (ah->ah_version != AR5K_AR5210) { 1217 ath5k_hw_tweak_initval_settings(ah, channel);
1032
1033 /*
1034 * Write initial RF gain settings
1035 * This should work for both 5111/5112
1036 */
1037 ret = ath5k_hw_rfgain_init(ah, freq);
1038 if (ret)
1039 return ret;
1040
1041 mdelay(1);
1042
1043 /*
1044 * Tweak initval settings for revised
1045 * chipsets and add some more config
1046 * bits
1047 */
1048 ath5k_hw_tweak_initval_settings(ah, channel);
1049
1050 /*
1051 * Set TX power
1052 */
1053 ret = ath5k_hw_txpower(ah, channel, ee_mode,
1054 ah->ah_txpower.txp_max_pwr / 2);
1055 if (ret)
1056 return ret;
1057
1058 /* Write rate duration table only on AR5212 and if
1059 * virtual interface has already been brought up
1060 * XXX: rethink this after new mode changes to
1061 * mac80211 are integrated */
1062 if (ah->ah_version == AR5K_AR5212 &&
1063 ah->ah_sc->vif != NULL)
1064 ath5k_hw_write_rate_duration(ah, mode);
1065
1066 /*
1067 * Write RF buffer
1068 */
1069 ret = ath5k_hw_rfregs_init(ah, channel, mode);
1070 if (ret)
1071 return ret;
1072
1073
1074 /* Write OFDM timings on 5212*/
1075 if (ah->ah_version == AR5K_AR5212 &&
1076 channel->hw_value & CHANNEL_OFDM) {
1077 1218
1078 ret = ath5k_hw_write_ofdm_timings(ah, channel); 1219 /* Commit values from EEPROM */
1079 if (ret) 1220 ath5k_hw_commit_eeprom_settings(ah, channel);
1080 return ret;
1081 1221
1082 /* Spur info is available only from EEPROM versions
1083 * bigger than 5.3 but but the EEPOM routines will use
1084 * static values for older versions */
1085 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
1086 ath5k_hw_set_spur_mitigation_filter(ah,
1087 channel);
1088 }
1089
1090 /*Enable/disable 802.11b mode on 5111
1091 (enable 2111 frequency converter + CCK)*/
1092 if (ah->ah_radio == AR5K_RF5111) {
1093 if (mode == AR5K_MODE_11B)
1094 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
1095 AR5K_TXCFG_B_MODE);
1096 else
1097 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
1098 AR5K_TXCFG_B_MODE);
1099 }
1100
1101 /* Commit values from EEPROM */
1102 ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
1103
1104 } else {
1105 /*
1106 * For 5210 we do all initialization using
1107 * initvals, so we don't have to modify
1108 * any settings (5210 also only supports
1109 * a/aturbo modes)
1110 */
1111 mdelay(1);
1112 /* Disable phy and wait */
1113 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1114 mdelay(1);
1115 }
1116 1222
1117 /* 1223 /*
1118 * Restore saved values 1224 * Restore saved values
1119 */ 1225 */
1120 1226
1121 /*DCU/Antenna selection not available on 5210*/ 1227 /* Seqnum, TSF */
1122 if (ah->ah_version != AR5K_AR5210) { 1228 if (ah->ah_version != AR5K_AR5210) {
1229 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1230 for (i = 0; i < 10; i++)
1231 ath5k_hw_reg_write(ah, s_seq[i],
1232 AR5K_QUEUE_DCU_SEQNUM(i));
1233 } else {
1234 ath5k_hw_reg_write(ah, s_seq[0],
1235 AR5K_QUEUE_DCU_SEQNUM(0));
1236 }
1123 1237
1124 if (change_channel) { 1238 if (ah->ah_version == AR5K_AR5211) {
1125 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 1239 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1126 for (i = 0; i < 10; i++) 1240 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1127 ath5k_hw_reg_write(ah, s_seq[i],
1128 AR5K_QUEUE_DCU_SEQNUM(i));
1129 } else {
1130 ath5k_hw_reg_write(ah, s_seq[0],
1131 AR5K_QUEUE_DCU_SEQNUM(0));
1132 }
1133
1134
1135 if (ah->ah_version == AR5K_AR5211) {
1136 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1137 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1138 }
1139 } 1241 }
1140 } 1242 }
1141 1243
@@ -1146,203 +1248,34 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1146 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); 1248 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1147 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); 1249 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1148 1250
1149 /* Restore sta_id flags and preserve our mac address*/
1150 ath5k_hw_reg_write(ah,
1151 get_unaligned_le32(common->macaddr),
1152 AR5K_STA_ID0);
1153 ath5k_hw_reg_write(ah,
1154 staid1_flags | get_unaligned_le16(common->macaddr + 4),
1155 AR5K_STA_ID1);
1156
1157
1158 /* 1251 /*
1159 * Configure PCU 1252 * Initialize PCU
1160 */ 1253 */
1161 1254 ath5k_hw_pcu_init(ah, op_mode, mode);
1162 /* Restore bssid and bssid mask */
1163 ath5k_hw_set_associd(ah);
1164
1165 /* Set PCU config */
1166 ath5k_hw_set_opmode(ah, op_mode);
1167
1168 /* Clear any pending interrupts
1169 * PISR/SISR Not available on 5210 */
1170 if (ah->ah_version != AR5K_AR5210)
1171 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1172
1173 /* Set RSSI/BRSSI thresholds
1174 *
1175 * Note: If we decide to set this value
1176 * dynamicaly, have in mind that when AR5K_RSSI_THR
1177 * register is read it might return 0x40 if we haven't
1178 * wrote anything to it plus BMISS RSSI threshold is zeroed.
1179 * So doing a save/restore procedure here isn't the right
1180 * choice. Instead store it on ath5k_hw */
1181 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
1182 AR5K_TUNE_BMISS_THRES <<
1183 AR5K_RSSI_THR_BMISS_S),
1184 AR5K_RSSI_THR);
1185
1186 /* MIC QoS support */
1187 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
1188 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
1189 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
1190 }
1191
1192 /* QoS NOACK Policy */
1193 if (ah->ah_version == AR5K_AR5212) {
1194 ath5k_hw_reg_write(ah,
1195 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
1196 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
1197 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
1198 AR5K_QOS_NOACK);
1199 }
1200
1201 1255
1202 /* 1256 /*
1203 * Configure PHY 1257 * Initialize PHY
1204 */ 1258 */
1205 1259 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1206 /* Set channel on PHY */ 1260 if (ret) {
1207 ret = ath5k_hw_channel(ah, channel); 1261 ATH5K_ERR(ah->ah_sc,
1208 if (ret) 1262 "failed to initialize PHY (%i) !\n", ret);
1209 return ret; 1263 return ret;
1210
1211 /*
1212 * Enable the PHY and wait until completion
1213 * This includes BaseBand and Synthesizer
1214 * activation.
1215 */
1216 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1217
1218 /*
1219 * On 5211+ read activation -> rx delay
1220 * and use it.
1221 *
1222 * TODO: Half/quarter rate support
1223 */
1224 if (ah->ah_version != AR5K_AR5210) {
1225 u32 delay;
1226 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1227 AR5K_PHY_RX_DELAY_M;
1228 delay = (channel->hw_value & CHANNEL_CCK) ?
1229 ((delay << 2) / 22) : (delay / 10);
1230
1231 udelay(100 + (2 * delay));
1232 } else {
1233 mdelay(1);
1234 }
1235
1236 /*
1237 * Perform ADC test to see if baseband is ready
1238 * Set tx hold and check adc test register
1239 */
1240 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1241 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1242 for (i = 0; i <= 20; i++) {
1243 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1244 break;
1245 udelay(200);
1246 }
1247 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1248
1249 /*
1250 * Start automatic gain control calibration
1251 *
1252 * During AGC calibration RX path is re-routed to
1253 * a power detector so we don't receive anything.
1254 *
1255 * This method is used to calibrate some static offsets
1256 * used together with on-the fly I/Q calibration (the
1257 * one performed via ath5k_hw_phy_calibrate), that doesn't
1258 * interrupt rx path.
1259 *
1260 * While rx path is re-routed to the power detector we also
1261 * start a noise floor calibration, to measure the
1262 * card's noise floor (the noise we measure when we are not
1263 * transmiting or receiving anything).
1264 *
1265 * If we are in a noisy environment AGC calibration may time
1266 * out and/or noise floor calibration might timeout.
1267 */
1268 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1269 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
1270
1271 /* At the same time start I/Q calibration for QAM constellation
1272 * -no need for CCK- */
1273 ah->ah_calibration = false;
1274 if (!(mode == AR5K_MODE_11B)) {
1275 ah->ah_calibration = true;
1276 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1277 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1278 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1279 AR5K_PHY_IQ_RUN);
1280 } 1264 }
1281 1265
1282 /* Wait for gain calibration to finish (we check for I/Q calibration
1283 * during ath5k_phy_calibrate) */
1284 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1285 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1286 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
1287 channel->center_freq);
1288 }
1289
1290 /* Restore antenna mode */
1291 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
1292
1293 /* Restore slot time and ACK timeouts */
1294 if (ah->ah_coverage_class > 0)
1295 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
1296
1297 /* 1266 /*
1298 * Configure QCUs/DCUs 1267 * Configure QCUs/DCUs
1299 */ 1268 */
1300 1269 ret = ath5k_hw_init_queues(ah);
1301 /* TODO: HW Compression support for data queues */ 1270 if (ret)
1302 /* TODO: Burst prefetch for data queues */ 1271 return ret;
1303
1304 /*
1305 * Reset queues and start beacon timers at the end of the reset routine
1306 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
1307 * Note: If we want we can assign multiple qcus on one dcu.
1308 */
1309 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1310 ret = ath5k_hw_reset_tx_queue(ah, i);
1311 if (ret) {
1312 ATH5K_ERR(ah->ah_sc,
1313 "failed to reset TX queue #%d\n", i);
1314 return ret;
1315 }
1316 }
1317 1272
1318 1273
1319 /* 1274 /*
1320 * Configure DMA/Interrupts 1275 * Initialize DMA/Interrupts
1321 */ 1276 */
1277 ath5k_hw_dma_init(ah);
1322 1278
1323 /*
1324 * Set Rx/Tx DMA Configuration
1325 *
1326 * Set standard DMA size (128). Note that
1327 * a DMA size of 512 causes rx overruns and tx errors
1328 * on pci-e cards (tested on 5424 but since rx overruns
1329 * also occur on 5416/5418 with madwifi we set 128
1330 * for all PCI-E cards to be safe).
1331 *
1332 * XXX: need to check 5210 for this
1333 * TODO: Check out tx triger level, it's always 64 on dumps but I
1334 * guess we can tweak it and see how it goes ;-)
1335 */
1336 if (ah->ah_version != AR5K_AR5210) {
1337 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1338 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
1339 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1340 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
1341 }
1342
1343 /* Pre-enable interrupts on 5211/5212*/
1344 if (ah->ah_version != AR5K_AR5210)
1345 ath5k_hw_set_imr(ah, ah->ah_imr);
1346 1279
1347 /* Enable 32KHz clock function for AR5212+ chips 1280 /* Enable 32KHz clock function for AR5212+ chips
1348 * Set clocks to 32KHz operation and use an 1281 * Set clocks to 32KHz operation and use an
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 03:20:14 -0400