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path: root/drivers/net/wireless/ath/ath9k/hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1117
1 files changed, 445 insertions, 672 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 3384ca164562..1be7c8bbef84 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc. 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55} 55}
56 56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan) 58 struct ath9k_channel *chan)
66{ 59{
@@ -88,29 +81,32 @@ static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
88/* Helper Functions */ 81/* Helper Functions */
89/********************/ 82/********************/
90 83
91static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 84static void ath9k_hw_set_clockrate(struct ath_hw *ah)
92{ 85{
93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
94 89
95 if (!ah->curchan) /* should really check for CCK instead */ 90 if (!ah->curchan) /* should really check for CCK instead */
96 return usecs *ATH9K_CLOCK_RATE_CCK; 91 clockrate = ATH9K_CLOCK_RATE_CCK;
97 if (conf->channel->band == IEEE80211_BAND_2GHZ) 92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
99 94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
102 else 96 else
103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM; 97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
104} 103}
105 104
106static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
107{ 106{
108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 107 struct ath_common *common = ath9k_hw_common(ah);
109 108
110 if (conf_is_ht40(conf)) 109 return usecs * common->clockrate;
111 return ath9k_hw_mac_clks(ah, usecs) * 2;
112 else
113 return ath9k_hw_mac_clks(ah, usecs);
114} 110}
115 111
116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
@@ -126,14 +122,28 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
126 udelay(AH_TIME_QUANTUM); 122 udelay(AH_TIME_QUANTUM);
127 } 123 }
128 124
129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val); 127 timeout, reg, REG_READ(ah, reg), mask, val);
132 128
133 return false; 129 return false;
134} 130}
135EXPORT_SYMBOL(ath9k_hw_wait); 131EXPORT_SYMBOL(ath9k_hw_wait);
136 132
133void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135{
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145}
146
137u32 ath9k_hw_reverse_bits(u32 val, u32 n) 147u32 ath9k_hw_reverse_bits(u32 val, u32 n)
138{ 148{
139 u32 retval; 149 u32 retval;
@@ -146,25 +156,6 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
146 return retval; 156 return retval;
147} 157}
148 158
149bool ath9k_get_channel_edges(struct ath_hw *ah,
150 u16 flags, u16 *low,
151 u16 *high)
152{
153 struct ath9k_hw_capabilities *pCap = &ah->caps;
154
155 if (flags & CHANNEL_5GHZ) {
156 *low = pCap->low_5ghz_chan;
157 *high = pCap->high_5ghz_chan;
158 return true;
159 }
160 if ((flags & CHANNEL_2GHZ)) {
161 *low = pCap->low_2ghz_chan;
162 *high = pCap->high_2ghz_chan;
163 return true;
164 }
165 return false;
166}
167
168u16 ath9k_hw_computetxtime(struct ath_hw *ah, 159u16 ath9k_hw_computetxtime(struct ath_hw *ah,
169 u8 phy, int kbps, 160 u8 phy, int kbps,
170 u32 frameLen, u16 rateix, 161 u32 frameLen, u16 rateix,
@@ -208,8 +199,8 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
208 } 199 }
209 break; 200 break;
210 default: 201 default:
211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 202 ath_err(ath9k_hw_common(ah),
212 "Unknown phy %u (rate ix %u)\n", phy, rateix); 203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
213 txTime = 0; 204 txTime = 0;
214 break; 205 break;
215 } 206 }
@@ -256,6 +247,17 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
256{ 247{
257 u32 val; 248 u32 val;
258 249
250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
254 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
258 return;
259 }
260
259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 261 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
260 262
261 if (val == 0xFF) { 263 if (val == 0xFF) {
@@ -281,11 +283,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
281 283
282static void ath9k_hw_disablepcie(struct ath_hw *ah) 284static void ath9k_hw_disablepcie(struct ath_hw *ah)
283{ 285{
284 if (AR_SREV_9100(ah)) 286 if (!AR_SREV_5416(ah))
285 return; 287 return;
286 288
287 ENABLE_REGWRITE_BUFFER(ah);
288
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -297,9 +297,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
298 298
299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
300
301 REGWRITE_BUFFER_FLUSH(ah);
302 DISABLE_REGWRITE_BUFFER(ah);
303} 300}
304 301
305/* This should work for all families including legacy */ 302/* This should work for all families including legacy */
@@ -308,10 +305,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
308 struct ath_common *common = ath9k_hw_common(ah); 305 struct ath_common *common = ath9k_hw_common(ah);
309 u32 regAddr[2] = { AR_STA_ID0 }; 306 u32 regAddr[2] = { AR_STA_ID0 };
310 u32 regHold[2]; 307 u32 regHold[2];
311 u32 patternData[4] = { 0x55555555, 308 static const u32 patternData[4] = {
312 0xaaaaaaaa, 309 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
313 0x66666666, 310 };
314 0x99999999 };
315 int i, j, loop_max; 311 int i, j, loop_max;
316 312
317 if (!AR_SREV_9300_20_OR_LATER(ah)) { 313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@ -330,11 +326,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
330 REG_WRITE(ah, addr, wrData); 326 REG_WRITE(ah, addr, wrData);
331 rdData = REG_READ(ah, addr); 327 rdData = REG_READ(ah, addr);
332 if (rdData != wrData) { 328 if (rdData != wrData) {
333 ath_print(common, ATH_DBG_FATAL, 329 ath_err(common,
334 "address test failed " 330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
335 "addr: 0x%08x - wr:0x%08x != " 331 addr, wrData, rdData);
336 "rd:0x%08x\n",
337 addr, wrData, rdData);
338 return false; 332 return false;
339 } 333 }
340 } 334 }
@@ -343,11 +337,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
343 REG_WRITE(ah, addr, wrData); 337 REG_WRITE(ah, addr, wrData);
344 rdData = REG_READ(ah, addr); 338 rdData = REG_READ(ah, addr);
345 if (wrData != rdData) { 339 if (wrData != rdData) {
346 ath_print(common, ATH_DBG_FATAL, 340 ath_err(common,
347 "address test failed " 341 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
348 "addr: 0x%08x - wr:0x%08x != " 342 addr, wrData, rdData);
349 "rd:0x%08x\n",
350 addr, wrData, rdData);
351 return false; 343 return false;
352 } 344 }
353 } 345 }
@@ -371,10 +363,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
371 ah->config.pcie_clock_req = 0; 363 ah->config.pcie_clock_req = 0;
372 ah->config.pcie_waen = 0; 364 ah->config.pcie_waen = 0;
373 ah->config.analog_shiftreg = 1; 365 ah->config.analog_shiftreg = 1;
374 ah->config.ofdm_trig_low = 200;
375 ah->config.ofdm_trig_high = 500;
376 ah->config.cck_trig_high = 200;
377 ah->config.cck_trig_low = 100;
378 ah->config.enable_ani = true; 366 ah->config.enable_ani = true;
379 367
380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 368 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
@@ -382,10 +370,8 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
382 ah->config.spurchans[i][1] = AR_NO_SPUR; 370 ah->config.spurchans[i][1] = AR_NO_SPUR;
383 } 371 }
384 372
385 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 373 /* PAPRD needs some more work to be enabled */
386 ah->config.ht_enable = 1; 374 ah->config.paprd_disable = 1;
387 else
388 ah->config.ht_enable = 0;
389 375
390 ah->config.rx_intr_mitigation = true; 376 ah->config.rx_intr_mitigation = true;
391 ah->config.pcieSerDesWrite = true; 377 ah->config.pcieSerDesWrite = true;
@@ -421,17 +407,14 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
421 ah->hw_version.magic = AR5416_MAGIC; 407 ah->hw_version.magic = AR5416_MAGIC;
422 ah->hw_version.subvendorid = 0; 408 ah->hw_version.subvendorid = 0;
423 409
424 ah->ah_flags = 0;
425 if (!AR_SREV_9100(ah))
426 ah->ah_flags = AH_USE_EEPROM;
427
428 ah->atim_window = 0; 410 ah->atim_window = 0;
429 ah->sta_id1_defaults = 411 ah->sta_id1_defaults =
430 AR_STA_ID1_CRPT_MIC_ENABLE | 412 AR_STA_ID1_CRPT_MIC_ENABLE |
431 AR_STA_ID1_MCAST_KSRCH; 413 AR_STA_ID1_MCAST_KSRCH;
432 ah->beacon_interval = 100; 414 if (AR_SREV_9100(ah))
415 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
433 ah->enable_32kHz_clock = DONT_USE_32KHZ; 416 ah->enable_32kHz_clock = DONT_USE_32KHZ;
434 ah->slottime = (u32) -1; 417 ah->slottime = 20;
435 ah->globaltxtimeout = (u32) -1; 418 ah->globaltxtimeout = (u32) -1;
436 ah->power_mode = ATH9K_PM_UNDEFINED; 419 ah->power_mode = ATH9K_PM_UNDEFINED;
437} 420}
@@ -442,7 +425,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
442 u32 sum; 425 u32 sum;
443 int i; 426 int i;
444 u16 eeval; 427 u16 eeval;
445 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 428 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
446 429
447 sum = 0; 430 sum = 0;
448 for (i = 0; i < 3; i++) { 431 for (i = 0; i < 3; i++) {
@@ -459,9 +442,10 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
459 442
460static int ath9k_hw_post_init(struct ath_hw *ah) 443static int ath9k_hw_post_init(struct ath_hw *ah)
461{ 444{
445 struct ath_common *common = ath9k_hw_common(ah);
462 int ecode; 446 int ecode;
463 447
464 if (!AR_SREV_9271(ah)) { 448 if (common->bus_ops->ath_bus_type != ATH_USB) {
465 if (!ath9k_hw_chip_test(ah)) 449 if (!ath9k_hw_chip_test(ah))
466 return -ENODEV; 450 return -ENODEV;
467 } 451 }
@@ -476,20 +460,20 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
476 if (ecode != 0) 460 if (ecode != 0)
477 return ecode; 461 return ecode;
478 462
479 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 463 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
480 "Eeprom VER: %d, REV: %d\n", 464 "Eeprom VER: %d, REV: %d\n",
481 ah->eep_ops->get_eeprom_ver(ah), 465 ah->eep_ops->get_eeprom_ver(ah),
482 ah->eep_ops->get_eeprom_rev(ah)); 466 ah->eep_ops->get_eeprom_rev(ah));
483 467
484 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 468 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
485 if (ecode) { 469 if (ecode) {
486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 470 ath_err(ath9k_hw_common(ah),
487 "Failed allocating banks for " 471 "Failed allocating banks for external radio\n");
488 "external radio\n"); 472 ath9k_hw_rf_free_ext_banks(ah);
489 return ecode; 473 return ecode;
490 } 474 }
491 475
492 if (!AR_SREV_9100(ah)) { 476 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
493 ath9k_hw_ani_setup(ah); 477 ath9k_hw_ani_setup(ah);
494 ath9k_hw_ani_init(ah); 478 ath9k_hw_ani_init(ah);
495 } 479 }
@@ -511,12 +495,19 @@ static int __ath9k_hw_init(struct ath_hw *ah)
511 struct ath_common *common = ath9k_hw_common(ah); 495 struct ath_common *common = ath9k_hw_common(ah);
512 int r = 0; 496 int r = 0;
513 497
514 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 498 ath9k_hw_read_revisions(ah);
515 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 499
500 /*
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
504 */
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
516 508
517 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
518 ath_print(common, ATH_DBG_FATAL, 510 ath_err(common, "Couldn't reset chip\n");
519 "Couldn't reset chip\n");
520 return -EIO; 511 return -EIO;
521 } 512 }
522 513
@@ -526,7 +517,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
526 ath9k_hw_attach_ops(ah); 517 ath9k_hw_attach_ops(ah);
527 518
528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
529 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 520 ath_err(common, "Couldn't wakeup chip\n");
530 return -EIO; 521 return -EIO;
531 } 522 }
532 523
@@ -542,7 +533,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
542 } 533 }
543 } 534 }
544 535
545 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
546 ah->config.serialize_regmode); 537 ah->config.serialize_regmode);
547 538
548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
@@ -550,36 +541,40 @@ static int __ath9k_hw_init(struct ath_hw *ah)
550 else 541 else
551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
552 543
553 if (!ath9k_hw_macversion_supported(ah)) { 544 switch (ah->hw_version.macVersion) {
554 ath_print(common, ATH_DBG_FATAL, 545 case AR_SREV_VERSION_5416_PCI:
555 "Mac Chip Rev 0x%02x.%x is not supported by " 546 case AR_SREV_VERSION_5416_PCIE:
556 "this driver\n", ah->hw_version.macVersion, 547 case AR_SREV_VERSION_9160:
557 ah->hw_version.macRev); 548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 case AR_SREV_VERSION_9340:
556 break;
557 default:
558 ath_err(common,
559 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
560 ah->hw_version.macVersion, ah->hw_version.macRev);
558 return -EOPNOTSUPP; 561 return -EOPNOTSUPP;
559 } 562 }
560 563
561 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
562 ah->is_pciexpress = false; 565 ah->is_pciexpress = false;
563 566
564 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
565 ath9k_hw_init_cal_settings(ah); 568 ath9k_hw_init_cal_settings(ah);
566 569
567 ah->ani_function = ATH9K_ANI_ALL; 570 ah->ani_function = ATH9K_ANI_ALL;
568 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 571 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
569 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
570 if (!AR_SREV_9300_20_OR_LATER(ah)) 573 if (!AR_SREV_9300_20_OR_LATER(ah))
571 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 574 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
572 575
573 ath9k_hw_init_mode_regs(ah); 576 ath9k_hw_init_mode_regs(ah);
574 577
575 /*
576 * Read back AR_WA into a permanent copy and set bits 14 and 17.
577 * We need to do this to avoid RMW of this register. We cannot
578 * read the reg when chip is asleep.
579 */
580 ah->WARegVal = REG_READ(ah, AR_WA);
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
582 AR_WA_ASPM_TIMER_BASED_DISABLE);
583 578
584 if (ah->is_pciexpress) 579 if (ah->is_pciexpress)
585 ath9k_hw_configpcipowersave(ah, 0, 0); 580 ath9k_hw_configpcipowersave(ah, 0, 0);
@@ -600,8 +595,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
600 595
601 r = ath9k_hw_init_macaddr(ah); 596 r = ath9k_hw_init_macaddr(ah);
602 if (r) { 597 if (r) {
603 ath_print(common, ATH_DBG_FATAL, 598 ath_err(common, "Failed to initialize MAC address\n");
604 "Failed to initialize MAC address\n");
605 return r; 599 return r;
606 } 600 }
607 601
@@ -635,21 +629,22 @@ int ath9k_hw_init(struct ath_hw *ah)
635 case AR9287_DEVID_PCIE: 629 case AR9287_DEVID_PCIE:
636 case AR2427_DEVID_PCIE: 630 case AR2427_DEVID_PCIE:
637 case AR9300_DEVID_PCIE: 631 case AR9300_DEVID_PCIE:
632 case AR9300_DEVID_AR9485_PCIE:
633 case AR9300_DEVID_AR9340:
638 break; 634 break;
639 default: 635 default:
640 if (common->bus_ops->ath_bus_type == ATH_USB) 636 if (common->bus_ops->ath_bus_type == ATH_USB)
641 break; 637 break;
642 ath_print(common, ATH_DBG_FATAL, 638 ath_err(common, "Hardware device ID 0x%04x not supported\n",
643 "Hardware device ID 0x%04x not supported\n", 639 ah->hw_version.devid);
644 ah->hw_version.devid);
645 return -EOPNOTSUPP; 640 return -EOPNOTSUPP;
646 } 641 }
647 642
648 ret = __ath9k_hw_init(ah); 643 ret = __ath9k_hw_init(ah);
649 if (ret) { 644 if (ret) {
650 ath_print(common, ATH_DBG_FATAL, 645 ath_err(common,
651 "Unable to initialize hardware; " 646 "Unable to initialize hardware; initialization status: %d\n",
652 "initialization status: %d\n", ret); 647 ret);
653 return ret; 648 return ret;
654 } 649 }
655 650
@@ -676,16 +671,101 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
676 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
677 672
678 REGWRITE_BUFFER_FLUSH(ah); 673 REGWRITE_BUFFER_FLUSH(ah);
679 DISABLE_REGWRITE_BUFFER(ah);
680} 674}
681 675
676u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
677{
678 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
679 udelay(100);
680 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681
682 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
683 udelay(100);
684
685 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
686}
687EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
688
682static void ath9k_hw_init_pll(struct ath_hw *ah, 689static void ath9k_hw_init_pll(struct ath_hw *ah,
683 struct ath9k_channel *chan) 690 struct ath9k_channel *chan)
684{ 691{
685 u32 pll = ath9k_hw_compute_pll_control(ah, chan); 692 u32 pll;
693
694 if (AR_SREV_9485(ah)) {
695
696 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
697 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
698 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
699 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
700 AR_CH0_DPLL2_KD, 0x40);
701 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
702 AR_CH0_DPLL2_KI, 0x4);
703
704 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
705 AR_CH0_BB_DPLL1_REFDIV, 0x5);
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
707 AR_CH0_BB_DPLL1_NINI, 0x58);
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
709 AR_CH0_BB_DPLL1_NFRAC, 0x0);
710
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
714 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
716 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
717
718 /* program BB PLL phase_shift to 0x6 */
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
720 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
721
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
724 udelay(1000);
725 } else if (AR_SREV_9340(ah)) {
726 u32 regval, pll2_divint, pll2_divfrac, refdiv;
727
728 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
729 udelay(1000);
730
731 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
732 udelay(100);
733
734 if (ah->is_clk_25mhz) {
735 pll2_divint = 0x54;
736 pll2_divfrac = 0x1eb85;
737 refdiv = 3;
738 } else {
739 pll2_divint = 88;
740 pll2_divfrac = 0;
741 refdiv = 5;
742 }
743
744 regval = REG_READ(ah, AR_PHY_PLL_MODE);
745 regval |= (0x1 << 16);
746 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
747 udelay(100);
748
749 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
750 (pll2_divint << 18) | pll2_divfrac);
751 udelay(100);
752
753 regval = REG_READ(ah, AR_PHY_PLL_MODE);
754 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
755 (0x4 << 26) | (0x18 << 19);
756 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
757 REG_WRITE(ah, AR_PHY_PLL_MODE,
758 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
759 udelay(1000);
760 }
761
762 pll = ath9k_hw_compute_pll_control(ah, chan);
686 763
687 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 764 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
688 765
766 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
767 udelay(1000);
768
689 /* Switch the core clock for ar9271 to 117Mhz */ 769 /* Switch the core clock for ar9271 to 117Mhz */
690 if (AR_SREV_9271(ah)) { 770 if (AR_SREV_9271(ah)) {
691 udelay(500); 771 udelay(500);
@@ -695,17 +775,34 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
695 udelay(RTC_PLL_SETTLE_DELAY); 775 udelay(RTC_PLL_SETTLE_DELAY);
696 776
697 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 777 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
778
779 if (AR_SREV_9340(ah)) {
780 if (ah->is_clk_25mhz) {
781 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
782 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
783 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
784 } else {
785 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
786 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
787 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
788 }
789 udelay(100);
790 }
698} 791}
699 792
700static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 793static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
701 enum nl80211_iftype opmode) 794 enum nl80211_iftype opmode)
702{ 795{
796 u32 sync_default = AR_INTR_SYNC_DEFAULT;
703 u32 imr_reg = AR_IMR_TXERR | 797 u32 imr_reg = AR_IMR_TXERR |
704 AR_IMR_TXURN | 798 AR_IMR_TXURN |
705 AR_IMR_RXERR | 799 AR_IMR_RXERR |
706 AR_IMR_RXORN | 800 AR_IMR_RXORN |
707 AR_IMR_BCNMISC; 801 AR_IMR_BCNMISC;
708 802
803 if (AR_SREV_9340(ah))
804 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
805
709 if (AR_SREV_9300_20_OR_LATER(ah)) { 806 if (AR_SREV_9300_20_OR_LATER(ah)) {
710 imr_reg |= AR_IMR_RXOK_HP; 807 imr_reg |= AR_IMR_RXOK_HP;
711 if (ah->config.rx_intr_mitigation) 808 if (ah->config.rx_intr_mitigation)
@@ -736,12 +833,11 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
736 833
737 if (!AR_SREV_9100(ah)) { 834 if (!AR_SREV_9100(ah)) {
738 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 835 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
739 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 836 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
740 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 837 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
741 } 838 }
742 839
743 REGWRITE_BUFFER_FLUSH(ah); 840 REGWRITE_BUFFER_FLUSH(ah);
744 DISABLE_REGWRITE_BUFFER(ah);
745 841
746 if (AR_SREV_9300_20_OR_LATER(ah)) { 842 if (AR_SREV_9300_20_OR_LATER(ah)) {
747 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 843 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
@@ -775,8 +871,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
775static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 871static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
776{ 872{
777 if (tu > 0xFFFF) { 873 if (tu > 0xFFFF) {
778 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 874 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
779 "bad global tx timeout %u\n", tu); 875 "bad global tx timeout %u\n", tu);
780 ah->globaltxtimeout = (u32) -1; 876 ah->globaltxtimeout = (u32) -1;
781 return false; 877 return false;
782 } else { 878 } else {
@@ -793,12 +889,11 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
793 int slottime; 889 int slottime;
794 int sifstime; 890 int sifstime;
795 891
796 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 892 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
797 ah->misc_mode); 893 ah->misc_mode);
798 894
799 if (ah->misc_mode != 0) 895 if (ah->misc_mode != 0)
800 REG_WRITE(ah, AR_PCU_MISC, 896 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
801 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
802 897
803 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 898 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
804 sifstime = 16; 899 sifstime = 16;
@@ -819,7 +914,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
819 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 914 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
820 acktimeout += 64 - sifstime - ah->slottime; 915 acktimeout += 64 - sifstime - ah->slottime;
821 916
822 ath9k_hw_setslottime(ah, slottime); 917 ath9k_hw_setslottime(ah, ah->slottime);
823 ath9k_hw_set_ack_timeout(ah, acktimeout); 918 ath9k_hw_set_ack_timeout(ah, acktimeout);
824 ath9k_hw_set_cts_timeout(ah, acktimeout); 919 ath9k_hw_set_cts_timeout(ah, acktimeout);
825 if (ah->globaltxtimeout != (u32) -1) 920 if (ah->globaltxtimeout != (u32) -1)
@@ -866,26 +961,21 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
866static inline void ath9k_hw_set_dma(struct ath_hw *ah) 961static inline void ath9k_hw_set_dma(struct ath_hw *ah)
867{ 962{
868 struct ath_common *common = ath9k_hw_common(ah); 963 struct ath_common *common = ath9k_hw_common(ah);
869 u32 regval;
870 964
871 ENABLE_REGWRITE_BUFFER(ah); 965 ENABLE_REGWRITE_BUFFER(ah);
872 966
873 /* 967 /*
874 * set AHB_MODE not to do cacheline prefetches 968 * set AHB_MODE not to do cacheline prefetches
875 */ 969 */
876 if (!AR_SREV_9300_20_OR_LATER(ah)) { 970 if (!AR_SREV_9300_20_OR_LATER(ah))
877 regval = REG_READ(ah, AR_AHB_MODE); 971 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
878 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
879 }
880 972
881 /* 973 /*
882 * let mac dma reads be in 128 byte chunks 974 * let mac dma reads be in 128 byte chunks
883 */ 975 */
884 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 976 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
885 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
886 977
887 REGWRITE_BUFFER_FLUSH(ah); 978 REGWRITE_BUFFER_FLUSH(ah);
888 DISABLE_REGWRITE_BUFFER(ah);
889 979
890 /* 980 /*
891 * Restore TX Trigger Level to its pre-reset value. 981 * Restore TX Trigger Level to its pre-reset value.
@@ -900,8 +990,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
900 /* 990 /*
901 * let mac dma writes be in 128 byte chunks 991 * let mac dma writes be in 128 byte chunks
902 */ 992 */
903 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 993 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
904 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
905 994
906 /* 995 /*
907 * Setup receive FIFO threshold to hold off TX activities 996 * Setup receive FIFO threshold to hold off TX activities
@@ -933,7 +1022,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
933 } 1022 }
934 1023
935 REGWRITE_BUFFER_FLUSH(ah); 1024 REGWRITE_BUFFER_FLUSH(ah);
936 DISABLE_REGWRITE_BUFFER(ah);
937 1025
938 if (AR_SREV_9300_20_OR_LATER(ah)) 1026 if (AR_SREV_9300_20_OR_LATER(ah))
939 ath9k_hw_reset_txstatus_ring(ah); 1027 ath9k_hw_reset_txstatus_ring(ah);
@@ -941,27 +1029,27 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
941 1029
942static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1030static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
943{ 1031{
944 u32 val; 1032 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1033 u32 set = AR_STA_ID1_KSRCH_MODE;
945 1034
946 val = REG_READ(ah, AR_STA_ID1);
947 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
948 switch (opmode) { 1035 switch (opmode) {
949 case NL80211_IFTYPE_AP:
950 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
951 | AR_STA_ID1_KSRCH_MODE);
952 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
953 break;
954 case NL80211_IFTYPE_ADHOC: 1036 case NL80211_IFTYPE_ADHOC:
955 case NL80211_IFTYPE_MESH_POINT: 1037 case NL80211_IFTYPE_MESH_POINT:
956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 1038 set |= AR_STA_ID1_ADHOC;
957 | AR_STA_ID1_KSRCH_MODE);
958 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1039 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
959 break; 1040 break;
1041 case NL80211_IFTYPE_AP:
1042 set |= AR_STA_ID1_STA_AP;
1043 /* fall through */
960 case NL80211_IFTYPE_STATION: 1044 case NL80211_IFTYPE_STATION:
961 case NL80211_IFTYPE_MONITOR: 1045 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
962 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 1046 break;
1047 default:
1048 if (!ah->is_monitoring)
1049 set = 0;
963 break; 1050 break;
964 } 1051 }
1052 REG_RMW(ah, AR_STA_ID1, set, mask);
965} 1053}
966 1054
967void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1055void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
@@ -987,10 +1075,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
987 u32 tmpReg; 1075 u32 tmpReg;
988 1076
989 if (AR_SREV_9100(ah)) { 1077 if (AR_SREV_9100(ah)) {
990 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 1078 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
991 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1079 AR_RTC_DERIVED_CLK_PERIOD, 1);
992 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
993 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
994 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1080 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
995 } 1081 }
996 1082
@@ -1031,14 +1117,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1031 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1117 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1032 1118
1033 REGWRITE_BUFFER_FLUSH(ah); 1119 REGWRITE_BUFFER_FLUSH(ah);
1034 DISABLE_REGWRITE_BUFFER(ah);
1035 1120
1036 udelay(50); 1121 udelay(50);
1037 1122
1038 REG_WRITE(ah, AR_RTC_RC, 0); 1123 REG_WRITE(ah, AR_RTC_RC, 0);
1039 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1124 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1040 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1041 "RTC stuck in MAC reset\n"); 1126 "RTC stuck in MAC reset\n");
1042 return false; 1127 return false;
1043 } 1128 }
1044 1129
@@ -1067,10 +1152,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1067 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1152 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1068 1153
1069 REG_WRITE(ah, AR_RTC_RESET, 0); 1154 REG_WRITE(ah, AR_RTC_RESET, 0);
1070 udelay(2);
1071 1155
1072 REGWRITE_BUFFER_FLUSH(ah); 1156 REGWRITE_BUFFER_FLUSH(ah);
1073 DISABLE_REGWRITE_BUFFER(ah);
1074 1157
1075 if (!AR_SREV_9300_20_OR_LATER(ah)) 1158 if (!AR_SREV_9300_20_OR_LATER(ah))
1076 udelay(2); 1159 udelay(2);
@@ -1085,13 +1168,11 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1085 AR_RTC_STATUS_M, 1168 AR_RTC_STATUS_M,
1086 AR_RTC_STATUS_ON, 1169 AR_RTC_STATUS_ON,
1087 AH_WAIT_TIMEOUT)) { 1170 AH_WAIT_TIMEOUT)) {
1088 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1171 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1089 "RTC not waking up\n"); 1172 "RTC not waking up\n");
1090 return false; 1173 return false;
1091 } 1174 }
1092 1175
1093 ath9k_hw_read_revisions(ah);
1094
1095 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1176 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1096} 1177}
1097 1178
@@ -1146,16 +1227,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1146 1227
1147 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1228 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1148 if (ath9k_hw_numtxpending(ah, qnum)) { 1229 if (ath9k_hw_numtxpending(ah, qnum)) {
1149 ath_print(common, ATH_DBG_QUEUE, 1230 ath_dbg(common, ATH_DBG_QUEUE,
1150 "Transmit frames pending on " 1231 "Transmit frames pending on queue %d\n", qnum);
1151 "queue %d\n", qnum);
1152 return false; 1232 return false;
1153 } 1233 }
1154 } 1234 }
1155 1235
1156 if (!ath9k_hw_rfbus_req(ah)) { 1236 if (!ath9k_hw_rfbus_req(ah)) {
1157 ath_print(common, ATH_DBG_FATAL, 1237 ath_err(common, "Could not kill baseband RX\n");
1158 "Could not kill baseband RX\n");
1159 return false; 1238 return false;
1160 } 1239 }
1161 1240
@@ -1163,17 +1242,17 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1163 1242
1164 r = ath9k_hw_rf_set_freq(ah, chan); 1243 r = ath9k_hw_rf_set_freq(ah, chan);
1165 if (r) { 1244 if (r) {
1166 ath_print(common, ATH_DBG_FATAL, 1245 ath_err(common, "Failed to set channel\n");
1167 "Failed to set channel\n");
1168 return false; 1246 return false;
1169 } 1247 }
1248 ath9k_hw_set_clockrate(ah);
1170 1249
1171 ah->eep_ops->set_txpower(ah, chan, 1250 ah->eep_ops->set_txpower(ah, chan,
1172 ath9k_regd_get_ctl(regulatory, chan), 1251 ath9k_regd_get_ctl(regulatory, chan),
1173 channel->max_antenna_gain * 2, 1252 channel->max_antenna_gain * 2,
1174 channel->max_power * 2, 1253 channel->max_power * 2,
1175 min((u32) MAX_RATE_POWER, 1254 min((u32) MAX_RATE_POWER,
1176 (u32) regulatory->power_limit)); 1255 (u32) regulatory->power_limit), false);
1177 1256
1178 ath9k_hw_rfbus_done(ah); 1257 ath9k_hw_rfbus_done(ah);
1179 1258
@@ -1185,12 +1264,26 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1185 return true; 1264 return true;
1186} 1265}
1187 1266
1267static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1268{
1269 u32 gpio_mask = ah->gpio_mask;
1270 int i;
1271
1272 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1273 if (!(gpio_mask & 1))
1274 continue;
1275
1276 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1277 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1278 }
1279}
1280
1188bool ath9k_hw_check_alive(struct ath_hw *ah) 1281bool ath9k_hw_check_alive(struct ath_hw *ah)
1189{ 1282{
1190 int count = 50; 1283 int count = 50;
1191 u32 reg; 1284 u32 reg;
1192 1285
1193 if (AR_SREV_9285_10_OR_LATER(ah)) 1286 if (AR_SREV_9285_12_OR_LATER(ah))
1194 return true; 1287 return true;
1195 1288
1196 do { 1289 do {
@@ -1227,19 +1320,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1227 ah->txchainmask = common->tx_chainmask; 1320 ah->txchainmask = common->tx_chainmask;
1228 ah->rxchainmask = common->rx_chainmask; 1321 ah->rxchainmask = common->rx_chainmask;
1229 1322
1230 if (!ah->chip_fullsleep) {
1231 ath9k_hw_abortpcurecv(ah);
1232 if (!ath9k_hw_stopdmarecv(ah)) {
1233 ath_print(common, ATH_DBG_XMIT,
1234 "Failed to stop receive dma\n");
1235 bChannelChange = false;
1236 }
1237 }
1238
1239 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1323 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1240 return -EIO; 1324 return -EIO;
1241 1325
1242 if (curchan && !ah->chip_fullsleep && ah->caldata) 1326 if (curchan && !ah->chip_fullsleep)
1243 ath9k_hw_getnf(ah, curchan); 1327 ath9k_hw_getnf(ah, curchan);
1244 1328
1245 ah->caldata = caldata; 1329 ah->caldata = caldata;
@@ -1258,11 +1342,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1258 (chan->channel != ah->curchan->channel) && 1342 (chan->channel != ah->curchan->channel) &&
1259 ((chan->channelFlags & CHANNEL_ALL) == 1343 ((chan->channelFlags & CHANNEL_ALL) ==
1260 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1344 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1261 !AR_SREV_9280(ah)) { 1345 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1262 1346
1263 if (ath9k_hw_channel_change(ah, chan)) { 1347 if (ath9k_hw_channel_change(ah, chan)) {
1264 ath9k_hw_loadnf(ah, ah->curchan); 1348 ath9k_hw_loadnf(ah, ah->curchan);
1265 ath9k_hw_start_nfcal(ah, true); 1349 ath9k_hw_start_nfcal(ah, true);
1350 if (AR_SREV_9271(ah))
1351 ar9002_hw_load_ani_reg(ah, chan);
1266 return 0; 1352 return 0;
1267 } 1353 }
1268 } 1354 }
@@ -1284,6 +1370,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1284 1370
1285 ath9k_hw_mark_phy_inactive(ah); 1371 ath9k_hw_mark_phy_inactive(ah);
1286 1372
1373 ah->paprd_table_write_done = false;
1374
1287 /* Only required on the first reset */ 1375 /* Only required on the first reset */
1288 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1376 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1289 REG_WRITE(ah, 1377 REG_WRITE(ah,
@@ -1293,7 +1381,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1293 } 1381 }
1294 1382
1295 if (!ath9k_hw_chip_reset(ah, chan)) { 1383 if (!ath9k_hw_chip_reset(ah, chan)) {
1296 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1384 ath_err(common, "Chip reset failed\n");
1297 return -EINVAL; 1385 return -EINVAL;
1298 } 1386 }
1299 1387
@@ -1310,7 +1398,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1310 if (tsf) 1398 if (tsf)
1311 ath9k_hw_settsf64(ah, tsf); 1399 ath9k_hw_settsf64(ah, tsf);
1312 1400
1313 if (AR_SREV_9280_10_OR_LATER(ah)) 1401 if (AR_SREV_9280_20_OR_LATER(ah))
1314 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1402 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1315 1403
1316 if (!AR_SREV_9300_20_OR_LATER(ah)) 1404 if (!AR_SREV_9300_20_OR_LATER(ah))
@@ -1354,8 +1442,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1354 ath9k_hw_spur_mitigate_freq(ah, chan); 1442 ath9k_hw_spur_mitigate_freq(ah, chan);
1355 ah->eep_ops->set_board_values(ah, chan); 1443 ah->eep_ops->set_board_values(ah, chan);
1356 1444
1357 ath9k_hw_set_operating_mode(ah, ah->opmode);
1358
1359 ENABLE_REGWRITE_BUFFER(ah); 1445 ENABLE_REGWRITE_BUFFER(ah);
1360 1446
1361 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1447 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
@@ -1372,22 +1458,24 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1372 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1458 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1373 1459
1374 REGWRITE_BUFFER_FLUSH(ah); 1460 REGWRITE_BUFFER_FLUSH(ah);
1375 DISABLE_REGWRITE_BUFFER(ah); 1461
1462 ath9k_hw_set_operating_mode(ah, ah->opmode);
1376 1463
1377 r = ath9k_hw_rf_set_freq(ah, chan); 1464 r = ath9k_hw_rf_set_freq(ah, chan);
1378 if (r) 1465 if (r)
1379 return r; 1466 return r;
1380 1467
1468 ath9k_hw_set_clockrate(ah);
1469
1381 ENABLE_REGWRITE_BUFFER(ah); 1470 ENABLE_REGWRITE_BUFFER(ah);
1382 1471
1383 for (i = 0; i < AR_NUM_DCU; i++) 1472 for (i = 0; i < AR_NUM_DCU; i++)
1384 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1473 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1385 1474
1386 REGWRITE_BUFFER_FLUSH(ah); 1475 REGWRITE_BUFFER_FLUSH(ah);
1387 DISABLE_REGWRITE_BUFFER(ah);
1388 1476
1389 ah->intr_txqs = 0; 1477 ah->intr_txqs = 0;
1390 for (i = 0; i < ah->caps.total_queues; i++) 1478 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1391 ath9k_hw_resettxqueue(ah, i); 1479 ath9k_hw_resettxqueue(ah, i);
1392 1480
1393 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1481 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
@@ -1395,7 +1483,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1395 ath9k_hw_init_qos(ah); 1483 ath9k_hw_init_qos(ah);
1396 1484
1397 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1485 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1398 ath9k_enable_rfkill(ah); 1486 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1399 1487
1400 ath9k_hw_init_global_settings(ah); 1488 ath9k_hw_init_global_settings(ah);
1401 1489
@@ -1404,8 +1492,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1404 ar9002_hw_enable_wep_aggregation(ah); 1492 ar9002_hw_enable_wep_aggregation(ah);
1405 } 1493 }
1406 1494
1407 REG_WRITE(ah, AR_STA_ID1, 1495 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1408 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1409 1496
1410 ath9k_hw_set_dma(ah); 1497 ath9k_hw_set_dma(ah);
1411 1498
@@ -1432,7 +1519,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1432 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1519 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1433 1520
1434 REGWRITE_BUFFER_FLUSH(ah); 1521 REGWRITE_BUFFER_FLUSH(ah);
1435 DISABLE_REGWRITE_BUFFER(ah);
1436 1522
1437 /* 1523 /*
1438 * For big endian systems turn on swapping for descriptors 1524 * For big endian systems turn on swapping for descriptors
@@ -1441,13 +1527,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1441 u32 mask; 1527 u32 mask;
1442 mask = REG_READ(ah, AR_CFG); 1528 mask = REG_READ(ah, AR_CFG);
1443 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1529 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1444 ath_print(common, ATH_DBG_RESET, 1530 ath_dbg(common, ATH_DBG_RESET,
1445 "CFG Byte Swap Set 0x%x\n", mask); 1531 "CFG Byte Swap Set 0x%x\n", mask);
1446 } else { 1532 } else {
1447 mask = 1533 mask =
1448 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1534 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1449 REG_WRITE(ah, AR_CFG, mask); 1535 REG_WRITE(ah, AR_CFG, mask);
1450 ath_print(common, ATH_DBG_RESET, 1536 ath_dbg(common, ATH_DBG_RESET,
1451 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1537 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1452 } 1538 }
1453 } else { 1539 } else {
@@ -1459,7 +1545,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1459 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1545 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1460 } 1546 }
1461#ifdef __BIG_ENDIAN 1547#ifdef __BIG_ENDIAN
1462 else 1548 else if (AR_SREV_9340(ah))
1549 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1550 else
1463 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1551 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1464#endif 1552#endif
1465 } 1553 }
@@ -1467,289 +1555,17 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1467 if (ah->btcoex_hw.enabled) 1555 if (ah->btcoex_hw.enabled)
1468 ath9k_hw_btcoex_enable(ah); 1556 ath9k_hw_btcoex_enable(ah);
1469 1557
1470 if (AR_SREV_9300_20_OR_LATER(ah)) 1558 if (AR_SREV_9300_20_OR_LATER(ah)) {
1471 ar9003_hw_bb_watchdog_config(ah); 1559 ar9003_hw_bb_watchdog_config(ah);
1472 1560
1473 return 0; 1561 ar9003_hw_disable_phy_restart(ah);
1474}
1475EXPORT_SYMBOL(ath9k_hw_reset);
1476
1477/************************/
1478/* Key Cache Management */
1479/************************/
1480
1481bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1482{
1483 u32 keyType;
1484
1485 if (entry >= ah->caps.keycache_size) {
1486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1487 "keychache entry %u out of range\n", entry);
1488 return false;
1489 } 1562 }
1490 1563
1491 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 1564 ath9k_hw_apply_gpio_override(ah);
1492 1565
1493 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 1566 return 0;
1494 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1495 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1496 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1497 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1498 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1499 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1500 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1501
1502 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1503 u16 micentry = entry + 64;
1504
1505 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1506 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1507 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1508 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1509
1510 }
1511
1512 return true;
1513}
1514EXPORT_SYMBOL(ath9k_hw_keyreset);
1515
1516static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1517{
1518 u32 macHi, macLo;
1519 u32 unicast_flag = AR_KEYTABLE_VALID;
1520
1521 if (entry >= ah->caps.keycache_size) {
1522 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1523 "keychache entry %u out of range\n", entry);
1524 return false;
1525 }
1526
1527 if (mac != NULL) {
1528 /*
1529 * AR_KEYTABLE_VALID indicates that the address is a unicast
1530 * address, which must match the transmitter address for
1531 * decrypting frames.
1532 * Not setting this bit allows the hardware to use the key
1533 * for multicast frame decryption.
1534 */
1535 if (mac[0] & 0x01)
1536 unicast_flag = 0;
1537
1538 macHi = (mac[5] << 8) | mac[4];
1539 macLo = (mac[3] << 24) |
1540 (mac[2] << 16) |
1541 (mac[1] << 8) |
1542 mac[0];
1543 macLo >>= 1;
1544 macLo |= (macHi & 1) << 31;
1545 macHi >>= 1;
1546 } else {
1547 macLo = macHi = 0;
1548 }
1549 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1550 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
1551
1552 return true;
1553}
1554
1555bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1556 const struct ath9k_keyval *k,
1557 const u8 *mac)
1558{
1559 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1560 struct ath_common *common = ath9k_hw_common(ah);
1561 u32 key0, key1, key2, key3, key4;
1562 u32 keyType;
1563
1564 if (entry >= pCap->keycache_size) {
1565 ath_print(common, ATH_DBG_FATAL,
1566 "keycache entry %u out of range\n", entry);
1567 return false;
1568 }
1569
1570 switch (k->kv_type) {
1571 case ATH9K_CIPHER_AES_OCB:
1572 keyType = AR_KEYTABLE_TYPE_AES;
1573 break;
1574 case ATH9K_CIPHER_AES_CCM:
1575 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1576 ath_print(common, ATH_DBG_ANY,
1577 "AES-CCM not supported by mac rev 0x%x\n",
1578 ah->hw_version.macRev);
1579 return false;
1580 }
1581 keyType = AR_KEYTABLE_TYPE_CCM;
1582 break;
1583 case ATH9K_CIPHER_TKIP:
1584 keyType = AR_KEYTABLE_TYPE_TKIP;
1585 if (ATH9K_IS_MIC_ENABLED(ah)
1586 && entry + 64 >= pCap->keycache_size) {
1587 ath_print(common, ATH_DBG_ANY,
1588 "entry %u inappropriate for TKIP\n", entry);
1589 return false;
1590 }
1591 break;
1592 case ATH9K_CIPHER_WEP:
1593 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1594 ath_print(common, ATH_DBG_ANY,
1595 "WEP key length %u too small\n", k->kv_len);
1596 return false;
1597 }
1598 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1599 keyType = AR_KEYTABLE_TYPE_40;
1600 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1601 keyType = AR_KEYTABLE_TYPE_104;
1602 else
1603 keyType = AR_KEYTABLE_TYPE_128;
1604 break;
1605 case ATH9K_CIPHER_CLR:
1606 keyType = AR_KEYTABLE_TYPE_CLR;
1607 break;
1608 default:
1609 ath_print(common, ATH_DBG_FATAL,
1610 "cipher %u not supported\n", k->kv_type);
1611 return false;
1612 }
1613
1614 key0 = get_unaligned_le32(k->kv_val + 0);
1615 key1 = get_unaligned_le16(k->kv_val + 4);
1616 key2 = get_unaligned_le32(k->kv_val + 6);
1617 key3 = get_unaligned_le16(k->kv_val + 10);
1618 key4 = get_unaligned_le32(k->kv_val + 12);
1619 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1620 key4 &= 0xff;
1621
1622 /*
1623 * Note: Key cache registers access special memory area that requires
1624 * two 32-bit writes to actually update the values in the internal
1625 * memory. Consequently, the exact order and pairs used here must be
1626 * maintained.
1627 */
1628
1629 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1630 u16 micentry = entry + 64;
1631
1632 /*
1633 * Write inverted key[47:0] first to avoid Michael MIC errors
1634 * on frames that could be sent or received at the same time.
1635 * The correct key will be written in the end once everything
1636 * else is ready.
1637 */
1638 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1639 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1640
1641 /* Write key[95:48] */
1642 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1643 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1644
1645 /* Write key[127:96] and key type */
1646 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1647 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1648
1649 /* Write MAC address for the entry */
1650 (void) ath9k_hw_keysetmac(ah, entry, mac);
1651
1652 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1653 /*
1654 * TKIP uses two key cache entries:
1655 * Michael MIC TX/RX keys in the same key cache entry
1656 * (idx = main index + 64):
1657 * key0 [31:0] = RX key [31:0]
1658 * key1 [15:0] = TX key [31:16]
1659 * key1 [31:16] = reserved
1660 * key2 [31:0] = RX key [63:32]
1661 * key3 [15:0] = TX key [15:0]
1662 * key3 [31:16] = reserved
1663 * key4 [31:0] = TX key [63:32]
1664 */
1665 u32 mic0, mic1, mic2, mic3, mic4;
1666
1667 mic0 = get_unaligned_le32(k->kv_mic + 0);
1668 mic2 = get_unaligned_le32(k->kv_mic + 4);
1669 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1670 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1671 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1672
1673 /* Write RX[31:0] and TX[31:16] */
1674 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1675 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1676
1677 /* Write RX[63:32] and TX[15:0] */
1678 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1679 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1680
1681 /* Write TX[63:32] and keyType(reserved) */
1682 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1683 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1684 AR_KEYTABLE_TYPE_CLR);
1685
1686 } else {
1687 /*
1688 * TKIP uses four key cache entries (two for group
1689 * keys):
1690 * Michael MIC TX/RX keys are in different key cache
1691 * entries (idx = main index + 64 for TX and
1692 * main index + 32 + 96 for RX):
1693 * key0 [31:0] = TX/RX MIC key [31:0]
1694 * key1 [31:0] = reserved
1695 * key2 [31:0] = TX/RX MIC key [63:32]
1696 * key3 [31:0] = reserved
1697 * key4 [31:0] = reserved
1698 *
1699 * Upper layer code will call this function separately
1700 * for TX and RX keys when these registers offsets are
1701 * used.
1702 */
1703 u32 mic0, mic2;
1704
1705 mic0 = get_unaligned_le32(k->kv_mic + 0);
1706 mic2 = get_unaligned_le32(k->kv_mic + 4);
1707
1708 /* Write MIC key[31:0] */
1709 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1710 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1711
1712 /* Write MIC key[63:32] */
1713 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1714 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1715
1716 /* Write TX[63:32] and keyType(reserved) */
1717 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1718 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1719 AR_KEYTABLE_TYPE_CLR);
1720 }
1721
1722 /* MAC address registers are reserved for the MIC entry */
1723 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1724 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1725
1726 /*
1727 * Write the correct (un-inverted) key[47:0] last to enable
1728 * TKIP now that all other registers are set with correct
1729 * values.
1730 */
1731 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1732 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1733 } else {
1734 /* Write key[47:0] */
1735 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1736 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1737
1738 /* Write key[95:48] */
1739 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1740 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1741
1742 /* Write key[127:96] and key type */
1743 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1744 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1745
1746 /* Write MAC address for the entry */
1747 (void) ath9k_hw_keysetmac(ah, entry, mac);
1748 }
1749
1750 return true;
1751} 1567}
1752EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); 1568EXPORT_SYMBOL(ath9k_hw_reset);
1753 1569
1754/******************************/ 1570/******************************/
1755/* Power Management (Chipset) */ 1571/* Power Management (Chipset) */
@@ -1852,9 +1668,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1852 AR_RTC_FORCE_WAKE_EN); 1668 AR_RTC_FORCE_WAKE_EN);
1853 } 1669 }
1854 if (i == 0) { 1670 if (i == 0) {
1855 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1671 ath_err(ath9k_hw_common(ah),
1856 "Failed to wakeup in %uus\n", 1672 "Failed to wakeup in %uus\n",
1857 POWER_UP_TIME / 20); 1673 POWER_UP_TIME / 20);
1858 return false; 1674 return false;
1859 } 1675 }
1860 } 1676 }
@@ -1878,8 +1694,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1878 if (ah->power_mode == mode) 1694 if (ah->power_mode == mode)
1879 return status; 1695 return status;
1880 1696
1881 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 1697 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1882 modes[ah->power_mode], modes[mode]); 1698 modes[ah->power_mode], modes[mode]);
1883 1699
1884 switch (mode) { 1700 switch (mode) {
1885 case ATH9K_PM_AWAKE: 1701 case ATH9K_PM_AWAKE:
@@ -1893,12 +1709,20 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1893 ath9k_set_power_network_sleep(ah, setChip); 1709 ath9k_set_power_network_sleep(ah, setChip);
1894 break; 1710 break;
1895 default: 1711 default:
1896 ath_print(common, ATH_DBG_FATAL, 1712 ath_err(common, "Unknown power mode %u\n", mode);
1897 "Unknown power mode %u\n", mode);
1898 return false; 1713 return false;
1899 } 1714 }
1900 ah->power_mode = mode; 1715 ah->power_mode = mode;
1901 1716
1717 /*
1718 * XXX: If this warning never comes up after a while then
1719 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1720 * ath9k_hw_setpower() return type void.
1721 */
1722
1723 if (!(ah->ah_flags & AH_UNPLUGGED))
1724 ATH_DBG_WARN_ON_ONCE(!status);
1725
1902 return status; 1726 return status;
1903} 1727}
1904EXPORT_SYMBOL(ath9k_hw_setpower); 1728EXPORT_SYMBOL(ath9k_hw_setpower);
@@ -1911,60 +1735,39 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1911{ 1735{
1912 int flags = 0; 1736 int flags = 0;
1913 1737
1914 ah->beacon_interval = beacon_period;
1915
1916 ENABLE_REGWRITE_BUFFER(ah); 1738 ENABLE_REGWRITE_BUFFER(ah);
1917 1739
1918 switch (ah->opmode) { 1740 switch (ah->opmode) {
1919 case NL80211_IFTYPE_STATION:
1920 case NL80211_IFTYPE_MONITOR:
1921 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1922 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1923 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1924 flags |= AR_TBTT_TIMER_EN;
1925 break;
1926 case NL80211_IFTYPE_ADHOC: 1741 case NL80211_IFTYPE_ADHOC:
1927 case NL80211_IFTYPE_MESH_POINT: 1742 case NL80211_IFTYPE_MESH_POINT:
1928 REG_SET_BIT(ah, AR_TXCFG, 1743 REG_SET_BIT(ah, AR_TXCFG,
1929 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1744 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1930 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1745 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1931 TU_TO_USEC(next_beacon + 1746 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1932 (ah->atim_window ? ah->
1933 atim_window : 1)));
1934 flags |= AR_NDP_TIMER_EN; 1747 flags |= AR_NDP_TIMER_EN;
1935 case NL80211_IFTYPE_AP: 1748 case NL80211_IFTYPE_AP:
1936 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1749 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1937 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1750 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1938 TU_TO_USEC(next_beacon - 1751 TU_TO_USEC(ah->config.dma_beacon_response_time));
1939 ah->config. 1752 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1940 dma_beacon_response_time)); 1753 TU_TO_USEC(ah->config.sw_beacon_response_time));
1941 REG_WRITE(ah, AR_NEXT_SWBA,
1942 TU_TO_USEC(next_beacon -
1943 ah->config.
1944 sw_beacon_response_time));
1945 flags |= 1754 flags |=
1946 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1755 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1947 break; 1756 break;
1948 default: 1757 default:
1949 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 1758 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1950 "%s: unsupported opmode: %d\n", 1759 "%s: unsupported opmode: %d\n",
1951 __func__, ah->opmode); 1760 __func__, ah->opmode);
1952 return; 1761 return;
1953 break; 1762 break;
1954 } 1763 }
1955 1764
1956 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1765 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1957 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1766 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1958 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1767 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1959 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1768 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1960 1769
1961 REGWRITE_BUFFER_FLUSH(ah); 1770 REGWRITE_BUFFER_FLUSH(ah);
1962 DISABLE_REGWRITE_BUFFER(ah);
1963
1964 beacon_period &= ~ATH9K_BEACON_ENA;
1965 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1966 ath9k_hw_reset_tsf(ah);
1967 }
1968 1771
1969 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1772 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1970} 1773}
@@ -1987,7 +1790,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1987 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1790 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1988 1791
1989 REGWRITE_BUFFER_FLUSH(ah); 1792 REGWRITE_BUFFER_FLUSH(ah);
1990 DISABLE_REGWRITE_BUFFER(ah);
1991 1793
1992 REG_RMW_FIELD(ah, AR_RSSI_THR, 1794 REG_RMW_FIELD(ah, AR_RSSI_THR,
1993 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1795 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
@@ -2006,10 +1808,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2006 else 1808 else
2007 nextTbtt = bs->bs_nexttbtt; 1809 nextTbtt = bs->bs_nexttbtt;
2008 1810
2009 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1811 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2010 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1812 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2011 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1813 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2012 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1814 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2013 1815
2014 ENABLE_REGWRITE_BUFFER(ah); 1816 ENABLE_REGWRITE_BUFFER(ah);
2015 1817
@@ -2033,7 +1835,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2033 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1835 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2034 1836
2035 REGWRITE_BUFFER_FLUSH(ah); 1837 REGWRITE_BUFFER_FLUSH(ah);
2036 DISABLE_REGWRITE_BUFFER(ah);
2037 1838
2038 REG_SET_BIT(ah, AR_TIMER_MODE, 1839 REG_SET_BIT(ah, AR_TIMER_MODE,
2039 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1840 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
@@ -2055,18 +1856,17 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2055 struct ath_common *common = ath9k_hw_common(ah); 1856 struct ath_common *common = ath9k_hw_common(ah);
2056 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1857 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2057 1858
2058 u16 capField = 0, eeval; 1859 u16 eeval;
1860 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2059 1861
2060 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1862 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2061 regulatory->current_rd = eeval; 1863 regulatory->current_rd = eeval;
2062 1864
2063 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 1865 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2064 if (AR_SREV_9285_10_OR_LATER(ah)) 1866 if (AR_SREV_9285_12_OR_LATER(ah))
2065 eeval |= AR9285_RDEXT_DEFAULT; 1867 eeval |= AR9285_RDEXT_DEFAULT;
2066 regulatory->current_rd_ext = eeval; 1868 regulatory->current_rd_ext = eeval;
2067 1869
2068 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2069
2070 if (ah->opmode != NL80211_IFTYPE_AP && 1870 if (ah->opmode != NL80211_IFTYPE_AP &&
2071 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 1871 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2072 if (regulatory->current_rd == 0x64 || 1872 if (regulatory->current_rd == 0x64 ||
@@ -2074,48 +1874,22 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2074 regulatory->current_rd += 5; 1874 regulatory->current_rd += 5;
2075 else if (regulatory->current_rd == 0x41) 1875 else if (regulatory->current_rd == 0x41)
2076 regulatory->current_rd = 0x43; 1876 regulatory->current_rd = 0x43;
2077 ath_print(common, ATH_DBG_REGULATORY, 1877 ath_dbg(common, ATH_DBG_REGULATORY,
2078 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1878 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2079 } 1879 }
2080 1880
2081 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1881 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2082 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1882 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2083 ath_print(common, ATH_DBG_FATAL, 1883 ath_err(common,
2084 "no band has been marked as supported in EEPROM.\n"); 1884 "no band has been marked as supported in EEPROM\n");
2085 return -EINVAL; 1885 return -EINVAL;
2086 } 1886 }
2087 1887
2088 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 1888 if (eeval & AR5416_OPFLAGS_11A)
1889 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2089 1890
2090 if (eeval & AR5416_OPFLAGS_11A) { 1891 if (eeval & AR5416_OPFLAGS_11G)
2091 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 1892 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2092 if (ah->config.ht_enable) {
2093 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2094 set_bit(ATH9K_MODE_11NA_HT20,
2095 pCap->wireless_modes);
2096 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2097 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2098 pCap->wireless_modes);
2099 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2100 pCap->wireless_modes);
2101 }
2102 }
2103 }
2104
2105 if (eeval & AR5416_OPFLAGS_11G) {
2106 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2107 if (ah->config.ht_enable) {
2108 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2109 set_bit(ATH9K_MODE_11NG_HT20,
2110 pCap->wireless_modes);
2111 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2112 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2113 pCap->wireless_modes);
2114 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2115 pCap->wireless_modes);
2116 }
2117 }
2118 }
2119 1893
2120 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 1894 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2121 /* 1895 /*
@@ -2127,63 +1901,32 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2127 !(AR_SREV_9271(ah))) 1901 !(AR_SREV_9271(ah)))
2128 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 1902 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2129 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 1903 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1904 else if (AR_SREV_9100(ah))
1905 pCap->rx_chainmask = 0x7;
2130 else 1906 else
2131 /* Use rx_chainmask from EEPROM. */ 1907 /* Use rx_chainmask from EEPROM. */
2132 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 1908 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2133 1909
2134 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 1910 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2135 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2136 1911
2137 pCap->low_2ghz_chan = 2312; 1912 /* enable key search for every frame in an aggregate */
2138 pCap->high_2ghz_chan = 2732; 1913 if (AR_SREV_9300_20_OR_LATER(ah))
2139 1914 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2140 pCap->low_5ghz_chan = 4920;
2141 pCap->high_5ghz_chan = 6100;
2142
2143 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2144 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2145 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2146 1915
2147 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 1916 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2148 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2149 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2150 1917
2151 if (ah->config.ht_enable) 1918 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2152 pCap->hw_caps |= ATH9K_HW_CAP_HT; 1919 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2153 else 1920 else
2154 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 1921 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2155 1922
2156 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2157 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2158 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2159 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2160
2161 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2162 pCap->total_queues =
2163 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2164 else
2165 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2166
2167 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2168 pCap->keycache_size =
2169 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2170 else
2171 pCap->keycache_size = AR_KEYTABLE_SIZE;
2172
2173 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2174
2175 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2176 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2177 else
2178 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2179
2180 if (AR_SREV_9271(ah)) 1923 if (AR_SREV_9271(ah))
2181 pCap->num_gpio_pins = AR9271_NUM_GPIO; 1924 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2182 else if (AR_DEVID_7010(ah)) 1925 else if (AR_DEVID_7010(ah))
2183 pCap->num_gpio_pins = AR7010_NUM_GPIO; 1926 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2184 else if (AR_SREV_9285_10_OR_LATER(ah)) 1927 else if (AR_SREV_9285_12_OR_LATER(ah))
2185 pCap->num_gpio_pins = AR9285_NUM_GPIO; 1928 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2186 else if (AR_SREV_9280_10_OR_LATER(ah)) 1929 else if (AR_SREV_9280_20_OR_LATER(ah))
2187 pCap->num_gpio_pins = AR928X_NUM_GPIO; 1930 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2188 else 1931 else
2189 pCap->num_gpio_pins = AR_NUM_GPIO; 1932 pCap->num_gpio_pins = AR_NUM_GPIO;
@@ -2195,8 +1938,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2195 pCap->rts_aggr_limit = (8 * 1024); 1938 pCap->rts_aggr_limit = (8 * 1024);
2196 } 1939 }
2197 1940
2198 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2199
2200#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1941#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2201 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 1942 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2202 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 1943 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
@@ -2218,52 +1959,40 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2218 else 1959 else
2219 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 1960 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2220 1961
2221 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 1962 if (common->btcoex_enabled) {
2222 pCap->reg_cap = 1963 if (AR_SREV_9300_20_OR_LATER(ah)) {
2223 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2224 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2225 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2226 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2227 } else {
2228 pCap->reg_cap =
2229 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2230 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2231 }
2232
2233 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2234 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2235 AR_SREV_5416(ah))
2236 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2237
2238 pCap->num_antcfg_5ghz =
2239 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2240 pCap->num_antcfg_2ghz =
2241 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2242
2243 if (AR_SREV_9280_10_OR_LATER(ah) &&
2244 ath9k_hw_btcoex_supported(ah)) {
2245 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2246 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2247
2248 if (AR_SREV_9285(ah)) {
2249 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 1964 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2250 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 1965 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2251 } else { 1966 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2252 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 1967 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
1968 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1969 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
1970 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
1971
1972 if (AR_SREV_9285(ah)) {
1973 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1974 btcoex_hw->btpriority_gpio =
1975 ATH_BTPRIORITY_GPIO_9285;
1976 } else {
1977 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1978 }
2253 } 1979 }
2254 } else { 1980 } else {
2255 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 1981 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2256 } 1982 }
2257 1983
2258 if (AR_SREV_9300_20_OR_LATER(ah)) { 1984 if (AR_SREV_9300_20_OR_LATER(ah)) {
2259 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | 1985 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2260 ATH9K_HW_CAP_FASTCLOCK; 1986 if (!AR_SREV_9485(ah))
1987 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1988
2261 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 1989 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2262 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 1990 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2263 pCap->rx_status_len = sizeof(struct ar9003_rxs); 1991 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2264 pCap->tx_desc_len = sizeof(struct ar9003_txc); 1992 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2265 pCap->txs_len = sizeof(struct ar9003_txs); 1993 pCap->txs_len = sizeof(struct ar9003_txs);
2266 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 1994 if (!ah->config.paprd_disable &&
1995 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2267 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 1996 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2268 } else { 1997 } else {
2269 pCap->tx_desc_len = sizeof(struct ath_desc); 1998 pCap->tx_desc_len = sizeof(struct ath_desc);
@@ -2277,9 +2006,59 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2277 if (AR_SREV_9300_20_OR_LATER(ah)) 2006 if (AR_SREV_9300_20_OR_LATER(ah))
2278 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2007 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2279 2008
2280 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah)) 2009 if (AR_SREV_9300_20_OR_LATER(ah))
2010 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2011
2012 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2281 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2013 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2282 2014
2015 if (AR_SREV_9285(ah))
2016 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2017 ant_div_ctl1 =
2018 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2019 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2020 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2021 }
2022 if (AR_SREV_9300_20_OR_LATER(ah)) {
2023 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2024 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2025 }
2026
2027
2028 if (AR_SREV_9485(ah)) {
2029 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2030 /*
2031 * enable the diversity-combining algorithm only when
2032 * both enable_lna_div and enable_fast_div are set
2033 * Table for Diversity
2034 * ant_div_alt_lnaconf bit 0-1
2035 * ant_div_main_lnaconf bit 2-3
2036 * ant_div_alt_gaintb bit 4
2037 * ant_div_main_gaintb bit 5
2038 * enable_ant_div_lnadiv bit 6
2039 * enable_ant_fast_div bit 7
2040 */
2041 if ((ant_div_ctl1 >> 0x6) == 0x3)
2042 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2043 }
2044
2045 if (AR_SREV_9485_10(ah)) {
2046 pCap->pcie_lcr_extsync_en = true;
2047 pCap->pcie_lcr_offset = 0x80;
2048 }
2049
2050 tx_chainmask = pCap->tx_chainmask;
2051 rx_chainmask = pCap->rx_chainmask;
2052 while (tx_chainmask || rx_chainmask) {
2053 if (tx_chainmask & BIT(0))
2054 pCap->max_txchains++;
2055 if (rx_chainmask & BIT(0))
2056 pCap->max_rxchains++;
2057
2058 tx_chainmask >>= 1;
2059 rx_chainmask >>= 1;
2060 }
2061
2283 return 0; 2062 return 0;
2284} 2063}
2285 2064
@@ -2350,14 +2129,15 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2350 val = REG_READ(ah, AR7010_GPIO_IN); 2129 val = REG_READ(ah, AR7010_GPIO_IN);
2351 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2130 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2352 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2131 } else if (AR_SREV_9300_20_OR_LATER(ah))
2353 return MS_REG_READ(AR9300, gpio) != 0; 2132 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2133 AR_GPIO_BIT(gpio)) != 0;
2354 else if (AR_SREV_9271(ah)) 2134 else if (AR_SREV_9271(ah))
2355 return MS_REG_READ(AR9271, gpio) != 0; 2135 return MS_REG_READ(AR9271, gpio) != 0;
2356 else if (AR_SREV_9287_10_OR_LATER(ah)) 2136 else if (AR_SREV_9287_11_OR_LATER(ah))
2357 return MS_REG_READ(AR9287, gpio) != 0; 2137 return MS_REG_READ(AR9287, gpio) != 0;
2358 else if (AR_SREV_9285_10_OR_LATER(ah)) 2138 else if (AR_SREV_9285_12_OR_LATER(ah))
2359 return MS_REG_READ(AR9285, gpio) != 0; 2139 return MS_REG_READ(AR9285, gpio) != 0;
2360 else if (AR_SREV_9280_10_OR_LATER(ah)) 2140 else if (AR_SREV_9280_20_OR_LATER(ah))
2361 return MS_REG_READ(AR928X, gpio) != 0; 2141 return MS_REG_READ(AR928X, gpio) != 0;
2362 else 2142 else
2363 return MS_REG_READ(AR, gpio) != 0; 2143 return MS_REG_READ(AR, gpio) != 0;
@@ -2449,14 +2229,11 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2449 REG_WRITE(ah, AR_PHY_ERR, phybits); 2229 REG_WRITE(ah, AR_PHY_ERR, phybits);
2450 2230
2451 if (phybits) 2231 if (phybits)
2452 REG_WRITE(ah, AR_RXCFG, 2232 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2453 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2454 else 2233 else
2455 REG_WRITE(ah, AR_RXCFG, 2234 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2456 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2457 2235
2458 REGWRITE_BUFFER_FLUSH(ah); 2236 REGWRITE_BUFFER_FLUSH(ah);
2459 DISABLE_REGWRITE_BUFFER(ah);
2460} 2237}
2461EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2238EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2462 2239
@@ -2483,7 +2260,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
2483} 2260}
2484EXPORT_SYMBOL(ath9k_hw_disable); 2261EXPORT_SYMBOL(ath9k_hw_disable);
2485 2262
2486void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 2263void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2487{ 2264{
2488 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2265 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2489 struct ath9k_channel *chan = ah->curchan; 2266 struct ath9k_channel *chan = ah->curchan;
@@ -2496,7 +2273,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2496 channel->max_antenna_gain * 2, 2273 channel->max_antenna_gain * 2,
2497 channel->max_power * 2, 2274 channel->max_power * 2,
2498 min((u32) MAX_RATE_POWER, 2275 min((u32) MAX_RATE_POWER,
2499 (u32) regulatory->power_limit)); 2276 (u32) regulatory->power_limit), test);
2500} 2277}
2501EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2278EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2502 2279
@@ -2556,8 +2333,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
2556{ 2333{
2557 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2334 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2558 AH_TSF_WRITE_TIMEOUT)) 2335 AH_TSF_WRITE_TIMEOUT))
2559 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 2336 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2560 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2337 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2561 2338
2562 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2339 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2563} 2340}
@@ -2648,9 +2425,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2648 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2425 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2649 2426
2650 if (timer == NULL) { 2427 if (timer == NULL) {
2651 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2428 ath_err(ath9k_hw_common(ah),
2652 "Failed to allocate memory" 2429 "Failed to allocate memory for hw timer[%d]\n",
2653 "for hw timer[%d]\n", timer_index); 2430 timer_index);
2654 return NULL; 2431 return NULL;
2655 } 2432 }
2656 2433
@@ -2667,11 +2444,11 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
2667 2444
2668void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2445void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2669 struct ath_gen_timer *timer, 2446 struct ath_gen_timer *timer,
2670 u32 timer_next, 2447 u32 trig_timeout,
2671 u32 timer_period) 2448 u32 timer_period)
2672{ 2449{
2673 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2450 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2674 u32 tsf; 2451 u32 tsf, timer_next;
2675 2452
2676 BUG_ON(!timer_period); 2453 BUG_ON(!timer_period);
2677 2454
@@ -2679,16 +2456,11 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2679 2456
2680 tsf = ath9k_hw_gettsf32(ah); 2457 tsf = ath9k_hw_gettsf32(ah);
2681 2458
2682 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2459 timer_next = tsf + trig_timeout;
2683 "curent tsf %x period %x"
2684 "timer_next %x\n", tsf, timer_period, timer_next);
2685 2460
2686 /* 2461 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2687 * Pull timer_next forward if the current TSF already passed it 2462 "current tsf %x period %x timer_next %x\n",
2688 * because of software latency 2463 tsf, timer_period, timer_next);
2689 */
2690 if (timer_next < tsf)
2691 timer_next = tsf + timer_period;
2692 2464
2693 /* 2465 /*
2694 * Program generic timer registers 2466 * Program generic timer registers
@@ -2761,8 +2533,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
2761 index = rightmost_index(timer_table, &thresh_mask); 2533 index = rightmost_index(timer_table, &thresh_mask);
2762 timer = timer_table->timers[index]; 2534 timer = timer_table->timers[index];
2763 BUG_ON(!timer); 2535 BUG_ON(!timer);
2764 ath_print(common, ATH_DBG_HWTIMER, 2536 ath_dbg(common, ATH_DBG_HWTIMER,
2765 "TSF overflow for Gen timer %d\n", index); 2537 "TSF overflow for Gen timer %d\n", index);
2766 timer->overflow(timer->arg); 2538 timer->overflow(timer->arg);
2767 } 2539 }
2768 2540
@@ -2770,8 +2542,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
2770 index = rightmost_index(timer_table, &trigger_mask); 2542 index = rightmost_index(timer_table, &trigger_mask);
2771 timer = timer_table->timers[index]; 2543 timer = timer_table->timers[index];
2772 BUG_ON(!timer); 2544 BUG_ON(!timer);
2773 ath_print(common, ATH_DBG_HWTIMER, 2545 ath_dbg(common, ATH_DBG_HWTIMER,
2774 "Gen timer[%d] trigger\n", index); 2546 "Gen timer[%d] trigger\n", index);
2775 timer->trigger(timer->arg); 2547 timer->trigger(timer->arg);
2776 } 2548 }
2777} 2549}
@@ -2802,6 +2574,7 @@ static struct {
2802 { AR_SREV_VERSION_9287, "9287" }, 2574 { AR_SREV_VERSION_9287, "9287" },
2803 { AR_SREV_VERSION_9271, "9271" }, 2575 { AR_SREV_VERSION_9271, "9271" },
2804 { AR_SREV_VERSION_9300, "9300" }, 2576 { AR_SREV_VERSION_9300, "9300" },
2577 { AR_SREV_VERSION_9485, "9485" },
2805}; 2578};
2806 2579
2807/* For devices with external radios */ 2580/* For devices with external radios */
@@ -2854,7 +2627,7 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2854 int used; 2627 int used;
2855 2628
2856 /* chipsets >= AR9280 are single-chip */ 2629 /* chipsets >= AR9280 are single-chip */
2857 if (AR_SREV_9280_10_OR_LATER(ah)) { 2630 if (AR_SREV_9280_20_OR_LATER(ah)) {
2858 used = snprintf(hw_name, len, 2631 used = snprintf(hw_name, len,
2859 "Atheros AR%s Rev:%x", 2632 "Atheros AR%s Rev:%x",
2860 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2633 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 00:50:44 -0400