70 files changed, 17203 insertions, 10553 deletions

diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index 35f23bdc442f..d9c08c619a3a 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -5,7 +5,7 @@ config ATH9K_COMMON
 
 config ATH9K
         tristate "Atheros 802.11n wireless cards support"
-        depends on PCI && MAC80211
+        depends on MAC80211
         select ATH9K_HW
         select MAC80211_LEDS
         select LEDS_CLASS
@@ -23,6 +23,24 @@ config ATH9K
 
           If you choose to build a module, it'll be called ath9k.
 
+config ATH9K_PCI
+        bool "Atheros ath9k PCI/PCIe bus support"
+        depends on ATH9K && PCI
+        ---help---
+          This option enables the PCI bus support in ath9k.
+
+          Say Y, if you have a compatible PCI/PCIe wireless card.
+
+config ATH9K_AHB
+        bool "Atheros ath9k AHB bus support"
+        depends on ATH9K
+        default n
+        ---help---
+          This option enables the AHB bus support in ath9k.
+
+          Say Y, if you have a SoC with a compatible built-in
+          wireless MAC. Say N if unsure.
+
 config ATH9K_DEBUGFS
         bool "Atheros ath9k debugging"
         depends on ATH9K && DEBUG_FS
@@ -32,6 +50,14 @@ config ATH9K_DEBUGFS
 
           Also required for changing debug message flags at run time.
 
+config ATH9K_RATE_CONTROL
+        bool "Atheros ath9k rate control"
+        depends on ATH9K
+        default y
+        ---help---
+          Say Y, if you want to use the ath9k specific rate control
+          module instead of minstrel_ht.
+
 config ATH9K_HTC
        tristate "Atheros HTC based wireless cards support"
        depends on USB && MAC80211
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 973ae4f49f35..05a6fade7b1c 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -4,11 +4,10 @@ ath9k-y +=	beacon.o \
                 main.o \
                 recv.o \
                 xmit.o \
-                virtual.o \
-                rc.o
 
-ath9k-$(CONFIG_PCI) += pci.o
-ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o
+ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
+ath9k-$(CONFIG_ATH9K_PCI) += pci.o
+ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
 
 obj-$(CONFIG_ATH9K) += ath9k.o
@@ -46,6 +45,9 @@ ath9k_htc-y +=	htc_hst.o \
                 htc_drv_txrx.o \
                 htc_drv_main.o \
                 htc_drv_beacon.o \
-                htc_drv_init.o
+                htc_drv_init.o \
+                htc_drv_gpio.o
+
+ath9k_htc-$(CONFIG_ATH9K_HTC_DEBUGFS) += htc_drv_debug.o
 
 obj-$(CONFIG_ATH9K_HTC) += ath9k_htc.o
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 1a984b02e9e5..5b49cd03bfdf 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
  * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
  *
@@ -21,6 +21,18 @@
 #include <linux/ath9k_platform.h>
 #include "ath9k.h"
 
+static const struct platform_device_id ath9k_platform_id_table[] = {
+        {
+                .name = "ath9k",
+                .driver_data = AR5416_AR9100_DEVID,
+        },
+        {
+                .name = "ar934x_wmac",
+                .driver_data = AR9300_DEVID_AR9340,
+        },
+        {},
+};
+
 /* return bus cachesize in 4B word units */
 static void ath_ahb_read_cachesize(struct ath_common *common, int *csz)
 {
@@ -35,10 +47,9 @@ static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 
         pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
         if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "%s: flash read failed, offset %08x "
-                          "is out of range\n",
-                          __func__, off);
+                ath_err(common,
+                        "%s: flash read failed, offset %08x is out of range\n",
+                        __func__, off);
                 return false;
         }
 
@@ -55,10 +66,10 @@ static struct ath_bus_ops ath_ahb_bus_ops  = {
 static int ath_ahb_probe(struct platform_device *pdev)
 {
         void __iomem *mem;
-        struct ath_wiphy *aphy;
         struct ath_softc *sc;
         struct ieee80211_hw *hw;
         struct resource *res;
+        const struct platform_device_id *id = platform_get_device_id(pdev);
         int irq;
         int ret = 0;
         struct ath_hw *ah;
@@ -77,7 +88,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
                 goto err_out;
         }
 
-        mem = ioremap_nocache(res->start, res->end - res->start + 1);
+        mem = ioremap_nocache(res->start, resource_size(res));
         if (mem == NULL) {
                 dev_err(&pdev->dev, "ioremap failed\n");
                 ret = -ENOMEM;
@@ -93,8 +104,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
 
         irq = res->start;
 
-        hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
-                                sizeof(struct ath_softc), &ath9k_ops);
+        hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
         if (hw == NULL) {
                 dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
                 ret = -ENOMEM;
@@ -104,11 +114,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
         SET_IEEE80211_DEV(hw, &pdev->dev);
         platform_set_drvdata(pdev, hw);
 
-        aphy = hw->priv;
-        sc = (struct ath_softc *) (aphy + 1);
-        aphy->sc = sc;
-        aphy->hw = hw;
-        sc->pri_wiphy = aphy;
+        sc = hw->priv;
         sc->hw = hw;
         sc->dev = &pdev->dev;
         sc->mem = mem;
@@ -123,7 +129,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
                 goto err_free_hw;
         }
 
-        ret = ath9k_init_device(AR5416_AR9100_DEVID, sc, 0x0, &ath_ahb_bus_ops);
+        ret = ath9k_init_device(id->driver_data, sc, 0x0, &ath_ahb_bus_ops);
         if (ret) {
                 dev_err(&pdev->dev, "failed to initialize device\n");
                 goto err_irq;
@@ -152,8 +158,7 @@ static int ath_ahb_remove(struct platform_device *pdev)
         struct ieee80211_hw *hw = platform_get_drvdata(pdev);
 
         if (hw) {
-                struct ath_wiphy *aphy = hw->priv;
-                struct ath_softc *sc = aphy->sc;
+                struct ath_softc *sc = hw->priv;
                 void __iomem *mem = sc->mem;
 
                 ath9k_deinit_device(sc);
@@ -173,8 +178,11 @@ static struct platform_driver ath_ahb_driver = {
                 .name   = "ath9k",
                 .owner  = THIS_MODULE,
         },
+        .id_table    = ath9k_platform_id_table,
 };
 
+MODULE_DEVICE_TABLE(platform, ath9k_platform_id_table);
+
 int ath_ahb_init(void)
 {
         return platform_driver_register(&ath_ahb_driver);
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index a3d95cca8f0c..bfb6481f01f9 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/kernel.h>
 #include "hw.h"
 #include "hw-ops.h"
 
@@ -48,7 +49,7 @@ static const struct ani_ofdm_level_entry ofdm_level_table[] = {
         {  7,  8,  0  }  /* lvl 9 */
 };
 #define ATH9K_ANI_OFDM_NUM_LEVEL \
-        (sizeof(ofdm_level_table)/sizeof(ofdm_level_table[0]))
+        ARRAY_SIZE(ofdm_level_table)
 #define ATH9K_ANI_OFDM_MAX_LEVEL \
         (ATH9K_ANI_OFDM_NUM_LEVEL-1)
 #define ATH9K_ANI_OFDM_DEF_LEVEL \
@@ -94,7 +95,7 @@ static const struct ani_cck_level_entry cck_level_table[] = {
 };
 
 #define ATH9K_ANI_CCK_NUM_LEVEL \
-        (sizeof(cck_level_table)/sizeof(cck_level_table[0]))
+        ARRAY_SIZE(cck_level_table)
 #define ATH9K_ANI_CCK_MAX_LEVEL \
         (ATH9K_ANI_CCK_NUM_LEVEL-1)
 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
@@ -102,31 +103,9 @@ static const struct ani_cck_level_entry cck_level_table[] = {
 #define ATH9K_ANI_CCK_DEF_LEVEL \
         2 /* default level - matches the INI settings */
 
-/* Private to ani.c */
-static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
+static bool use_new_ani(struct ath_hw *ah)
 {
-        ath9k_hw_private_ops(ah)->ani_lower_immunity(ah);
-}
-
-int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
-                                 struct ath9k_channel *chan)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
-                if (ah->ani[i].c &&
-                    ah->ani[i].c->channel == chan->channel)
-                        return i;
-                if (ah->ani[i].c == NULL) {
-                        ah->ani[i].c = chan;
-                        return i;
-                }
-        }
-
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
-                  "No more channel states left. Using channel 0\n");
-
-        return 0;
+        return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
 }
 
 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
@@ -139,82 +118,34 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
 }
 
-static void ath9k_ani_restart_old(struct ath_hw *ah)
+static void ath9k_ani_restart(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
+        u32 ofdm_base = 0, cck_base = 0;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
         aniState->listenTime = 0;
 
-        if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
-                aniState->ofdmPhyErrBase = 0;
-                ath_print(common, ATH_DBG_ANI,
-                          "OFDM Trigger is too high for hw counters\n");
-        } else {
-                aniState->ofdmPhyErrBase =
-                        AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
-        }
-        if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
-                aniState->cckPhyErrBase = 0;
-                ath_print(common, ATH_DBG_ANI,
-                          "CCK Trigger is too high for hw counters\n");
-        } else {
-                aniState->cckPhyErrBase =
-                        AR_PHY_COUNTMAX - aniState->cckTrigHigh;
+        if (!use_new_ani(ah)) {
+                ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
+                cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
         }
-        ath_print(common, ATH_DBG_ANI,
-                  "Writing ofdmbase=%u   cckbase=%u\n",
-                  aniState->ofdmPhyErrBase,
-                  aniState->cckPhyErrBase);
-
-        ENABLE_REGWRITE_BUFFER(ah);
-
-        REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
-        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
-
-        REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
-
-        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
-
-        aniState->ofdmPhyErrCount = 0;
-        aniState->cckPhyErrCount = 0;
-}
 
-static void ath9k_ani_restart_new(struct ath_hw *ah)
-{
-        struct ar5416AniState *aniState;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
-        aniState->listenTime = 0;
-
-        aniState->ofdmPhyErrBase = 0;
-        aniState->cckPhyErrBase = 0;
-
-        ath_print(common, ATH_DBG_ANI,
-                  "Writing ofdmbase=%08x   cckbase=%08x\n",
-                  aniState->ofdmPhyErrBase,
-                  aniState->cckPhyErrBase);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Writing ofdmbase=%u   cckbase=%u\n", ofdm_base, cck_base);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
-        REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
+        REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
+        REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -228,10 +159,7 @@ static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
         struct ar5416AniState *aniState;
         int32_t rssi;
 
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
 
         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
@@ -300,10 +228,7 @@ static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
         struct ar5416AniState *aniState;
         int32_t rssi;
 
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
                                          aniState->noiseImmunityLevel + 1)) {
@@ -335,18 +260,18 @@ static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
 /* Adjust the OFDM Noise Immunity Level */
 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath_common *common = ath9k_hw_common(ah);
         const struct ani_ofdm_level_entry *entry_ofdm;
         const struct ani_cck_level_entry *entry_cck;
 
         aniState->noiseFloor = BEACON_RSSI(ah);
 
-        ath_print(common, ATH_DBG_ANI,
-                  "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
-                  aniState->ofdmNoiseImmunityLevel,
-                  immunityLevel, aniState->noiseFloor,
-                  aniState->rssiThrLow, aniState->rssiThrHigh);
+        ath_dbg(common, ATH_DBG_ANI,
+                "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
+                aniState->ofdmNoiseImmunityLevel,
+                immunityLevel, aniState->noiseFloor,
+                aniState->rssiThrLow, aniState->rssiThrHigh);
 
         aniState->ofdmNoiseImmunityLevel = immunityLevel;
 
@@ -380,14 +305,19 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
         }
 }
 
-static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
+static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        if (!use_new_ani(ah)) {
+                ath9k_hw_ani_ofdm_err_trigger_old(ah);
+                return;
+        }
+
+        aniState = &ah->curchan->ani;
 
         if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
                 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
@@ -398,17 +328,17 @@ static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
  */
 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath_common *common = ath9k_hw_common(ah);
         const struct ani_ofdm_level_entry *entry_ofdm;
         const struct ani_cck_level_entry *entry_cck;
 
         aniState->noiseFloor = BEACON_RSSI(ah);
-        ath_print(common, ATH_DBG_ANI,
-                  "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
-                  aniState->cckNoiseImmunityLevel, immunityLevel,
-                  aniState->noiseFloor, aniState->rssiThrLow,
-                  aniState->rssiThrHigh);
+        ath_dbg(common, ATH_DBG_ANI,
+                "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
+                aniState->cckNoiseImmunityLevel, immunityLevel,
+                aniState->noiseFloor, aniState->rssiThrLow,
+                aniState->rssiThrHigh);
 
         if ((ah->opmode == NL80211_IFTYPE_STATION ||
              ah->opmode == NL80211_IFTYPE_ADHOC) &&
@@ -428,7 +358,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
                                      entry_cck->fir_step_level);
 
         /* Skip MRC CCK for pre AR9003 families */
-        if (!AR_SREV_9300_20_OR_LATER(ah))
+        if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
                 return;
 
         if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
@@ -437,14 +367,19 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
                                      entry_cck->mrc_cck_on);
 }
 
-static void ath9k_hw_ani_cck_err_trigger_new(struct ath_hw *ah)
+static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        if (!use_new_ani(ah)) {
+                ath9k_hw_ani_cck_err_trigger_old(ah);
+                return;
+        }
+
+        aniState = &ah->curchan->ani;
 
         if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
                 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
@@ -455,7 +390,7 @@ static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
         struct ar5416AniState *aniState;
         int32_t rssi;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
 
         if (ah->opmode == NL80211_IFTYPE_AP) {
                 if (aniState->firstepLevel > 0) {
@@ -507,11 +442,16 @@ static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
  * only lower either OFDM or CCK errors per turn
  * we lower the other one next time
  */
-static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
+static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
 {
         struct ar5416AniState *aniState;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
+
+        if (!use_new_ani(ah)) {
+                ath9k_hw_ani_lower_immunity_old(ah);
+                return;
+        }
 
         /* lower OFDM noise immunity */
         if (aniState->ofdmNoiseImmunityLevel > 0 &&
@@ -525,90 +465,21 @@ static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
                 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
 }
 
-static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
-{
-        struct ath9k_channel *chan = ah->curchan;
-        struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
-        u8 clockrate; /* in MHz */
-
-        if (!ah->curchan) /* should really check for CCK instead */
-                clockrate = ATH9K_CLOCK_RATE_CCK;
-        else if (conf->channel->band == IEEE80211_BAND_2GHZ)
-                clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
-        else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
-                clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
-        else
-                clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
-
-        if (conf_is_ht40(conf))
-                return clockrate * 2;
-
-        return clockrate;
-}
-
-static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
-{
-        struct ar5416AniState *aniState;
-        struct ath_common *common = ath9k_hw_common(ah);
-        u32 txFrameCount, rxFrameCount, cycleCount;
-        int32_t listenTime;
-
-        txFrameCount = REG_READ(ah, AR_TFCNT);
-        rxFrameCount = REG_READ(ah, AR_RFCNT);
-        cycleCount = REG_READ(ah, AR_CCCNT);
-
-        aniState = ah->curani;
-        if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
-                listenTime = 0;
-                ah->stats.ast_ani_lzero++;
-                ath_print(common, ATH_DBG_ANI,
-                          "1st call: aniState->cycleCount=%d\n",
-                          aniState->cycleCount);
-        } else {
-                int32_t ccdelta = cycleCount - aniState->cycleCount;
-                int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
-                int32_t tfdelta = txFrameCount - aniState->txFrameCount;
-                int32_t clock_rate;
-
-                /*
-                 * convert HW counter values to ms using mode
-                 * specifix clock rate
-                 */
-                clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
-
-                listenTime = (ccdelta - rfdelta - tfdelta) / clock_rate;
-
-                ath_print(common, ATH_DBG_ANI,
-                          "cyclecount=%d, rfcount=%d, "
-                          "tfcount=%d, listenTime=%d CLOCK_RATE=%d\n",
-                          ccdelta, rfdelta, tfdelta, listenTime, clock_rate);
-        }
-
-        aniState->cycleCount = cycleCount;
-        aniState->txFrameCount = txFrameCount;
-        aniState->rxFrameCount = rxFrameCount;
-
-        return listenTime;
-}
-
 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
 {
         struct ar5416AniState *aniState;
         struct ath9k_channel *chan = ah->curchan;
         struct ath_common *common = ath9k_hw_common(ah);
-        int index;
 
         if (!DO_ANI(ah))
                 return;
 
-        index = ath9k_hw_get_ani_channel_idx(ah, chan);
-        aniState = &ah->ani[index];
-        ah->curani = aniState;
+        aniState = &ah->curchan->ani;
 
-        if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
+        if (ah->opmode != NL80211_IFTYPE_STATION
             && ah->opmode != NL80211_IFTYPE_ADHOC) {
-                ath_print(common, ATH_DBG_ANI,
-                          "Reset ANI state opmode %u\n", ah->opmode);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Reset ANI state opmode %u\n", ah->opmode);
                 ah->stats.ast_ani_reset++;
 
                 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -634,17 +505,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
                 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
                                      ATH9K_RX_FILTER_PHYERR);
 
-                if (ah->opmode == NL80211_IFTYPE_AP) {
-                        ah->curani->ofdmTrigHigh =
-                                ah->config.ofdm_trig_high;
-                        ah->curani->ofdmTrigLow =
-                                ah->config.ofdm_trig_low;
-                        ah->curani->cckTrigHigh =
-                                ah->config.cck_trig_high;
-                        ah->curani->cckTrigLow =
-                                ah->config.cck_trig_low;
-                }
-                ath9k_ani_restart_old(ah);
+                ath9k_ani_restart(ah);
                 return;
         }
 
@@ -666,7 +527,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
 
         ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
                              ~ATH9K_RX_FILTER_PHYERR);
-        ath9k_ani_restart_old(ah);
+        ath9k_ani_restart(ah);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -674,7 +535,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /*
@@ -682,15 +542,18 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
  * This routine should be called for every hardware reset and for
  * every channel change.
  */
-static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
+void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath9k_channel *chan = ah->curchan;
         struct ath_common *common = ath9k_hw_common(ah);
 
         if (!DO_ANI(ah))
                 return;
 
+        if (!use_new_ani(ah))
+                return ath9k_ani_reset_old(ah, is_scanning);
+
         BUG_ON(aniState == NULL);
         ah->stats.ast_ani_reset++;
 
@@ -721,16 +584,14 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
                     ATH9K_ANI_OFDM_DEF_LEVEL ||
                     aniState->cckNoiseImmunityLevel !=
                     ATH9K_ANI_CCK_DEF_LEVEL) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "Restore defaults: opmode %u "
-                                  "chan %d Mhz/0x%x is_scanning=%d "
-                                  "ofdm:%d cck:%d\n",
-                                  ah->opmode,
-                                  chan->channel,
-                                  chan->channelFlags,
-                                  is_scanning,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  aniState->cckNoiseImmunityLevel);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
+                                ah->opmode,
+                                chan->channel,
+                                chan->channelFlags,
+                                is_scanning,
+                                aniState->ofdmNoiseImmunityLevel,
+                                aniState->cckNoiseImmunityLevel);
 
                         ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
                         ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
@@ -739,16 +600,14 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
                 /*
                  * restore historical levels for this channel
                  */
-                ath_print(common, ATH_DBG_ANI,
-                          "Restore history: opmode %u "
-                          "chan %d Mhz/0x%x is_scanning=%d "
-                          "ofdm:%d cck:%d\n",
-                          ah->opmode,
-                          chan->channel,
-                          chan->channelFlags,
-                          is_scanning,
-                          aniState->ofdmNoiseImmunityLevel,
-                          aniState->cckNoiseImmunityLevel);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
+                        ah->opmode,
+                        chan->channel,
+                        chan->channelFlags,
+                        is_scanning,
+                        aniState->ofdmNoiseImmunityLevel,
+                        aniState->cckNoiseImmunityLevel);
 
                         ath9k_hw_set_ofdm_nil(ah,
                                               aniState->ofdmNoiseImmunityLevel);
@@ -760,7 +619,7 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
          * enable phy counters if hw supports or if not, enable phy
          * interrupts (so we can count each one)
          */
-        ath9k_ani_restart_new(ah);
+        ath9k_ani_restart(ah);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -768,28 +627,30 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
-static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
-                                     struct ath9k_channel *chan)
+static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
 {
-        struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
-        int32_t listenTime;
-        u32 phyCnt1, phyCnt2;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
+        u32 ofdm_base = 0;
+        u32 cck_base = 0;
         u32 ofdmPhyErrCnt, cckPhyErrCnt;
+        u32 phyCnt1, phyCnt2;
+        int32_t listenTime;
 
-        if (!DO_ANI(ah))
-                return;
-
-        aniState = ah->curani;
+        ath_hw_cycle_counters_update(common);
+        listenTime = ath_hw_get_listen_time(common);
 
-        listenTime = ath9k_hw_ani_get_listen_time(ah);
-        if (listenTime < 0) {
+        if (listenTime <= 0) {
                 ah->stats.ast_ani_lneg++;
-                ath9k_ani_restart_old(ah);
-                return;
+                ath9k_ani_restart(ah);
+                return false;
+        }
+
+        if (!use_new_ani(ah)) {
+                ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
+                cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
         }
 
         aniState->listenTime += listenTime;
@@ -799,215 +660,95 @@ static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
 
-        if (phyCnt1 < aniState->ofdmPhyErrBase ||
-            phyCnt2 < aniState->cckPhyErrBase) {
-                if (phyCnt1 < aniState->ofdmPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt1 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt1,
-                                  aniState->ofdmPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_1,
-                                  aniState->ofdmPhyErrBase);
+        if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
+                if (phyCnt1 < ofdm_base) {
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "phyCnt1 0x%x, resetting counter value to 0x%x\n",
+                                phyCnt1, ofdm_base);
+                        REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
                         REG_WRITE(ah, AR_PHY_ERR_MASK_1,
                                   AR_PHY_ERR_OFDM_TIMING);
                 }
-                if (phyCnt2 < aniState->cckPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt2 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt2,
-                                  aniState->cckPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_2,
-                                  aniState->cckPhyErrBase);
+                if (phyCnt2 < cck_base) {
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "phyCnt2 0x%x, resetting counter value to 0x%x\n",
+                                phyCnt2, cck_base);
+                        REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
                         REG_WRITE(ah, AR_PHY_ERR_MASK_2,
                                   AR_PHY_ERR_CCK_TIMING);
                 }
-                return;
+                return false;
         }
 
-        ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
+        ofdmPhyErrCnt = phyCnt1 - ofdm_base;
         ah->stats.ast_ani_ofdmerrs +=
                 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
         aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
 
-        cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
+        cckPhyErrCnt = phyCnt2 - cck_base;
         ah->stats.ast_ani_cckerrs +=
                 cckPhyErrCnt - aniState->cckPhyErrCount;
         aniState->cckPhyErrCount = cckPhyErrCnt;
-
-        if (aniState->listenTime > 5 * ah->aniperiod) {
-                if (aniState->ofdmPhyErrCount <= aniState->listenTime *
-                    aniState->ofdmTrigLow / 1000 &&
-                    aniState->cckPhyErrCount <= aniState->listenTime *
-                    aniState->cckTrigLow / 1000)
-                        ath9k_hw_ani_lower_immunity(ah);
-                ath9k_ani_restart_old(ah);
-        } else if (aniState->listenTime > ah->aniperiod) {
-                if (aniState->ofdmPhyErrCount > aniState->listenTime *
-                    aniState->ofdmTrigHigh / 1000) {
-                        ath9k_hw_ani_ofdm_err_trigger_old(ah);
-                        ath9k_ani_restart_old(ah);
-                } else if (aniState->cckPhyErrCount >
-                           aniState->listenTime * aniState->cckTrigHigh /
-                           1000) {
-                        ath9k_hw_ani_cck_err_trigger_old(ah);
-                        ath9k_ani_restart_old(ah);
-                }
-        }
+        return true;
 }
 
-static void ath9k_hw_ani_monitor_new(struct ath_hw *ah,
-                                     struct ath9k_channel *chan)
+void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
 {
         struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
-        int32_t listenTime;
-        u32 phyCnt1, phyCnt2;
-        u32 ofdmPhyErrCnt, cckPhyErrCnt;
         u32 ofdmPhyErrRate, cckPhyErrRate;
 
         if (!DO_ANI(ah))
                 return;
 
-        aniState = ah->curani;
+        aniState = &ah->curchan->ani;
         if (WARN_ON(!aniState))
                 return;
 
-        listenTime = ath9k_hw_ani_get_listen_time(ah);
-        if (listenTime <= 0) {
-                ah->stats.ast_ani_lneg++;
-                /* restart ANI period if listenTime is invalid */
-                ath_print(common, ATH_DBG_ANI,
-                          "listenTime=%d - on new ani monitor\n",
-                          listenTime);
-                ath9k_ani_restart_new(ah);
+        if (!ath9k_hw_ani_read_counters(ah))
                 return;
-        }
-
-        aniState->listenTime += listenTime;
-
-        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
-
-        phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
-        phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
-
-        if (phyCnt1 < aniState->ofdmPhyErrBase ||
-            phyCnt2 < aniState->cckPhyErrBase) {
-                if (phyCnt1 < aniState->ofdmPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt1 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt1,
-                                  aniState->ofdmPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_1,
-                                  aniState->ofdmPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_MASK_1,
-                                  AR_PHY_ERR_OFDM_TIMING);
-                }
-                if (phyCnt2 < aniState->cckPhyErrBase) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt2 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt2,
-                                  aniState->cckPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_2,
-                                  aniState->cckPhyErrBase);
-                        REG_WRITE(ah, AR_PHY_ERR_MASK_2,
-                                  AR_PHY_ERR_CCK_TIMING);
-                }
-                return;
-        }
-
-        ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
-        ah->stats.ast_ani_ofdmerrs +=
-                ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
-        aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
-
-        cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
-        ah->stats.ast_ani_cckerrs +=
-                cckPhyErrCnt - aniState->cckPhyErrCount;
-        aniState->cckPhyErrCount = cckPhyErrCnt;
-
-        ath_print(common, ATH_DBG_ANI,
-                  "Errors: OFDM=0x%08x-0x%08x=%d   "
-                  "CCK=0x%08x-0x%08x=%d\n",
-                  phyCnt1,
-                  aniState->ofdmPhyErrBase,
-                  ofdmPhyErrCnt,
-                  phyCnt2,
-                  aniState->cckPhyErrBase,
-                  cckPhyErrCnt);
 
         ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
                          aniState->listenTime;
         cckPhyErrRate =  aniState->cckPhyErrCount * 1000 /
                          aniState->listenTime;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
-                  "errs=%d/s ofdm_turn=%d\n",
-                  listenTime, aniState->ofdmNoiseImmunityLevel,
-                  ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
-                  cckPhyErrRate, aniState->ofdmsTurn);
+        ath_dbg(common, ATH_DBG_ANI,
+                "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
+                aniState->listenTime,
+                aniState->ofdmNoiseImmunityLevel,
+                ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
+                cckPhyErrRate, aniState->ofdmsTurn);
 
         if (aniState->listenTime > 5 * ah->aniperiod) {
-                if (ofdmPhyErrRate <= aniState->ofdmTrigLow &&
-                    cckPhyErrRate <= aniState->cckTrigLow) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "1. listenTime=%d OFDM:%d errs=%d/s(<%d)  "
-                                  "CCK:%d errs=%d/s(<%d) -> "
-                                  "ath9k_hw_ani_lower_immunity()\n",
-                                  aniState->listenTime,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  ofdmPhyErrRate,
-                                  aniState->ofdmTrigLow,
-                                  aniState->cckNoiseImmunityLevel,
-                                  cckPhyErrRate,
-                                  aniState->cckTrigLow);
+                if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
+                    cckPhyErrRate <= ah->config.cck_trig_low) {
                         ath9k_hw_ani_lower_immunity(ah);
                         aniState->ofdmsTurn = !aniState->ofdmsTurn;
                 }
-                ath_print(common, ATH_DBG_ANI,
-                          "1 listenTime=%d ofdm=%d/s cck=%d/s - "
-                          "calling ath9k_ani_restart_new()\n",
-                          aniState->listenTime, ofdmPhyErrRate, cckPhyErrRate);
-                ath9k_ani_restart_new(ah);
+                ath9k_ani_restart(ah);
         } else if (aniState->listenTime > ah->aniperiod) {
                 /* check to see if need to raise immunity */
-                if (ofdmPhyErrRate > aniState->ofdmTrigHigh &&
-                    (cckPhyErrRate <= aniState->cckTrigHigh ||
+                if (ofdmPhyErrRate > ah->config.ofdm_trig_high &&
+                    (cckPhyErrRate <= ah->config.cck_trig_high ||
                      aniState->ofdmsTurn)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "2 listenTime=%d OFDM:%d errs=%d/s(>%d) -> "
-                                  "ath9k_hw_ani_ofdm_err_trigger_new()\n",
-                                  aniState->listenTime,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  ofdmPhyErrRate,
-                                  aniState->ofdmTrigHigh);
-                        ath9k_hw_ani_ofdm_err_trigger_new(ah);
-                        ath9k_ani_restart_new(ah);
+                        ath9k_hw_ani_ofdm_err_trigger(ah);
+                        ath9k_ani_restart(ah);
                         aniState->ofdmsTurn = false;
-                } else if (cckPhyErrRate > aniState->cckTrigHigh) {
-                        ath_print(common, ATH_DBG_ANI,
-                                 "3 listenTime=%d CCK:%d errs=%d/s(>%d) -> "
-                                 "ath9k_hw_ani_cck_err_trigger_new()\n",
-                                 aniState->listenTime,
-                                 aniState->cckNoiseImmunityLevel,
-                                 cckPhyErrRate,
-                                 aniState->cckTrigHigh);
-                        ath9k_hw_ani_cck_err_trigger_new(ah);
-                        ath9k_ani_restart_new(ah);
+                } else if (cckPhyErrRate > ah->config.cck_trig_high) {
+                        ath9k_hw_ani_cck_err_trigger(ah);
+                        ath9k_ani_restart(ah);
                         aniState->ofdmsTurn = true;
                 }
         }
 }
+EXPORT_SYMBOL(ath9k_hw_ani_monitor);
 
 void ath9k_enable_mib_counters(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
+        ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");
 
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -1022,7 +763,6 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /* Freeze the MIB counters, get the stats and then clear them */
@@ -1030,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
+        ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");
 
         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -1040,53 +780,12 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
 
-u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
-                                  u32 *rxc_pcnt,
-                                  u32 *rxf_pcnt,
-                                  u32 *txf_pcnt)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        static u32 cycles, rx_clear, rx_frame, tx_frame;
-        u32 good = 1;
-
-        u32 rc = REG_READ(ah, AR_RCCNT);
-        u32 rf = REG_READ(ah, AR_RFCNT);
-        u32 tf = REG_READ(ah, AR_TFCNT);
-        u32 cc = REG_READ(ah, AR_CCCNT);
-
-        if (cycles == 0 || cycles > cc) {
-                ath_print(common, ATH_DBG_ANI,
-                          "cycle counter wrap. ExtBusy = 0\n");
-                good = 0;
-        } else {
-                u32 cc_d = cc - cycles;
-                u32 rc_d = rc - rx_clear;
-                u32 rf_d = rf - rx_frame;
-                u32 tf_d = tf - tx_frame;
-
-                if (cc_d != 0) {
-                        *rxc_pcnt = rc_d * 100 / cc_d;
-                        *rxf_pcnt = rf_d * 100 / cc_d;
-                        *txf_pcnt = tf_d * 100 / cc_d;
-                } else {
-                        good = 0;
-                }
-        }
-
-        cycles = cc;
-        rx_frame = rf;
-        rx_clear = rc;
-        tx_frame = tf;
-
-        return good;
-}
-
 /*
  * Process a MIB interrupt.  We may potentially be invoked because
  * any of the MIB counters overflow/trigger so don't assume we're
  * here because a PHY error counter triggered.
  */
-static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah)
+void ath9k_hw_proc_mib_event(struct ath_hw *ah)
 {
         u32 phyCnt1, phyCnt2;
 
@@ -1114,81 +813,24 @@ static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah)
         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
-                struct ar5416AniState *aniState = ah->curani;
-                u32 ofdmPhyErrCnt, cckPhyErrCnt;
 
-                /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
-                ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
-                ah->stats.ast_ani_ofdmerrs +=
-                        ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
-                aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
+                if (!use_new_ani(ah))
+                        ath9k_hw_ani_read_counters(ah);
 
-                cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
-                ah->stats.ast_ani_cckerrs +=
-                        cckPhyErrCnt - aniState->cckPhyErrCount;
-                aniState->cckPhyErrCount = cckPhyErrCnt;
-
-                /*
-                 * NB: figure out which counter triggered.  If both
-                 * trigger we'll only deal with one as the processing
-                 * clobbers the error counter so the trigger threshold
-                 * check will never be true.
-                 */
-                if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
-                        ath9k_hw_ani_ofdm_err_trigger_new(ah);
-                if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
-                        ath9k_hw_ani_cck_err_trigger_old(ah);
                 /* NB: always restart to insure the h/w counters are reset */
-                ath9k_ani_restart_old(ah);
-        }
-}
-
-/*
- * Process a MIB interrupt.  We may potentially be invoked because
- * any of the MIB counters overflow/trigger so don't assume we're
- * here because a PHY error counter triggered.
- */
-static void ath9k_hw_proc_mib_event_new(struct ath_hw *ah)
-{
-        u32 phyCnt1, phyCnt2;
-
-        /* Reset these counters regardless */
-        REG_WRITE(ah, AR_FILT_OFDM, 0);
-        REG_WRITE(ah, AR_FILT_CCK, 0);
-        if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
-                REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
-
-        /* Clear the mib counters and save them in the stats */
-        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
-
-        if (!DO_ANI(ah)) {
-                /*
-                 * We must always clear the interrupt cause by
-                 * resetting the phy error regs.
-                 */
-                REG_WRITE(ah, AR_PHY_ERR_1, 0);
-                REG_WRITE(ah, AR_PHY_ERR_2, 0);
-                return;
+                ath9k_ani_restart(ah);
         }
-
-        /* NB: these are not reset-on-read */
-        phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
-        phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
-
-        /* NB: always restart to insure the h/w counters are reset */
-        if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
-            ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK))
-                ath9k_ani_restart_new(ah);
 }
+EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
 
 void ath9k_hw_ani_setup(struct ath_hw *ah)
 {
         int i;
 
-        const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
-        const int coarseHigh[] = { -14, -14, -14, -14, -12 };
-        const int coarseLow[] = { -64, -64, -64, -64, -70 };
-        const int firpwr[] = { -78, -78, -78, -78, -80 };
+        static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
+        static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
+        static const int coarseLow[] = { -64, -64, -64, -64, -70 };
+        static const int firpwr[] = { -78, -78, -78, -78, -80 };
 
         for (i = 0; i < 5; i++) {
                 ah->totalSizeDesired[i] = totalSizeDesired[i];
@@ -1203,69 +845,60 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         int i;
 
-        ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
+        ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");
 
-        memset(ah->ani, 0, sizeof(ah->ani));
-        for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
-                if (AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani) {
-                        ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
-                        ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
+        if (use_new_ani(ah)) {
+                ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
+                ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
 
-                        ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
-                        ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW_NEW;
+                ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
+                ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
+        } else {
+                ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
+                ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
 
-                        ah->ani[i].spurImmunityLevel =
-                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
+                ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
+                ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
+        }
 
-                        ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
+        for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
+                struct ath9k_channel *chan = &ah->channels[i];
+                struct ar5416AniState *ani = &chan->ani;
 
-                        ah->ani[i].ofdmPhyErrBase = 0;
-                        ah->ani[i].cckPhyErrBase = 0;
+                if (use_new_ani(ah)) {
+                        ani->spurImmunityLevel =
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
+
+                        ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
 
                         if (AR_SREV_9300_20_OR_LATER(ah))
-                                ah->ani[i].mrcCCKOff =
+                                ani->mrcCCKOff =
                                         !ATH9K_ANI_ENABLE_MRC_CCK;
                         else
-                                ah->ani[i].mrcCCKOff = true;
+                                ani->mrcCCKOff = true;
 
-                        ah->ani[i].ofdmsTurn = true;
+                        ani->ofdmsTurn = true;
                 } else {
-                        ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
-                        ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
-
-                        ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
-                        ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW_OLD;
-
-                        ah->ani[i].spurImmunityLevel =
+                        ani->spurImmunityLevel =
                                 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
-                        ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
+                        ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
 
-                        ah->ani[i].ofdmPhyErrBase =
-                                AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
-                        ah->ani[i].cckPhyErrBase =
-                                AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH_OLD;
-                        ah->ani[i].cckWeakSigThreshold =
+                        ani->cckWeakSigThreshold =
                                 ATH9K_ANI_CCK_WEAK_SIG_THR;
                 }
 
-                ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
-                ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
-                ah->ani[i].ofdmWeakSigDetectOff =
+                ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
+                ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
+                ani->ofdmWeakSigDetectOff =
                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
-                ah->ani[i].cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
+                ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
         }
 
         /*
          * since we expect some ongoing maintenance on the tables, let's sanity
          * check here default level should not modify INI setting.
          */
-        if (AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani) {
-                const struct ani_ofdm_level_entry *entry_ofdm;
-                const struct ani_cck_level_entry *entry_cck;
-
-                entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL];
-                entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL];
-
+        if (use_new_ani(ah)) {
                 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
                 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
         } else {
@@ -1273,50 +906,9 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
                 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Setting OfdmErrBase = 0x%08x\n",
-                  ah->ani[0].ofdmPhyErrBase);
-        ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
-                  ah->ani[0].cckPhyErrBase);
-
-        ENABLE_REGWRITE_BUFFER(ah);
-
-        REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
-        REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
-
-        REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
-
-        ath9k_enable_mib_counters(ah);
-
         if (ah->config.enable_ani)
                 ah->proc_phyerr |= HAL_PROCESS_ANI;
-}
-
-void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
-
-        priv_ops->ani_reset = ath9k_ani_reset_old;
-        priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_old;
-
-        ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_old;
-        ops->ani_monitor = ath9k_hw_ani_monitor_old;
-
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v1\n");
-}
-
-void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 
-        priv_ops->ani_reset = ath9k_ani_reset_new;
-        priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_new;
-
-        ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_new;
-        ops->ani_monitor = ath9k_hw_ani_monitor_new;
-
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v2\n");
+        ath9k_ani_restart(ah);
+        ath9k_enable_mib_counters(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
index f4d0a4d48b37..dbab5b9ce494 100644
--- a/drivers/net/wireless/ath/ath9k/ani.h
+++ b/drivers/net/wireless/ath/ath9k/ani.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,7 +19,7 @@
 
 #define HAL_PROCESS_ANI           0x00000001
 
-#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI))
+#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI) && ah->curchan)
 
 #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
 
@@ -123,20 +123,11 @@ struct ar5416AniState {
         u8 ofdmWeakSigDetectOff;
         u8 cckWeakSigThreshold;
         u32 listenTime;
-        u32 ofdmTrigHigh;
-        u32 ofdmTrigLow;
-        int32_t cckTrigHigh;
-        int32_t cckTrigLow;
         int32_t rssiThrLow;
         int32_t rssiThrHigh;
         u32 noiseFloor;
-        u32 txFrameCount;
-        u32 rxFrameCount;
-        u32 cycleCount;
         u32 ofdmPhyErrCount;
         u32 cckPhyErrCount;
-        u32 ofdmPhyErrBase;
-        u32 cckPhyErrBase;
         int16_t pktRssi[2];
         int16_t ofdmErrRssi[2];
         int16_t cckErrRssi[2];
@@ -166,8 +157,6 @@ struct ar5416Stats {
 
 void ath9k_enable_mib_counters(struct ath_hw *ah);
 void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
-u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
-                                  u32 *rxf_pcnt, u32 *txf_pcnt);
 void ath9k_hw_ani_setup(struct ath_hw *ah);
 void ath9k_hw_ani_init(struct ath_hw *ah);
 int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
index 36f7d0639db3..234617c948a1 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 3d2c8679bc85..441bb33f17ad 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -44,6 +44,34 @@ static const int m1ThreshExt_off = 127;
 static const int m2ThreshExt_off = 127;
 
 
+static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
+                                 int col)
+{
+        int i;
+
+        for (i = 0; i < array->ia_rows; i++)
+                bank[i] = INI_RA(array, i, col);
+}
+
+
+#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
+        ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
+
+static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                                  u32 *data, unsigned int *writecnt)
+{
+        int r;
+
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        for (r = 0; r < array->ia_rows; r++) {
+                REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
+                DO_DELAY(*writecnt);
+        }
+
+        REGWRITE_BUFFER_FLUSH(ah);
+}
+
 /**
  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  * @rfbuf:
@@ -118,7 +146,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
         if (!AR_SREV_5416(ah) || synth_freq >= 3000)
                 return;
 
-        BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
+        BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 
         if (synth_freq < 2412)
                 new_bias = 0;
@@ -130,9 +158,8 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
         /* pre-reverse this field */
         tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Force rf_pwd_icsyndiv to %1d on %4d\n",
-                  new_bias, synth_freq);
+        ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
+                new_bias, synth_freq);
 
         /* swizzle rf_pwd_icsyndiv */
         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
@@ -143,7 +170,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
 
 /**
  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
- * @ah: atheros hardware stucture
+ * @ah: atheros hardware structure
  * @chan:
  *
  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
@@ -173,8 +200,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                         channelSel = ((freq - 704) * 2 - 3040) / 10;
                         bModeSynth = 1;
                 } else {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Invalid channel %u MHz\n", freq);
+                        ath_err(common, "Invalid channel %u MHz\n", freq);
                         return -EINVAL;
                 }
 
@@ -206,8 +232,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
         } else {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Invalid channel %u MHz\n", freq);
+                ath_err(common, "Invalid channel %u MHz\n", freq);
                 return -EINVAL;
         }
 
@@ -244,13 +269,15 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
         int upper, lower, cur_vit_mask;
         int tmp, new;
         int i;
-        int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                          AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+        static int pilot_mask_reg[4] = {
+                AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
         };
-        int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                         AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+        static int chan_mask_reg[4] = {
+                AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
         };
-        int inc[4] = { 0, 100, 0, 0 };
+        static int inc[4] = { 0, 100, 0, 0 };
 
         int8_t mask_m[123];
         int8_t mask_p[123];
@@ -446,15 +473,14 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 #define ATH_ALLOC_BANK(bank, size) do { \
                 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
                 if (!bank) { \
-                        ath_print(common, ATH_DBG_FATAL, \
-                                  "Cannot allocate RF banks\n"); \
+                        ath_err(common, "Cannot allocate RF banks\n"); \
                         return -ENOMEM; \
                 } \
         } while (0);
 
         struct ath_common *common = ath9k_hw_common(ah);
 
-        BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
+        BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 
         ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
         ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
@@ -484,7 +510,7 @@ static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
                 bank = NULL; \
         } while (0);
 
-        BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
+        BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 
         ATH_FREE_BANK(ah->analogBank0Data);
         ATH_FREE_BANK(ah->analogBank1Data);
@@ -525,23 +551,23 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
          * for single chip devices, that is AR9280 or anything
          * after that.
          */
-        if (AR_SREV_9280_10_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah))
                 return true;
 
         /* Setup rf parameters */
         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 
         /* Setup Bank 0 Write */
-        RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
+        ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
 
         /* Setup Bank 1 Write */
-        RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
+        ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
 
         /* Setup Bank 2 Write */
-        RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
+        ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
 
         /* Setup Bank 6 Write */
-        RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
+        ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
                       modesIndex);
         {
                 int i;
@@ -571,7 +597,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
         }
 
         /* Setup Bank 7 Setup */
-        RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
+        ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
 
         /* Write Analog registers */
         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
@@ -613,14 +639,11 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
         rx_chainmask = ah->rxchainmask;
         tx_chainmask = ah->txchainmask;
 
-        ENABLE_REGWRITE_BUFFER(ah);
 
         switch (rx_chainmask) {
         case 0x5:
-                DISABLE_REGWRITE_BUFFER(ah);
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                             AR_PHY_SWAP_ALT_CHAIN);
-                ENABLE_REGWRITE_BUFFER(ah);
         case 0x3:
                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -630,17 +653,18 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
         case 0x1:
         case 0x2:
         case 0x7:
+                ENABLE_REGWRITE_BUFFER(ah);
                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
                 break;
         default:
+                ENABLE_REGWRITE_BUFFER(ah);
                 break;
         }
 
         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (tx_chainmask == 0x5) {
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
@@ -663,20 +687,20 @@ static void ar5008_hw_override_ini(struct ath_hw *ah,
          */
         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
 
                 if (!AR_SREV_9271(ah))
                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
 
-                if (AR_SREV_9287_10_OR_LATER(ah))
+                if (AR_SREV_9287_11_OR_LATER(ah))
                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
 
                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
         }
 
         if (!AR_SREV_5416_20_OR_LATER(ah) ||
-            AR_SREV_9280_10_OR_LATER(ah))
+            AR_SREV_9280_20_OR_LATER(ah))
                 return;
         /*
          * Disable BB clock gating
@@ -701,7 +725,7 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
         u32 phymode;
         u32 enableDacFifo = 0;
 
-        if (AR_SREV_9285_10_OR_LATER(ah))
+        if (AR_SREV_9285_12_OR_LATER(ah))
                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
                                          AR_PHY_FC_ENABLE_DAC_FIFO);
 
@@ -726,7 +750,6 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 
@@ -734,6 +757,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                                  struct ath9k_channel *chan)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+        struct ath_common *common = ath9k_hw_common(ah);
         int i, regWrites = 0;
         struct ieee80211_channel *channel = chan->chan;
         u32 modesIndex, freqIndex;
@@ -810,7 +834,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                 REG_WRITE(ah, reg, val);
 
                 if (reg >= 0x7800 && reg < 0x78a0
-                    && ah->config.analog_shiftreg) {
+                    && ah->config.analog_shiftreg
+                    && (common->bus_ops->ath_bus_type != ATH_USB)) {
                         udelay(100);
                 }
 
@@ -818,13 +843,12 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
-        if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
+        if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
 
         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
-            AR_SREV_9287_10_OR_LATER(ah))
+            AR_SREV_9287_11_OR_LATER(ah))
                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 
         if (AR_SREV_9271_10(ah))
@@ -841,7 +865,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                 REG_WRITE(ah, reg, val);
 
                 if (reg >= 0x7800 && reg < 0x78a0
-                    && ah->config.analog_shiftreg) {
+                    && ah->config.analog_shiftreg
+                    && (common->bus_ops->ath_bus_type != ATH_USB)) {
                         udelay(100);
                 }
 
@@ -849,7 +874,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (AR_SREV_9271(ah)) {
                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
@@ -878,12 +902,11 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), false);
 
         /* Write analog registers */
         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "ar5416SetRfRegs failed\n");
+                ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
                 return -EIO;
         }
 
@@ -900,7 +923,7 @@ static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 
-        if (!AR_SREV_9280_10_OR_LATER(ah))
+        if (!AR_SREV_9280_20_OR_LATER(ah))
                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 
@@ -969,18 +992,6 @@ static void ar5008_hw_rfbus_done(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
-{
-        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-
-        REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                    AR_GPIO_INPUT_MUX2_RFSILENT);
-
-        ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-        REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar5008_restore_chainmask(struct ath_hw *ah)
 {
         int rx_chainmask = ah->rxchainmask;
@@ -1053,7 +1064,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                                       enum ath9k_ani_cmd cmd,
                                       int param)
 {
-        struct ar5416AniState *aniState = ah->curani;
+        struct ar5416AniState *aniState = &ah->curchan->ani;
         struct ath_common *common = ath9k_hw_common(ah);
 
         switch (cmd & ah->ani_function) {
@@ -1061,10 +1072,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(ah->totalSizeDesired));
                         return false;
                 }
 
@@ -1089,12 +1099,12 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
-                const int m1ThreshLow[] = { 127, 50 };
-                const int m2ThreshLow[] = { 127, 40 };
-                const int m1Thresh[] = { 127, 0x4d };
-                const int m2Thresh[] = { 127, 0x40 };
-                const int m2CountThr[] = { 31, 16 };
-                const int m2CountThrLow[] = { 63, 48 };
+                static const int m1ThreshLow[] = { 127, 50 };
+                static const int m2ThreshLow[] = { 127, 40 };
+                static const int m1Thresh[] = { 127, 0x4d };
+                static const int m2Thresh[] = { 127, 0x40 };
+                static const int m2CountThr[] = { 31, 16 };
+                static const int m2CountThrLow[] = { 63, 48 };
                 u32 on = param ? 1 : 0;
 
                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
@@ -1146,7 +1156,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
-                const int weakSigThrCck[] = { 8, 6 };
+                static const int weakSigThrCck[] = { 8, 6 };
                 u32 high = param ? 1 : 0;
 
                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
@@ -1162,14 +1172,13 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_FIRSTEP_LEVEL:{
-                const int firstep[] = { 0, 4, 8 };
+                static const int firstep[] = { 0, 4, 8 };
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep));
                         return false;
                 }
                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -1183,14 +1192,13 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
-                const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
+                static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1));
                         return false;
                 }
                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -1206,27 +1214,23 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
-        ath_print(common, ATH_DBG_ANI,
-                  "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
-                  "ofdmWeakSigDetectOff=%d\n",
-                  aniState->noiseImmunityLevel,
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff);
-        ath_print(common, ATH_DBG_ANI,
-                  "cckWeakSigThreshold=%d, "
-                  "firstepLevel=%d, listenTime=%d\n",
-                  aniState->cckWeakSigThreshold,
-                  aniState->firstepLevel,
-                  aniState->listenTime);
-        ath_print(common, ATH_DBG_ANI,
-                "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
-                aniState->cycleCount,
+        ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
+        ath_dbg(common, ATH_DBG_ANI,
+                "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
+                aniState->noiseImmunityLevel,
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff);
+        ath_dbg(common, ATH_DBG_ANI,
+                "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
+                aniState->cckWeakSigThreshold,
+                aniState->firstepLevel,
+                aniState->listenTime);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
                 aniState->ofdmPhyErrCount,
                 aniState->cckPhyErrCount);
 
@@ -1237,9 +1241,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                                       enum ath9k_ani_cmd cmd,
                                       int param)
 {
-        struct ar5416AniState *aniState = ah->curani;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
+        struct ar5416AniState *aniState = &chan->ani;
         s32 value, value2;
 
         switch (cmd & ah->ani_function) {
@@ -1310,12 +1314,12 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                 if (!on != aniState->ofdmWeakSigDetectOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: ofdm weak signal: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->ofdmWeakSigDetectOff ?
-                                        "on" : "off",
-                                  on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: ofdm weak signal: %s=>%s\n",
+                                chan->channel,
+                                !aniState->ofdmWeakSigDetectOff ?
+                                "on" : "off",
+                                on ? "on" : "off");
                         if (on)
                                 ah->stats.ast_ani_ofdmon++;
                         else
@@ -1328,11 +1332,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_FIRSTEP_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep_table));
                         return false;
                 }
 
@@ -1367,24 +1369,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                               AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
 
                 if (level != aniState->firstepLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.firstep);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep_low[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.firstepLow);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value,
+                                aniState->iniDef.firstep);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value2,
+                                aniState->iniDef.firstepLow);
                         if (level > aniState->firstepLevel)
                                 ah->stats.ast_ani_stepup++;
                         else if (level < aniState->firstepLevel)
@@ -1397,11 +1397,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1_table));
                         return false;
                 }
                 /*
@@ -1435,24 +1433,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                               AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
 
                 if (level != aniState->spurImmunityLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.cycpwrThr1);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1Ext[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.cycpwrThr1Ext);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value,
+                                aniState->iniDef.cycpwrThr1);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value2,
+                                aniState->iniDef.cycpwrThr1Ext);
                         if (level > aniState->spurImmunityLevel)
                                 ah->stats.ast_ani_spurup++;
                         else if (level < aniState->spurImmunityLevel)
@@ -1471,24 +1467,19 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                  "MRCcck=%s listenTime=%d CC=%d listen=%d "
-                  "ofdmErrs=%d cckErrs=%d\n",
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
-                  aniState->firstepLevel,
-                  !aniState->mrcCCKOff ? "on" : "off",
-                  aniState->listenTime,
-                  aniState->cycleCount,
-                  aniState->listenTime,
-                  aniState->ofdmPhyErrCount,
-                  aniState->cckPhyErrCount);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+                aniState->firstepLevel,
+                !aniState->mrcCCKOff ? "on" : "off",
+                aniState->listenTime,
+                aniState->ofdmPhyErrCount,
+                aniState->cckPhyErrCount);
         return true;
 }
 
@@ -1498,25 +1489,25 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
-        nfarray[2] = sign_extend(nf, 9);
+        nfarray[2] = sign_extend32(nf, 8);
 
         if (!IS_CHAN_HT40(ah->curchan))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-        nfarray[3] = sign_extend(nf, 9);
+        nfarray[3] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
-        nfarray[4] = sign_extend(nf, 9);
+        nfarray[4] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
-        nfarray[5] = sign_extend(nf, 9);
+        nfarray[5] = sign_extend32(nf, 8);
 }
 
 /*
@@ -1526,25 +1517,20 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
  */
 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
 {
-        struct ar5416AniState *aniState;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
+        struct ar5416AniState *aniState = &chan->ani;
         struct ath9k_ani_default *iniDef;
-        int index;
         u32 val;
 
-        index = ath9k_hw_get_ani_channel_idx(ah, chan);
-        aniState = &ah->ani[index];
-        ah->curani = aniState;
         iniDef = &aniState->iniDef;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
-                  ah->hw_version.macVersion,
-                  ah->hw_version.macRev,
-                  ah->opmode,
-                  chan->channel,
-                  chan->channelFlags);
+        ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+                ah->hw_version.macVersion,
+                ah->hw_version.macRev,
+                ah->opmode,
+                chan->channel,
+                chan->channelFlags);
 
         val = REG_READ(ah, AR_PHY_SFCORR);
         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1579,8 +1565,6 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
         aniState->mrcCCKOff = true; /* not available on pre AR9003 */
-
-        aniState->cycleCount = 0;
 }
 
 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
@@ -1593,10 +1577,55 @@ static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
 }
 
+static void ar5008_hw_set_radar_params(struct ath_hw *ah,
+                                       struct ath_hw_radar_conf *conf)
+{
+        u32 radar_0 = 0, radar_1 = 0;
+
+        if (!conf) {
+                REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+                return;
+        }
+
+        radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+        radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+        radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+        radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+        radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+        radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+        radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+        radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+        radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+        radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+        radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+        REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+        REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+        if (conf->ext_channel)
+                REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+        else
+                REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
+{
+        struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+        conf->fir_power = -33;
+        conf->radar_rssi = 20;
+        conf->pulse_height = 10;
+        conf->pulse_rssi = 24;
+        conf->pulse_inband = 15;
+        conf->pulse_maxlen = 255;
+        conf->pulse_inband_step = 12;
+        conf->radar_inband = 8;
+}
+
 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        const u32 ar5416_cca_regs[6] = {
+        static const u32 ar5416_cca_regs[6] = {
                 AR_PHY_CCA,
                 AR_PHY_CH1_CCA,
                 AR_PHY_CH2_CCA,
@@ -1619,10 +1648,10 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
         priv_ops->rfbus_req = ar5008_hw_rfbus_req;
         priv_ops->rfbus_done = ar5008_hw_rfbus_done;
-        priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
         priv_ops->restore_chainmask = ar5008_restore_chainmask;
         priv_ops->set_diversity = ar5008_set_diversity;
         priv_ops->do_getnf = ar5008_hw_do_getnf;
+        priv_ops->set_radar_params = ar5008_hw_set_radar_params;
 
         if (modparam_force_new_ani) {
                 priv_ops->ani_control = ar5008_hw_ani_control_new;
@@ -1638,5 +1667,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
                 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
 
         ar5008_hw_set_nf_limits(ah);
+        ar5008_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
index 69a94c7e45cb..6d2e2f3303f9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index fe7418aefc4a..2d4c0910295b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,6 +20,34 @@
 
 #define AR9285_CLCAL_REDO_THRESH    1
 
+enum ar9002_cal_types {
+        ADC_GAIN_CAL = BIT(0),
+        ADC_DC_CAL = BIT(1),
+        IQ_MISMATCH_CAL = BIT(2),
+};
+
+static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                enum ar9002_cal_types cal_type)
+{
+        bool supported = false;
+        switch (ah->supp_cals & cal_type) {
+        case IQ_MISMATCH_CAL:
+                /* Run IQ Mismatch for non-CCK only */
+                if (!IS_CHAN_B(chan))
+                        supported = true;
+                break;
+        case ADC_GAIN_CAL:
+        case ADC_DC_CAL:
+                /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
+                if (!IS_CHAN_B(chan) &&
+                    !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
+                        supported = true;
+                break;
+        }
+        return supported;
+}
+
 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
                                         struct ath9k_cal_list *currCal)
 {
@@ -32,26 +60,19 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah,
         switch (currCal->calData->calType) {
         case IQ_MISMATCH_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting IQ Mismatch Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting IQ Mismatch Calibration\n");
                 break;
         case ADC_GAIN_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting ADC Gain Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting ADC Gain Calibration\n");
                 break;
         case ADC_DC_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting ADC DC Calibration\n");
-                break;
-        case ADC_DC_INIT_CAL:
-                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting Init ADC DC Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting ADC DC Calibration\n");
                 break;
-        case TEMP_COMP_CAL:
-                break; /* Not supported */
         }
 
         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
@@ -96,25 +117,6 @@ static bool ar9002_hw_per_calibration(struct ath_hw *ah,
         return iscaldone;
 }
 
-/* Assumes you are talking about the currently configured channel */
-static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
-                                      enum ath9k_cal_types calType)
-{
-        struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
-
-        switch (calType & ah->supp_cals) {
-        case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
-                return true;
-        case ADC_GAIN_CAL:
-        case ADC_DC_CAL:
-                if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
-                      conf_is_ht20(conf)))
-                        return true;
-                break;
-        }
-        return false;
-}
-
 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
 {
         int i;
@@ -126,11 +128,11 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
                 ah->totalIqCorrMeas[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
-                          ah->cal_samples, i, ah->totalPowerMeasI[i],
-                          ah->totalPowerMeasQ[i],
-                          ah->totalIqCorrMeas[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+                        ah->cal_samples, i, ah->totalPowerMeasI[i],
+                        ah->totalPowerMeasQ[i],
+                        ah->totalIqCorrMeas[i]);
         }
 }
 
@@ -148,14 +150,13 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
                 ah->totalAdcQEvenPhase[i] +=
                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
-                          "oddq=0x%08x; evenq=0x%08x;\n",
-                          ah->cal_samples, i,
-                          ah->totalAdcIOddPhase[i],
-                          ah->totalAdcIEvenPhase[i],
-                          ah->totalAdcQOddPhase[i],
-                          ah->totalAdcQEvenPhase[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+                        ah->cal_samples, i,
+                        ah->totalAdcIOddPhase[i],
+                        ah->totalAdcIEvenPhase[i],
+                        ah->totalAdcQOddPhase[i],
+                        ah->totalAdcQEvenPhase[i]);
         }
 }
 
@@ -173,14 +174,13 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
                 ah->totalAdcDcOffsetQEvenPhase[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
-                          "oddq=0x%08x; evenq=0x%08x;\n",
-                          ah->cal_samples, i,
-                          ah->totalAdcDcOffsetIOddPhase[i],
-                          ah->totalAdcDcOffsetIEvenPhase[i],
-                          ah->totalAdcDcOffsetQOddPhase[i],
-                          ah->totalAdcDcOffsetQEvenPhase[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+                        ah->cal_samples, i,
+                        ah->totalAdcDcOffsetIOddPhase[i],
+                        ah->totalAdcDcOffsetIEvenPhase[i],
+                        ah->totalAdcDcOffsetQOddPhase[i],
+                        ah->totalAdcDcOffsetQEvenPhase[i]);
         }
 }
 
@@ -197,13 +197,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 powerMeasQ = ah->totalPowerMeasQ[i];
                 iqCorrMeas = ah->totalIqCorrMeas[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting IQ Cal and Correction for Chain %d\n",
-                          i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting IQ Cal and Correction for Chain %d\n",
+                        i);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
-                          i, ah->totalIqCorrMeas[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
 
@@ -212,12 +212,12 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iqCorrNeg = 1;
                 }
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-                ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
-                          iqCorrNeg);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
+                ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+                        iqCorrNeg);
 
                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
                 qCoffDenom = powerMeasQ / 64;
@@ -226,14 +226,14 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                     (qCoffDenom != 0)) {
                         iCoff = iqCorrMeas / iCoffDenom;
                         qCoff = powerMeasI / qCoffDenom - 64;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                         iCoff = iCoff & 0x3f;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
                         if (iqCorrNeg == 0x0)
                                 iCoff = 0x40 - iCoff;
 
@@ -242,9 +242,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         else if (qCoff <= -16)
                                 qCoff = -16;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                  i, iCoff, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
+                                i, iCoff, qCoff);
 
                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -252,9 +252,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
                                       qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ Cal and Correction done for Chain %d\n",
-                                  i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "IQ Cal and Correction done for Chain %d\n",
+                                i);
                 }
         }
 
@@ -274,21 +274,21 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                 qOddMeasOffset = ah->totalAdcQOddPhase[i];
                 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting ADC Gain Cal for Chain %d\n", i);
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
-                          iOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
-                          iEvenMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
-                          qOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
-                          qEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting ADC Gain Cal for Chain %d\n", i);
+
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
+                        iOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_i = 0x%08x\n", i,
+                        iEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
+                        qOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_q = 0x%08x\n", i,
+                        qEvenMeasOffset);
 
                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
                         iGainMismatch =
@@ -298,20 +298,20 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                                 ((qOddMeasOffset * 32) /
                                  qEvenMeasOffset) & 0x3f;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
-                                  iGainMismatch);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
-                                  qGainMismatch);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d gain_mismatch_i = 0x%08x\n", i,
+                                iGainMismatch);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d gain_mismatch_q = 0x%08x\n", i,
+                                qGainMismatch);
 
                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
                         val &= 0xfffff000;
                         val |= (qGainMismatch) | (iGainMismatch << 6);
                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "ADC Gain Cal done for Chain %d\n", i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "ADC Gain Cal done for Chain %d\n", i);
                 }
         }
 
@@ -336,41 +336,41 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
                 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
                 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                           "Starting ADC DC Offset Cal for Chain %d\n", i);
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_i = %d\n", i,
-                          iOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_i = %d\n", i,
-                          iEvenMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_q = %d\n", i,
-                          qOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_q = %d\n", i,
-                          qEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting ADC DC Offset Cal for Chain %d\n", i);
+
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_i = %d\n", i,
+                        iOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_i = %d\n", i,
+                        iEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_q = %d\n", i,
+                        qOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_q = %d\n", i,
+                        qEvenMeasOffset);
 
                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
                                numSamples) & 0x1ff;
                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
                                numSamples) & 0x1ff;
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
-                          iDcMismatch);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
-                          qDcMismatch);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
+                        iDcMismatch);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
+                        qDcMismatch);
 
                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
                 val &= 0xc0000fff;
                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "ADC DC Offset Cal done for Chain %d\n", i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "ADC DC Offset Cal done for Chain %d\n", i);
         }
 
         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -541,7 +541,6 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
@@ -560,18 +559,13 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 { 0x7838, 0 },
         };
 
-        ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
 
         /* PA CAL is not needed for high power solution */
         if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
             AR5416_EEP_TXGAIN_HIGH_POWER)
                 return;
 
-        if (AR_SREV_9285_11(ah)) {
-                REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
-                udelay(10);
-        }
-
         for (i = 0; i < ARRAY_SIZE(regList); i++)
                 regList[i][1] = REG_READ(ah, regList[i][0]);
 
@@ -651,10 +645,6 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 
         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
-
-        if (AR_SREV_9285_11(ah))
-                REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
-
 }
 
 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
@@ -664,7 +654,7 @@ static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                         ar9271_hw_pa_cal(ah, is_reset);
                 else
                         ah->pacal_info.skipcount--;
-        } else if (AR_SREV_9285_11_OR_LATER(ah)) {
+        } else if (AR_SREV_9285_12_OR_LATER(ah)) {
                 if (is_reset || !ah->pacal_info.skipcount)
                         ar9285_hw_pa_cal(ah, is_reset);
                 else
@@ -710,10 +700,6 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,
 
         /* Do NF cal only at longer intervals */
         if (longcal || nfcal_pending) {
-                /* Do periodic PAOffset Cal */
-                ar9002_hw_pa_cal(ah, false);
-                ar9002_hw_olc_temp_compensation(ah);
-
                 /*
                  * Get the value from the previous NF cal and update
                  * history buffer.
@@ -728,8 +714,12 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,
                         ath9k_hw_loadnf(ah, ah->curchan);
                 }
 
-                if (longcal)
+                if (longcal) {
                         ath9k_hw_start_nfcal(ah, false);
+                        /* Do periodic PAOffset Cal */
+                        ar9002_hw_pa_cal(ah, false);
+                        ar9002_hw_olc_temp_compensation(ah);
+                }
         }
 
         return iscaldone;
@@ -750,9 +740,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                   AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
-                        ath_print(common, ATH_DBG_CALIBRATE, "offset "
-                                  "calibration failed to complete in "
-                                  "1ms; noisy ??\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "offset calibration failed to complete in 1ms; noisy environment?\n");
                         return false;
                 }
                 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -765,8 +754,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                           0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
-                          "failed to complete in 1ms; noisy ??\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "offset calibration failed to complete in 1ms; noisy environment?\n");
                 return false;
         }
 
@@ -837,12 +826,15 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
+        if (AR_SREV_9271(ah)) {
+                if (!ar9285_hw_cl_cal(ah, chan))
+                        return false;
+        } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
                 if (!ar9285_hw_clc(ah, chan))
                         return false;
         } else {
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
-                        if (!AR_SREV_9287_10_OR_LATER(ah))
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        if (!AR_SREV_9287_11_OR_LATER(ah))
                                 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
                                             AR_PHY_ADC_CTL_OFF_PWDADC);
                         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
@@ -858,14 +850,13 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                    AR_PHY_AGC_CONTROL_CAL,
                                    0, AH_WAIT_TIMEOUT)) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "offset calibration failed to "
-                                  "complete in 1ms; noisy environment?\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "offset calibration failed to complete in 1ms; noisy environment?\n");
                         return false;
                 }
 
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
-                        if (!AR_SREV_9287_10_OR_LATER(ah))
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        if (!AR_SREV_9287_11_OR_LATER(ah))
                                 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
                                             AR_PHY_ADC_CTL_OFF_PWDADC);
                         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
@@ -886,23 +877,33 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 
         /* Enable IQ, ADC Gain and ADC DC offset CALs */
         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
-                if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
+                ah->supp_cals = IQ_MISMATCH_CAL;
+
+                if (AR_SREV_9160_10_OR_LATER(ah))
+                        ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
+
+                if (AR_SREV_9287(ah))
+                        ah->supp_cals &= ~ADC_GAIN_CAL;
+
+                if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
                         INIT_CAL(&ah->adcgain_caldata);
                         INSERT_CAL(ah, &ah->adcgain_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling ADC Gain Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "enabling ADC Gain Calibration.\n");
                 }
-                if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
+
+                if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
                         INIT_CAL(&ah->adcdc_caldata);
                         INSERT_CAL(ah, &ah->adcdc_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling ADC DC Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "enabling ADC DC Calibration.\n");
                 }
-                if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
+
+                if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
                         INIT_CAL(&ah->iq_caldata);
                         INSERT_CAL(ah, &ah->iq_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling IQ Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "enabling IQ Calibration.\n");
                 }
 
                 ah->cal_list_curr = ah->cal_list;
@@ -959,13 +960,6 @@ static const struct ath9k_percal_data adc_dc_cal_single_sample = {
         ar9002_hw_adc_dccal_collect,
         ar9002_hw_adc_dccal_calibrate
 };
-static const struct ath9k_percal_data adc_init_dc_cal = {
-        ADC_DC_INIT_CAL,
-        MIN_CAL_SAMPLES,
-        INIT_LOG_COUNT,
-        ar9002_hw_adc_dccal_collect,
-        ar9002_hw_adc_dccal_calibrate
-};
 
 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
 {
@@ -976,24 +970,23 @@ static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
         }
 
         if (AR_SREV_9160_10_OR_LATER(ah)) {
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
                         ah->iq_caldata.calData = &iq_cal_single_sample;
                         ah->adcgain_caldata.calData =
                                 &adc_gain_cal_single_sample;
                         ah->adcdc_caldata.calData =
                                 &adc_dc_cal_single_sample;
-                        ah->adcdc_calinitdata.calData =
-                                &adc_init_dc_cal;
                 } else {
                         ah->iq_caldata.calData = &iq_cal_multi_sample;
                         ah->adcgain_caldata.calData =
                                 &adc_gain_cal_multi_sample;
                         ah->adcdc_caldata.calData =
                                 &adc_dc_cal_multi_sample;
-                        ah->adcdc_calinitdata.calData =
-                                &adc_init_dc_cal;
                 }
                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
+
+                if (AR_SREV_9287(ah))
+                        ah->supp_cals &= ~ADC_GAIN_CAL;
         }
 }
 
@@ -1005,7 +998,6 @@ void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
         priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
         priv_ops->init_cal = ar9002_hw_init_cal;
         priv_ops->setup_calibration = ar9002_hw_setup_calibration;
-        priv_ops->iscal_supported = ar9002_hw_iscal_supported;
 
         ops->calibrate = ar9002_hw_calibrate;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 303c63da5ea3..f344cc2b3d59 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -22,28 +22,10 @@
 
 int modparam_force_new_ani;
 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
-MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
+MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
 
 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
 
-static bool ar9002_hw_macversion_supported(u32 macversion)
-{
-        switch (macversion) {
-        case AR_SREV_VERSION_5416_PCI:
-        case AR_SREV_VERSION_5416_PCIE:
-        case AR_SREV_VERSION_9160:
-        case AR_SREV_VERSION_9100:
-        case AR_SREV_VERSION_9280:
-        case AR_SREV_VERSION_9285:
-        case AR_SREV_VERSION_9287:
-        case AR_SREV_VERSION_9271:
-                return true;
-        default:
-                break;
-        }
-        return false;
-}
-
 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 {
         if (AR_SREV_9271(ah)) {
@@ -371,7 +353,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
                         REGWRITE_BUFFER_FLUSH(ah);
-                        DISABLE_REGWRITE_BUFFER(ah);
                 }
 
                 udelay(1000);
@@ -411,6 +392,9 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
                 }
 
+                if (AR_SREV_9280(ah))
+                        val |= AR_WA_BIT22;
+
                 if (AR_SREV_9285E_20(ah))
                         val |= AR_WA_BIT23;
 
@@ -442,9 +426,8 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                 }
 
                 /* WAR for ASPM system hang */
-                if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
+                if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
-                }
 
                 if (AR_SREV_9285E_20(ah))
                         val |= AR_WA_BIT23;
@@ -468,7 +451,6 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah)
                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
@@ -493,9 +475,9 @@ int ar9002_hw_rf_claim(struct ath_hw *ah)
         case AR_RAD2122_SREV_MAJOR:
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Radio Chip Rev 0x%02X not supported\n",
-                          val & AR_RADIO_SREV_MAJOR);
+                ath_err(ath9k_hw_common(ah),
+                        "Radio Chip Rev 0x%02X not supported\n",
+                        val & AR_RADIO_SREV_MAJOR);
                 return -EOPNOTSUPP;
         }
 
@@ -564,19 +546,61 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
 
         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
-        priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 
         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 
         ar5008_hw_attach_phy_ops(ah);
-        if (AR_SREV_9280_10_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah))
                 ar9002_hw_attach_phy_ops(ah);
 
         ar9002_hw_attach_calib_ops(ah);
         ar9002_hw_attach_mac_ops(ah);
+}
 
-        if (modparam_force_new_ani)
-                ath9k_hw_attach_ani_ops_new(ah);
-        else
-                ath9k_hw_attach_ani_ops_old(ah);
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
+{
+        u32 modesIndex;
+        int i;
+
+        switch (chan->chanmode) {
+        case CHANNEL_A:
+        case CHANNEL_A_HT20:
+                modesIndex = 1;
+                break;
+        case CHANNEL_A_HT40PLUS:
+        case CHANNEL_A_HT40MINUS:
+                modesIndex = 2;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_G_HT20:
+        case CHANNEL_B:
+                modesIndex = 4;
+                break;
+        case CHANNEL_G_HT40PLUS:
+        case CHANNEL_G_HT40MINUS:
+                modesIndex = 3;
+                break;
+
+        default:
+                return;
+        }
+
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
+                u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
+                u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
+                u32 val_orig;
+
+                if (reg == AR_PHY_CCK_DETECT) {
+                        val_orig = REG_READ(ah, reg);
+                        val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
+                        val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
+
+                        REG_WRITE(ah, reg, val|val_orig);
+                } else
+                        REG_WRITE(ah, reg, val);
+        }
+
+        REGWRITE_BUFFER_FLUSH(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
index 6203eed860dd..7573257731b6 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index 50dda394f8be..077e8a6983fa 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -90,13 +90,10 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 
                 *masked = isr & ATH9K_INT_COMMON;
 
-                if (ah->config.rx_intr_mitigation) {
-                        if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
-                                *masked |= ATH9K_INT_RX;
-                }
-
-                if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+                if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
+                           AR_ISR_RXOK | AR_ISR_RXERR))
                         *masked |= ATH9K_INT_RX;
+
                 if (isr &
                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
                      AR_ISR_TXEOL)) {
@@ -114,16 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 }
 
                 if (isr & AR_ISR_RXORN) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "receive FIFO overrun interrupt\n");
-                }
-
-                if (!AR_SREV_9100(ah)) {
-                        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
-                                u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
-                                if (isr5 & AR_ISR_S5_TIM_TIMER)
-                                        *masked |= ATH9K_INT_TIM_TIMER;
-                        }
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "receive FIFO overrun interrupt\n");
                 }
 
                 *masked |= mask2;
@@ -136,17 +125,18 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 u32 s5_s;
 
                 s5_s = REG_READ(ah, AR_ISR_S5_S);
-                if (isr & AR_ISR_GENTMR) {
-                        ah->intr_gen_timer_trigger =
+                ah->intr_gen_timer_trigger =
                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
 
-                        ah->intr_gen_timer_thresh =
-                                MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
+                ah->intr_gen_timer_thresh =
+                        MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
 
-                        if (ah->intr_gen_timer_trigger)
-                                *masked |= ATH9K_INT_GENTIMER;
+                if (ah->intr_gen_timer_trigger)
+                        *masked |= ATH9K_INT_GENTIMER;
 
-                }
+                if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
+                    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+                        *masked |= ATH9K_INT_TIM_TIMER;
         }
 
         if (sync_cause) {
@@ -157,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 
                 if (fatal_int) {
                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
-                                ath_print(common, ATH_DBG_ANY,
-                                          "received PCI FATAL interrupt\n");
+                                ath_dbg(common, ATH_DBG_ANY,
+                                        "received PCI FATAL interrupt\n");
                         }
                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
-                                ath_print(common, ATH_DBG_ANY,
-                                          "received PCI PERR interrupt\n");
+                                ath_dbg(common, ATH_DBG_ANY,
+                                        "received PCI PERR interrupt\n");
                         }
                         *masked |= ATH9K_INT_FATAL;
                 }
                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
                         REG_WRITE(ah, AR_RC, 0);
                         *masked |= ATH9K_INT_FATAL;
                 }
                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
                 }
 
                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -218,77 +208,70 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                  struct ath_tx_status *ts)
 {
         struct ar5416_desc *ads = AR5416DESC(ds);
+        u32 status;
 
-        if ((ads->ds_txstatus9 & AR_TxDone) == 0)
+        status = ACCESS_ONCE(ads->ds_txstatus9);
+        if ((status & AR_TxDone) == 0)
                 return -EINPROGRESS;
 
-        ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
         ts->ts_tstamp = ads->AR_SendTimestamp;
         ts->ts_status = 0;
         ts->ts_flags = 0;
 
-        if (ads->ds_txstatus1 & AR_FrmXmitOK)
+        if (status & AR_TxOpExceeded)
+                ts->ts_status |= ATH9K_TXERR_XTXOP;
+        ts->tid = MS(status, AR_TxTid);
+        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
+        ts->ts_seqnum = MS(status, AR_SeqNum);
+
+        status = ACCESS_ONCE(ads->ds_txstatus0);
+        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
+        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
+        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
+        if (status & AR_TxBaStatus) {
+                ts->ts_flags |= ATH9K_TX_BA;
+                ts->ba_low = ads->AR_BaBitmapLow;
+                ts->ba_high = ads->AR_BaBitmapHigh;
+        }
+
+        status = ACCESS_ONCE(ads->ds_txstatus1);
+        if (status & AR_FrmXmitOK)
                 ts->ts_status |= ATH9K_TX_ACKED;
-        if (ads->ds_txstatus1 & AR_ExcessiveRetries)
-                ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->ds_txstatus1 & AR_Filtered)
-                ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
-                ts->ts_status |= ATH9K_TXERR_FIFO;
-                ath9k_hw_updatetxtriglevel(ah, true);
+        else {
+                if (status & AR_ExcessiveRetries)
+                        ts->ts_status |= ATH9K_TXERR_XRETRY;
+                if (status & AR_Filtered)
+                        ts->ts_status |= ATH9K_TXERR_FILT;
+                if (status & AR_FIFOUnderrun) {
+                        ts->ts_status |= ATH9K_TXERR_FIFO;
+                        ath9k_hw_updatetxtriglevel(ah, true);
+                }
         }
-        if (ads->ds_txstatus9 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->ds_txstatus1 & AR_TxTimerExpired)
+        if (status & AR_TxTimerExpired)
                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->ds_txstatus1 & AR_DescCfgErr)
+        if (status & AR_DescCfgErr)
                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
+        if (status & AR_TxDataUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
+        if (status & AR_TxDelimUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->ds_txstatus0 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->AR_BaBitmapLow;
-                ts->ba_high = ads->AR_BaBitmapHigh;
-        }
+        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
+        ts->ts_longretry = MS(status, AR_DataFailCnt);
+        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
-        ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
-        switch (ts->ts_rateindex) {
-        case 0:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
-                break;
-        case 1:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
-                break;
-        case 2:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
-                break;
-        case 3:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
-                break;
-        }
+        status = ACCESS_ONCE(ads->ds_txstatus5);
+        ts->ts_rssi = MS(status, AR_TxRSSICombined);
+        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
+        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
+        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
-        ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
         ts->evm0 = ads->AR_TxEVM0;
         ts->evm1 = ads->AR_TxEVM1;
         ts->evm2 = ads->AR_TxEVM2;
-        ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
-        ts->tid = MS(ads->ds_txstatus9, AR_TxTid);
-        ts->ts_antenna = 0;
 
         return 0;
 }
@@ -300,7 +283,6 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
 {
         struct ar5416_desc *ads = AR5416DESC(ds);
 
-        txPower += ah->txpower_indexoffset;
         if (txPower > 63)
                 txPower = 63;
 
@@ -308,7 +290,6 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
                 | SM(txPower, AR_XmitPower)
                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
-                | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
 
@@ -329,6 +310,16 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         }
 }
 
+static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
+{
+        struct ar5416_desc *ads = AR5416DESC(ds);
+
+        if (val)
+                ads->ds_ctl0 |= AR_ClrDestMask;
+        else
+                ads->ds_ctl0 &= ~AR_ClrDestMask;
+}
+
 static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
                                           void *lastds,
                                           u32 durUpdateEn, u32 rtsctsRate,
@@ -424,26 +415,6 @@ static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
 }
 
-static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
-                                           u32 burstDuration)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_ctl2 &= ~AR_BurstDur;
-        ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
-}
-
-static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
-                                            u32 vmf)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        if (vmf)
-                ads->ds_ctl0 |= AR_VirtMoreFrag;
-        else
-                ads->ds_ctl0 &= ~AR_VirtMoreFrag;
-}
-
 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
                           u32 size, u32 flags)
 {
@@ -476,6 +447,5 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
         ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
         ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
         ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
-        ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
-        ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
+        ops->set_clrdmask = ar9002_hw_set_clrdmask;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index adbf031fbc5a..2fe0a34cbabc 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -175,13 +175,15 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         int upper, lower, cur_vit_mask;
         int tmp, newVal;
         int i;
-        int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                          AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+        static const int pilot_mask_reg[4] = {
+                AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
         };
-        int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                         AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+        static const int chan_mask_reg[4] = {
+                AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
         };
-        int inc[4] = { 0, 100, 0, 0 };
+        static const int inc[4] = { 0, 100, 0, 0 };
         struct chan_centers centers;
 
         int8_t mask_m[123];
@@ -201,13 +203,14 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
 
+                if (AR_NO_SPUR == cur_bb_spur)
+                        break;
+
                 if (is2GHz)
                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
                 else
                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
 
-                if (AR_NO_SPUR == cur_bb_spur)
-                        break;
                 cur_bb_spur = cur_bb_spur - freq;
 
                 if (IS_CHAN_HT40(chan)) {
@@ -415,7 +418,6 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ar9002_olc_init(struct ath_hw *ah)
@@ -474,21 +476,21 @@ static void ar9002_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
         if (IS_CHAN_HT40(ah->curchan))
-                nfarray[3] = sign_extend(nf, 9);
+                nfarray[3] = sign_extend32(nf, 8);
 
         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
         if (IS_CHAN_HT40(ah->curchan))
-                nfarray[4] = sign_extend(nf, 9);
+                nfarray[4] = sign_extend32(nf, 8);
 }
 
 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
@@ -515,9 +517,45 @@ static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
         }
 }
 
+static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
+        antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
+                                  AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
+        antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
+                                 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
+        antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
+                                  AR_PHY_9285_FAST_DIV_BIAS_S;
+        antconf->lna1_lna2_delta = -3;
+        antconf->div_group = 0;
+}
+
+static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
+        regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
+                    AR_PHY_9285_ANT_DIV_ALT_LNACONF |
+                    AR_PHY_9285_FAST_DIV_BIAS);
+        regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
+                   & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
+        regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
+                   & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
+        regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
+                   & AR_PHY_9285_FAST_DIV_BIAS);
+
+        REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
+}
+
 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 
         priv_ops->set_rf_regs = NULL;
         priv_ops->rf_alloc_ext_banks = NULL;
@@ -528,5 +566,8 @@ void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
         priv_ops->do_getnf = ar9002_hw_do_getnf;
 
+        ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
+        ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
+
         ar9002_hw_set_nf_limits(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
index c5151a4dd10b..453af6dc514b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -302,6 +302,8 @@
 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
 
 #define AR_PHY_MULTICHAIN_GAIN_CTL          0x99ac
+#define AR_PHY_9285_FAST_DIV_BIAS           0x00007E00
+#define AR_PHY_9285_FAST_DIV_BIAS_S         9
 #define AR_PHY_9285_ANT_DIV_CTL_ALL         0x7f000000
 #define AR_PHY_9285_ANT_DIV_CTL             0x01000000
 #define AR_PHY_9285_ANT_DIV_CTL_S           24
@@ -481,7 +483,11 @@
 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN     0x01F80000
 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S   19
 
+#define AR_PHY_TX_PWRCTRL8       0xa278
+
 #define AR_PHY_TX_PWRCTRL9       0xa27C
+
+#define AR_PHY_TX_PWRCTRL10       0xa394
 #define AR_PHY_TX_DESIRED_SCALE_CCK        0x00007C00
 #define AR_PHY_TX_DESIRED_SCALE_CCK_S      10
 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL  0x80000000
@@ -493,6 +499,8 @@
 
 #define AR_PHY_CH0_TX_PWRCTRL11  0xa398
 #define AR_PHY_CH1_TX_PWRCTRL11  0xb398
+#define AR_PHY_CH0_TX_PWRCTRL12  0xa3dc
+#define AR_PHY_CH0_TX_PWRCTRL13  0xa3e0
 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP   0x0000FC00
 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index ec98ab50748a..e8ac70da5ac7 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -34,6 +34,10 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
 
 static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -52,21 +56,21 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
         {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
         {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
-        {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
-        {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
-        {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
-        {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
-        {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
-        {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
-        {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
-        {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
-        {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
+        {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
+        {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
+        {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
+        {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
+        {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
+        {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
+        {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
+        {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
         {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
         {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
         {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -84,21 +88,45 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
         {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
         {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
-        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
-        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
-        {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
-        {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
-        {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
-        {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
-        {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
-        {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
-        {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
+        {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
+        {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
+        {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
+        {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
+        {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
+        {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
+        {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
+        {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
+        {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
+        {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
+        {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
         {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
@@ -118,7 +146,7 @@ static const u32 ar9300Modes_fast_clock_2p2[][3] = {
         {0x00008014, 0x044c044c, 0x08980898},
         {0x0000801c, 0x148ec02b, 0x148ec057},
         {0x00008318, 0x000044c0, 0x00008980},
-        {0x00009e00, 0x03721821, 0x03721821},
+        {0x00009e00, 0x0372131c, 0x0372131c},
         {0x0000a230, 0x0000000b, 0x00000016},
         {0x0000a254, 0x00000898, 0x00001130},
 };
@@ -595,20 +623,22 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
-        {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
-        {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
+        {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
         {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
         {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
-        {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+        {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
         {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
         {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
         {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27},
         {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
         {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
         {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
         {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+        {0x0000a22c, 0x01026a2f, 0x01026a2f, 0x01026a2f, 0x01026a2f},
         {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
         {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
         {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
@@ -624,16 +654,16 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
         {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
-        {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+        {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
         {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
         {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000be04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
         {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
@@ -649,13 +679,13 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x00009814, 0x9280c00a},
         {0x00009818, 0x00000000},
         {0x0000981c, 0x00020028},
-        {0x00009834, 0x5f3ca3de},
+        {0x00009834, 0x6400a290},
         {0x00009838, 0x0108ecff},
-        {0x0000983c, 0x14750600},
+        {0x0000983c, 0x0d000600},
         {0x00009880, 0x201fff00},
         {0x00009884, 0x00001042},
         {0x000098a4, 0x00200400},
-        {0x000098b0, 0x52440bbe},
+        {0x000098b0, 0x32840bbe},
         {0x000098d0, 0x004b6a8e},
         {0x000098d4, 0x00000820},
         {0x000098dc, 0x00000000},
@@ -681,7 +711,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x00009e30, 0x06336f77},
         {0x00009e34, 0x6af6532f},
         {0x00009e38, 0x0cc80c00},
-        {0x00009e3c, 0xcf946222},
         {0x00009e40, 0x0d261820},
         {0x00009e4c, 0x00001004},
         {0x00009e50, 0x00ff03f1},
@@ -694,7 +723,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a220, 0x00000000},
         {0x0000a224, 0x00000000},
         {0x0000a228, 0x10002310},
-        {0x0000a22c, 0x01036a1e},
         {0x0000a23c, 0x00000000},
         {0x0000a244, 0x0c000000},
         {0x0000a2a0, 0x00000001},
@@ -702,10 +730,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a2c8, 0x00000000},
         {0x0000a2cc, 0x18c43433},
         {0x0000a2d4, 0x00000000},
-        {0x0000a2dc, 0x00000000},
-        {0x0000a2e0, 0x00000000},
-        {0x0000a2e4, 0x00000000},
-        {0x0000a2e8, 0x00000000},
         {0x0000a2ec, 0x00000000},
         {0x0000a2f0, 0x00000000},
         {0x0000a2f4, 0x00000000},
@@ -753,33 +777,17 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a430, 0x1ce739ce},
         {0x0000a434, 0x00000000},
         {0x0000a438, 0x00001801},
-        {0x0000a43c, 0x00000000},
+        {0x0000a43c, 0x00100000},
         {0x0000a440, 0x00000000},
         {0x0000a444, 0x00000000},
         {0x0000a448, 0x06000080},
         {0x0000a44c, 0x00000001},
         {0x0000a450, 0x00010000},
         {0x0000a458, 0x00000000},
-        {0x0000a600, 0x00000000},
-        {0x0000a604, 0x00000000},
-        {0x0000a608, 0x00000000},
-        {0x0000a60c, 0x00000000},
-        {0x0000a610, 0x00000000},
-        {0x0000a614, 0x00000000},
-        {0x0000a618, 0x00000000},
-        {0x0000a61c, 0x00000000},
-        {0x0000a620, 0x00000000},
-        {0x0000a624, 0x00000000},
-        {0x0000a628, 0x00000000},
-        {0x0000a62c, 0x00000000},
-        {0x0000a630, 0x00000000},
-        {0x0000a634, 0x00000000},
-        {0x0000a638, 0x00000000},
-        {0x0000a63c, 0x00000000},
         {0x0000a640, 0x00000000},
         {0x0000a644, 0x3fad9d74},
         {0x0000a648, 0x0048060a},
-        {0x0000a64c, 0x00000637},
+        {0x0000a64c, 0x00003c37},
         {0x0000a670, 0x03020100},
         {0x0000a674, 0x09080504},
         {0x0000a678, 0x0d0c0b0a},
@@ -802,10 +810,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a8f4, 0x00000000},
         {0x0000b2d0, 0x00000080},
         {0x0000b2d4, 0x00000000},
-        {0x0000b2dc, 0x00000000},
-        {0x0000b2e0, 0x00000000},
-        {0x0000b2e4, 0x00000000},
-        {0x0000b2e8, 0x00000000},
         {0x0000b2ec, 0x00000000},
         {0x0000b2f0, 0x00000000},
         {0x0000b2f4, 0x00000000},
@@ -820,10 +824,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000b8f4, 0x00000000},
         {0x0000c2d0, 0x00000080},
         {0x0000c2d4, 0x00000000},
-        {0x0000c2dc, 0x00000000},
-        {0x0000c2e0, 0x00000000},
-        {0x0000c2e4, 0x00000000},
-        {0x0000c2e8, 0x00000000},
         {0x0000c2ec, 0x00000000},
         {0x0000c2f0, 0x00000000},
         {0x0000c2f4, 0x00000000},
@@ -835,6 +835,10 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
 
 static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -855,7 +859,7 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
         {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
         {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
         {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
-        {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+        {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
         {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
         {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
         {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
@@ -900,6 +904,30 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+        {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+        {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
         {0x00016048, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
         {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
@@ -913,6 +941,10 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
 
 static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -933,7 +965,7 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
         {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
         {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
-        {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+        {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
         {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
         {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
         {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
@@ -978,6 +1010,30 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+        {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+        {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
         {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
@@ -1151,14 +1207,14 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
         {0x0000b074, 0x00000000},
         {0x0000b078, 0x00000000},
         {0x0000b07c, 0x00000000},
-        {0x0000b080, 0x32323232},
-        {0x0000b084, 0x2f2f3232},
-        {0x0000b088, 0x23282a2d},
-        {0x0000b08c, 0x1c1e2123},
-        {0x0000b090, 0x14171919},
-        {0x0000b094, 0x0e0e1214},
-        {0x0000b098, 0x03050707},
-        {0x0000b09c, 0x00030303},
+        {0x0000b080, 0x2a2d2f32},
+        {0x0000b084, 0x21232328},
+        {0x0000b088, 0x19191c1e},
+        {0x0000b08c, 0x12141417},
+        {0x0000b090, 0x07070e0e},
+        {0x0000b094, 0x03030305},
+        {0x0000b098, 0x00000003},
+        {0x0000b09c, 0x00000000},
         {0x0000b0a0, 0x00000000},
         {0x0000b0a4, 0x00000000},
         {0x0000b0a8, 0x00000000},
@@ -1251,6 +1307,10 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
 
 static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -1269,21 +1329,21 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
         {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
         {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
-        {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
-        {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
-        {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
-        {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
-        {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
-        {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
-        {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
-        {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
-        {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
+        {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
+        {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
+        {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
+        {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
+        {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
+        {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
+        {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
+        {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
         {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
         {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
         {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -1301,21 +1361,45 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
         {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
         {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
-        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
-        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
-        {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
-        {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
-        {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
-        {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
-        {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
-        {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
-        {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
+        {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
+        {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
+        {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
+        {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
+        {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
+        {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
+        {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
+        {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
+        {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
+        {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
+        {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+        {0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
+        {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
+        {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
+        {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
         {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
@@ -1414,15 +1498,10 @@ static const u32 ar9300_2p2_mac_core[][2] = {
         {0x00008144, 0xffffffff},
         {0x00008168, 0x00000000},
         {0x0000816c, 0x00000000},
-        {0x00008170, 0x18486200},
-        {0x00008174, 0x33332210},
-        {0x00008178, 0x00000000},
-        {0x0000817c, 0x00020000},
         {0x000081c0, 0x00000000},
         {0x000081c4, 0x33332210},
         {0x000081c8, 0x00000000},
         {0x000081cc, 0x00000000},
-        {0x000081d4, 0x00000000},
         {0x000081ec, 0x00000000},
         {0x000081f0, 0x00000000},
         {0x000081f4, 0x00000000},
@@ -1763,7 +1842,7 @@ static const u32 ar9300_2p2_soc_preamble[][2] = {
 
 static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
         /* Addr      allmodes  */
-        {0x00004040, 0x08212e5e},
+        {0x00004040, 0x0821265e},
         {0x00004040, 0x0008003b},
         {0x00004044, 0x00000000},
 };
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 4674ea8c9c99..f48051c50092 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,21 @@
 #include "hw-ops.h"
 #include "ar9003_phy.h"
 
+#define MAX_MEASUREMENT 8
+#define MAX_MAG_DELTA   11
+#define MAX_PHS_DELTA   10
+
+struct coeff {
+        int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
+        int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
+        int iqc_coeff[2];
+};
+
+enum ar9003_cal_types {
+        IQ_MISMATCH_CAL = BIT(0),
+        TEMP_COMP_CAL = BIT(1),
+};
+
 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                                         struct ath9k_cal_list *currCal)
 {
@@ -35,8 +50,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                 currCal->calData->calCountMax);
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting IQ Mismatch Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting IQ Mismatch Calibration\n");
 
                 /* Kick-off cal */
                 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
@@ -47,13 +62,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
                               AR_PHY_65NM_CH0_THERM_START, 1);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting Temperature Compensation Calibration\n");
-                break;
-        case ADC_DC_INIT_CAL:
-        case ADC_GAIN_CAL:
-        case ADC_DC_CAL:
-                /* Not yet */
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting Temperature Compensation Calibration\n");
                 break;
         }
 }
@@ -175,17 +185,19 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
 
         /* Accumulate IQ cal measures for active chains */
         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
-                ah->totalPowerMeasI[i] +=
-                        REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
-                ah->totalPowerMeasQ[i] +=
-                        REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
-                ah->totalIqCorrMeas[i] +=
-                        (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
-                          ah->cal_samples, i, ah->totalPowerMeasI[i],
-                          ah->totalPowerMeasQ[i],
-                          ah->totalIqCorrMeas[i]);
+                if (ah->txchainmask & BIT(i)) {
+                        ah->totalPowerMeasI[i] +=
+                                REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
+                        ah->totalPowerMeasQ[i] +=
+                                REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
+                        ah->totalIqCorrMeas[i] +=
+                                (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                                "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+                                ah->cal_samples, i, ah->totalPowerMeasI[i],
+                                ah->totalPowerMeasQ[i],
+                                ah->totalIqCorrMeas[i]);
+                }
         }
 }
 
@@ -196,7 +208,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
         u32 qCoffDenom, iCoffDenom;
         int32_t qCoff, iCoff;
         int iqCorrNeg, i;
-        const u_int32_t offset_array[3] = {
+        static const u_int32_t offset_array[3] = {
                 AR_PHY_RX_IQCAL_CORR_B0,
                 AR_PHY_RX_IQCAL_CORR_B1,
                 AR_PHY_RX_IQCAL_CORR_B2,
@@ -207,13 +219,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 powerMeasQ = ah->totalPowerMeasQ[i];
                 iqCorrMeas = ah->totalIqCorrMeas[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting IQ Cal and Correction for Chain %d\n",
-                          i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting IQ Cal and Correction for Chain %d\n",
+                        i);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
-                          i, ah->totalIqCorrMeas[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
 
@@ -222,12 +234,12 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iqCorrNeg = 1;
                 }
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-                ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
-                          iqCorrNeg);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
+                ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+                        iqCorrNeg);
 
                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
                 qCoffDenom = powerMeasQ / 64;
@@ -235,10 +247,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
                         iCoff = iqCorrMeas / iCoffDenom;
                         qCoff = powerMeasI / qCoffDenom - 64;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                         /* Force bounds on iCoff */
                         if (iCoff >= 63)
@@ -259,14 +271,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iCoff = iCoff & 0x7f;
                         qCoff = qCoff & 0x7f;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                  i, iCoff, qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) "
-                                  "before update = 0x%x\n",
-                                  offset_array[i],
-                                  REG_READ(ah, offset_array[i]));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
+                                i, iCoff, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) before update = 0x%x\n",
+                                offset_array[i],
+                                REG_READ(ah, offset_array[i]));
 
                         REG_RMW_FIELD(ah, offset_array[i],
                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
@@ -274,33 +285,29 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         REG_RMW_FIELD(ah, offset_array[i],
                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
                                       qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) QI COFF "
-                                  "(bitfields 0x%08x) after update = 0x%x\n",
-                                  offset_array[i],
-                                  AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
-                                  REG_READ(ah, offset_array[i]));
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) QQ COFF "
-                                  "(bitfields 0x%08x) after update = 0x%x\n",
-                                  offset_array[i],
-                                  AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
-                                  REG_READ(ah, offset_array[i]));
-
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ Cal and Correction done for Chain %d\n",
-                                  i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
+                                offset_array[i],
+                                AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
+                                REG_READ(ah, offset_array[i]));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
+                                offset_array[i],
+                                AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
+                                REG_READ(ah, offset_array[i]));
+
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "IQ Cal and Correction done for Chain %d\n", i);
                 }
         }
 
         REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
                     AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "IQ Cal and Correction (offset 0x%04x) enabled "
-                  "(bit position 0x%08x). New Value 0x%08x\n",
-                  (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
-                  AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
-                  REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
+                (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
+                AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
+                REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
 }
 
 static const struct ath9k_percal_data iq_cal_single_sample = {
@@ -314,27 +321,6 @@ static const struct ath9k_percal_data iq_cal_single_sample = {
 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
 {
         ah->iq_caldata.calData = &iq_cal_single_sample;
-        ah->supp_cals = IQ_MISMATCH_CAL;
-}
-
-static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
-                                      enum ath9k_cal_types calType)
-{
-        switch (calType & ah->supp_cals) {
-        case IQ_MISMATCH_CAL:
-                /*
-                 * XXX: Run IQ Mismatch for non-CCK only
-                 * Note that CHANNEL_B is never set though.
-                 */
-                return true;
-        case ADC_GAIN_CAL:
-        case ADC_DC_CAL:
-                return false;
-        case TEMP_COMP_CAL:
-                return true;
-        }
-
-        return false;
 }
 
 /*
@@ -361,7 +347,7 @@ static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
         f2 = (f1 * f1 + f3 * f3) / result_shift;
 
         if (!f2) {
-                ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
                 return false;
         }
 
@@ -482,11 +468,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
             (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0:\na0_d0=%d\n"
-                          "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
-                          i2_p_q2_a0_d0, i2_p_q2_a0_d1,
-                          i2_p_q2_a1_d0, i2_p_q2_a1_d1);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0:\n"
+                        "a0_d0=%d\n"
+                        "a0_d1=%d\n"
+                        "a2_d0=%d\n"
+                        "a1_d1=%d\n",
+                        i2_p_q2_a0_d0, i2_p_q2_a0_d1,
+                        i2_p_q2_a1_d0, i2_p_q2_a1_d1);
                 return false;
         }
 
@@ -519,9 +508,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
 
         if ((mag1 == 0) || (mag2 == 0)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag1=%d, mag2=%d\n",
-                          mag1, mag2);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag1=%d, mag2=%d\n",
+                        mag1, mag2);
                 return false;
         }
 
@@ -538,8 +527,8 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
                              mag_a0_d0, phs_a0_d0,
                              mag_a1_d0,
                              phs_a1_d0, solved_eq)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Call to ar9003_hw_solve_iq_cal() failed.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Call to ar9003_hw_solve_iq_cal() failed.\n");
                 return false;
         }
 
@@ -548,14 +537,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         mag_rx = solved_eq[2];
         phs_rx = solved_eq[3];
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "chain %d: mag mismatch=%d phase mismatch=%d\n",
-                  chain_idx, mag_tx/res_scale, phs_tx/res_scale);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "chain %d: mag mismatch=%d phase mismatch=%d\n",
+                chain_idx, mag_tx/res_scale, phs_tx/res_scale);
 
         if (res_scale == mag_tx) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag_tx=%d, res_scale=%d\n",
-                          mag_tx, res_scale);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag_tx=%d, res_scale=%d\n",
+                        mag_tx, res_scale);
                 return false;
         }
 
@@ -566,9 +555,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         q_q_coff = (mag_corr_tx * 128 / res_scale);
         q_i_coff = (phs_corr_tx * 256 / res_scale);
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "tx chain %d: mag corr=%d  phase corr=%d\n",
-                  chain_idx, q_q_coff, q_i_coff);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "tx chain %d: mag corr=%d  phase corr=%d\n",
+                chain_idx, q_q_coff, q_i_coff);
 
         if (q_i_coff < -63)
                 q_i_coff = -63;
@@ -581,14 +570,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "tx chain %d: iq corr coeff=%x\n",
-                  chain_idx, iqc_coeff[0]);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "tx chain %d: iq corr coeff=%x\n",
+                chain_idx, iqc_coeff[0]);
 
         if (-mag_rx == res_scale) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag_rx=%d, res_scale=%d\n",
-                          mag_rx, res_scale);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag_rx=%d, res_scale=%d\n",
+                        mag_rx, res_scale);
                 return false;
         }
 
@@ -599,9 +588,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         q_q_coff = (mag_corr_rx * 128 / res_scale);
         q_i_coff = (phs_corr_rx * 256 / res_scale);
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "rx chain %d: mag corr=%d  phase corr=%d\n",
-                  chain_idx, q_q_coff, q_i_coff);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "rx chain %d: mag corr=%d  phase corr=%d\n",
+                chain_idx, q_q_coff, q_i_coff);
 
         if (q_i_coff < -63)
                 q_i_coff = -63;
@@ -614,14 +603,142 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "rx chain %d: iq corr coeff=%x\n",
-                  chain_idx, iqc_coeff[1]);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "rx chain %d: iq corr coeff=%x\n",
+                chain_idx, iqc_coeff[1]);
 
         return true;
 }
 
-static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
+static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
+                                     int max_delta)
+{
+        int mp_max = -64, max_idx = 0;
+        int mp_min = 63, min_idx = 0;
+        int mp_avg = 0, i, outlier_idx = 0;
+
+        /* find min/max mismatch across all calibrated gains */
+        for (i = 0; i < nmeasurement; i++) {
+                mp_avg += mp_coeff[i];
+                if (mp_coeff[i] > mp_max) {
+                        mp_max = mp_coeff[i];
+                        max_idx = i;
+                } else if (mp_coeff[i] < mp_min) {
+                        mp_min = mp_coeff[i];
+                        min_idx = i;
+                }
+        }
+
+        /* find average (exclude max abs value) */
+        for (i = 0; i < nmeasurement; i++) {
+                if ((abs(mp_coeff[i]) < abs(mp_max)) ||
+                    (abs(mp_coeff[i]) < abs(mp_min)))
+                        mp_avg += mp_coeff[i];
+        }
+        mp_avg /= (nmeasurement - 1);
+
+        /* detect outlier */
+        if (abs(mp_max - mp_min) > max_delta) {
+                if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
+                        outlier_idx = max_idx;
+                else
+                        outlier_idx = min_idx;
+        }
+        mp_coeff[outlier_idx] = mp_avg;
+}
+
+static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
+                                                 u8 num_chains,
+                                                 struct coeff *coeff)
+{
+        int i, im, nmeasurement;
+        u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
+
+        memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
+        for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
+                tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
+                if (!AR_SREV_9485(ah)) {
+                        tx_corr_coeff[i * 2][1] =
+                        tx_corr_coeff[(i * 2) + 1][1] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
+
+                        tx_corr_coeff[i * 2][2] =
+                        tx_corr_coeff[(i * 2) + 1][2] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
+                }
+        }
+
+        /* Load the average of 2 passes */
+        for (i = 0; i < num_chains; i++) {
+                nmeasurement = REG_READ_FIELD(ah,
+                                AR_PHY_TX_IQCAL_STATUS_B0,
+                                AR_PHY_CALIBRATED_GAINS_0);
+
+                if (nmeasurement > MAX_MEASUREMENT)
+                        nmeasurement = MAX_MEASUREMENT;
+
+                /* detect outlier only if nmeasurement > 1 */
+                if (nmeasurement > 1) {
+                        /* Detect magnitude outlier */
+                        ar9003_hw_detect_outlier(coeff->mag_coeff[i],
+                                        nmeasurement, MAX_MAG_DELTA);
+
+                        /* Detect phase outlier */
+                        ar9003_hw_detect_outlier(coeff->phs_coeff[i],
+                                        nmeasurement, MAX_PHS_DELTA);
+                }
+
+                for (im = 0; im < nmeasurement; im++) {
+
+                        coeff->iqc_coeff[0] = (coeff->mag_coeff[i][im] & 0x7f) |
+                                ((coeff->phs_coeff[i][im] & 0x7f) << 7);
+
+                        if ((im % 2) == 0)
+                                REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
+                                        coeff->iqc_coeff[0]);
+                        else
+                                REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
+                                        coeff->iqc_coeff[0]);
+                }
+        }
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
+                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
+        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
+                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
+
+        return;
+
+}
+
+static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u8 tx_gain_forced;
+
+        tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
+                                        AR_PHY_TXGAIN_FORCE);
+        if (tx_gain_forced)
+                REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
+                              AR_PHY_TXGAIN_FORCE, 0);
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
+                      AR_PHY_TX_IQCAL_START_DO_CAL, 1);
+
+        if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
+                        AR_PHY_TX_IQCAL_START_DO_CAL, 0,
+                        AH_WAIT_TIMEOUT)) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Tx IQ Cal is not completed.\n");
+                return false;
+        }
+        return true;
+}
+
+static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
         const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
@@ -629,128 +746,130 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
                 AR_PHY_TX_IQCAL_STATUS_B1,
                 AR_PHY_TX_IQCAL_STATUS_B2,
         };
-        const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
-        };
-        const u32 rx_corr[AR9300_MAX_CHAINS] = {
-                AR_PHY_RX_IQCAL_CORR_B0,
-                AR_PHY_RX_IQCAL_CORR_B1,
-                AR_PHY_RX_IQCAL_CORR_B2,
-        };
         const u_int32_t chan_info_tab[] = {
                 AR_PHY_CHAN_INFO_TAB_0,
                 AR_PHY_CHAN_INFO_TAB_1,
                 AR_PHY_CHAN_INFO_TAB_2,
         };
+        struct coeff coeff;
         s32 iq_res[6];
-        s32 iqc_coeff[2];
-        s32 i, j;
-        u32 num_chains = 0;
+        u8 num_chains = 0;
+        int i, im, j;
+        int nmeasurement;
 
         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
                 if (ah->txchainmask & (1 << i))
                         num_chains++;
         }
 
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
-                      AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
-                      DELPT);
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
-                      AR_PHY_TX_IQCAL_START_DO_CAL,
-                      AR_PHY_TX_IQCAL_START_DO_CAL);
-
-        if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
-                           AR_PHY_TX_IQCAL_START_DO_CAL,
-                           0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Tx IQ Cal not complete.\n");
-                goto TX_IQ_CAL_FAILED;
-        }
-
         for (i = 0; i < num_chains; i++) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Doing Tx IQ Cal for chain %d.\n", i);
-
-                if (REG_READ(ah, txiqcal_status[i]) &
-                             AR_PHY_TX_IQCAL_STATUS_FAILED) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Tx IQ Cal failed for chain %d.\n", i);
-                        goto TX_IQ_CAL_FAILED;
-                }
-
-                for (j = 0; j < 3; j++) {
-                        u_int8_t idx = 2 * j,
-                        offset = 4 * j;
-
-                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
-                                      AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
-
-                        /* 32 bits */
-                        iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
+                nmeasurement = REG_READ_FIELD(ah,
+                                AR_PHY_TX_IQCAL_STATUS_B0,
+                                AR_PHY_CALIBRATED_GAINS_0);
+                if (nmeasurement > MAX_MEASUREMENT)
+                        nmeasurement = MAX_MEASUREMENT;
+
+                for (im = 0; im < nmeasurement; im++) {
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Doing Tx IQ Cal for chain %d.\n", i);
+
+                        if (REG_READ(ah, txiqcal_status[i]) &
+                                        AR_PHY_TX_IQCAL_STATUS_FAILED) {
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "Tx IQ Cal failed for chain %d.\n", i);
+                                goto tx_iqcal_fail;
+                        }
 
-                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
-                                      AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
+                        for (j = 0; j < 3; j++) {
+                                u32 idx = 2 * j, offset = 4 * (3 * im + j);
+
+                                REG_RMW_FIELD(ah,
+                                                AR_PHY_CHAN_INFO_MEMORY,
+                                                AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                0);
+
+                                /* 32 bits */
+                                iq_res[idx] = REG_READ(ah,
+                                                chan_info_tab[i] +
+                                                offset);
+
+                                REG_RMW_FIELD(ah,
+                                                AR_PHY_CHAN_INFO_MEMORY,
+                                                AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                1);
+
+                                /* 16 bits */
+                                iq_res[idx + 1] = 0xffff & REG_READ(ah,
+                                                chan_info_tab[i] + offset);
+
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "IQ RES[%d]=0x%x"
+                                        "IQ_RES[%d]=0x%x\n",
+                                        idx, iq_res[idx], idx + 1,
+                                        iq_res[idx + 1]);
+                        }
 
-                        /* 16 bits */
-                        iq_res[idx+1] = 0xffff & REG_READ(ah,
-                                                          chan_info_tab[i] +
-                                                          offset);
+                        if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
+                                                coeff.iqc_coeff)) {
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "Failed in calculation of \
+                                        IQ correction.\n");
+                                goto tx_iqcal_fail;
+                        }
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
-                                  idx, iq_res[idx], idx+1, iq_res[idx+1]);
-                }
+                        coeff.mag_coeff[i][im] = coeff.iqc_coeff[0] & 0x7f;
+                        coeff.phs_coeff[i][im] =
+                                (coeff.iqc_coeff[0] >> 7) & 0x7f;
 
-                if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Failed in calculation of IQ correction.\n");
-                        goto TX_IQ_CAL_FAILED;
+                        if (coeff.mag_coeff[i][im] > 63)
+                                coeff.mag_coeff[i][im] -= 128;
+                        if (coeff.phs_coeff[i][im] > 63)
+                                coeff.phs_coeff[i][im] -= 128;
                 }
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
-                          iqc_coeff[0], iqc_coeff[1]);
-
-                REG_RMW_FIELD(ah, tx_corr_coeff[i],
-                              AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
-                              iqc_coeff[0]);
-                REG_RMW_FIELD(ah, rx_corr[i],
-                              AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
-                              iqc_coeff[1] >> 7);
-                REG_RMW_FIELD(ah, rx_corr[i],
-                              AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
-                              iqc_coeff[1]);
         }
-
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
-                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
-        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
-                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
+        ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
 
         return;
 
-TX_IQ_CAL_FAILED:
-        ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+tx_iqcal_fail:
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+        return;
 }
-
 static bool ar9003_hw_init_cal(struct ath_hw *ah,
                                struct ath9k_channel *chan)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_capabilities *pCap = &ah->caps;
+        int val;
+        bool txiqcal_done = false;
 
-        /*
-         * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
-         * running AGC/TxIQ cals
-         */
-        ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
+        val = REG_READ(ah, AR_ENT_OTP);
+        ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
+
+        /* Configure rx/tx chains before running AGC/TxiQ cals */
+        if (val & AR_ENT_OTP_CHAIN2_DISABLE)
+                ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
+        else
+                ar9003_hw_set_chain_masks(ah, pCap->rx_chainmask,
+                                          pCap->tx_chainmask);
 
         /* Do Tx IQ Calibration */
-        ar9003_hw_tx_iq_cal(ah);
-        REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-        udelay(5);
-        REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
+                      AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
+                      DELPT);
+
+        /*
+         * For AR9485 or later chips, TxIQ cal runs as part of
+         * AGC calibration
+         */
+        if (AR_SREV_9485_OR_LATER(ah))
+                txiqcal_done = true;
+        else {
+                txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
+                REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+                udelay(5);
+                REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+        }
 
         /* Calibrate the AGC */
         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -760,12 +879,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
         /* Poll for offset calibration complete */
         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                            0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "offset calibration failed to "
-                          "complete in 1ms; noisy environment?\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "offset calibration failed to complete in 1ms; noisy environment?\n");
                 return false;
         }
 
+        if (txiqcal_done)
+                ar9003_hw_tx_iq_cal_post_proc(ah);
+
         /* Revert chainmasks to their original values before NF cal */
         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 
@@ -773,19 +894,20 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
 
         /* Initialize list pointers */
         ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
+        ah->supp_cals = IQ_MISMATCH_CAL;
 
-        if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
+        if (ah->supp_cals & IQ_MISMATCH_CAL) {
                 INIT_CAL(&ah->iq_caldata);
                 INSERT_CAL(ah, &ah->iq_caldata);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling IQ Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling IQ Calibration.\n");
         }
 
-        if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
+        if (ah->supp_cals & TEMP_COMP_CAL) {
                 INIT_CAL(&ah->tempCompCalData);
                 INSERT_CAL(ah, &ah->tempCompCalData);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling Temperature Compensation Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling Temperature Compensation Calibration.\n");
         }
 
         /* Initialize current pointer to first element in list */
@@ -808,7 +930,6 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
         priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
         priv_ops->init_cal = ar9003_hw_init_cal;
         priv_ops->setup_calibration = ar9003_hw_setup_calibration;
-        priv_ops->iscal_supported = ar9003_hw_iscal_supported;
 
         ops->calibrate = ar9003_hw_calibrate;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 057fb69ddf7f..ff8150e46f0e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -22,12 +22,14 @@
 #define COMP_CKSUM_LEN 2
 
 #define AR_CH0_TOP (0x00016288)
-#define AR_CH0_TOP_XPABIASLVL (0x3)
+#define AR_CH0_TOP_XPABIASLVL (0x300)
 #define AR_CH0_TOP_XPABIASLVL_S (8)
 
 #define AR_CH0_THERM (0x00016290)
-#define AR_CH0_THERM_SPARE (0x3f)
-#define AR_CH0_THERM_SPARE_S (0)
+#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
+#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
+#define AR_CH0_THERM_XPASHORT2GND 0x4
+#define AR_CH0_THERM_XPASHORT2GND_S 2
 
 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
 #define AR_SWITCH_TABLE_COM_ALL_S (0)
@@ -55,6 +57,14 @@
 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
 
+#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
+
+#define EEPROM_DATA_LEN_9485    1088
+
+static int ar9003_hw_power_interpolate(int32_t x,
+                                       int32_t *px, int32_t *py, u_int16_t np);
+
+
 static const struct ar9300_eeprom ar9300_default = {
         .eepromVersion = 2,
         .templateVersion = 2,
@@ -65,7 +75,7 @@ static const struct ar9300_eeprom ar9300_default = {
                 .regDmn = { LE16(0), LE16(0x1f) },
                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
                 .opCapFlags = {
-                        .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
                         .eepMisc = 0,
                 },
                 .rfSilent = 0,
@@ -144,13 +154,16 @@ static const struct ar9300_eeprom ar9300_default = {
                 .txEndToRxOn = 0x2,
                 .txFrameToXpaOn = 0xe,
                 .thresh62 = 28,
-                .papdRateMaskHt20 = LE32(0x80c080),
-                .papdRateMaskHt40 = LE32(0x80c080),
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
                 .futureModal = {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                 },
          },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
         .calFreqPier2G = {
                 FREQ2FBIN(2412, 1),
                 FREQ2FBIN(2437, 1),
@@ -285,25 +298,25 @@ static const struct ar9300_eeprom ar9300_default = {
                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
-                        /* Data[11].ctlEdges[3].bChannel */
-                        FREQ2FBIN(2462, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
                 }
          },
         .ctlPowerData_2G = {
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 
-                 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
-                 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
-                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
          },
         .modalHeader5G = {
                 /* 4 idle,t1,t2,b (4 bits per setting) */
@@ -343,13 +356,20 @@ static const struct ar9300_eeprom ar9300_default = {
                 .txEndToRxOn = 0x2,
                 .txFrameToXpaOn = 0xe,
                 .thresh62 = 28,
-                .papdRateMaskHt20 = LE32(0xf0e0e0),
-                .papdRateMaskHt40 = LE32(0xf0e0e0),
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
                 .futureModal = {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                 },
          },
+        .base_ext2 = {
+                .tempSlopeLow = 0,
+                .tempSlopeHigh = 0,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+        },
         .calFreqPier5G = {
                 FREQ2FBIN(5180, 0),
                 FREQ2FBIN(5220, 0),
@@ -568,64 +588,2396 @@ static const struct ar9300_eeprom ar9300_default = {
         .ctlPowerData_5G = {
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+         }
+};
+
+static const struct ar9300_eeprom ar9300_x113 = {
+        .eepromVersion = 2,
+        .templateVersion = 6,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"x113-023-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                 /*
+                  * bit0 - enable tx temp comp - disabled
+                  * bit1 - enable tx volt comp - disabled
+                  * bit2 - enable fastClock - enabled
+                  * bit3 - enable doubling - enabled
+                  * bit4 - enable internal regulator - disabled
+                  * bit5 - enable pa predistortion - disabled
+                  */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x21,
+                .swreg = 0,
+         },
+        .modalHeader2G = {
+        /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+         .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+         },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+         },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTargetPowerCck = {
+                 /* 1L-5L,5S,11L,11S */
+                 { {34, 34, 34, 34} },
+                 { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                 /* 6-24,36,48,54 */
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+         },
+        .ctlPowerData_2G = {
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+         },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x11111),
+                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 68,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0xf,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+        .base_ext2 = {
+                .tempSlopeLow = 72,
+                .tempSlopeHigh = 105,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+         },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5190, 0),
+                FREQ2FBIN(5230, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5410, 0),
+                FREQ2FBIN(5510, 0),
+                FREQ2FBIN(5670, 0),
+                FREQ2FBIN(5755, 0),
+                FREQ2FBIN(5825, 0)
+         },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+         },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
+                { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
+         },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
+                { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
+         },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+         },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
                         }
                 },
                 {
                         {
-                                {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                                {60, 1}, {60, 0}, {60, 0}, {60, 0},
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                                {60, 0}, {60, 0}, {60, 0}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 0}, {60, 0}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 1},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                         }
                 },
                 {
                         {
-                                {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                                {60, 1}, {60, 1}, {60, 0}, {60, 1},
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
                         }
                 },
          }
 };
 
+
+static const struct ar9300_eeprom ar9300_h112 = {
+        .eepromVersion = 2,
+        .templateVersion = 3,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"h112-241-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                /*
+                 * bit0 - enable tx temp comp - disabled
+                 * bit1 - enable tx volt comp - disabled
+                 * bit2 - enable fastClock - enabled
+                 * bit3 - enable doubling - enabled
+                 * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
+                 */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x10,
+                .swreg = 0,
+        },
+        .modalHeader2G = {
+                /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x80c080),
+                .papdRateMaskHt40 = LE32(0x80c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+        },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2484, 1),
+        },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTargetPowerCck = {
+                /* 1L-5L,5S,11L,11S */
+                { {34, 34, 34, 34} },
+                { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                /* 6-24,36,48,54 */
+                { {34, 34, 32, 32} },
+                { {34, 34, 32, 32} },
+                { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+        },
+        .ctlPowerData_2G = {
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+        },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+                /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 45,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext2 = {
+                .tempSlopeLow = 40,
+                .tempSlopeHigh = 50,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+        },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calPierData5G = {
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+        },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
+        },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
+        },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+        },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+        }
+};
+
+
+static const struct ar9300_eeprom ar9300_x112 = {
+        .eepromVersion = 2,
+        .templateVersion = 5,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"x112-041-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                /*
+                 * bit0 - enable tx temp comp - disabled
+                 * bit1 - enable tx volt comp - disabled
+                 * bit2 - enable fastclock - enabled
+                 * bit3 - enable doubling - enabled
+                 * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
+                 */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x0,
+                .swreg = 0,
+        },
+        .modalHeader2G = {
+                /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x22222),
+
+                /*
+                 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+                /*
+                 * xatten1DB[AR9300_max_chains];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0x1b, 0x1b, 0x1b},
+
+                /*
+                 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x15, 0x15, 0x15},
+                .tempSlope = 50,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+        },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTargetPowerCck = {
+                /* 1L-5L,5S,11L,11s */
+                { {38, 38, 38, 38} },
+                { {38, 38, 38, 38} },
+        },
+        .calTargetPower2G = {
+                /* 6-24,36,48,54 */
+                { {38, 38, 36, 34} },
+                { {38, 38, 36, 34} },
+                { {38, 38, 34, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
+                { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
+                { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
+        },
+        .calTargetPower2GHT40 = {
+                { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
+                { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
+                { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
+                }
+        },
+        .ctlPowerData_2G = {
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+        },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x22222),
+                /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x0), LE16(0x0), LE16(0x0),
+                },
+                /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0x13, 0x19, 0x17},
+
+                /*
+                 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x19, 0x19, 0x19},
+                .tempSlope = 70,
+                .voltSlope = 15,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshch check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext2 = {
+                .tempSlopeLow = 72,
+                .tempSlopeHigh = 105,
+                .xatten1DBLow = {0x10, 0x14, 0x10},
+                .xatten1MarginLow = {0x19, 0x19 , 0x19},
+                .xatten1DBHigh = {0x1d, 0x20, 0x24},
+                .xatten1MarginHigh = {0x10, 0x10, 0x10}
+        },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {32, 32, 28, 26} },
+                { {32, 32, 28, 26} },
+                { {32, 32, 28, 26} },
+                { {32, 32, 26, 24} },
+                { {32, 32, 26, 24} },
+                { {32, 32, 24, 22} },
+                { {30, 30, 24, 22} },
+                { {30, 30, 24, 22} },
+        },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
+                { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
+                { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
+        },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
+                { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
+                { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+        },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctledges[6].bchannel */ 0xFF,
+                        /* Data[3].ctledges[7].bchannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctledges[4].bchannel */ 0xFF,
+                        /* Data[4].ctledges[5].bchannel */ 0xFF,
+                        /* Data[4].ctledges[6].bchannel */ 0xFF,
+                        /* Data[4].ctledges[7].bchannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctledges[6].bchannel */ 0xFF,
+                        /* Data[5].ctledges[7].bchannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
+                }
+        },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+        }
+};
+
+static const struct ar9300_eeprom ar9300_h116 = {
+        .eepromVersion = 2,
+        .templateVersion = 4,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"h116-041-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                 /*
+                  * bit0 - enable tx temp comp - disabled
+                  * bit1 - enable tx volt comp - disabled
+                  * bit2 - enable fastClock - enabled
+                  * bit3 - enable doubling - enabled
+                  * bit4 - enable internal regulator - disabled
+                  * bit5 - enable pa predistortion - disabled
+                  */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x10,
+                .swreg = 0,
+         },
+        .modalHeader2G = {
+        /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0x1f, 0x1f, 0x1f},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x12, 0x12, 0x12},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80C080),
+                .papdRateMaskHt40 = LE32(0x0080C080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+         .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+         },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+         },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTargetPowerCck = {
+                 /* 1L-5L,5S,11L,11S */
+                 { {34, 34, 34, 34} },
+                 { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                 /* 6-24,36,48,54 */
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+         },
+        .ctlPowerData_2G = {
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+         },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0x19, 0x19, 0x19},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x14, 0x14, 0x14},
+                .tempSlope = 70,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+        .base_ext2 = {
+                .tempSlopeLow = 35,
+                .tempSlopeHigh = 50,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+         },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+         },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+         },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+         },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+         },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+         },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+         }
+};
+
+
+static const struct ar9300_eeprom *ar9300_eep_templates[] = {
+        &ar9300_default,
+        &ar9300_x112,
+        &ar9300_h116,
+        &ar9300_h112,
+        &ar9300_x113,
+};
+
+static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
+{
+#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
+        int it;
+
+        for (it = 0; it < N_LOOP; it++)
+                if (ar9300_eep_templates[it]->templateVersion == id)
+                        return ar9300_eep_templates[it];
+        return NULL;
+#undef N_LOOP
+}
+
+
 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
 {
-        if (fbin == AR9300_BCHAN_UNUSED)
+        if (fbin == AR5416_BCHAN_UNUSED)
                 return fbin;
 
         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
@@ -636,6 +2988,16 @@ static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
         return 0;
 }
 
+static int interpolate(int x, int xa, int xb, int ya, int yb)
+{
+        int bf, factor, plus;
+
+        bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
+        factor = bf / 2;
+        plus = bf % 2;
+        return ya + factor + plus;
+}
+
 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                                       enum eeprom_param param)
 {
@@ -673,6 +3035,10 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                 return le32_to_cpu(pBase->swreg);
         case EEP_PAPRD:
                 return !!(pBase->featureEnable & BIT(5));
+        case EEP_CHAIN_MASK_REDUCE:
+                return (pBase->miscConfiguration >> 0x3) & 0x1;
+        case EEP_ANT_DIV_CTL1:
+                return le32_to_cpu(eep->base_ext1.ant_div_control);
         default:
                 return 0;
         }
@@ -711,8 +3077,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
         int i;
 
         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "eeprom address not in range\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "eeprom address not in range\n");
                 return false;
         }
 
@@ -743,11 +3109,41 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
         return true;
 
 error:
-        ath_print(common, ATH_DBG_EEPROM,
-                  "unable to read eeprom region at offset %d\n", address);
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "unable to read eeprom region at offset %d\n", address);
         return false;
 }
 
+static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
+{
+        REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
+
+        if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
+                           AR9300_OTP_STATUS_VALID, 1000))
+                return false;
+
+        *data = REG_READ(ah, AR9300_OTP_READ_DATA);
+        return true;
+}
+
+static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
+                            int count)
+{
+        u32 data;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                int offset = 8 * ((address - i) % 4);
+                if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
+                        return false;
+
+                buffer[i] = (data >> offset) & 0xff;
+        }
+
+        return true;
+}
+
+
 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
                                    int *length, int *major, int *minor)
 {
@@ -798,17 +3194,15 @@ static bool ar9300_uncompress_block(struct ath_hw *ah,
                 length &= 0xff;
 
                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Restore at %d: spot=%d "
-                                  "offset=%d length=%d\n",
-                                   it, spot, offset, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Restore at %d: spot=%d offset=%d length=%d\n",
+                                it, spot, offset, length);
                         memcpy(&mptr[spot], &block[it+2], length);
                         spot += length;
                 } else if (length > 0) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Bad restore at %d: spot=%d "
-                                  "offset=%d length=%d\n",
-                                  it, spot, offset, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Bad restore at %d: spot=%d offset=%d length=%d\n",
+                                it, spot, offset, length);
                         return false;
                 }
         }
@@ -823,46 +3217,79 @@ static int ar9300_compress_decision(struct ath_hw *ah,
                                     u8 *word, int length, int mdata_size)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        u8 *dptr;
+        const struct ar9300_eeprom *eep = NULL;
 
         switch (code) {
         case _CompressNone:
                 if (length != mdata_size) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "EEPROM structure size mismatch"
-                                  "memory=%d eeprom=%d\n", mdata_size, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "EEPROM structure size mismatch memory=%d eeprom=%d\n",
+                                mdata_size, length);
                         return -1;
                 }
                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
-                ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
-                          " uncompressed, length %d\n", it, length);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "restored eeprom %d: uncompressed, length %d\n",
+                        it, length);
                 break;
         case _CompressBlock:
                 if (reference == 0) {
-                        dptr = mptr;
                 } else {
-                        if (reference != 2) {
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "cant find reference eeprom"
-                                          "struct %d\n", reference);
+                        eep = ar9003_eeprom_struct_find_by_id(reference);
+                        if (eep == NULL) {
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "can't find reference eeprom struct %d\n",
+                                        reference);
                                 return -1;
                         }
-                        memcpy(mptr, &ar9300_default, mdata_size);
+                        memcpy(mptr, eep, mdata_size);
                 }
-                ath_print(common, ATH_DBG_EEPROM,
-                          "restore eeprom %d: block, reference %d,"
-                          " length %d\n", it, reference, length);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "restore eeprom %d: block, reference %d, length %d\n",
+                        it, reference, length);
                 ar9300_uncompress_block(ah, mptr, mdata_size,
                                         (u8 *) (word + COMP_HDR_LEN), length);
                 break;
         default:
-                ath_print(common, ATH_DBG_EEPROM, "unknown compression"
-                          " code %d\n", code);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "unknown compression code %d\n", code);
                 return -1;
         }
         return 0;
 }
 
+typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
+                               int count);
+
+static bool ar9300_check_header(void *data)
+{
+        u32 *word = data;
+        return !(*word == 0 || *word == ~0);
+}
+
+static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
+                                       int base_addr)
+{
+        u8 header[4];
+
+        if (!read(ah, base_addr, header, 4))
+                return false;
+
+        return ar9300_check_header(header);
+}
+
+static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
+                                       int mdata_size)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u16 *data = (u16 *) mptr;
+        int i;
+
+        for (i = 0; i < mdata_size / 2; i++, data++)
+                ath9k_hw_nvram_read(common, i, data);
+
+        return 0;
+}
 /*
  * Read the configuration data from the eeprom.
  * The data can be put in any specified memory buffer.
@@ -883,6 +3310,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
         int it;
         u16 checksum, mchecksum;
         struct ath_common *common = ath9k_hw_common(ah);
+        eeprom_read_op read;
+
+        if (ath9k_hw_use_flash(ah))
+                return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
 
         word = kzalloc(2048, GFP_KERNEL);
         if (!word)
@@ -890,43 +3321,73 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
 
         memcpy(mptr, &ar9300_default, mdata_size);
 
+        read = ar9300_read_eeprom;
+        if (AR_SREV_9485(ah))
+                cptr = AR9300_BASE_ADDR_4K;
+        else
+                cptr = AR9300_BASE_ADDR;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying EEPROM access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        cptr = AR9300_BASE_ADDR_512;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying EEPROM access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        read = ar9300_read_otp;
         cptr = AR9300_BASE_ADDR;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying OTP access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        cptr = AR9300_BASE_ADDR_512;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying OTP access at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        goto fail;
+
+found:
+        ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
+
         for (it = 0; it < MSTATE; it++) {
-                if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
+                if (!read(ah, cptr, word, COMP_HDR_LEN))
                         goto fail;
 
-                if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
-                     word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
-                                       && word[2] == 0xff && word[3] == 0xff))
+                if (!ar9300_check_header(word))
                         break;
 
                 ar9300_comp_hdr_unpack(word, &code, &reference,
                                        &length, &major, &minor);
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Found block at %x: code=%d ref=%d"
-                          "length=%d major=%d minor=%d\n", cptr, code,
-                          reference, length, major, minor);
-                if (length >= 1024) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Skipping bad header\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
+                        cptr, code, reference, length, major, minor);
+                if ((!AR_SREV_9485(ah) && length >= 1024) ||
+                    (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Skipping bad header\n");
                         cptr -= COMP_HDR_LEN;
                         continue;
                 }
 
                 osize = length;
-                ar9300_read_eeprom(ah, cptr, word,
-                                   COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
+                read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
                 mchecksum = word[COMP_HDR_LEN + osize] |
                     (word[COMP_HDR_LEN + osize + 1] << 8);
-                ath_print(common, ATH_DBG_EEPROM,
-                          "checksum %x %x\n", checksum, mchecksum);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "checksum %x %x\n", checksum, mchecksum);
                 if (checksum == mchecksum) {
                         ar9300_compress_decision(ah, it, code, reference, mptr,
                                                  word, length, mdata_size);
                 } else {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "skipping block with bad checksum\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "skipping block with bad checksum\n");
                 }
                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
         }
@@ -967,18 +3428,6 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
         return 0;
 }
 
-static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
-                                             enum ieee80211_band freq_band)
-{
-        return 1;
-}
-
-static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                                  struct ath9k_channel *chan)
-{
-        return -EINVAL;
-}
-
 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 {
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
@@ -992,9 +3441,17 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
-        REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
-        REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
-                      ((bias >> 2) & 0x3));
+
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+        else {
+                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+                REG_RMW_FIELD(ah, AR_CH0_THERM,
+                                AR_CH0_THERM_XPABIASLVL_MSB,
+                                bias >> 2);
+                REG_RMW_FIELD(ah, AR_CH0_THERM,
+                                AR_CH0_THERM_XPASHORT2GND, 1);
+        }
 }
 
 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@ -1040,20 +3497,77 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
 
 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
 {
+        int chain;
+        u32 regval;
+        u32 ant_div_ctl1;
+        static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
+                        AR_PHY_SWITCH_CHAIN_0,
+                        AR_PHY_SWITCH_CHAIN_1,
+                        AR_PHY_SWITCH_CHAIN_2,
+        };
+
         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
+
         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
 
         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
+        for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
+                if ((ah->rxchainmask & BIT(chain)) ||
+                    (ah->txchainmask & BIT(chain))) {
+                        value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
+                                                             is2ghz);
+                        REG_RMW_FIELD(ah, switch_chain_reg[chain],
+                                      AR_SWITCH_TABLE_ALL, value);
+                }
+        }
+
+        if (AR_SREV_9485(ah)) {
+                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                /*
+                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
+                 * are the fields present
+                 */
+                regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                regval &= (~AR_ANT_DIV_CTRL_ALL);
+                regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
+                /* enable_lnadiv */
+                regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
+                regval |= ((value >> 6) & 0x1) <<
+                                AR_PHY_9485_ANT_DIV_LNADIV_S;
+                REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+
+                /*enable fast_div */
+                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
+                regval &= (~AR_FAST_DIV_ENABLE);
+                regval |= ((value >> 7) & 0x1) <<
+                                AR_FAST_DIV_ENABLE_S;
+                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
+                ant_div_ctl1 =
+                        ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                /* check whether antenna diversity is enabled */
+                if ((ant_div_ctl1 >> 0x6) == 0x3) {
+                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                        /*
+                         * clear bits 25-30 main_lnaconf, alt_lnaconf,
+                         * main_tb, alt_tb
+                         */
+                        regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                                        AR_PHY_9485_ANT_DIV_ALT_GAINTB |
+                                        AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
+                        /* by default use LNA1 for the main antenna */
+                        regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
+                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
+                        regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
+                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
+                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+                }
+
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
+        }
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
 }
 
 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@ -1097,28 +3611,180 @@ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
 }
 
+static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
+                                     struct ath9k_channel *chan)
+{
+        int f[3], t[3];
+        u16 value;
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (chain >= 0 && chain < 3) {
+                if (IS_CHAN_2GHZ(chan))
+                        return eep->modalHeader2G.xatten1DB[chain];
+                else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
+                        t[0] = eep->base_ext2.xatten1DBLow[chain];
+                        f[0] = 5180;
+                        t[1] = eep->modalHeader5G.xatten1DB[chain];
+                        f[1] = 5500;
+                        t[2] = eep->base_ext2.xatten1DBHigh[chain];
+                        f[2] = 5785;
+                        value = ar9003_hw_power_interpolate((s32) chan->channel,
+                                                            f, t, 3);
+                        return value;
+                } else
+                        return eep->modalHeader5G.xatten1DB[chain];
+        }
+
+        return 0;
+}
+
+
+static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
+                                            struct ath9k_channel *chan)
+{
+        int f[3], t[3];
+        u16 value;
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (chain >= 0 && chain < 3) {
+                if (IS_CHAN_2GHZ(chan))
+                        return eep->modalHeader2G.xatten1Margin[chain];
+                else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
+                        t[0] = eep->base_ext2.xatten1MarginLow[chain];
+                        f[0] = 5180;
+                        t[1] = eep->modalHeader5G.xatten1Margin[chain];
+                        f[1] = 5500;
+                        t[2] = eep->base_ext2.xatten1MarginHigh[chain];
+                        f[2] = 5785;
+                        value = ar9003_hw_power_interpolate((s32) chan->channel,
+                                                            f, t, 3);
+                        return value;
+                } else
+                        return eep->modalHeader5G.xatten1Margin[chain];
+        }
+
+        return 0;
+}
+
+static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
+{
+        int i;
+        u16 value;
+        unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
+                                          AR_PHY_EXT_ATTEN_CTL_1,
+                                          AR_PHY_EXT_ATTEN_CTL_2,
+                                         };
+
+        /* Test value. if 0 then attenuation is unused. Don't load anything. */
+        for (i = 0; i < 3; i++) {
+                if (ah->txchainmask & BIT(i)) {
+                        value = ar9003_hw_atten_chain_get(ah, i, chan);
+                        REG_RMW_FIELD(ah, ext_atten_reg[i],
+                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
+
+                        value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
+                        REG_RMW_FIELD(ah, ext_atten_reg[i],
+                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
+                                      value);
+                }
+        }
+}
+
+static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
+{
+        int timeout = 100;
+
+        while (pmu_set != REG_READ(ah, pmu_reg)) {
+                if (timeout-- == 0)
+                        return false;
+                REG_WRITE(ah, pmu_reg, pmu_set);
+                udelay(10);
+        }
+
+        return true;
+}
+
 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
 {
         int internal_regulator =
                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
 
         if (internal_regulator) {
-                /* Internal regulator is ON. Write swreg register. */
-                int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
-                REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                REG_READ(ah, AR_RTC_REG_CONTROL1) &
-                         (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
-                REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
-                /* Set REG_CONTROL1.SWREG_PROGRAM */
-                REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                          REG_READ(ah,
-                                   AR_RTC_REG_CONTROL1) |
-                                   AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+                if (AR_SREV_9485(ah)) {
+                        int reg_pmu_set;
+
+                        reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
+                                      (2 << 14) | (6 << 17) | (1 << 20) |
+                                      (3 << 24) | (1 << 28);
+
+                        REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
+                                        | (4 << 26);
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
+                                        | (1 << 21);
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+                } else {
+                        /* Internal regulator is ON. Write swreg register. */
+                        int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                  REG_READ(ah, AR_RTC_REG_CONTROL1) &
+                                  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
+                        /* Set REG_CONTROL1.SWREG_PROGRAM */
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                  REG_READ(ah,
+                                           AR_RTC_REG_CONTROL1) |
+                                           AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+                }
         } else {
-                REG_WRITE(ah, AR_RTC_SLEEP_CLK,
-                          (REG_READ(ah,
-                                    AR_RTC_SLEEP_CLK) |
-                                    AR_RTC_FORCE_SWREG_PRD));
+                if (AR_SREV_9485(ah)) {
+                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
+                        while (REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                              AR_PHY_PMU2_PGM))
+                                udelay(10);
+
+                        REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
+                        while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
+                                               AR_PHY_PMU1_PWD))
+                                udelay(10);
+                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
+                        while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                              AR_PHY_PMU2_PGM))
+                                udelay(10);
+                } else
+                        REG_WRITE(ah, AR_RTC_SLEEP_CLK,
+                                  (REG_READ(ah,
+                                   AR_RTC_SLEEP_CLK) |
+                                   AR_RTC_FORCE_SWREG_PRD));
+        }
+
+}
+
+static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+
+        if (eep->baseEepHeader.featureEnable & 0x40) {
+                tuning_caps_param &= 0x7f;
+                REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
+                              tuning_caps_param);
+                REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
+                              tuning_caps_param);
         }
 }
 
@@ -1128,7 +3794,11 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
         ar9003_hw_drive_strength_apply(ah);
-        ar9003_hw_internal_regulator_apply(ah);
+        ar9003_hw_atten_apply(ah, chan);
+        if (!AR_SREV_9340(ah))
+                ar9003_hw_internal_regulator_apply(ah);
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                ar9003_hw_apply_tuning_caps(ah);
 }
 
 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -1189,7 +3859,7 @@ static int ar9003_hw_power_interpolate(int32_t x,
                         if (hx == lx)
                                 y = ly;
                         else    /* interpolate  */
-                                y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
+                                y = interpolate(x, lx, hx, ly, hy);
                 } else          /* only low is good, use it */
                         y = ly;
         } else if (hhave)       /* only high is good, use it */
@@ -1336,19 +4006,19 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
 {
 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
         /* make sure forced gain is not set */
-        REG_WRITE(ah, 0xa458, 0);
+        REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
 
         /* Write the OFDM power per rate set */
 
         /* 6 (LSB), 9, 12, 18 (MSB) */
-        REG_WRITE(ah, 0xa3c0,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
 
         /* 24 (LSB), 36, 48, 54 (MSB) */
-        REG_WRITE(ah, 0xa3c4,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
@@ -1357,24 +4027,34 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
         /* Write the CCK power per rate set */
 
         /* 1L (LSB), reserved, 2L, 2S (MSB) */
-        REG_WRITE(ah, 0xa3c8,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
 
         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
-        REG_WRITE(ah, 0xa3cc,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
             );
 
+        /* Write the power for duplicated frames - HT40 */
+
+        /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
+        REG_WRITE(ah, 0xa3e0,
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
+                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
+            );
+
         /* Write the HT20 power per rate set */
 
         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
-        REG_WRITE(ah, 0xa3d0,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
@@ -1382,7 +4062,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 6 (LSB), 7, 12, 13 (MSB) */
-        REG_WRITE(ah, 0xa3d4,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
@@ -1390,7 +4070,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 14 (LSB), 15, 20, 21 */
-        REG_WRITE(ah, 0xa3e4,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
@@ -1400,7 +4080,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
         /* Mixed HT20 and HT40 rates */
 
         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
-        REG_WRITE(ah, 0xa3e8,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
@@ -1412,7 +4092,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
          * correct PAR difference between HT40 and HT20/LEGACY
          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
          */
-        REG_WRITE(ah, 0xa3d8,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
@@ -1420,7 +4100,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 6 (LSB), 7, 12, 13 (MSB) */
-        REG_WRITE(ah, 0xa3dc,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
@@ -1428,7 +4108,7 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
             );
 
         /* 14 (LSB), 15, 20, 21 */
-        REG_WRITE(ah, 0xa3ec,
+        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
@@ -1558,22 +4238,9 @@ static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
                                               is2GHz) + ht40PowerIncForPdadc;
 
-        while (i < ar9300RateSize) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
-                i++;
+        for (i = 0; i < ar9300RateSize; i++) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
         }
 }
 
@@ -1592,18 +4259,17 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
         struct ath_common *common = ath9k_hw_common(ah);
 
         if (ichain >= AR9300_MAX_CHAINS) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Invalid chain index, must be less than %d\n",
-                          AR9300_MAX_CHAINS);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Invalid chain index, must be less than %d\n",
+                        AR9300_MAX_CHAINS);
                 return -1;
         }
 
         if (mode) {             /* 5GHz */
                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Invalid 5GHz cal pier index, must "
-                                  "be less than %d\n",
-                                  AR9300_NUM_5G_CAL_PIERS);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Invalid 5GHz cal pier index, must be less than %d\n",
+                                AR9300_NUM_5G_CAL_PIERS);
                         return -1;
                 }
                 pCalPier = &(eep->calFreqPier5G[ipier]);
@@ -1611,9 +4277,9 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
                 is2GHz = 0;
         } else {
                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Invalid 2GHz cal pier index, must "
-                                  "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Invalid 2GHz cal pier index, must be less than %d\n",
+                                AR9300_NUM_2G_CAL_PIERS);
                         return -1;
                 }
 
@@ -1637,27 +4303,32 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
 {
         int tempSlope = 0;
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        int f[3], t[3];
 
         REG_RMW(ah, AR_PHY_TPC_11_B0,
                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                 AR_PHY_TPC_OLPC_GAIN_DELTA);
-        REG_RMW(ah, AR_PHY_TPC_11_B1,
-                (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-                AR_PHY_TPC_OLPC_GAIN_DELTA);
-        REG_RMW(ah, AR_PHY_TPC_11_B2,
-                (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-                AR_PHY_TPC_OLPC_GAIN_DELTA);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW(ah, AR_PHY_TPC_11_B1,
+                        (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                        AR_PHY_TPC_OLPC_GAIN_DELTA);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW(ah, AR_PHY_TPC_11_B2,
+                        (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                        AR_PHY_TPC_OLPC_GAIN_DELTA);
 
         /* enable open loop power control on chip */
         REG_RMW(ah, AR_PHY_TPC_6_B0,
                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                 AR_PHY_TPC_6_ERROR_EST_MODE);
-        REG_RMW(ah, AR_PHY_TPC_6_B1,
-                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-                AR_PHY_TPC_6_ERROR_EST_MODE);
-        REG_RMW(ah, AR_PHY_TPC_6_B2,
-                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-                AR_PHY_TPC_6_ERROR_EST_MODE);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW(ah, AR_PHY_TPC_6_B1,
+                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                        AR_PHY_TPC_6_ERROR_EST_MODE);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW(ah, AR_PHY_TPC_6_B2,
+                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                        AR_PHY_TPC_6_ERROR_EST_MODE);
 
         /*
          * enable temperature compensation
@@ -1665,7 +4336,16 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
          */
         if (frequency < 4000)
                 tempSlope = eep->modalHeader2G.tempSlope;
-        else
+        else if (eep->base_ext2.tempSlopeLow != 0) {
+                t[0] = eep->base_ext2.tempSlopeLow;
+                f[0] = 5180;
+                t[1] = eep->modalHeader5G.tempSlope;
+                f[1] = 5500;
+                t[2] = eep->base_ext2.tempSlopeHigh;
+                f[2] = 5785;
+                tempSlope = ar9003_hw_power_interpolate((s32) frequency,
+                                                        f, t, 3);
+        } else
                 tempSlope = eep->modalHeader5G.tempSlope;
 
         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
@@ -1753,11 +4433,11 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
 
         /* interpolate  */
         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "ch=%d f=%d low=%d %d h=%d %d\n",
-                          ichain, frequency, lfrequency[ichain],
-                          lcorrection[ichain], hfrequency[ichain],
-                          hcorrection[ichain]);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "ch=%d f=%d low=%d %d h=%d %d\n",
+                        ichain, frequency, lfrequency[ichain],
+                        lcorrection[ichain], hfrequency[ichain],
+                        hcorrection[ichain]);
                 /* they're the same, so just pick one */
                 if (hfrequency[ichain] == lfrequency[ichain]) {
                         correction[ichain] = lcorrection[ichain];
@@ -1769,25 +4449,23 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
                         /* so is the high frequency, interpolate */
                         if (hfrequency[ichain] - frequency < 1000) {
 
-                                correction[ichain] = lcorrection[ichain] +
-                                    (((frequency - lfrequency[ichain]) *
-                                      (hcorrection[ichain] -
-                                       lcorrection[ichain])) /
-                                     (hfrequency[ichain] - lfrequency[ichain]));
-
-                                temperature[ichain] = ltemperature[ichain] +
-                                    (((frequency - lfrequency[ichain]) *
-                                      (htemperature[ichain] -
-                                       ltemperature[ichain])) /
-                                     (hfrequency[ichain] - lfrequency[ichain]));
-
-                                voltage[ichain] =
-                                    lvoltage[ichain] +
-                                    (((frequency -
-                                       lfrequency[ichain]) * (hvoltage[ichain] -
-                                                              lvoltage[ichain]))
-                                     / (hfrequency[ichain] -
-                                        lfrequency[ichain]));
+                                correction[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                lcorrection[ichain],
+                                                hcorrection[ichain]);
+
+                                temperature[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                ltemperature[ichain],
+                                                htemperature[ichain]);
+
+                                voltage[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                lvoltage[ichain],
+                                                hvoltage[ichain]);
                         }
                         /* only low is good, use it */
                         else {
@@ -1811,9 +4489,9 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
                                          temperature);
 
-        ath_print(common, ATH_DBG_EEPROM,
-                  "for frequency=%d, calibration correction = %d %d %d\n",
-                  frequency, correction[0], correction[1], correction[2]);
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "for frequency=%d, calibration correction = %d %d %d\n",
+                frequency, correction[0], correction[1], correction[2]);
 
         return 0;
 }
@@ -1827,9 +4505,9 @@ static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
 
         if (is2GHz)
-                return ctl_2g[idx].ctlEdges[edge].tPower;
+                return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
         else
-                return ctl_5g[idx].ctlEdges[edge].tPower;
+                return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
 }
 
 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
@@ -1847,15 +4525,15 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
 
         if (is2GHz) {
                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
-                    ctl_2g[idx].ctlEdges[edge - 1].flag)
-                        return ctl_2g[idx].ctlEdges[edge - 1].tPower;
+                    CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
+                        return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
         } else {
                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
-                    ctl_5g[idx].ctlEdges[edge - 1].flag)
-                        return ctl_5g[idx].ctlEdges[edge - 1].tPower;
+                    CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
+                        return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
         }
 
-        return AR9300_MAX_RATE_POWER;
+        return MAX_RATE_POWER;
 }
 
 /*
@@ -1864,7 +4542,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
                                         u16 freq, int idx, bool is2GHz)
 {
-        u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         u8 *ctl_freqbin = is2GHz ?
                 &eep->ctl_freqbin_2G[idx][0] :
                 &eep->ctl_freqbin_5G[idx][0];
@@ -1874,7 +4552,7 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
 
         /* Get the edge power */
         for (edge = 0;
-             (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
+             (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
              edge++) {
                 /*
                  * If there's an exact channel match or an inband flag set
@@ -1912,21 +4590,23 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
-        u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] = {
-                0, 3, 6, 9, AR9300_MAX_RATE_POWER
+                0, 3, 6, 9, MAX_RATE_POWER
         };
         int i;
         int16_t  twiceLargestAntenna;
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11a[] = {
+        static const u16 ctlModesFor11a[] = {
                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
         };
-        u16 ctlModesFor11g[] = {
+        static const u16 ctlModesFor11g[] = {
                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
                 CTL_11G_EXT, CTL_2GHT40
         };
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         u8 *ctlIndex;
         u8 ctlNum;
@@ -1965,10 +4645,16 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         case 1:
                 break;
         case 2:
-                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         case 3:
-                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         }
 
@@ -2016,11 +4702,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                 else
                         freq = centers.ctl_center;
 
-                ath_print(common, ATH_DBG_REGULATORY,
-                          "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
-                          "EXT_ADDITIVE %d\n",
-                          ctlMode, numCtlModes, isHt40CtlMode,
-                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
+                ath_dbg(common, ATH_DBG_REGULATORY,
+                        "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
+                        ctlMode, numCtlModes, isHt40CtlMode,
+                        (pCtlMode[ctlMode] & EXT_ADDITIVE));
 
                 /* walk through each CTL index stored in EEPROM */
                 if (is2ghz) {
@@ -2032,12 +4717,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                 }
 
                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
-                        ath_print(common, ATH_DBG_REGULATORY,
-                                  "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
-                                  "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
-                                  "chan %dn",
-                                  i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
-                                  chan->channel);
+                        ath_dbg(common, ATH_DBG_REGULATORY,
+                                "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
+                                i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
+                                chan->channel);
 
                                 /*
                                  * compare test group from regulatory
@@ -2076,11 +4759,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
 
                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 
-                        ath_print(common, ATH_DBG_REGULATORY,
-                                  "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
-                                  "sP %d minCtlPwr %d\n",
-                                  ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
-                                  scaledPower, minCtlPower);
+                        ath_dbg(common, ATH_DBG_REGULATORY,
+                                "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
+                                ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
+                                scaledPower, minCtlPower);
 
                         /* Apply ctl mode to correct target power set */
                         switch (pCtlMode[ctlMode]) {
@@ -2127,40 +4809,101 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         } /* end ctl mode checking */
 }
 
+static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
+{
+        u8 mod_idx = mcs_idx % 8;
+
+        if (mod_idx <= 3)
+                return mod_idx ? (base_pwridx + 1) : base_pwridx;
+        else
+                return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
+}
+
 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
                                         struct ath9k_channel *chan, u16 cfgCtl,
                                         u8 twiceAntennaReduction,
                                         u8 twiceMaxRegulatoryPower,
-                                        u8 powerLimit)
+                                        u8 powerLimit, bool test)
 {
+        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        struct ar9300_modal_eep_header *modal_hdr;
         u8 targetPowerValT2[ar9300RateSize];
-        unsigned int i = 0;
+        u8 target_power_val_t2_eep[ar9300RateSize];
+        unsigned int i = 0, paprd_scale_factor = 0;
+        u8 pwr_idx, min_pwridx = 0;
 
         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
+
+        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
+                if (IS_CHAN_2GHZ(chan))
+                        modal_hdr = &eep->modalHeader2G;
+                else
+                        modal_hdr = &eep->modalHeader5G;
+
+                ah->paprd_ratemask =
+                        le32_to_cpu(modal_hdr->papdRateMaskHt20) &
+                        AR9300_PAPRD_RATE_MASK;
+
+                ah->paprd_ratemask_ht40 =
+                        le32_to_cpu(modal_hdr->papdRateMaskHt40) &
+                        AR9300_PAPRD_RATE_MASK;
+
+                paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
+                min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
+                                                  ALL_TARGET_HT20_0_8_16;
+
+                if (!ah->paprd_table_write_done) {
+                        memcpy(target_power_val_t2_eep, targetPowerValT2,
+                               sizeof(targetPowerValT2));
+                        for (i = 0; i < 24; i++) {
+                                pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
+                                if (ah->paprd_ratemask & (1 << i)) {
+                                        if (targetPowerValT2[pwr_idx] &&
+                                            targetPowerValT2[pwr_idx] ==
+                                            target_power_val_t2_eep[pwr_idx])
+                                                targetPowerValT2[pwr_idx] -=
+                                                        paprd_scale_factor;
+                                }
+                        }
+                }
+                memcpy(target_power_val_t2_eep, targetPowerValT2,
+                       sizeof(targetPowerValT2));
+        }
+
         ar9003_hw_set_power_per_rate_table(ah, chan,
                                            targetPowerValT2, cfgCtl,
                                            twiceAntennaReduction,
                                            twiceMaxRegulatoryPower,
                                            powerLimit);
 
-        while (i < ar9300RateSize) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
-                i++;
+        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
+                for (i = 0; i < ar9300RateSize; i++) {
+                        if ((ah->paprd_ratemask & (1 << i)) &&
+                            (abs(targetPowerValT2[i] -
+                                target_power_val_t2_eep[i]) >
+                            paprd_scale_factor)) {
+                                ah->paprd_ratemask &= ~(1 << i);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "paprd disabled for mcs %d\n", i);
+                        }
+                }
         }
 
-        /* Write target power array to registers */
-        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
+        regulatory->max_power_level = 0;
+        for (i = 0; i < ar9300RateSize; i++) {
+                if (targetPowerValT2[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = targetPowerValT2[i];
+        }
+
+        if (test)
+                return;
+
+        for (i = 0; i < ar9300RateSize; i++) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
+        }
 
         /*
          * This is the TX power we send back to driver core,
@@ -2180,8 +4923,24 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
                 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
 
         ah->txpower_limit = targetPowerValT2[i];
+        regulatory->max_power_level = targetPowerValT2[i];
 
+        /* Write target power array to registers */
+        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
         ar9003_hw_calibration_apply(ah, chan->channel);
+
+        if (IS_CHAN_2GHZ(chan)) {
+                if (IS_CHAN_HT40(chan))
+                        i = ALL_TARGET_HT40_0_8_16;
+                else
+                        i = ALL_TARGET_HT20_0_8_16;
+        } else {
+                if (IS_CHAN_HT40(chan))
+                        i = ALL_TARGET_HT40_7;
+                else
+                        i = ALL_TARGET_HT20_7;
+        }
+        ah->paprd_target_power = targetPowerValT2[i];
 }
 
 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
@@ -2204,14 +4963,43 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
 }
 
+u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (is_2ghz)
+                return eep->modalHeader2G.spurChans;
+        else
+                return eep->modalHeader5G.spurChans;
+}
+
+unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+                                           struct ath9k_channel *chan)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (IS_CHAN_2GHZ(chan))
+                return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
+                          AR9300_PAPRD_SCALE_1);
+        else {
+                if (chan->channel >= 5700)
+                return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
+                          AR9300_PAPRD_SCALE_1);
+                else if (chan->channel >= 5400)
+                        return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
+                                   AR9300_PAPRD_SCALE_2);
+                else
+                        return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
+                                  AR9300_PAPRD_SCALE_1);
+        }
+}
+
 const struct eeprom_ops eep_ar9300_ops = {
         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
-        .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
         .set_board_values = ath9k_hw_ar9300_set_board_values,
         .set_addac = ath9k_hw_ar9300_set_addac,
         .set_txpower = ath9k_hw_ar9300_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 3c533bb983c7..ab21a4915981 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
 #ifndef AR9003_EEPROM_H
 #define AR9003_EEPROM_H
 
@@ -20,47 +36,22 @@
 /* #define AR9300_NUM_CTLS              21 */
 #define AR9300_NUM_CTLS_5G           9
 #define AR9300_NUM_CTLS_2G           12
-#define AR9300_CTL_MODE_M            0xF
 #define AR9300_NUM_BAND_EDGES_5G     8
 #define AR9300_NUM_BAND_EDGES_2G     4
-#define AR9300_NUM_PD_GAINS          4
-#define AR9300_PD_GAINS_IN_MASK      4
-#define AR9300_PD_GAIN_ICEPTS        5
-#define AR9300_EEPROM_MODAL_SPURS    5
-#define AR9300_MAX_RATE_POWER        63
-#define AR9300_NUM_PDADC_VALUES      128
-#define AR9300_NUM_RATES             16
-#define AR9300_BCHAN_UNUSED          0xFF
-#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
-#define AR9300_OPFLAGS_11A           0x01
-#define AR9300_OPFLAGS_11G           0x02
-#define AR9300_OPFLAGS_5G_HT40       0x04
-#define AR9300_OPFLAGS_2G_HT40       0x08
-#define AR9300_OPFLAGS_5G_HT20       0x10
-#define AR9300_OPFLAGS_2G_HT20       0x20
 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
 #define AR9300_EEPMISC_WOW           0x02
 #define AR9300_CUSTOMER_DATA_SIZE    20
 
-#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
 #define AR9300_MAX_CHAINS            3
 #define AR9300_ANT_16S               25
 #define AR9300_FUTURE_MODAL_SZ       6
 
-#define AR9300_NUM_ANT_CHAIN_FIELDS     7
-#define AR9300_NUM_ANT_COMMON_FIELDS    4
-#define AR9300_SIZE_ANT_CHAIN_FIELD     3
-#define AR9300_SIZE_ANT_COMMON_FIELD    4
-#define AR9300_ANT_CHAIN_MASK           0x7
-#define AR9300_ANT_COMMON_MASK          0xf
-#define AR9300_CHAIN_0_IDX              0
-#define AR9300_CHAIN_1_IDX              1
-#define AR9300_CHAIN_2_IDX              2
-
-#define AR928X_NUM_ANT_CHAIN_FIELDS     6
-#define AR928X_SIZE_ANT_CHAIN_FIELD     2
-#define AR928X_ANT_CHAIN_MASK           0x3
+#define AR9300_PAPRD_RATE_MASK          0x01ffffff
+#define AR9300_PAPRD_SCALE_1            0x0e000000
+#define AR9300_PAPRD_SCALE_1_S          25
+#define AR9300_PAPRD_SCALE_2            0x70000000
+#define AR9300_PAPRD_SCALE_2_S          28
 
 /* Delta from which to start power to pdadc table */
 /* This offset is used in both open loop and closed loop power control
@@ -71,14 +62,20 @@
  */
 #define AR9300_PWR_TABLE_OFFSET  0
 
-/* enable flags for voltage and temp compensation */
-#define ENABLE_TEMP_COMPENSATION 0x01
-#define ENABLE_VOLT_COMPENSATION 0x02
 /* byte addressable */
 #define AR9300_EEPROM_SIZE (16*1024)
-#define FIXED_CCA_THRESHOLD 15
 
+#define AR9300_BASE_ADDR_4K 0xfff
 #define AR9300_BASE_ADDR 0x3ff
+#define AR9300_BASE_ADDR_512 0x1ff
+
+#define AR9300_OTP_BASE                 0x14000
+#define AR9300_OTP_STATUS               0x15f18
+#define AR9300_OTP_STATUS_TYPE          0x7
+#define AR9300_OTP_STATUS_VALID         0x4
+#define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
+#define AR9300_OTP_STATUS_SM_BUSY       0x1
+#define AR9300_OTP_READ_DATA            0x15f1c
 
 enum targetPowerHTRates {
         HT_TARGET_RATE_0_8_16,
@@ -216,7 +213,7 @@ struct ar9300_modal_eep_header {
         int8_t tempSlope;
         int8_t voltSlope;
         /* spur channels in usual fbin coding format */
-        u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
+        u8 spurChans[AR_EEPROM_MODAL_SPURS];
         /* 3  Check if the register is per chain */
         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
         u8 ob[AR9300_MAX_CHAINS];
@@ -236,7 +233,7 @@ struct ar9300_modal_eep_header {
         u8 thresh62;
         __le32 papdRateMaskHt20;
         __le32 papdRateMaskHt40;
-        u8 futureModal[24];
+        u8 futureModal[10];
 } __packed;
 
 struct ar9300_cal_data_per_freq_op_loop {
@@ -261,17 +258,26 @@ struct cal_tgt_pow_ht {
         u8 tPow2x[14];
 } __packed;
 
-struct cal_ctl_edge_pwr {
-        u8 tPower:6,
-           flag:2;
-} __packed;
-
 struct cal_ctl_data_2g {
-        struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_2G];
+        u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
 } __packed;
 
 struct cal_ctl_data_5g {
-        struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+        u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+} __packed;
+
+struct ar9300_BaseExtension_1 {
+        u8 ant_div_control;
+        u8 future[13];
+} __packed;
+
+struct ar9300_BaseExtension_2 {
+        int8_t    tempSlopeLow;
+        int8_t    tempSlopeHigh;
+        u8   xatten1DBLow[AR9300_MAX_CHAINS];
+        u8   xatten1MarginLow[AR9300_MAX_CHAINS];
+        u8   xatten1DBHigh[AR9300_MAX_CHAINS];
+        u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
 } __packed;
 
 struct ar9300_eeprom {
@@ -283,6 +289,7 @@ struct ar9300_eeprom {
         struct ar9300_base_eep_hdr baseEepHeader;
 
         struct ar9300_modal_eep_header modalHeader2G;
+        struct ar9300_BaseExtension_1 base_ext1;
         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
         struct ar9300_cal_data_per_freq_op_loop
          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
@@ -302,6 +309,7 @@ struct ar9300_eeprom {
         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
         struct ar9300_modal_eep_header modalHeader5G;
+        struct ar9300_BaseExtension_2 base_ext2;
         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
         struct ar9300_cal_data_per_freq_op_loop
          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
@@ -322,4 +330,8 @@ struct ar9300_eeprom {
 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
 
+u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
+
+unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+                                           struct ath9k_channel *chan);
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 064168909108..392bf0f8ff16 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,174 +16,203 @@
 
 #include "hw.h"
 #include "ar9003_mac.h"
-#include "ar9003_2p0_initvals.h"
 #include "ar9003_2p2_initvals.h"
+#include "ar9485_initvals.h"
+#include "ar9340_initvals.h"
 
 /* General hardware code for the AR9003 hadware family */
 
-static bool ar9003_hw_macversion_supported(u32 macversion)
-{
-        switch (macversion) {
-        case AR_SREV_VERSION_9300:
-                return true;
-        default:
-                break;
-        }
-        return false;
-}
-
-/* AR9003 2.0 */
-static void ar9003_2p0_hw_init_mode_regs(struct ath_hw *ah)
-{
-        /* mac */
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ar9300_2p0_mac_core,
-                       ARRAY_SIZE(ar9300_2p0_mac_core), 2);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
-                       ar9300_2p0_mac_postamble,
-                       ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
-
-        /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
-                       ar9300_2p0_baseband_core,
-                       ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
-                       ar9300_2p0_baseband_postamble,
-                       ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
-
-        /* radio */
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
-                       ar9300_2p0_radio_core,
-                       ARRAY_SIZE(ar9300_2p0_radio_core), 2);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
-                       ar9300_2p0_radio_postamble,
-                       ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
-
-        /* soc */
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-                       ar9300_2p0_soc_preamble,
-                       ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
-                       ar9300_2p0_soc_postamble,
-                       ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
-
-        /* rx/tx gain */
-        INIT_INI_ARRAY(&ah->iniModesRxGain,
-                       ar9300Common_rx_gain_table_2p0,
-                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
-        INIT_INI_ARRAY(&ah->iniModesTxGain,
-                       ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
-                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
-                       5);
-
-        /* Load PCIE SERDES settings from INI */
-
-        /* Awake Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                       ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
-                       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
-                       2);
-
-        /* Sleep Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                       ar9300PciePhy_clkreq_enable_L1_2p0,
-                       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
-                       2);
-
-        /* Fast clock modal settings */
-        INIT_INI_ARRAY(&ah->iniModesAdditional,
-                       ar9300Modes_fast_clock_2p0,
-                       ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
-                       3);
-}
-
-/* AR9003 2.2 */
-static void ar9003_2p2_hw_init_mode_regs(struct ath_hw *ah)
-{
-        /* mac */
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ar9300_2p2_mac_core,
-                       ARRAY_SIZE(ar9300_2p2_mac_core), 2);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
-                       ar9300_2p2_mac_postamble,
-                       ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
-
-        /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
-                       ar9300_2p2_baseband_core,
-                       ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
-                       ar9300_2p2_baseband_postamble,
-                       ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
-
-        /* radio */
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
-                       ar9300_2p2_radio_core,
-                       ARRAY_SIZE(ar9300_2p2_radio_core), 2);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
-                       ar9300_2p2_radio_postamble,
-                       ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
-
-        /* soc */
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-                       ar9300_2p2_soc_preamble,
-                       ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
-                       ar9300_2p2_soc_postamble,
-                       ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
-
-        /* rx/tx gain */
-        INIT_INI_ARRAY(&ah->iniModesRxGain,
-                       ar9300Common_rx_gain_table_2p2,
-                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
-        INIT_INI_ARRAY(&ah->iniModesTxGain,
-                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
-                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
-                       5);
-
-        /* Load PCIE SERDES settings from INI */
-
-        /* Awake Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                       ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
-                       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
-                       2);
-
-        /* Sleep Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                       ar9300PciePhy_clkreq_enable_L1_2p2,
-                       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
-                       2);
-
-        /* Fast clock modal settings */
-        INIT_INI_ARRAY(&ah->iniModesAdditional,
-                       ar9300Modes_fast_clock_2p2,
-                       ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
-                       3);
-}
-
 /*
  * The AR9003 family uses a new INI format (pre, core, post
- * arrays per subsystem).
+ * arrays per subsystem). This provides support for the
+ * AR9003 2.2 chipsets.
  */
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-        if (AR_SREV_9300_20(ah))
-                ar9003_2p0_hw_init_mode_regs(ah);
-        else
-                ar9003_2p2_hw_init_mode_regs(ah);
+        if (AR_SREV_9340(ah)) {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9340_1p0_mac_core,
+                                ARRAY_SIZE(ar9340_1p0_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9340_1p0_mac_postamble,
+                                ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9340_1p0_baseband_core,
+                                ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9340_1p0_baseband_postamble,
+                                ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9340_1p0_radio_core,
+                                ARRAY_SIZE(ar9340_1p0_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9340_1p0_radio_postamble,
+                                ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9340_1p0_soc_preamble,
+                                ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ar9340_1p0_soc_postamble,
+                                ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9340Common_wo_xlna_rx_gain_table_1p0,
+                                ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+                                5);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9340Modes_high_ob_db_tx_gain_table_1p0,
+                                ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+                                5);
+
+                INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                ar9340Modes_fast_clock_1p0,
+                                ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
+                                3);
+
+                INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
+                                ar9340_1p0_radio_core_40M,
+                                ARRAY_SIZE(ar9340_1p0_radio_core_40M),
+                                2);
+        } else if (AR_SREV_9485_11(ah)) {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9485_1_1_mac_core,
+                                ARRAY_SIZE(ar9485_1_1_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9485_1_1_mac_postamble,
+                                ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
+                                ARRAY_SIZE(ar9485_1_1), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9485_1_1_baseband_core,
+                                ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9485_1_1_baseband_postamble,
+                                ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9485_1_1_radio_core,
+                                ARRAY_SIZE(ar9485_1_1_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9485_1_1_radio_postamble,
+                                ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9485_1_1_soc_preamble,
+                                ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9485Common_wo_xlna_rx_gain_1_1,
+                                ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9485_modes_lowest_ob_db_tx_gain_1_1,
+                                ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+                                5);
+
+                /* Load PCIE SERDES settings from INI */
+
+                /* Awake Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9485_1_1_pcie_phy_clkreq_disable_L1,
+                                ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+                                2);
+
+                /* Sleep Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9485_1_1_pcie_phy_clkreq_disable_L1,
+                                ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+                                2);
+        } else {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9300_2p2_mac_core,
+                                ARRAY_SIZE(ar9300_2p2_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9300_2p2_mac_postamble,
+                                ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9300_2p2_baseband_core,
+                                ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9300_2p2_baseband_postamble,
+                                ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9300_2p2_radio_core,
+                                ARRAY_SIZE(ar9300_2p2_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9300_2p2_radio_postamble,
+                                ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9300_2p2_soc_preamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ar9300_2p2_soc_postamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9300Common_rx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+                                5);
+
+                /* Load PCIE SERDES settings from INI */
+
+                /* Awake Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                2);
+
+                /* Sleep Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                2);
+
+                /* Fast clock modal settings */
+                INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                ar9300Modes_fast_clock_2p2,
+                                ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+                                3);
+        }
 }
 
 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
@@ -191,10 +220,15 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
         switch (ar9003_hw_get_tx_gain_idx(ah)) {
         case 0:
         default:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
-                                       ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
+                                       ar9485_modes_lowest_ob_db_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
                                        5);
                 else
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -203,10 +237,15 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                        5);
                 break;
         case 1:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
-                                       ar9300Modes_high_ob_db_tx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
+                                       ar9485Modes_high_ob_db_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
                                        5);
                 else
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -215,10 +254,15 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                        5);
                 break;
         case 2:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
-                                       ar9300Modes_low_ob_db_tx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
+                                       ar9485Modes_low_ob_db_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
                                        5);
                 else
                         INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -226,6 +270,23 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                        ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
                                        5);
                 break;
+        case 3:
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+                                       5);
+                else if (AR_SREV_9485_11(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9485Modes_high_power_tx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
+                                       5);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9300Modes_high_power_tx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
+                                       5);
+                break;
         }
 }
 
@@ -234,10 +295,15 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
         switch (ar9003_hw_get_rx_gain_idx(ah)) {
         case 0:
         default:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9340Common_rx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
+                                       2);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
-                                       ar9300Common_rx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
+                                       ar9485Common_wo_xlna_rx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
                                        2);
                 else
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -246,10 +312,15 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
                                        2);
                 break;
         case 1:
-                if (AR_SREV_9300_20(ah))
+                if (AR_SREV_9340(ah))
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9340Common_wo_xlna_rx_gain_table_1p0,
+                                       ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+                                       2);
+                else if (AR_SREV_9485_11(ah))
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
-                                       ar9300Common_wo_xlna_rx_gain_table_2p0,
-                                       ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
+                                       ar9485Common_wo_xlna_rx_gain_1_1,
+                                       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
                                        2);
                 else
                         INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -326,13 +397,10 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
 
         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
-        priv_ops->macversion_supported = ar9003_hw_macversion_supported;
 
         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 
         ar9003_hw_attach_phy_ops(ah);
         ar9003_hw_attach_calib_ops(ah);
         ar9003_hw_attach_mac_ops(ah);
-
-        ath9k_hw_attach_ani_ops_new(ah);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 5b995bee70ae..10d71f7d3fc2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -182,10 +182,10 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 }
 
                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
 
-                        REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
+                REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 
         }
@@ -237,73 +237,76 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                  struct ath_tx_status *ts)
 {
         struct ar9003_txs *ads;
+        u32 status;
 
         ads = &ah->ts_ring[ah->ts_tail];
 
-        if ((ads->status8 & AR_TxDone) == 0)
+        status = ACCESS_ONCE(ads->status8);
+        if ((status & AR_TxDone) == 0)
                 return -EINPROGRESS;
 
         ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
 
         if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
             (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                          "Tx Descriptor error %x\n", ads->ds_info);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                        "Tx Descriptor error %x\n", ads->ds_info);
                 memset(ads, 0, sizeof(*ads));
                 return -EIO;
         }
 
+        if (status & AR_TxOpExceeded)
+                ts->ts_status |= ATH9K_TXERR_XTXOP;
+        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
+        ts->ts_seqnum = MS(status, AR_SeqNum);
+        ts->tid = MS(status, AR_TxTid);
+
         ts->qid = MS(ads->ds_info, AR_TxQcuNum);
         ts->desc_id = MS(ads->status1, AR_TxDescId);
-        ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
         ts->ts_tstamp = ads->status4;
         ts->ts_status = 0;
         ts->ts_flags  = 0;
 
-        if (ads->status3 & AR_ExcessiveRetries)
+        status = ACCESS_ONCE(ads->status2);
+        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
+        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
+        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
+        if (status & AR_TxBaStatus) {
+                ts->ts_flags |= ATH9K_TX_BA;
+                ts->ba_low = ads->status5;
+                ts->ba_high = ads->status6;
+        }
+
+        status = ACCESS_ONCE(ads->status3);
+        if (status & AR_ExcessiveRetries)
                 ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->status3 & AR_Filtered)
+        if (status & AR_Filtered)
                 ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->status3 & AR_FIFOUnderrun) {
+        if (status & AR_FIFOUnderrun) {
                 ts->ts_status |= ATH9K_TXERR_FIFO;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status8 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->status3 & AR_TxTimerExpired)
+        if (status & AR_TxTimerExpired)
                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->status3 & AR_DescCfgErr)
+        if (status & AR_DescCfgErr)
                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->status3 & AR_TxDataUnderrun) {
+        if (status & AR_TxDataUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status3 & AR_TxDelimUnderrun) {
+        if (status & AR_TxDelimUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status2 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->status5;
-                ts->ba_high = ads->status6;
-        }
-
-        ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
-
-        ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
-        ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
-        ts->ts_antenna = 0;
+        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
+        ts->ts_longretry = MS(status, AR_DataFailCnt);
+        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
-        ts->tid = MS(ads->status8, AR_TxTid);
+        status = ACCESS_ONCE(ads->status7);
+        ts->ts_rssi = MS(status, AR_TxRSSICombined);
+        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
+        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
+        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
         memset(ads, 0, sizeof(*ads));
 
@@ -319,7 +322,6 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         if (txpower > ah->txpower_limit)
                 txpower = ah->txpower_limit;
 
-        txpower += ah->txpower_indexoffset;
         if (txpower > 63)
                 txpower = 63;
 
@@ -327,7 +329,6 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
                 | SM(txpower, AR_XmitPower)
                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
-                | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
                 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
 
@@ -348,6 +349,16 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         ads->ctl22 = 0;
 }
 
+static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
+{
+        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
+
+        if (val)
+                ads->ctl11 |= AR_ClrDestMask;
+        else
+                ads->ctl11 &= ~AR_ClrDestMask;
+}
+
 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
                                           void *lastds,
                                           u32 durUpdateEn, u32 rtsctsRate,
@@ -407,12 +418,36 @@ static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
                                         u32 aggrLen)
 {
+#define FIRST_DESC_NDELIMS 60
         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
 
         ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
 
-        ads->ctl17 &= ~AR_AggrLen;
-        ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+        if (ah->ent_mode & AR_ENT_OTP_MPSD) {
+                u32 ctl17, ndelim;
+                /*
+                 * Add delimiter when using RTS/CTS with aggregation
+                 * and non enterprise AR9003 card
+                 */
+                ctl17 = ads->ctl17;
+                ndelim = MS(ctl17, AR_PadDelim);
+
+                if (ndelim < FIRST_DESC_NDELIMS) {
+                        aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
+                        ndelim = FIRST_DESC_NDELIMS;
+                }
+
+                ctl17 &= ~AR_AggrLen;
+                ctl17 |= SM(aggrLen, AR_AggrLen);
+
+                ctl17 &= ~AR_PadDelim;
+                ctl17 |= SM(ndelim, AR_PadDelim);
+
+                ads->ctl17 = ctl17;
+        } else {
+                ads->ctl17 &= ~AR_AggrLen;
+                ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+        }
 }
 
 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
@@ -449,27 +484,6 @@ static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
         ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
 }
 
-static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
-                                           u32 burstDuration)
-{
-        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
-
-        ads->ctl13 &= ~AR_BurstDur;
-        ads->ctl13 |= SM(burstDuration, AR_BurstDur);
-
-}
-
-static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
-                                             u32 vmf)
-{
-        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
-
-        if (vmf)
-                ads->ctl11 |=  AR_VirtMoreFrag;
-        else
-                ads->ctl11 &= ~AR_VirtMoreFrag;
-}
-
 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
 {
         struct ar9003_txc *ads = ds;
@@ -494,8 +508,7 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
         ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
         ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
         ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
-        ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
-        ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
+        ops->set_clrdmask = ar9003_hw_set_clrdmask;
 }
 
 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
@@ -587,9 +600,9 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
                  * possibly be reviewing the last subframe. AR_CRCErr
                  * is the CRC of the actual data.
                  */
-                if (rxsp->status11 & AR_CRCErr) {
+                if (rxsp->status11 & AR_CRCErr)
                         rxs->rs_status |= ATH9K_RXERR_CRC;
-                } else if (rxsp->status11 & AR_PHYErr) {
+                else if (rxsp->status11 & AR_PHYErr) {
                         phyerr = MS(rxsp->status11, AR_PHYErrCode);
                         /*
                          * If we reach a point here where AR_PostDelimCRCErr is
@@ -612,11 +625,13 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
                                 rxs->rs_phyerr = phyerr;
                         }
 
-                } else if (rxsp->status11 & AR_DecryptCRCErr) {
+                } else if (rxsp->status11 & AR_DecryptCRCErr)
                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
-                } else if (rxsp->status11 & AR_MichaelErr) {
+                else if (rxsp->status11 & AR_MichaelErr)
                         rxs->rs_status |= ATH9K_RXERR_MIC;
-                }
+
+                if (rxsp->status11 & AR_KeyMiss)
+                        rxs->rs_status |= ATH9K_RXERR_DECRYPT;
         }
 
         return 0;
@@ -630,10 +645,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
         memset((void *) ah->ts_ring, 0,
                 ah->ts_size * sizeof(struct ar9003_txs));
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                  "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
-                   ah->ts_paddr_start, ah->ts_paddr_end,
-                   ah->ts_ring, ah->ts_size);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
+                ah->ts_paddr_start, ah->ts_paddr_end,
+                ah->ts_ring, ah->ts_size);
 
         REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
         REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
index 9f2cea70a840..c50449387bf1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -65,7 +65,7 @@ struct ar9003_rxs {
         u32 status9;
         u32 status10;
         u32 status11;
-} __packed;
+} __packed __aligned(4);
 
 /* Transmit Control Descriptor */
 struct ar9003_txc {
@@ -93,7 +93,7 @@ struct ar9003_txc {
         u32 ctl21;  /* DMA control 21 */
         u32 ctl22;  /* DMA control 22 */
         u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
-} __packed;
+} __packed __aligned(4);
 
 struct ar9003_txs {
         u32 ds_info;
@@ -105,7 +105,7 @@ struct ar9003_txs {
         u32 status6;
         u32 status7;
         u32 status8;
-} __packed;
+} __packed __aligned(4);
 
 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 7c38229ba670..e4d6a87ec538 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,45 +19,124 @@
 
 void ar9003_paprd_enable(struct ath_hw *ah, bool val)
 {
+        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+        struct ath9k_channel *chan = ah->curchan;
+
+        if (val) {
+                ah->paprd_table_write_done = true;
+
+                ah->eep_ops->set_txpower(ah, chan,
+                                ath9k_regd_get_ctl(regulatory, chan),
+                                chan->chan->max_antenna_gain * 2,
+                                chan->chan->max_power * 2,
+                                min((u32) MAX_RATE_POWER,
+                                (u32) regulatory->power_limit), false);
+        }
+
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
                       AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
-                      AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
-                      AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
+                              AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
+                              AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
 }
 EXPORT_SYMBOL(ar9003_paprd_enable);
 
-static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
+static int ar9003_get_training_power_2g(struct ath_hw *ah)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        struct ar9300_modal_eep_header *hdr = &eep->modalHeader2G;
+        unsigned int power, scale, delta;
+
+        scale = MS(le32_to_cpu(hdr->papdRateMaskHt20), AR9300_PAPRD_SCALE_1);
+        power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
+                               AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
+
+        delta = abs((int) ah->paprd_target_power - (int) power);
+        if (delta > scale)
+                return -1;
+
+        if (delta < 4)
+                power -= 4 - delta;
+
+        return power;
+}
+
+static int ar9003_get_training_power_5g(struct ath_hw *ah)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
-        struct ar9300_modal_eep_header *hdr;
-        const u32 ctrl0[3] = {
+        struct ar9300_modal_eep_header *hdr = &eep->modalHeader5G;
+        struct ath9k_channel *chan = ah->curchan;
+        unsigned int power, scale, delta;
+
+        if (chan->channel >= 5700)
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt20),
+                           AR9300_PAPRD_SCALE_1);
+        else if (chan->channel >= 5400)
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
+                           AR9300_PAPRD_SCALE_2);
+        else
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
+                           AR9300_PAPRD_SCALE_1);
+
+        if (IS_CHAN_HT40(chan))
+                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
+                        AR_PHY_POWERTX_RATE8_POWERTXHT40_5);
+        else
+                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE6,
+                        AR_PHY_POWERTX_RATE6_POWERTXHT20_5);
+
+        power += scale;
+        delta = abs((int) ah->paprd_target_power - (int) power);
+        if (delta > scale)
+                return -1;
+
+        power += 2 * get_streams(common->tx_chainmask);
+        return power;
+}
+
+static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        static const u32 ctrl0[3] = {
                 AR_PHY_PAPRD_CTRL0_B0,
                 AR_PHY_PAPRD_CTRL0_B1,
                 AR_PHY_PAPRD_CTRL0_B2
         };
-        const u32 ctrl1[3] = {
+        static const u32 ctrl1[3] = {
                 AR_PHY_PAPRD_CTRL1_B0,
                 AR_PHY_PAPRD_CTRL1_B1,
                 AR_PHY_PAPRD_CTRL1_B2
         };
-        u32 am_mask, ht40_mask;
+        int training_power;
         int i;
 
-        if (ah->curchan && IS_CHAN_5GHZ(ah->curchan))
-                hdr = &eep->modalHeader5G;
+        if (IS_CHAN_2GHZ(ah->curchan))
+                training_power = ar9003_get_training_power_2g(ah);
         else
-                hdr = &eep->modalHeader2G;
-
-        am_mask = le32_to_cpu(hdr->papdRateMaskHt20);
-        ht40_mask = le32_to_cpu(hdr->papdRateMaskHt40);
+                training_power = ar9003_get_training_power_5g(ah);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, am_mask);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
-
-        for (i = 0; i < 3; i++) {
+        if (training_power < 0) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "PAPRD target power delta out of range");
+                return -ERANGE;
+        }
+        ah->paprd_training_power = training_power;
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "Training power: %d, Target power: %d\n",
+                ah->paprd_training_power, ah->paprd_target_power);
+
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
+                      ah->paprd_ratemask);
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
+                      ah->paprd_ratemask);
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
+                      ah->paprd_ratemask_ht40);
+
+        for (i = 0; i < ah->caps.max_txchains; i++) {
                 REG_RMW_FIELD(ah, ctrl0[i],
                               AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1);
                 REG_RMW_FIELD(ah, ctrl1[i],
@@ -102,8 +181,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
-                      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6);
+        if (AR_SREV_9485(ah))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+                              AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+                              -3);
+        else
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+                              AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+                              -6);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
                       -15);
@@ -132,6 +217,7 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
                       AR_PHY_PAPRD_PRE_POST_SCALING, 185706);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
                       AR_PHY_PAPRD_PRE_POST_SCALING, 175487);
+        return 0;
 }
 
 static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
@@ -347,6 +433,10 @@ static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
             (((Y[6] - Y[3]) * 1 << scale_factor) +
              (x_est[6] - x_est[3])) / (x_est[6] - x_est[3]);
 
+        /* prevent division by zero */
+        if (G_fxp == 0)
+                return false;
+
         Y_intercept =
             (G_fxp * (x_est[0] - x_est[3]) +
              (1 << scale_factor)) / (1 << scale_factor) + Y[3];
@@ -356,14 +446,12 @@ static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
 
         for (i = 0; i <= 3; i++) {
                 y_est[i] = i * 32;
-
-                /* prevent division by zero */
-                if (G_fxp == 0)
-                        return false;
-
                 x_est[i] = ((y_est[i] * 1 << scale_factor) + G_fxp) / G_fxp;
         }
 
+        if (y_est[max_index] == 0)
+                return false;
+
         x_est_fxp1_nonlin =
             x_est[max_index] - ((1 << scale_factor) * y_est[max_index] +
                                 G_fxp) / G_fxp;
@@ -457,6 +545,8 @@ static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
 
         Q_scale_B = find_proper_scale(find_expn(abs(scale_B)), 10);
         scale_B = scale_B / (1 << Q_scale_B);
+        if (scale_B == 0)
+                return false;
         Q_beta = find_proper_scale(find_expn(abs(beta_raw)), 10);
         Q_alpha = find_proper_scale(find_expn(abs(alpha_raw)), 10);
         beta_raw = beta_raw / (1 << Q_beta);
@@ -582,15 +672,10 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
 {
         u32 *paprd_table_val = caldata->pa_table[chain];
         u32 small_signal_gain = caldata->small_signal_gain[chain];
-        u32 training_power;
+        u32 training_power = ah->paprd_training_power;
         u32 reg = 0;
         int i;
 
-        training_power =
-            REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
-                           AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
-        training_power -= 4;
-
         if (chain == 0)
                 reg = AR_PHY_PAPRD_MEM_TAB_B0;
         else if (chain == 1)
@@ -616,26 +701,22 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
                       AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
                       training_power);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
-                      AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
-                      training_power);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
+                              AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
+                              training_power);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
-                      AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
-                      training_power);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
+                              AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
+                              training_power);
 }
 EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
 
 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
 {
-
         unsigned int i, desired_gain, gain_index;
-        unsigned int train_power;
-
-        train_power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
-                                     AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
-
-        train_power = train_power - 4;
+        unsigned int train_power = ah->paprd_training_power;
 
         desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
 
@@ -701,7 +782,12 @@ EXPORT_SYMBOL(ar9003_paprd_create_curve);
 
 int ar9003_paprd_init_table(struct ath_hw *ah)
 {
-        ar9003_paprd_setup_single_table(ah);
+        int ret;
+
+        ret = ar9003_paprd_setup_single_table(ah);
+        if (ret < 0)
+            return ret;
+
         ar9003_paprd_get_gain_table(ah);
         return 0;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index a491854fa38a..892c48b15434 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -75,13 +75,42 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
         freq = centers.synth_center;
 
         if (freq < 4800) {     /* 2 GHz, fractional mode */
-                channelSel = CHANSEL_2G(freq);
+                if (AR_SREV_9485(ah)) {
+                        u32 chan_frac;
+
+                        /*
+                         * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
+                         * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
+                         * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
+                         */
+                        channelSel = (freq * 4) / 120;
+                        chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
+                        channelSel = (channelSel << 17) | chan_frac;
+                } else if (AR_SREV_9340(ah)) {
+                        if (ah->is_clk_25mhz) {
+                                u32 chan_frac;
+
+                                channelSel = (freq * 2) / 75;
+                                chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
+                                channelSel = (channelSel << 17) | chan_frac;
+                        } else
+                                channelSel = CHANSEL_2G(freq) >> 1;
+                } else
+                        channelSel = CHANSEL_2G(freq);
                 /* Set to 2G mode */
                 bMode = 1;
         } else {
-                channelSel = CHANSEL_5G(freq);
-                /* Doubler is ON, so, divide channelSel by 2. */
-                channelSel >>= 1;
+                if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
+                        u32 chan_frac;
+
+                        channelSel = (freq * 2) / 75;
+                        chan_frac = ((freq % 75) * 0x20000) / 75;
+                        channelSel = (channelSel << 17) | chan_frac;
+                } else {
+                        channelSel = CHANSEL_5G(freq);
+                        /* Doubler is ON, so, divide channelSel by 2. */
+                        channelSel >>= 1;
+                }
                 /* Set to 5G mode */
                 bMode = 0;
         }
@@ -128,24 +157,53 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
                                             struct ath9k_channel *chan)
 {
-        u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
+        static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
         int cur_bb_spur, negative = 0, cck_spur_freq;
         int i;
+        int range, max_spur_cnts, synth_freq;
+        u8 *spur_fbin_ptr = NULL;
 
         /*
          * Need to verify range +/- 10 MHz in control channel, otherwise spur
          * is out-of-band and can be ignored.
          */
 
-        for (i = 0; i < 4; i++) {
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
+                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
+                                                         IS_CHAN_2GHZ(chan));
+                if (spur_fbin_ptr[0] == 0) /* No spur */
+                        return;
+                max_spur_cnts = 5;
+                if (IS_CHAN_HT40(chan)) {
+                        range = 19;
+                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                                           AR_PHY_GC_DYN2040_PRI_CH) == 0)
+                                synth_freq = chan->channel + 10;
+                        else
+                                synth_freq = chan->channel - 10;
+                } else {
+                        range = 10;
+                        synth_freq = chan->channel;
+                }
+        } else {
+                range = 10;
+                max_spur_cnts = 4;
+                synth_freq = chan->channel;
+        }
+
+        for (i = 0; i < max_spur_cnts; i++) {
                 negative = 0;
-                cur_bb_spur = spur_freq[i] - chan->channel;
+                if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
+                                        IS_CHAN_2GHZ(chan)) - synth_freq;
+                else
+                        cur_bb_spur = spur_freq[i] - synth_freq;
 
                 if (cur_bb_spur < 0) {
                         negative = 1;
                         cur_bb_spur = -cur_bb_spur;
                 }
-                if (cur_bb_spur < 10) {
+                if (cur_bb_spur < range) {
                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 
                         if (negative == 1)
@@ -369,7 +427,7 @@ static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 
         ar9003_hw_spur_ofdm_clear(ah);
 
-        for (i = 0; spurChansPtr[i] && i < 5; i++) {
+        for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
                 if (abs(freq_offset) < range) {
                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
@@ -487,7 +545,11 @@ void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
                 break;
         }
 
-        REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+        if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
+                REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
+        else
+                REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+
         if (tx == 0x5) {
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                             AR_PHY_SWAP_ALT_CHAIN);
@@ -542,10 +604,7 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
                 u32 reg = INI_RA(iniArr, i, 0);
                 u32 val = INI_RA(iniArr, i, column);
 
-                if (reg >= 0x16000 && reg < 0x17000)
-                        ath9k_hw_analog_shift_regwrite(ah, reg, val);
-                else
-                        REG_WRITE(ah, reg, val);
+                REG_WRITE(ah, reg, val);
 
                 DO_DELAY(regWrites);
         }
@@ -557,29 +616,25 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         unsigned int regWrites = 0, i;
         struct ieee80211_channel *channel = chan->chan;
-        u32 modesIndex, freqIndex;
+        u32 modesIndex;
 
         switch (chan->chanmode) {
         case CHANNEL_A:
         case CHANNEL_A_HT20:
                 modesIndex = 1;
-                freqIndex = 1;
                 break;
         case CHANNEL_A_HT40PLUS:
         case CHANNEL_A_HT40MINUS:
                 modesIndex = 2;
-                freqIndex = 1;
                 break;
         case CHANNEL_G:
         case CHANNEL_G_HT20:
         case CHANNEL_B:
                 modesIndex = 4;
-                freqIndex = 2;
                 break;
         case CHANNEL_G_HT40PLUS:
         case CHANNEL_G_HT40MINUS:
                 modesIndex = 3;
-                freqIndex = 2;
                 break;
 
         default:
@@ -604,6 +659,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                 modesIndex, regWrites);
 
+        if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
+                REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
+
         ar9003_hw_override_ini(ah);
         ar9003_hw_set_channel_regs(ah, chan);
         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
@@ -614,7 +672,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), false);
 
         return 0;
 }
@@ -712,28 +770,6 @@ static void ar9003_hw_rfbus_done(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-/*
- * Set the interrupt and GPIO values so the ISR can disable RF
- * on a switch signal.  Assumes GPIO port and interrupt polarity
- * are set prior to call.
- */
-static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
-{
-        /* Connect rfsilent_bb_l to baseband */
-        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-        /* Set input mux for rfsilent_bb_l to GPIO #0 */
-        REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                    AR_GPIO_INPUT_MUX2_RFSILENT);
-
-        /*
-         * Configure the desired GPIO port for input and
-         * enable baseband rf silence.
-         */
-        ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-        REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 {
         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
@@ -747,9 +783,9 @@ static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                   enum ath9k_ani_cmd cmd, int param)
 {
-        struct ar5416AniState *aniState = ah->curani;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
+        struct ar5416AniState *aniState = &chan->ani;
         s32 value, value2;
 
         switch (cmd & ah->ani_function) {
@@ -820,12 +856,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                 if (!on != aniState->ofdmWeakSigDetectOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: ofdm weak signal: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->ofdmWeakSigDetectOff ?
-                                        "on" : "off",
-                                  on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: ofdm weak signal: %s=>%s\n",
+                                chan->channel,
+                                !aniState->ofdmWeakSigDetectOff ?
+                                "on" : "off",
+                                on ? "on" : "off");
                         if (on)
                                 ah->stats.ast_ani_ofdmon++;
                         else
@@ -838,11 +874,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_FIRSTEP_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep_table));
                         return false;
                 }
 
@@ -877,24 +911,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 
                 if (level != aniState->firstepLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.firstep);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep_low[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.firstepLow);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value,
+                                aniState->iniDef.firstep);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value2,
+                                aniState->iniDef.firstepLow);
                         if (level > aniState->firstepLevel)
                                 ah->stats.ast_ani_stepup++;
                         else if (level < aniState->firstepLevel)
@@ -907,11 +939,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1_table));
                         return false;
                 }
                 /*
@@ -945,24 +975,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                               AR_PHY_EXT_CYCPWR_THR1, value2);
 
                 if (level != aniState->spurImmunityLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.cycpwrThr1);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1Ext[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.cycpwrThr1Ext);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value,
+                                aniState->iniDef.cycpwrThr1);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value2,
+                                aniState->iniDef.cycpwrThr1Ext);
                         if (level > aniState->spurImmunityLevel)
                                 ah->stats.ast_ani_spurup++;
                         else if (level < aniState->spurImmunityLevel)
@@ -982,11 +1010,11 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
                               AR_PHY_MRC_CCK_MUX_REG, is_on);
                 if (!is_on != aniState->mrcCCKOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: MRC CCK: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->mrcCCKOff ? "on" : "off",
-                                  is_on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: MRC CCK: %s=>%s\n",
+                                chan->channel,
+                                !aniState->mrcCCKOff ? "on" : "off",
+                                is_on ? "on" : "off");
                 if (is_on)
                         ah->stats.ast_ani_ccklow++;
                 else
@@ -998,52 +1026,48 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                  "MRCcck=%s listenTime=%d CC=%d listen=%d "
-                  "ofdmErrs=%d cckErrs=%d\n",
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
-                  aniState->firstepLevel,
-                  !aniState->mrcCCKOff ? "on" : "off",
-                  aniState->listenTime,
-                  aniState->cycleCount,
-                  aniState->listenTime,
-                  aniState->ofdmPhyErrCount,
-                  aniState->cckPhyErrCount);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+                aniState->firstepLevel,
+                !aniState->mrcCCKOff ? "on" : "off",
+                aniState->listenTime,
+                aniState->ofdmPhyErrCount,
+                aniState->cckPhyErrCount);
         return true;
 }
 
 static void ar9003_hw_do_getnf(struct ath_hw *ah,
                               int16_t nfarray[NUM_NF_READINGS])
 {
-        int16_t nf;
-
-        nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+#define AR_PHY_CH_MINCCA_PWR    0x1FF00000
+#define AR_PHY_CH_MINCCA_PWR_S  20
+#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
+#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
 
-        nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
-
-        nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
-        nfarray[2] = sign_extend(nf, 9);
-
-        if (!IS_CHAN_HT40(ah->curchan))
-                return;
+        int16_t nf;
+        int i;
 
-        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-        nfarray[3] = sign_extend(nf, 9);
+        for (i = 0; i < AR9300_MAX_CHAINS; i++) {
+                if (ah->rxchainmask & BIT(i)) {
+                        nf = MS(REG_READ(ah, ah->nf_regs[i]),
+                                         AR_PHY_CH_MINCCA_PWR);
+                        nfarray[i] = sign_extend32(nf, 8);
 
-        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
-        nfarray[4] = sign_extend(nf, 9);
+                        if (IS_CHAN_HT40(ah->curchan)) {
+                                u8 ext_idx = AR9300_MAX_CHAINS + i;
 
-        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
-        nfarray[5] = sign_extend(nf, 9);
+                                nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
+                                                 AR_PHY_CH_EXT_MINCCA_PWR);
+                                nfarray[ext_idx] = sign_extend32(nf, 8);
+                        }
+                }
+        }
 }
 
 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
@@ -1067,21 +1091,18 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
         struct ath9k_ani_default *iniDef;
-        int index;
         u32 val;
 
-        index = ath9k_hw_get_ani_channel_idx(ah, chan);
-        aniState = &ah->ani[index];
-        ah->curani = aniState;
+        aniState = &ah->curchan->ani;
         iniDef = &aniState->iniDef;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
-                  ah->hw_version.macVersion,
-                  ah->hw_version.macRev,
-                  ah->opmode,
-                  chan->channel,
-                  chan->channelFlags);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+                ah->hw_version.macVersion,
+                ah->hw_version.macRev,
+                ah->opmode,
+                chan->channel,
+                chan->channelFlags);
 
         val = REG_READ(ah, AR_PHY_SFCORR);
         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1116,14 +1137,100 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
+}
+
+static void ar9003_hw_set_radar_params(struct ath_hw *ah,
+                                       struct ath_hw_radar_conf *conf)
+{
+        u32 radar_0 = 0, radar_1 = 0;
+
+        if (!conf) {
+                REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+                return;
+        }
+
+        radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+        radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+        radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+        radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+        radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+        radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+        radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+        radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+        radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+        radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+        radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+        REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+        REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+        if (conf->ext_channel)
+                REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+        else
+                REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
+{
+        struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+        conf->fir_power = -28;
+        conf->radar_rssi = 0;
+        conf->pulse_height = 10;
+        conf->pulse_rssi = 24;
+        conf->pulse_inband = 8;
+        conf->pulse_maxlen = 255;
+        conf->pulse_inband_step = 12;
+        conf->radar_inband = 8;
+}
+
+static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+        antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
+                                  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
+        antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
+                                 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
+        antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
+                                  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
+        antconf->lna1_lna2_delta = -9;
+        antconf->div_group = 2;
+}
 
-        aniState->cycleCount = 0;
+static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                   struct ath_hw_antcomb_conf *antconf)
+{
+        u32 regval;
+
+        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+        regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                    AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                    AR_PHY_9485_ANT_FAST_DIV_BIAS |
+                    AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
+                    AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+        regval |= ((antconf->main_lna_conf <<
+                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
+                   & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
+        regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
+                   & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
+        regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
+                   & AR_PHY_9485_ANT_FAST_DIV_BIAS);
+        regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
+                   & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
+        regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
+                   & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+
+        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 }
 
 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        const u32 ar9300_cca_regs[6] = {
+        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
+        static const u32 ar9300_cca_regs[6] = {
                 AR_PHY_CCA_0,
                 AR_PHY_CCA_1,
                 AR_PHY_CCA_2,
@@ -1143,13 +1250,17 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
-        priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
         priv_ops->set_diversity = ar9003_hw_set_diversity;
         priv_ops->ani_control = ar9003_hw_ani_control;
         priv_ops->do_getnf = ar9003_hw_do_getnf;
         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
+        priv_ops->set_radar_params = ar9003_hw_set_radar_params;
+
+        ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
+        ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
 
         ar9003_hw_set_nf_limits(ah);
+        ar9003_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
 }
 
@@ -1172,7 +1283,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
                             AR_PHY_WATCHDOG_IDLE_ENABLE));
 
-                ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
+                ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
                 return;
         }
 
@@ -1208,9 +1319,9 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
                   AR_PHY_WATCHDOG_IDLE_MASK |
                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
 
-        ath_print(common, ATH_DBG_RESET,
-                  "Enabled BB Watchdog timeout (%u ms)\n",
-                  idle_tmo_ms);
+        ath_dbg(common, ATH_DBG_RESET,
+                "Enabled BB Watchdog timeout (%u ms)\n",
+                idle_tmo_ms);
 }
 
 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
@@ -1232,42 +1343,63 @@ void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status;
+        u32 status;
 
         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
                 return;
 
         status = ah->bb_watchdog_last_status;
-        ath_print(common, ATH_DBG_RESET,
-                  "\n==== BB update: BB status=0x%08x ====\n", status);
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
-                  "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
-                  MS(status, AR_PHY_WATCHDOG_INFO),
-                  MS(status, AR_PHY_WATCHDOG_DET_HANG),
-                  MS(status, AR_PHY_WATCHDOG_RADAR_SM),
-                  MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
-                  MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
-                  MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
-                  MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
-                  MS(status, AR_PHY_WATCHDOG_AGC_SM),
-                  MS(status,AR_PHY_WATCHDOG_SRCH_SM));
-
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
-                  REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
-                  REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB mode: BB_gen_controls=0x%08x **\n",
-                  REG_READ(ah, AR_PHY_GEN_CTRL));
-
-        if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt))
-                ath_print(common, ATH_DBG_RESET,
-                          "** BB busy times: rx_clear=%d%%, "
-                          "rx_frame=%d%%, tx_frame=%d%% **\n",
-                          rxc_pcnt, rxf_pcnt, txf_pcnt);
-
-        ath_print(common, ATH_DBG_RESET,
-                  "==== BB update: done ====\n\n");
+        ath_dbg(common, ATH_DBG_RESET,
+                "\n==== BB update: BB status=0x%08x ====\n", status);
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
+                MS(status, AR_PHY_WATCHDOG_INFO),
+                MS(status, AR_PHY_WATCHDOG_DET_HANG),
+                MS(status, AR_PHY_WATCHDOG_RADAR_SM),
+                MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
+                MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
+                MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
+                MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
+                MS(status, AR_PHY_WATCHDOG_AGC_SM),
+                MS(status, AR_PHY_WATCHDOG_SRCH_SM));
+
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
+                REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
+                REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB mode: BB_gen_controls=0x%08x **\n",
+                REG_READ(ah, AR_PHY_GEN_CTRL));
+
+#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
+        if (common->cc_survey.cycles)
+                ath_dbg(common, ATH_DBG_RESET,
+                        "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
+                        PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
+
+        ath_dbg(common, ATH_DBG_RESET,
+                "==== BB update: done ====\n\n");
 }
 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
+
+void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
+{
+        u32 val;
+
+        /* While receiving unsupported rate frame rx state machine
+         * gets into a state 0xb and if phy_restart happens in that
+         * state, BB would go hang. If RXSM is in 0xb state after
+         * first bb panic, ensure to disable the phy_restart.
+         */
+        if (!((MS(ah->bb_watchdog_last_status,
+                  AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
+            ah->bb_hang_rx_ofdm))
+                return;
+
+        ah->bb_hang_rx_ofdm = true;
+        val = REG_READ(ah, AR_PHY_RESTART);
+        val &= ~AR_PHY_RESTART_ENA;
+
+        REG_WRITE(ah, AR_PHY_RESTART, val);
+}
+EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 3394dfe52b42..443090d278e3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002-2010 Atheros Communications, Inc.
+ * Copyright (c) 2010-2011 Atheros Communications, Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -260,7 +260,35 @@
 #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
 #define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
 #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
+
+/*
+ * Antenna Diversity  settings
+ */
 #define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)
+#define AR_ANT_DIV_CTRL_ALL     0x7e000000
+#define AR_ANT_DIV_CTRL_ALL_S   25
+#define AR_ANT_DIV_ENABLE       0x1000000
+#define AR_ANT_DIV_ENABLE_S     24
+
+
+#define AR_PHY_9485_ANT_FAST_DIV_BIAS                   0x00007e00
+#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9
+#define AR_PHY_9485_ANT_DIV_LNADIV                      0x01000000
+#define AR_PHY_9485_ANT_DIV_LNADIV_S                    24
+#define AR_PHY_9485_ANT_DIV_ALT_LNACONF                 0x06000000
+#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S               25
+#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF                0x18000000
+#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S              27
+#define AR_PHY_9485_ANT_DIV_ALT_GAINTB                  0x20000000
+#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S                29
+#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB                 0x40000000
+#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S               30
+
+#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2             0x0
+#define AR_PHY_9485_ANT_DIV_LNA2                        0x1
+#define AR_PHY_9485_ANT_DIV_LNA1                        0x2
+#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2              0x3
+
 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
 #define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
@@ -271,7 +299,11 @@
 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
 #define AR_PHY_RSSI_0           (AR_AGC_BASE + 0x180)
 #define AR_PHY_SPUR_CCK_REP0    (AR_AGC_BASE + 0x184)
+
 #define AR_PHY_CCK_DETECT       (AR_AGC_BASE + 0x1c0)
+#define AR_FAST_DIV_ENABLE      0x2000
+#define AR_FAST_DIV_ENABLE_S    13
+
 #define AR_PHY_DAG_CTRLCCK      (AR_AGC_BASE + 0x1c4)
 #define AR_PHY_IQCORR_CTRL_CCK  (AR_AGC_BASE + 0x1c8)
 
@@ -476,6 +508,8 @@
 #define AR_PHY_HEAVYCLIP_40      (AR_SM_BASE + 0x1ac)
 #define AR_PHY_ILLEGAL_TXRATE    (AR_SM_BASE + 0x1b0)
 
+#define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
+
 #define AR_PHY_PWRTX_MAX         (AR_SM_BASE + 0x1f0)
 #define AR_PHY_POWER_TX_SUB      (AR_SM_BASE + 0x1f4)
 
@@ -536,10 +570,15 @@
 
 #define AR_PHY_TXGAIN_TABLE      (AR_SM_BASE + 0x300)
 
-#define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + 0x448)
-#define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + 0x440)
-#define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0    (AR_SM_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + AR_SREV_9485(ah) ? \
+                                                 0x3c8 : 0x448)
+#define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + AR_SREV_9485(ah) ? \
+                                                 0x3c4 : 0x440)
+#define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + AR_SREV_9485(ah) ? \
+                                                 0x3f0 : 0x48c)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i)    (AR_SM_BASE + \
+                                             (AR_SREV_9485(ah) ? \
+                                              0x3d0 : 0x450) + ((_i) << 2))
 
 #define AR_PHY_WATCHDOG_STATUS      (AR_SM_BASE + 0x5c0)
 #define AR_PHY_WATCHDOG_CTL_1       (AR_SM_BASE + 0x5c4)
@@ -568,7 +607,7 @@
 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
 #define AR_PHY_65NM_CH0_BIAS4       0x160cc
 #define AR_PHY_65NM_CH0_RXTX4       0x1610c
-#define AR_PHY_65NM_CH0_THERM       0x16290
+#define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 : 0x1628c)
 
 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
@@ -584,6 +623,24 @@
 #define AR_PHY_65NM_CH2_RXTX1       0x16900
 #define AR_PHY_65NM_CH2_RXTX2       0x16904
 
+#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
+#define AR_CH0_TOP2_XPABIASLVL          0xf000
+#define AR_CH0_TOP2_XPABIASLVL_S        12
+
+#define AR_CH0_XTAL             (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
+#define AR_CH0_XTAL_CAPINDAC    0x7f000000
+#define AR_CH0_XTAL_CAPINDAC_S  24
+#define AR_CH0_XTAL_CAPOUTDAC   0x00fe0000
+#define AR_CH0_XTAL_CAPOUTDAC_S 17
+
+#define AR_PHY_PMU1             0x16c40
+#define AR_PHY_PMU1_PWD         0x1
+#define AR_PHY_PMU1_PWD_S       0
+
+#define AR_PHY_PMU2             0x16c44
+#define AR_PHY_PMU2_PGM         0x00200000
+#define AR_PHY_PMU2_PGM_S       21
+
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT          0x00380000
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S        19
 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT          0x00c00000
@@ -683,6 +740,7 @@
 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN    0x00000001
 #define AR_PHY_TXGAIN_FORCE               0x00000001
+#define AR_PHY_TXGAIN_FORCE_S             0
 #define AR_PHY_TXGAIN_FORCED_PADVGNRA     0x00003c00
 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S   10
 #define AR_PHY_TXGAIN_FORCED_PADVGNRB     0x0003c000
@@ -719,14 +777,19 @@
 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT   0x01000000
 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR      0x00000004
-#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
-#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
-#define AR_PHY_TX_IQCAL_START_DO_CAL        0x00000001
-#define AR_PHY_TX_IQCAL_START_DO_CAL_S      0
+#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
+#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
+#define AR_PHY_TX_IQCAL_START_DO_CAL        0x00000001
+#define AR_PHY_TX_IQCAL_START_DO_CAL_S      0
 
 #define AR_PHY_TX_IQCAL_STATUS_FAILED    0x00000001
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x00003fff
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    0
+#define AR_PHY_CALIBRATED_GAINS_0        0x3e
+#define AR_PHY_CALIBRATED_GAINS_0_S      1
+
+#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE      0x00003fff
+#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S    0
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x0fffc000
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    14
 
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
@@ -785,7 +848,7 @@
 #define AR_PHY_TPC_11_B1         (AR_SM1_BASE + 0x220)
 #define AR_PHY_PDADC_TAB_1       (AR_SM1_BASE + 0x240)
 #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1    (AR_SM1_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM_BASE + 0x450 + ((_i) << 2))
 
 /*
  * Channel 2 Register Map
@@ -838,7 +901,7 @@
 #define AR_PHY_TPC_11_B2         (AR_SM2_BASE + 0x220)
 #define AR_PHY_PDADC_TAB_2       (AR_SM2_BASE + 0x240)
 #define AR_PHY_TX_IQCAL_STATUS_B2   (AR_SM2_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2    (AR_SM2_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i)    (AR_SM2_BASE + 0x450 + ((_i) << 2))
 
 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED    0x00000001
 
@@ -945,7 +1008,9 @@
 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT         0x0ffe0000
 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S       17
 
-#define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + 0x490)
+#define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x580 : 0x490))
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE     0x00000001
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S   0
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING       0x0000007e
@@ -961,11 +1026,15 @@
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP             0x0003f000
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S           12
 
-#define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + 0x494)
+#define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x584 : 0x494))
 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN     0xFFFFFFFF
 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S   0
 
-#define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + 0x498)
+#define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x588 : 0x498))
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE    0x0000003f
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S  0
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP          0x00000fc0
@@ -981,7 +1050,9 @@
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE     0x20000000
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S   29
 
-#define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + 0x49c)
+#define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x58c : 0x49c))
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES   0x03ff0000
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA        0x0000f000
@@ -1040,6 +1111,14 @@
 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0      0x3F
 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S    0
 
+#define AR_PHY_POWERTX_RATE6                    (AR_SM_BASE + 0x1d4)
+#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5      0x3F00
+#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S    8
+
+#define AR_PHY_POWERTX_RATE8                    (AR_SM_BASE + 0x1dc)
+#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5      0x3F00
+#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S    8
+
 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
 
 #endif  /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
index d3375fc4ce8b..815a8af1beef 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -14,26 +14,20 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#ifndef INITVALS_9003_2P0_H
-#define INITVALS_9003_2P0_H
+#ifndef INITVALS_9340_H
+#define INITVALS_9340_H
 
-/* AR9003 2.0 */
-
-static const u32 ar9300_2p0_radio_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-        {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
-        {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
-        {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
-        {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
-        {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
-        {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+static const u32 ar9340_1p0_radio_postamble[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+        {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
+        {0x0001610c, 0x08000000, 0x08000000, 0x00000000, 0x00000000},
+        {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
+        {0x0001650c, 0x08000000, 0x08000000, 0x00000000, 0x00000000},
+        {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
 };
 
-static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
+        /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -99,19 +93,14 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
-        {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
-        {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016448, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
-        {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016848, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
-        {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 };
 
-static const u32 ar9300Modes_fast_clock_2p0[][3] = {
-        /* Addr      5G_HT20     5G_HT40   */
+static const u32 ar9340Modes_fast_clock_1p0[][3] = {
+        /*  Addr      5G_HT20     5G_HT40  */
         {0x00001030, 0x00000268, 0x000004d0},
         {0x00001070, 0x0000018c, 0x00000318},
         {0x000010b0, 0x00000fd0, 0x00001fa0},
@@ -123,46 +112,49 @@ static const u32 ar9300Modes_fast_clock_2p0[][3] = {
         {0x0000a254, 0x00000898, 0x00001130},
 };
 
-static const u32 ar9300_2p0_radio_core[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_radio_core[][2] = {
+        /*  Addr     allmodes  */
         {0x00016000, 0x36db6db6},
         {0x00016004, 0x6db6db40},
         {0x00016008, 0x73f00000},
         {0x0001600c, 0x00000000},
         {0x00016040, 0x7f80fff8},
-        {0x0001604c, 0x76d005b5},
-        {0x00016050, 0x556cf031},
-        {0x00016054, 0x13449440},
-        {0x00016058, 0x0c51c92c},
-        {0x0001605c, 0x3db7fffc},
-        {0x00016060, 0xfffffffc},
-        {0x00016064, 0x000f0278},
-        {0x0001606c, 0x6db60000},
-        {0x00016080, 0x00000000},
+        {0x00016044, 0x03b6d2db},
+        {0x00016048, 0x24925266},
+        {0x0001604c, 0x000f0278},
+        {0x00016050, 0x6db6db6c},
+        {0x00016054, 0x6db60000},
+        {0x00016080, 0x00080000},
         {0x00016084, 0x0e48048c},
-        {0x00016088, 0x54214514},
-        {0x0001608c, 0x119f481e},
+        {0x00016088, 0x14214514},
+        {0x0001608c, 0x119f081c},
         {0x00016090, 0x24926490},
-        {0x00016098, 0xd2888888},
-        {0x000160a0, 0x0a108ffe},
+        {0x00016094, 0x00000000},
+        {0x00016098, 0xd411eb84},
+        {0x0001609c, 0x03e47f32},
+        {0x000160a0, 0xc2108ffe},
         {0x000160a4, 0x812fc370},
         {0x000160a8, 0x423c8000},
-        {0x000160b4, 0x92480080},
-        {0x000160c0, 0x00adb6d0},
+        {0x000160ac, 0xa4646800},
+        {0x000160b0, 0x00fe7f46},
+        {0x000160b4, 0x92480000},
+        {0x000160c0, 0x006db6db},
         {0x000160c4, 0x6db6db60},
         {0x000160c8, 0x6db6db6c},
-        {0x000160cc, 0x01e6c000},
-        {0x00016100, 0x3fffbe01},
+        {0x000160cc, 0x6de6db6c},
+        {0x000160d0, 0xb6da4924},
+        {0x00016100, 0x04cb0001},
         {0x00016104, 0xfff80000},
         {0x00016108, 0x00080010},
-        {0x00016144, 0x02084080},
-        {0x00016148, 0x00000000},
-        {0x00016280, 0x058a0001},
-        {0x00016284, 0x3d840208},
-        {0x00016288, 0x05a20408},
-        {0x0001628c, 0x00038c07},
-        {0x00016290, 0x40000004},
-        {0x00016294, 0x458aa14f},
+        {0x0001610c, 0x00000000},
+        {0x00016140, 0x50804008},
+        {0x00016144, 0x01884080},
+        {0x00016148, 0x000080c0},
+        {0x00016280, 0x01000015},
+        {0x00016284, 0x05530000},
+        {0x00016288, 0x00318000},
+        {0x0001628c, 0x50000000},
+        {0x00016290, 0x4080294f},
         {0x00016380, 0x00000000},
         {0x00016384, 0x00000000},
         {0x00016388, 0x00800700},
@@ -190,19 +182,18 @@ static const u32 ar9300_2p0_radio_core[][2] = {
         {0x00016408, 0x73f00000},
         {0x0001640c, 0x00000000},
         {0x00016440, 0x7f80fff8},
-        {0x0001644c, 0x76d005b5},
-        {0x00016450, 0x556cf031},
-        {0x00016454, 0x13449440},
-        {0x00016458, 0x0c51c92c},
-        {0x0001645c, 0x3db7fffc},
-        {0x00016460, 0xfffffffc},
-        {0x00016464, 0x000f0278},
-        {0x0001646c, 0x6db60000},
-        {0x00016500, 0x3fffbe01},
+        {0x00016444, 0x03b6d2db},
+        {0x00016448, 0x24927266},
+        {0x0001644c, 0x000f0278},
+        {0x00016450, 0x6db6db6c},
+        {0x00016454, 0x6db60000},
+        {0x00016500, 0x04cb0001},
         {0x00016504, 0xfff80000},
         {0x00016508, 0x00080010},
-        {0x00016544, 0x02084080},
-        {0x00016548, 0x00000000},
+        {0x0001650c, 0x00000000},
+        {0x00016540, 0x50804008},
+        {0x00016544, 0x01884080},
+        {0x00016548, 0x000080c0},
         {0x00016780, 0x00000000},
         {0x00016784, 0x00000000},
         {0x00016788, 0x00800700},
@@ -225,310 +216,16 @@ static const u32 ar9300_2p0_radio_core[][2] = {
         {0x000167cc, 0x00001402},
         {0x000167d0, 0x00000000},
         {0x000167d4, 0x00000000},
-        {0x00016800, 0x36db6db6},
-        {0x00016804, 0x6db6db40},
-        {0x00016808, 0x73f00000},
-        {0x0001680c, 0x00000000},
-        {0x00016840, 0x7f80fff8},
-        {0x0001684c, 0x76d005b5},
-        {0x00016850, 0x556cf031},
-        {0x00016854, 0x13449440},
-        {0x00016858, 0x0c51c92c},
-        {0x0001685c, 0x3db7fffc},
-        {0x00016860, 0xfffffffc},
-        {0x00016864, 0x000f0278},
-        {0x0001686c, 0x6db60000},
-        {0x00016900, 0x3fffbe01},
-        {0x00016904, 0xfff80000},
-        {0x00016908, 0x00080010},
-        {0x00016944, 0x02084080},
-        {0x00016948, 0x00000000},
-        {0x00016b80, 0x00000000},
-        {0x00016b84, 0x00000000},
-        {0x00016b88, 0x00800700},
-        {0x00016b8c, 0x00800700},
-        {0x00016b90, 0x00800700},
-        {0x00016b94, 0x00000000},
-        {0x00016b98, 0x00000000},
-        {0x00016b9c, 0x00000000},
-        {0x00016ba0, 0x00000001},
-        {0x00016ba4, 0x00000001},
-        {0x00016ba8, 0x00000000},
-        {0x00016bac, 0x00000000},
-        {0x00016bb0, 0x00000000},
-        {0x00016bb4, 0x00000000},
-        {0x00016bb8, 0x00000000},
-        {0x00016bbc, 0x00000000},
-        {0x00016bc0, 0x000000a0},
-        {0x00016bc4, 0x000c0000},
-        {0x00016bc8, 0x14021402},
-        {0x00016bcc, 0x00001402},
-        {0x00016bd0, 0x00000000},
-        {0x00016bd4, 0x00000000},
 };
 
-static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x0000a000, 0x02000101},
-        {0x0000a004, 0x02000102},
-        {0x0000a008, 0x02000103},
-        {0x0000a00c, 0x02000104},
-        {0x0000a010, 0x02000200},
-        {0x0000a014, 0x02000201},
-        {0x0000a018, 0x02000202},
-        {0x0000a01c, 0x02000203},
-        {0x0000a020, 0x02000204},
-        {0x0000a024, 0x02000205},
-        {0x0000a028, 0x02000208},
-        {0x0000a02c, 0x02000302},
-        {0x0000a030, 0x02000303},
-        {0x0000a034, 0x02000304},
-        {0x0000a038, 0x02000400},
-        {0x0000a03c, 0x02010300},
-        {0x0000a040, 0x02010301},
-        {0x0000a044, 0x02010302},
-        {0x0000a048, 0x02000500},
-        {0x0000a04c, 0x02010400},
-        {0x0000a050, 0x02020300},
-        {0x0000a054, 0x02020301},
-        {0x0000a058, 0x02020302},
-        {0x0000a05c, 0x02020303},
-        {0x0000a060, 0x02020400},
-        {0x0000a064, 0x02030300},
-        {0x0000a068, 0x02030301},
-        {0x0000a06c, 0x02030302},
-        {0x0000a070, 0x02030303},
-        {0x0000a074, 0x02030400},
-        {0x0000a078, 0x02040300},
-        {0x0000a07c, 0x02040301},
-        {0x0000a080, 0x02040302},
-        {0x0000a084, 0x02040303},
-        {0x0000a088, 0x02030500},
-        {0x0000a08c, 0x02040400},
-        {0x0000a090, 0x02050203},
-        {0x0000a094, 0x02050204},
-        {0x0000a098, 0x02050205},
-        {0x0000a09c, 0x02040500},
-        {0x0000a0a0, 0x02050301},
-        {0x0000a0a4, 0x02050302},
-        {0x0000a0a8, 0x02050303},
-        {0x0000a0ac, 0x02050400},
-        {0x0000a0b0, 0x02050401},
-        {0x0000a0b4, 0x02050402},
-        {0x0000a0b8, 0x02050403},
-        {0x0000a0bc, 0x02050500},
-        {0x0000a0c0, 0x02050501},
-        {0x0000a0c4, 0x02050502},
-        {0x0000a0c8, 0x02050503},
-        {0x0000a0cc, 0x02050504},
-        {0x0000a0d0, 0x02050600},
-        {0x0000a0d4, 0x02050601},
-        {0x0000a0d8, 0x02050602},
-        {0x0000a0dc, 0x02050603},
-        {0x0000a0e0, 0x02050604},
-        {0x0000a0e4, 0x02050700},
-        {0x0000a0e8, 0x02050701},
-        {0x0000a0ec, 0x02050702},
-        {0x0000a0f0, 0x02050703},
-        {0x0000a0f4, 0x02050704},
-        {0x0000a0f8, 0x02050705},
-        {0x0000a0fc, 0x02050708},
-        {0x0000a100, 0x02050709},
-        {0x0000a104, 0x0205070a},
-        {0x0000a108, 0x0205070b},
-        {0x0000a10c, 0x0205070c},
-        {0x0000a110, 0x0205070d},
-        {0x0000a114, 0x02050710},
-        {0x0000a118, 0x02050711},
-        {0x0000a11c, 0x02050712},
-        {0x0000a120, 0x02050713},
-        {0x0000a124, 0x02050714},
-        {0x0000a128, 0x02050715},
-        {0x0000a12c, 0x02050730},
-        {0x0000a130, 0x02050731},
-        {0x0000a134, 0x02050732},
-        {0x0000a138, 0x02050733},
-        {0x0000a13c, 0x02050734},
-        {0x0000a140, 0x02050735},
-        {0x0000a144, 0x02050750},
-        {0x0000a148, 0x02050751},
-        {0x0000a14c, 0x02050752},
-        {0x0000a150, 0x02050753},
-        {0x0000a154, 0x02050754},
-        {0x0000a158, 0x02050755},
-        {0x0000a15c, 0x02050770},
-        {0x0000a160, 0x02050771},
-        {0x0000a164, 0x02050772},
-        {0x0000a168, 0x02050773},
-        {0x0000a16c, 0x02050774},
-        {0x0000a170, 0x02050775},
-        {0x0000a174, 0x00000776},
-        {0x0000a178, 0x00000776},
-        {0x0000a17c, 0x00000776},
-        {0x0000a180, 0x00000776},
-        {0x0000a184, 0x00000776},
-        {0x0000a188, 0x00000776},
-        {0x0000a18c, 0x00000776},
-        {0x0000a190, 0x00000776},
-        {0x0000a194, 0x00000776},
-        {0x0000a198, 0x00000776},
-        {0x0000a19c, 0x00000776},
-        {0x0000a1a0, 0x00000776},
-        {0x0000a1a4, 0x00000776},
-        {0x0000a1a8, 0x00000776},
-        {0x0000a1ac, 0x00000776},
-        {0x0000a1b0, 0x00000776},
-        {0x0000a1b4, 0x00000776},
-        {0x0000a1b8, 0x00000776},
-        {0x0000a1bc, 0x00000776},
-        {0x0000a1c0, 0x00000776},
-        {0x0000a1c4, 0x00000776},
-        {0x0000a1c8, 0x00000776},
-        {0x0000a1cc, 0x00000776},
-        {0x0000a1d0, 0x00000776},
-        {0x0000a1d4, 0x00000776},
-        {0x0000a1d8, 0x00000776},
-        {0x0000a1dc, 0x00000776},
-        {0x0000a1e0, 0x00000776},
-        {0x0000a1e4, 0x00000776},
-        {0x0000a1e8, 0x00000776},
-        {0x0000a1ec, 0x00000776},
-        {0x0000a1f0, 0x00000776},
-        {0x0000a1f4, 0x00000776},
-        {0x0000a1f8, 0x00000776},
-        {0x0000a1fc, 0x00000776},
-        {0x0000b000, 0x02000101},
-        {0x0000b004, 0x02000102},
-        {0x0000b008, 0x02000103},
-        {0x0000b00c, 0x02000104},
-        {0x0000b010, 0x02000200},
-        {0x0000b014, 0x02000201},
-        {0x0000b018, 0x02000202},
-        {0x0000b01c, 0x02000203},
-        {0x0000b020, 0x02000204},
-        {0x0000b024, 0x02000205},
-        {0x0000b028, 0x02000208},
-        {0x0000b02c, 0x02000302},
-        {0x0000b030, 0x02000303},
-        {0x0000b034, 0x02000304},
-        {0x0000b038, 0x02000400},
-        {0x0000b03c, 0x02010300},
-        {0x0000b040, 0x02010301},
-        {0x0000b044, 0x02010302},
-        {0x0000b048, 0x02000500},
-        {0x0000b04c, 0x02010400},
-        {0x0000b050, 0x02020300},
-        {0x0000b054, 0x02020301},
-        {0x0000b058, 0x02020302},
-        {0x0000b05c, 0x02020303},
-        {0x0000b060, 0x02020400},
-        {0x0000b064, 0x02030300},
-        {0x0000b068, 0x02030301},
-        {0x0000b06c, 0x02030302},
-        {0x0000b070, 0x02030303},
-        {0x0000b074, 0x02030400},
-        {0x0000b078, 0x02040300},
-        {0x0000b07c, 0x02040301},
-        {0x0000b080, 0x02040302},
-        {0x0000b084, 0x02040303},
-        {0x0000b088, 0x02030500},
-        {0x0000b08c, 0x02040400},
-        {0x0000b090, 0x02050203},
-        {0x0000b094, 0x02050204},
-        {0x0000b098, 0x02050205},
-        {0x0000b09c, 0x02040500},
-        {0x0000b0a0, 0x02050301},
-        {0x0000b0a4, 0x02050302},
-        {0x0000b0a8, 0x02050303},
-        {0x0000b0ac, 0x02050400},
-        {0x0000b0b0, 0x02050401},
-        {0x0000b0b4, 0x02050402},
-        {0x0000b0b8, 0x02050403},
-        {0x0000b0bc, 0x02050500},
-        {0x0000b0c0, 0x02050501},
-        {0x0000b0c4, 0x02050502},
-        {0x0000b0c8, 0x02050503},
-        {0x0000b0cc, 0x02050504},
-        {0x0000b0d0, 0x02050600},
-        {0x0000b0d4, 0x02050601},
-        {0x0000b0d8, 0x02050602},
-        {0x0000b0dc, 0x02050603},
-        {0x0000b0e0, 0x02050604},
-        {0x0000b0e4, 0x02050700},
-        {0x0000b0e8, 0x02050701},
-        {0x0000b0ec, 0x02050702},
-        {0x0000b0f0, 0x02050703},
-        {0x0000b0f4, 0x02050704},
-        {0x0000b0f8, 0x02050705},
-        {0x0000b0fc, 0x02050708},
-        {0x0000b100, 0x02050709},
-        {0x0000b104, 0x0205070a},
-        {0x0000b108, 0x0205070b},
-        {0x0000b10c, 0x0205070c},
-        {0x0000b110, 0x0205070d},
-        {0x0000b114, 0x02050710},
-        {0x0000b118, 0x02050711},
-        {0x0000b11c, 0x02050712},
-        {0x0000b120, 0x02050713},
-        {0x0000b124, 0x02050714},
-        {0x0000b128, 0x02050715},
-        {0x0000b12c, 0x02050730},
-        {0x0000b130, 0x02050731},
-        {0x0000b134, 0x02050732},
-        {0x0000b138, 0x02050733},
-        {0x0000b13c, 0x02050734},
-        {0x0000b140, 0x02050735},
-        {0x0000b144, 0x02050750},
-        {0x0000b148, 0x02050751},
-        {0x0000b14c, 0x02050752},
-        {0x0000b150, 0x02050753},
-        {0x0000b154, 0x02050754},
-        {0x0000b158, 0x02050755},
-        {0x0000b15c, 0x02050770},
-        {0x0000b160, 0x02050771},
-        {0x0000b164, 0x02050772},
-        {0x0000b168, 0x02050773},
-        {0x0000b16c, 0x02050774},
-        {0x0000b170, 0x02050775},
-        {0x0000b174, 0x00000776},
-        {0x0000b178, 0x00000776},
-        {0x0000b17c, 0x00000776},
-        {0x0000b180, 0x00000776},
-        {0x0000b184, 0x00000776},
-        {0x0000b188, 0x00000776},
-        {0x0000b18c, 0x00000776},
-        {0x0000b190, 0x00000776},
-        {0x0000b194, 0x00000776},
-        {0x0000b198, 0x00000776},
-        {0x0000b19c, 0x00000776},
-        {0x0000b1a0, 0x00000776},
-        {0x0000b1a4, 0x00000776},
-        {0x0000b1a8, 0x00000776},
-        {0x0000b1ac, 0x00000776},
-        {0x0000b1b0, 0x00000776},
-        {0x0000b1b4, 0x00000776},
-        {0x0000b1b8, 0x00000776},
-        {0x0000b1bc, 0x00000776},
-        {0x0000b1c0, 0x00000776},
-        {0x0000b1c4, 0x00000776},
-        {0x0000b1c8, 0x00000776},
-        {0x0000b1cc, 0x00000776},
-        {0x0000b1d0, 0x00000776},
-        {0x0000b1d4, 0x00000776},
-        {0x0000b1d8, 0x00000776},
-        {0x0000b1dc, 0x00000776},
-        {0x0000b1e0, 0x00000776},
-        {0x0000b1e4, 0x00000776},
-        {0x0000b1e8, 0x00000776},
-        {0x0000b1ec, 0x00000776},
-        {0x0000b1f0, 0x00000776},
-        {0x0000b1f4, 0x00000776},
-        {0x0000b1f8, 0x00000776},
-        {0x0000b1fc, 0x00000776},
+static const u32 ar9340_1p0_radio_core_40M[][2] = {
+        {0x0001609c, 0x02566f3a},
+        {0x000160ac, 0xa4647c00},
+        {0x000160b0, 0x01885f5a},
 };
 
-static const u32 ar9300_2p0_mac_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340_1p0_mac_postamble[][5] = {
+        /* Addr       5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
         {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
         {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
         {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
@@ -539,66 +236,24 @@ static const u32 ar9300_2p0_mac_postamble[][5] = {
         {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
 };
 
-static const u32 ar9300_2p0_soc_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340_1p0_soc_postamble[][5] = {
+        /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
 };
 
-static const u32 ar9200_merlin_2p0_radio_core[][2] = {
-        /* Addr      allmodes  */
-        {0x00007800, 0x00040000},
-        {0x00007804, 0xdb005012},
-        {0x00007808, 0x04924914},
-        {0x0000780c, 0x21084210},
-        {0x00007810, 0x6d801300},
-        {0x00007814, 0x0019beff},
-        {0x00007818, 0x07e41000},
-        {0x0000781c, 0x00392000},
-        {0x00007820, 0x92592480},
-        {0x00007824, 0x00040000},
-        {0x00007828, 0xdb005012},
-        {0x0000782c, 0x04924914},
-        {0x00007830, 0x21084210},
-        {0x00007834, 0x6d801300},
-        {0x00007838, 0x0019beff},
-        {0x0000783c, 0x07e40000},
-        {0x00007840, 0x00392000},
-        {0x00007844, 0x92592480},
-        {0x00007848, 0x00100000},
-        {0x0000784c, 0x773f0567},
-        {0x00007850, 0x54214514},
-        {0x00007854, 0x12035828},
-        {0x00007858, 0x92592692},
-        {0x0000785c, 0x00000000},
-        {0x00007860, 0x56400000},
-        {0x00007864, 0x0a8e370e},
-        {0x00007868, 0xc0102850},
-        {0x0000786c, 0x812d4000},
-        {0x00007870, 0x807ec400},
-        {0x00007874, 0x001b6db0},
-        {0x00007878, 0x00376b63},
-        {0x0000787c, 0x06db6db6},
-        {0x00007880, 0x006d8000},
-        {0x00007884, 0xffeffffe},
-        {0x00007888, 0xffeffffe},
-        {0x0000788c, 0x00010000},
-        {0x00007890, 0x02060aeb},
-        {0x00007894, 0x5a108000},
-};
-
-static const u32 ar9300_2p0_baseband_postamble[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340_1p0_baseband_postamble[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
-        {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
+        {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
         {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
         {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
         {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
-        {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
         {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
-        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
+        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e},
         {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
@@ -607,7 +262,7 @@ static const u32 ar9300_2p0_baseband_postamble[][5] = {
         {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27},
         {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
         {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
-        {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
+        {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
         {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
         {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
         {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
@@ -619,33 +274,27 @@ static const u32 ar9300_2p0_baseband_postamble[][5] = {
         {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
         {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
         {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
-        {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
-        {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
+        {0x0000a288, 0x00000220, 0x00000220, 0x00000110, 0x00000110},
+        {0x0000a28c, 0x00011111, 0x00011111, 0x00022222, 0x00022222},
         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
         {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
         {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000ae04, 0x00180000, 0x00180000, 0x00180000, 0x00180000},
         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
         {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
-        {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
-        {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
-        {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
-        {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
 };
 
-static const u32 ar9300_2p0_baseband_core[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_baseband_core[][2] = {
+        /*  Addr     allmodes  */
         {0x00009800, 0xafe68e30},
         {0x00009804, 0xfd14e000},
         {0x00009808, 0x9c0a9f6b},
         {0x0000980c, 0x04900000},
-        {0x00009814, 0x9280c00a},
+        {0x00009814, 0xb280c00a},
         {0x00009818, 0x00000000},
         {0x0000981c, 0x00020028},
         {0x00009834, 0x5f3ca3de},
@@ -794,7 +443,7 @@ static const u32 ar9300_2p0_baseband_core[][2] = {
         {0x0000a7cc, 0x00000000},
         {0x0000a7d0, 0x00000000},
         {0x0000a7d4, 0x00000004},
-        {0x0000a7dc, 0x00000001},
+        {0x0000a7dc, 0x00000000},
         {0x0000a8d0, 0x004b6a8e},
         {0x0000a8d4, 0x00000820},
         {0x0000a8dc, 0x00000000},
@@ -813,28 +462,10 @@ static const u32 ar9300_2p0_baseband_core[][2] = {
         {0x0000b408, 0x0e79e5c0},
         {0x0000b40c, 0x00820820},
         {0x0000b420, 0x00000000},
-        {0x0000b8d0, 0x004b6a8e},
-        {0x0000b8d4, 0x00000820},
-        {0x0000b8dc, 0x00000000},
-        {0x0000b8f0, 0x00000000},
-        {0x0000b8f4, 0x00000000},
-        {0x0000c2d0, 0x00000080},
-        {0x0000c2d4, 0x00000000},
-        {0x0000c2dc, 0x00000000},
-        {0x0000c2e0, 0x00000000},
-        {0x0000c2e4, 0x00000000},
-        {0x0000c2e8, 0x00000000},
-        {0x0000c2ec, 0x00000000},
-        {0x0000c2f0, 0x00000000},
-        {0x0000c2f4, 0x00000000},
-        {0x0000c2f8, 0x00000000},
-        {0x0000c408, 0x0e79e5c0},
-        {0x0000c40c, 0x00820820},
-        {0x0000c420, 0x00000000},
 };
 
-static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -900,19 +531,14 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
-        {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
-        {0x00016048, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
-        {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
-        {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
-        {0x00016448, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
-        {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
-        {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
-        {0x00016848, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
-        {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 };
 
-static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
+        /*  Addr       5G_HT20    5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -978,19 +604,87 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
         {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
-        {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
-        {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
-        {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
-        {0x00016448, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
-        {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
-        {0x00016848, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
-        {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+        {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016048, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266},
+        {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016448, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266},
+};
+static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
+        /*  Addr      5G_HT20      5G_HT40     2G_HT40    2G_HT20  */
+        {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+        {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+        {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
+        {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
+        {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
+        {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
+        {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
+        {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
+        {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
+        {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
+        {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
+        {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
+        {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
+        {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
+        {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
+        {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
+        {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
+        {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
+        {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+        {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+        {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
+        {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
+        {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
+        {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
+        {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
+        {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+        {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+        {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
+        {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
+        {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
+        {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
+        {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
+        {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
+        {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
+        {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
+        {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
+        {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
+        {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
+        {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
+        {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
+        {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
+        {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
+        {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
+        {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
+        {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
+        {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
+        {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
+        {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
+        {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
+        {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
+        {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
+        {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+        {0x00016044, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db},
+        {0x00016048, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266},
+        {0x00016444, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db},
+        {0x00016448, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266},
 };
 
-static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
-        /* Addr      allmodes  */
+
+static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
+        /*   Addr     allmodes */
         {0x0000a000, 0x00010000},
         {0x0000a004, 0x00030002},
         {0x0000a008, 0x00050004},
@@ -1249,8 +943,8 @@ static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
         {0x0000b1fc, 0x00000196},
 };
 
-static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
-        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
+static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
+        /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -1316,19 +1010,87 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
         {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
         {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
-        {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016048, 0x64000001, 0x64000001, 0x64000001, 0x64000001},
-        {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016448, 0x64000001, 0x64000001, 0x64000001, 0x64000001},
-        {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
-        {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
-        {0x00016848, 0x64000001, 0x64000001, 0x64000001, 0x64000001},
-        {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
+        {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+};
+
+static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
+        /*  Addr       5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
+        {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
+        {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
+        {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
+        {0x0000a518, 0x21020220, 0x21020220, 0x15000402, 0x15000402},
+        {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
+        {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603},
+        {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02},
+        {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04},
+        {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x26000a20, 0x26000a20},
+        {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2a000e20, 0x2a000e20},
+        {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
+        {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
+        {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
+        {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
+        {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
+        {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
+        {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x42001a83, 0x42001a83},
+        {0x0000a550, 0x61042a6c, 0x61042a6c, 0x44001c84, 0x44001c84},
+        {0x0000a554, 0x66062a6c, 0x66062a6c, 0x48001ce3, 0x48001ce3},
+        {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x4c001ce5, 0x4c001ce5},
+        {0x0000a55c, 0x7006308c, 0x7006308c, 0x50001ce9, 0x50001ce9},
+        {0x0000a560, 0x730a308a, 0x730a308a, 0x54001ceb, 0x54001ceb},
+        {0x0000a564, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a568, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a56c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a570, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a574, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a578, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a57c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec},
+        {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
+        {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
+        {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
+        {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
+        {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
+        {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
+        {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
+        {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
+        {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
+        {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
+        {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
+        {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
+        {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
+        {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
+        {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
+        {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
+        {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
+        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
+        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
+        {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
+        {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
+        {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
+        {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
+        {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
+        {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
+        {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
+        {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016048, 0x24927266, 0x24927266, 0x8e483266, 0x8e483266},
+        {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
+        {0x00016448, 0x24927266, 0x24927266, 0x8e482266, 0x8e482266},
 };
 
-static const u32 ar9300_2p0_mac_core[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_mac_core[][2] = {
+        /*    Addr        allmodes        */
         {0x00000008, 0x00000000},
         {0x00000030, 0x00020085},
         {0x00000034, 0x00000005},
@@ -1437,7 +1199,7 @@ static const u32 ar9300_2p0_mac_core[][2] = {
         {0x00008258, 0x00000000},
         {0x0000825c, 0x40000000},
         {0x00008260, 0x00080922},
-        {0x00008264, 0x98a00010},
+        {0x00008264, 0x9d400010},
         {0x00008268, 0xffffffff},
         {0x0000826c, 0x0000ffff},
         {0x00008270, 0x00000000},
@@ -1491,8 +1253,8 @@ static const u32 ar9300_2p0_mac_core[][2] = {
         {0x000083d0, 0x000301ff},
 };
 
-static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = {
+        /*    Addr        allmodes        */
         {0x0000a000, 0x00010000},
         {0x0000a004, 0x00030002},
         {0x0000a008, 0x00050004},
@@ -1751,8 +1513,8 @@ static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
         {0x0000b1fc, 0x00000196},
 };
 
-static const u32 ar9300_2p0_soc_preamble[][2] = {
-        /* Addr      allmodes  */
+static const u32 ar9340_1p0_soc_preamble[][2] = {
+        /*    Addr        allmodes        */
         {0x000040a4, 0x00a0c1c9},
         {0x00007008, 0x00000000},
         {0x00007020, 0x00000000},
@@ -1760,25 +1522,4 @@ static const u32 ar9300_2p0_soc_preamble[][2] = {
         {0x00007038, 0x000004c2},
 };
 
-static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x00004040, 0x08212e5e},
-        {0x00004040, 0x0008003b},
-        {0x00004044, 0x00000000},
-};
-
-static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x00004040, 0x08253e5e},
-        {0x00004040, 0x0008003b},
-        {0x00004044, 0x00000000},
-};
-
-static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
-        /* Addr      allmodes  */
-        {0x00004040, 0x08213e5e},
-        {0x00004040, 0x0008003b},
-        {0x00004044, 0x00000000},
-};
-
-#endif /* INITVALS_9003_2P0_H */
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
new file mode 100644
index 000000000000..611ea6ce8508
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -0,0 +1,1161 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef INITVALS_9485_H
+#define INITVALS_9485_H
+
+static const u32 ar9485_1_1_mac_core[][2] = {
+        /*  Addr       allmodes */
+        {0x00000008, 0x00000000},
+        {0x00000030, 0x00020085},
+        {0x00000034, 0x00000005},
+        {0x00000040, 0x00000000},
+        {0x00000044, 0x00000000},
+        {0x00000048, 0x00000008},
+        {0x0000004c, 0x00000010},
+        {0x00000050, 0x00000000},
+        {0x00001040, 0x002ffc0f},
+        {0x00001044, 0x002ffc0f},
+        {0x00001048, 0x002ffc0f},
+        {0x0000104c, 0x002ffc0f},
+        {0x00001050, 0x002ffc0f},
+        {0x00001054, 0x002ffc0f},
+        {0x00001058, 0x002ffc0f},
+        {0x0000105c, 0x002ffc0f},
+        {0x00001060, 0x002ffc0f},
+        {0x00001064, 0x002ffc0f},
+        {0x000010f0, 0x00000100},
+        {0x00001270, 0x00000000},
+        {0x000012b0, 0x00000000},
+        {0x000012f0, 0x00000000},
+        {0x0000143c, 0x00000000},
+        {0x0000147c, 0x00000000},
+        {0x00008000, 0x00000000},
+        {0x00008004, 0x00000000},
+        {0x00008008, 0x00000000},
+        {0x0000800c, 0x00000000},
+        {0x00008018, 0x00000000},
+        {0x00008020, 0x00000000},
+        {0x00008038, 0x00000000},
+        {0x0000803c, 0x00000000},
+        {0x00008040, 0x00000000},
+        {0x00008044, 0x00000000},
+        {0x00008048, 0x00000000},
+        {0x0000804c, 0xffffffff},
+        {0x00008054, 0x00000000},
+        {0x00008058, 0x00000000},
+        {0x0000805c, 0x000fc78f},
+        {0x00008060, 0x0000000f},
+        {0x00008064, 0x00000000},
+        {0x00008070, 0x00000310},
+        {0x00008074, 0x00000020},
+        {0x00008078, 0x00000000},
+        {0x0000809c, 0x0000000f},
+        {0x000080a0, 0x00000000},
+        {0x000080a4, 0x02ff0000},
+        {0x000080a8, 0x0e070605},
+        {0x000080ac, 0x0000000d},
+        {0x000080b0, 0x00000000},
+        {0x000080b4, 0x00000000},
+        {0x000080b8, 0x00000000},
+        {0x000080bc, 0x00000000},
+        {0x000080c0, 0x2a800000},
+        {0x000080c4, 0x06900168},
+        {0x000080c8, 0x13881c22},
+        {0x000080cc, 0x01f40000},
+        {0x000080d0, 0x00252500},
+        {0x000080d4, 0x00a00000},
+        {0x000080d8, 0x00400000},
+        {0x000080dc, 0x00000000},
+        {0x000080e0, 0xffffffff},
+        {0x000080e4, 0x0000ffff},
+        {0x000080e8, 0x3f3f3f3f},
+        {0x000080ec, 0x00000000},
+        {0x000080f0, 0x00000000},
+        {0x000080f4, 0x00000000},
+        {0x000080fc, 0x00020000},
+        {0x00008100, 0x00000000},
+        {0x00008108, 0x00000052},
+        {0x0000810c, 0x00000000},
+        {0x00008110, 0x00000000},
+        {0x00008114, 0x000007ff},
+        {0x00008118, 0x000000aa},
+        {0x0000811c, 0x00003210},
+        {0x00008124, 0x00000000},
+        {0x00008128, 0x00000000},
+        {0x0000812c, 0x00000000},
+        {0x00008130, 0x00000000},
+        {0x00008134, 0x00000000},
+        {0x00008138, 0x00000000},
+        {0x0000813c, 0x0000ffff},
+        {0x00008144, 0xffffffff},
+        {0x00008168, 0x00000000},
+        {0x0000816c, 0x00000000},
+        {0x00008170, 0x18486200},
+        {0x00008174, 0x33332210},
+        {0x00008178, 0x00000000},
+        {0x0000817c, 0x00020000},
+        {0x000081c0, 0x00000000},
+        {0x000081c4, 0x33332210},
+        {0x000081d4, 0x00000000},
+        {0x000081ec, 0x00000000},
+        {0x000081f0, 0x00000000},
+        {0x000081f4, 0x00000000},
+        {0x000081f8, 0x00000000},
+        {0x000081fc, 0x00000000},
+        {0x00008240, 0x00100000},
+        {0x00008244, 0x0010f400},
+        {0x00008248, 0x00000800},
+        {0x0000824c, 0x0001e800},
+        {0x00008250, 0x00000000},
+        {0x00008254, 0x00000000},
+        {0x00008258, 0x00000000},
+        {0x0000825c, 0x40000000},
+        {0x00008260, 0x00080922},
+        {0x00008264, 0x9ca00010},
+        {0x00008268, 0xffffffff},
+        {0x0000826c, 0x0000ffff},
+        {0x00008270, 0x00000000},
+        {0x00008274, 0x40000000},
+        {0x00008278, 0x003e4180},
+        {0x0000827c, 0x00000004},
+        {0x00008284, 0x0000002c},
+        {0x00008288, 0x0000002c},
+        {0x0000828c, 0x000000ff},
+        {0x00008294, 0x00000000},
+        {0x00008298, 0x00000000},
+        {0x0000829c, 0x00000000},
+        {0x00008300, 0x00000140},
+        {0x00008314, 0x00000000},
+        {0x0000831c, 0x0000010d},
+        {0x00008328, 0x00000000},
+        {0x0000832c, 0x00000007},
+        {0x00008330, 0x00000302},
+        {0x00008334, 0x00000700},
+        {0x00008338, 0x00ff0000},
+        {0x0000833c, 0x02400000},
+        {0x00008340, 0x000107ff},
+        {0x00008344, 0xa248105b},
+        {0x00008348, 0x008f0000},
+        {0x0000835c, 0x00000000},
+        {0x00008360, 0xffffffff},
+        {0x00008364, 0xffffffff},
+        {0x00008368, 0x00000000},
+        {0x00008370, 0x00000000},
+        {0x00008374, 0x000000ff},
+        {0x00008378, 0x00000000},
+        {0x0000837c, 0x00000000},
+        {0x00008380, 0xffffffff},
+        {0x00008384, 0xffffffff},
+        {0x00008390, 0xffffffff},
+        {0x00008394, 0xffffffff},
+        {0x00008398, 0x00000000},
+        {0x0000839c, 0x00000000},
+        {0x000083a0, 0x00000000},
+        {0x000083a4, 0x0000fa14},
+        {0x000083a8, 0x000f0c00},
+        {0x000083ac, 0x33332210},
+        {0x000083b0, 0x33332210},
+        {0x000083b4, 0x33332210},
+        {0x000083b8, 0x33332210},
+        {0x000083bc, 0x00000000},
+        {0x000083c0, 0x00000000},
+        {0x000083c4, 0x00000000},
+        {0x000083c8, 0x00000000},
+        {0x000083cc, 0x00000200},
+        {0x000083d0, 0x000301ff},
+};
+
+static const u32 ar9485_1_1_baseband_core[][2] = {
+        /* Addr       allmodes */
+        {0x00009800, 0xafe68e30},
+        {0x00009804, 0xfd14e000},
+        {0x00009808, 0x9c0a8f6b},
+        {0x0000980c, 0x04800000},
+        {0x00009814, 0x9280c00a},
+        {0x00009818, 0x00000000},
+        {0x0000981c, 0x00020028},
+        {0x00009834, 0x5f3ca3de},
+        {0x00009838, 0x0108ecff},
+        {0x0000983c, 0x14750600},
+        {0x00009880, 0x201fff00},
+        {0x00009884, 0x00001042},
+        {0x000098a4, 0x00200400},
+        {0x000098b0, 0x52440bbe},
+        {0x000098d0, 0x004b6a8e},
+        {0x000098d4, 0x00000820},
+        {0x000098dc, 0x00000000},
+        {0x000098f0, 0x00000000},
+        {0x000098f4, 0x00000000},
+        {0x00009c04, 0x00000000},
+        {0x00009c08, 0x03200000},
+        {0x00009c0c, 0x00000000},
+        {0x00009c10, 0x00000000},
+        {0x00009c14, 0x00046384},
+        {0x00009c18, 0x05b6b440},
+        {0x00009c1c, 0x00b6b440},
+        {0x00009d00, 0xc080a333},
+        {0x00009d04, 0x40206c10},
+        {0x00009d08, 0x009c4060},
+        {0x00009d0c, 0x1883800a},
+        {0x00009d10, 0x01834061},
+        {0x00009d14, 0x00c00400},
+        {0x00009d18, 0x00000000},
+        {0x00009d1c, 0x00000000},
+        {0x00009e08, 0x0038233c},
+        {0x00009e24, 0x9927b515},
+        {0x00009e28, 0x12ef0200},
+        {0x00009e30, 0x06336f77},
+        {0x00009e34, 0x6af6532f},
+        {0x00009e38, 0x0cc80c00},
+        {0x00009e40, 0x0d261820},
+        {0x00009e4c, 0x00001004},
+        {0x00009e50, 0x00ff03f1},
+        {0x00009fc0, 0x80be4788},
+        {0x00009fc4, 0x0001efb5},
+        {0x00009fcc, 0x40000014},
+        {0x0000a20c, 0x00000000},
+        {0x0000a210, 0x00000000},
+        {0x0000a220, 0x00000000},
+        {0x0000a224, 0x00000000},
+        {0x0000a228, 0x10002310},
+        {0x0000a23c, 0x00000000},
+        {0x0000a244, 0x0c000000},
+        {0x0000a2a0, 0x00000001},
+        {0x0000a2c0, 0x00000001},
+        {0x0000a2c8, 0x00000000},
+        {0x0000a2cc, 0x18c43433},
+        {0x0000a2d4, 0x00000000},
+        {0x0000a2dc, 0x00000000},
+        {0x0000a2e0, 0x00000000},
+        {0x0000a2e4, 0x00000000},
+        {0x0000a2e8, 0x00000000},
+        {0x0000a2ec, 0x00000000},
+        {0x0000a2f0, 0x00000000},
+        {0x0000a2f4, 0x00000000},
+        {0x0000a2f8, 0x00000000},
+        {0x0000a344, 0x00000000},
+        {0x0000a34c, 0x00000000},
+        {0x0000a350, 0x0000a000},
+        {0x0000a364, 0x00000000},
+        {0x0000a370, 0x00000000},
+        {0x0000a390, 0x00000001},
+        {0x0000a394, 0x00000444},
+        {0x0000a398, 0x001f0e0f},
+        {0x0000a39c, 0x0075393f},
+        {0x0000a3a0, 0xb79f6427},
+        {0x0000a3a4, 0x000000ff},
+        {0x0000a3a8, 0x3b3b3b3b},
+        {0x0000a3ac, 0x2f2f2f2f},
+        {0x0000a3c0, 0x20202020},
+        {0x0000a3c4, 0x22222220},
+        {0x0000a3c8, 0x20200020},
+        {0x0000a3cc, 0x20202020},
+        {0x0000a3d0, 0x20202020},
+        {0x0000a3d4, 0x20202020},
+        {0x0000a3d8, 0x20202020},
+        {0x0000a3dc, 0x20202020},
+        {0x0000a3e0, 0x20202020},
+        {0x0000a3e4, 0x20202020},
+        {0x0000a3e8, 0x20202020},
+        {0x0000a3ec, 0x20202020},
+        {0x0000a3f0, 0x00000000},
+        {0x0000a3f4, 0x00000006},
+        {0x0000a3f8, 0x0cdbd380},
+        {0x0000a3fc, 0x000f0f01},
+        {0x0000a400, 0x8fa91f01},
+        {0x0000a404, 0x00000000},
+        {0x0000a408, 0x0e79e5c6},
+        {0x0000a40c, 0x00820820},
+        {0x0000a414, 0x1ce739cf},
+        {0x0000a418, 0x2d0019ce},
+        {0x0000a41c, 0x1ce739ce},
+        {0x0000a420, 0x000001ce},
+        {0x0000a424, 0x1ce739ce},
+        {0x0000a428, 0x000001ce},
+        {0x0000a42c, 0x1ce739ce},
+        {0x0000a430, 0x1ce739ce},
+        {0x0000a434, 0x00000000},
+        {0x0000a438, 0x00001801},
+        {0x0000a43c, 0x00000000},
+        {0x0000a440, 0x00000000},
+        {0x0000a444, 0x00000000},
+        {0x0000a448, 0x04000000},
+        {0x0000a44c, 0x00000001},
+        {0x0000a450, 0x00010000},
+        {0x0000a5c4, 0xbfad9d74},
+        {0x0000a5c8, 0x0048060a},
+        {0x0000a5cc, 0x00000637},
+        {0x0000a760, 0x03020100},
+        {0x0000a764, 0x09080504},
+        {0x0000a768, 0x0d0c0b0a},
+        {0x0000a76c, 0x13121110},
+        {0x0000a770, 0x31301514},
+        {0x0000a774, 0x35343332},
+        {0x0000a778, 0x00000036},
+        {0x0000a780, 0x00000838},
+        {0x0000a7c0, 0x00000000},
+        {0x0000a7c4, 0xfffffffc},
+        {0x0000a7c8, 0x00000000},
+        {0x0000a7cc, 0x00000000},
+        {0x0000a7d0, 0x00000000},
+        {0x0000a7d4, 0x00000004},
+        {0x0000a7dc, 0x00000000},
+};
+
+static const u32 ar9485Common_1_1[][2] = {
+        /*  Addr      allmodes */
+        {0x00007010, 0x00000022},
+        {0x00007020, 0x00000000},
+        {0x00007034, 0x00000002},
+        {0x00007038, 0x000004c2},
+};
+
+static const u32 ar9485_1_1_baseband_postamble[][5] = {
+        /* Addr       5G_HT20        5G_HT40       2G_HT40       2G_HT20 */
+        {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+        {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+        {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+        {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+        {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+        {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+        {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+        {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
+        {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+        {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
+        {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+        {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+        {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+        {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
+        {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+        {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+        {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+        {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
+        {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+        {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
+        {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
+        {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+        {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+        {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+        {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+        {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+        {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+        {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+        {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+        {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
+        {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+        {0x0000a2d0, 0x00071981, 0x00071981, 0x00071982, 0x00071982},
+        {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+        {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+};
+
+static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20  */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_1_1_radio_postamble[][2] = {
+        /* Addr        allmodes */
+        {0x0001609c, 0x0b283f31},
+        {0x000160ac, 0x24611800},
+        {0x000160b0, 0x03284f3e},
+        {0x0001610c, 0x00170000},
+        {0x00016140, 0x10804008},
+};
+
+static const u32 ar9485_1_1_mac_postamble[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+        {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+        {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+        {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+        {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+        {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+        {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+        {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+};
+
+static const u32 ar9485_1_1_radio_core[][2] = {
+        /* Addr        allmodes */
+        {0x00016000, 0x36db6db6},
+        {0x00016004, 0x6db6db40},
+        {0x00016008, 0x73800000},
+        {0x0001600c, 0x00000000},
+        {0x00016040, 0x7f80fff8},
+        {0x0001604c, 0x000f0278},
+        {0x00016050, 0x4db6db8c},
+        {0x00016054, 0x6db60000},
+        {0x00016080, 0x00080000},
+        {0x00016084, 0x0e48048c},
+        {0x00016088, 0x14214514},
+        {0x0001608c, 0x119f081e},
+        {0x00016090, 0x24926490},
+        {0x00016098, 0xd28b3330},
+        {0x000160a0, 0xc2108ffe},
+        {0x000160a4, 0x812fc370},
+        {0x000160a8, 0x423c8000},
+        {0x000160b4, 0x92480040},
+        {0x000160c0, 0x006db6db},
+        {0x000160c4, 0x0186db60},
+        {0x000160c8, 0x6db6db6c},
+        {0x000160cc, 0x6de6fbe0},
+        {0x000160d0, 0xf7dfcf3c},
+        {0x00016100, 0x04cb0001},
+        {0x00016104, 0xfff80015},
+        {0x00016108, 0x00080010},
+        {0x00016144, 0x01884080},
+        {0x00016148, 0x00008040},
+        {0x00016240, 0x08400000},
+        {0x00016244, 0x1bf90f00},
+        {0x00016248, 0x00000000},
+        {0x0001624c, 0x00000000},
+        {0x00016280, 0x01000015},
+        {0x00016284, 0x00d30000},
+        {0x00016288, 0x00318000},
+        {0x0001628c, 0x50000000},
+        {0x00016290, 0x4b96210f},
+        {0x00016380, 0x00000000},
+        {0x00016384, 0x00000000},
+        {0x00016388, 0x00800700},
+        {0x0001638c, 0x00800700},
+        {0x00016390, 0x00800700},
+        {0x00016394, 0x00000000},
+        {0x00016398, 0x00000000},
+        {0x0001639c, 0x00000000},
+        {0x000163a0, 0x00000001},
+        {0x000163a4, 0x00000001},
+        {0x000163a8, 0x00000000},
+        {0x000163ac, 0x00000000},
+        {0x000163b0, 0x00000000},
+        {0x000163b4, 0x00000000},
+        {0x000163b8, 0x00000000},
+        {0x000163bc, 0x00000000},
+        {0x000163c0, 0x000000a0},
+        {0x000163c4, 0x000c0000},
+        {0x000163c8, 0x14021402},
+        {0x000163cc, 0x00001402},
+        {0x000163d0, 0x00000000},
+        {0x000163d4, 0x00000000},
+        {0x00016c40, 0x13188278},
+        {0x00016c44, 0x12000000},
+};
+
+static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
+        /* Addr        allmodes */
+        {0x00018c00, 0x10052e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_1_1[][2] = {
+        /* Addr        allmodes */
+        {0x0000a580, 0x00000000},
+        {0x0000a584, 0x00000000},
+        {0x0000a588, 0x00000000},
+        {0x0000a58c, 0x00000000},
+        {0x0000a590, 0x00000000},
+        {0x0000a594, 0x00000000},
+        {0x0000a598, 0x00000000},
+        {0x0000a59c, 0x00000000},
+        {0x0000a5a0, 0x00000000},
+        {0x0000a5a4, 0x00000000},
+        {0x0000a5a8, 0x00000000},
+        {0x0000a5ac, 0x00000000},
+        {0x0000a5b0, 0x00000000},
+        {0x0000a5b4, 0x00000000},
+        {0x0000a5b8, 0x00000000},
+        {0x0000a5bc, 0x00000000},
+};
+
+static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
+        {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000006, 0x00000006},
+        {0x0000a504, 0x05062002, 0x05062002, 0x03000201, 0x03000201},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x06000203, 0x06000203},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0a000401, 0x0a000401},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x0e000403, 0x0e000403},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x12000405, 0x12000405},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x15000604, 0x15000604},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x18000605, 0x18000605},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x1c000a04, 0x1c000a04},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x21000a06, 0x21000a06},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x29000a24, 0x29000a24},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2f000e21, 0x2f000e21},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000e20, 0x31000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x33000e20, 0x33000e20},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b504, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b508, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b50c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b510, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b514, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b518, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b51c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b520, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b524, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b528, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
+        {0x0000b52c, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a},
+        {0x0000b530, 0x0000003a, 0x0000003a, 0x0000003a, 0x0000003a},
+        {0x0000b534, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a},
+        {0x0000b538, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b53c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b540, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b544, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b548, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b54c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b550, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b554, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b558, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b55c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b560, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b564, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b568, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b56c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b570, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b574, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b578, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x0000b57c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
+        /* Addr        allmodes */
+        {0x00018c00, 0x10013e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485_1_1_soc_preamble[][2] = {
+        /* Addr        allmodes */
+        {0x00004014, 0xba280400},
+        {0x00004090, 0x00aa10aa},
+        {0x000040a4, 0x00a0c9c9},
+        {0x00007010, 0x00000022},
+        {0x00007020, 0x00000000},
+        {0x00007034, 0x00000002},
+        {0x00007038, 0x000004c2},
+        {0x00007048, 0x00000002},
+};
+
+static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
+        /* Addr        allmodes */
+        {0x0000a398, 0x00000000},
+        {0x0000a39c, 0x6f7f0301},
+        {0x0000a3a0, 0xca9228ee},
+};
+
+static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
+        /* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20  */
+        {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+        {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+        {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+};
+
+static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
+        /* Addr        5G_HT2        5G_HT40  */
+        {0x00009e00, 0x03721821, 0x03721821},
+        {0x0000a230, 0x0000400b, 0x00004016},
+        {0x0000a254, 0x00000898, 0x00001130},
+};
+
+static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
+        /* Addr        allmodes  */
+        {0x00018c00, 0x10012e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485_common_rx_gain_1_1[][2] = {
+        /* Addr        allmodes */
+        {0x0000a000, 0x00010000},
+        {0x0000a004, 0x00030002},
+        {0x0000a008, 0x00050004},
+        {0x0000a00c, 0x00810080},
+        {0x0000a010, 0x01800082},
+        {0x0000a014, 0x01820181},
+        {0x0000a018, 0x01840183},
+        {0x0000a01c, 0x01880185},
+        {0x0000a020, 0x018a0189},
+        {0x0000a024, 0x02850284},
+        {0x0000a028, 0x02890288},
+        {0x0000a02c, 0x03850384},
+        {0x0000a030, 0x03890388},
+        {0x0000a034, 0x038b038a},
+        {0x0000a038, 0x038d038c},
+        {0x0000a03c, 0x03910390},
+        {0x0000a040, 0x03930392},
+        {0x0000a044, 0x03950394},
+        {0x0000a048, 0x00000396},
+        {0x0000a04c, 0x00000000},
+        {0x0000a050, 0x00000000},
+        {0x0000a054, 0x00000000},
+        {0x0000a058, 0x00000000},
+        {0x0000a05c, 0x00000000},
+        {0x0000a060, 0x00000000},
+        {0x0000a064, 0x00000000},
+        {0x0000a068, 0x00000000},
+        {0x0000a06c, 0x00000000},
+        {0x0000a070, 0x00000000},
+        {0x0000a074, 0x00000000},
+        {0x0000a078, 0x00000000},
+        {0x0000a07c, 0x00000000},
+        {0x0000a080, 0x28282828},
+        {0x0000a084, 0x28282828},
+        {0x0000a088, 0x28282828},
+        {0x0000a08c, 0x28282828},
+        {0x0000a090, 0x28282828},
+        {0x0000a094, 0x21212128},
+        {0x0000a098, 0x171c1c1c},
+        {0x0000a09c, 0x02020212},
+        {0x0000a0a0, 0x00000202},
+        {0x0000a0a4, 0x00000000},
+        {0x0000a0a8, 0x00000000},
+        {0x0000a0ac, 0x00000000},
+        {0x0000a0b0, 0x00000000},
+        {0x0000a0b4, 0x00000000},
+        {0x0000a0b8, 0x00000000},
+        {0x0000a0bc, 0x00000000},
+        {0x0000a0c0, 0x001f0000},
+        {0x0000a0c4, 0x111f1100},
+        {0x0000a0c8, 0x111d111e},
+        {0x0000a0cc, 0x111b111c},
+        {0x0000a0d0, 0x22032204},
+        {0x0000a0d4, 0x22012202},
+        {0x0000a0d8, 0x221f2200},
+        {0x0000a0dc, 0x221d221e},
+        {0x0000a0e0, 0x33013302},
+        {0x0000a0e4, 0x331f3300},
+        {0x0000a0e8, 0x4402331e},
+        {0x0000a0ec, 0x44004401},
+        {0x0000a0f0, 0x441e441f},
+        {0x0000a0f4, 0x55015502},
+        {0x0000a0f8, 0x551f5500},
+        {0x0000a0fc, 0x6602551e},
+        {0x0000a100, 0x66006601},
+        {0x0000a104, 0x661e661f},
+        {0x0000a108, 0x7703661d},
+        {0x0000a10c, 0x77017702},
+        {0x0000a110, 0x00007700},
+        {0x0000a114, 0x00000000},
+        {0x0000a118, 0x00000000},
+        {0x0000a11c, 0x00000000},
+        {0x0000a120, 0x00000000},
+        {0x0000a124, 0x00000000},
+        {0x0000a128, 0x00000000},
+        {0x0000a12c, 0x00000000},
+        {0x0000a130, 0x00000000},
+        {0x0000a134, 0x00000000},
+        {0x0000a138, 0x00000000},
+        {0x0000a13c, 0x00000000},
+        {0x0000a140, 0x001f0000},
+        {0x0000a144, 0x111f1100},
+        {0x0000a148, 0x111d111e},
+        {0x0000a14c, 0x111b111c},
+        {0x0000a150, 0x22032204},
+        {0x0000a154, 0x22012202},
+        {0x0000a158, 0x221f2200},
+        {0x0000a15c, 0x221d221e},
+        {0x0000a160, 0x33013302},
+        {0x0000a164, 0x331f3300},
+        {0x0000a168, 0x4402331e},
+        {0x0000a16c, 0x44004401},
+        {0x0000a170, 0x441e441f},
+        {0x0000a174, 0x55015502},
+        {0x0000a178, 0x551f5500},
+        {0x0000a17c, 0x6602551e},
+        {0x0000a180, 0x66006601},
+        {0x0000a184, 0x661e661f},
+        {0x0000a188, 0x7703661d},
+        {0x0000a18c, 0x77017702},
+        {0x0000a190, 0x00007700},
+        {0x0000a194, 0x00000000},
+        {0x0000a198, 0x00000000},
+        {0x0000a19c, 0x00000000},
+        {0x0000a1a0, 0x00000000},
+        {0x0000a1a4, 0x00000000},
+        {0x0000a1a8, 0x00000000},
+        {0x0000a1ac, 0x00000000},
+        {0x0000a1b0, 0x00000000},
+        {0x0000a1b4, 0x00000000},
+        {0x0000a1b8, 0x00000000},
+        {0x0000a1bc, 0x00000000},
+        {0x0000a1c0, 0x00000000},
+        {0x0000a1c4, 0x00000000},
+        {0x0000a1c8, 0x00000000},
+        {0x0000a1cc, 0x00000000},
+        {0x0000a1d0, 0x00000000},
+        {0x0000a1d4, 0x00000000},
+        {0x0000a1d8, 0x00000000},
+        {0x0000a1dc, 0x00000000},
+        {0x0000a1e0, 0x00000000},
+        {0x0000a1e4, 0x00000000},
+        {0x0000a1e8, 0x00000000},
+        {0x0000a1ec, 0x00000000},
+        {0x0000a1f0, 0x00000396},
+        {0x0000a1f4, 0x00000396},
+        {0x0000a1f8, 0x00000396},
+        {0x0000a1fc, 0x00000296},
+};
+
+static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
+        /* Addr        allmodes */
+        {0x00018c00, 0x10053e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000080c},
+};
+
+static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
+        /* Addr        allmodes */
+        {0x0000a000, 0x00060005},
+        {0x0000a004, 0x00810080},
+        {0x0000a008, 0x00830082},
+        {0x0000a00c, 0x00850084},
+        {0x0000a010, 0x01820181},
+        {0x0000a014, 0x01840183},
+        {0x0000a018, 0x01880185},
+        {0x0000a01c, 0x018a0189},
+        {0x0000a020, 0x02850284},
+        {0x0000a024, 0x02890288},
+        {0x0000a028, 0x028b028a},
+        {0x0000a02c, 0x03850384},
+        {0x0000a030, 0x03890388},
+        {0x0000a034, 0x038b038a},
+        {0x0000a038, 0x038d038c},
+        {0x0000a03c, 0x03910390},
+        {0x0000a040, 0x03930392},
+        {0x0000a044, 0x03950394},
+        {0x0000a048, 0x00000396},
+        {0x0000a04c, 0x00000000},
+        {0x0000a050, 0x00000000},
+        {0x0000a054, 0x00000000},
+        {0x0000a058, 0x00000000},
+        {0x0000a05c, 0x00000000},
+        {0x0000a060, 0x00000000},
+        {0x0000a064, 0x00000000},
+        {0x0000a068, 0x00000000},
+        {0x0000a06c, 0x00000000},
+        {0x0000a070, 0x00000000},
+        {0x0000a074, 0x00000000},
+        {0x0000a078, 0x00000000},
+        {0x0000a07c, 0x00000000},
+        {0x0000a080, 0x28282828},
+        {0x0000a084, 0x28282828},
+        {0x0000a088, 0x28282828},
+        {0x0000a08c, 0x28282828},
+        {0x0000a090, 0x28282828},
+        {0x0000a094, 0x24242428},
+        {0x0000a098, 0x171e1e1e},
+        {0x0000a09c, 0x02020b0b},
+        {0x0000a0a0, 0x02020202},
+        {0x0000a0a4, 0x00000000},
+        {0x0000a0a8, 0x00000000},
+        {0x0000a0ac, 0x00000000},
+        {0x0000a0b0, 0x00000000},
+        {0x0000a0b4, 0x00000000},
+        {0x0000a0b8, 0x00000000},
+        {0x0000a0bc, 0x00000000},
+        {0x0000a0c0, 0x22072208},
+        {0x0000a0c4, 0x22052206},
+        {0x0000a0c8, 0x22032204},
+        {0x0000a0cc, 0x22012202},
+        {0x0000a0d0, 0x221f2200},
+        {0x0000a0d4, 0x221d221e},
+        {0x0000a0d8, 0x33023303},
+        {0x0000a0dc, 0x33003301},
+        {0x0000a0e0, 0x331e331f},
+        {0x0000a0e4, 0x4402331d},
+        {0x0000a0e8, 0x44004401},
+        {0x0000a0ec, 0x441e441f},
+        {0x0000a0f0, 0x55025503},
+        {0x0000a0f4, 0x55005501},
+        {0x0000a0f8, 0x551e551f},
+        {0x0000a0fc, 0x6602551d},
+        {0x0000a100, 0x66006601},
+        {0x0000a104, 0x661e661f},
+        {0x0000a108, 0x7703661d},
+        {0x0000a10c, 0x77017702},
+        {0x0000a110, 0x00007700},
+        {0x0000a114, 0x00000000},
+        {0x0000a118, 0x00000000},
+        {0x0000a11c, 0x00000000},
+        {0x0000a120, 0x00000000},
+        {0x0000a124, 0x00000000},
+        {0x0000a128, 0x00000000},
+        {0x0000a12c, 0x00000000},
+        {0x0000a130, 0x00000000},
+        {0x0000a134, 0x00000000},
+        {0x0000a138, 0x00000000},
+        {0x0000a13c, 0x00000000},
+        {0x0000a140, 0x001f0000},
+        {0x0000a144, 0x111f1100},
+        {0x0000a148, 0x111d111e},
+        {0x0000a14c, 0x111b111c},
+        {0x0000a150, 0x22032204},
+        {0x0000a154, 0x22012202},
+        {0x0000a158, 0x221f2200},
+        {0x0000a15c, 0x221d221e},
+        {0x0000a160, 0x33013302},
+        {0x0000a164, 0x331f3300},
+        {0x0000a168, 0x4402331e},
+        {0x0000a16c, 0x44004401},
+        {0x0000a170, 0x441e441f},
+        {0x0000a174, 0x55015502},
+        {0x0000a178, 0x551f5500},
+        {0x0000a17c, 0x6602551e},
+        {0x0000a180, 0x66006601},
+        {0x0000a184, 0x661e661f},
+        {0x0000a188, 0x7703661d},
+        {0x0000a18c, 0x77017702},
+        {0x0000a190, 0x00007700},
+        {0x0000a194, 0x00000000},
+        {0x0000a198, 0x00000000},
+        {0x0000a19c, 0x00000000},
+        {0x0000a1a0, 0x00000000},
+        {0x0000a1a4, 0x00000000},
+        {0x0000a1a8, 0x00000000},
+        {0x0000a1ac, 0x00000000},
+        {0x0000a1b0, 0x00000000},
+        {0x0000a1b4, 0x00000000},
+        {0x0000a1b8, 0x00000000},
+        {0x0000a1bc, 0x00000000},
+        {0x0000a1c0, 0x00000000},
+        {0x0000a1c4, 0x00000000},
+        {0x0000a1c8, 0x00000000},
+        {0x0000a1cc, 0x00000000},
+        {0x0000a1d0, 0x00000000},
+        {0x0000a1d4, 0x00000000},
+        {0x0000a1d8, 0x00000000},
+        {0x0000a1dc, 0x00000000},
+        {0x0000a1e0, 0x00000000},
+        {0x0000a1e4, 0x00000000},
+        {0x0000a1e8, 0x00000000},
+        {0x0000a1ec, 0x00000000},
+        {0x0000a1f0, 0x00000396},
+        {0x0000a1f4, 0x00000396},
+        {0x0000a1f8, 0x00000396},
+        {0x0000a1fc, 0x00000296},
+};
+
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 07f26ee7a723..f75068b4b310 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -62,7 +62,6 @@ struct ath_node;
 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
 
 struct ath_config {
-        u32 ath_aggr_prot;
         u16 txpowlimit;
         u8 cabqReadytime;
 };
@@ -86,33 +85,19 @@ struct ath_config {
 /**
  * enum buffer_type - Buffer type flags
  *
- * @BUF_HT: Send this buffer using HT capabilities
  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  *      (used in aggregation scheduling)
- * @BUF_RETRY: Indicates whether the buffer is retried
  * @BUF_XRETRY: To denote excessive retries of the buffer
  */
 enum buffer_type {
-        BUF_HT                  = BIT(1),
-        BUF_AMPDU               = BIT(2),
-        BUF_AGGR                = BIT(3),
-        BUF_RETRY               = BIT(4),
-        BUF_XRETRY              = BIT(5),
+        BUF_AMPDU               = BIT(0),
+        BUF_AGGR                = BIT(1),
+        BUF_XRETRY              = BIT(2),
 };
 
-#define bf_nframes              bf_state.bfs_nframes
-#define bf_al                   bf_state.bfs_al
-#define bf_frmlen               bf_state.bfs_frmlen
-#define bf_retries              bf_state.bfs_retries
-#define bf_seqno                bf_state.bfs_seqno
-#define bf_tidno                bf_state.bfs_tidno
-#define bf_keyix                bf_state.bfs_keyix
-#define bf_keytype              bf_state.bfs_keytype
-#define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
-#define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 
 #define ATH_TXSTATUS_RING_SIZE 64
@@ -134,13 +119,11 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 /* RX / TX */
 /***********/
 
-#define ATH_MAX_ANTENNA         3
 #define ATH_RXBUF               512
 #define ATH_TXBUF               512
 #define ATH_TXBUF_RESERVE       5
 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 #define ATH_TXMAXTRY            13
-#define ATH_MGT_TXMAXTRY        4
 
 #define TID_TO_WME_AC(_tid)                             \
         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
@@ -148,7 +131,6 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
          WME_AC_VO)
 
-#define ADDBA_EXCHANGE_ATTEMPTS    10
 #define ATH_AGGR_DELIM_SZ          4
 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 /* number of delimiters for encryption padding */
@@ -177,8 +159,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 
 /* returns delimiter padding required given the packet length */
 #define ATH_AGGR_GET_NDELIM(_len)                                       \
-        (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
-          (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
+       (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
+        DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 
 #define BAW_WITHIN(_start, _bawsz, _seqno) \
         ((((_seqno) - (_start)) & 4095) < (_bawsz))
@@ -195,12 +177,13 @@ enum ATH_AGGR_STATUS {
 
 #define ATH_TXFIFO_DEPTH 8
 struct ath_txq {
-        int axq_class;
-        u32 axq_qnum;
+        int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
+        u32 axq_qnum; /* ath9k hardware queue number */
         u32 *axq_link;
         struct list_head axq_q;
         spinlock_t axq_lock;
         u32 axq_depth;
+        u32 axq_ampdu_depth;
         bool stopped;
         bool axq_tx_inprogress;
         struct list_head axq_acq;
@@ -208,27 +191,30 @@ struct ath_txq {
         struct list_head txq_fifo_pending;
         u8 txq_headidx;
         u8 txq_tailidx;
+        int pending_frames;
 };
 
 struct ath_atx_ac {
+        struct ath_txq *txq;
         int sched;
-        int qnum;
         struct list_head list;
         struct list_head tid_q;
+        bool clear_ps_filter;
+};
+
+struct ath_frame_info {
+        int framelen;
+        u32 keyix;
+        enum ath9k_key_type keytype;
+        u8 retries;
+        u16 seqno;
 };
 
 struct ath_buf_state {
-        int bfs_nframes;
-        u16 bfs_al;
-        u16 bfs_frmlen;
-        int bfs_seqno;
-        int bfs_tidno;
-        int bfs_retries;
         u8 bf_type;
         u8 bfs_paprd;
         unsigned long bfs_paprd_timestamp;
-        u32 bfs_keyix;
-        enum ath9k_key_type bfs_keytype;
+        enum ath9k_internal_frame_type bfs_ftype;
 };
 
 struct ath_buf {
@@ -239,14 +225,10 @@ struct ath_buf {
         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
         void *bf_desc;                  /* virtual addr of desc */
         dma_addr_t bf_daddr;            /* physical addr of desc */
-        dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
+        dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
         bool bf_stale;
-        bool bf_isnullfunc;
-        bool bf_tx_aborted;
         u16 bf_flags;
         struct ath_buf_state bf_state;
-        dma_addr_t bf_dmacontext;
-        struct ath_wiphy *aphy;
 };
 
 struct ath_atx_tid {
@@ -254,7 +236,7 @@ struct ath_atx_tid {
         struct list_head buf_q;
         struct ath_node *an;
         struct ath_atx_ac *ac;
-        struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
+        unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
         u16 seq_start;
         u16 seq_next;
         u16 baw_size;
@@ -267,12 +249,18 @@ struct ath_atx_tid {
 };
 
 struct ath_node {
-        struct ath_common *common;
+#ifdef CONFIG_ATH9K_DEBUGFS
+        struct list_head list; /* for sc->nodes */
+        struct ieee80211_sta *sta; /* station struct we're part of */
+#endif
         struct ath_atx_tid tid[WME_NUM_TID];
         struct ath_atx_ac ac[WME_NUM_AC];
+        int ps_key;
+
         u16 maxampdu;
         u8 mpdudensity;
-        int last_rssi;
+
+        bool sleeping;
 };
 
 #define AGGR_CLEANUP         BIT(1)
@@ -281,6 +269,7 @@ struct ath_node {
 
 struct ath_tx_control {
         struct ath_txq *txq;
+        struct ath_node *an;
         int if_id;
         enum ath9k_internal_frame_type frame_type;
         u8 paprd;
@@ -290,15 +279,19 @@ struct ath_tx_control {
 #define ATH_TX_XRETRY       0x02
 #define ATH_TX_BAR          0x04
 
+/**
+ * @txq_map:  Index is mac80211 queue number.  This is
+ *  not necessarily the same as the hardware queue number
+ *  (axq_qnum).
+ */
 struct ath_tx {
         u16 seq_no;
         u32 txqsetup;
-        int hwq_map[WME_NUM_AC];
         spinlock_t txbuflock;
         struct list_head txbuf;
         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
         struct ath_descdma txdma;
-        int pending_frames[WME_NUM_AC];
+        struct ath_txq *txq_map[WME_NUM_AC];
 };
 
 struct ath_rx_edma {
@@ -312,12 +305,13 @@ struct ath_rx {
         u8 rxotherant;
         u32 *rxlink;
         unsigned int rxfilter;
-        spinlock_t rxflushlock;
         spinlock_t rxbuflock;
         struct list_head rxbuf;
         struct ath_descdma rxdma;
         struct ath_buf *rx_bufptr;
         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
+
+        struct sk_buff *frag;
 };
 
 int ath_startrecv(struct ath_softc *sc);
@@ -329,8 +323,7 @@ void ath_rx_cleanup(struct ath_softc *sc);
 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
-int ath_tx_setup(struct ath_softc *sc, int haltype);
-void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
+bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 void ath_draintxq(struct ath_softc *sc,
                      struct ath_txq *txq, bool retry_tx);
 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
@@ -344,13 +337,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
                  struct ath_tx_control *txctl);
 void ath_tx_tasklet(struct ath_softc *sc);
 void ath_tx_edma_tasklet(struct ath_softc *sc);
-void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
-bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
-void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
-                       u16 tid, u16 *ssn);
+int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
+                      u16 tid, u16 *ssn);
 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
-void ath9k_enable_ps(struct ath_softc *sc);
+
+void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
+bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an);
 
 /********/
 /* VIFs */
@@ -358,11 +351,9 @@ void ath9k_enable_ps(struct ath_softc *sc);
 
 struct ath_vif {
         int av_bslot;
+        bool is_bslot_active, primary_sta_vif;
         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
-        enum nl80211_iftype av_opmode;
         struct ath_buf *av_bcbuf;
-        struct ath_tx_control av_btxctl;
-        u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 };
 
 /*******************/
@@ -374,14 +365,14 @@ struct ath_vif {
  * number of BSSIDs) if a given beacon does not go out even after waiting this
  * number of beacon intervals, the game's up.
  */
-#define BSTUCK_THRESH                   (9 * ATH_BCBUF)
+#define BSTUCK_THRESH                   9
 #define ATH_BCBUF                       4
 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 #define ATH_DEFAULT_BMISS_LIMIT         10
 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 
 struct ath_beacon_config {
-        u16 beacon_interval;
+        int beacon_interval;
         u16 listen_interval;
         u16 dtim_period;
         u16 bmiss_timeout;
@@ -398,22 +389,26 @@ struct ath_beacon {
         u32 beaconq;
         u32 bmisscnt;
         u32 ast_be_xmit;
-        u64 bc_tstamp;
+        u32 bc_tstamp;
         struct ieee80211_vif *bslot[ATH_BCBUF];
-        struct ath_wiphy *bslot_aphy[ATH_BCBUF];
         int slottime;
         int slotupdate;
         struct ath9k_tx_queue_info beacon_qi;
         struct ath_descdma bdma;
         struct ath_txq *cabq;
         struct list_head bbuf;
+
+        bool tx_processed;
+        bool tx_last;
 };
 
 void ath_beacon_tasklet(unsigned long data);
 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
-int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
+int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 int ath_beaconq_config(struct ath_softc *sc);
+void ath_set_beacon(struct ath_softc *sc);
+void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
 
 /*******/
 /* ANI */
@@ -423,12 +418,14 @@ int ath_beaconq_config(struct ath_softc *sc);
 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
+#define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 
 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 
 void ath_hw_check(struct work_struct *work);
+void ath_hw_pll_work(struct work_struct *work);
 void ath_paprd_calibrate(struct work_struct *work);
 void ath_ani_calibrate(unsigned long data);
 
@@ -436,14 +433,6 @@ void ath_ani_calibrate(unsigned long data);
 /* BTCOEX */
 /**********/
 
-/* Defines the BT AR_BT_COEX_WGHT used */
-enum ath_stomp_type {
-        ATH_BTCOEX_NO_STOMP,
-        ATH_BTCOEX_STOMP_ALL,
-        ATH_BTCOEX_STOMP_LOW,
-        ATH_BTCOEX_STOMP_NONE
-};
-
 struct ath_btcoex {
         bool hw_timer_enabled;
         spinlock_t btcoex_lock;
@@ -467,26 +456,75 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 
 #define ATH_LED_PIN_DEF                 1
 #define ATH_LED_PIN_9287                8
-#define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
-#define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
-
-enum ath_led_type {
-        ATH_LED_RADIO,
-        ATH_LED_ASSOC,
-        ATH_LED_TX,
-        ATH_LED_RX
-};
-
-struct ath_led {
-        struct ath_softc *sc;
-        struct led_classdev led_cdev;
-        enum ath_led_type led_type;
-        char name[32];
-        bool registered;
-};
+#define ATH_LED_PIN_9300                10
+#define ATH_LED_PIN_9485                6
 
+#ifdef CONFIG_MAC80211_LEDS
 void ath_init_leds(struct ath_softc *sc);
 void ath_deinit_leds(struct ath_softc *sc);
+#else
+static inline void ath_init_leds(struct ath_softc *sc)
+{
+}
+
+static inline void ath_deinit_leds(struct ath_softc *sc)
+{
+}
+#endif
+
+
+/* Antenna diversity/combining */
+#define ATH_ANT_RX_CURRENT_SHIFT 4
+#define ATH_ANT_RX_MAIN_SHIFT 2
+#define ATH_ANT_RX_MASK 0x3
+
+#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
+#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
+#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
+#define ATH_ANT_DIV_COMB_INIT_COUNT 95
+#define ATH_ANT_DIV_COMB_MAX_COUNT 100
+#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
+#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
+
+#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
+#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
+#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
+#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
+
+enum ath9k_ant_div_comb_lna_conf {
+        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
+        ATH_ANT_DIV_COMB_LNA2,
+        ATH_ANT_DIV_COMB_LNA1,
+        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
+};
+
+struct ath_ant_comb {
+        u16 count;
+        u16 total_pkt_count;
+        bool scan;
+        bool scan_not_start;
+        int main_total_rssi;
+        int alt_total_rssi;
+        int alt_recv_cnt;
+        int main_recv_cnt;
+        int rssi_lna1;
+        int rssi_lna2;
+        int rssi_add;
+        int rssi_sub;
+        int rssi_first;
+        int rssi_second;
+        int rssi_third;
+        bool alt_good;
+        int quick_scan_cnt;
+        int main_conf;
+        enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
+        enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
+        int first_bias;
+        int second_bias;
+        bool first_ratio;
+        bool second_ratio;
+        unsigned long scan_start_time;
+};
 
 /********************/
 /* Main driver core */
@@ -501,7 +539,6 @@ void ath_deinit_leds(struct ath_softc *sc);
 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 #define ATH_MAX_SW_RETRIES      10
 #define ATH_CHAN_MAX            255
-#define IEEE80211_WEP_NKID      4       /* number of key ids */
 
 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 #define ATH_RATE_DUMMY_MARKER   0
@@ -516,11 +553,12 @@ void ath_deinit_leds(struct ath_softc *sc);
 #define SC_OP_RXFLUSH                BIT(7)
 #define SC_OP_LED_ASSOCIATED         BIT(8)
 #define SC_OP_LED_ON                 BIT(9)
-#define SC_OP_SCANNING               BIT(10)
 #define SC_OP_TSF_RESET              BIT(11)
 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 #define SC_OP_BT_SCAN                BIT(13)
 #define SC_OP_ANI_RUN                BIT(14)
+#define SC_OP_ENABLE_APM             BIT(15)
+#define SC_OP_PRIM_STA_VIF           BIT(16)
 
 /* Powersave flags */
 #define PS_WAIT_FOR_BEACON        BIT(0)
@@ -528,103 +566,91 @@ void ath_deinit_leds(struct ath_softc *sc);
 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 #define PS_BEACON_SYNC            BIT(4)
-#define PS_NULLFUNC_COMPLETED     BIT(5)
-#define PS_ENABLED                BIT(6)
+#define PS_TSFOOR_SYNC            BIT(5)
 
-struct ath_wiphy;
 struct ath_rate_table;
 
+struct ath9k_vif_iter_data {
+        const u8 *hw_macaddr; /* phy's hardware address, set
+                               * before starting iteration for
+                               * valid bssid mask.
+                               */
+        u8 mask[ETH_ALEN]; /* bssid mask */
+        int naps;      /* number of AP vifs */
+        int nmeshes;   /* number of mesh vifs */
+        int nstations; /* number of station vifs */
+        int nwds;      /* number of nwd vifs */
+        int nadhocs;   /* number of adhoc vifs */
+        int nothers;   /* number of vifs not specified above. */
+};
+
 struct ath_softc {
         struct ieee80211_hw *hw;
         struct device *dev;
 
-        spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
-        struct ath_wiphy *pri_wiphy;
-        struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
-                                       * have NULL entries */
-        int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
         int chan_idx;
         int chan_is_ht;
-        struct ath_wiphy *next_wiphy;
-        struct work_struct chan_work;
-        int wiphy_select_failures;
-        unsigned long wiphy_select_first_fail;
-        struct delayed_work wiphy_work;
-        unsigned long wiphy_scheduler_int;
-        int wiphy_scheduler_index;
+        struct survey_info *cur_survey;
+        struct survey_info survey[ATH9K_NUM_CHANNELS];
 
         struct tasklet_struct intr_tq;
         struct tasklet_struct bcon_tasklet;
         struct ath_hw *sc_ah;
         void __iomem *mem;
         int irq;
-        spinlock_t sc_resetlock;
         spinlock_t sc_serial_rw;
         spinlock_t sc_pm_lock;
+        spinlock_t sc_pcu_lock;
         struct mutex mutex;
         struct work_struct paprd_work;
         struct work_struct hw_check_work;
         struct completion paprd_complete;
 
+        unsigned int hw_busy_count;
+
         u32 intrstatus;
         u32 sc_flags; /* SC_OP_* */
         u16 ps_flags; /* PS_* */
         u16 curtxpow;
-        u8 nbcnvifs;
-        u16 nvifs;
         bool ps_enabled;
         bool ps_idle;
+        short nbcnvifs;
+        short nvifs;
         unsigned long ps_usecount;
 
         struct ath_config config;
         struct ath_rx rx;
         struct ath_tx tx;
         struct ath_beacon beacon;
-        const struct ath_rate_table *cur_rate_table;
-        enum wireless_mode cur_rate_mode;
         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 
-        struct ath_led radio_led;
-        struct ath_led assoc_led;
-        struct ath_led tx_led;
-        struct ath_led rx_led;
-        struct delayed_work ath_led_blink_work;
-        int led_on_duration;
-        int led_off_duration;
-        int led_on_cnt;
-        int led_off_cnt;
+#ifdef CONFIG_MAC80211_LEDS
+        bool led_registered;
+        char led_name[32];
+        struct led_classdev led_cdev;
+#endif
 
-        int beacon_interval;
+        struct ath9k_hw_cal_data caldata;
+        int last_rssi;
 
 #ifdef CONFIG_ATH9K_DEBUGFS
         struct ath9k_debug debug;
+        spinlock_t nodes_lock;
+        struct list_head nodes; /* basically, stations */
+        unsigned int tx_complete_poll_work_seen;
 #endif
         struct ath_beacon_config cur_beacon_conf;
         struct delayed_work tx_complete_work;
+        struct delayed_work hw_pll_work;
         struct ath_btcoex btcoex;
 
         struct ath_descdma txsdma;
-};
 
-struct ath_wiphy {
-        struct ath_softc *sc; /* shared for all virtual wiphys */
-        struct ieee80211_hw *hw;
-        struct ath9k_hw_cal_data caldata;
-        enum ath_wiphy_state {
-                ATH_WIPHY_INACTIVE,
-                ATH_WIPHY_ACTIVE,
-                ATH_WIPHY_PAUSING,
-                ATH_WIPHY_PAUSED,
-                ATH_WIPHY_SCAN,
-        } state;
-        bool idle;
-        int chan_idx;
-        int chan_is_ht;
+        struct ath_ant_comb ant_comb;
 };
 
 void ath9k_tasklet(unsigned long data);
 int ath_reset(struct ath_softc *sc, bool retry_tx);
-int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 int ath_cabq_update(struct ath_softc *);
 
 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
@@ -633,25 +659,25 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 }
 
 extern struct ieee80211_ops ath9k_ops;
-extern int modparam_nohwcrypt;
+extern int ath9k_modparam_nohwcrypt;
 extern int led_blink;
+extern bool is_ath9k_unloaded;
 
 irqreturn_t ath_isr(int irq, void *dev);
+void ath9k_init_crypto(struct ath_softc *sc);
 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
                     const struct ath_bus_ops *bus_ops);
 void ath9k_deinit_device(struct ath_softc *sc);
 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
-void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
-                           struct ath9k_channel *ichan);
-void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                     struct ath9k_channel *hchan);
 
 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
+bool ath9k_uses_beacons(int type);
 
-#ifdef CONFIG_PCI
+#ifdef CONFIG_ATH9K_PCI
 int ath_pci_init(void);
 void ath_pci_exit(void);
 #else
@@ -659,7 +685,7 @@ static inline int ath_pci_init(void) { return 0; };
 static inline void ath_pci_exit(void) {};
 #endif
 
-#ifdef CONFIG_ATHEROS_AR71XX
+#ifdef CONFIG_ATH9K_AHB
 int ath_ahb_init(void);
 void ath_ahb_exit(void);
 #else
@@ -670,27 +696,13 @@ static inline void ath_ahb_exit(void) {};
 void ath9k_ps_wakeup(struct ath_softc *sc);
 void ath9k_ps_restore(struct ath_softc *sc);
 
-void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
-int ath9k_wiphy_add(struct ath_softc *sc);
-int ath9k_wiphy_del(struct ath_wiphy *aphy);
-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
-int ath9k_wiphy_pause(struct ath_wiphy *aphy);
-int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
-int ath9k_wiphy_select(struct ath_wiphy *aphy);
-void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
-void ath9k_wiphy_chan_work(struct work_struct *work);
-bool ath9k_wiphy_started(struct ath_softc *sc);
-void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
-                                  struct ath_wiphy *selected);
-bool ath9k_wiphy_scanning(struct ath_softc *sc);
-void ath9k_wiphy_work(struct work_struct *work);
-bool ath9k_all_wiphys_idle(struct ath_softc *sc);
-void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
-
-void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
-bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
+u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 
 void ath_start_rfkill_poll(struct ath_softc *sc);
 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
+void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               struct ath9k_vif_iter_data *iter_data);
+
 
 #endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 4d4b22d52dfd..d4d8ceced89b 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,12 @@
 
 #define FUDGE 2
 
+static void ath9k_reset_beacon_status(struct ath_softc *sc)
+{
+        sc->beacon.tx_processed = false;
+        sc->beacon.tx_last = false;
+}
+
 /*
  *  This function will modify certain transmit queue properties depending on
  *  the operating mode of the station (AP or AdHoc).  Parameters are AIFS
@@ -28,7 +34,7 @@ int ath_beaconq_config(struct ath_softc *sc)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info qi, qi_be;
-        int qnum;
+        struct ath_txq *txq;
 
         ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
@@ -38,16 +44,16 @@ int ath_beaconq_config(struct ath_softc *sc)
                 qi.tqi_cwmax = 0;
         } else {
                 /* Adhoc mode; important thing is to use 2x cwmin. */
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+                txq = sc->tx.txq_map[WME_AC_BE];
+                ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi_be);
                 qi.tqi_aifs = qi_be.tqi_aifs;
                 qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
                 qi.tqi_cwmax = qi_be.tqi_cwmax;
         }
 
         if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to update h/w beacon queue parameters\n");
+                ath_err(common,
+                        "Unable to update h/w beacon queue parameters\n");
                 return 0;
         } else {
                 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -57,8 +63,8 @@ int ath_beaconq_config(struct ath_softc *sc)
 
 /*
  *  Associates the beacon frame buffer with a transmit descriptor.  Will set
- *  up all required antenna switch parameters, rate codes, and channel flags.
- *  Beacons are always sent out at the lowest rate, and are not retried.
+ *  up rate codes, and channel flags. Beacons are always sent out at the
+ *  lowest rate, and are not retried.
 */
 static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
                              struct ath_buf *bf, int rateidx)
@@ -68,20 +74,16 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_desc *ds;
         struct ath9k_11n_rate_series series[4];
-        int flags, antenna, ctsrate = 0, ctsduration = 0;
+        int flags, ctsrate = 0, ctsduration = 0;
         struct ieee80211_supported_band *sband;
         u8 rate = 0;
 
+        ath9k_reset_beacon_status(sc);
+
         ds = bf->bf_desc;
         flags = ATH9K_TXDESC_NOACK;
 
         ds->ds_link = 0;
-        /*
-         * Switch antenna every beacon.
-         * Should only switch every beacon period, not for every SWBA
-         * XXX assumes two antennae
-         */
-        antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
 
         sband = &sc->sbands[common->hw->conf.channel->band];
         rate = sband->bitrates[rateidx].hw_value;
@@ -103,17 +105,35 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
         memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
         series[0].Tries = 1;
         series[0].Rate = rate;
-        series[0].ChSel = common->tx_chainmask;
+        series[0].ChSel = ath_txchainmask_reduction(sc,
+                        common->tx_chainmask, series[0].Rate);
         series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
         ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
                                      series, 4, 0);
 }
 
+static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_tx_control txctl;
+
+        memset(&txctl, 0, sizeof(struct ath_tx_control));
+        txctl.txq = sc->beacon.cabq;
+
+        ath_dbg(common, ATH_DBG_XMIT,
+                "transmitting CABQ packet, skb: %p\n", skb);
+
+        if (ath_tx_start(hw, skb, &txctl) != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n");
+                dev_kfree_skb_any(skb);
+        }
+}
+
 static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
                                            struct ieee80211_vif *vif)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_buf *bf;
         struct ath_vif *avp;
@@ -122,13 +142,12 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
         struct ieee80211_tx_info *info;
         int cabq_depth;
 
-        if (aphy->state != ATH_WIPHY_ACTIVE)
-                return NULL;
+        ath9k_reset_beacon_status(sc);
 
         avp = (void *)vif->drv_priv;
         cabq = sc->beacon.cabq;
 
-        if (avp->av_bcbuf == NULL)
+        if ((avp->av_bcbuf == NULL) || !avp->is_bslot_active)
                 return NULL;
 
         /* Release the old beacon first */
@@ -136,9 +155,10 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
         bf = avp->av_bcbuf;
         skb = bf->bf_mpdu;
         if (skb) {
-                dma_unmap_single(sc->dev, bf->bf_dmacontext,
+                dma_unmap_single(sc->dev, bf->bf_buf_addr,
                                  skb->len, DMA_TO_DEVICE);
                 dev_kfree_skb_any(skb);
+                bf->bf_buf_addr = 0;
         }
 
         /* Get a new beacon from mac80211 */
@@ -162,14 +182,13 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
         }
 
-        bf->bf_buf_addr = bf->bf_dmacontext =
-                dma_map_single(sc->dev, skb->data,
-                               skb->len, DMA_TO_DEVICE);
+        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+                                         skb->len, DMA_TO_DEVICE);
         if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
-                ath_print(common, ATH_DBG_FATAL,
-                          "dma_mapping_error on beaconing\n");
+                bf->bf_buf_addr = 0;
+                ath_err(common, "dma_mapping_error on beaconing\n");
                 return NULL;
         }
 
@@ -189,8 +208,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
 
         if (skb && cabq_depth) {
                 if (sc->nvifs > 1) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "Flushing previous cabq traffic\n");
+                        ath_dbg(common, ATH_DBG_BEACON,
+                                "Flushing previous cabq traffic\n");
                         ath_draintxq(sc, cabq, false);
                 }
         }
@@ -205,13 +224,13 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
         return bf;
 }
 
-int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
+int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
 {
-        struct ath_softc *sc = aphy->sc;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_vif *avp;
         struct ath_buf *bf;
         struct sk_buff *skb;
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         __le64 tstamp;
 
         avp = (void *)vif->drv_priv;
@@ -224,9 +243,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                                                  struct ath_buf, list);
                 list_del(&avp->av_bcbuf->list);
 
-                if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
-                    sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC ||
-                    sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) {
+                if (ath9k_uses_beacons(vif->type)) {
                         int slot;
                         /*
                          * Assign the vif to a beacon xmit slot. As
@@ -236,6 +253,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                         for (slot = 0; slot < ATH_BCBUF; slot++)
                                 if (sc->beacon.bslot[slot] == NULL) {
                                         avp->av_bslot = slot;
+                                        avp->is_bslot_active = false;
 
                                         /* NB: keep looking for a double slot */
                                         if (slot == 0 || !sc->beacon.bslot[slot-1])
@@ -243,7 +261,6 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                                 }
                         BUG_ON(sc->beacon.bslot[avp->av_bslot] != NULL);
                         sc->beacon.bslot[avp->av_bslot] = vif;
-                        sc->beacon.bslot_aphy[avp->av_bslot] = aphy;
                         sc->nbcnvifs++;
                 }
         }
@@ -252,27 +269,26 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
         bf = avp->av_bcbuf;
         if (bf->bf_mpdu != NULL) {
                 skb = bf->bf_mpdu;
-                dma_unmap_single(sc->dev, bf->bf_dmacontext,
+                dma_unmap_single(sc->dev, bf->bf_buf_addr,
                                  skb->len, DMA_TO_DEVICE);
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
+                bf->bf_buf_addr = 0;
         }
 
         /* NB: the beacon data buffer must be 32-bit aligned. */
         skb = ieee80211_beacon_get(sc->hw, vif);
-        if (skb == NULL) {
-                ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
+        if (skb == NULL)
                 return -ENOMEM;
-        }
 
         tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
-        sc->beacon.bc_tstamp = le64_to_cpu(tstamp);
+        sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp);
         /* Calculate a TSF adjustment factor required for staggered beacons. */
         if (avp->av_bslot > 0) {
                 u64 tsfadjust;
                 int intval;
 
-                intval = sc->beacon_interval ? : ATH_DEFAULT_BINTVAL;
+                intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
 
                 /*
                  * Calculate the TSF offset for this beacon slot, i.e., the
@@ -282,13 +298,12 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                  * adjustment. Other slots are adjusted to get the timestamp
                  * close to the TBTT for the BSS.
                  */
-                tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
-                avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
+                tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
+                avp->tsf_adjust = cpu_to_le64(tsfadjust);
 
-                ath_print(common, ATH_DBG_BEACON,
-                          "stagger beacons, bslot %d intval "
-                          "%u tsfadjust %llu\n",
-                          avp->av_bslot, intval, (unsigned long long)tsfadjust);
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
+                        avp->av_bslot, intval, (unsigned long long)tsfadjust);
 
                 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
                         avp->tsf_adjust;
@@ -296,16 +311,16 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                 avp->tsf_adjust = cpu_to_le64(0);
 
         bf->bf_mpdu = skb;
-        bf->bf_buf_addr = bf->bf_dmacontext =
-                dma_map_single(sc->dev, skb->data,
-                               skb->len, DMA_TO_DEVICE);
+        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+                                         skb->len, DMA_TO_DEVICE);
         if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
-                ath_print(common, ATH_DBG_FATAL,
-                          "dma_mapping_error on beacon alloc\n");
+                bf->bf_buf_addr = 0;
+                ath_err(common, "dma_mapping_error on beacon alloc\n");
                 return -ENOMEM;
         }
+        avp->is_bslot_active = true;
 
         return 0;
 }
@@ -315,19 +330,21 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
         if (avp->av_bcbuf != NULL) {
                 struct ath_buf *bf;
 
+                avp->is_bslot_active = false;
                 if (avp->av_bslot != -1) {
                         sc->beacon.bslot[avp->av_bslot] = NULL;
-                        sc->beacon.bslot_aphy[avp->av_bslot] = NULL;
                         sc->nbcnvifs--;
+                        avp->av_bslot = -1;
                 }
 
                 bf = avp->av_bcbuf;
                 if (bf->bf_mpdu != NULL) {
                         struct sk_buff *skb = bf->bf_mpdu;
-                        dma_unmap_single(sc->dev, bf->bf_dmacontext,
+                        dma_unmap_single(sc->dev, bf->bf_buf_addr,
                                          skb->len, DMA_TO_DEVICE);
                         dev_kfree_skb_any(skb);
                         bf->bf_mpdu = NULL;
+                        bf->bf_buf_addr = 0;
                 }
                 list_add_tail(&bf->list, &sc->beacon.bbuf);
 
@@ -338,15 +355,13 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
 void ath_beacon_tasklet(unsigned long data)
 {
         struct ath_softc *sc = (struct ath_softc *)data;
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_buf *bf = NULL;
         struct ieee80211_vif *vif;
-        struct ath_wiphy *aphy;
         int slot;
-        u32 bfaddr, bc = 0, tsftu;
-        u64 tsf;
-        u16 intval;
+        u32 bfaddr, bc = 0;
 
         /*
          * Check if the previous beacon has gone out.  If
@@ -358,60 +373,65 @@ void ath_beacon_tasklet(unsigned long data)
         if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0) {
                 sc->beacon.bmisscnt++;
 
-                if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "missed %u consecutive beacons\n",
-                                  sc->beacon.bmisscnt);
+                if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "missed %u consecutive beacons\n",
+                                sc->beacon.bmisscnt);
+                        ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+                        if (sc->beacon.bmisscnt > 3)
+                                ath9k_hw_bstuck_nfcal(ah);
                 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "beacon is officially stuck\n");
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "beacon is officially stuck\n");
                         sc->sc_flags |= SC_OP_TSF_RESET;
-                        ath_reset(sc, false);
+                        ath_reset(sc, true);
                 }
 
                 return;
         }
 
-        if (sc->beacon.bmisscnt != 0) {
-                ath_print(common, ATH_DBG_BEACON,
-                          "resume beacon xmit after %u misses\n",
-                          sc->beacon.bmisscnt);
-                sc->beacon.bmisscnt = 0;
-        }
-
         /*
          * Generate beacon frames. we are sending frames
          * staggered so calculate the slot for this frame based
          * on the tsf to safeguard against missing an swba.
          */
 
-        intval = sc->beacon_interval ? : ATH_DEFAULT_BINTVAL;
 
-        tsf = ath9k_hw_gettsf64(ah);
-        tsftu = TSF_TO_TU(tsf>>32, tsf);
-        slot = ((tsftu % intval) * ATH_BCBUF) / intval;
-        /*
-         * Reverse the slot order to get slot 0 on the TBTT offset that does
-         * not require TSF adjustment and other slots adding
-         * slot/ATH_BCBUF * beacon_int to timestamp. For example, with
-         * ATH_BCBUF = 4, we process beacon slots as follows: 3 2 1 0 3 2 1 ..
-         * and slot 0 is at correct offset to TBTT.
-         */
-        slot = ATH_BCBUF - slot - 1;
-        vif = sc->beacon.bslot[slot];
-        aphy = sc->beacon.bslot_aphy[slot];
+        if (ah->opmode == NL80211_IFTYPE_AP) {
+                u16 intval;
+                u32 tsftu;
+                u64 tsf;
+
+                intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
+                tsf = ath9k_hw_gettsf64(ah);
+                tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
+                tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
+                slot = (tsftu % (intval * ATH_BCBUF)) / intval;
+                vif = sc->beacon.bslot[slot];
+
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
+                        slot, tsf, tsftu / ATH_BCBUF, intval, vif);
+        } else {
+                slot = 0;
+                vif = sc->beacon.bslot[slot];
+        }
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
-                  slot, tsf, tsftu, intval, vif);
 
         bfaddr = 0;
         if (vif) {
-                bf = ath_beacon_generate(aphy->hw, vif);
+                bf = ath_beacon_generate(sc->hw, vif);
                 if (bf != NULL) {
                         bfaddr = bf->bf_daddr;
                         bc = 1;
                 }
+
+                if (sc->beacon.bmisscnt != 0) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "resume beacon xmit after %u misses\n",
+                                sc->beacon.bmisscnt);
+                        sc->beacon.bmisscnt = 0;
+                }
         }
 
         /*
@@ -439,16 +459,6 @@ void ath_beacon_tasklet(unsigned long data)
                 sc->beacon.updateslot = OK;
         }
         if (bfaddr != 0) {
-                /*
-                 * Stop any current dma and put the new frame(s) on the queue.
-                 * This should never fail since we check above that no frames
-                 * are still pending on the queue.
-                 */
-                if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                "beacon queue %u did not stop?\n", sc->beacon.beaconq);
-                }
-
                 /* NB: cabq traffic should already be queued and primed */
                 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
                 ath9k_hw_txstart(ah, sc->beacon.beaconq);
@@ -461,13 +471,17 @@ static void ath9k_beacon_init(struct ath_softc *sc,
                               u32 next_beacon,
                               u32 beacon_period)
 {
-        if (beacon_period & ATH9K_BEACON_RESET_TSF)
+        if (sc->sc_flags & SC_OP_TSF_RESET) {
                 ath9k_ps_wakeup(sc);
+                ath9k_hw_reset_tsf(sc->sc_ah);
+        }
 
         ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
 
-        if (beacon_period & ATH9K_BEACON_RESET_TSF)
+        if (sc->sc_flags & SC_OP_TSF_RESET) {
                 ath9k_ps_restore(sc);
+                sc->sc_flags &= ~SC_OP_TSF_RESET;
+        }
 }
 
 /*
@@ -482,32 +496,23 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
         u32 nexttbtt, intval;
 
         /* NB: the beacon interval is kept internally in TU's */
-        intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
+        intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
         intval /= ATH_BCBUF;    /* for staggered beacons */
         nexttbtt = intval;
 
-        if (sc->sc_flags & SC_OP_TSF_RESET)
-                intval |= ATH9K_BEACON_RESET_TSF;
-
         /*
          * In AP mode we enable the beacon timers and SWBA interrupts to
          * prepare beacon frames.
          */
-        intval |= ATH9K_BEACON_ENA;
         ah->imask |= ATH9K_INT_SWBA;
         ath_beaconq_config(sc);
 
         /* Set the computed AP beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_beacon_init(sc, nexttbtt, intval);
         sc->beacon.bmisscnt = 0;
         ath9k_hw_set_interrupts(ah, ah->imask);
-
-        /* Clear the reset TSF flag, so that subsequent beacon updation
-           will not reset the HW TSF. */
-
-        sc->sc_flags &= ~SC_OP_TSF_RESET;
 }
 
 /*
@@ -532,8 +537,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
 
         /* No need to configure beacon if we are not associated */
         if (!common->curaid) {
-                ath_print(common, ATH_DBG_BEACON,
-                         "STA is not yet associated..skipping beacon config\n");
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "STA is not yet associated..skipping beacon config\n");
                 return;
         }
 
@@ -545,8 +550,6 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
          * last beacon we received (which may be none).
          */
         dtimperiod = conf->dtim_period;
-        if (dtimperiod <= 0)            /* NB: 0 if not known */
-                dtimperiod = 1;
         dtimcount = conf->dtim_count;
         if (dtimcount >= dtimperiod)    /* NB: sanity check */
                 dtimcount = 0;
@@ -554,8 +557,6 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
         cfpcount = 0;
 
         sleepduration = conf->listen_interval * intval;
-        if (sleepduration <= 0)
-                sleepduration = intval;
 
         /*
          * Pull nexttbtt forward to reflect the current
@@ -626,89 +627,135 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
         /* TSF out of range threshold fixed at 1 second */
         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
 
-        ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
-        ath_print(common, ATH_DBG_BEACON,
-                  "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
-                  bs.bs_bmissthreshold, bs.bs_sleepduration,
-                  bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
+        ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+                bs.bs_bmissthreshold, bs.bs_sleepduration,
+                bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
 
         /* Set the computed STA beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_hw_set_sta_beacon_timers(ah, &bs);
         ah->imask |= ATH9K_INT_BMISS;
-        ath9k_hw_set_interrupts(ah, ah->imask);
+
+        /*
+         * If the beacon config is called beacause of TSFOOR,
+         * Interrupts will be enabled back at the end of ath9k_tasklet
+         */
+        if (!(sc->ps_flags & PS_TSFOOR_SYNC))
+                ath9k_hw_set_interrupts(ah, ah->imask);
 }
 
 static void ath_beacon_config_adhoc(struct ath_softc *sc,
-                                    struct ath_beacon_config *conf,
-                                    struct ieee80211_vif *vif)
+                                    struct ath_beacon_config *conf)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
-        u64 tsf;
-        u32 tsftu, intval, nexttbtt;
-
-        intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
-
+        u32 tsf, delta, intval, nexttbtt;
 
-        /* Pull nexttbtt forward to reflect the current TSF */
+        ath9k_reset_beacon_status(sc);
 
-        nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
-        if (nexttbtt == 0)
-                nexttbtt = intval;
-        else if (intval)
-                nexttbtt = roundup(nexttbtt, intval);
+        tsf = ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE);
+        intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
 
-        tsf = ath9k_hw_gettsf64(ah);
-        tsftu = TSF_TO_TU((u32)(tsf>>32), (u32)tsf) + FUDGE;
-        do {
-                nexttbtt += intval;
-        } while (nexttbtt < tsftu);
+        if (!sc->beacon.bc_tstamp)
+                nexttbtt = tsf + intval;
+        else {
+                if (tsf > sc->beacon.bc_tstamp)
+                        delta = (tsf - sc->beacon.bc_tstamp);
+                else
+                        delta = (tsf + 1 + (~0U - sc->beacon.bc_tstamp));
+                nexttbtt = tsf + intval - (delta % intval);
+        }
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "IBSS nexttbtt %u intval %u (%u)\n",
-                  nexttbtt, intval, conf->beacon_interval);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "IBSS nexttbtt %u intval %u (%u)\n",
+                nexttbtt, intval, conf->beacon_interval);
 
         /*
          * In IBSS mode enable the beacon timers but only enable SWBA interrupts
          * if we need to manually prepare beacon frames.  Otherwise we use a
          * self-linked tx descriptor and let the hardware deal with things.
          */
-        intval |= ATH9K_BEACON_ENA;
         ah->imask |= ATH9K_INT_SWBA;
 
         ath_beaconq_config(sc);
 
         /* Set the computed ADHOC beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_beacon_init(sc, nexttbtt, intval);
         sc->beacon.bmisscnt = 0;
-        ath9k_hw_set_interrupts(ah, ah->imask);
+        /*
+         * If the beacon config is called beacause of TSFOOR,
+         * Interrupts will be enabled back at the end of ath9k_tasklet
+         */
+        if (!(sc->ps_flags & PS_TSFOOR_SYNC))
+                ath9k_hw_set_interrupts(ah, ah->imask);
 }
 
-void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
+static bool ath9k_allow_beacon_config(struct ath_softc *sc,
+                                      struct ieee80211_vif *vif)
 {
         struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        enum nl80211_iftype iftype;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath_vif *avp = (void *)vif->drv_priv;
 
-        /* Setup the beacon configuration parameters */
-        if (vif) {
-                struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        /*
+         * Can not have different beacon interval on multiple
+         * AP interface case
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+            (sc->nbcnvifs > 1) &&
+            (vif->type == NL80211_IFTYPE_AP) &&
+            (cur_conf->beacon_interval != bss_conf->beacon_int)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Changing beacon interval of multiple \
+                        AP interfaces !\n");
+                return false;
+        }
+        /*
+         * Can not configure station vif's beacon config
+         * while on AP opmode
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+            (vif->type != NL80211_IFTYPE_AP)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "STA vif's beacon not allowed on AP mode\n");
+                return false;
+        }
+        /*
+         * Do not allow beacon config if HW was already configured
+         * with another STA vif
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+            (vif->type == NL80211_IFTYPE_STATION) &&
+            (sc->sc_flags & SC_OP_BEACONS) &&
+            !avp->primary_sta_vif) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Beacon already configured for a station interface\n");
+                return false;
+        }
+        return true;
+}
 
-                iftype = vif->type;
+void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
+{
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
 
-                cur_conf->beacon_interval = bss_conf->beacon_int;
-                cur_conf->dtim_period = bss_conf->dtim_period;
-                cur_conf->listen_interval = 1;
-                cur_conf->dtim_count = 1;
-                cur_conf->bmiss_timeout =
-                        ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
-        } else {
-                iftype = sc->sc_ah->opmode;
-        }
+        if (!ath9k_allow_beacon_config(sc, vif))
+                return;
+
+        /* Setup the beacon configuration parameters */
+        cur_conf->beacon_interval = bss_conf->beacon_int;
+        cur_conf->dtim_period = bss_conf->dtim_period;
+        cur_conf->listen_interval = 1;
+        cur_conf->dtim_count = 1;
+        cur_conf->bmiss_timeout =
+                ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
 
         /*
          * It looks like mac80211 may end up using beacon interval of zero in
@@ -719,22 +766,80 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
         if (cur_conf->beacon_interval == 0)
                 cur_conf->beacon_interval = 100;
 
-        switch (iftype) {
+        /*
+         * We don't parse dtim period from mac80211 during the driver
+         * initialization as it breaks association with hidden-ssid
+         * AP and it causes latency in roaming
+         */
+        if (cur_conf->dtim_period == 0)
+                cur_conf->dtim_period = 1;
+
+        ath_set_beacon(sc);
+}
+
+static bool ath_has_valid_bslot(struct ath_softc *sc)
+{
+        struct ath_vif *avp;
+        int slot;
+        bool found = false;
+
+        for (slot = 0; slot < ATH_BCBUF; slot++) {
+                if (sc->beacon.bslot[slot]) {
+                        avp = (void *)sc->beacon.bslot[slot]->drv_priv;
+                        if (avp->is_bslot_active) {
+                                found = true;
+                                break;
+                        }
+                }
+        }
+        return found;
+}
+
+
+void ath_set_beacon(struct ath_softc *sc)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+
+        switch (sc->sc_ah->opmode) {
         case NL80211_IFTYPE_AP:
-                ath_beacon_config_ap(sc, cur_conf);
+                if (ath_has_valid_bslot(sc))
+                        ath_beacon_config_ap(sc, cur_conf);
                 break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
-                ath_beacon_config_adhoc(sc, cur_conf, vif);
+                ath_beacon_config_adhoc(sc, cur_conf);
                 break;
         case NL80211_IFTYPE_STATION:
                 ath_beacon_config_sta(sc, cur_conf);
                 break;
         default:
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unsupported beaconing mode\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
                 return;
         }
 
         sc->sc_flags |= SC_OP_BEACONS;
 }
+
+void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
+{
+        struct ath_hw *ah = sc->sc_ah;
+
+        if (!ath_has_valid_bslot(sc))
+                return;
+
+        ath9k_ps_wakeup(sc);
+        if (status) {
+                /* Re-enable beaconing */
+                ah->imask |= ATH9K_INT_SWBA;
+                ath9k_hw_set_interrupts(ah, ah->imask);
+        } else {
+                /* Disable SWBA interrupt */
+                ah->imask &= ~ATH9K_INT_SWBA;
+                ath9k_hw_set_interrupts(ah, ah->imask);
+                tasklet_kill(&sc->bcon_tasklet);
+                ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+        }
+        ath9k_ps_restore(sc);
+}
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index fb4ac15f3b93..41ce0b139886 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -35,29 +35,6 @@ struct ath_btcoex_config {
         bool bt_hold_rx_clear;
 };
 
-static const u16 ath_subsysid_tbl[] = {
-        AR9280_COEX2WIRE_SUBSYSID,
-        AT9285_COEX3WIRE_SA_SUBSYSID,
-        AT9285_COEX3WIRE_DA_SUBSYSID
-};
-
-/*
- * Checks the subsystem id of the device to see if it
- * supports btcoex
- */
-bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
-{
-        int i;
-
-        if (!ah->hw_version.subsysid)
-                return false;
-
-        for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
-                if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
-                        return true;
-
-        return false;
-}
 
 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
 {
@@ -74,6 +51,10 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
                 .bt_hold_rx_clear = true,
         };
         u32 i;
+        bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
+
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
 
         btcoex_hw->bt_coex_mode =
                 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
@@ -82,7 +63,7 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
                 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
                 SM(ath_bt_config.bt_mode, AR_BT_MODE) |
                 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
-                SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
+                SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
                 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
                 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
                 SM(qnum, AR_BT_QCU_THRESH);
@@ -165,18 +146,39 @@ void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
 }
 EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
 
+
 static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
 {
         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
+        u32  val;
 
         /*
          * Program coex mode and weight registers to
          * enable coex 3-wire
          */
         REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
-        REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
         REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
 
+
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ah->bt_coex_wlan_weight[0]);
+                REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ah->bt_coex_wlan_weight[1]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ah->bt_coex_bt_weight[0]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ah->bt_coex_bt_weight[1]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ah->bt_coex_bt_weight[2]);
+                REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ah->bt_coex_bt_weight[3]);
+
+        } else
+                REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
+
+
+
+        if (AR_SREV_9271(ah)) {
+                val = REG_READ(ah, 0x50040);
+                val &= 0xFFFFFEFF;
+                REG_WRITE(ah, 0x50040, val);
+        }
+
         REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
         REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
 
@@ -218,10 +220,86 @@ void ath9k_hw_btcoex_disable(struct ath_hw *ah)
 
         if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
                 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
-                REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
                 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
+
+                if (AR_SREV_9300_20_OR_LATER(ah)) {
+                        REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
+                        REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
+                        REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
+                } else
+                        REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
+
         }
 
         ah->btcoex_hw.enabled = false;
 }
 EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
+
+static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
+                         enum ath_stomp_type stomp_type)
+{
+        ah->bt_coex_bt_weight[0] = AR9300_BT_WGHT;
+        ah->bt_coex_bt_weight[1] = AR9300_BT_WGHT;
+        ah->bt_coex_bt_weight[2] = AR9300_BT_WGHT;
+        ah->bt_coex_bt_weight[3] = AR9300_BT_WGHT;
+
+
+        switch (stomp_type) {
+        case ATH_BTCOEX_STOMP_ALL:
+                ah->bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
+                ah->bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
+                break;
+        case ATH_BTCOEX_STOMP_LOW:
+                ah->bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
+                ah->bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
+                break;
+        case ATH_BTCOEX_STOMP_NONE:
+                ah->bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
+                ah->bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
+                break;
+
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "Invalid Stomptype\n");
+                break;
+        }
+
+        ath9k_hw_btcoex_enable(ah);
+}
+
+/*
+ * Configures appropriate weight based on stomp type.
+ */
+void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
+                              enum ath_stomp_type stomp_type)
+{
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                ar9003_btcoex_bt_stomp(ah, stomp_type);
+                return;
+        }
+
+        switch (stomp_type) {
+        case ATH_BTCOEX_STOMP_ALL:
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                AR_STOMP_ALL_WLAN_WGHT);
+                break;
+        case ATH_BTCOEX_STOMP_LOW:
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                AR_STOMP_LOW_WLAN_WGHT);
+                break;
+        case ATH_BTCOEX_STOMP_NONE:
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                AR_STOMP_NONE_WLAN_WGHT);
+                break;
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "Invalid Stomptype\n");
+                break;
+        }
+
+        ath9k_hw_btcoex_enable(ah);
+}
+EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 1ee5a15ccbb1..234f77689b14 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,9 +19,13 @@
 
 #include "hw.h"
 
-#define ATH_WLANACTIVE_GPIO     5
-#define ATH_BTACTIVE_GPIO       6
-#define ATH_BTPRIORITY_GPIO     7
+#define ATH_WLANACTIVE_GPIO_9280     5
+#define ATH_BTACTIVE_GPIO_9280       6
+#define ATH_BTPRIORITY_GPIO_9285     7
+
+#define ATH_WLANACTIVE_GPIO_9300     5
+#define ATH_BTACTIVE_GPIO_9300       4
+#define ATH_BTPRIORITY_GPIO_9300     8
 
 #define ATH_BTCOEX_DEF_BT_PERIOD  45
 #define ATH_BTCOEX_DEF_DUTY_CYCLE 55
@@ -32,6 +36,14 @@
 #define ATH_BT_CNT_THRESHOLD           3
 #define ATH_BT_CNT_SCAN_THRESHOLD      15
 
+/* Defines the BT AR_BT_COEX_WGHT used */
+enum ath_stomp_type {
+        ATH_BTCOEX_NO_STOMP,
+        ATH_BTCOEX_STOMP_ALL,
+        ATH_BTCOEX_STOMP_LOW,
+        ATH_BTCOEX_STOMP_NONE
+};
+
 enum ath_btcoex_scheme {
         ATH_BTCOEX_CFG_NONE,
         ATH_BTCOEX_CFG_2WIRE,
@@ -49,7 +61,6 @@ struct ath_btcoex_hw {
         u32 bt_coex_mode2;      /* Register setting for AR_BT_COEX_MODE2 */
 };
 
-bool ath9k_hw_btcoex_supported(struct ath_hw *ah);
 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah);
 void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah);
 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum);
@@ -58,5 +69,7 @@ void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
                                 u32 wlan_weight);
 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
 void ath9k_hw_btcoex_disable(struct ath_hw *ah);
+void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
+                              enum ath_stomp_type stomp_type);
 
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 45208690c0ec..a1250c586e40 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,8 +19,7 @@
 
 /* Common calibration code */
 
-/* We can tune this as we go by monitoring really low values */
-#define ATH9K_NF_TOO_LOW        -60
+#define ATH9K_NF_TOO_HIGH       -60
 
 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
 {
@@ -45,12 +44,46 @@ static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
         return nfval;
 }
 
-static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
+static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah,
+                                                    struct ath9k_channel *chan)
+{
+        struct ath_nf_limits *limit;
+
+        if (!chan || IS_CHAN_2GHZ(chan))
+                limit = &ah->nf_2g;
+        else
+                limit = &ah->nf_5g;
+
+        return limit;
+}
+
+static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
+                                   struct ath9k_channel *chan)
+{
+        return ath9k_hw_get_nf_limits(ah, chan)->nominal;
+}
+
+
+static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
+                                              struct ath9k_hw_cal_data *cal,
                                               int16_t *nfarray)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_conf *conf = &common->hw->conf;
+        struct ath_nf_limits *limit;
+        struct ath9k_nfcal_hist *h;
+        bool high_nf_mid = false;
+        u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
         int i;
 
+        h = cal->nfCalHist;
+        limit = ath9k_hw_get_nf_limits(ah, ah->curchan);
+
         for (i = 0; i < NUM_NF_READINGS; i++) {
+                if (!(chainmask & (1 << i)) ||
+                    ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf)))
+                        continue;
+
                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
 
                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
@@ -63,7 +96,39 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
                         h[i].privNF =
                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
                 }
+
+                if (!h[i].privNF)
+                        continue;
+
+                if (h[i].privNF > limit->max) {
+                        high_nf_mid = true;
+
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NFmid[%d] (%d) > MAX (%d), %s\n",
+                                i, h[i].privNF, limit->max,
+                                (cal->nfcal_interference ?
+                                 "not corrected (due to interference)" :
+                                 "correcting to MAX"));
+
+                        /*
+                         * Normally we limit the average noise floor by the
+                         * hardware specific maximum here. However if we have
+                         * encountered stuck beacons because of interference,
+                         * we bypass this limit here in order to better deal
+                         * with our environment.
+                         */
+                        if (!cal->nfcal_interference)
+                                h[i].privNF = limit->max;
+                }
         }
+
+        /*
+         * If the noise floor seems normal for all chains, assume that
+         * there is no significant interference in the environment anymore.
+         * Re-enable the enforcement of the NF maximum again.
+         */
+        if (!high_nf_mid)
+                cal->nfcal_interference = false;
 }
 
 static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
@@ -104,19 +169,6 @@ void ath9k_hw_reset_calibration(struct ath_hw *ah,
         ah->cal_samples = 0;
 }
 
-static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
-                                   struct ath9k_channel *chan)
-{
-        struct ath_nf_limits *limit;
-
-        if (!chan || IS_CHAN_2GHZ(chan))
-                limit = &ah->nf_2g;
-        else
-                limit = &ah->nf_5g;
-
-        return limit->nominal;
-}
-
 /* This is done for the currently configured channel */
 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
 {
@@ -134,18 +186,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
                 return true;
 
         if (currCal->calState != CAL_DONE) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Calibration state incorrect, %d\n",
-                          currCal->calState);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Calibration state incorrect, %d\n",
+                        currCal->calState);
                 return true;
         }
 
-        if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
+        if (!(ah->supp_cals & currCal->calData->calType))
                 return true;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "Resetting Cal %d state for channel %u\n",
-                  currCal->calData->calType, conf->channel->center_freq);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "Resetting Cal %d state for channel %u\n",
+                currCal->calData->calType, conf->channel->center_freq);
 
         ah->caldata->CalValid &= ~currCal->calData->calType;
         currCal->calState = CAL_WAITING;
@@ -179,6 +231,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
         int32_t val;
         u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_conf *conf = &common->hw->conf;
         s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
 
         if (ah->caldata)
@@ -188,6 +241,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
                 if (chainmask & (1 << i)) {
                         s16 nfval;
 
+                        if ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf))
+                                continue;
+
                         if (h)
                                 nfval = h[i].privNF;
                         else
@@ -216,7 +272,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
          * since 250us often results in NF load timeout and causes deaf
          * condition during stress testing 12/12/2009
          */
-        for (j = 0; j < 1000; j++) {
+        for (j = 0; j < 10000; j++) {
                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
                      AR_PHY_AGC_CONTROL_NF) == 0)
                         break;
@@ -232,10 +288,10 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
          * here, the baseband nf cal will just be capped by our present
          * noisefloor until the next calibration timer.
          */
-        if (j == 1000) {
-                ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
-                          "to load: AR_PHY_AGC_CONTROL=0x%x\n",
-                          REG_READ(ah, AR_PHY_AGC_CONTROL));
+        if (j == 10000) {
+                ath_dbg(common, ATH_DBG_ANY,
+                        "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
+                        REG_READ(ah, AR_PHY_AGC_CONTROL));
                 return;
         }
 
@@ -247,6 +303,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
         ENABLE_REGWRITE_BUFFER(ah);
         for (i = 0; i < NUM_NF_READINGS; i++) {
                 if (chainmask & (1 << i)) {
+                        if ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf))
+                                continue;
+
                         val = REG_READ(ah, ah->nf_regs[i]);
                         val &= 0xFFFFFE00;
                         val |= (((u32) (-50) << 1) & 0x1ff);
@@ -254,7 +313,6 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
                 }
         }
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 
@@ -273,19 +331,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
                 if (!nf[i])
                         continue;
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "NF calibrated [%s] [chain %d] is %d\n",
-                          (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "NF calibrated [%s] [chain %d] is %d\n",
+                        (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
 
-                if (nf[i] > limit->max) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NF[%d] (%d) > MAX (%d), correcting to MAX",
-                                  i, nf[i], limit->max);
+                if (nf[i] > ATH9K_NF_TOO_HIGH) {
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
+                                i, nf[i], ATH9K_NF_TOO_HIGH);
                         nf[i] = limit->max;
                 } else if (nf[i] < limit->min) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NF[%d] (%d) < MIN (%d), correcting to NOM",
-                                  i, nf[i], limit->min);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
+                                i, nf[i], limit->min);
                         nf[i] = limit->nominal;
                 }
         }
@@ -300,34 +358,33 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
         struct ieee80211_channel *c = chan->chan;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
 
-        if (!caldata)
-                return false;
-
         chan->channelFlags &= (~CHANNEL_CW_INT);
         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "NF did not complete in calibration window\n");
-                nf = 0;
-                caldata->rawNoiseFloor = nf;
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "NF did not complete in calibration window\n");
+                return false;
+        }
+
+        ath9k_hw_do_getnf(ah, nfarray);
+        ath9k_hw_nf_sanitize(ah, nfarray);
+        nf = nfarray[0];
+        if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
+            && nf > nfThresh) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "noise floor failed detected; detected %d, threshold %d\n",
+                        nf, nfThresh);
+                chan->channelFlags |= CHANNEL_CW_INT;
+        }
+
+        if (!caldata) {
+                chan->noisefloor = nf;
                 return false;
-        } else {
-                ath9k_hw_do_getnf(ah, nfarray);
-                ath9k_hw_nf_sanitize(ah, nfarray);
-                nf = nfarray[0];
-                if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
-                    && nf > nfThresh) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "noise floor failed detected; "
-                                  "detected %d, threshold %d\n",
-                                  nf, nfThresh);
-                        chan->channelFlags |= CHANNEL_CW_INT;
-                }
         }
 
         h = caldata->nfCalHist;
         caldata->nfcal_pending = false;
-        ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
-        caldata->rawNoiseFloor = h[0].privNF;
+        ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
+        chan->noisefloor = h[0].privNF;
         return true;
 }
 
@@ -338,9 +395,8 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
         s16 default_nf;
         int i, j;
 
-        if (!ah->caldata)
-                return;
-
+        ah->caldata->channel = chan->channel;
+        ah->caldata->channelFlags = chan->channelFlags & ~CHANNEL_CW_INT;
         h = ah->caldata->nfCalHist;
         default_nf = ath9k_hw_get_default_nf(ah, chan);
         for (i = 0; i < NUM_NF_READINGS; i++) {
@@ -353,11 +409,28 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
         }
 }
 
-s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
+
+void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
 {
-        if (!ah->caldata || !ah->caldata->rawNoiseFloor)
-                return ath9k_hw_get_default_nf(ah, chan);
+        struct ath9k_hw_cal_data *caldata = ah->caldata;
+
+        if (unlikely(!caldata))
+                return;
 
-        return ah->caldata->rawNoiseFloor;
+        /*
+         * If beacons are stuck, the most likely cause is interference.
+         * Triggering a noise floor calibration at this point helps the
+         * hardware adapt to a noisy environment much faster.
+         * To ensure that we recover from stuck beacons quickly, let
+         * the baseband update the internal NF value itself, similar to
+         * what is being done after a full reset.
+         */
+        if (!caldata->nfcal_pending)
+                ath9k_hw_start_nfcal(ah, true);
+        else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
+                ath9k_hw_getnf(ah, ah->curchan);
+
+        caldata->nfcal_interference = true;
 }
-EXPORT_SYMBOL(ath9k_hw_getchan_noise);
+EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
+
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 0a304b3eeeb6..1bef41d1b1ff 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -58,14 +58,6 @@ struct ar5416IniArray {
                 }                                                       \
         } while (0)
 
-enum ath9k_cal_types {
-        ADC_DC_INIT_CAL = 0x1,
-        ADC_GAIN_CAL = 0x2,
-        ADC_DC_CAL = 0x4,
-        IQ_MISMATCH_CAL = 0x8,
-        TEMP_COMP_CAL = 0x10,
-};
-
 enum ath9k_cal_state {
         CAL_INACTIVE,
         CAL_WAITING,
@@ -80,7 +72,7 @@ enum ath9k_cal_state {
 #define PER_MAX_LOG_COUNT  10
 
 struct ath9k_percal_data {
-        enum ath9k_cal_types calType;
+        u32 calType;
         u32 calNumSamples;
         u32 calCountMax;
         void (*calCollect) (struct ath_hw *);
@@ -113,7 +105,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
 bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan);
 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
                                   struct ath9k_channel *chan);
-s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
+void ath9k_hw_bstuck_nfcal(struct ath_hw *ah);
 void ath9k_hw_reset_calibration(struct ath_hw *ah,
                                 struct ath9k_cal_list *currCal);
 
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
index c86f7d3593ab..fa6bd2d189e5 100644
--- a/drivers/net/wireless/ath/ath9k/common.c
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -46,12 +46,17 @@ int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb)
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
 
         if (tx_info->control.hw_key) {
-                if (tx_info->control.hw_key->alg == ALG_WEP)
+                switch (tx_info->control.hw_key->cipher) {
+                case WLAN_CIPHER_SUITE_WEP40:
+                case WLAN_CIPHER_SUITE_WEP104:
                         return ATH9K_KEY_TYPE_WEP;
-                else if (tx_info->control.hw_key->alg == ALG_TKIP)
+                case WLAN_CIPHER_SUITE_TKIP:
                         return ATH9K_KEY_TYPE_TKIP;
-                else if (tx_info->control.hw_key->alg == ALG_CCMP)
+                case WLAN_CIPHER_SUITE_CCMP:
                         return ATH9K_KEY_TYPE_AES;
+                default:
+                        break;
+                }
         }
 
         return ATH9K_KEY_TYPE_CLEAR;
@@ -102,26 +107,23 @@ static u32 ath9k_get_extchanmode(struct ieee80211_channel *chan,
 /*
  * Update internal channel flags.
  */
-void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-                               struct ath9k_channel *ichan)
+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
+                               struct ieee80211_channel *chan,
+                               enum nl80211_channel_type channel_type)
 {
-        struct ieee80211_channel *chan = hw->conf.channel;
-        struct ieee80211_conf *conf = &hw->conf;
-
         ichan->channel = chan->center_freq;
         ichan->chan = chan;
 
         if (chan->band == IEEE80211_BAND_2GHZ) {
                 ichan->chanmode = CHANNEL_G;
-                ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
+                ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
         } else {
                 ichan->chanmode = CHANNEL_A;
                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
         }
 
-        if (conf_is_ht(conf))
-                ichan->chanmode = ath9k_get_extchanmode(chan,
-                                                        conf->channel_type);
+        if (channel_type != NL80211_CHAN_NO_HT)
+                ichan->chanmode = ath9k_get_extchanmode(chan, channel_type);
 }
 EXPORT_SYMBOL(ath9k_cmn_update_ichannel);
 
@@ -137,270 +139,12 @@ struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
 
         chan_idx = curchan->hw_value;
         channel = &ah->channels[chan_idx];
-        ath9k_cmn_update_ichannel(hw, channel);
+        ath9k_cmn_update_ichannel(channel, curchan, hw->conf.channel_type);
 
         return channel;
 }
 EXPORT_SYMBOL(ath9k_cmn_get_curchannel);
 
-static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
-                           struct ath9k_keyval *hk, const u8 *addr,
-                           bool authenticator)
-{
-        struct ath_hw *ah = common->ah;
-        const u8 *key_rxmic;
-        const u8 *key_txmic;
-
-        key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
-        key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
-
-        if (addr == NULL) {
-                /*
-                 * Group key installation - only two key cache entries are used
-                 * regardless of splitmic capability since group key is only
-                 * used either for TX or RX.
-                 */
-                if (authenticator) {
-                        memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
-                        memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
-                } else {
-                        memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
-                        memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
-                }
-                return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
-        }
-        if (!common->splitmic) {
-                /* TX and RX keys share the same key cache entry. */
-                memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
-                memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
-                return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
-        }
-
-        /* Separate key cache entries for TX and RX */
-
-        /* TX key goes at first index, RX key at +32. */
-        memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
-        if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
-                /* TX MIC entry failed. No need to proceed further */
-                ath_print(common, ATH_DBG_FATAL,
-                          "Setting TX MIC Key Failed\n");
-                return 0;
-        }
-
-        memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
-        /* XXX delete tx key on failure? */
-        return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
-}
-
-static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
-{
-        int i;
-
-        for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
-                if (test_bit(i, common->keymap) ||
-                    test_bit(i + 64, common->keymap))
-                        continue; /* At least one part of TKIP key allocated */
-                if (common->splitmic &&
-                    (test_bit(i + 32, common->keymap) ||
-                     test_bit(i + 64 + 32, common->keymap)))
-                        continue; /* At least one part of TKIP key allocated */
-
-                /* Found a free slot for a TKIP key */
-                return i;
-        }
-        return -1;
-}
-
-static int ath_reserve_key_cache_slot(struct ath_common *common,
-                                      enum ieee80211_key_alg alg)
-{
-        int i;
-
-        if (alg == ALG_TKIP)
-                return ath_reserve_key_cache_slot_tkip(common);
-
-        /* First, try to find slots that would not be available for TKIP. */
-        if (common->splitmic) {
-                for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
-                        if (!test_bit(i, common->keymap) &&
-                            (test_bit(i + 32, common->keymap) ||
-                             test_bit(i + 64, common->keymap) ||
-                             test_bit(i + 64 + 32, common->keymap)))
-                                return i;
-                        if (!test_bit(i + 32, common->keymap) &&
-                            (test_bit(i, common->keymap) ||
-                             test_bit(i + 64, common->keymap) ||
-                             test_bit(i + 64 + 32, common->keymap)))
-                                return i + 32;
-                        if (!test_bit(i + 64, common->keymap) &&
-                            (test_bit(i , common->keymap) ||
-                             test_bit(i + 32, common->keymap) ||
-                             test_bit(i + 64 + 32, common->keymap)))
-                                return i + 64;
-                        if (!test_bit(i + 64 + 32, common->keymap) &&
-                            (test_bit(i, common->keymap) ||
-                             test_bit(i + 32, common->keymap) ||
-                             test_bit(i + 64, common->keymap)))
-                                return i + 64 + 32;
-                }
-        } else {
-                for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
-                        if (!test_bit(i, common->keymap) &&
-                            test_bit(i + 64, common->keymap))
-                                return i;
-                        if (test_bit(i, common->keymap) &&
-                            !test_bit(i + 64, common->keymap))
-                                return i + 64;
-                }
-        }
-
-        /* No partially used TKIP slots, pick any available slot */
-        for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
-                /* Do not allow slots that could be needed for TKIP group keys
-                 * to be used. This limitation could be removed if we know that
-                 * TKIP will not be used. */
-                if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
-                        continue;
-                if (common->splitmic) {
-                        if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
-                                continue;
-                        if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
-                                continue;
-                }
-
-                if (!test_bit(i, common->keymap))
-                        return i; /* Found a free slot for a key */
-        }
-
-        /* No free slot found */
-        return -1;
-}
-
-/*
- * Configure encryption in the HW.
- */
-int ath9k_cmn_key_config(struct ath_common *common,
-                         struct ieee80211_vif *vif,
-                         struct ieee80211_sta *sta,
-                         struct ieee80211_key_conf *key)
-{
-        struct ath_hw *ah = common->ah;
-        struct ath9k_keyval hk;
-        const u8 *mac = NULL;
-        u8 gmac[ETH_ALEN];
-        int ret = 0;
-        int idx;
-
-        memset(&hk, 0, sizeof(hk));
-
-        switch (key->alg) {
-        case ALG_WEP:
-                hk.kv_type = ATH9K_CIPHER_WEP;
-                break;
-        case ALG_TKIP:
-                hk.kv_type = ATH9K_CIPHER_TKIP;
-                break;
-        case ALG_CCMP:
-                hk.kv_type = ATH9K_CIPHER_AES_CCM;
-                break;
-        default:
-                return -EOPNOTSUPP;
-        }
-
-        hk.kv_len = key->keylen;
-        memcpy(hk.kv_val, key->key, key->keylen);
-
-        if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
-                switch (vif->type) {
-                case NL80211_IFTYPE_AP:
-                        memcpy(gmac, vif->addr, ETH_ALEN);
-                        gmac[0] |= 0x01;
-                        mac = gmac;
-                        idx = ath_reserve_key_cache_slot(common, key->alg);
-                        break;
-                case NL80211_IFTYPE_ADHOC:
-                        if (!sta) {
-                                idx = key->keyidx;
-                                break;
-                        }
-                        memcpy(gmac, sta->addr, ETH_ALEN);
-                        gmac[0] |= 0x01;
-                        mac = gmac;
-                        idx = ath_reserve_key_cache_slot(common, key->alg);
-                        break;
-                default:
-                        idx = key->keyidx;
-                        break;
-                }
-        } else if (key->keyidx) {
-                if (WARN_ON(!sta))
-                        return -EOPNOTSUPP;
-                mac = sta->addr;
-
-                if (vif->type != NL80211_IFTYPE_AP) {
-                        /* Only keyidx 0 should be used with unicast key, but
-                         * allow this for client mode for now. */
-                        idx = key->keyidx;
-                } else
-                        return -EIO;
-        } else {
-                if (WARN_ON(!sta))
-                        return -EOPNOTSUPP;
-                mac = sta->addr;
-
-                idx = ath_reserve_key_cache_slot(common, key->alg);
-        }
-
-        if (idx < 0)
-                return -ENOSPC; /* no free key cache entries */
-
-        if (key->alg == ALG_TKIP)
-                ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
-                                      vif->type == NL80211_IFTYPE_AP);
-        else
-                ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
-
-        if (!ret)
-                return -EIO;
-
-        set_bit(idx, common->keymap);
-        if (key->alg == ALG_TKIP) {
-                set_bit(idx + 64, common->keymap);
-                if (common->splitmic) {
-                        set_bit(idx + 32, common->keymap);
-                        set_bit(idx + 64 + 32, common->keymap);
-                }
-        }
-
-        return idx;
-}
-EXPORT_SYMBOL(ath9k_cmn_key_config);
-
-/*
- * Delete Key.
- */
-void ath9k_cmn_key_delete(struct ath_common *common,
-                          struct ieee80211_key_conf *key)
-{
-        struct ath_hw *ah = common->ah;
-
-        ath9k_hw_keyreset(ah, key->hw_key_idx);
-        if (key->hw_key_idx < IEEE80211_WEP_NKID)
-                return;
-
-        clear_bit(key->hw_key_idx, common->keymap);
-        if (key->alg != ALG_TKIP)
-                return;
-
-        clear_bit(key->hw_key_idx + 64, common->keymap);
-        if (common->splitmic) {
-                ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
-                clear_bit(key->hw_key_idx + 32, common->keymap);
-                clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
-        }
-}
-EXPORT_SYMBOL(ath9k_cmn_key_delete);
-
 int ath9k_cmn_count_streams(unsigned int chainmask, int max)
 {
         int streams = 0;
@@ -414,6 +158,17 @@ int ath9k_cmn_count_streams(unsigned int chainmask, int max)
 }
 EXPORT_SYMBOL(ath9k_cmn_count_streams);
 
+void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
+                            u16 new_txpow, u16 *txpower)
+{
+        if (cur_txpow != new_txpow) {
+                ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
+                /* read back in case value is clamped */
+                *txpower = ath9k_hw_regulatory(ah)->power_limit;
+        }
+}
+EXPORT_SYMBOL(ath9k_cmn_update_txpow);
+
 static int __init ath9k_cmn_init(void)
 {
         return 0;
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
index 97809d39c73f..77ec288b5a70 100644
--- a/drivers/net/wireless/ath/ath9k/common.h
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009 Atheros Communications Inc.
+ * Copyright (c) 2009-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,24 +17,22 @@
 #include <net/mac80211.h>
 
 #include "../ath.h"
-#include "../debug.h"
 
 #include "hw.h"
 #include "hw-ops.h"
 
 /* Common header for Atheros 802.11n base driver cores */
 
-#define IEEE80211_WEP_NKID 4
-
 #define WME_NUM_TID             16
 #define WME_BA_BMP_SIZE         64
 #define WME_MAX_BA              WME_BA_BMP_SIZE
 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 
-#define WME_AC_BE   0
-#define WME_AC_BK   1
-#define WME_AC_VI   2
-#define WME_AC_VO   3
+/* These must match mac80211 skb queue mapping numbers */
+#define WME_AC_VO   0
+#define WME_AC_VI   1
+#define WME_AC_BE   2
+#define WME_AC_BK   3
 #define WME_NUM_AC  4
 
 #define ATH_RSSI_DUMMY_MARKER   0x127
@@ -54,14 +52,13 @@
 
 int ath9k_cmn_padpos(__le16 frame_control);
 int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb);
-void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-                               struct ath9k_channel *ichan);
+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
+                               struct ieee80211_channel *chan,
+                               enum nl80211_channel_type channel_type);
 struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
                                                struct ath_hw *ah);
-int ath9k_cmn_key_config(struct ath_common *common,
-                         struct ieee80211_vif *vif,
-                         struct ieee80211_sta *sta,
-                         struct ieee80211_key_conf *key);
-void ath9k_cmn_key_delete(struct ath_common *common,
-                          struct ieee80211_key_conf *key);
 int ath9k_cmn_count_streams(unsigned int chainmask, int max);
+void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common,
+                                  enum ath_stomp_type stomp_type);
+void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
+                            u16 new_txpow, u16 *txpower);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 54aae931424e..d55ffd7d4bd2 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,6 +15,7 @@
  */
 
 #include <linux/slab.h>
+#include <linux/vmalloc.h>
 #include <asm/unaligned.h>
 
 #include "ath9k.h"
@@ -24,14 +25,25 @@
 #define REG_READ_D(_ah, _reg) \
         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
 
-static struct dentry *ath9k_debugfs_root;
-
 static int ath9k_debugfs_open(struct inode *inode, struct file *file)
 {
         file->private_data = inode->i_private;
         return 0;
 }
 
+static ssize_t ath9k_debugfs_read_buf(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        u8 *buf = file->private_data;
+        return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
+}
+
+static int ath9k_debugfs_release_buf(struct inode *inode, struct file *file)
+{
+        vfree(file->private_data);
+        return 0;
+}
+
 #ifdef CONFIG_ATH_DEBUG
 
 static ssize_t read_file_debug(struct file *file, char __user *user_buf,
@@ -71,7 +83,8 @@ static const struct file_operations fops_debug = {
         .read = read_file_debug,
         .write = write_file_debug,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 #endif
@@ -116,7 +129,8 @@ static const struct file_operations fops_tx_chainmask = {
         .read = read_file_tx_chainmask,
         .write = write_file_tx_chainmask,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -158,7 +172,8 @@ static const struct file_operations fops_rx_chainmask = {
         .read = read_file_rx_chainmask,
         .write = write_file_rx_chainmask,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -259,7 +274,8 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
 static const struct file_operations fops_dma = {
         .read = read_file_dma,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 
@@ -310,6 +326,8 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
                 sc->debug.stats.istats.dtimsync++;
         if (status & ATH9K_INT_DTIM)
                 sc->debug.stats.istats.dtim++;
+        if (status & ATH9K_INT_TSFOOR)
+                sc->debug.stats.istats.tsfoor++;
 }
 
 static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
@@ -364,8 +382,11 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
         len += snprintf(buf + len, sizeof(buf) - len,
                 "%8s: %10u\n", "DTIM", sc->debug.stats.istats.dtim);
         len += snprintf(buf + len, sizeof(buf) - len,
+                "%8s: %10u\n", "TSFOOR", sc->debug.stats.istats.tsfoor);
+        len += snprintf(buf + len, sizeof(buf) - len,
                 "%8s: %10u\n", "TOTAL", sc->debug.stats.istats.total);
 
+
         if (len > sizeof(buf))
                 len = sizeof(buf);
 
@@ -375,140 +396,46 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
 static const struct file_operations fops_interrupt = {
         .read = read_file_interrupt,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
-void ath_debug_stat_rc(struct ath_softc *sc, int final_rate)
-{
-        struct ath_rc_stats *stats;
-
-        stats = &sc->debug.stats.rcstats[final_rate];
-        stats->success++;
-}
-
-void ath_debug_stat_retries(struct ath_softc *sc, int rix,
-                            int xretries, int retries, u8 per)
+static const char *channel_type_str(enum nl80211_channel_type t)
 {
-        struct ath_rc_stats *stats = &sc->debug.stats.rcstats[rix];
-
-        stats->xretries += xretries;
-        stats->retries += retries;
-        stats->per = per;
-}
-
-static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
-                                size_t count, loff_t *ppos)
-{
-        struct ath_softc *sc = file->private_data;
-        char *buf;
-        unsigned int len = 0, max;
-        int i = 0;
-        ssize_t retval;
-
-        if (sc->cur_rate_table == NULL)
-                return 0;
-
-        max = 80 + sc->cur_rate_table->rate_cnt * 1024 + 1;
-        buf = kmalloc(max, GFP_KERNEL);
-        if (buf == NULL)
-                return -ENOMEM;
-
-        len += sprintf(buf, "%6s %6s %6s "
-                       "%10s %10s %10s %10s\n",
-                       "HT", "MCS", "Rate",
-                       "Success", "Retries", "XRetries", "PER");
-
-        for (i = 0; i < sc->cur_rate_table->rate_cnt; i++) {
-                u32 ratekbps = sc->cur_rate_table->info[i].ratekbps;
-                struct ath_rc_stats *stats = &sc->debug.stats.rcstats[i];
-                char mcs[5];
-                char htmode[5];
-                int used_mcs = 0, used_htmode = 0;
-
-                if (WLAN_RC_PHY_HT(sc->cur_rate_table->info[i].phy)) {
-                        used_mcs = snprintf(mcs, 5, "%d",
-                                sc->cur_rate_table->info[i].ratecode);
-
-                        if (WLAN_RC_PHY_40(sc->cur_rate_table->info[i].phy))
-                                used_htmode = snprintf(htmode, 5, "HT40");
-                        else if (WLAN_RC_PHY_20(sc->cur_rate_table->info[i].phy))
-                                used_htmode = snprintf(htmode, 5, "HT20");
-                        else
-                                used_htmode = snprintf(htmode, 5, "????");
-                }
-
-                mcs[used_mcs] = '\0';
-                htmode[used_htmode] = '\0';
-
-                len += snprintf(buf + len, max - len,
-                        "%6s %6s %3u.%d: "
-                        "%10u %10u %10u %10u\n",
-                        htmode,
-                        mcs,
-                        ratekbps / 1000,
-                        (ratekbps % 1000) / 100,
-                        stats->success,
-                        stats->retries,
-                        stats->xretries,
-                        stats->per);
+        switch (t) {
+        case NL80211_CHAN_NO_HT:
+                return "no ht";
+        case NL80211_CHAN_HT20:
+                return "ht20";
+        case NL80211_CHAN_HT40MINUS:
+                return "ht40-";
+        case NL80211_CHAN_HT40PLUS:
+                return "ht40+";
+        default:
+                return "???";
         }
-
-        if (len > max)
-                len = max;
-
-        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
-        kfree(buf);
-        return retval;
-}
-
-static const struct file_operations fops_rcstat = {
-        .read = read_file_rcstat,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-static const char * ath_wiphy_state_str(enum ath_wiphy_state state)
-{
-        switch (state) {
-        case ATH_WIPHY_INACTIVE:
-                return "INACTIVE";
-        case ATH_WIPHY_ACTIVE:
-                return "ACTIVE";
-        case ATH_WIPHY_PAUSING:
-                return "PAUSING";
-        case ATH_WIPHY_PAUSED:
-                return "PAUSED";
-        case ATH_WIPHY_SCAN:
-                return "SCAN";
-        }
-        return "?";
 }
 
 static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
                                size_t count, loff_t *ppos)
 {
         struct ath_softc *sc = file->private_data;
+        struct ieee80211_channel *chan = sc->hw->conf.channel;
+        struct ieee80211_conf *conf = &(sc->hw->conf);
         char buf[512];
         unsigned int len = 0;
-        int i;
         u8 addr[ETH_ALEN];
+        u32 tmp;
 
         len += snprintf(buf + len, sizeof(buf) - len,
-                        "primary: %s (%s chan=%d ht=%d)\n",
-                        wiphy_name(sc->pri_wiphy->hw->wiphy),
-                        ath_wiphy_state_str(sc->pri_wiphy->state),
-                        sc->pri_wiphy->chan_idx, sc->pri_wiphy->chan_is_ht);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
-                        continue;
-                len += snprintf(buf + len, sizeof(buf) - len,
-                                "secondary: %s (%s chan=%d ht=%d)\n",
-                                wiphy_name(aphy->hw->wiphy),
-                                ath_wiphy_state_str(aphy->state),
-                                aphy->chan_idx, aphy->chan_is_ht);
-        }
+                        "%s (chan=%d  center-freq: %d MHz  channel-type: %d (%s))\n",
+                        wiphy_name(sc->hw->wiphy),
+                        ieee80211_frequency_to_channel(chan->center_freq),
+                        chan->center_freq,
+                        conf->channel_type,
+                        channel_type_str(conf->channel_type));
 
+        ath9k_ps_wakeup(sc);
         put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_STA_ID0), addr);
         put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4);
         len += snprintf(buf + len, sizeof(buf) - len,
@@ -517,6 +444,38 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
         put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_BSSMSKU) & 0xffff, addr + 4);
         len += snprintf(buf + len, sizeof(buf) - len,
                         "addrmask: %pM\n", addr);
+        tmp = ath9k_hw_getrxfilter(sc->sc_ah);
+        ath9k_ps_restore(sc);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "rfilt: 0x%x", tmp);
+        if (tmp & ATH9K_RX_FILTER_UCAST)
+                len += snprintf(buf + len, sizeof(buf) - len, " UCAST");
+        if (tmp & ATH9K_RX_FILTER_MCAST)
+                len += snprintf(buf + len, sizeof(buf) - len, " MCAST");
+        if (tmp & ATH9K_RX_FILTER_BCAST)
+                len += snprintf(buf + len, sizeof(buf) - len, " BCAST");
+        if (tmp & ATH9K_RX_FILTER_CONTROL)
+                len += snprintf(buf + len, sizeof(buf) - len, " CONTROL");
+        if (tmp & ATH9K_RX_FILTER_BEACON)
+                len += snprintf(buf + len, sizeof(buf) - len, " BEACON");
+        if (tmp & ATH9K_RX_FILTER_PROM)
+                len += snprintf(buf + len, sizeof(buf) - len, " PROM");
+        if (tmp & ATH9K_RX_FILTER_PROBEREQ)
+                len += snprintf(buf + len, sizeof(buf) - len, " PROBEREQ");
+        if (tmp & ATH9K_RX_FILTER_PHYERR)
+                len += snprintf(buf + len, sizeof(buf) - len, " PHYERR");
+        if (tmp & ATH9K_RX_FILTER_MYBEACON)
+                len += snprintf(buf + len, sizeof(buf) - len, " MYBEACON");
+        if (tmp & ATH9K_RX_FILTER_COMP_BAR)
+                len += snprintf(buf + len, sizeof(buf) - len, " COMP_BAR");
+        if (tmp & ATH9K_RX_FILTER_PSPOLL)
+                len += snprintf(buf + len, sizeof(buf) - len, " PSPOLL");
+        if (tmp & ATH9K_RX_FILTER_PHYRADAR)
+                len += snprintf(buf + len, sizeof(buf) - len, " PHYRADAR");
+        if (tmp & ATH9K_RX_FILTER_MCAST_BCAST_ALL)
+                len += snprintf(buf + len, sizeof(buf) - len, " MCAST_BCAST_ALL\n");
+        else
+                len += snprintf(buf + len, sizeof(buf) - len, "\n");
 
         if (len > sizeof(buf))
                 len = sizeof(buf);
@@ -524,136 +483,76 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 }
 
-static struct ath_wiphy * get_wiphy(struct ath_softc *sc, const char *name)
-{
-        int i;
-        if (strcmp(name, wiphy_name(sc->pri_wiphy->hw->wiphy)) == 0)
-                return sc->pri_wiphy;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy && strcmp(name, wiphy_name(aphy->hw->wiphy)) == 0)
-                        return aphy;
-        }
-        return NULL;
-}
-
-static int del_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_del(aphy);
-}
-
-static int pause_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_pause(aphy);
-}
-
-static int unpause_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_unpause(aphy);
-}
-
-static int select_wiphy(struct ath_softc *sc, const char *name)
-{
-        struct ath_wiphy *aphy = get_wiphy(sc, name);
-        if (!aphy)
-                return -ENOENT;
-        return ath9k_wiphy_select(aphy);
-}
-
-static int schedule_wiphy(struct ath_softc *sc, const char *msec)
-{
-        ath9k_wiphy_set_scheduler(sc, simple_strtoul(msec, NULL, 0));
-        return 0;
-}
-
-static ssize_t write_file_wiphy(struct file *file, const char __user *user_buf,
-                                size_t count, loff_t *ppos)
-{
-        struct ath_softc *sc = file->private_data;
-        char buf[50];
-        size_t len;
-
-        len = min(count, sizeof(buf) - 1);
-        if (copy_from_user(buf, user_buf, len))
-                return -EFAULT;
-        buf[len] = '\0';
-        if (len > 0 && buf[len - 1] == '\n')
-                buf[len - 1] = '\0';
-
-        if (strncmp(buf, "add", 3) == 0) {
-                int res = ath9k_wiphy_add(sc);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "del=", 4) == 0) {
-                int res = del_wiphy(sc, buf + 4);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "pause=", 6) == 0) {
-                int res = pause_wiphy(sc, buf + 6);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "unpause=", 8) == 0) {
-                int res = unpause_wiphy(sc, buf + 8);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "select=", 7) == 0) {
-                int res = select_wiphy(sc, buf + 7);
-                if (res < 0)
-                        return res;
-        } else if (strncmp(buf, "schedule=", 9) == 0) {
-                int res = schedule_wiphy(sc, buf + 9);
-                if (res < 0)
-                        return res;
-        } else
-                return -EOPNOTSUPP;
-
-        return count;
-}
-
 static const struct file_operations fops_wiphy = {
         .read = read_file_wiphy,
-        .write = write_file_wiphy,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
+#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
 #define PR(str, elem)                                                   \
         do {                                                            \
                 len += snprintf(buf + len, size - len,                  \
                                 "%s%13u%11u%10u%10u\n", str,            \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BE]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BK]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VI]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VO]].elem); \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem, \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem, \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem, \
+                sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem); \
+                if (len >= size)                          \
+                        goto done;                        \
 } while(0)
 
+#define PRX(str, elem)                                                  \
+do {                                                                    \
+        len += snprintf(buf + len, size - len,                          \
+                        "%s%13u%11u%10u%10u\n", str,                    \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_BE]->elem),        \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_BK]->elem),        \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_VI]->elem),        \
+                        (unsigned int)(sc->tx.txq_map[WME_AC_VO]->elem));       \
+        if (len >= size)                                                \
+                goto done;                                              \
+} while(0)
+
+#define PRQLE(str, elem)                                                \
+do {                                                                    \
+        len += snprintf(buf + len, size - len,                          \
+                        "%s%13i%11i%10i%10i\n", str,                    \
+                        list_empty(&sc->tx.txq_map[WME_AC_BE]->elem),   \
+                        list_empty(&sc->tx.txq_map[WME_AC_BK]->elem),   \
+                        list_empty(&sc->tx.txq_map[WME_AC_VI]->elem),   \
+                        list_empty(&sc->tx.txq_map[WME_AC_VO]->elem));  \
+        if (len >= size)                                                \
+                goto done;                                              \
+} while (0)
+
 static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
                               size_t count, loff_t *ppos)
 {
         struct ath_softc *sc = file->private_data;
         char *buf;
-        unsigned int len = 0, size = 2048;
+        unsigned int len = 0, size = 8000;
+        int i;
         ssize_t retval = 0;
+        char tmp[32];
 
         buf = kzalloc(size, GFP_KERNEL);
         if (buf == NULL)
                 return -ENOMEM;
 
-        len += sprintf(buf, "%30s %10s%10s%10s\n\n", "BE", "BK", "VI", "VO");
+        len += sprintf(buf, "Num-Tx-Queues: %i  tx-queues-setup: 0x%x"
+                       " poll-work-seen: %u\n"
+                       "%30s %10s%10s%10s\n\n",
+                       ATH9K_NUM_TX_QUEUES, sc->tx.txqsetup,
+                       sc->tx_complete_poll_work_seen,
+                       "BE", "BK", "VI", "VO");
 
         PR("MPDUs Queued:    ", queued);
         PR("MPDUs Completed: ", completed);
         PR("Aggregates:      ", a_aggr);
-        PR("AMPDUs Queued:   ", a_queued);
+        PR("AMPDUs Queued HW:", a_queued_hw);
+        PR("AMPDUs Queued SW:", a_queued_sw);
         PR("AMPDUs Completed:", a_completed);
         PR("AMPDUs Retried:  ", a_retries);
         PR("AMPDUs XRetried: ", a_xretries);
@@ -663,7 +562,64 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
         PR("DESC CFG Error:  ", desc_cfg_err);
         PR("DATA Underrun:   ", data_underrun);
         PR("DELIM Underrun:  ", delim_underrun);
+        PR("TX-Pkts-All:     ", tx_pkts_all);
+        PR("TX-Bytes-All:    ", tx_bytes_all);
+        PR("hw-put-tx-buf:   ", puttxbuf);
+        PR("hw-tx-start:     ", txstart);
+        PR("hw-tx-proc-desc: ", txprocdesc);
+        len += snprintf(buf + len, size - len,
+                        "%s%11p%11p%10p%10p\n", "txq-memory-address:",
+                        sc->tx.txq_map[WME_AC_BE],
+                        sc->tx.txq_map[WME_AC_BK],
+                        sc->tx.txq_map[WME_AC_VI],
+                        sc->tx.txq_map[WME_AC_VO]);
+        if (len >= size)
+                goto done;
+
+        PRX("axq-qnum:        ", axq_qnum);
+        PRX("axq-depth:       ", axq_depth);
+        PRX("axq-ampdu_depth: ", axq_ampdu_depth);
+        PRX("axq-stopped      ", stopped);
+        PRX("tx-in-progress   ", axq_tx_inprogress);
+        PRX("pending-frames   ", pending_frames);
+        PRX("txq_headidx:     ", txq_headidx);
+        PRX("txq_tailidx:     ", txq_headidx);
+
+        PRQLE("axq_q empty:       ", axq_q);
+        PRQLE("axq_acq empty:     ", axq_acq);
+        PRQLE("txq_fifo_pending:  ", txq_fifo_pending);
+        for (i = 0; i < ATH_TXFIFO_DEPTH; i++) {
+                snprintf(tmp, sizeof(tmp) - 1, "txq_fifo[%i] empty: ", i);
+                PRQLE(tmp, txq_fifo[i]);
+        }
 
+        /* Print out more detailed queue-info */
+        for (i = 0; i <= WME_AC_BK; i++) {
+                struct ath_txq *txq = &(sc->tx.txq[i]);
+                struct ath_atx_ac *ac;
+                struct ath_atx_tid *tid;
+                if (len >= size)
+                        goto done;
+                spin_lock_bh(&txq->axq_lock);
+                if (!list_empty(&txq->axq_acq)) {
+                        ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac,
+                                              list);
+                        len += snprintf(buf + len, size - len,
+                                        "txq[%i] first-ac: %p sched: %i\n",
+                                        i, ac, ac->sched);
+                        if (list_empty(&ac->tid_q) || (len >= size))
+                                goto done_for;
+                        tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
+                                               list);
+                        len += snprintf(buf + len, size - len,
+                                        " first-tid: %p sched: %i paused: %i\n",
+                                        tid, tid->sched, tid->paused);
+                }
+        done_for:
+                spin_unlock_bh(&txq->axq_lock);
+        }
+
+done:
         if (len > size)
                 len = size;
 
@@ -673,36 +629,220 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
         return retval;
 }
 
-void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-                       struct ath_buf *bf, struct ath_tx_status *ts)
+static ssize_t read_file_stations(struct file *file, char __user *user_buf,
+                                  size_t count, loff_t *ppos)
 {
+        struct ath_softc *sc = file->private_data;
+        char *buf;
+        unsigned int len = 0, size = 64000;
+        struct ath_node *an = NULL;
+        ssize_t retval = 0;
+        int q;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "Stations:\n"
+                        " tid: addr sched paused buf_q-empty an ac\n"
+                        " ac: addr sched tid_q-empty txq\n");
+
+        spin_lock(&sc->nodes_lock);
+        list_for_each_entry(an, &sc->nodes, list) {
+                len += snprintf(buf + len, size - len,
+                                "%pM\n", an->sta->addr);
+                if (len >= size)
+                        goto done;
+
+                for (q = 0; q < WME_NUM_TID; q++) {
+                        struct ath_atx_tid *tid = &(an->tid[q]);
+                        len += snprintf(buf + len, size - len,
+                                        " tid: %p %s %s %i %p %p\n",
+                                        tid, tid->sched ? "sched" : "idle",
+                                        tid->paused ? "paused" : "running",
+                                        list_empty(&tid->buf_q),
+                                        tid->an, tid->ac);
+                        if (len >= size)
+                                goto done;
+                }
+
+                for (q = 0; q < WME_NUM_AC; q++) {
+                        struct ath_atx_ac *ac = &(an->ac[q]);
+                        len += snprintf(buf + len, size - len,
+                                        " ac: %p %s %i %p\n",
+                                        ac, ac->sched ? "sched" : "idle",
+                                        list_empty(&ac->tid_q), ac->txq);
+                        if (len >= size)
+                                goto done;
+                }
+        }
+
+done:
+        spin_unlock(&sc->nodes_lock);
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+static ssize_t read_file_misc(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+        struct ath_softc *sc = file->private_data;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_hw *ah = sc->sc_ah;
+        struct ieee80211_hw *hw = sc->hw;
+        char *buf;
+        unsigned int len = 0, size = 8000;
+        ssize_t retval = 0;
+        const char *tmp;
+        unsigned int reg;
+        struct ath9k_vif_iter_data iter_data;
+
+        ath9k_calculate_iter_data(hw, NULL, &iter_data);
+        
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        switch (sc->sc_ah->opmode) {
+        case  NL80211_IFTYPE_ADHOC:
+                tmp = "ADHOC";
+                break;
+        case  NL80211_IFTYPE_MESH_POINT:
+                tmp = "MESH";
+                break;
+        case  NL80211_IFTYPE_AP:
+                tmp = "AP";
+                break;
+        case  NL80211_IFTYPE_STATION:
+                tmp = "STATION";
+                break;
+        default:
+                tmp = "???";
+                break;
+        }
+
+        ath9k_ps_wakeup(sc);
+        len += snprintf(buf + len, size - len,
+                        "curbssid: %pM\n"
+                        "OP-Mode: %s(%i)\n"
+                        "Beacon-Timer-Register: 0x%x\n",
+                        common->curbssid,
+                        tmp, (int)(sc->sc_ah->opmode),
+                        REG_READ(ah, AR_BEACON_PERIOD));
+
+        reg = REG_READ(ah, AR_TIMER_MODE);
+        ath9k_ps_restore(sc);
+        len += snprintf(buf + len, size - len, "Timer-Mode-Register: 0x%x (",
+                        reg);
+        if (reg & AR_TBTT_TIMER_EN)
+                len += snprintf(buf + len, size - len, "TBTT ");
+        if (reg & AR_DBA_TIMER_EN)
+                len += snprintf(buf + len, size - len, "DBA ");
+        if (reg & AR_SWBA_TIMER_EN)
+                len += snprintf(buf + len, size - len, "SWBA ");
+        if (reg & AR_HCF_TIMER_EN)
+                len += snprintf(buf + len, size - len, "HCF ");
+        if (reg & AR_TIM_TIMER_EN)
+                len += snprintf(buf + len, size - len, "TIM ");
+        if (reg & AR_DTIM_TIMER_EN)
+                len += snprintf(buf + len, size - len, "DTIM ");
+        len += snprintf(buf + len, size - len, ")\n");
+
+        reg = sc->sc_ah->imask;
+        len += snprintf(buf + len, size - len, "imask: 0x%x (", reg);
+        if (reg & ATH9K_INT_SWBA)
+                len += snprintf(buf + len, size - len, "SWBA ");
+        if (reg & ATH9K_INT_BMISS)
+                len += snprintf(buf + len, size - len, "BMISS ");
+        if (reg & ATH9K_INT_CST)
+                len += snprintf(buf + len, size - len, "CST ");
+        if (reg & ATH9K_INT_RX)
+                len += snprintf(buf + len, size - len, "RX ");
+        if (reg & ATH9K_INT_RXHP)
+                len += snprintf(buf + len, size - len, "RXHP ");
+        if (reg & ATH9K_INT_RXLP)
+                len += snprintf(buf + len, size - len, "RXLP ");
+        if (reg & ATH9K_INT_BB_WATCHDOG)
+                len += snprintf(buf + len, size - len, "BB_WATCHDOG ");
+        /* there are other IRQs if one wanted to add them. */
+        len += snprintf(buf + len, size - len, ")\n");
+
+        len += snprintf(buf + len, size - len,
+                        "VIF Counts: AP: %i STA: %i MESH: %i WDS: %i"
+                        " ADHOC: %i OTHER: %i nvifs: %hi beacon-vifs: %hi\n",
+                        iter_data.naps, iter_data.nstations, iter_data.nmeshes,
+                        iter_data.nwds, iter_data.nadhocs, iter_data.nothers,
+                        sc->nvifs, sc->nbcnvifs);
+
+        len += snprintf(buf + len, size - len,
+                        "Calculated-BSSID-Mask: %pM\n",
+                        iter_data.mask);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
+                       struct ath_tx_status *ts, struct ath_txq *txq)
+{
+        int qnum = txq->axq_qnum;
+
+        TX_STAT_INC(qnum, tx_pkts_all);
+        sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len;
+
         if (bf_isampdu(bf)) {
                 if (bf_isxretried(bf))
-                        TX_STAT_INC(txq->axq_qnum, a_xretries);
+                        TX_STAT_INC(qnum, a_xretries);
                 else
-                        TX_STAT_INC(txq->axq_qnum, a_completed);
+                        TX_STAT_INC(qnum, a_completed);
         } else {
-                TX_STAT_INC(txq->axq_qnum, completed);
+                TX_STAT_INC(qnum, completed);
         }
 
         if (ts->ts_status & ATH9K_TXERR_FIFO)
-                TX_STAT_INC(txq->axq_qnum, fifo_underrun);
+                TX_STAT_INC(qnum, fifo_underrun);
         if (ts->ts_status & ATH9K_TXERR_XTXOP)
-                TX_STAT_INC(txq->axq_qnum, xtxop);
+                TX_STAT_INC(qnum, xtxop);
         if (ts->ts_status & ATH9K_TXERR_TIMER_EXPIRED)
-                TX_STAT_INC(txq->axq_qnum, timer_exp);
+                TX_STAT_INC(qnum, timer_exp);
         if (ts->ts_flags & ATH9K_TX_DESC_CFG_ERR)
-                TX_STAT_INC(txq->axq_qnum, desc_cfg_err);
+                TX_STAT_INC(qnum, desc_cfg_err);
         if (ts->ts_flags & ATH9K_TX_DATA_UNDERRUN)
-                TX_STAT_INC(txq->axq_qnum, data_underrun);
+                TX_STAT_INC(qnum, data_underrun);
         if (ts->ts_flags & ATH9K_TX_DELIM_UNDERRUN)
-                TX_STAT_INC(txq->axq_qnum, delim_underrun);
+                TX_STAT_INC(qnum, delim_underrun);
 }
 
 static const struct file_operations fops_xmit = {
         .read = read_file_xmit,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static const struct file_operations fops_stations = {
+        .read = read_file_stations,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static const struct file_operations fops_misc = {
+        .read = read_file_misc,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 static ssize_t read_file_recv(struct file *file, char __user *user_buf,
@@ -714,7 +854,7 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
 
         struct ath_softc *sc = file->private_data;
         char *buf;
-        unsigned int len = 0, size = 1152;
+        unsigned int len = 0, size = 1400;
         ssize_t retval = 0;
 
         buf = kzalloc(size, GFP_KERNEL);
@@ -743,6 +883,34 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
                         "%18s : %10u\n", "DECRYPT BUSY ERR",
                         sc->debug.stats.rxstats.decrypt_busy_err);
 
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-CTL0",
+                        sc->debug.stats.rxstats.rs_rssi_ctl0);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-CTL1",
+                        sc->debug.stats.rxstats.rs_rssi_ctl1);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-CTL2",
+                        sc->debug.stats.rxstats.rs_rssi_ctl2);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-EXT0",
+                        sc->debug.stats.rxstats.rs_rssi_ext0);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-EXT1",
+                        sc->debug.stats.rxstats.rs_rssi_ext1);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "RSSI-EXT2",
+                        sc->debug.stats.rxstats.rs_rssi_ext2);
+
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10d\n", "Rx Antenna",
+                        sc->debug.stats.rxstats.rs_antenna);
+
         PHY_ERR("UNDERRUN", ATH9K_PHYERR_UNDERRUN);
         PHY_ERR("TIMING", ATH9K_PHYERR_TIMING);
         PHY_ERR("PARITY", ATH9K_PHYERR_PARITY);
@@ -770,6 +938,13 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
         PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL);
         PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL);
 
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10u\n", "RX-Pkts-All",
+                        sc->debug.stats.rxstats.rx_pkts_all);
+        len += snprintf(buf + len, size - len,
+                        "%18s : %10u\n", "RX-Bytes-All",
+                        sc->debug.stats.rxstats.rx_bytes_all);
+
         if (len > size)
                 len = size;
 
@@ -788,6 +963,9 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
 
         u32 phyerr;
 
+        RX_STAT_INC(rx_pkts_all);
+        sc->debug.stats.rxstats.rx_bytes_all += rs->rs_datalen;
+
         if (rs->rs_status & ATH9K_RXERR_CRC)
                 RX_STAT_INC(crc_err);
         if (rs->rs_status & ATH9K_RXERR_DECRYPT)
@@ -807,6 +985,16 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
                 RX_PHY_ERR_INC(phyerr);
         }
 
+        sc->debug.stats.rxstats.rs_rssi_ctl0 = rs->rs_rssi_ctl0;
+        sc->debug.stats.rxstats.rs_rssi_ctl1 = rs->rs_rssi_ctl1;
+        sc->debug.stats.rxstats.rs_rssi_ctl2 = rs->rs_rssi_ctl2;
+
+        sc->debug.stats.rxstats.rs_rssi_ext0 = rs->rs_rssi_ext0;
+        sc->debug.stats.rxstats.rs_rssi_ext1 = rs->rs_rssi_ext1;
+        sc->debug.stats.rxstats.rs_rssi_ext2 = rs->rs_rssi_ext2;
+
+        sc->debug.stats.rxstats.rs_antenna = rs->rs_antenna;
+
 #undef RX_STAT_INC
 #undef RX_PHY_ERR_INC
 }
@@ -814,7 +1002,8 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
 static const struct file_operations fops_recv = {
         .read = read_file_recv,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 static ssize_t read_file_regidx(struct file *file, char __user *user_buf,
@@ -852,7 +1041,8 @@ static const struct file_operations fops_regidx = {
         .read = read_file_regidx,
         .write = write_file_regidx,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
 static ssize_t read_file_regval(struct file *file, char __user *user_buf,
@@ -864,7 +1054,9 @@ static ssize_t read_file_regval(struct file *file, char __user *user_buf,
         unsigned int len;
         u32 regval;
 
+        ath9k_ps_wakeup(sc);
         regval = REG_READ_D(ah, sc->debug.regidx);
+        ath9k_ps_restore(sc);
         len = sprintf(buf, "0x%08x\n", regval);
         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 }
@@ -886,7 +1078,9 @@ static ssize_t write_file_regval(struct file *file, const char __user *user_buf,
         if (strict_strtoul(buf, 0, &regval))
                 return -EINVAL;
 
+        ath9k_ps_wakeup(sc);
         REG_WRITE_D(ah, sc->debug.regidx, regval);
+        ath9k_ps_restore(sc);
         return count;
 }
 
@@ -894,98 +1088,94 @@ static const struct file_operations fops_regval = {
         .read = read_file_regval,
         .write = write_file_regval,
         .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
 };
 
-int ath9k_init_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath_softc *sc = (struct ath_softc *) common->priv;
+#define REGDUMP_LINE_SIZE       20
 
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
+static int open_file_regdump(struct inode *inode, struct file *file)
+{
+        struct ath_softc *sc = inode->i_private;
+        unsigned int len = 0;
+        u8 *buf;
+        int i;
+        unsigned long num_regs, regdump_len, max_reg_offset;
 
-        sc->debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
-                                                      ath9k_debugfs_root);
-        if (!sc->debug.debugfs_phy)
+        max_reg_offset = AR_SREV_9300_20_OR_LATER(sc->sc_ah) ? 0x16bd4 : 0xb500;
+        num_regs = max_reg_offset / 4 + 1;
+        regdump_len = num_regs * REGDUMP_LINE_SIZE + 1;
+        buf = vmalloc(regdump_len);
+        if (!buf)
                 return -ENOMEM;
 
-#ifdef CONFIG_ATH_DEBUG
-        if (!debugfs_create_file("debug", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_debug))
-                goto err;
-#endif
-
-        if (!debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_dma))
-                goto err;
-
-        if (!debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_interrupt))
-                goto err;
-
-        if (!debugfs_create_file("rcstat", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_rcstat))
-                goto err;
-
-        if (!debugfs_create_file("wiphy", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_wiphy))
-                goto err;
-
-        if (!debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_xmit))
-                goto err;
-
-        if (!debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy,
-                        sc, &fops_recv))
-                goto err;
-
-        if (!debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_rx_chainmask))
-                goto err;
-
-        if (!debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_tx_chainmask))
-                goto err;
-
-        if (!debugfs_create_file("regidx", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_regidx))
-                goto err;
-
-        if (!debugfs_create_file("regval", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, sc, &fops_regval))
-                goto err;
+        ath9k_ps_wakeup(sc);
+        for (i = 0; i < num_regs; i++)
+                len += scnprintf(buf + len, regdump_len - len,
+                        "0x%06x 0x%08x\n", i << 2, REG_READ(sc->sc_ah, i << 2));
+        ath9k_ps_restore(sc);
 
-        if (!debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
-                        sc->debug.debugfs_phy, &ah->config.cwm_ignore_extcca))
-                goto err;
+        file->private_data = buf;
 
-        sc->debug.regidx = 0;
         return 0;
-err:
-        ath9k_exit_debug(ah);
-        return -ENOMEM;
 }
 
-void ath9k_exit_debug(struct ath_hw *ah)
+static const struct file_operations fops_regdump = {
+        .open = open_file_regdump,
+        .read = ath9k_debugfs_read_buf,
+        .release = ath9k_debugfs_release_buf,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,/* read accesses f_pos */
+};
+
+int ath9k_init_debug(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_softc *sc = (struct ath_softc *) common->priv;
 
-        debugfs_remove_recursive(sc->debug.debugfs_phy);
-}
+        sc->debug.debugfs_phy = debugfs_create_dir("ath9k",
+                                                   sc->hw->wiphy->debugfsdir);
+        if (!sc->debug.debugfs_phy)
+                return -ENOMEM;
 
-int ath9k_debug_create_root(void)
-{
-        ath9k_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
+#ifdef CONFIG_ATH_DEBUG
+        debugfs_create_file("debug", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_debug);
+#endif
+        debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_dma);
+        debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_interrupt);
+        debugfs_create_file("wiphy", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_wiphy);
+        debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_xmit);
+        debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_stations);
+        debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_misc);
+        debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_recv);
+        debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
+                            sc->debug.debugfs_phy, sc, &fops_rx_chainmask);
+        debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
+                            sc->debug.debugfs_phy, sc, &fops_tx_chainmask);
+        debugfs_create_file("regidx", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_regidx);
+        debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
+                            sc, &fops_regval);
+        debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
+                            sc->debug.debugfs_phy,
+                            &ah->config.cwm_ignore_extcca);
+        debugfs_create_file("regdump", S_IRUSR, sc->debug.debugfs_phy, sc,
+                            &fops_regdump);
+
+        debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
+                           sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
+
+        debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
+                           sc->debug.debugfs_phy, &sc->sc_ah->gpio_val);
 
+        sc->debug.regidx = 0;
         return 0;
 }
-
-void ath9k_debug_remove_root(void)
-{
-        debugfs_remove(ath9k_debugfs_root);
-        ath9k_debugfs_root = NULL;
-}
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 5d21704e87ff..8ce6ad80f4e2 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -54,6 +54,9 @@ struct ath_buf;
  * @dtimsync: DTIM sync lossage
  * @dtim: RX Beacon with DTIM
  * @bb_watchdog: Baseband watchdog
+ * @tsfoor: TSF out of range, indicates that the corrected TSF received
+ * from a beacon differs from the PCU's internal TSF by more than a
+ * (programmable) threshold
  */
 struct ath_interrupt_stats {
         u32 total;
@@ -78,21 +81,20 @@ struct ath_interrupt_stats {
         u32 dtimsync;
         u32 dtim;
         u32 bb_watchdog;
-};
-
-struct ath_rc_stats {
-        u32 success;
-        u32 retries;
-        u32 xretries;
-        u8 per;
+        u32 tsfoor;
 };
 
 /**
  * struct ath_tx_stats - Statistics about TX
+ * @tx_pkts_all:  No. of total frames transmitted, including ones that
+        may have had errors.
+ * @tx_bytes_all:  No. of total bytes transmitted, including ones that
+        may have had errors.
  * @queued: Total MPDUs (non-aggr) queued
  * @completed: Total MPDUs (non-aggr) completed
  * @a_aggr: Total no. of aggregates queued
- * @a_queued: Total AMPDUs queued
+ * @a_queued_hw: Total AMPDUs queued to hardware
+ * @a_queued_sw: Total AMPDUs queued to software queues
  * @a_completed: Total AMPDUs completed
  * @a_retries: No. of AMPDUs retried (SW)
  * @a_xretries: No. of AMPDUs dropped due to xretries
@@ -105,12 +107,18 @@ struct ath_rc_stats {
  * @desc_cfg_err: Descriptor configuration errors
  * @data_urn: TX data underrun errors
  * @delim_urn: TX delimiter underrun errors
+ * @puttxbuf: Number of times hardware was given txbuf to write.
+ * @txstart:  Number of times hardware was told to start tx.
+ * @txprocdesc:  Number of times tx descriptor was processed
  */
 struct ath_tx_stats {
+        u32 tx_pkts_all;
+        u32 tx_bytes_all;
         u32 queued;
         u32 completed;
         u32 a_aggr;
-        u32 a_queued;
+        u32 a_queued_hw;
+        u32 a_queued_sw;
         u32 a_completed;
         u32 a_retries;
         u32 a_xretries;
@@ -120,10 +128,17 @@ struct ath_tx_stats {
         u32 desc_cfg_err;
         u32 data_underrun;
         u32 delim_underrun;
+        u32 puttxbuf;
+        u32 txstart;
+        u32 txprocdesc;
 };
 
 /**
  * struct ath_rx_stats - RX Statistics
+ * @rx_pkts_all:  No. of total frames received, including ones that
+        may have had errors.
+ * @rx_bytes_all:  No. of total bytes received, including ones that
+        may have had errors.
  * @crc_err: No. of frames with incorrect CRC value
  * @decrypt_crc_err: No. of frames whose CRC check failed after
         decryption process completed
@@ -136,6 +151,8 @@ struct ath_tx_stats {
  * @phy_err_stats: Individual PHY error statistics
  */
 struct ath_rx_stats {
+        u32 rx_pkts_all;
+        u32 rx_bytes_all;
         u32 crc_err;
         u32 decrypt_crc_err;
         u32 phy_err;
@@ -144,11 +161,17 @@ struct ath_rx_stats {
         u32 post_delim_crc_err;
         u32 decrypt_busy_err;
         u32 phy_err_stats[ATH9K_PHYERR_MAX];
+        int8_t rs_rssi_ctl0;
+        int8_t rs_rssi_ctl1;
+        int8_t rs_rssi_ctl2;
+        int8_t rs_rssi_ext0;
+        int8_t rs_rssi_ext1;
+        int8_t rs_rssi_ext2;
+        u8 rs_antenna;
 };
 
 struct ath_stats {
         struct ath_interrupt_stats istats;
-        struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
         struct ath_rx_stats rxstats;
 };
@@ -160,17 +183,11 @@ struct ath9k_debug {
 };
 
 int ath9k_init_debug(struct ath_hw *ah);
-void ath9k_exit_debug(struct ath_hw *ah);
 
-int ath9k_debug_create_root(void);
-void ath9k_debug_remove_root(void);
 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
-void ath_debug_stat_rc(struct ath_softc *sc, int final_rate);
-void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-                       struct ath_buf *bf, struct ath_tx_status *ts);
+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
+                       struct ath_tx_status *ts, struct ath_txq *txq);
 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
-void ath_debug_stat_retries(struct ath_softc *sc, int rix,
-                            int xretries, int retries, u8 per);
 
 #else
 
@@ -179,33 +196,15 @@ static inline int ath9k_init_debug(struct ath_hw *ah)
         return 0;
 }
 
-static inline void ath9k_exit_debug(struct ath_hw *ah)
-{
-}
-
-static inline int ath9k_debug_create_root(void)
-{
-        return 0;
-}
-
-static inline void ath9k_debug_remove_root(void)
-{
-}
-
 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
                                             enum ath9k_int status)
 {
 }
 
-static inline void ath_debug_stat_rc(struct ath_softc *sc,
-                                     int final_rate)
-{
-}
-
 static inline void ath_debug_stat_tx(struct ath_softc *sc,
-                                     struct ath_txq *txq,
                                      struct ath_buf *bf,
-                                     struct ath_tx_status *ts)
+                                     struct ath_tx_status *ts,
+                                     struct ath_txq *txq)
 {
 }
 
@@ -214,11 +213,6 @@ static inline void ath_debug_stat_rx(struct ath_softc *sc,
 {
 }
 
-static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
-                                          int xretries, int retries, u8 per)
-{
-}
-
 #endif /* CONFIG_ATH9K_DEBUGFS */
 
 #endif /* DEBUG_H */
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 1266333f586d..e61404dda8c5 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -89,6 +89,38 @@ bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
         return false;
 }
 
+void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
+                                  int eep_start_loc, int size)
+{
+        int i = 0, j, addr;
+        u32 addrdata[8];
+        u32 data[8];
+
+        for (addr = 0; addr < size; addr++) {
+                addrdata[i] = AR5416_EEPROM_OFFSET +
+                        ((addr + eep_start_loc) << AR5416_EEPROM_S);
+                i++;
+                if (i == 8) {
+                        REG_READ_MULTI(ah, addrdata, data, i);
+
+                        for (j = 0; j < i; j++) {
+                                *eep_data = data[j];
+                                eep_data++;
+                        }
+                        i = 0;
+                }
+        }
+
+        if (i != 0) {
+                REG_READ_MULTI(ah, addrdata, data, i);
+
+                for (j = 0; j < i; j++) {
+                        *eep_data = data[j];
+                        eep_data++;
+                }
+        }
+}
+
 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
 {
         return common->bus_ops->eeprom_read(common, off, data);
@@ -234,22 +266,22 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah,
 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
                                 bool is2GHz, int num_band_edges)
 {
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         int i;
 
         for (i = 0; (i < num_band_edges) &&
                      (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
-                        twiceMaxEdgePower = pRdEdgesPower[i].tPower;
+                        twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
                         break;
                 } else if ((i > 0) &&
                            (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
                                                       is2GHz))) {
                         if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
                                                is2GHz) < freq &&
-                            pRdEdgesPower[i - 1].flag) {
+                            CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
                                 twiceMaxEdgePower =
-                                        pRdEdgesPower[i - 1].tPower;
+                                        CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
                         }
                         break;
                 }
@@ -273,12 +305,225 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
                 break;
         default:
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Invalid chainmask configuration\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Invalid chainmask configuration\n");
                 break;
         }
 }
 
+void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                void *pRawDataSet,
+                                u8 *bChans, u16 availPiers,
+                                u16 tPdGainOverlap,
+                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
+                                u16 numXpdGains)
+{
+        int i, j, k;
+        int16_t ss;
+        u16 idxL = 0, idxR = 0, numPiers;
+        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+        u8 minPwrT4[AR5416_NUM_PD_GAINS];
+        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
+        int16_t vpdStep;
+        int16_t tmpVal;
+        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
+        bool match;
+        int16_t minDelta = 0;
+        struct chan_centers centers;
+        int pdgain_boundary_default;
+        struct cal_data_per_freq *data_def = pRawDataSet;
+        struct cal_data_per_freq_4k *data_4k = pRawDataSet;
+        struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
+        bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
+        int intercepts;
+
+        if (AR_SREV_9287(ah))
+                intercepts = AR9287_PD_GAIN_ICEPTS;
+        else
+                intercepts = AR5416_PD_GAIN_ICEPTS;
+
+        memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
+        ath9k_hw_get_channel_centers(ah, chan, &centers);
+
+        for (numPiers = 0; numPiers < availPiers; numPiers++) {
+                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
+                        break;
+        }
+
+        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
+                                                             IS_CHAN_2GHZ(chan)),
+                                               bChans, numPiers, &idxL, &idxR);
+
+        if (match) {
+                if (AR_SREV_9287(ah)) {
+                        /* FIXME: array overrun? */
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_9287[idxL].pwrPdg[i],
+                                                data_9287[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                } else if (eeprom_4k) {
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_4k[idxL].pwrPdg[i],
+                                                data_4k[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                } else {
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_def[idxL].pwrPdg[i],
+                                                data_def[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                }
+        } else {
+                for (i = 0; i < numXpdGains; i++) {
+                        if (AR_SREV_9287(ah)) {
+                                pVpdL = data_9287[idxL].vpdPdg[i];
+                                pPwrL = data_9287[idxL].pwrPdg[i];
+                                pVpdR = data_9287[idxR].vpdPdg[i];
+                                pPwrR = data_9287[idxR].pwrPdg[i];
+                        } else if (eeprom_4k) {
+                                pVpdL = data_4k[idxL].vpdPdg[i];
+                                pPwrL = data_4k[idxL].pwrPdg[i];
+                                pVpdR = data_4k[idxR].vpdPdg[i];
+                                pPwrR = data_4k[idxR].pwrPdg[i];
+                        } else {
+                                pVpdL = data_def[idxL].vpdPdg[i];
+                                pPwrL = data_def[idxL].pwrPdg[i];
+                                pVpdR = data_def[idxR].vpdPdg[i];
+                                pPwrR = data_def[idxR].pwrPdg[i];
+                        }
+
+                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
+
+                        maxPwrT4[i] =
+                                min(pPwrL[intercepts - 1],
+                                    pPwrR[intercepts - 1]);
+
+
+                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                pPwrL, pVpdL,
+                                                intercepts,
+                                                vpdTableL[i]);
+                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                pPwrR, pVpdR,
+                                                intercepts,
+                                                vpdTableR[i]);
+
+                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
+                                vpdTableI[i][j] =
+                                        (u8)(ath9k_hw_interpolate((u16)
+                                             FREQ2FBIN(centers.
+                                                       synth_center,
+                                                       IS_CHAN_2GHZ
+                                                       (chan)),
+                                             bChans[idxL], bChans[idxR],
+                                             vpdTableL[i][j], vpdTableR[i][j]));
+                        }
+                }
+        }
+
+        k = 0;
+
+        for (i = 0; i < numXpdGains; i++) {
+                if (i == (numXpdGains - 1))
+                        pPdGainBoundaries[i] =
+                                (u16)(maxPwrT4[i] / 2);
+                else
+                        pPdGainBoundaries[i] =
+                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
+
+                pPdGainBoundaries[i] =
+                        min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
+
+                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
+                        minDelta = pPdGainBoundaries[0] - 23;
+                        pPdGainBoundaries[0] = 23;
+                } else {
+                        minDelta = 0;
+                }
+
+                if (i == 0) {
+                        if (AR_SREV_9280_20_OR_LATER(ah))
+                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
+                        else
+                                ss = 0;
+                } else {
+                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
+                                        (minPwrT4[i] / 2)) -
+                                       tPdGainOverlap + 1 + minDelta);
+                }
+                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
+                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+
+                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
+                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
+                        ss++;
+                }
+
+                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
+                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
+                                (minPwrT4[i] / 2));
+                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
+                        tgtIndex : sizeCurrVpdTable;
+
+                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                        pPDADCValues[k++] = vpdTableI[i][ss++];
+                }
+
+                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
+                                    vpdTableI[i][sizeCurrVpdTable - 2]);
+                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+
+                if (tgtIndex >= maxIndex) {
+                        while ((ss <= tgtIndex) &&
+                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
+                                                    (ss - maxIndex + 1) * vpdStep));
+                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
+                                                         255 : tmpVal);
+                                ss++;
+                        }
+                }
+        }
+
+        if (eeprom_4k)
+                pdgain_boundary_default = 58;
+        else
+                pdgain_boundary_default = pPdGainBoundaries[i - 1];
+
+        while (i < AR5416_PD_GAINS_IN_MASK) {
+                pPdGainBoundaries[i] = pdgain_boundary_default;
+                i++;
+        }
+
+        while (k < AR5416_NUM_PDADC_VALUES) {
+                pPDADCValues[k] = pPDADCValues[k - 1];
+                k++;
+        }
+}
+
 int ath9k_hw_eeprom_init(struct ath_hw *ah)
 {
         int status;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 0b09db0f8e7d..de99c0da52e4 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,12 +17,12 @@
 #ifndef EEPROM_H
 #define EEPROM_H
 
+#define AR_EEPROM_MODAL_SPURS   5
+
 #include "../ath.h"
 #include <net/cfg80211.h>
 #include "ar9003_eeprom.h"
 
-#define AH_USE_EEPROM   0x1
-
 #ifdef __BIG_ENDIAN
 #define AR5416_EEPROM_MAGIC 0x5aa5
 #else
@@ -101,7 +101,7 @@
 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
-#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
+#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 
 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
@@ -149,8 +149,6 @@
 #define AR5416_NUM_PD_GAINS             4
 #define AR5416_PD_GAINS_IN_MASK         4
 #define AR5416_PD_GAIN_ICEPTS           5
-#define AR5416_EEPROM_MODAL_SPURS       5
-#define AR5416_MAX_RATE_POWER           63
 #define AR5416_NUM_PDADC_VALUES         128
 #define AR5416_BCHAN_UNUSED             0xFF
 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
@@ -175,8 +173,6 @@
 #define AR5416_EEP4K_NUM_CTLS                 12
 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 #define AR5416_EEP4K_NUM_PD_GAINS             2
-#define AR5416_EEP4K_PD_GAINS_IN_MASK         4
-#define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 #define AR5416_EEP4K_MAX_CHAINS               1
 
 #define AR9280_TX_GAIN_TABLE_SIZE 22
@@ -198,41 +194,30 @@
 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 #define AR9287_NUM_CTLS                 12
 #define AR9287_NUM_BAND_EDGES           4
-#define AR9287_NUM_PD_GAINS             4
-#define AR9287_PD_GAINS_IN_MASK         4
 #define AR9287_PD_GAIN_ICEPTS           1
-#define AR9287_EEPROM_MODAL_SPURS       5
-#define AR9287_MAX_RATE_POWER           63
-#define AR9287_NUM_PDADC_VALUES         128
-#define AR9287_NUM_RATES                16
-#define AR9287_BCHAN_UNUSED             0xFF
-#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
-#define AR9287_OPFLAGS_11A              0x01
-#define AR9287_OPFLAGS_11G              0x02
-#define AR9287_OPFLAGS_2G_HT40          0x08
-#define AR9287_OPFLAGS_2G_HT20          0x20
-#define AR9287_OPFLAGS_5G_HT40          0x04
-#define AR9287_OPFLAGS_5G_HT20          0x10
 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 #define AR9287_EEPMISC_WOW              0x02
 #define AR9287_MAX_CHAINS               2
 #define AR9287_ANT_16S                  32
-#define AR9287_custdatasize             20
-
-#define AR9287_NUM_ANT_CHAIN_FIELDS     6
-#define AR9287_NUM_ANT_COMMON_FIELDS    4
-#define AR9287_SIZE_ANT_CHAIN_FIELD     2
-#define AR9287_SIZE_ANT_COMMON_FIELD    4
-#define AR9287_ANT_CHAIN_MASK           0x3
-#define AR9287_ANT_COMMON_MASK          0xf
-#define AR9287_CHAIN_0_IDX              0
-#define AR9287_CHAIN_1_IDX              1
+
 #define AR9287_DATA_SZ                  32
 
 #define AR9287_PWR_TABLE_OFFSET_DB  -5
 
 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
 
+#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
+#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
+
+#define LNA_CTL_BUF_MODE        BIT(0)
+#define LNA_CTL_ISEL_LO         BIT(1)
+#define LNA_CTL_ISEL_HI         BIT(2)
+#define LNA_CTL_BUF_IN          BIT(3)
+#define LNA_CTL_FEM_BAND        BIT(4)
+#define LNA_CTL_LOCAL_BIAS      BIT(5)
+#define LNA_CTL_FORCE_XPA       BIT(6)
+#define LNA_CTL_USE_ANT1        BIT(7)
+
 enum eeprom_param {
         EEP_NFTHRESH_5,
         EEP_NFTHRESH_2,
@@ -266,6 +251,9 @@ enum eeprom_param {
         EEP_INTERNAL_REGULATOR,
         EEP_SWREG,
         EEP_PAPRD,
+        EEP_MODAL_VER,
+        EEP_ANT_DIV_CTL1,
+        EEP_CHAIN_MASK_REDUCE
 };
 
 enum ar5416_rates {
@@ -376,15 +364,12 @@ struct modal_eep_header {
         u8 xatten2Margin[AR5416_MAX_CHAINS];
         u8 ob_ch1;
         u8 db_ch1;
-        u8 useAnt1:1,
-            force_xpaon:1,
-            local_bias:1,
-            femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
+        u8 lna_ctl;
         u8 miscBits;
         u16 xpaBiasLvlFreq[3];
         u8 futureModal[6];
 
-        struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct calDataPerFreqOpLoop {
@@ -451,8 +436,12 @@ struct modal_eep_4k_header {
         u8 db2_2:4, db2_3:4;
         u8 db2_4:4, reserved:4;
 #endif
-        u8 futureModal[4];
-        struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
+        u8 tx_diversity;
+        u8 flc_pwr_thresh;
+        u8 bb_scale_smrt_antenna;
+#define EEP_4K_BB_DESIRED_SCALE_MASK    0x1f
+        u8 futureModal[1];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct base_eep_ar9287_header {
@@ -510,7 +499,7 @@ struct modal_eep_ar9287_header {
         u8 ob_qam;
         u8 ob_pal_off;
         u8 futureModal[30];
-        struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct cal_data_per_freq {
@@ -519,8 +508,8 @@ struct cal_data_per_freq {
 } __packed;
 
 struct cal_data_per_freq_4k {
-        u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
-        u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
+        u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+        u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 } __packed;
 
 struct cal_target_power_leg {
@@ -533,18 +522,10 @@ struct cal_target_power_ht {
         u8 tPow2x[8];
 } __packed;
 
-
-#ifdef __BIG_ENDIAN_BITFIELD
 struct cal_ctl_edges {
         u8 bChannel;
-        u8 flag:2, tPower:6;
+        u8 ctl;
 } __packed;
-#else
-struct cal_ctl_edges {
-        u8 bChannel;
-        u8 tPower:6, flag:2;
-} __packed;
-#endif
 
 struct cal_data_op_loop_ar9287 {
         u8 pwrPdg[2][5];
@@ -554,8 +535,8 @@ struct cal_data_op_loop_ar9287 {
 } __packed;
 
 struct cal_data_per_freq_ar9287 {
-        u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
-        u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+        u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+        u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 } __packed;
 
 union cal_data_per_freq_ar9287_u {
@@ -670,14 +651,12 @@ struct eeprom_ops {
         bool (*fill_eeprom)(struct ath_hw *hw);
         int (*get_eeprom_ver)(struct ath_hw *hw);
         int (*get_eeprom_rev)(struct ath_hw *hw);
-        u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
-        u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
-                                      struct ath9k_channel *chan);
         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
                            u16 cfgCtl, u8 twiceAntennaReduction,
-                           u8 twiceMaxRegulatoryPower, u8 powerLimit);
+                           u8 twiceMaxRegulatoryPower, u8 powerLimit,
+                           bool test);
         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 };
 
@@ -690,6 +669,8 @@ int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
                                     u16 *indexL, u16 *indexR);
 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
+void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
+                                  int eep_start_loc, int size);
 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
                              u8 *pVpdList, u16 numIntercepts,
                              u8 *pRetVpdList);
@@ -710,6 +691,14 @@ u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 
+void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                void *pRawDataSet,
+                                u8 *bChans, u16 availPiers,
+                                u16 tPdGainOverlap,
+                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
+                                u16 numXpdGains);
+
 #define ar5416_get_ntxchains(_txchainmask)                      \
         (((_txchainmask >> 2) & 1) +                            \
          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 9cccd12e8f21..5b1e894f3d67 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -27,33 +27,52 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
 }
 
-static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
-{
 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
+
+static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
+{
         struct ath_common *common = ath9k_hw_common(ah);
         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
-        int addr, eep_start_loc = 0;
-
-        eep_start_loc = 64;
-
-        if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Reading from EEPROM, not flash\n");
-        }
+        int addr, eep_start_loc = 64;
 
         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Unable to read eeprom region\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
         }
 
         return true;
-#undef SIZE_EEPROM_4K
 }
 
+static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
+{
+        u16 *eep_data = (u16 *)&ah->eeprom.map4k;
+
+        ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
+
+        return true;
+}
+
+static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!ath9k_hw_use_flash(ah)) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
+        }
+
+        if (common->bus_ops->ath_bus_type == ATH_USB)
+                return __ath9k_hw_usb_4k_fill_eeprom(ah);
+        else
+                return __ath9k_hw_4k_fill_eeprom(ah);
+}
+
+#undef SIZE_EEPROM_4K
+
 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 {
 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
@@ -69,13 +88,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
         if (!ath9k_hw_use_flash(ah)) {
                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
                                          &magic)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Reading Magic # failed\n");
+                        ath_err(common, "Reading Magic # failed\n");
                         return false;
                 }
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -90,16 +108,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -120,8 +137,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                 u32 integer;
                 u16 word;
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "EEPROM Endianness is not native.. Changing\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "EEPROM Endianness is not native.. Changing\n");
 
                 word = swab16(eep->baseEepHeader.length);
                 eep->baseEepHeader.length = word;
@@ -155,7 +172,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                         eep->modalHeader.antCtrlChain[i] = integer;
                 }
 
-                for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
                         eep->modalHeader.spurChans[i].spurChan = word;
                 }
@@ -163,9 +180,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
-                          sum, ah->eep_ops->get_eeprom_ver(ah));
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                        sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
@@ -179,6 +195,9 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
         struct modal_eep_4k_header *pModal = &eep->modalHeader;
         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
+        u16 ver_minor;
+
+        ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 
         switch (param) {
         case EEP_NFTHRESH_2:
@@ -204,7 +223,7 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
         case EEP_DB_2:
                 return pModal->db1_1;
         case EEP_MINOR_REV:
-                return pBase->version & AR5416_EEP_VER_MINOR_MASK;
+                return ver_minor;
         case EEP_TX_MASK:
                 return pBase->txMask;
         case EEP_RX_MASK:
@@ -213,178 +232,20 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
                 return 0;
         case EEP_PWR_TABLE_OFFSET:
                 return AR5416_PWR_TABLE_OFFSET_DB;
+        case EEP_MODAL_VER:
+                return pModal->version;
+        case EEP_ANT_DIV_CTL1:
+                return pModal->antdiv_ctl1;
+        case EEP_TXGAIN_TYPE:
+                if (ver_minor >= AR5416_EEP_MINOR_VER_19)
+                        return pBase->txGainType;
+                else
+                        return AR5416_EEP_TXGAIN_ORIGINAL;
         default:
                 return 0;
         }
 }
 
-static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
-                                struct ath9k_channel *chan,
-                                struct cal_data_per_freq_4k *pRawDataSet,
-                                u8 *bChans, u16 availPiers,
-                                u16 tPdGainOverlap,
-                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
-                                u16 numXpdGains)
-{
-#define TMP_VAL_VPD_TABLE \
-        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
-        u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-#define PD_GAIN_BOUNDARY_DEFAULT 58;
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index(
-                                        (u8)FREQ2FBIN(centers.synth_center,
-                                        IS_CHAN_2GHZ(chan)), bChans, numPiers,
-                                        &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                        pRawDataSet[idxL].pwrPdg[i],
-                                        pRawDataSet[idxL].vpdPdg[i],
-                                        AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                        vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] =
-                                min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
-                                    pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
-
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] =
-                                        (u8)(ath9k_hw_interpolate((u16)
-                                             FREQ2FBIN(centers.
-                                                       synth_center,
-                                                       IS_CHAN_2GHZ
-                                                       (chan)),
-                                             bChans[idxL], bChans[idxR],
-                                             vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
-
-                pPdGainBoundaries[i] =
-                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
-
-                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
-                        minDelta = pPdGainBoundaries[0] - 23;
-                        pPdGainBoundaries[0] = 23;
-                } else {
-                        minDelta = 0;
-                }
-
-                if (i == 0) {
-                        if (AR_SREV_9280_10_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
-                                (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                        tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex >= maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
-                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
-                                                         255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
-                i++;
-        }
-
-        while (k < AR5416_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k - 1];
-                k++;
-        }
-
-        return;
-#undef TMP_VAL_VPD_TABLE
-}
-
 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                                   struct ath9k_channel *chan,
                                   int16_t *pTxPowerIndexOffset)
@@ -395,7 +256,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
         u8 *pCalBChans = NULL;
         u16 pdGainOverlap_t2;
         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
-        u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
+        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
         u16 numPiers, i, j;
         u16 numXpdGain, xpdMask;
         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
@@ -417,12 +278,12 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 
         numXpdGain = 0;
 
-        for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
-                if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
+        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
                                 break;
                         xpdGainValues[numXpdGain] =
-                                (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
+                                (u16)(AR5416_PD_GAINS_IN_MASK - i);
                         numXpdGain++;
                 }
         }
@@ -446,7 +307,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
                         pRawDataset = pEepData->calPierData2G[i];
 
-                        ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
+                        ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
                                             pRawDataset, pCalBChans,
                                             numPiers, pdGainOverlap_t2,
                                             gainBoundaries,
@@ -476,27 +337,25 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
                                 REG_WRITE(ah, regOffset, reg32);
 
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
-                                          i, regChainOffset, regOffset,
-                                          reg32);
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC: Chain %d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d |\n",
-                                          i, 4 * j, pdadcValues[4 * j],
-                                          4 * j + 1, pdadcValues[4 * j + 1],
-                                          4 * j + 2, pdadcValues[4 * j + 2],
-                                          4 * j + 3,
-                                          pdadcValues[4 * j + 3]);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
+                                        i, regChainOffset, regOffset,
+                                        reg32);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC: Chain %d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d |\n",
+                                        i, 4 * j, pdadcValues[4 * j],
+                                        4 * j + 1, pdadcValues[4 * j + 1],
+                                        4 * j + 2, pdadcValues[4 * j + 2],
+                                        4 * j + 3, pdadcValues[4 * j + 3]);
 
                                 regOffset += 4;
                         }
 
                         REGWRITE_BUFFER_FLUSH(ah);
-                        DISABLE_REGWRITE_BUFFER(ah);
                 }
         }
 
@@ -521,14 +380,16 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
         int i;
         int16_t twiceLargestAntenna;
         u16 twiceMinEdgePower;
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         struct cal_ctl_data_4k *rep;
         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
                 0, { 0, 0, 0, 0}
         };
@@ -539,10 +400,10 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
                 0, {0, 0, 0, 0}
         };
-        u16 ctlModesFor11g[] =
-                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
-                  CTL_2GHT40
-                };
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
 
         ath9k_hw_get_channel_centers(ah, chan, &centers);
 
@@ -604,7 +465,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 
                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+                        twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
                              pEepData->ctlIndex[i]; i++) {
@@ -715,7 +576,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
                                     u16 cfgCtl,
                                     u8 twiceAntennaReduction,
                                     u8 twiceMaxRegulatoryPower,
-                                    u8 powerLimit)
+                                    u8 powerLimit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
@@ -740,15 +601,20 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
-                        ratesArray[i] = AR5416_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
         }
 
+        if (test)
+            return;
 
         /* Update regulatory */
-
         i = rate6mb;
         if (IS_CHAN_HT40(chan))
                 i = rateHt40_0;
@@ -757,7 +623,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 
         regulatory->max_power_level = ratesArray[i];
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++)
                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
         }
@@ -828,7 +694,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
@@ -905,9 +770,6 @@ static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
-
-        if (AR_SREV_9285_11(ah))
-                REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
 }
 
 /*
@@ -919,6 +781,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 {
         struct modal_eep_4k_header *pModal;
         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
+        struct base_eep_header_4k *pBase = &eep->baseEepHeader;
         u8 txRxAttenLocal;
         u8 ob[5], db1[5], db2[5];
         u8 ant_div_control1, ant_div_control2;
@@ -927,8 +790,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
         pModal = &eep->modalHeader;
         txRxAttenLocal = 23;
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 
         /* Single chain for 4K EEPROM*/
         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
@@ -1105,9 +967,6 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
         }
 
 
-        if (AR_SREV_9285_11(ah))
-                REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
-
         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
                       pModal->switchSettling);
         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
@@ -1145,21 +1004,31 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
                                       AR_PHY_SETTLING_SWITCH,
                                       pModal->swSettleHt40);
         }
-}
-
-static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                              struct ath9k_channel *chan)
-{
-        struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
-        struct modal_eep_4k_header *pModal = &eep->modalHeader;
-
-        return pModal->antCtrlCommon;
-}
-
-static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
-                                         enum ieee80211_band freq_band)
-{
-        return 1;
+        if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {
+                u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
+                                EEP_4K_BB_DESIRED_SCALE_MASK);
+                if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
+                        u32 pwrctrl, mask, clr;
+
+                        mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
+                        pwrctrl = mask * bb_desired_scale;
+                        clr = mask * 0x1f;
+                        REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
+                        REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
+                        REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
+
+                        mask = BIT(0)|BIT(5)|BIT(15);
+                        pwrctrl = mask * bb_desired_scale;
+                        clr = mask * 0x1f;
+                        REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
+
+                        mask = BIT(0)|BIT(5);
+                        pwrctrl = mask * bb_desired_scale;
+                        clr = mask * 0x1f;
+                        REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
+                        REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
+                }
+        }
 }
 
 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
@@ -1170,17 +1039,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_MAP4K_SPURCHAN;
@@ -1198,8 +1067,6 @@ const struct eeprom_ops eep_4k_ops = {
         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_4k_set_board_values,
         .set_addac              = ath9k_hw_4k_set_addac,
         .set_txpower            = ath9k_hw_4k_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index dff2da777312..343fc9f946db 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,7 +17,7 @@
 #include "hw.h"
 #include "ar9002_phy.h"
 
-#define NUM_EEP_WORDS (sizeof(struct ar9287_eeprom) / sizeof(u16))
+#define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
 
 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
 {
@@ -29,29 +29,19 @@ static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
         return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
 }
 
-static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
+static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
 {
         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
         struct ath_common *common = ath9k_hw_common(ah);
         u16 *eep_data;
-        int addr, eep_start_loc;
+        int addr, eep_start_loc = AR9287_EEP_START_LOC;
         eep_data = (u16 *)eep;
 
-        if (ah->hw_version.devid == 0x7015)
-                eep_start_loc = AR9287_HTC_EEP_START_LOC;
-        else
-                eep_start_loc = AR9287_EEP_START_LOC;
-
-        if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Reading from EEPROM, not flash\n");
-        }
-
-        for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
+        for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
                                          eep_data)) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Unable to read eeprom region\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
@@ -60,6 +50,31 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
         return true;
 }
 
+static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
+{
+        u16 *eep_data = (u16 *)&ah->eeprom.map9287;
+
+        ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
+                                     AR9287_HTC_EEP_START_LOC,
+                                     SIZE_EEPROM_AR9287);
+        return true;
+}
+
+static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!ath9k_hw_use_flash(ah)) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
+        }
+
+        if (common->bus_ops->ath_bus_type == ATH_USB)
+                return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
+        else
+                return __ath9k_hw_ar9287_fill_eeprom(ah);
+}
+
 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
 {
         u32 sum = 0, el, integer;
@@ -72,13 +87,12 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
         if (!ath9k_hw_use_flash(ah)) {
                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
                                          &magic)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Reading Magic # failed\n");
+                        ath_err(common, "Reading Magic # failed\n");
                         return false;
                 }
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -87,22 +101,21 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
                                 need_swap = true;
                                 eepdata = (u16 *)(&ah->eeprom);
 
-                                for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
+                                for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
                                         temp = swab16(*eepdata);
                                         *eepdata = temp;
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "Endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -152,7 +165,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
                         eep->modalHeader.antCtrlChain[i] = integer;
                 }
 
-                for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
+                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
                         eep->modalHeader.spurChans[i].spurChan = word;
                 }
@@ -160,9 +173,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
             || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
-                           sum, ah->eep_ops->get_eeprom_ver(ah));
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                        sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
@@ -223,163 +235,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
         }
 }
 
-static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
-                               struct ath9k_channel *chan,
-                               struct cal_data_per_freq_ar9287 *pRawDataSet,
-                               u8 *bChans, u16 availPiers,
-                               u16 tPdGainOverlap,
-                               u16 *pPdGainBoundaries,
-                               u8 *pPDADCValues,
-                               u16 numXpdGains)
-{
-#define TMP_VAL_VPD_TABLE                                               \
-        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
-
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR9287_NUM_PD_GAINS];
-        u8 maxPwrT4[AR9287_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index(
-                (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
-                bChans, numPiers, &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pRawDataSet[idxL].pwrPdg[i],
-                                                pRawDataSet[idxL].vpdPdg[i],
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
-                                          pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
-                                       (u16)FREQ2FBIN(centers. synth_center,
-                                                      IS_CHAN_2GHZ(chan)),
-                                       bChans[idxL], bChans[idxR],
-                                       vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
-
-                pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
-                                           pPdGainBoundaries[i]);
-
-
-                minDelta = 0;
-
-                if (i == 0) {
-                        if (AR_SREV_9280_10_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i-1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] +
-                                tPdGainOverlap - (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                            tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex > maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                                (k < (AR9287_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
-                                pPDADCValues[k++] =
-                                        (u8)((tmpVal > 255) ? 255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR9287_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
-                i++;
-        }
-
-        while (k < AR9287_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k-1];
-                k++;
-        }
-
-#undef TMP_VAL_VPD_TABLE
-}
-
 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
                             struct ath9k_channel *chan,
                             struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
@@ -392,7 +247,7 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
         ath9k_hw_get_channel_centers(ah, chan, &centers);
 
         for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
+                if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
                         break;
         }
 
@@ -458,16 +313,15 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
         struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
         u8 *pCalBChans = NULL;
         u16 pdGainOverlap_t2;
-        u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
-        u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
+        u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
+        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
         u16 numPiers = 0, i, j;
         u16 numXpdGain, xpdMask;
-        u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
+        u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
         u32 reg32, regOffset, regChainOffset, regval;
-        int16_t modalIdx, diff = 0;
+        int16_t diff = 0;
         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
 
-        modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
         xpdMask = pEepData->modalHeader.xpdGain;
 
         if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
@@ -490,12 +344,12 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
         numXpdGain = 0;
 
         /* Calculate the value of xpdgains from the xpdGain Mask */
-        for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
-                if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
-                        if (numXpdGain >= AR9287_NUM_PD_GAINS)
+        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
+                        if (numXpdGain >= AR5416_NUM_PD_GAINS)
                                 break;
                         xpdGainValues[numXpdGain] =
-                                (u16)(AR9287_PD_GAINS_IN_MASK-i);
+                                (u16)(AR5416_PD_GAINS_IN_MASK-i);
                         numXpdGain++;
                 }
         }
@@ -528,7 +382,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                         (struct cal_data_per_freq_ar9287 *)
                                         pEepData->calPierData2G[i];
 
-                                ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan,
+                                ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
                                                            pRawDataset,
                                                            pCalBChans, numPiers,
                                                            pdGainOverlap_t2,
@@ -537,6 +391,8 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                                            numXpdGain);
                         }
 
+                        ENABLE_REGWRITE_BUFFER(ah);
+
                         if (i == 0) {
                                 if (!ath9k_hw_ar9287_get_eeprom(ah,
                                                         EEP_OL_PWRCTRL)) {
@@ -564,13 +420,13 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                              (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
                                 diff *= 2;
 
-                                for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++)
+                                for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
                                         pdadcValues[j] = pdadcValues[j+diff];
 
-                                for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
-                                     j < AR9287_NUM_PDADC_VALUES; j++)
+                                for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
+                                     j < AR5416_NUM_PDADC_VALUES; j++)
                                         pdadcValues[j] =
-                                          pdadcValues[AR9287_NUM_PDADC_VALUES-diff];
+                                          pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
                         }
 
                         if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
@@ -587,6 +443,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                         regOffset += 4;
                                 }
                         }
+                        REGWRITE_BUFFER_FLUSH(ah);
                 }
         }
 
@@ -613,9 +470,9 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
 
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
         int i;
         int16_t twiceLargestAntenna;
         struct cal_ctl_data_ar9287 *rep;
@@ -626,13 +483,13 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
         struct cal_target_power_ht targetPowerHt20,
                                     targetPowerHt40 = {0, {0, 0, 0, 0} };
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11g[] = {CTL_11B,
-                                CTL_11G,
-                                CTL_2GHT20,
-                                CTL_11B_EXT,
-                                CTL_11G_EXT,
-                                CTL_2GHT40};
-        u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
+        u16 numCtlModes = 0;
+        const u16 *pCtlMode = NULL;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         int tx_chainmask;
         u16 twiceMinEdgePower;
@@ -667,10 +524,16 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
         case 1:
                 break;
         case 2:
-                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         case 3:
-                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         }
         scaledPower = max((u16)0, scaledPower);
@@ -853,7 +716,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                                         struct ath9k_channel *chan, u16 cfgCtl,
                                         u8 twiceAntennaReduction,
                                         u8 twiceMaxRegulatoryPower,
-                                        u8 powerLimit)
+                                        u8 powerLimit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
@@ -877,17 +740,33 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR9287_MAX_RATE_POWER)
-                        ratesArray[i] = AR9287_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (test)
+                return;
+
+        if (IS_CHAN_2GHZ(chan))
+                i = rate1l;
+        else
+                i = rate6mb;
+
+        regulatory->max_power_level = ratesArray[i];
+
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++)
                         ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
         }
 
+        ENABLE_REGWRITE_BUFFER(ah);
+
         /* OFDM power per rate */
         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
@@ -971,17 +850,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
         }
-
-        if (IS_CHAN_2GHZ(chan))
-                i = rate1l;
-        else
-                i = rate6mb;
-
-        if (AR_SREV_9280_10_OR_LATER(ah))
-                regulatory->max_power_level =
-                        ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
-        else
-                regulatory->max_power_level = ratesArray[i];
+        REGWRITE_BUFFER_FLUSH(ah);
 }
 
 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
@@ -994,37 +863,13 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
 {
         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
-        u16 antWrites[AR9287_ANT_16S];
         u32 regChainOffset, regval;
         u8 txRxAttenLocal;
-        int i, j, offset_num;
+        int i;
 
         pModal = &eep->modalHeader;
 
-        antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
-        antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
-        antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
-        antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
-        antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
-        antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
-        antWrites[6] = (u16)((pModal->antCtrlCommon >> 4)  & 0xF);
-        antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
-
-        offset_num = 8;
-
-        for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
-                antWrites[j++] = 0;
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
-                antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
-                antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
-        }
-
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 
         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
                 regChainOffset = i * 0x1000;
@@ -1125,21 +970,6 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
                                   pModal->xpaBiasLvl);
 }
 
-static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
-                                             enum ieee80211_band freq_band)
-{
-        return 1;
-}
-
-static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                                  struct ath9k_channel *chan)
-{
-        struct ar9287_eeprom *eep = &ah->eeprom.map9287;
-        struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
-
-        return pModal->antCtrlCommon;
-}
-
 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
                                             u16 i, bool is2GHz)
 {
@@ -1149,17 +979,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
         struct ath_common *common = ath9k_hw_common(ah);
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_MAP9287_SPURCHAN;
@@ -1177,8 +1007,6 @@ const struct eeprom_ops eep_ar9287_ops = {
         .fill_eeprom            = ath9k_hw_ar9287_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_ar9287_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_ar9287_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_ar9287_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_ar9287_set_board_values,
         .set_addac              = ath9k_hw_ar9287_set_addac,
         .set_txpower            = ath9k_hw_ar9287_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index afa2b73ddbdd..17f0a6806207 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -86,9 +86,10 @@ static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
 }
 
-static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
-{
 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
+
+static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
+{
         struct ath_common *common = ath9k_hw_common(ah);
         u16 *eep_data = (u16 *)&ah->eeprom.def;
         int addr, ar5416_eep_start_loc = 0x100;
@@ -96,16 +97,41 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
                                          eep_data)) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "Unable to read eeprom region\n");
+                        ath_err(ath9k_hw_common(ah),
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
         }
         return true;
-#undef SIZE_EEPROM_DEF
 }
 
+static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
+{
+        u16 *eep_data = (u16 *)&ah->eeprom.def;
+
+        ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
+                                     0x100, SIZE_EEPROM_DEF);
+        return true;
+}
+
+static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!ath9k_hw_use_flash(ah)) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
+        }
+
+        if (common->bus_ops->ath_bus_type == ATH_USB)
+                return __ath9k_hw_usb_def_fill_eeprom(ah);
+        else
+                return __ath9k_hw_def_fill_eeprom(ah);
+}
+
+#undef SIZE_EEPROM_DEF
+
 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 {
         struct ar5416_eeprom_def *eep =
@@ -117,13 +143,13 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
         int i, addr, size;
 
         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
-                ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
+                ath_err(common, "Reading Magic # failed\n");
                 return false;
         }
 
         if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -139,16 +165,15 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "Endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -169,8 +194,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                 u32 integer, j;
                 u16 word;
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "EEPROM Endianness is not native.. Changing.\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "EEPROM Endianness is not native.. Changing.\n");
 
                 word = swab16(eep->baseEepHeader.length);
                 eep->baseEepHeader.length = word;
@@ -206,8 +231,12 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                                 integer = swab32(pModal->antCtrlChain[i]);
                                 pModal->antCtrlChain[i] = integer;
                         }
+                        for (i = 0; i < 3; i++) {
+                                word = swab16(pModal->xpaBiasLvlFreq[i]);
+                                pModal->xpaBiasLvlFreq[i] = word;
+                        }
 
-                        for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+                        for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                                 word = swab16(pModal->spurChans[i].spurChan);
                                 pModal->spurChans[i].spurChan = word;
                         }
@@ -216,18 +245,21 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
                         sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
         /* Enable fixup for AR_AN_TOP2 if necessary */
-        if (AR_SREV_9280_10_OR_LATER(ah) &&
-            (eep->baseEepHeader.version & 0xff) > 0x0a &&
-            eep->baseEepHeader.pwdclkind == 0)
+        if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
+            ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
+            (eep->baseEepHeader.pwdclkind == 0))
                 ah->need_an_top2_fixup = 1;
 
+        if ((common->bus_ops->ath_bus_type == ATH_USB) &&
+            (AR_SREV_9280(ah)))
+                eep->modalHeader[0].xpaBiasLvl = 0;
+
         return 0;
 }
 
@@ -317,7 +349,7 @@ static void ath9k_hw_def_set_gain(struct ath_hw *ah,
         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
                 txRxAttenLocal = pModal->txRxAttenCh[i];
 
-                if (AR_SREV_9280_10_OR_LATER(ah)) {
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
                               pModal->bswMargin[i]);
@@ -344,7 +376,7 @@ static void ath9k_hw_def_set_gain(struct ath_hw *ah,
                 }
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 REG_RMW_FIELD(ah,
                       AR_PHY_RXGAIN + regChainOffset,
                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
@@ -376,8 +408,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
 
         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
                 if (AR_SREV_9280(ah)) {
@@ -408,7 +439,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
                                               regChainOffset, i);
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 if (IS_CHAN_2GHZ(chan)) {
                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
                                                   AR_AN_RF2G1_CH0_OB,
@@ -451,9 +482,10 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
                                           AR_AN_TOP2_LOCALBIAS,
                                           AR_AN_TOP2_LOCALBIAS_S,
-                                          pModal->local_bias);
+                                          !!(pModal->lna_ctl &
+                                             LNA_CTL_LOCAL_BIAS));
                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
-                              pModal->force_xpaon);
+                              !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
         }
 
         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
@@ -461,7 +493,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
                       pModal->adcDesiredSize);
 
-        if (!AR_SREV_9280_10_OR_LATER(ah))
+        if (!AR_SREV_9280_20_OR_LATER(ah))
                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
                               AR_PHY_DESIRED_SZ_PGA,
                               pModal->pgaDesiredSize);
@@ -478,7 +510,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
                       pModal->txEndToRxOn);
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
                               pModal->thresh62);
                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
@@ -589,168 +621,6 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 #undef XPA_LVL_FREQ
 }
 
-static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
-                                struct ath9k_channel *chan,
-                                struct cal_data_per_freq *pRawDataSet,
-                                u8 *bChans, u16 availPiers,
-                                u16 tPdGainOverlap,
-                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
-                                u16 numXpdGains)
-{
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR5416_NUM_PD_GAINS];
-        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
-                                                             IS_CHAN_2GHZ(chan)),
-                                               bChans, numPiers, &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                        pRawDataSet[idxL].pwrPdg[i],
-                                        pRawDataSet[idxL].vpdPdg[i],
-                                        AR5416_PD_GAIN_ICEPTS,
-                                        vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] =
-                                min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
-                                    pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
-
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR5416_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR5416_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] =
-                                        (u8)(ath9k_hw_interpolate((u16)
-                                             FREQ2FBIN(centers.
-                                                       synth_center,
-                                                       IS_CHAN_2GHZ
-                                                       (chan)),
-                                             bChans[idxL], bChans[idxR],
-                                             vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
-
-                pPdGainBoundaries[i] =
-                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
-
-                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
-                        minDelta = pPdGainBoundaries[0] - 23;
-                        pPdGainBoundaries[0] = 23;
-                } else {
-                        minDelta = 0;
-                }
-
-                if (i == 0) {
-                        if (AR_SREV_9280_10_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
-                                (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                        tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-                }
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex >= maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
-                                                    (ss - maxIndex + 1) * vpdStep));
-                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
-                                                         255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR5416_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
-                i++;
-        }
-
-        while (k < AR5416_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k - 1];
-                k++;
-        }
-}
-
 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
                                 u16 *gb,
                                 u16 numXpdGain,
@@ -783,7 +653,7 @@ static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
                 /* Because of a hardware limitation, ensure the gain boundary
                  * is not larger than (63 - overlap)
                  */
-                gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
+                gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 
                 for (k = 0; k < numXpdGain; k++)
                         gb[k] = (u16)min(gb_limit, gb[k]);
@@ -917,7 +787,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
                                                      txPower/2, pdadcValues);
                         } else {
-                                ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
+                                ath9k_hw_get_gain_boundaries_pdadcs(ah,
                                                         chan, pRawDataset,
                                                         pCalBChans, numPiers,
                                                         pdGainOverlap_t2,
@@ -933,6 +803,8 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                                            pwr_table_offset,
                                                            &diff);
 
+                        ENABLE_REGWRITE_BUFFER(ah);
+
                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
                                 if (OLC_FOR_AR9280_20_LATER) {
                                         REG_WRITE(ah,
@@ -965,23 +837,23 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
                                 REG_WRITE(ah, regOffset, reg32);
 
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
-                                          i, regChainOffset, regOffset,
-                                          reg32);
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC: Chain %d | PDADC %3d "
-                                          "Value %3d | PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | PDADC %3d "
-                                          "Value %3d |\n",
-                                          i, 4 * j, pdadcValues[4 * j],
-                                          4 * j + 1, pdadcValues[4 * j + 1],
-                                          4 * j + 2, pdadcValues[4 * j + 2],
-                                          4 * j + 3,
-                                          pdadcValues[4 * j + 3]);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
+                                        i, regChainOffset, regOffset,
+                                        reg32);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC: Chain %d | PDADC %3d "
+                                        "Value %3d | PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | PDADC %3d "
+                                        "Value %3d |\n",
+                                        i, 4 * j, pdadcValues[4 * j],
+                                        4 * j + 1, pdadcValues[4 * j + 1],
+                                        4 * j + 2, pdadcValues[4 * j + 2],
+                                        4 * j + 3, pdadcValues[4 * j + 3]);
 
                                 regOffset += 4;
                         }
+                        REGWRITE_BUFFER_FLUSH(ah);
                 }
         }
 
@@ -1003,9 +875,9 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
 
         int i;
         int16_t twiceLargestAntenna;
@@ -1021,13 +893,16 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
                 0, {0, 0, 0, 0}
         };
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11a[] =
-                { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
-        u16 ctlModesFor11g[] =
-                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
-                  CTL_2GHT40
-                };
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        static const u16 ctlModesFor11a[] = {
+                CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
+        };
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         int tx_chainmask;
         u16 twiceMinEdgePower;
@@ -1062,15 +937,19 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
         case 1:
                 break;
         case 2:
-                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         case 3:
-                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
+                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
+                else
+                        scaledPower = 0;
                 break;
         }
 
-        scaledPower = max((u16)0, scaledPower);
-
         if (IS_CHAN_2GHZ(chan)) {
                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
                         SUB_NUM_CTL_MODES_AT_2G_40;
@@ -1143,7 +1022,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 
                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+                        twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                         if ((((cfgCtl & ~CTL_MODE_M) |
@@ -1258,7 +1137,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                                     u16 cfgCtl,
                                     u8 twiceAntennaReduction,
                                     u8 twiceMaxRegulatoryPower,
-                                    u8 powerLimit)
+                                    u8 powerLimit, bool test)
 {
 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
@@ -1285,13 +1164,45 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
-                        ratesArray[i] = AR5416_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
+        }
+
+        if (!test) {
+                i = rate6mb;
+
+                if (IS_CHAN_HT40(chan))
+                        i = rateHt40_0;
+                else if (IS_CHAN_HT20(chan))
+                        i = rateHt20_0;
+
+                regulatory->max_power_level = ratesArray[i];
         }
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        switch(ar5416_get_ntxchains(ah->txchainmask)) {
+        case 1:
+                break;
+        case 2:
+                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
+                break;
+        case 3:
+                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
+                break;
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
+                        "Invalid chainmask configuration\n");
+                break;
+        }
+
+        if (test)
+                return;
+
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++) {
                         int8_t pwr_table_offset;
 
@@ -1301,6 +1212,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                 }
         }
 
+        ENABLE_REGWRITE_BUFFER(ah);
+
         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
@@ -1388,61 +1301,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
 
-        i = rate6mb;
-
-        if (IS_CHAN_HT40(chan))
-                i = rateHt40_0;
-        else if (IS_CHAN_HT20(chan))
-                i = rateHt20_0;
-
-        if (AR_SREV_9280_10_OR_LATER(ah))
-                regulatory->max_power_level =
-                        ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
-        else
-                regulatory->max_power_level = ratesArray[i];
-
-        switch(ar5416_get_ntxchains(ah->txchainmask)) {
-        case 1:
-                break;
-        case 2:
-                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
-                break;
-        case 3:
-                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
-                break;
-        default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
-                          "Invalid chainmask configuration\n");
-                break;
-        }
-}
-
-static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
-                                          enum ieee80211_band freq_band)
-{
-        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
-        struct modal_eep_header *pModal =
-                &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
-        struct base_eep_header *pBase = &eep->baseEepHeader;
-        u8 num_ant_config;
-
-        num_ant_config = 1;
-
-        if (pBase->version >= 0x0E0D)
-                if (pModal->useAnt1)
-                        num_ant_config += 1;
-
-        return num_ant_config;
-}
-
-static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                               struct ath9k_channel *chan)
-{
-        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
-        struct modal_eep_header *pModal =
-                &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
-
-        return pModal->antCtrlCommon;
+        REGWRITE_BUFFER_FLUSH(ah);
 }
 
 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
@@ -1453,17 +1312,17 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_DEF_SPURCHAN;
@@ -1481,8 +1340,6 @@ const struct eeprom_ops eep_def_ops = {
         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_def_set_board_values,
         .set_addac              = ath9k_hw_def_set_addac,
         .set_txpower            = ath9k_hw_def_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 3a8ee999da5d..bc713fc28191 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,123 +20,37 @@
 /*       LED functions          */
 /********************************/
 
-static void ath_led_blink_work(struct work_struct *work)
-{
-        struct ath_softc *sc = container_of(work, struct ath_softc,
-                                            ath_led_blink_work.work);
-
-        if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
-                return;
-
-        if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
-            (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
-                ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
-        else
-                ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
-                                  (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
-
-        ieee80211_queue_delayed_work(sc->hw,
-                                     &sc->ath_led_blink_work,
-                                     (sc->sc_flags & SC_OP_LED_ON) ?
-                                        msecs_to_jiffies(sc->led_off_duration) :
-                                        msecs_to_jiffies(sc->led_on_duration));
-
-        sc->led_on_duration = sc->led_on_cnt ?
-                        max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
-                        ATH_LED_ON_DURATION_IDLE;
-        sc->led_off_duration = sc->led_off_cnt ?
-                        max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
-                        ATH_LED_OFF_DURATION_IDLE;
-        sc->led_on_cnt = sc->led_off_cnt = 0;
-        if (sc->sc_flags & SC_OP_LED_ON)
-                sc->sc_flags &= ~SC_OP_LED_ON;
-        else
-                sc->sc_flags |= SC_OP_LED_ON;
-}
-
+#ifdef CONFIG_MAC80211_LEDS
 static void ath_led_brightness(struct led_classdev *led_cdev,
                                enum led_brightness brightness)
 {
-        struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
-        struct ath_softc *sc = led->sc;
-
-        switch (brightness) {
-        case LED_OFF:
-                if (led->led_type == ATH_LED_ASSOC ||
-                    led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
-                                (led->led_type == ATH_LED_RADIO));
-                        sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
-                        if (led->led_type == ATH_LED_RADIO)
-                                sc->sc_flags &= ~SC_OP_LED_ON;
-                } else {
-                        sc->led_off_cnt++;
-                }
-                break;
-        case LED_FULL:
-                if (led->led_type == ATH_LED_ASSOC) {
-                        sc->sc_flags |= SC_OP_LED_ASSOCIATED;
-                        if (led_blink)
-                                ieee80211_queue_delayed_work(sc->hw,
-                                                     &sc->ath_led_blink_work, 0);
-                } else if (led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
-                        sc->sc_flags |= SC_OP_LED_ON;
-                } else {
-                        sc->led_on_cnt++;
-                }
-                break;
-        default:
-                break;
-        }
-}
-
-static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
-                            char *trigger)
-{
-        int ret;
-
-        led->sc = sc;
-        led->led_cdev.name = led->name;
-        led->led_cdev.default_trigger = trigger;
-        led->led_cdev.brightness_set = ath_led_brightness;
-
-        ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
-        if (ret)
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Failed to register led:%s", led->name);
-        else
-                led->registered = 1;
-        return ret;
-}
-
-static void ath_unregister_led(struct ath_led *led)
-{
-        if (led->registered) {
-                led_classdev_unregister(&led->led_cdev);
-                led->registered = 0;
-        }
+        struct ath_softc *sc = container_of(led_cdev, struct ath_softc, led_cdev);
+        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, (brightness == LED_OFF));
 }
 
 void ath_deinit_leds(struct ath_softc *sc)
 {
-        ath_unregister_led(&sc->assoc_led);
-        sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
-        ath_unregister_led(&sc->tx_led);
-        ath_unregister_led(&sc->rx_led);
-        ath_unregister_led(&sc->radio_led);
-        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
+        if (!sc->led_registered)
+                return;
+
+        ath_led_brightness(&sc->led_cdev, LED_OFF);
+        led_classdev_unregister(&sc->led_cdev);
 }
 
 void ath_init_leds(struct ath_softc *sc)
 {
-        char *trigger;
         int ret;
 
-        if (AR_SREV_9287(sc->sc_ah))
-                sc->sc_ah->led_pin = ATH_LED_PIN_9287;
-        else
-                sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
+        if (sc->sc_ah->led_pin < 0) {
+                if (AR_SREV_9287(sc->sc_ah))
+                        sc->sc_ah->led_pin = ATH_LED_PIN_9287;
+                else if (AR_SREV_9485(sc->sc_ah))
+                        sc->sc_ah->led_pin = ATH_LED_PIN_9485;
+                else if (AR_SREV_9300(sc->sc_ah))
+                        sc->sc_ah->led_pin = ATH_LED_PIN_9300;
+                else
+                        sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
+        }
 
         /* Configure gpio 1 for output */
         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
@@ -144,48 +58,22 @@ void ath_init_leds(struct ath_softc *sc)
         /* LED off, active low */
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
-        if (led_blink)
-                INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
-
-        trigger = ieee80211_get_radio_led_name(sc->hw);
-        snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
-                "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->radio_led, trigger);
-        sc->radio_led.led_type = ATH_LED_RADIO;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_assoc_led_name(sc->hw);
-        snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
-                "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->assoc_led, trigger);
-        sc->assoc_led.led_type = ATH_LED_ASSOC;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_tx_led_name(sc->hw);
-        snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
-                "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->tx_led, trigger);
-        sc->tx_led.led_type = ATH_LED_TX;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_rx_led_name(sc->hw);
-        snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
-                "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
-        ret = ath_register_led(sc, &sc->rx_led, trigger);
-        sc->rx_led.led_type = ATH_LED_RX;
-        if (ret)
-                goto fail;
-
-        return;
-
-fail:
-        if (led_blink)
-                cancel_delayed_work_sync(&sc->ath_led_blink_work);
-        ath_deinit_leds(sc);
+        if (!led_blink)
+                sc->led_cdev.default_trigger =
+                        ieee80211_get_radio_led_name(sc->hw);
+
+        snprintf(sc->led_name, sizeof(sc->led_name),
+                "ath9k-%s", wiphy_name(sc->hw->wiphy));
+        sc->led_cdev.name = sc->led_name;
+        sc->led_cdev.brightness_set = ath_led_brightness;
+
+        ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &sc->led_cdev);
+        if (ret < 0)
+                return;
+
+        sc->led_registered = true;
 }
+#endif
 
 /*******************/
 /*      Rfkill     */
@@ -201,8 +89,7 @@ static bool ath_is_rfkill_set(struct ath_softc *sc)
 
 void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         bool blocked = !!ath_is_rfkill_set(sc);
 
         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
@@ -236,13 +123,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
                 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
                 /* Detect if colocated bt started scanning */
                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
-                                  "BT scan detected");
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
+                                "BT scan detected\n");
                         sc->sc_flags |= (SC_OP_BT_SCAN |
                                          SC_OP_BT_PRIORITY_DETECTED);
                 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
-                                  "BT priority traffic detected");
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
+                                "BT priority traffic detected\n");
                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
                 }
 
@@ -251,45 +138,15 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
         }
 }
 
-/*
- * Configures appropriate weight based on stomp type.
- */
-static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
-                                  enum ath_stomp_type stomp_type)
-{
-        struct ath_hw *ah = sc->sc_ah;
-
-        switch (stomp_type) {
-        case ATH_BTCOEX_STOMP_ALL:
-                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
-                                           AR_STOMP_ALL_WLAN_WGHT);
-                break;
-        case ATH_BTCOEX_STOMP_LOW:
-                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
-                                           AR_STOMP_LOW_WLAN_WGHT);
-                break;
-        case ATH_BTCOEX_STOMP_NONE:
-                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
-                                           AR_STOMP_NONE_WLAN_WGHT);
-                break;
-        default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                          "Invalid Stomptype\n");
-                break;
-        }
-
-        ath9k_hw_btcoex_enable(ah);
-}
-
 static void ath9k_gen_timer_start(struct ath_hw *ah,
                                   struct ath_gen_timer *timer,
-                                  u32 timer_next,
+                                  u32 trig_timeout,
                                   u32 timer_period)
 {
-        ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
+        ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
 
         if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 ah->imask |= ATH9K_INT_GENTIMER;
                 ath9k_hw_set_interrupts(ah, ah->imask);
         }
@@ -303,7 +160,7 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
 
         /* if no timer is enabled, turn off interrupt mask */
         if (timer_table->timer_mask.val == 0) {
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 ah->imask &= ~ATH9K_INT_GENTIMER;
                 ath9k_hw_set_interrupts(ah, ah->imask);
         }
@@ -322,13 +179,14 @@ static void ath_btcoex_period_timer(unsigned long data)
         u32 timer_period;
         bool is_btscan;
 
+        ath9k_ps_wakeup(sc);
         ath_detect_bt_priority(sc);
 
         is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
 
         spin_lock_bh(&btcoex->btcoex_lock);
 
-        ath9k_btcoex_bt_stomp(sc, is_btscan ? ATH_BTCOEX_STOMP_ALL :
+        ath9k_hw_btcoex_bt_stomp(ah, is_btscan ? ATH_BTCOEX_STOMP_ALL :
                               btcoex->bt_stomp_type);
 
         spin_unlock_bh(&btcoex->btcoex_lock);
@@ -339,13 +197,12 @@ static void ath_btcoex_period_timer(unsigned long data)
 
                 timer_period = is_btscan ? btcoex->btscan_no_stomp :
                                            btcoex->btcoex_no_stomp;
-                ath9k_gen_timer_start(ah,
-                                      btcoex->no_stomp_timer,
-                                      (ath9k_hw_gettsf32(ah) +
-                                       timer_period), timer_period * 10);
+                ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
+                                      timer_period * 10);
                 btcoex->hw_timer_enabled = true;
         }
 
+        ath9k_ps_restore(sc);
         mod_timer(&btcoex->period_timer, jiffies +
                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
 }
@@ -359,19 +216,22 @@ static void ath_btcoex_no_stomp_timer(void *arg)
         struct ath_softc *sc = (struct ath_softc *)arg;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_btcoex *btcoex = &sc->btcoex;
+        struct ath_common *common = ath9k_hw_common(ah);
         bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                  "no stomp timer running\n");
+        ath_dbg(common, ATH_DBG_BTCOEX,
+                "no stomp timer running\n");
 
+        ath9k_ps_wakeup(sc);
         spin_lock_bh(&btcoex->btcoex_lock);
 
         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
-                ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
-                ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
 
         spin_unlock_bh(&btcoex->btcoex_lock);
+        ath9k_ps_restore(sc);
 }
 
 int ath_init_btcoex_timer(struct ath_softc *sc)
@@ -408,8 +268,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
         struct ath_btcoex *btcoex = &sc->btcoex;
         struct ath_hw *ah = sc->sc_ah;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                  "Starting btcoex timers");
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                "Starting btcoex timers\n");
 
         /* make sure duty cycle timer is also stopped when resuming */
         if (btcoex->hw_timer_enabled)
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 17e7a9a367e7..260f1f37a60e 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,26 +17,42 @@
 #include "htc.h"
 
 /* identify firmware images */
-#define FIRMWARE_AR7010         "ar7010.fw"
-#define FIRMWARE_AR7010_1_1     "ar7010_1_1.fw"
-#define FIRMWARE_AR9271         "ar9271.fw"
+#define FIRMWARE_AR7010_1_1     "htc_7010.fw"
+#define FIRMWARE_AR9271         "htc_9271.fw"
 
-MODULE_FIRMWARE(FIRMWARE_AR7010);
 MODULE_FIRMWARE(FIRMWARE_AR7010_1_1);
 MODULE_FIRMWARE(FIRMWARE_AR9271);
 
 static struct usb_device_id ath9k_hif_usb_ids[] = {
         { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */
         { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */
-        { USB_DEVICE(0x0cf3, 0x7010) }, /* Atheros */
-        { USB_DEVICE(0x0cf3, 0x7015) }, /* Atheros */
         { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */
-        { USB_DEVICE(0x0846, 0x9018) }, /* Netgear WNDA3200 */
         { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */
         { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */
         { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */
+        { USB_DEVICE(0x13D3, 0x3346) }, /* IMC Networks */
+        { USB_DEVICE(0x13D3, 0x3348) }, /* Azurewave */
+        { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */
+        { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */
         { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */
-        { USB_DEVICE(0x083A, 0xA704) }, /* SMC Networks */
+        { USB_DEVICE(0x040D, 0x3801) }, /* VIA */
+        { USB_DEVICE(0x0cf3, 0xb003) }, /* Ubiquiti WifiStation Ext */
+
+        { USB_DEVICE(0x0cf3, 0x7015),
+          .driver_info = AR9287_USB },  /* Atheros */
+        { USB_DEVICE(0x1668, 0x1200),
+          .driver_info = AR9287_USB },  /* Verizon */
+
+        { USB_DEVICE(0x0cf3, 0x7010),
+          .driver_info = AR9280_USB },  /* Atheros */
+        { USB_DEVICE(0x0846, 0x9018),
+          .driver_info = AR9280_USB },  /* Netgear WNDA3200 */
+        { USB_DEVICE(0x083A, 0xA704),
+          .driver_info = AR9280_USB },  /* SMC Networks */
+
+        { USB_DEVICE(0x0cf3, 0x20ff),
+          .driver_info = STORAGE_DEVICE },
+
         { },
 };
 
@@ -62,7 +78,7 @@ static void hif_usb_regout_cb(struct urb *urb)
 
         if (cmd) {
                 ath9k_htc_txcompletion_cb(cmd->hif_dev->htc_handle,
-                                          cmd->skb, 1);
+                                          cmd->skb, true);
                 kfree(cmd);
         }
 
@@ -92,10 +108,10 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
         cmd->skb = skb;
         cmd->hif_dev = hif_dev;
 
-        usb_fill_int_urb(urb, hif_dev->udev,
-                         usb_sndintpipe(hif_dev->udev, USB_REG_OUT_PIPE),
+        usb_fill_bulk_urb(urb, hif_dev->udev,
+                         usb_sndbulkpipe(hif_dev->udev, USB_REG_OUT_PIPE),
                          skb->data, skb->len,
-                         hif_usb_regout_cb, cmd, 1);
+                         hif_usb_regout_cb, cmd);
 
         usb_anchor_urb(urb, &hif_dev->regout_submitted);
         ret = usb_submit_urb(urb, GFP_KERNEL);
@@ -108,6 +124,90 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
         return ret;
 }
 
+static void hif_usb_mgmt_cb(struct urb *urb)
+{
+        struct cmd_buf *cmd = (struct cmd_buf *)urb->context;
+        struct hif_device_usb *hif_dev = cmd->hif_dev;
+        bool txok = true;
+
+        if (!cmd || !cmd->skb || !cmd->hif_dev)
+                return;
+
+        switch (urb->status) {
+        case 0:
+                break;
+        case -ENOENT:
+        case -ECONNRESET:
+        case -ENODEV:
+        case -ESHUTDOWN:
+                txok = false;
+
+                /*
+                 * If the URBs are being flushed, no need to complete
+                 * this packet.
+                 */
+                spin_lock(&hif_dev->tx.tx_lock);
+                if (hif_dev->tx.flags & HIF_USB_TX_FLUSH) {
+                        spin_unlock(&hif_dev->tx.tx_lock);
+                        dev_kfree_skb_any(cmd->skb);
+                        kfree(cmd);
+                        return;
+                }
+                spin_unlock(&hif_dev->tx.tx_lock);
+
+                break;
+        default:
+                txok = false;
+                break;
+        }
+
+        skb_pull(cmd->skb, 4);
+        ath9k_htc_txcompletion_cb(cmd->hif_dev->htc_handle,
+                                  cmd->skb, txok);
+        kfree(cmd);
+}
+
+static int hif_usb_send_mgmt(struct hif_device_usb *hif_dev,
+                             struct sk_buff *skb)
+{
+        struct urb *urb;
+        struct cmd_buf *cmd;
+        int ret = 0;
+        __le16 *hdr;
+
+        urb = usb_alloc_urb(0, GFP_ATOMIC);
+        if (urb == NULL)
+                return -ENOMEM;
+
+        cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
+        if (cmd == NULL) {
+                usb_free_urb(urb);
+                return -ENOMEM;
+        }
+
+        cmd->skb = skb;
+        cmd->hif_dev = hif_dev;
+
+        hdr = (__le16 *) skb_push(skb, 4);
+        *hdr++ = cpu_to_le16(skb->len - 4);
+        *hdr++ = cpu_to_le16(ATH_USB_TX_STREAM_MODE_TAG);
+
+        usb_fill_bulk_urb(urb, hif_dev->udev,
+                         usb_sndbulkpipe(hif_dev->udev, USB_WLAN_TX_PIPE),
+                         skb->data, skb->len,
+                         hif_usb_mgmt_cb, cmd);
+
+        usb_anchor_urb(urb, &hif_dev->mgmt_submitted);
+        ret = usb_submit_urb(urb, GFP_ATOMIC);
+        if (ret) {
+                usb_unanchor_urb(urb);
+                kfree(cmd);
+        }
+        usb_free_urb(urb);
+
+        return ret;
+}
+
 static inline void ath9k_skb_queue_purge(struct hif_device_usb *hif_dev,
                                          struct sk_buff_head *list)
 {
@@ -115,7 +215,22 @@ static inline void ath9k_skb_queue_purge(struct hif_device_usb *hif_dev,
 
         while ((skb = __skb_dequeue(list)) != NULL) {
                 dev_kfree_skb_any(skb);
-                TX_STAT_INC(skb_dropped);
+        }
+}
+
+static inline void ath9k_skb_queue_complete(struct hif_device_usb *hif_dev,
+                                            struct sk_buff_head *queue,
+                                            bool txok)
+{
+        struct sk_buff *skb;
+
+        while ((skb = __skb_dequeue(queue)) != NULL) {
+                ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
+                                          skb, txok);
+                if (txok)
+                        TX_STAT_INC(skb_success);
+                else
+                        TX_STAT_INC(skb_failed);
         }
 }
 
@@ -123,7 +238,7 @@ static void hif_usb_tx_cb(struct urb *urb)
 {
         struct tx_buf *tx_buf = (struct tx_buf *) urb->context;
         struct hif_device_usb *hif_dev;
-        struct sk_buff *skb;
+        bool txok = true;
 
         if (!tx_buf || !tx_buf->hif_dev)
                 return;
@@ -137,33 +252,28 @@ static void hif_usb_tx_cb(struct urb *urb)
         case -ECONNRESET:
         case -ENODEV:
         case -ESHUTDOWN:
+                txok = false;
+
                 /*
-                 * The URB has been killed, free the SKBs
-                 * and return.
+                 * If the URBs are being flushed, no need to add this
+                 * URB to the free list.
                  */
-                ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
-                return;
+                spin_lock(&hif_dev->tx.tx_lock);
+                if (hif_dev->tx.flags & HIF_USB_TX_FLUSH) {
+                        spin_unlock(&hif_dev->tx.tx_lock);
+                        ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
+                        return;
+                }
+                spin_unlock(&hif_dev->tx.tx_lock);
+
+                break;
         default:
+                txok = false;
                 break;
         }
 
-        /* Check if TX has been stopped */
-        spin_lock(&hif_dev->tx.tx_lock);
-        if (hif_dev->tx.flags & HIF_USB_TX_STOP) {
-                spin_unlock(&hif_dev->tx.tx_lock);
-                ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
-                goto add_free;
-        }
-        spin_unlock(&hif_dev->tx.tx_lock);
-
-        /* Complete the queued SKBs. */
-        while ((skb = __skb_dequeue(&tx_buf->skb_queue)) != NULL) {
-                ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
-                                          skb, 1);
-                TX_STAT_INC(skb_completed);
-        }
+        ath9k_skb_queue_complete(hif_dev, &tx_buf->skb_queue, txok);
 
-add_free:
         /* Re-initialize the SKB queue */
         tx_buf->len = tx_buf->offset = 0;
         __skb_queue_head_init(&tx_buf->skb_queue);
@@ -184,8 +294,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
         struct tx_buf *tx_buf = NULL;
         struct sk_buff *nskb = NULL;
         int ret = 0, i;
-        u16 *hdr, tx_skb_cnt = 0;
+        u16 tx_skb_cnt = 0;
         u8 *buf;
+        __le16 *hdr;
 
         if (hif_dev->tx.tx_skb_cnt == 0)
                 return 0;
@@ -210,9 +321,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
 
                 buf = tx_buf->buf;
                 buf += tx_buf->offset;
-                hdr = (u16 *)buf;
-                *hdr++ = nskb->len;
-                *hdr++ = ATH_USB_TX_STREAM_MODE_TAG;
+                hdr = (__le16 *)buf;
+                *hdr++ = cpu_to_le16(nskb->len);
+                *hdr++ = cpu_to_le16(ATH_USB_TX_STREAM_MODE_TAG);
                 buf += 4;
                 memcpy(buf, nskb->data, nskb->len);
                 tx_buf->len = nskb->len + 4;
@@ -235,7 +346,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
         ret = usb_submit_urb(tx_buf->urb, GFP_ATOMIC);
         if (ret) {
                 tx_buf->len = tx_buf->offset = 0;
-                ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
+                ath9k_skb_queue_complete(hif_dev, &tx_buf->skb_queue, false);
                 __skb_queue_head_init(&tx_buf->skb_queue);
                 list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf);
                 hif_dev->tx.tx_buf_cnt++;
@@ -247,10 +358,11 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
         return ret;
 }
 
-static int hif_usb_send_tx(struct hif_device_usb *hif_dev, struct sk_buff *skb,
-                           struct ath9k_htc_tx_ctl *tx_ctl)
+static int hif_usb_send_tx(struct hif_device_usb *hif_dev, struct sk_buff *skb)
 {
+        struct ath9k_htc_tx_ctl *tx_ctl;
         unsigned long flags;
+        int ret = 0;
 
         spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
 
@@ -265,26 +377,36 @@ static int hif_usb_send_tx(struct hif_device_usb *hif_dev, struct sk_buff *skb,
                 return -ENOMEM;
         }
 
-        __skb_queue_tail(&hif_dev->tx.tx_skb_queue, skb);
-        hif_dev->tx.tx_skb_cnt++;
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
+        tx_ctl = HTC_SKB_CB(skb);
 
-        /* Send normal frames immediately */
-        if (!tx_ctl || (tx_ctl && (tx_ctl->type == ATH9K_HTC_NORMAL)))
-                __hif_usb_tx(hif_dev);
+        /* Mgmt/Beacon frames don't use the TX buffer pool */
+        if ((tx_ctl->type == ATH9K_HTC_MGMT) ||
+            (tx_ctl->type == ATH9K_HTC_BEACON)) {
+                ret = hif_usb_send_mgmt(hif_dev, skb);
+        }
+
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+
+        if ((tx_ctl->type == ATH9K_HTC_NORMAL) ||
+            (tx_ctl->type == ATH9K_HTC_AMPDU)) {
+                __skb_queue_tail(&hif_dev->tx.tx_skb_queue, skb);
+                hif_dev->tx.tx_skb_cnt++;
+        }
 
         /* Check if AMPDUs have to be sent immediately */
-        if (tx_ctl && (tx_ctl->type == ATH9K_HTC_AMPDU) &&
-            (hif_dev->tx.tx_buf_cnt == MAX_TX_URB_NUM) &&
+        if ((hif_dev->tx.tx_buf_cnt == MAX_TX_URB_NUM) &&
             (hif_dev->tx.tx_skb_cnt < 2)) {
                 __hif_usb_tx(hif_dev);
         }
 
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
 
-        return 0;
+        return ret;
 }
 
-static void hif_usb_start(void *hif_handle, u8 pipe_id)
+static void hif_usb_start(void *hif_handle)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
         unsigned long flags;
@@ -296,27 +418,35 @@ static void hif_usb_start(void *hif_handle, u8 pipe_id)
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
 }
 
-static void hif_usb_stop(void *hif_handle, u8 pipe_id)
+static void hif_usb_stop(void *hif_handle)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
+        struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
         unsigned long flags;
 
         spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
-        ath9k_skb_queue_purge(hif_dev, &hif_dev->tx.tx_skb_queue);
+        ath9k_skb_queue_complete(hif_dev, &hif_dev->tx.tx_skb_queue, false);
         hif_dev->tx.tx_skb_cnt = 0;
         hif_dev->tx.flags |= HIF_USB_TX_STOP;
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
+        /* The pending URBs have to be canceled. */
+        list_for_each_entry_safe(tx_buf, tx_buf_tmp,
+                                 &hif_dev->tx.tx_pending, list) {
+                usb_kill_urb(tx_buf->urb);
+        }
+
+        usb_kill_anchored_urbs(&hif_dev->mgmt_submitted);
 }
 
-static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb,
-                        struct ath9k_htc_tx_ctl *tx_ctl)
+static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
         int ret = 0;
 
         switch (pipe_id) {
         case USB_WLAN_TX_PIPE:
-                ret = hif_usb_send_tx(hif_dev, skb, tx_ctl);
+                ret = hif_usb_send_tx(hif_dev, skb);
                 break;
         case USB_REG_OUT_PIPE:
                 ret = hif_usb_send_regout(hif_dev, skb);
@@ -331,6 +461,40 @@ static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb,
         return ret;
 }
 
+static inline bool check_index(struct sk_buff *skb, u8 idx)
+{
+        struct ath9k_htc_tx_ctl *tx_ctl;
+
+        tx_ctl = HTC_SKB_CB(skb);
+
+        if ((tx_ctl->type == ATH9K_HTC_AMPDU) &&
+            (tx_ctl->sta_idx == idx))
+                return true;
+
+        return false;
+}
+
+static void hif_usb_sta_drain(void *hif_handle, u8 idx)
+{
+        struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
+        struct sk_buff *skb, *tmp;
+        unsigned long flags;
+
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+
+        skb_queue_walk_safe(&hif_dev->tx.tx_skb_queue, skb, tmp) {
+                if (check_index(skb, idx)) {
+                        __skb_unlink(skb, &hif_dev->tx.tx_skb_queue);
+                        ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
+                                                  skb, false);
+                        hif_dev->tx.tx_skb_cnt--;
+                        TX_STAT_INC(skb_failed);
+                }
+        }
+
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+}
+
 static struct ath9k_htc_hif hif_usb = {
         .transport = ATH9K_HIF_USB,
         .name = "ath9k_hif_usb",
@@ -340,6 +504,7 @@ static struct ath9k_htc_hif hif_usb = {
 
         .start = hif_usb_start,
         .stop = hif_usb_stop,
+        .sta_drain = hif_usb_sta_drain,
         .send = hif_usb_send,
 };
 
@@ -347,9 +512,9 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
                                     struct sk_buff *skb)
 {
         struct sk_buff *nskb, *skb_pool[MAX_PKT_NUM_IN_TRANSFER];
-        int index = 0, i = 0, chk_idx, len = skb->len;
-        int rx_remain_len = 0, rx_pkt_len = 0;
-        u16 pkt_len, pkt_tag, pool_index = 0;
+        int index = 0, i = 0, len = skb->len;
+        int rx_remain_len, rx_pkt_len;
+        u16 pool_index = 0;
         u8 *ptr;
 
         spin_lock(&hif_dev->rx_lock);
@@ -383,64 +548,64 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
         spin_unlock(&hif_dev->rx_lock);
 
         while (index < len) {
+                u16 pkt_len;
+                u16 pkt_tag;
+                u16 pad_len;
+                int chk_idx;
+
                 ptr = (u8 *) skb->data;
 
                 pkt_len = ptr[index] + (ptr[index+1] << 8);
                 pkt_tag = ptr[index+2] + (ptr[index+3] << 8);
 
-                if (pkt_tag == ATH_USB_RX_STREAM_MODE_TAG) {
-                        u16 pad_len;
-
-                        pad_len = 4 - (pkt_len & 0x3);
-                        if (pad_len == 4)
-                                pad_len = 0;
-
-                        chk_idx = index;
-                        index = index + 4 + pkt_len + pad_len;
-
-                        if (index > MAX_RX_BUF_SIZE) {
-                                spin_lock(&hif_dev->rx_lock);
-                                hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE;
-                                hif_dev->rx_transfer_len =
-                                        MAX_RX_BUF_SIZE - chk_idx - 4;
-                                hif_dev->rx_pad_len = pad_len;
-
-                                nskb = __dev_alloc_skb(pkt_len + 32,
-                                                       GFP_ATOMIC);
-                                if (!nskb) {
-                                        dev_err(&hif_dev->udev->dev,
-                                        "ath9k_htc: RX memory allocation"
-                                        " error\n");
-                                        spin_unlock(&hif_dev->rx_lock);
-                                        goto err;
-                                }
-                                skb_reserve(nskb, 32);
-                                RX_STAT_INC(skb_allocated);
-
-                                memcpy(nskb->data, &(skb->data[chk_idx+4]),
-                                       hif_dev->rx_transfer_len);
-
-                                /* Record the buffer pointer */
-                                hif_dev->remain_skb = nskb;
+                if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) {
+                        RX_STAT_INC(skb_dropped);
+                        return;
+                }
+
+                pad_len = 4 - (pkt_len & 0x3);
+                if (pad_len == 4)
+                        pad_len = 0;
+
+                chk_idx = index;
+                index = index + 4 + pkt_len + pad_len;
+
+                if (index > MAX_RX_BUF_SIZE) {
+                        spin_lock(&hif_dev->rx_lock);
+                        hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE;
+                        hif_dev->rx_transfer_len =
+                                MAX_RX_BUF_SIZE - chk_idx - 4;
+                        hif_dev->rx_pad_len = pad_len;
+
+                        nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
+                        if (!nskb) {
+                                dev_err(&hif_dev->udev->dev,
+                                        "ath9k_htc: RX memory allocation error\n");
                                 spin_unlock(&hif_dev->rx_lock);
-                        } else {
-                                nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
-                                if (!nskb) {
-                                        dev_err(&hif_dev->udev->dev,
-                                        "ath9k_htc: RX memory allocation"
-                                        " error\n");
-                                        goto err;
-                                }
-                                skb_reserve(nskb, 32);
-                                RX_STAT_INC(skb_allocated);
-
-                                memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len);
-                                skb_put(nskb, pkt_len);
-                                skb_pool[pool_index++] = nskb;
+                                goto err;
                         }
+                        skb_reserve(nskb, 32);
+                        RX_STAT_INC(skb_allocated);
+
+                        memcpy(nskb->data, &(skb->data[chk_idx+4]),
+                               hif_dev->rx_transfer_len);
+
+                        /* Record the buffer pointer */
+                        hif_dev->remain_skb = nskb;
+                        spin_unlock(&hif_dev->rx_lock);
                 } else {
-                        RX_STAT_INC(skb_dropped);
-                        return;
+                        nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
+                        if (!nskb) {
+                                dev_err(&hif_dev->udev->dev,
+                                        "ath9k_htc: RX memory allocation error\n");
+                                goto err;
+                        }
+                        skb_reserve(nskb, 32);
+                        RX_STAT_INC(skb_allocated);
+
+                        memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len);
+                        skb_put(nskb, pkt_len);
+                        skb_pool[pool_index++] = nskb;
                 }
         }
 
@@ -455,7 +620,7 @@ err:
 static void ath9k_hif_usb_rx_cb(struct urb *urb)
 {
         struct sk_buff *skb = (struct sk_buff *) urb->context;
-        struct hif_device_usb *hif_dev = (struct hif_device_usb *)
+        struct hif_device_usb *hif_dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int ret;
 
@@ -502,7 +667,7 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
 {
         struct sk_buff *skb = (struct sk_buff *) urb->context;
         struct sk_buff *nskb;
-        struct hif_device_usb *hif_dev = (struct hif_device_usb *)
+        struct hif_device_usb *hif_dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int ret;
 
@@ -521,6 +686,9 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
         case -ESHUTDOWN:
                 goto free;
         default:
+                skb_reset_tail_pointer(skb);
+                skb_trim(skb, 0);
+
                 goto resubmit;
         }
 
@@ -540,27 +708,20 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
                         return;
                 }
 
-                usb_fill_int_urb(urb, hif_dev->udev,
-                                 usb_rcvintpipe(hif_dev->udev, USB_REG_IN_PIPE),
+                usb_fill_bulk_urb(urb, hif_dev->udev,
+                                 usb_rcvbulkpipe(hif_dev->udev,
+                                                 USB_REG_IN_PIPE),
                                  nskb->data, MAX_REG_IN_BUF_SIZE,
-                                 ath9k_hif_usb_reg_in_cb, nskb, 1);
-
-                ret = usb_submit_urb(urb, GFP_ATOMIC);
-                if (ret) {
-                        kfree_skb(nskb);
-                        urb->context = NULL;
-                }
-
-                return;
+                                 ath9k_hif_usb_reg_in_cb, nskb);
         }
 
 resubmit:
-        skb_reset_tail_pointer(skb);
-        skb_trim(skb, 0);
-
+        usb_anchor_urb(urb, &hif_dev->reg_in_submitted);
         ret = usb_submit_urb(urb, GFP_ATOMIC);
-        if (ret)
+        if (ret) {
+                usb_unanchor_urb(urb);
                 goto free;
+        }
 
         return;
 free:
@@ -571,6 +732,7 @@ free:
 static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
 {
         struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
+        unsigned long flags;
 
         list_for_each_entry_safe(tx_buf, tx_buf_tmp,
                                  &hif_dev->tx.tx_buf, list) {
@@ -581,6 +743,10 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
                 kfree(tx_buf);
         }
 
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+        hif_dev->tx.flags |= HIF_USB_TX_FLUSH;
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
         list_for_each_entry_safe(tx_buf, tx_buf_tmp,
                                  &hif_dev->tx.tx_pending, list) {
                 usb_kill_urb(tx_buf->urb);
@@ -589,6 +755,8 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
                 kfree(tx_buf->buf);
                 kfree(tx_buf);
         }
+
+        usb_kill_anchored_urbs(&hif_dev->mgmt_submitted);
 }
 
 static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev)
@@ -600,6 +768,7 @@ static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev)
         INIT_LIST_HEAD(&hif_dev->tx.tx_pending);
         spin_lock_init(&hif_dev->tx.tx_lock);
         __skb_queue_head_init(&hif_dev->tx.tx_skb_queue);
+        init_usb_anchor(&hif_dev->mgmt_submitted);
 
         for (i = 0; i < MAX_TX_URB_NUM; i++) {
                 tx_buf = kzalloc(sizeof(struct tx_buf), GFP_KERNEL);
@@ -696,42 +865,67 @@ err_urb:
         return ret;
 }
 
-static void ath9k_hif_usb_dealloc_reg_in_urb(struct hif_device_usb *hif_dev)
+static void ath9k_hif_usb_dealloc_reg_in_urbs(struct hif_device_usb *hif_dev)
 {
-        if (hif_dev->reg_in_urb) {
-                usb_kill_urb(hif_dev->reg_in_urb);
-                if (hif_dev->reg_in_urb->context)
-                        kfree_skb((void *)hif_dev->reg_in_urb->context);
-                usb_free_urb(hif_dev->reg_in_urb);
-                hif_dev->reg_in_urb = NULL;
-        }
+        usb_kill_anchored_urbs(&hif_dev->reg_in_submitted);
 }
 
-static int ath9k_hif_usb_alloc_reg_in_urb(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_alloc_reg_in_urbs(struct hif_device_usb *hif_dev)
 {
-        struct sk_buff *skb;
+        struct urb *urb = NULL;
+        struct sk_buff *skb = NULL;
+        int i, ret;
 
-        hif_dev->reg_in_urb = usb_alloc_urb(0, GFP_KERNEL);
-        if (hif_dev->reg_in_urb == NULL)
-                return -ENOMEM;
+        init_usb_anchor(&hif_dev->reg_in_submitted);
 
-        skb = alloc_skb(MAX_REG_IN_BUF_SIZE, GFP_KERNEL);
-        if (!skb)
-                goto err;
+        for (i = 0; i < MAX_REG_IN_URB_NUM; i++) {
+
+                /* Allocate URB */
+                urb = usb_alloc_urb(0, GFP_KERNEL);
+                if (urb == NULL) {
+                        ret = -ENOMEM;
+                        goto err_urb;
+                }
 
-        usb_fill_int_urb(hif_dev->reg_in_urb, hif_dev->udev,
-                         usb_rcvintpipe(hif_dev->udev, USB_REG_IN_PIPE),
-                         skb->data, MAX_REG_IN_BUF_SIZE,
-                         ath9k_hif_usb_reg_in_cb, skb, 1);
+                /* Allocate buffer */
+                skb = alloc_skb(MAX_REG_IN_BUF_SIZE, GFP_KERNEL);
+                if (!skb) {
+                        ret = -ENOMEM;
+                        goto err_skb;
+                }
 
-        if (usb_submit_urb(hif_dev->reg_in_urb, GFP_KERNEL) != 0)
-                goto err;
+                usb_fill_bulk_urb(urb, hif_dev->udev,
+                                  usb_rcvbulkpipe(hif_dev->udev,
+                                                  USB_REG_IN_PIPE),
+                                  skb->data, MAX_REG_IN_BUF_SIZE,
+                                  ath9k_hif_usb_reg_in_cb, skb);
+
+                /* Anchor URB */
+                usb_anchor_urb(urb, &hif_dev->reg_in_submitted);
+
+                /* Submit URB */
+                ret = usb_submit_urb(urb, GFP_KERNEL);
+                if (ret) {
+                        usb_unanchor_urb(urb);
+                        goto err_submit;
+                }
+
+                /*
+                 * Drop reference count.
+                 * This ensures that the URB is freed when killing them.
+                 */
+                usb_free_urb(urb);
+        }
 
         return 0;
 
-err:
-        ath9k_hif_usb_dealloc_reg_in_urb(hif_dev);
-        return -ENOMEM;
+err_submit:
+        kfree_skb(skb);
+err_skb:
+        usb_free_urb(urb);
+err_urb:
+        ath9k_hif_usb_dealloc_reg_in_urbs(hif_dev);
+        return ret;
 }
 
 static int ath9k_hif_usb_alloc_urbs(struct hif_device_usb *hif_dev)
@@ -748,7 +942,7 @@ static int ath9k_hif_usb_alloc_urbs(struct hif_device_usb *hif_dev)
                 goto err_rx;
 
         /* Register Read */
-        if (ath9k_hif_usb_alloc_reg_in_urb(hif_dev) < 0)
+        if (ath9k_hif_usb_alloc_reg_in_urbs(hif_dev) < 0)
                 goto err_reg;
 
         return 0;
@@ -763,12 +957,13 @@ err:
 static void ath9k_hif_usb_dealloc_urbs(struct hif_device_usb *hif_dev)
 {
         usb_kill_anchored_urbs(&hif_dev->regout_submitted);
-        ath9k_hif_usb_dealloc_reg_in_urb(hif_dev);
+        ath9k_hif_usb_dealloc_reg_in_urbs(hif_dev);
         ath9k_hif_usb_dealloc_tx_urbs(hif_dev);
         ath9k_hif_usb_dealloc_rx_urbs(hif_dev);
 }
 
-static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
+                                     u32 drv_info)
 {
         int transfer, err;
         const void *data = hif_dev->firmware->data;
@@ -799,7 +994,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
         }
         kfree(buf);
 
-        if ((hif_dev->device_id == 0x7010) || (hif_dev->device_id == 0x7015))
+        if (IS_AR7010_DEVICE(drv_info))
                 firm_offset = AR7010_FIRMWARE_TEXT;
         else
                 firm_offset = AR9271_FIRMWARE_TEXT;
@@ -820,9 +1015,11 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
         return 0;
 }
 
-static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
 {
-        int ret;
+        int ret, idx;
+        struct usb_host_interface *alt = &hif_dev->interface->altsetting[0];
+        struct usb_endpoint_descriptor *endp;
 
         /* Request firmware */
         ret = request_firmware(&hif_dev->firmware, hif_dev->fw_name,
@@ -833,28 +1030,40 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
                 goto err_fw_req;
         }
 
-        /* Alloc URBs */
-        ret = ath9k_hif_usb_alloc_urbs(hif_dev);
+        /* Download firmware */
+        ret = ath9k_hif_usb_download_fw(hif_dev, drv_info);
         if (ret) {
                 dev_err(&hif_dev->udev->dev,
-                        "ath9k_htc: Unable to allocate URBs\n");
-                goto err_urb;
+                        "ath9k_htc: Firmware - %s download failed\n",
+                        hif_dev->fw_name);
+                goto err_fw_download;
         }
 
-        /* Download firmware */
-        ret = ath9k_hif_usb_download_fw(hif_dev);
+        /* On downloading the firmware to the target, the USB descriptor of EP4
+         * is 'patched' to change the type of the endpoint to Bulk. This will
+         * bring down CPU usage during the scan period.
+         */
+        for (idx = 0; idx < alt->desc.bNumEndpoints; idx++) {
+                endp = &alt->endpoint[idx].desc;
+                if ((endp->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
+                                == USB_ENDPOINT_XFER_INT) {
+                        endp->bmAttributes &= ~USB_ENDPOINT_XFERTYPE_MASK;
+                        endp->bmAttributes |= USB_ENDPOINT_XFER_BULK;
+                        endp->bInterval = 0;
+                }
+        }
+
+        /* Alloc URBs */
+        ret = ath9k_hif_usb_alloc_urbs(hif_dev);
         if (ret) {
                 dev_err(&hif_dev->udev->dev,
-                        "ath9k_htc: Firmware - %s download failed\n",
-                        hif_dev->fw_name);
+                        "ath9k_htc: Unable to allocate URBs\n");
                 goto err_fw_download;
         }
 
         return 0;
 
 err_fw_download:
-        ath9k_hif_usb_dealloc_urbs(hif_dev);
-err_urb:
         release_firmware(hif_dev->firmware);
 err_fw_req:
         hif_dev->firmware = NULL;
@@ -868,6 +1077,61 @@ static void ath9k_hif_usb_dev_deinit(struct hif_device_usb *hif_dev)
                 release_firmware(hif_dev->firmware);
 }
 
+/*
+ * An exact copy of the function from zd1211rw.
+ */
+static int send_eject_command(struct usb_interface *interface)
+{
+        struct usb_device *udev = interface_to_usbdev(interface);
+        struct usb_host_interface *iface_desc = &interface->altsetting[0];
+        struct usb_endpoint_descriptor *endpoint;
+        unsigned char *cmd;
+        u8 bulk_out_ep;
+        int r;
+
+        /* Find bulk out endpoint */
+        for (r = 1; r >= 0; r--) {
+                endpoint = &iface_desc->endpoint[r].desc;
+                if (usb_endpoint_dir_out(endpoint) &&
+                    usb_endpoint_xfer_bulk(endpoint)) {
+                        bulk_out_ep = endpoint->bEndpointAddress;
+                        break;
+                }
+        }
+        if (r == -1) {
+                dev_err(&udev->dev,
+                        "ath9k_htc: Could not find bulk out endpoint\n");
+                return -ENODEV;
+        }
+
+        cmd = kzalloc(31, GFP_KERNEL);
+        if (cmd == NULL)
+                return -ENODEV;
+
+        /* USB bulk command block */
+        cmd[0] = 0x55;  /* bulk command signature */
+        cmd[1] = 0x53;  /* bulk command signature */
+        cmd[2] = 0x42;  /* bulk command signature */
+        cmd[3] = 0x43;  /* bulk command signature */
+        cmd[14] = 6;    /* command length */
+
+        cmd[15] = 0x1b; /* SCSI command: START STOP UNIT */
+        cmd[19] = 0x2;  /* eject disc */
+
+        dev_info(&udev->dev, "Ejecting storage device...\n");
+        r = usb_bulk_msg(udev, usb_sndbulkpipe(udev, bulk_out_ep),
+                cmd, 31, NULL, 2000);
+        kfree(cmd);
+        if (r)
+                return r;
+
+        /* At this point, the device disconnects and reconnects with the real
+         * ID numbers. */
+
+        usb_set_intfdata(interface, NULL);
+        return 0;
+}
+
 static int ath9k_hif_usb_probe(struct usb_interface *interface,
                                const struct usb_device_id *id)
 {
@@ -875,6 +1139,9 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
         struct hif_device_usb *hif_dev;
         int ret = 0;
 
+        if (id->driver_info == STORAGE_DEVICE)
+                return send_eject_command(interface);
+
         hif_dev = kzalloc(sizeof(struct hif_device_usb), GFP_KERNEL);
         if (!hif_dev) {
                 ret = -ENOMEM;
@@ -899,28 +1166,20 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
 
         /* Find out which firmware to load */
 
-        switch(hif_dev->device_id) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
-                if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202)
-                        hif_dev->fw_name = FIRMWARE_AR7010_1_1;
-                else
-                        hif_dev->fw_name = FIRMWARE_AR7010;
-                break;
-        default:
+        if (IS_AR7010_DEVICE(id->driver_info))
+                hif_dev->fw_name = FIRMWARE_AR7010_1_1;
+        else
                 hif_dev->fw_name = FIRMWARE_AR9271;
-                break;
-        }
 
-        ret = ath9k_hif_usb_dev_init(hif_dev);
+        ret = ath9k_hif_usb_dev_init(hif_dev, id->driver_info);
         if (ret) {
                 ret = -EINVAL;
                 goto err_hif_init_usb;
         }
 
         ret = ath9k_htc_hw_init(hif_dev->htc_handle,
-                                &hif_dev->udev->dev, hif_dev->device_id);
+                                &interface->dev, hif_dev->device_id,
+                                hif_dev->udev->product, id->driver_info);
         if (ret) {
                 ret = -EINVAL;
                 goto err_htc_hw_init;
@@ -963,18 +1222,18 @@ static void ath9k_hif_usb_reboot(struct usb_device *udev)
 static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
 {
         struct usb_device *udev = interface_to_usbdev(interface);
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
-
-        if (hif_dev) {
-                ath9k_htc_hw_deinit(hif_dev->htc_handle,
-                    (udev->state == USB_STATE_NOTATTACHED) ? true : false);
-                ath9k_htc_hw_free(hif_dev->htc_handle);
-                ath9k_hif_usb_dev_deinit(hif_dev);
-                usb_set_intfdata(interface, NULL);
-        }
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+        bool unplugged = (udev->state == USB_STATE_NOTATTACHED) ? true : false;
+
+        if (!hif_dev)
+                return;
+
+        ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged);
+        ath9k_htc_hw_free(hif_dev->htc_handle);
+        ath9k_hif_usb_dev_deinit(hif_dev);
+        usb_set_intfdata(interface, NULL);
 
-        if (hif_dev->flags & HIF_USB_START)
+        if (!unplugged && (hif_dev->flags & HIF_USB_START))
                 ath9k_hif_usb_reboot(udev);
 
         kfree(hif_dev);
@@ -986,8 +1245,14 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
 static int ath9k_hif_usb_suspend(struct usb_interface *interface,
                                  pm_message_t message)
 {
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+
+        /*
+         * The device has to be set to FULLSLEEP mode in case no
+         * interface is up.
+         */
+        if (!(hif_dev->flags & HIF_USB_START))
+                ath9k_htc_suspend(hif_dev->htc_handle);
 
         ath9k_hif_usb_dealloc_urbs(hif_dev);
 
@@ -996,8 +1261,8 @@ static int ath9k_hif_usb_suspend(struct usb_interface *interface,
 
 static int ath9k_hif_usb_resume(struct usb_interface *interface)
 {
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+        struct htc_target *htc_handle = hif_dev->htc_handle;
         int ret;
 
         ret = ath9k_hif_usb_alloc_urbs(hif_dev);
@@ -1005,7 +1270,8 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
                 return ret;
 
         if (hif_dev->firmware) {
-                ret = ath9k_hif_usb_download_fw(hif_dev);
+                ret = ath9k_hif_usb_download_fw(hif_dev,
+                                htc_handle->drv_priv->ah->hw_version.usbdev);
                 if (ret)
                         goto fail_resume;
         } else {
@@ -1015,7 +1281,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
 
         mdelay(100);
 
-        ret = ath9k_htc_resume(hif_dev->htc_handle);
+        ret = ath9k_htc_resume(htc_handle);
 
         if (ret)
                 goto fail_resume;
@@ -1030,7 +1296,7 @@ fail_resume:
 #endif
 
 static struct usb_driver ath9k_hif_usb_driver = {
-        .name = "ath9k_hif_usb",
+        .name = KBUILD_MODNAME,
         .probe = ath9k_hif_usb_probe,
         .disconnect = ath9k_hif_usb_disconnect,
 #ifdef CONFIG_PM
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
index 2daf97b11c08..794f63094e5d 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.h
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,6 +17,11 @@
 #ifndef HTC_USB_H
 #define HTC_USB_H
 
+#define MAJOR_VERSION_REQ 1
+#define MINOR_VERSION_REQ 3
+
+#define IS_AR7010_DEVICE(_v) (((_v) == AR9280_USB) || ((_v) == AR9287_USB))
+
 #define AR9271_FIRMWARE       0x501000
 #define AR9271_FIRMWARE_TEXT  0x903000
 #define AR7010_FIRMWARE_TEXT  0x906000
@@ -29,7 +34,7 @@
 
 /* FIXME: Verify these numbers (with Windows) */
 #define MAX_TX_URB_NUM  8
-#define MAX_TX_BUF_NUM  1024
+#define MAX_TX_BUF_NUM  256
 #define MAX_TX_BUF_SIZE 32768
 #define MAX_TX_AGGR_NUM 20
 
@@ -38,7 +43,7 @@
 #define MAX_PKT_NUM_IN_TRANSFER 10
 
 #define MAX_REG_OUT_URB_NUM  1
-#define MAX_REG_OUT_BUF_NUM  8
+#define MAX_REG_IN_URB_NUM   64
 
 #define MAX_REG_IN_BUF_SIZE 64
 
@@ -62,6 +67,7 @@ struct tx_buf {
 };
 
 #define HIF_USB_TX_STOP  BIT(0)
+#define HIF_USB_TX_FLUSH BIT(1)
 
 struct hif_usb_tx {
         u8 flags;
@@ -87,9 +93,10 @@ struct hif_device_usb {
         const struct firmware *firmware;
         struct htc_target *htc_handle;
         struct hif_usb_tx tx;
-        struct urb *reg_in_urb;
         struct usb_anchor regout_submitted;
         struct usb_anchor rx_submitted;
+        struct usb_anchor reg_in_submitted;
+        struct usb_anchor mgmt_submitted;
         struct sk_buff *remain_skb;
         const char *fw_name;
         int rx_remain_len;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 43b9e21bc562..5bc022087e65 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -32,6 +32,7 @@
 #include "wmi.h"
 
 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
+#define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 #define ATH_ANI_POLLINTERVAL      100     /* 100 ms */
 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
@@ -45,15 +46,8 @@ extern struct ieee80211_ops ath9k_htc_ops;
 extern int htc_modparam_nohwcrypt;
 
 enum htc_phymode {
-        HTC_MODE_AUTO           = 0,
-        HTC_MODE_11A            = 1,
-        HTC_MODE_11B            = 2,
-        HTC_MODE_11G            = 3,
-        HTC_MODE_FH             = 4,
-        HTC_MODE_TURBO_A        = 5,
-        HTC_MODE_TURBO_G        = 6,
-        HTC_MODE_11NA           = 7,
-        HTC_MODE_11NG           = 8
+        HTC_MODE_11NA           = 0,
+        HTC_MODE_11NG           = 1
 };
 
 enum htc_opmode {
@@ -65,23 +59,24 @@ enum htc_opmode {
         HTC_M_WDS       = 2
 };
 
-#define ATH9K_HTC_HDRSPACE sizeof(struct htc_frame_hdr)
-#define ATH9K_HTC_AMPDU 1
+#define ATH9K_HTC_AMPDU  1
 #define ATH9K_HTC_NORMAL 2
+#define ATH9K_HTC_BEACON 3
+#define ATH9K_HTC_MGMT   4
 
 #define ATH9K_HTC_TX_CTSONLY      0x1
 #define ATH9K_HTC_TX_RTSCTS       0x2
-#define ATH9K_HTC_TX_USE_MIN_RATE 0x100
 
 struct tx_frame_hdr {
         u8 data_type;
         u8 node_idx;
         u8 vif_idx;
         u8 tidno;
-        u32 flags; /* ATH9K_HTC_TX_* */
+        __be32 flags; /* ATH9K_HTC_TX_* */
         u8 key_type;
         u8 keyix;
-        u8 reserved[26];
+        u8 cookie;
+        u8 pad;
 } __packed;
 
 struct tx_mgmt_hdr {
@@ -91,78 +86,46 @@ struct tx_mgmt_hdr {
         u8 flags;
         u8 key_type;
         u8 keyix;
-        u16 reserved;
+        u8 cookie;
+        u8 pad;
 } __packed;
 
 struct tx_beacon_header {
-        u8 len_changed;
         u8 vif_index;
+        u8 len_changed;
         u16 rev;
 } __packed;
 
-struct ath9k_htc_target_hw {
-        u32 flags;
-        u32 flags_ext;
-        u32 ampdu_limit;
-        u8 ampdu_subframes;
-        u8 tx_chainmask;
-        u8 tx_chainmask_legacy;
-        u8 rtscts_ratecode;
-        u8 protmode;
-} __packed;
+#define MAX_TX_AMPDU_SUBFRAMES_9271 17
+#define MAX_TX_AMPDU_SUBFRAMES_7010 22
 
 struct ath9k_htc_cap_target {
-        u32 flags;
-        u32 flags_ext;
-        u32 ampdu_limit;
+        __be32 ampdu_limit;
         u8 ampdu_subframes;
+        u8 enable_coex;
         u8 tx_chainmask;
-        u8 tx_chainmask_legacy;
-        u8 rtscts_ratecode;
-        u8 protmode;
+        u8 pad;
 } __packed;
 
 struct ath9k_htc_target_vif {
         u8 index;
-        u8 des_bssid[ETH_ALEN];
-        __be32 opmode;
+        u8 opmode;
         u8 myaddr[ETH_ALEN];
-        u8 bssid[ETH_ALEN];
-        u32 flags;
-        u32 flags_ext;
-        u16 ps_sta;
-        __be16 rtsthreshold;
         u8 ath_cap;
-        u8 node;
-        s8 mcast_rate;
+        __be16 rtsthreshold;
+        u8 pad;
 } __packed;
 
-#define ATH_HTC_STA_AUTH  0x0001
-#define ATH_HTC_STA_QOS   0x0002
-#define ATH_HTC_STA_ERP   0x0004
-#define ATH_HTC_STA_HT    0x0008
-
-/* FIXME: UAPSD variables */
 struct ath9k_htc_target_sta {
-        u16 associd;
-        u16 txpower;
-        u32 ucastkey;
         u8 macaddr[ETH_ALEN];
         u8 bssid[ETH_ALEN];
         u8 sta_index;
         u8 vif_index;
-        u8 vif_sta;
-        __be16 flags; /* ATH_HTC_STA_* */
-        u16 htcap;
-        u8 valid;
-        u16 capinfo;
-        struct ath9k_htc_target_hw *hw;
-        struct ath9k_htc_target_vif *vif;
-        u16 txseqmgmt;
         u8 is_vif_sta;
-        u16 maxampdu;
-        u16 iv16;
-        u32 iv32;
+        __be16 flags;
+        __be16 htcap;
+        __be16 maxampdu;
+        u8 pad;
 } __packed;
 
 struct ath9k_htc_target_aggr {
@@ -196,16 +159,86 @@ struct ath9k_htc_target_rate {
         struct ath9k_htc_rate rates;
 };
 
-struct ath9k_htc_target_stats {
-        __be32 tx_shortretry;
-        __be32 tx_longretry;
-        __be32 tx_xretries;
-        __be32 ht_txunaggr_xretry;
-        __be32 ht_tx_xretries;
+struct ath9k_htc_target_rate_mask {
+        u8 vif_index;
+        u8 band;
+        __be32 mask;
+        u16 pad;
 } __packed;
 
+struct ath9k_htc_target_int_stats {
+        __be32 rx;
+        __be32 rxorn;
+        __be32 rxeol;
+        __be32 txurn;
+        __be32 txto;
+        __be32 cst;
+} __packed;
+
+struct ath9k_htc_target_tx_stats {
+        __be32 xretries;
+        __be32 fifoerr;
+        __be32 filtered;
+        __be32 timer_exp;
+        __be32 shortretries;
+        __be32 longretries;
+        __be32 qnull;
+        __be32 encap_fail;
+        __be32 nobuf;
+} __packed;
+
+struct ath9k_htc_target_rx_stats {
+        __be32 nobuf;
+        __be32 host_send;
+        __be32 host_done;
+} __packed;
+
+#define ATH9K_HTC_MAX_VIF 2
+#define ATH9K_HTC_MAX_BCN_VIF 2
+
+#define INC_VIF(_priv, _type) do {              \
+                switch (_type) {                \
+                case NL80211_IFTYPE_STATION:    \
+                        _priv->num_sta_vif++;   \
+                        break;                  \
+                case NL80211_IFTYPE_ADHOC:      \
+                        _priv->num_ibss_vif++;  \
+                        break;                  \
+                case NL80211_IFTYPE_AP:         \
+                        _priv->num_ap_vif++;    \
+                        break;                  \
+                default:                        \
+                        break;                  \
+                }                               \
+        } while (0)
+
+#define DEC_VIF(_priv, _type) do {              \
+                switch (_type) {                \
+                case NL80211_IFTYPE_STATION:    \
+                        _priv->num_sta_vif--;   \
+                        break;                  \
+                case NL80211_IFTYPE_ADHOC:      \
+                        _priv->num_ibss_vif--;  \
+                        break;                  \
+                case NL80211_IFTYPE_AP:         \
+                        _priv->num_ap_vif--;    \
+                        break;                  \
+                default:                        \
+                        break;                  \
+                }                               \
+        } while (0)
+
 struct ath9k_htc_vif {
         u8 index;
+        u16 seq_no;
+        bool beacon_configured;
+        int bslot;
+        __le64 tsfadjust;
+};
+
+struct ath9k_vif_iter_data {
+        const u8 *hw_macaddr;
+        u8 mask[ETH_ALEN];
 };
 
 #define ATH9K_HTC_MAX_STA 8
@@ -239,23 +272,65 @@ struct ath9k_htc_rx {
         spinlock_t rxbuflock;
 };
 
+#define ATH9K_HTC_TX_CLEANUP_INTERVAL 50 /* ms */
+#define ATH9K_HTC_TX_TIMEOUT_INTERVAL 3000 /* ms */
+#define ATH9K_HTC_TX_RESERVE 10
+#define ATH9K_HTC_TX_TIMEOUT_COUNT 40
+#define ATH9K_HTC_TX_THRESHOLD (MAX_TX_BUF_NUM - ATH9K_HTC_TX_RESERVE)
+
+#define ATH9K_HTC_OP_TX_QUEUES_STOP BIT(0)
+#define ATH9K_HTC_OP_TX_DRAIN       BIT(1)
+
+struct ath9k_htc_tx {
+        u8 flags;
+        int queued_cnt;
+        struct sk_buff_head mgmt_ep_queue;
+        struct sk_buff_head cab_ep_queue;
+        struct sk_buff_head data_be_queue;
+        struct sk_buff_head data_bk_queue;
+        struct sk_buff_head data_vi_queue;
+        struct sk_buff_head data_vo_queue;
+        struct sk_buff_head tx_failed;
+        DECLARE_BITMAP(tx_slot, MAX_TX_BUF_NUM);
+        struct timer_list cleanup_timer;
+        spinlock_t tx_lock;
+};
+
 struct ath9k_htc_tx_ctl {
         u8 type; /* ATH9K_HTC_* */
+        u8 epid;
+        u8 txok;
+        u8 sta_idx;
+        unsigned long timestamp;
 };
 
+static inline struct ath9k_htc_tx_ctl *HTC_SKB_CB(struct sk_buff *skb)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+
+        BUILD_BUG_ON(sizeof(struct ath9k_htc_tx_ctl) >
+                     IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
+        return (struct ath9k_htc_tx_ctl *) &tx_info->driver_data;
+}
+
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
 
 #define TX_STAT_INC(c) (hif_dev->htc_handle->drv_priv->debug.tx_stats.c++)
 #define RX_STAT_INC(c) (hif_dev->htc_handle->drv_priv->debug.rx_stats.c++)
+#define CAB_STAT_INC   priv->debug.tx_stats.cab_queued++
 
 #define TX_QSTAT_INC(q) (priv->debug.tx_stats.queue_stats[q]++)
 
+void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv,
+                           struct ath_htc_rx_status *rxs);
+
 struct ath_tx_stats {
         u32 buf_queued;
         u32 buf_completed;
         u32 skb_queued;
-        u32 skb_completed;
-        u32 skb_dropped;
+        u32 skb_success;
+        u32 skb_failed;
+        u32 cab_queued;
         u32 queue_stats[WME_NUM_AC];
 };
 
@@ -263,70 +338,79 @@ struct ath_rx_stats {
         u32 skb_allocated;
         u32 skb_completed;
         u32 skb_dropped;
+        u32 err_crc;
+        u32 err_decrypt_crc;
+        u32 err_mic;
+        u32 err_pre_delim;
+        u32 err_post_delim;
+        u32 err_decrypt_busy;
+        u32 err_phy;
+        u32 err_phy_stats[ATH9K_PHYERR_MAX];
 };
 
 struct ath9k_debug {
         struct dentry *debugfs_phy;
-        struct dentry *debugfs_tgt_stats;
-        struct dentry *debugfs_xmit;
-        struct dentry *debugfs_recv;
         struct ath_tx_stats tx_stats;
         struct ath_rx_stats rx_stats;
-        u32 txrate;
 };
 
 #else
 
 #define TX_STAT_INC(c) do { } while (0)
 #define RX_STAT_INC(c) do { } while (0)
+#define CAB_STAT_INC   do { } while (0)
 
 #define TX_QSTAT_INC(c) do { } while (0)
 
+static inline void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv,
+                                         struct ath_htc_rx_status *rxs)
+{
+}
+
 #endif /* CONFIG_ATH9K_HTC_DEBUGFS */
 
 #define ATH_LED_PIN_DEF             1
-#define ATH_LED_PIN_9287            8
+#define ATH_LED_PIN_9287            10
 #define ATH_LED_PIN_9271            15
 #define ATH_LED_PIN_7010            12
-#define ATH_LED_ON_DURATION_IDLE    350 /* in msecs */
-#define ATH_LED_OFF_DURATION_IDLE   250 /* in msecs */
-
-enum ath_led_type {
-        ATH_LED_RADIO,
-        ATH_LED_ASSOC,
-        ATH_LED_TX,
-        ATH_LED_RX
-};
 
-struct ath_led {
-        struct ath9k_htc_priv *priv;
-        struct led_classdev led_cdev;
-        enum ath_led_type led_type;
-        struct delayed_work brightness_work;
-        char name[32];
-        bool registered;
-        int brightness;
-};
+#define BSTUCK_THRESHOLD 10
+
+/*
+ * Adjust these when the max. no of beaconing interfaces is
+ * increased.
+ */
+#define DEFAULT_SWBA_RESPONSE 40 /* in TUs */
+#define MIN_SWBA_RESPONSE     10 /* in TUs */
 
 struct htc_beacon_config {
+        struct ieee80211_vif *bslot[ATH9K_HTC_MAX_BCN_VIF];
         u16 beacon_interval;
-        u16 listen_interval;
         u16 dtim_period;
         u16 bmiss_timeout;
-        u8 dtim_count;
+        u32 bmiss_cnt;
+};
+
+struct ath_btcoex {
+        u32 bt_priority_cnt;
+        unsigned long bt_priority_time;
+        int bt_stomp_type; /* Types of BT stomping */
+        u32 btcoex_no_stomp;
+        u32 btcoex_period;
+        u32 btscan_no_stomp;
 };
 
-#define OP_INVALID        BIT(0)
-#define OP_SCANNING       BIT(1)
-#define OP_FULL_RESET     BIT(2)
-#define OP_LED_ASSOCIATED BIT(3)
-#define OP_LED_ON         BIT(4)
-#define OP_PREAMBLE_SHORT BIT(5)
-#define OP_PROTECT_ENABLE BIT(6)
-#define OP_ASSOCIATED     BIT(7)
-#define OP_ENABLE_BEACON  BIT(8)
-#define OP_LED_DEINIT     BIT(9)
-#define OP_UNPLUGGED      BIT(10)
+void ath_htc_init_btcoex_work(struct ath9k_htc_priv *priv);
+void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv);
+void ath_htc_cancel_btcoex_work(struct ath9k_htc_priv *priv);
+
+#define OP_INVALID                 BIT(0)
+#define OP_SCANNING                BIT(1)
+#define OP_ENABLE_BEACON           BIT(2)
+#define OP_BT_PRIORITY_DETECTED    BIT(3)
+#define OP_BT_SCAN                 BIT(4)
+#define OP_ANI_RUNNING             BIT(5)
+#define OP_TSF_RESET               BIT(6)
 
 struct ath9k_htc_priv {
         struct device *dev;
@@ -335,6 +419,9 @@ struct ath9k_htc_priv {
         struct htc_target *htc;
         struct wmi *wmi;
 
+        u16 fw_version_major;
+        u16 fw_version_minor;
+
         enum htc_endpoint_id wmi_cmd_ep;
         enum htc_endpoint_id beacon_ep;
         enum htc_endpoint_id cab_ep;
@@ -345,52 +432,60 @@ struct ath9k_htc_priv {
         enum htc_endpoint_id data_vi_ep;
         enum htc_endpoint_id data_vo_ep;
 
+        u8 vif_slot;
+        u8 mon_vif_idx;
+        u8 sta_slot;
+        u8 vif_sta_pos[ATH9K_HTC_MAX_VIF];
+        u8 num_ibss_vif;
+        u8 num_sta_vif;
+        u8 num_sta_assoc_vif;
+        u8 num_ap_vif;
+
         u16 op_flags;
         u16 curtxpow;
         u16 txpowlimit;
         u16 nvifs;
         u16 nstations;
-        u16 seq_no;
-        u32 bmiss_cnt;
+        bool rearm_ani;
+        bool reconfig_beacon;
+        unsigned int rxfilter;
 
-        struct ath9k_hw_cal_data caldata[38];
+        struct ath9k_hw_cal_data caldata;
+        struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 
         spinlock_t beacon_lock;
+        struct htc_beacon_config cur_beacon_conf;
 
-        bool tx_queues_stop;
-        spinlock_t tx_lock;
+        struct ath9k_htc_rx rx;
+        struct ath9k_htc_tx tx;
 
-        struct ieee80211_vif *vif;
-        struct htc_beacon_config cur_beacon_conf;
-        unsigned int rxfilter;
-        struct tasklet_struct wmi_tasklet;
+        struct tasklet_struct swba_tasklet;
         struct tasklet_struct rx_tasklet;
-        struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
-        struct ath9k_htc_rx rx;
-        struct tasklet_struct tx_tasklet;
-        struct sk_buff_head tx_queue;
-        struct delayed_work ath9k_ani_work;
+        struct delayed_work ani_work;
+        struct tasklet_struct tx_failed_tasklet;
         struct work_struct ps_work;
+        struct work_struct fatal_work;
 
         struct mutex htc_pm_lock;
         unsigned long ps_usecount;
         bool ps_enabled;
         bool ps_idle;
 
-        struct ath_led radio_led;
-        struct ath_led assoc_led;
-        struct ath_led tx_led;
-        struct ath_led rx_led;
-        struct delayed_work ath9k_led_blink_work;
-        int led_on_duration;
-        int led_off_duration;
-        int led_on_cnt;
-        int led_off_cnt;
+#ifdef CONFIG_MAC80211_LEDS
+        enum led_brightness brightness;
+        bool led_registered;
+        char led_name[32];
+        struct led_classdev led_cdev;
+        struct work_struct led_work;
+#endif
 
         int beaconq;
         int cabq;
         int hwq_map[WME_NUM_AC];
 
+        struct ath_btcoex btcoex;
+        struct delayed_work coex_period_work;
+        struct delayed_work duty_cycle_work;
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
         struct ath9k_debug debug;
 #endif
@@ -402,10 +497,20 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
         common->bus_ops->read_cachesize(common, csz);
 }
 
+void ath9k_htc_reset(struct ath9k_htc_priv *priv);
+
+void ath9k_htc_assign_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif);
+void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif);
+void ath9k_htc_set_tsfadjust(struct ath9k_htc_priv *priv,
+                             struct ieee80211_vif *vif);
 void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv);
 void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
                              struct ieee80211_vif *vif);
-void ath9k_htc_swba(struct ath9k_htc_priv *priv, u8 beacon_pending);
+void ath9k_htc_beacon_reconfig(struct ath9k_htc_priv *priv);
+void ath9k_htc_swba(struct ath9k_htc_priv *priv,
+                    struct wmi_event_swba *swba);
 
 void ath9k_htc_rxep(void *priv, struct sk_buff *skb,
                     enum htc_endpoint_id ep_id);
@@ -414,19 +519,32 @@ void ath9k_htc_txep(void *priv, struct sk_buff *skb, enum htc_endpoint_id ep_id,
 void ath9k_htc_beaconep(void *drv_priv, struct sk_buff *skb,
                         enum htc_endpoint_id ep_id, bool txok);
 
+int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv,
+                                u8 enable_coex);
 void ath9k_htc_station_work(struct work_struct *work);
 void ath9k_htc_aggr_work(struct work_struct *work);
-void ath9k_ani_work(struct work_struct *work);;
+void ath9k_htc_ani_work(struct work_struct *work);
+void ath9k_htc_start_ani(struct ath9k_htc_priv *priv);
+void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv);
 
 int ath9k_tx_init(struct ath9k_htc_priv *priv);
-void ath9k_tx_tasklet(unsigned long data);
-int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, struct sk_buff *skb);
+int ath9k_htc_tx_start(struct ath9k_htc_priv *priv,
+                       struct sk_buff *skb, u8 slot, bool is_cab);
 void ath9k_tx_cleanup(struct ath9k_htc_priv *priv);
 bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype);
 int ath9k_htc_cabq_setup(struct ath9k_htc_priv *priv);
 int get_hw_qnum(u16 queue, int *hwq_map);
 int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
                        struct ath9k_tx_queue_info *qinfo);
+void ath9k_htc_check_stop_queues(struct ath9k_htc_priv *priv);
+void ath9k_htc_check_wake_queues(struct ath9k_htc_priv *priv);
+int ath9k_htc_tx_get_slot(struct ath9k_htc_priv *priv);
+void ath9k_htc_tx_clear_slot(struct ath9k_htc_priv *priv, int slot);
+void ath9k_htc_tx_drain(struct ath9k_htc_priv *priv);
+void ath9k_htc_txstatus(struct ath9k_htc_priv *priv, void *wmi_event);
+void ath9k_htc_tx_failed(struct ath9k_htc_priv *priv);
+void ath9k_tx_failed_tasklet(unsigned long data);
+void ath9k_htc_tx_cleanup_timer(unsigned long data);
 
 int ath9k_rx_init(struct ath9k_htc_priv *priv);
 void ath9k_rx_cleanup(struct ath9k_htc_priv *priv);
@@ -437,27 +555,43 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv);
 void ath9k_htc_ps_wakeup(struct ath9k_htc_priv *priv);
 void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv);
 void ath9k_ps_work(struct work_struct *work);
+bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
+                        enum ath9k_power_mode mode);
 
 void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv);
+void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw);
+void ath9k_htc_radio_enable(struct ieee80211_hw *hw);
+void ath9k_htc_radio_disable(struct ieee80211_hw *hw);
+
+#ifdef CONFIG_MAC80211_LEDS
 void ath9k_init_leds(struct ath9k_htc_priv *priv);
 void ath9k_deinit_leds(struct ath9k_htc_priv *priv);
+void ath9k_led_work(struct work_struct *work);
+#else
+static inline void ath9k_init_leds(struct ath9k_htc_priv *priv)
+{
+}
+
+static inline void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
+{
+}
+
+static inline void ath9k_led_work(struct work_struct *work)
+{
+}
+#endif
 
 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
-                           u16 devid);
+                           u16 devid, char *product, u32 drv_info);
 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug);
 #ifdef CONFIG_PM
+void ath9k_htc_suspend(struct htc_target *htc_handle);
 int ath9k_htc_resume(struct htc_target *htc_handle);
 #endif
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
-int ath9k_htc_debug_create_root(void);
-void ath9k_htc_debug_remove_root(void);
 int ath9k_htc_init_debug(struct ath_hw *ah);
-void ath9k_htc_exit_debug(struct ath_hw *ah);
 #else
-static inline int ath9k_htc_debug_create_root(void) { return 0; };
-static inline void ath9k_htc_debug_remove_root(void) {};
 static inline int ath9k_htc_init_debug(struct ath_hw *ah) { return 0; };
-static inline void ath9k_htc_exit_debug(struct ath_hw *ah) {};
 #endif /* CONFIG_ATH9K_HTC_DEBUGFS */
 
 #endif /* HTC_H */
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index bd1506e69105..aa6a73118706 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,50 @@
 
 #define FUDGE 2
 
+void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
+{
+        struct ath_hw *ah = priv->ah;
+        struct ath9k_tx_queue_info qi, qi_be;
+
+        memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
+        memset(&qi_be, 0, sizeof(struct ath9k_tx_queue_info));
+
+        ath9k_hw_get_txq_props(ah, priv->beaconq, &qi);
+
+        if (priv->ah->opmode == NL80211_IFTYPE_AP) {
+                qi.tqi_aifs = 1;
+                qi.tqi_cwmin = 0;
+                qi.tqi_cwmax = 0;
+        } else if (priv->ah->opmode == NL80211_IFTYPE_ADHOC) {
+                int qnum = priv->hwq_map[WME_AC_BE];
+
+                ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+
+                qi.tqi_aifs = qi_be.tqi_aifs;
+
+                /*
+                 * For WIFI Beacon Distribution
+                 * Long slot time  : 2x cwmin
+                 * Short slot time : 4x cwmin
+                 */
+                if (ah->slottime == ATH9K_SLOT_TIME_20)
+                        qi.tqi_cwmin = 2*qi_be.tqi_cwmin;
+                else
+                        qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
+
+                qi.tqi_cwmax = qi_be.tqi_cwmax;
+
+        }
+
+        if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) {
+                ath_err(ath9k_hw_common(ah),
+                        "Unable to update beacon queue %u!\n", priv->beaconq);
+        } else {
+                ath9k_hw_resettxqueue(ah, priv->beaconq);
+        }
+}
+
+
 static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
                                         struct htc_beacon_config *bss_conf)
 {
@@ -30,7 +74,7 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         __be32 htc_imask = 0;
         u64 tsf;
         int num_beacons, offset, dtim_dec_count, cfp_dec_count;
-        int ret;
+        int ret __attribute__ ((unused));
         u8 cmd_rsp;
 
         memset(&bs, 0, sizeof(bs));
@@ -123,11 +167,12 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         /* TSF out of range threshold fixed at 1 second */
         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
 
-        ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
-        ath_print(common, ATH_DBG_BEACON,
-                  "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
-                  bs.bs_bmissthreshold, bs.bs_sleepduration,
-                  bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
+        ath_dbg(common, ATH_DBG_CONFIG, "intval: %u tsf: %llu tsftu: %u\n",
+                intval, tsf, tsftu);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+                bs.bs_bmissthreshold, bs.bs_sleepduration,
+                bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
 
         /* Set the computed STA beacon timers */
 
@@ -138,29 +183,105 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
 }
 
+static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
+                                       struct htc_beacon_config *bss_conf)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        enum ath9k_int imask = 0;
+        u32 nexttbtt, intval, tsftu;
+        __be32 htc_imask = 0;
+        int ret __attribute__ ((unused));
+        u8 cmd_rsp;
+        u64 tsf;
+
+        intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD;
+        intval /= ATH9K_HTC_MAX_BCN_VIF;
+        nexttbtt = intval;
+
+        /*
+         * To reduce beacon misses under heavy TX load,
+         * set the beacon response time to a larger value.
+         */
+        if (intval > DEFAULT_SWBA_RESPONSE)
+                priv->ah->config.sw_beacon_response_time = DEFAULT_SWBA_RESPONSE;
+        else
+                priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
+
+        if (priv->op_flags & OP_TSF_RESET) {
+                ath9k_hw_reset_tsf(priv->ah);
+                priv->op_flags &= ~OP_TSF_RESET;
+        } else {
+                /*
+                 * Pull nexttbtt forward to reflect the current TSF.
+                 */
+                tsf = ath9k_hw_gettsf64(priv->ah);
+                tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
+                do {
+                        nexttbtt += intval;
+                } while (nexttbtt < tsftu);
+        }
+
+        if (priv->op_flags & OP_ENABLE_BEACON)
+                imask |= ATH9K_INT_SWBA;
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "AP Beacon config, intval: %d, nexttbtt: %u, resp_time: %d "
+                "imask: 0x%x\n",
+                bss_conf->beacon_interval, nexttbtt,
+                priv->ah->config.sw_beacon_response_time, imask);
+
+        ath9k_htc_beaconq_config(priv);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+        ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
+        priv->cur_beacon_conf.bmiss_cnt = 0;
+        htc_imask = cpu_to_be32(imask);
+        WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
+}
+
 static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
                                           struct htc_beacon_config *bss_conf)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         enum ath9k_int imask = 0;
-        u32 nexttbtt, intval;
+        u32 nexttbtt, intval, tsftu;
         __be32 htc_imask = 0;
-        int ret;
+        int ret __attribute__ ((unused));
         u8 cmd_rsp;
+        u64 tsf;
 
         intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD;
         nexttbtt = intval;
-        intval |= ATH9K_BEACON_ENA;
+
+        /*
+         * Pull nexttbtt forward to reflect the current TSF.
+         */
+        tsf = ath9k_hw_gettsf64(priv->ah);
+        tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
+        do {
+                nexttbtt += intval;
+        } while (nexttbtt < tsftu);
+
+        /*
+         * Only one IBSS interfce is allowed.
+         */
+        if (intval > DEFAULT_SWBA_RESPONSE)
+                priv->ah->config.sw_beacon_response_time = DEFAULT_SWBA_RESPONSE;
+        else
+                priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
+
         if (priv->op_flags & OP_ENABLE_BEACON)
                 imask |= ATH9K_INT_SWBA;
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "IBSS Beacon config, intval: %d, imask: 0x%x\n",
-                  bss_conf->beacon_interval, imask);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "IBSS Beacon config, intval: %d, nexttbtt: %u, "
+                "resp_time: %d, imask: 0x%x\n",
+                bss_conf->beacon_interval, nexttbtt,
+                priv->ah->config.sw_beacon_response_time, imask);
 
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
-        ath9k_hw_beaconinit(priv->ah, nexttbtt, intval);
-        priv->bmiss_cnt = 0;
+        ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
+        priv->cur_beacon_conf.bmiss_cnt = 0;
         htc_imask = cpu_to_be32(imask);
         WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
 }
@@ -171,79 +292,318 @@ void ath9k_htc_beaconep(void *drv_priv, struct sk_buff *skb,
         dev_kfree_skb_any(skb);
 }
 
-void ath9k_htc_swba(struct ath9k_htc_priv *priv, u8 beacon_pending)
+static void ath9k_htc_send_buffered(struct ath9k_htc_priv *priv,
+                                    int slot)
 {
-        struct ath9k_htc_vif *avp = (void *)priv->vif->drv_priv;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ieee80211_vif *vif;
+        struct sk_buff *skb;
+        struct ieee80211_hdr *hdr;
+        int padpos, padsize, ret, tx_slot;
+
+        spin_lock_bh(&priv->beacon_lock);
+
+        vif = priv->cur_beacon_conf.bslot[slot];
+
+        skb = ieee80211_get_buffered_bc(priv->hw, vif);
+
+        while(skb) {
+                hdr = (struct ieee80211_hdr *) skb->data;
+
+                padpos = ath9k_cmn_padpos(hdr->frame_control);
+                padsize = padpos & 3;
+                if (padsize && skb->len > padpos) {
+                        if (skb_headroom(skb) < padsize) {
+                                dev_kfree_skb_any(skb);
+                                goto next;
+                        }
+                        skb_push(skb, padsize);
+                        memmove(skb->data, skb->data + padsize, padpos);
+                }
+
+                tx_slot = ath9k_htc_tx_get_slot(priv);
+                if (tx_slot < 0) {
+                        ath_dbg(common, ATH_DBG_XMIT, "No free CAB slot\n");
+                        dev_kfree_skb_any(skb);
+                        goto next;
+                }
+
+                ret = ath9k_htc_tx_start(priv, skb, tx_slot, true);
+                if (ret != 0) {
+                        ath9k_htc_tx_clear_slot(priv, tx_slot);
+                        dev_kfree_skb_any(skb);
+
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Failed to send CAB frame\n");
+                } else {
+                        spin_lock_bh(&priv->tx.tx_lock);
+                        priv->tx.queued_cnt++;
+                        spin_unlock_bh(&priv->tx.tx_lock);
+                }
+        next:
+                skb = ieee80211_get_buffered_bc(priv->hw, vif);
+        }
+
+        spin_unlock_bh(&priv->beacon_lock);
+}
+
+static void ath9k_htc_send_beacon(struct ath9k_htc_priv *priv,
+                                  int slot)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ieee80211_vif *vif;
+        struct ath9k_htc_vif *avp;
         struct tx_beacon_header beacon_hdr;
-        struct ath9k_htc_tx_ctl tx_ctl;
+        struct ath9k_htc_tx_ctl *tx_ctl;
         struct ieee80211_tx_info *info;
+        struct ieee80211_mgmt *mgmt;
         struct sk_buff *beacon;
         u8 *tx_fhdr;
+        int ret;
 
         memset(&beacon_hdr, 0, sizeof(struct tx_beacon_header));
-        memset(&tx_ctl, 0, sizeof(struct ath9k_htc_tx_ctl));
-
-        /* FIXME: Handle BMISS */
-        if (beacon_pending != 0) {
-                priv->bmiss_cnt++;
-                return;
-        }
 
         spin_lock_bh(&priv->beacon_lock);
 
+        vif = priv->cur_beacon_conf.bslot[slot];
+        avp = (struct ath9k_htc_vif *)vif->drv_priv;
+
         if (unlikely(priv->op_flags & OP_SCANNING)) {
                 spin_unlock_bh(&priv->beacon_lock);
                 return;
         }
 
         /* Get a new beacon */
-        beacon = ieee80211_beacon_get(priv->hw, priv->vif);
+        beacon = ieee80211_beacon_get(priv->hw, vif);
         if (!beacon) {
                 spin_unlock_bh(&priv->beacon_lock);
                 return;
         }
 
+        /*
+         * Update the TSF adjust value here, the HW will
+         * add this value for every beacon.
+         */
+        mgmt = (struct ieee80211_mgmt *)beacon->data;
+        mgmt->u.beacon.timestamp = avp->tsfadjust;
+
         info = IEEE80211_SKB_CB(beacon);
         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
                 struct ieee80211_hdr *hdr =
                         (struct ieee80211_hdr *) beacon->data;
-                priv->seq_no += 0x10;
+                avp->seq_no += 0x10;
                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
-                hdr->seq_ctrl |= cpu_to_le16(priv->seq_no);
+                hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
         }
 
-        tx_ctl.type = ATH9K_HTC_NORMAL;
+        tx_ctl = HTC_SKB_CB(beacon);
+        memset(tx_ctl, 0, sizeof(*tx_ctl));
+
+        tx_ctl->type = ATH9K_HTC_BEACON;
+        tx_ctl->epid = priv->beacon_ep;
+
         beacon_hdr.vif_index = avp->index;
         tx_fhdr = skb_push(beacon, sizeof(beacon_hdr));
         memcpy(tx_fhdr, (u8 *) &beacon_hdr, sizeof(beacon_hdr));
 
-        htc_send(priv->htc, beacon, priv->beacon_ep, &tx_ctl);
+        ret = htc_send(priv->htc, beacon);
+        if (ret != 0) {
+                if (ret == -ENOMEM) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "Failed to send beacon, no free TX buffer\n");
+                }
+                dev_kfree_skb_any(beacon);
+        }
 
         spin_unlock_bh(&priv->beacon_lock);
 }
 
-/* Currently, only for IBSS */
-void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
+static int ath9k_htc_choose_bslot(struct ath9k_htc_priv *priv,
+                                  struct wmi_event_swba *swba)
 {
-        struct ath_hw *ah = priv->ah;
-        struct ath9k_tx_queue_info qi, qi_be;
-        int qnum = priv->hwq_map[WME_AC_BE];
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        u64 tsf;
+        u32 tsftu;
+        u16 intval;
+        int slot;
 
-        memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
-        memset(&qi_be, 0, sizeof(struct ath9k_tx_queue_info));
+        intval = priv->cur_beacon_conf.beacon_interval & ATH9K_BEACON_PERIOD;
 
-        ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+        tsf = be64_to_cpu(swba->tsf);
+        tsftu = TSF_TO_TU(tsf >> 32, tsf);
+        slot = ((tsftu % intval) * ATH9K_HTC_MAX_BCN_VIF) / intval;
+        slot = ATH9K_HTC_MAX_BCN_VIF - slot - 1;
 
-        qi.tqi_aifs = qi_be.tqi_aifs;
-        qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
-        qi.tqi_cwmax = qi_be.tqi_cwmax;
+        ath_dbg(common, ATH_DBG_BEACON,
+                "Choose slot: %d, tsf: %llu, tsftu: %u, intval: %u\n",
+                slot, tsf, tsftu, intval);
 
-        if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unable to update beacon queue %u!\n", qnum);
-        } else {
-                ath9k_hw_resettxqueue(ah, priv->beaconq);
+        return slot;
+}
+
+void ath9k_htc_swba(struct ath9k_htc_priv *priv,
+                    struct wmi_event_swba *swba)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        int slot;
+
+        if (swba->beacon_pending != 0) {
+                priv->cur_beacon_conf.bmiss_cnt++;
+                if (priv->cur_beacon_conf.bmiss_cnt > BSTUCK_THRESHOLD) {
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "Beacon stuck, HW reset\n");
+                        ieee80211_queue_work(priv->hw,
+                                             &priv->fatal_work);
+                }
+                return;
+        }
+
+        if (priv->cur_beacon_conf.bmiss_cnt) {
+                ath_dbg(common, ATH_DBG_BSTUCK,
+                        "Resuming beacon xmit after %u misses\n",
+                        priv->cur_beacon_conf.bmiss_cnt);
+                priv->cur_beacon_conf.bmiss_cnt = 0;
+        }
+
+        slot = ath9k_htc_choose_bslot(priv, swba);
+        spin_lock_bh(&priv->beacon_lock);
+        if (priv->cur_beacon_conf.bslot[slot] == NULL) {
+                spin_unlock_bh(&priv->beacon_lock);
+                return;
+        }
+        spin_unlock_bh(&priv->beacon_lock);
+
+        ath9k_htc_send_buffered(priv, slot);
+        ath9k_htc_send_beacon(priv, slot);
+}
+
+void ath9k_htc_assign_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *)vif->drv_priv;
+        int i = 0;
+
+        spin_lock_bh(&priv->beacon_lock);
+        for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++) {
+                if (priv->cur_beacon_conf.bslot[i] == NULL) {
+                        avp->bslot = i;
+                        break;
+                }
+        }
+
+        priv->cur_beacon_conf.bslot[avp->bslot] = vif;
+        spin_unlock_bh(&priv->beacon_lock);
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Added interface at beacon slot: %d\n", avp->bslot);
+}
+
+void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv,
+                            struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *)vif->drv_priv;
+
+        spin_lock_bh(&priv->beacon_lock);
+        priv->cur_beacon_conf.bslot[avp->bslot] = NULL;
+        spin_unlock_bh(&priv->beacon_lock);
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Removed interface at beacon slot: %d\n", avp->bslot);
+}
+
+/*
+ * Calculate the TSF adjustment value for all slots
+ * other than zero.
+ */
+void ath9k_htc_set_tsfadjust(struct ath9k_htc_priv *priv,
+                             struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *)vif->drv_priv;
+        struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
+        u64 tsfadjust;
+
+        if (avp->bslot == 0)
+                return;
+
+        /*
+         * The beacon interval cannot be different for multi-AP mode,
+         * and we reach here only for VIF slots greater than zero,
+         * so beacon_interval is guaranteed to be set in cur_conf.
+         */
+        tsfadjust = cur_conf->beacon_interval * avp->bslot / ATH9K_HTC_MAX_BCN_VIF;
+        avp->tsfadjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "tsfadjust is: %llu for bslot: %d\n",
+                (unsigned long long)tsfadjust, avp->bslot);
+}
+
+static void ath9k_htc_beacon_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        bool *beacon_configured = (bool *)data;
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
+
+        if (vif->type == NL80211_IFTYPE_STATION &&
+            avp->beacon_configured)
+                *beacon_configured = true;
+}
+
+static bool ath9k_htc_check_beacon_config(struct ath9k_htc_priv *priv,
+                                          struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        bool beacon_configured;
+
+        /*
+         * Changing the beacon interval when multiple AP interfaces
+         * are configured will affect beacon transmission of all
+         * of them.
+         */
+        if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
+            (priv->num_ap_vif > 1) &&
+            (vif->type == NL80211_IFTYPE_AP) &&
+            (cur_conf->beacon_interval != bss_conf->beacon_int)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Changing beacon interval of multiple AP interfaces !\n");
+                return false;
         }
+
+        /*
+         * If the HW is operating in AP mode, any new station interfaces that
+         * are added cannot change the beacon parameters.
+         */
+        if (priv->num_ap_vif &&
+            (vif->type != NL80211_IFTYPE_AP)) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "HW in AP mode, cannot set STA beacon parameters\n");
+                return false;
+        }
+
+        /*
+         * The beacon parameters are configured only for the first
+         * station interface.
+         */
+        if ((priv->ah->opmode == NL80211_IFTYPE_STATION) &&
+            (priv->num_sta_vif > 1) &&
+            (vif->type == NL80211_IFTYPE_STATION)) {
+                beacon_configured = false;
+                ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                           ath9k_htc_beacon_iter,
+                                                           &beacon_configured);
+
+                if (beacon_configured) {
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Beacon already configured for a station interface\n");
+                        return false;
+                }
+        }
+
+        return true;
 }
 
 void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
@@ -252,27 +612,55 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
         struct ath_common *common = ath9k_hw_common(priv->ah);
         struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
         struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
+
+        if (!ath9k_htc_check_beacon_config(priv, vif))
+                return;
 
         cur_conf->beacon_interval = bss_conf->beacon_int;
         if (cur_conf->beacon_interval == 0)
                 cur_conf->beacon_interval = 100;
 
         cur_conf->dtim_period = bss_conf->dtim_period;
-        cur_conf->listen_interval = 1;
-        cur_conf->dtim_count = 1;
         cur_conf->bmiss_timeout =
                 ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
 
         switch (vif->type) {
         case NL80211_IFTYPE_STATION:
                 ath9k_htc_beacon_config_sta(priv, cur_conf);
+                avp->beacon_configured = true;
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                ath9k_htc_beacon_config_adhoc(priv, cur_conf);
+                break;
+        case NL80211_IFTYPE_AP:
+                ath9k_htc_beacon_config_ap(priv, cur_conf);
+                break;
+        default:
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
+                return;
+        }
+}
+
+void ath9k_htc_beacon_reconfig(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
+
+        switch (priv->ah->opmode) {
+        case NL80211_IFTYPE_STATION:
+                ath9k_htc_beacon_config_sta(priv, cur_conf);
                 break;
         case NL80211_IFTYPE_ADHOC:
                 ath9k_htc_beacon_config_adhoc(priv, cur_conf);
                 break;
+        case NL80211_IFTYPE_AP:
+                ath9k_htc_beacon_config_ap(priv, cur_conf);
+                break;
         default:
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unsupported beaconing mode\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
                 return;
         }
 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
new file mode 100644
index 000000000000..aa48b3abbc48
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
@@ -0,0 +1,960 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "htc.h"
+
+static int ath9k_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t read_file_tgt_int_stats(struct file *file, char __user *user_buf,
+                                       size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath9k_htc_target_int_stats cmd_rsp;
+        char buf[512];
+        unsigned int len = 0;
+        int ret = 0;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        ath9k_htc_ps_wakeup(priv);
+
+        WMI_CMD(WMI_INT_STATS_CMDID);
+        if (ret) {
+                ath9k_htc_ps_restore(priv);
+                return -EINVAL;
+        }
+
+        ath9k_htc_ps_restore(priv);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "RX",
+                        be32_to_cpu(cmd_rsp.rx));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "RXORN",
+                        be32_to_cpu(cmd_rsp.rxorn));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "RXEOL",
+                        be32_to_cpu(cmd_rsp.rxeol));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "TXURN",
+                        be32_to_cpu(cmd_rsp.txurn));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "TXTO",
+                        be32_to_cpu(cmd_rsp.txto));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "CST",
+                        be32_to_cpu(cmd_rsp.cst));
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_tgt_int_stats = {
+        .read = read_file_tgt_int_stats,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_tgt_tx_stats(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath9k_htc_target_tx_stats cmd_rsp;
+        char buf[512];
+        unsigned int len = 0;
+        int ret = 0;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        ath9k_htc_ps_wakeup(priv);
+
+        WMI_CMD(WMI_TX_STATS_CMDID);
+        if (ret) {
+                ath9k_htc_ps_restore(priv);
+                return -EINVAL;
+        }
+
+        ath9k_htc_ps_restore(priv);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Xretries",
+                        be32_to_cpu(cmd_rsp.xretries));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "FifoErr",
+                        be32_to_cpu(cmd_rsp.fifoerr));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Filtered",
+                        be32_to_cpu(cmd_rsp.filtered));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "TimerExp",
+                        be32_to_cpu(cmd_rsp.timer_exp));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "ShortRetries",
+                        be32_to_cpu(cmd_rsp.shortretries));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "LongRetries",
+                        be32_to_cpu(cmd_rsp.longretries));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "QueueNull",
+                        be32_to_cpu(cmd_rsp.qnull));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "EncapFail",
+                        be32_to_cpu(cmd_rsp.encap_fail));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "NoBuf",
+                        be32_to_cpu(cmd_rsp.nobuf));
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_tgt_tx_stats = {
+        .read = read_file_tgt_tx_stats,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_tgt_rx_stats(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath9k_htc_target_rx_stats cmd_rsp;
+        char buf[512];
+        unsigned int len = 0;
+        int ret = 0;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        ath9k_htc_ps_wakeup(priv);
+
+        WMI_CMD(WMI_RX_STATS_CMDID);
+        if (ret) {
+                ath9k_htc_ps_restore(priv);
+                return -EINVAL;
+        }
+
+        ath9k_htc_ps_restore(priv);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "NoBuf",
+                        be32_to_cpu(cmd_rsp.nobuf));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "HostSend",
+                        be32_to_cpu(cmd_rsp.host_send));
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "HostDone",
+                        be32_to_cpu(cmd_rsp.host_done));
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_tgt_rx_stats = {
+        .read = read_file_tgt_rx_stats,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        char buf[512];
+        unsigned int len = 0;
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Buffers queued",
+                        priv->debug.tx_stats.buf_queued);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "Buffers completed",
+                        priv->debug.tx_stats.buf_completed);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "SKBs queued",
+                        priv->debug.tx_stats.skb_queued);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "SKBs success",
+                        priv->debug.tx_stats.skb_success);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "SKBs failed",
+                        priv->debug.tx_stats.skb_failed);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "CAB queued",
+                        priv->debug.tx_stats.cab_queued);
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "BE queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_BE]);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "BK queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_BK]);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "VI queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_VI]);
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "%20s : %10u\n", "VO queued",
+                        priv->debug.tx_stats.queue_stats[WME_AC_VO]);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_xmit = {
+        .read = read_file_xmit,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv,
+                           struct ath_htc_rx_status *rxs)
+{
+#define RX_PHY_ERR_INC(c) priv->debug.rx_stats.err_phy_stats[c]++
+
+        if (rxs->rs_status & ATH9K_RXERR_CRC)
+                priv->debug.rx_stats.err_crc++;
+        if (rxs->rs_status & ATH9K_RXERR_DECRYPT)
+                priv->debug.rx_stats.err_decrypt_crc++;
+        if (rxs->rs_status & ATH9K_RXERR_MIC)
+                priv->debug.rx_stats.err_mic++;
+        if (rxs->rs_status & ATH9K_RX_DELIM_CRC_PRE)
+                priv->debug.rx_stats.err_pre_delim++;
+        if (rxs->rs_status & ATH9K_RX_DELIM_CRC_POST)
+                priv->debug.rx_stats.err_post_delim++;
+        if (rxs->rs_status & ATH9K_RX_DECRYPT_BUSY)
+                priv->debug.rx_stats.err_decrypt_busy++;
+
+        if (rxs->rs_status & ATH9K_RXERR_PHY) {
+                priv->debug.rx_stats.err_phy++;
+                if (rxs->rs_phyerr < ATH9K_PHYERR_MAX)
+                        RX_PHY_ERR_INC(rxs->rs_phyerr);
+        }
+
+#undef RX_PHY_ERR_INC
+}
+
+static ssize_t read_file_recv(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+#define PHY_ERR(s, p)                                                   \
+        len += snprintf(buf + len, size - len, "%20s : %10u\n", s,      \
+                        priv->debug.rx_stats.err_phy_stats[p]);
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        char *buf;
+        unsigned int len = 0, size = 1500;
+        ssize_t retval = 0;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "SKBs allocated",
+                        priv->debug.rx_stats.skb_allocated);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "SKBs completed",
+                        priv->debug.rx_stats.skb_completed);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "SKBs Dropped",
+                        priv->debug.rx_stats.skb_dropped);
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "CRC ERR",
+                        priv->debug.rx_stats.err_crc);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "DECRYPT CRC ERR",
+                        priv->debug.rx_stats.err_decrypt_crc);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "MIC ERR",
+                        priv->debug.rx_stats.err_mic);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "PRE-DELIM CRC ERR",
+                        priv->debug.rx_stats.err_pre_delim);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "POST-DELIM CRC ERR",
+                        priv->debug.rx_stats.err_post_delim);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "DECRYPT BUSY ERR",
+                        priv->debug.rx_stats.err_decrypt_busy);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10u\n", "TOTAL PHY ERR",
+                        priv->debug.rx_stats.err_phy);
+
+
+        PHY_ERR("UNDERRUN", ATH9K_PHYERR_UNDERRUN);
+        PHY_ERR("TIMING", ATH9K_PHYERR_TIMING);
+        PHY_ERR("PARITY", ATH9K_PHYERR_PARITY);
+        PHY_ERR("RATE", ATH9K_PHYERR_RATE);
+        PHY_ERR("LENGTH", ATH9K_PHYERR_LENGTH);
+        PHY_ERR("RADAR", ATH9K_PHYERR_RADAR);
+        PHY_ERR("SERVICE", ATH9K_PHYERR_SERVICE);
+        PHY_ERR("TOR", ATH9K_PHYERR_TOR);
+        PHY_ERR("OFDM-TIMING", ATH9K_PHYERR_OFDM_TIMING);
+        PHY_ERR("OFDM-SIGNAL-PARITY", ATH9K_PHYERR_OFDM_SIGNAL_PARITY);
+        PHY_ERR("OFDM-RATE", ATH9K_PHYERR_OFDM_RATE_ILLEGAL);
+        PHY_ERR("OFDM-LENGTH", ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL);
+        PHY_ERR("OFDM-POWER-DROP", ATH9K_PHYERR_OFDM_POWER_DROP);
+        PHY_ERR("OFDM-SERVICE", ATH9K_PHYERR_OFDM_SERVICE);
+        PHY_ERR("OFDM-RESTART", ATH9K_PHYERR_OFDM_RESTART);
+        PHY_ERR("FALSE-RADAR-EXT", ATH9K_PHYERR_FALSE_RADAR_EXT);
+        PHY_ERR("CCK-TIMING", ATH9K_PHYERR_CCK_TIMING);
+        PHY_ERR("CCK-HEADER-CRC", ATH9K_PHYERR_CCK_HEADER_CRC);
+        PHY_ERR("CCK-RATE", ATH9K_PHYERR_CCK_RATE_ILLEGAL);
+        PHY_ERR("CCK-SERVICE", ATH9K_PHYERR_CCK_SERVICE);
+        PHY_ERR("CCK-RESTART", ATH9K_PHYERR_CCK_RESTART);
+        PHY_ERR("CCK-LENGTH", ATH9K_PHYERR_CCK_LENGTH_ILLEGAL);
+        PHY_ERR("CCK-POWER-DROP", ATH9K_PHYERR_CCK_POWER_DROP);
+        PHY_ERR("HT-CRC", ATH9K_PHYERR_HT_CRC_ERROR);
+        PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL);
+        PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PHY_ERR
+}
+
+static const struct file_operations fops_recv = {
+        .read = read_file_recv,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_slot(struct file *file, char __user *user_buf,
+                              size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        char buf[512];
+        unsigned int len = 0;
+
+        spin_lock_bh(&priv->tx.tx_lock);
+
+        len += snprintf(buf + len, sizeof(buf) - len, "TX slot bitmap : ");
+
+        len += bitmap_scnprintf(buf + len, sizeof(buf) - len,
+                               priv->tx.tx_slot, MAX_TX_BUF_NUM);
+
+        len += snprintf(buf + len, sizeof(buf) - len, "\n");
+
+        len += snprintf(buf + len, sizeof(buf) - len,
+                        "Used slots     : %d\n",
+                        bitmap_weight(priv->tx.tx_slot, MAX_TX_BUF_NUM));
+
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static const struct file_operations fops_slot = {
+        .read = read_file_slot,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_queue(struct file *file, char __user *user_buf,
+                               size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        char buf[512];
+        unsigned int len = 0;
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Mgmt endpoint", skb_queue_len(&priv->tx.mgmt_ep_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Cab endpoint", skb_queue_len(&priv->tx.cab_ep_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data BE endpoint", skb_queue_len(&priv->tx.data_be_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data BK endpoint", skb_queue_len(&priv->tx.data_bk_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data VI endpoint", skb_queue_len(&priv->tx.data_vi_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Data VO endpoint", skb_queue_len(&priv->tx.data_vo_queue));
+
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Failed queue", skb_queue_len(&priv->tx.tx_failed));
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        len += snprintf(buf + len, sizeof(buf) - len, "%20s : %10u\n",
+                        "Queued count", priv->tx.queued_cnt);
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        if (len > sizeof(buf))
+                len = sizeof(buf);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+
+}
+
+static const struct file_operations fops_queue = {
+        .read = read_file_queue,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_debug(struct file *file, char __user *user_buf,
+                               size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        char buf[32];
+        unsigned int len;
+
+        len = sprintf(buf, "0x%08x\n", common->debug_mask);
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
+                                size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        unsigned long mask;
+        char buf[32];
+        ssize_t len;
+
+        len = min(count, sizeof(buf) - 1);
+        if (copy_from_user(buf, user_buf, len))
+                return -EFAULT;
+
+        buf[len] = '\0';
+        if (strict_strtoul(buf, 0, &mask))
+                return -EINVAL;
+
+        common->debug_mask = mask;
+        return count;
+}
+
+static const struct file_operations fops_debug = {
+        .read = read_file_debug,
+        .write = write_file_debug,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_file_base_eeprom(struct file *file, char __user *user_buf,
+                                     size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct base_eep_header *pBase = NULL;
+        unsigned int len = 0, size = 1500;
+        ssize_t retval = 0;
+        char *buf;
+
+        /*
+         * This can be done since all the 3 EEPROM families have the
+         * same base header upto a certain point, and we are interested in
+         * the data only upto that point.
+         */
+
+        if (AR_SREV_9271(priv->ah))
+                pBase = (struct base_eep_header *)
+                        &priv->ah->eeprom.map4k.baseEepHeader;
+        else if (priv->ah->hw_version.usbdev == AR9280_USB)
+                pBase = (struct base_eep_header *)
+                        &priv->ah->eeprom.def.baseEepHeader;
+        else if (priv->ah->hw_version.usbdev == AR9287_USB)
+                pBase = (struct base_eep_header *)
+                        &priv->ah->eeprom.map9287.baseEepHeader;
+
+        if (pBase == NULL) {
+                ath_err(common, "Unknown EEPROM type\n");
+                return 0;
+        }
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Major Version",
+                        pBase->version >> 12);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Minor Version",
+                        pBase->version & 0xFFF);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Checksum",
+                        pBase->checksum);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "Length",
+                        pBase->length);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "RegDomain1",
+                        pBase->regDmn[0]);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n", "RegDomain2",
+                        pBase->regDmn[1]);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "TX Mask", pBase->txMask);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "RX Mask", pBase->rxMask);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Allow 5GHz",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Allow 2GHz",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 2GHz HT20",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_2G_HT20));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 2GHz HT40",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_2G_HT40));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 5Ghz HT20",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_5G_HT20));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Disable 5Ghz HT40",
+                        !!(pBase->opCapFlags & AR5416_OPFLAGS_N_5G_HT40));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Big Endian",
+                        !!(pBase->eepMisc & 0x01));
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Cal Bin Major Ver",
+                        (pBase->binBuildNumber >> 24) & 0xFF);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Cal Bin Minor Ver",
+                        (pBase->binBuildNumber >> 16) & 0xFF);
+        len += snprintf(buf + len, size - len,
+                        "%20s : %10d\n",
+                        "Cal Bin Build",
+                        (pBase->binBuildNumber >> 8) & 0xFF);
+
+        /*
+         * UB91 specific data.
+         */
+        if (AR_SREV_9271(priv->ah)) {
+                struct base_eep_header_4k *pBase4k =
+                        &priv->ah->eeprom.map4k.baseEepHeader;
+
+                len += snprintf(buf + len, size - len,
+                                "%20s : %10d\n",
+                                "TX Gain type",
+                                pBase4k->txGainType);
+        }
+
+        /*
+         * UB95 specific data.
+         */
+        if (priv->ah->hw_version.usbdev == AR9287_USB) {
+                struct base_eep_ar9287_header *pBase9287 =
+                        &priv->ah->eeprom.map9287.baseEepHeader;
+
+                len += snprintf(buf + len, size - len,
+                                "%20s : %10ddB\n",
+                                "Power Table Offset",
+                                pBase9287->pwrTableOffset);
+
+                len += snprintf(buf + len, size - len,
+                                "%20s : %10d\n",
+                                "OpenLoop Power Ctrl",
+                                pBase9287->openLoopPwrCntl);
+        }
+
+        len += snprintf(buf + len, size - len,
+                        "%20s : %02X:%02X:%02X:%02X:%02X:%02X\n",
+                        "MacAddress",
+                        pBase->macAddr[0], pBase->macAddr[1], pBase->macAddr[2],
+                        pBase->macAddr[3], pBase->macAddr[4], pBase->macAddr[5]);
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+static const struct file_operations fops_base_eeprom = {
+        .read = read_file_base_eeprom,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+static ssize_t read_4k_modal_eeprom(struct file *file,
+                                    char __user *user_buf,
+                                    size_t count, loff_t *ppos)
+{
+#define PR_EEP(_s, _val)                                                \
+        do {                                                            \
+                len += snprintf(buf + len, size - len, "%20s : %10d\n", \
+                                _s, (_val));                            \
+        } while (0)
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct modal_eep_4k_header *pModal = &priv->ah->eeprom.map4k.modalHeader;
+        unsigned int len = 0, size = 2048;
+        ssize_t retval = 0;
+        char *buf;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        PR_EEP("Chain0 Ant. Control", pModal->antCtrlChain[0]);
+        PR_EEP("Ant. Common Control", pModal->antCtrlCommon);
+        PR_EEP("Chain0 Ant. Gain", pModal->antennaGainCh[0]);
+        PR_EEP("Switch Settle", pModal->switchSettling);
+        PR_EEP("Chain0 TxRxAtten", pModal->txRxAttenCh[0]);
+        PR_EEP("Chain0 RxTxMargin", pModal->rxTxMarginCh[0]);
+        PR_EEP("ADC Desired size", pModal->adcDesiredSize);
+        PR_EEP("PGA Desired size", pModal->pgaDesiredSize);
+        PR_EEP("Chain0 xlna Gain", pModal->xlnaGainCh[0]);
+        PR_EEP("txEndToXpaOff", pModal->txEndToXpaOff);
+        PR_EEP("txEndToRxOn", pModal->txEndToRxOn);
+        PR_EEP("txFrameToXpaOn", pModal->txFrameToXpaOn);
+        PR_EEP("CCA Threshold)", pModal->thresh62);
+        PR_EEP("Chain0 NF Threshold", pModal->noiseFloorThreshCh[0]);
+        PR_EEP("xpdGain", pModal->xpdGain);
+        PR_EEP("External PD", pModal->xpd);
+        PR_EEP("Chain0 I Coefficient", pModal->iqCalICh[0]);
+        PR_EEP("Chain0 Q Coefficient", pModal->iqCalQCh[0]);
+        PR_EEP("pdGainOverlap", pModal->pdGainOverlap);
+        PR_EEP("O/D Bias Version", pModal->version);
+        PR_EEP("CCK OutputBias", pModal->ob_0);
+        PR_EEP("BPSK OutputBias", pModal->ob_1);
+        PR_EEP("QPSK OutputBias", pModal->ob_2);
+        PR_EEP("16QAM OutputBias", pModal->ob_3);
+        PR_EEP("64QAM OutputBias", pModal->ob_4);
+        PR_EEP("CCK Driver1_Bias", pModal->db1_0);
+        PR_EEP("BPSK Driver1_Bias", pModal->db1_1);
+        PR_EEP("QPSK Driver1_Bias", pModal->db1_2);
+        PR_EEP("16QAM Driver1_Bias", pModal->db1_3);
+        PR_EEP("64QAM Driver1_Bias", pModal->db1_4);
+        PR_EEP("CCK Driver2_Bias", pModal->db2_0);
+        PR_EEP("BPSK Driver2_Bias", pModal->db2_1);
+        PR_EEP("QPSK Driver2_Bias", pModal->db2_2);
+        PR_EEP("16QAM Driver2_Bias", pModal->db2_3);
+        PR_EEP("64QAM Driver2_Bias", pModal->db2_4);
+        PR_EEP("xPA Bias Level", pModal->xpaBiasLvl);
+        PR_EEP("txFrameToDataStart", pModal->txFrameToDataStart);
+        PR_EEP("txFrameToPaOn", pModal->txFrameToPaOn);
+        PR_EEP("HT40 Power Inc.", pModal->ht40PowerIncForPdadc);
+        PR_EEP("Chain0 bswAtten", pModal->bswAtten[0]);
+        PR_EEP("Chain0 bswMargin", pModal->bswMargin[0]);
+        PR_EEP("HT40 Switch Settle", pModal->swSettleHt40);
+        PR_EEP("Chain0 xatten2Db", pModal->xatten2Db[0]);
+        PR_EEP("Chain0 xatten2Margin", pModal->xatten2Margin[0]);
+        PR_EEP("Ant. Diversity ctl1", pModal->antdiv_ctl1);
+        PR_EEP("Ant. Diversity ctl2", pModal->antdiv_ctl2);
+        PR_EEP("TX Diversity", pModal->tx_diversity);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PR_EEP
+}
+
+static ssize_t read_def_modal_eeprom(struct file *file,
+                                     char __user *user_buf,
+                                     size_t count, loff_t *ppos)
+{
+#define PR_EEP(_s, _val)                                                \
+        do {                                                            \
+                if (pBase->opCapFlags & AR5416_OPFLAGS_11G) {           \
+                        pModal = &priv->ah->eeprom.def.modalHeader[1];  \
+                        len += snprintf(buf + len, size - len, "%20s : %8d%7s", \
+                                        _s, (_val), "|");               \
+                }                                                       \
+                if (pBase->opCapFlags & AR5416_OPFLAGS_11A) {           \
+                        pModal = &priv->ah->eeprom.def.modalHeader[0];  \
+                        len += snprintf(buf + len, size - len, "%9d\n", \
+                                        (_val));                        \
+                }                                                       \
+        } while (0)
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct base_eep_header *pBase = &priv->ah->eeprom.def.baseEepHeader;
+        struct modal_eep_header *pModal = NULL;
+        unsigned int len = 0, size = 3500;
+        ssize_t retval = 0;
+        char *buf;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len,
+                        "%31s %15s\n", "2G", "5G");
+        len += snprintf(buf + len, size - len,
+                        "%32s %16s\n", "====", "====\n");
+
+        PR_EEP("Chain0 Ant. Control", pModal->antCtrlChain[0]);
+        PR_EEP("Chain1 Ant. Control", pModal->antCtrlChain[1]);
+        PR_EEP("Chain2 Ant. Control", pModal->antCtrlChain[2]);
+        PR_EEP("Ant. Common Control", pModal->antCtrlCommon);
+        PR_EEP("Chain0 Ant. Gain", pModal->antennaGainCh[0]);
+        PR_EEP("Chain1 Ant. Gain", pModal->antennaGainCh[1]);
+        PR_EEP("Chain2 Ant. Gain", pModal->antennaGainCh[2]);
+        PR_EEP("Switch Settle", pModal->switchSettling);
+        PR_EEP("Chain0 TxRxAtten", pModal->txRxAttenCh[0]);
+        PR_EEP("Chain1 TxRxAtten", pModal->txRxAttenCh[1]);
+        PR_EEP("Chain2 TxRxAtten", pModal->txRxAttenCh[2]);
+        PR_EEP("Chain0 RxTxMargin", pModal->rxTxMarginCh[0]);
+        PR_EEP("Chain1 RxTxMargin", pModal->rxTxMarginCh[1]);
+        PR_EEP("Chain2 RxTxMargin", pModal->rxTxMarginCh[2]);
+        PR_EEP("ADC Desired size", pModal->adcDesiredSize);
+        PR_EEP("PGA Desired size", pModal->pgaDesiredSize);
+        PR_EEP("Chain0 xlna Gain", pModal->xlnaGainCh[0]);
+        PR_EEP("Chain1 xlna Gain", pModal->xlnaGainCh[1]);
+        PR_EEP("Chain2 xlna Gain", pModal->xlnaGainCh[2]);
+        PR_EEP("txEndToXpaOff", pModal->txEndToXpaOff);
+        PR_EEP("txEndToRxOn", pModal->txEndToRxOn);
+        PR_EEP("txFrameToXpaOn", pModal->txFrameToXpaOn);
+        PR_EEP("CCA Threshold)", pModal->thresh62);
+        PR_EEP("Chain0 NF Threshold", pModal->noiseFloorThreshCh[0]);
+        PR_EEP("Chain1 NF Threshold", pModal->noiseFloorThreshCh[1]);
+        PR_EEP("Chain2 NF Threshold", pModal->noiseFloorThreshCh[2]);
+        PR_EEP("xpdGain", pModal->xpdGain);
+        PR_EEP("External PD", pModal->xpd);
+        PR_EEP("Chain0 I Coefficient", pModal->iqCalICh[0]);
+        PR_EEP("Chain1 I Coefficient", pModal->iqCalICh[1]);
+        PR_EEP("Chain2 I Coefficient", pModal->iqCalICh[2]);
+        PR_EEP("Chain0 Q Coefficient", pModal->iqCalQCh[0]);
+        PR_EEP("Chain1 Q Coefficient", pModal->iqCalQCh[1]);
+        PR_EEP("Chain2 Q Coefficient", pModal->iqCalQCh[2]);
+        PR_EEP("pdGainOverlap", pModal->pdGainOverlap);
+        PR_EEP("Chain0 OutputBias", pModal->ob);
+        PR_EEP("Chain0 DriverBias", pModal->db);
+        PR_EEP("xPA Bias Level", pModal->xpaBiasLvl);
+        PR_EEP("2chain pwr decrease", pModal->pwrDecreaseFor2Chain);
+        PR_EEP("3chain pwr decrease", pModal->pwrDecreaseFor3Chain);
+        PR_EEP("txFrameToDataStart", pModal->txFrameToDataStart);
+        PR_EEP("txFrameToPaOn", pModal->txFrameToPaOn);
+        PR_EEP("HT40 Power Inc.", pModal->ht40PowerIncForPdadc);
+        PR_EEP("Chain0 bswAtten", pModal->bswAtten[0]);
+        PR_EEP("Chain1 bswAtten", pModal->bswAtten[1]);
+        PR_EEP("Chain2 bswAtten", pModal->bswAtten[2]);
+        PR_EEP("Chain0 bswMargin", pModal->bswMargin[0]);
+        PR_EEP("Chain1 bswMargin", pModal->bswMargin[1]);
+        PR_EEP("Chain2 bswMargin", pModal->bswMargin[2]);
+        PR_EEP("HT40 Switch Settle", pModal->swSettleHt40);
+        PR_EEP("Chain0 xatten2Db", pModal->xatten2Db[0]);
+        PR_EEP("Chain1 xatten2Db", pModal->xatten2Db[1]);
+        PR_EEP("Chain2 xatten2Db", pModal->xatten2Db[2]);
+        PR_EEP("Chain0 xatten2Margin", pModal->xatten2Margin[0]);
+        PR_EEP("Chain1 xatten2Margin", pModal->xatten2Margin[1]);
+        PR_EEP("Chain2 xatten2Margin", pModal->xatten2Margin[2]);
+        PR_EEP("Chain1 OutputBias", pModal->ob_ch1);
+        PR_EEP("Chain1 DriverBias", pModal->db_ch1);
+        PR_EEP("LNA Control", pModal->lna_ctl);
+        PR_EEP("XPA Bias Freq0", pModal->xpaBiasLvlFreq[0]);
+        PR_EEP("XPA Bias Freq1", pModal->xpaBiasLvlFreq[1]);
+        PR_EEP("XPA Bias Freq2", pModal->xpaBiasLvlFreq[2]);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PR_EEP
+}
+
+static ssize_t read_9287_modal_eeprom(struct file *file,
+                                      char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+#define PR_EEP(_s, _val)                                                \
+        do {                                                            \
+                len += snprintf(buf + len, size - len, "%20s : %10d\n", \
+                                _s, (_val));                            \
+        } while (0)
+
+        struct ath9k_htc_priv *priv = file->private_data;
+        struct modal_eep_ar9287_header *pModal = &priv->ah->eeprom.map9287.modalHeader;
+        unsigned int len = 0, size = 3000;
+        ssize_t retval = 0;
+        char *buf;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        PR_EEP("Chain0 Ant. Control", pModal->antCtrlChain[0]);
+        PR_EEP("Chain1 Ant. Control", pModal->antCtrlChain[1]);
+        PR_EEP("Ant. Common Control", pModal->antCtrlCommon);
+        PR_EEP("Chain0 Ant. Gain", pModal->antennaGainCh[0]);
+        PR_EEP("Chain1 Ant. Gain", pModal->antennaGainCh[1]);
+        PR_EEP("Switch Settle", pModal->switchSettling);
+        PR_EEP("Chain0 TxRxAtten", pModal->txRxAttenCh[0]);
+        PR_EEP("Chain1 TxRxAtten", pModal->txRxAttenCh[1]);
+        PR_EEP("Chain0 RxTxMargin", pModal->rxTxMarginCh[0]);
+        PR_EEP("Chain1 RxTxMargin", pModal->rxTxMarginCh[1]);
+        PR_EEP("ADC Desired size", pModal->adcDesiredSize);
+        PR_EEP("txEndToXpaOff", pModal->txEndToXpaOff);
+        PR_EEP("txEndToRxOn", pModal->txEndToRxOn);
+        PR_EEP("txFrameToXpaOn", pModal->txFrameToXpaOn);
+        PR_EEP("CCA Threshold)", pModal->thresh62);
+        PR_EEP("Chain0 NF Threshold", pModal->noiseFloorThreshCh[0]);
+        PR_EEP("Chain1 NF Threshold", pModal->noiseFloorThreshCh[1]);
+        PR_EEP("xpdGain", pModal->xpdGain);
+        PR_EEP("External PD", pModal->xpd);
+        PR_EEP("Chain0 I Coefficient", pModal->iqCalICh[0]);
+        PR_EEP("Chain1 I Coefficient", pModal->iqCalICh[1]);
+        PR_EEP("Chain0 Q Coefficient", pModal->iqCalQCh[0]);
+        PR_EEP("Chain1 Q Coefficient", pModal->iqCalQCh[1]);
+        PR_EEP("pdGainOverlap", pModal->pdGainOverlap);
+        PR_EEP("xPA Bias Level", pModal->xpaBiasLvl);
+        PR_EEP("txFrameToDataStart", pModal->txFrameToDataStart);
+        PR_EEP("txFrameToPaOn", pModal->txFrameToPaOn);
+        PR_EEP("HT40 Power Inc.", pModal->ht40PowerIncForPdadc);
+        PR_EEP("Chain0 bswAtten", pModal->bswAtten[0]);
+        PR_EEP("Chain1 bswAtten", pModal->bswAtten[1]);
+        PR_EEP("Chain0 bswMargin", pModal->bswMargin[0]);
+        PR_EEP("Chain1 bswMargin", pModal->bswMargin[1]);
+        PR_EEP("HT40 Switch Settle", pModal->swSettleHt40);
+        PR_EEP("AR92x7 Version", pModal->version);
+        PR_EEP("DriverBias1", pModal->db1);
+        PR_EEP("DriverBias2", pModal->db1);
+        PR_EEP("CCK OutputBias", pModal->ob_cck);
+        PR_EEP("PSK OutputBias", pModal->ob_psk);
+        PR_EEP("QAM OutputBias", pModal->ob_qam);
+        PR_EEP("PAL_OFF OutputBias", pModal->ob_pal_off);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+
+#undef PR_EEP
+}
+
+static ssize_t read_file_modal_eeprom(struct file *file, char __user *user_buf,
+                                      size_t count, loff_t *ppos)
+{
+        struct ath9k_htc_priv *priv = file->private_data;
+
+        if (AR_SREV_9271(priv->ah))
+                return read_4k_modal_eeprom(file, user_buf, count, ppos);
+        else if (priv->ah->hw_version.usbdev == AR9280_USB)
+                return read_def_modal_eeprom(file, user_buf, count, ppos);
+        else if (priv->ah->hw_version.usbdev == AR9287_USB)
+                return read_9287_modal_eeprom(file, user_buf, count, ppos);
+
+        return 0;
+}
+
+static const struct file_operations fops_modal_eeprom = {
+        .read = read_file_modal_eeprom,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+int ath9k_htc_init_debug(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
+
+        priv->debug.debugfs_phy = debugfs_create_dir(KBUILD_MODNAME,
+                                             priv->hw->wiphy->debugfsdir);
+        if (!priv->debug.debugfs_phy)
+                return -ENOMEM;
+
+        debugfs_create_file("tgt_int_stats", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_tgt_int_stats);
+        debugfs_create_file("tgt_tx_stats", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_tgt_tx_stats);
+        debugfs_create_file("tgt_rx_stats", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_tgt_rx_stats);
+        debugfs_create_file("xmit", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_xmit);
+        debugfs_create_file("recv", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_recv);
+        debugfs_create_file("slot", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_slot);
+        debugfs_create_file("queue", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_queue);
+        debugfs_create_file("debug", S_IRUSR | S_IWUSR, priv->debug.debugfs_phy,
+                            priv, &fops_debug);
+        debugfs_create_file("base_eeprom", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_base_eeprom);
+        debugfs_create_file("modal_eeprom", S_IRUSR, priv->debug.debugfs_phy,
+                            priv, &fops_modal_eeprom);
+
+        return 0;
+}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
new file mode 100644
index 000000000000..db2352e5cc0d
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "htc.h"
+
+/******************/
+/*     BTCOEX     */
+/******************/
+
+/*
+ * Detects if there is any priority bt traffic
+ */
+static void ath_detect_bt_priority(struct ath9k_htc_priv *priv)
+{
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_hw *ah = priv->ah;
+
+        if (ath9k_hw_gpio_get(ah, ah->btcoex_hw.btpriority_gpio))
+                btcoex->bt_priority_cnt++;
+
+        if (time_after(jiffies, btcoex->bt_priority_time +
+                        msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
+                priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN);
+                /* Detect if colocated bt started scanning */
+                if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "BT scan detected\n");
+                        priv->op_flags |= (OP_BT_SCAN |
+                                         OP_BT_PRIORITY_DETECTED);
+                } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "BT priority traffic detected\n");
+                        priv->op_flags |= OP_BT_PRIORITY_DETECTED;
+                }
+
+                btcoex->bt_priority_cnt = 0;
+                btcoex->bt_priority_time = jiffies;
+        }
+}
+
+/*
+ * This is the master bt coex work which runs for every
+ * 45ms, bt traffic will be given priority during 55% of this
+ * period while wlan gets remaining 45%
+ */
+static void ath_btcoex_period_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   coex_period_work.work);
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        u32 timer_period;
+        bool is_btscan;
+        int ret;
+
+        ath_detect_bt_priority(priv);
+
+        is_btscan = !!(priv->op_flags & OP_BT_SCAN);
+
+        ret = ath9k_htc_update_cap_target(priv,
+                                  !!(priv->op_flags & OP_BT_PRIORITY_DETECTED));
+        if (ret) {
+                ath_err(common, "Unable to set BTCOEX parameters\n");
+                return;
+        }
+
+        ath9k_hw_btcoex_bt_stomp(priv->ah, is_btscan ? ATH_BTCOEX_STOMP_ALL :
+                        btcoex->bt_stomp_type);
+
+        timer_period = is_btscan ? btcoex->btscan_no_stomp :
+                btcoex->btcoex_no_stomp;
+        ieee80211_queue_delayed_work(priv->hw, &priv->duty_cycle_work,
+                                     msecs_to_jiffies(timer_period));
+        ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work,
+                                     msecs_to_jiffies(btcoex->btcoex_period));
+}
+
+/*
+ * Work to time slice between wlan and bt traffic and
+ * configure weight registers
+ */
+static void ath_btcoex_duty_cycle_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   duty_cycle_work.work);
+        struct ath_hw *ah = priv->ah;
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_common *common = ath9k_hw_common(ah);
+        bool is_btscan = priv->op_flags & OP_BT_SCAN;
+
+        ath_dbg(common, ATH_DBG_BTCOEX,
+                "time slice work for bt and wlan\n");
+
+        if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
+        else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
+                ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
+}
+
+void ath_htc_init_btcoex_work(struct ath9k_htc_priv *priv)
+{
+        struct ath_btcoex *btcoex = &priv->btcoex;
+
+        btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
+        btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
+                btcoex->btcoex_period / 100;
+        btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
+                                   btcoex->btcoex_period / 100;
+        INIT_DELAYED_WORK(&priv->coex_period_work, ath_btcoex_period_work);
+        INIT_DELAYED_WORK(&priv->duty_cycle_work, ath_btcoex_duty_cycle_work);
+}
+
+/*
+ * (Re)start btcoex work
+ */
+
+void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv)
+{
+        struct ath_btcoex *btcoex = &priv->btcoex;
+        struct ath_hw *ah = priv->ah;
+
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, "Starting btcoex work\n");
+
+        btcoex->bt_priority_cnt = 0;
+        btcoex->bt_priority_time = jiffies;
+        priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN);
+        ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 0);
+}
+
+
+/*
+ * Cancel btcoex and bt duty cycle work.
+ */
+void ath_htc_cancel_btcoex_work(struct ath9k_htc_priv *priv)
+{
+        cancel_delayed_work_sync(&priv->coex_period_work);
+        cancel_delayed_work_sync(&priv->duty_cycle_work);
+}
+
+/*******/
+/* LED */
+/*******/
+
+#ifdef CONFIG_MAC80211_LEDS
+void ath9k_led_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work,
+                                                   struct ath9k_htc_priv,
+                                                   led_work);
+
+        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
+                          (priv->brightness == LED_OFF));
+}
+
+static void ath9k_led_brightness(struct led_classdev *led_cdev,
+                                 enum led_brightness brightness)
+{
+        struct ath9k_htc_priv *priv = container_of(led_cdev,
+                                                   struct ath9k_htc_priv,
+                                                   led_cdev);
+
+        /* Not locked, but it's just a tiny green light..*/
+        priv->brightness = brightness;
+        ieee80211_queue_work(priv->hw, &priv->led_work);
+}
+
+void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
+{
+        if (!priv->led_registered)
+                return;
+
+        ath9k_led_brightness(&priv->led_cdev, LED_OFF);
+        led_classdev_unregister(&priv->led_cdev);
+        cancel_work_sync(&priv->led_work);
+}
+
+void ath9k_init_leds(struct ath9k_htc_priv *priv)
+{
+        int ret;
+
+        if (AR_SREV_9287(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_9287;
+        else if (AR_SREV_9271(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_9271;
+        else if (AR_DEVID_7010(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_7010;
+        else
+                priv->ah->led_pin = ATH_LED_PIN_DEF;
+
+        /* Configure gpio 1 for output */
+        ath9k_hw_cfg_output(priv->ah, priv->ah->led_pin,
+                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+        /* LED off, active low */
+        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
+
+        snprintf(priv->led_name, sizeof(priv->led_name),
+                "ath9k_htc-%s", wiphy_name(priv->hw->wiphy));
+        priv->led_cdev.name = priv->led_name;
+        priv->led_cdev.brightness_set = ath9k_led_brightness;
+
+        ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &priv->led_cdev);
+        if (ret < 0)
+                return;
+
+        INIT_WORK(&priv->led_work, ath9k_led_work);
+        priv->led_registered = true;
+
+        return;
+}
+#endif
+
+/*******************/
+/*      Rfkill     */
+/*******************/
+
+static bool ath_is_rfkill_set(struct ath9k_htc_priv *priv)
+{
+        return ath9k_hw_gpio_get(priv->ah, priv->ah->rfkill_gpio) ==
+                priv->ah->rfkill_polarity;
+}
+
+void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        bool blocked = !!ath_is_rfkill_set(priv);
+
+        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
+}
+
+void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
+{
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
+                wiphy_rfkill_start_polling(priv->hw->wiphy);
+}
+
+void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret;
+        u8 cmd_rsp;
+
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        /* Reset the HW */
+        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, ah->curchan->channel);
+        }
+
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
+
+        /* Start RX */
+        WMI_CMD(WMI_START_RECV_CMDID);
+        ath9k_host_rx_init(priv);
+
+        /* Start TX */
+        htc_start(priv->htc);
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
+        spin_unlock_bh(&priv->tx.tx_lock);
+        ieee80211_wake_queues(hw);
+
+        WMI_CMD(WMI_ENABLE_INTR_CMDID);
+
+        /* Enable LED */
+        ath9k_hw_cfg_output(ah, ah->led_pin,
+                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
+}
+
+void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret;
+        u8 cmd_rsp;
+
+        ath9k_htc_ps_wakeup(priv);
+
+        /* Disable LED */
+        ath9k_hw_set_gpio(ah, ah->led_pin, 1);
+        ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+
+        /* Stop TX */
+        ieee80211_stop_queues(hw);
+        ath9k_htc_tx_drain(priv);
+        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
+
+        /* Stop RX */
+        WMI_CMD(WMI_STOP_RECV_CMDID);
+
+        /* Clear the WMI event queue */
+        ath9k_wmi_event_drain(priv);
+
+        /*
+         * The MIB counters have to be disabled here,
+         * since the target doesn't do it.
+         */
+        ath9k_hw_disable_mib_counters(ah);
+
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        /* Reset the HW */
+        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, ah->curchan->channel);
+        }
+
+        /* Disable the PHY */
+        ath9k_hw_phy_disable(ah);
+
+        ath9k_htc_ps_restore(priv);
+        ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
+}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 2d4279191d7a..61e6d3950718 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -41,6 +41,8 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
         .max_power = 20, \
 }
 
+#define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
+
 static struct ieee80211_channel ath9k_2ghz_channels[] = {
         CHAN2G(2412, 0), /* Channel 1 */
         CHAN2G(2417, 1), /* Channel 2 */
@@ -115,6 +117,21 @@ static struct ieee80211_rate ath9k_legacy_rates[] = {
         RATE(540, 0x0c, 0),
 };
 
+#ifdef CONFIG_MAC80211_LEDS
+static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
+        { .throughput = 0 * 1024, .blink_time = 334 },
+        { .throughput = 1 * 1024, .blink_time = 260 },
+        { .throughput = 5 * 1024, .blink_time = 220 },
+        { .throughput = 10 * 1024, .blink_time = 190 },
+        { .throughput = 20 * 1024, .blink_time = 170 },
+        { .throughput = 50 * 1024, .blink_time = 150 },
+        { .throughput = 70 * 1024, .blink_time = 130 },
+        { .throughput = 100 * 1024, .blink_time = 110 },
+        { .throughput = 200 * 1024, .blink_time = 80 },
+        { .throughput = 300 * 1024, .blink_time = 50 },
+};
+#endif
+
 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
 {
         int time_left;
@@ -138,11 +155,7 @@ static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
 
 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
 {
-        ath9k_htc_exit_debug(priv->ah);
         ath9k_hw_deinit(priv->ah);
-        tasklet_kill(&priv->wmi_tasklet);
-        tasklet_kill(&priv->rx_tasklet);
-        tasklet_kill(&priv->tx_tasklet);
         kfree(priv->ah);
         priv->ah = NULL;
 }
@@ -179,7 +192,8 @@ static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
         return htc_connect_service(priv->htc, &req, ep_id);
 }
 
-static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
+static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
+                                   u32 drv_info)
 {
         int ret;
 
@@ -243,15 +257,10 @@ static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
          * the HIF layer, shouldn't matter much.
          */
 
-        switch(devid) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
+        if (IS_AR7010_DEVICE(drv_info))
                 priv->htc->credits = 45;
-                break;
-        default:
+        else
                 priv->htc->credits = 33;
-        }
 
         ret = htc_init(priv->htc);
         if (ret)
@@ -290,21 +299,49 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
                           (u8 *) &val, sizeof(val),
                           100);
         if (unlikely(r)) {
-                ath_print(common, ATH_DBG_WMI,
-                          "REGISTER READ FAILED: (0x%04x, %d)\n",
-                           reg_offset, r);
+                ath_dbg(common, ATH_DBG_WMI,
+                        "REGISTER READ FAILED: (0x%04x, %d)\n",
+                        reg_offset, r);
                 return -EIO;
         }
 
         return be32_to_cpu(val);
 }
 
+static void ath9k_multi_regread(void *hw_priv, u32 *addr,
+                                u32 *val, u16 count)
+{
+        struct ath_hw *ah = (struct ath_hw *) hw_priv;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
+        __be32 tmpaddr[8];
+        __be32 tmpval[8];
+        int i, ret;
+
+       for (i = 0; i < count; i++) {
+               tmpaddr[i] = cpu_to_be32(addr[i]);
+       }
+
+       ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
+                           (u8 *)tmpaddr , sizeof(u32) * count,
+                           (u8 *)tmpval, sizeof(u32) * count,
+                           100);
+        if (unlikely(ret)) {
+                ath_dbg(common, ATH_DBG_WMI,
+                        "Multiple REGISTER READ FAILED (count: %d)\n", count);
+        }
+
+       for (i = 0; i < count; i++) {
+               val[i] = be32_to_cpu(tmpval[i]);
+       }
+}
+
 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
 {
         struct ath_hw *ah = (struct ath_hw *) hw_priv;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-        __be32 buf[2] = {
+        const __be32 buf[2] = {
                 cpu_to_be32(reg_offset),
                 cpu_to_be32(val),
         };
@@ -315,9 +352,9 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
                           (u8 *) &val, sizeof(val),
                           100);
         if (unlikely(r)) {
-                ath_print(common, ATH_DBG_WMI,
-                          "REGISTER WRITE FAILED:(0x%04x, %d)\n",
-                          reg_offset, r);
+                ath_dbg(common, ATH_DBG_WMI,
+                        "REGISTER WRITE FAILED:(0x%04x, %d)\n",
+                        reg_offset, r);
         }
 }
 
@@ -347,9 +384,9 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
                           (u8 *) &rsp_status, sizeof(rsp_status),
                           100);
                 if (unlikely(r)) {
-                        ath_print(common, ATH_DBG_WMI,
-                                  "REGISTER WRITE FAILED, multi len: %d\n",
-                                  priv->wmi->multi_write_idx);
+                        ath_dbg(common, ATH_DBG_WMI,
+                                "REGISTER WRITE FAILED, multi len: %d\n",
+                                priv->wmi->multi_write_idx);
                 }
                 priv->wmi->multi_write_idx = 0;
         }
@@ -378,15 +415,6 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv)
         atomic_inc(&priv->wmi->mwrite_cnt);
 }
 
-static void ath9k_disable_regwrite_buffer(void *hw_priv)
-{
-        struct ath_hw *ah = (struct ath_hw *) hw_priv;
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-        atomic_dec(&priv->wmi->mwrite_cnt);
-}
-
 static void ath9k_regwrite_flush(void *hw_priv)
 {
         struct ath_hw *ah = (struct ath_hw *) hw_priv;
@@ -395,6 +423,8 @@ static void ath9k_regwrite_flush(void *hw_priv)
         u32 rsp_status;
         int r;
 
+        atomic_dec(&priv->wmi->mwrite_cnt);
+
         mutex_lock(&priv->wmi->multi_write_mutex);
 
         if (priv->wmi->multi_write_idx) {
@@ -404,9 +434,9 @@ static void ath9k_regwrite_flush(void *hw_priv)
                           (u8 *) &rsp_status, sizeof(rsp_status),
                           100);
                 if (unlikely(r)) {
-                        ath_print(common, ATH_DBG_WMI,
-                                  "REGISTER WRITE FAILED, multi len: %d\n",
-                                  priv->wmi->multi_write_idx);
+                        ath_dbg(common, ATH_DBG_WMI,
+                                "REGISTER WRITE FAILED, multi len: %d\n",
+                                priv->wmi->multi_write_idx);
                 }
                 priv->wmi->multi_write_idx = 0;
         }
@@ -414,13 +444,16 @@ static void ath9k_regwrite_flush(void *hw_priv)
         mutex_unlock(&priv->wmi->multi_write_mutex);
 }
 
-static const struct ath_ops ath9k_common_ops = {
-        .read = ath9k_regread,
-        .write = ath9k_regwrite,
-        .enable_write_buffer = ath9k_enable_regwrite_buffer,
-        .disable_write_buffer = ath9k_disable_regwrite_buffer,
-        .write_flush = ath9k_regwrite_flush,
-};
+static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
+{
+        u32 val;
+
+        val = ath9k_regread(hw_priv, reg_offset);
+        val &= ~clr;
+        val |= set;
+        ath9k_regwrite(hw_priv, val, reg_offset);
+        return val;
+}
 
 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
 {
@@ -479,9 +512,9 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv,
         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "TX streams %d, RX streams: %d\n",
-                  tx_streams, rx_streams);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "TX streams %d, RX streams: %d\n",
+                tx_streams, rx_streams);
 
         if (tx_streams != rx_streams) {
                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -505,37 +538,31 @@ static int ath9k_init_queues(struct ath9k_htc_priv *priv)
 
         priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
         if (priv->beaconq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup BEACON xmit queue\n");
+                ath_err(common, "Unable to setup BEACON xmit queue\n");
                 goto err;
         }
 
         priv->cabq = ath9k_htc_cabq_setup(priv);
         if (priv->cabq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup CAB xmit queue\n");
+                ath_err(common, "Unable to setup CAB xmit queue\n");
                 goto err;
         }
 
         if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BE traffic\n");
+                ath_err(common, "Unable to setup xmit queue for BE traffic\n");
                 goto err;
         }
 
         if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BK traffic\n");
+                ath_err(common, "Unable to setup xmit queue for BK traffic\n");
                 goto err;
         }
         if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VI traffic\n");
+                ath_err(common, "Unable to setup xmit queue for VI traffic\n");
                 goto err;
         }
         if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VO traffic\n");
+                ath_err(common, "Unable to setup xmit queue for VO traffic\n");
                 goto err;
         }
 
@@ -551,25 +578,22 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
         int i = 0;
 
         /* Get the hardware key cache size. */
-        common->keymax = priv->ah->caps.keycache_size;
-        if (common->keymax > ATH_KEYMAX) {
-                ath_print(common, ATH_DBG_ANY,
-                          "Warning, using only %u entries in %u key cache\n",
-                          ATH_KEYMAX, common->keymax);
-                common->keymax = ATH_KEYMAX;
-        }
+        common->keymax = AR_KEYTABLE_SIZE;
+
+        if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
+                common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
 
         /*
          * Reset the key cache since some parts do not
          * reset the contents on initial power up.
          */
         for (i = 0; i < common->keymax; i++)
-                ath9k_hw_keyreset(priv->ah, (u16) i);
+                ath_hw_keyreset(common, (u16) i);
 }
 
 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
 {
-        if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
                 priv->sbands[IEEE80211_BAND_2GHZ].channels =
                         ath9k_2ghz_channels;
                 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
@@ -580,7 +604,7 @@ static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
                         ARRAY_SIZE(ath9k_legacy_rates);
         }
 
-        if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) {
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
                 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
                 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
                 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
@@ -599,17 +623,41 @@ static void ath9k_init_misc(struct ath9k_htc_priv *priv)
         common->tx_chainmask = priv->ah->caps.tx_chainmask;
         common->rx_chainmask = priv->ah->caps.rx_chainmask;
 
-        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
+        memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 
         priv->ah->opmode = NL80211_IFTYPE_STATION;
 }
 
-static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
+static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
+{
+        int qnum;
+
+        switch (priv->ah->btcoex_hw.scheme) {
+        case ATH_BTCOEX_CFG_NONE:
+                break;
+        case ATH_BTCOEX_CFG_3WIRE:
+                priv->ah->btcoex_hw.btactive_gpio = 7;
+                priv->ah->btcoex_hw.btpriority_gpio = 6;
+                priv->ah->btcoex_hw.wlanactive_gpio = 8;
+                priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
+                ath9k_hw_btcoex_init_3wire(priv->ah);
+                ath_htc_init_btcoex_work(priv);
+                qnum = priv->hwq_map[WME_AC_BE];
+                ath9k_hw_init_btcoex_hw(priv->ah, qnum);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+}
+
+static int ath9k_init_priv(struct ath9k_htc_priv *priv,
+                           u16 devid, char *product,
+                           u32 drv_info)
 {
         struct ath_hw *ah = NULL;
         struct ath_common *common;
-        int ret = 0, csz = 0;
+        int i, ret = 0, csz = 0;
 
         priv->op_flags |= OP_INVALID;
 
@@ -619,28 +667,37 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
 
         ah->hw_version.devid = devid;
         ah->hw_version.subsysid = 0; /* FIXME */
+        ah->hw_version.usbdev = drv_info;
+        ah->ah_flags |= AH_USE_EEPROM;
+        ah->reg_ops.read = ath9k_regread;
+        ah->reg_ops.multi_read = ath9k_multi_regread;
+        ah->reg_ops.write = ath9k_regwrite;
+        ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
+        ah->reg_ops.write_flush = ath9k_regwrite_flush;
+        ah->reg_ops.rmw = ath9k_reg_rmw;
         priv->ah = ah;
 
         common = ath9k_hw_common(ah);
-        common->ops = &ath9k_common_ops;
+        common->ops = &ah->reg_ops;
         common->bus_ops = &ath9k_usb_bus_ops;
         common->ah = ah;
         common->hw = priv->hw;
         common->priv = priv;
         common->debug_mask = ath9k_debug;
 
-        spin_lock_init(&priv->wmi->wmi_lock);
         spin_lock_init(&priv->beacon_lock);
-        spin_lock_init(&priv->tx_lock);
+        spin_lock_init(&priv->tx.tx_lock);
         mutex_init(&priv->mutex);
         mutex_init(&priv->htc_pm_lock);
-        tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
-                     (unsigned long)priv);
         tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
                      (unsigned long)priv);
-        tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
-        INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
+        tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
+                     (unsigned long)priv);
+        INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
         INIT_WORK(&priv->ps_work, ath9k_ps_work);
+        INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
+        setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
+                    (unsigned long)priv);
 
         /*
          * Cache line size is used to size and align various
@@ -651,32 +708,31 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
 
         ret = ath9k_hw_init(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize hardware; "
-                          "initialization status: %d\n", ret);
+                ath_err(common,
+                        "Unable to initialize hardware; initialization status: %d\n",
+                        ret);
                 goto err_hw;
         }
 
-        ret = ath9k_htc_init_debug(ah);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to create debugfs files\n");
-                goto err_debug;
-        }
-
         ret = ath9k_init_queues(priv);
         if (ret)
                 goto err_queues;
 
+        for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
+                priv->cur_beacon_conf.bslot[i] = NULL;
+
         ath9k_init_crypto(priv);
         ath9k_init_channels_rates(priv);
         ath9k_init_misc(priv);
 
+        if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
+                ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
+                ath9k_init_btcoex(priv);
+        }
+
         return 0;
 
 err_queues:
-        ath9k_htc_exit_debug(ah);
-err_debug:
         ath9k_hw_deinit(ah);
 err_hw:
 
@@ -697,17 +753,22 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
                 IEEE80211_HW_HAS_RATE_CONTROL |
                 IEEE80211_HW_RX_INCLUDES_FCS |
                 IEEE80211_HW_SUPPORTS_PS |
-                IEEE80211_HW_PS_NULLFUNC_STACK;
+                IEEE80211_HW_PS_NULLFUNC_STACK |
+                IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
 
         hw->wiphy->interface_modes =
                 BIT(NL80211_IFTYPE_STATION) |
-                BIT(NL80211_IFTYPE_ADHOC);
+                BIT(NL80211_IFTYPE_ADHOC) |
+                BIT(NL80211_IFTYPE_AP) |
+                BIT(NL80211_IFTYPE_P2P_GO) |
+                BIT(NL80211_IFTYPE_P2P_CLIENT);
 
         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 
         hw->queues = 4;
         hw->channel_change_time = 5000;
         hw->max_listen_interval = 10;
+
         hw->vif_data_size = sizeof(struct ath9k_htc_vif);
         hw->sta_data_size = sizeof(struct ath9k_htc_sta);
 
@@ -715,18 +776,18 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
         hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
                 sizeof(struct htc_frame_hdr) + 4;
 
-        if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &priv->sbands[IEEE80211_BAND_2GHZ];
-        if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
                         &priv->sbands[IEEE80211_BAND_5GHZ];
 
         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
-                if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
+                if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                         setup_ht_cap(priv,
                                      &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
-                if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
+                if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                         setup_ht_cap(priv,
                                      &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
         }
@@ -734,16 +795,55 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 }
 
-static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
+static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
+{
+        struct ieee80211_hw *hw = priv->hw;
+        struct wmi_fw_version cmd_rsp;
+        int ret;
+
+        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
+
+        WMI_CMD(WMI_GET_FW_VERSION);
+        if (ret)
+                return -EINVAL;
+
+        priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
+        priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
+
+        snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
+                 priv->fw_version_major,
+                 priv->fw_version_minor);
+
+        dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
+                 priv->fw_version_major,
+                 priv->fw_version_minor);
+
+        /*
+         * Check if the available FW matches the driver's
+         * required version.
+         */
+        if (priv->fw_version_major != MAJOR_VERSION_REQ ||
+            priv->fw_version_minor != MINOR_VERSION_REQ) {
+                dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
+                        MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int ath9k_init_device(struct ath9k_htc_priv *priv,
+                             u16 devid, char *product, u32 drv_info)
 {
         struct ieee80211_hw *hw = priv->hw;
         struct ath_common *common;
         struct ath_hw *ah;
         int error = 0;
         struct ath_regulatory *reg;
+        char hw_name[64];
 
         /* Bring up device */
-        error = ath9k_init_priv(priv, devid);
+        error = ath9k_init_priv(priv, devid, product, drv_info);
         if (error != 0)
                 goto err_init;
 
@@ -751,6 +851,10 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
         common = ath9k_hw_common(ah);
         ath9k_set_hw_capab(priv, hw);
 
+        error = ath9k_init_firmware_version(priv);
+        if (error != 0)
+                goto err_fw;
+
         /* Initialize regulatory */
         error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
                               ath9k_reg_notifier);
@@ -769,6 +873,13 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
         if (error != 0)
                 goto err_rx;
 
+#ifdef CONFIG_MAC80211_LEDS
+        /* must be initialized before ieee80211_register_hw */
+        priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
+                IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
+                ARRAY_SIZE(ath9k_htc_tpt_blink));
+#endif
+
         /* Register with mac80211 */
         error = ieee80211_register_hw(hw);
         if (error)
@@ -781,6 +892,28 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
                         goto err_world;
         }
 
+        error = ath9k_htc_init_debug(priv->ah);
+        if (error) {
+                ath_err(common, "Unable to create debugfs files\n");
+                goto err_world;
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, "
+                "BE:%d, BK:%d, VI:%d, VO:%d\n",
+                priv->wmi_cmd_ep,
+                priv->beacon_ep,
+                priv->cab_ep,
+                priv->uapsd_ep,
+                priv->mgmt_ep,
+                priv->data_be_ep,
+                priv->data_bk_ep,
+                priv->data_vi_ep,
+                priv->data_vo_ep);
+
+        ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
+        wiphy_info(hw->wiphy, "%s\n", hw_name);
+
         ath9k_init_leds(priv);
         ath9k_start_rfkill_poll(priv);
 
@@ -795,13 +928,15 @@ err_rx:
 err_tx:
         /* Nothing */
 err_regd:
+        /* Nothing */
+err_fw:
         ath9k_deinit_priv(priv);
 err_init:
         return error;
 }
 
 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
-                           u16 devid)
+                           u16 devid, char *product, u32 drv_info)
 {
         struct ieee80211_hw *hw;
         struct ath9k_htc_priv *priv;
@@ -828,14 +963,11 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
                 goto err_free;
         }
 
-        ret = ath9k_init_htc_services(priv, devid);
+        ret = ath9k_init_htc_services(priv, devid, drv_info);
         if (ret)
                 goto err_init;
 
-        /* The device may have been unplugged earlier. */
-        priv->op_flags &= ~OP_UNPLUGGED;
-
-        ret = ath9k_init_device(priv, devid);
+        ret = ath9k_init_device(priv, devid, product, drv_info);
         if (ret)
                 goto err_init;
 
@@ -854,7 +986,7 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 
                 /* Check if the device has been yanked out. */
                 if (hotunplug)
-                        htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
+                        htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
 
                 ath9k_deinit_device(htc_handle->drv_priv);
                 ath9k_deinit_wmi(htc_handle->drv_priv);
@@ -863,54 +995,43 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 }
 
 #ifdef CONFIG_PM
+
+void ath9k_htc_suspend(struct htc_target *htc_handle)
+{
+        ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
+}
+
 int ath9k_htc_resume(struct htc_target *htc_handle)
 {
+        struct ath9k_htc_priv *priv = htc_handle->drv_priv;
         int ret;
 
-        ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
+        ret = ath9k_htc_wait_for_target(priv);
         if (ret)
                 return ret;
 
-        ret = ath9k_init_htc_services(htc_handle->drv_priv,
-                              htc_handle->drv_priv->ah->hw_version.devid);
+        ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
+                                      priv->ah->hw_version.usbdev);
         return ret;
 }
 #endif
 
 static int __init ath9k_htc_init(void)
 {
-        int error;
-
-        error = ath9k_htc_debug_create_root();
-        if (error < 0) {
-                printk(KERN_ERR
-                        "ath9k_htc: Unable to create debugfs root: %d\n",
-                        error);
-                goto err_dbg;
-        }
-
-        error = ath9k_hif_usb_init();
-        if (error < 0) {
+        if (ath9k_hif_usb_init() < 0) {
                 printk(KERN_ERR
                         "ath9k_htc: No USB devices found,"
                         " driver not installed.\n");
-                error = -ENODEV;
-                goto err_usb;
+                return -ENODEV;
         }
 
         return 0;
-
-err_usb:
-        ath9k_htc_debug_remove_root();
-err_dbg:
-        return error;
 }
 module_init(ath9k_htc_init);
 
 static void __exit ath9k_htc_exit(void)
 {
         ath9k_hif_usb_exit();
-        ath9k_htc_debug_remove_root();
         printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
 }
 module_exit(ath9k_htc_exit);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 7d09b4b17bbd..7b7796895432 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,32 +16,17 @@
 
 #include "htc.h"
 
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-static struct dentry *ath9k_debugfs_root;
-#endif
-
 /*************/
 /* Utilities */
 /*************/
 
-static void ath_update_txpow(struct ath9k_htc_priv *priv)
-{
-        struct ath_hw *ah = priv->ah;
-
-        if (priv->curtxpow != priv->txpowlimit) {
-                ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit);
-                /* read back in case value is clamped */
-                priv->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
-        }
-}
-
 /* HACK Alert: Use 11NG for 2.4, use 11NA for 5 */
 static enum htc_phymode ath9k_htc_get_curmode(struct ath9k_htc_priv *priv,
                                               struct ath9k_channel *ichan)
 {
         enum htc_phymode mode;
 
-        mode = HTC_MODE_AUTO;
+        mode = -EINVAL;
 
         switch (ichan->chanmode) {
         case CHANNEL_G:
@@ -60,11 +45,13 @@ static enum htc_phymode ath9k_htc_get_curmode(struct ath9k_htc_priv *priv,
                 break;
         }
 
+        WARN_ON(mode < 0);
+
         return mode;
 }
 
-static bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
-                               enum ath9k_power_mode mode)
+bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
+                        enum ath9k_power_mode mode)
 {
         bool ret;
 
@@ -116,6 +103,138 @@ void ath9k_ps_work(struct work_struct *work)
         ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
 }
 
+static void ath9k_htc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_htc_priv *priv = data;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+
+        if ((vif->type == NL80211_IFTYPE_AP) && bss_conf->enable_beacon)
+                priv->reconfig_beacon = true;
+
+        if (bss_conf->assoc) {
+                priv->rearm_ani = true;
+                priv->reconfig_beacon = true;
+        }
+}
+
+static void ath9k_htc_vif_reconfig(struct ath9k_htc_priv *priv)
+{
+        priv->rearm_ani = false;
+        priv->reconfig_beacon = false;
+
+        ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                   ath9k_htc_vif_iter, priv);
+        if (priv->rearm_ani)
+                ath9k_htc_start_ani(priv);
+
+        if (priv->reconfig_beacon) {
+                ath9k_htc_ps_wakeup(priv);
+                ath9k_htc_beacon_reconfig(priv);
+                ath9k_htc_ps_restore(priv);
+        }
+}
+
+static void ath9k_htc_bssid_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_vif_iter_data *iter_data = data;
+        int i;
+
+        for (i = 0; i < ETH_ALEN; i++)
+                iter_data->mask[i] &= ~(iter_data->hw_macaddr[i] ^ mac[i]);
+}
+
+static void ath9k_htc_set_bssid_mask(struct ath9k_htc_priv *priv,
+                                     struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_vif_iter_data iter_data;
+
+        /*
+         * Use the hardware MAC address as reference, the hardware uses it
+         * together with the BSSID mask when matching addresses.
+         */
+        iter_data.hw_macaddr = common->macaddr;
+        memset(&iter_data.mask, 0xff, ETH_ALEN);
+
+        if (vif)
+                ath9k_htc_bssid_iter(&iter_data, vif->addr, vif);
+
+        /* Get list of all active MAC addresses */
+        ieee80211_iterate_active_interfaces_atomic(priv->hw, ath9k_htc_bssid_iter,
+                                                   &iter_data);
+
+        memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
+        ath_hw_setbssidmask(common);
+}
+
+static void ath9k_htc_set_opmode(struct ath9k_htc_priv *priv)
+{
+        if (priv->num_ibss_vif)
+                priv->ah->opmode = NL80211_IFTYPE_ADHOC;
+        else if (priv->num_ap_vif)
+                priv->ah->opmode = NL80211_IFTYPE_AP;
+        else
+                priv->ah->opmode = NL80211_IFTYPE_STATION;
+
+        ath9k_hw_setopmode(priv->ah);
+}
+
+void ath9k_htc_reset(struct ath9k_htc_priv *priv)
+{
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_channel *channel = priv->hw->conf.channel;
+        struct ath9k_hw_cal_data *caldata = NULL;
+        enum htc_phymode mode;
+        __be16 htc_mode;
+        u8 cmd_rsp;
+        int ret;
+
+        mutex_lock(&priv->mutex);
+        ath9k_htc_ps_wakeup(priv);
+
+        ath9k_htc_stop_ani(priv);
+        ieee80211_stop_queues(priv->hw);
+
+        del_timer_sync(&priv->tx.cleanup_timer);
+        ath9k_htc_tx_drain(priv);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
+        WMI_CMD(WMI_STOP_RECV_CMDID);
+
+        ath9k_wmi_event_drain(priv);
+
+        caldata = &priv->caldata;
+        ret = ath9k_hw_reset(ah, ah->curchan, caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset device (%u Mhz) reset status %d\n",
+                        channel->center_freq, ret);
+        }
+
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
+
+        WMI_CMD(WMI_START_RECV_CMDID);
+        ath9k_host_rx_init(priv);
+
+        mode = ath9k_htc_get_curmode(priv, ah->curchan);
+        htc_mode = cpu_to_be16(mode);
+        WMI_CMD_BUF(WMI_SET_MODE_CMDID, &htc_mode);
+
+        WMI_CMD(WMI_ENABLE_INTR_CMDID);
+        htc_start(priv->htc);
+        ath9k_htc_vif_reconfig(priv);
+        ieee80211_wake_queues(priv->hw);
+
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
+
+        ath9k_htc_ps_restore(priv);
+        mutex_unlock(&priv->mutex);
+}
+
 static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
                                  struct ieee80211_hw *hw,
                                  struct ath9k_channel *hchan)
@@ -123,9 +242,9 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_conf *conf = &common->hw->conf;
-        bool fastcc = true;
+        bool fastcc;
         struct ieee80211_channel *channel = hw->conf.channel;
-        struct ath9k_hw_cal_data *caldata;
+        struct ath9k_hw_cal_data *caldata = NULL;
         enum htc_phymode mode;
         __be16 htc_mode;
         u8 cmd_rsp;
@@ -134,32 +253,38 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         if (priv->op_flags & OP_INVALID)
                 return -EIO;
 
-        if (priv->op_flags & OP_FULL_RESET)
-                fastcc = false;
+        fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
 
-        /* Fiddle around with fastcc later on, for now just use full reset */
-        fastcc = false;
         ath9k_htc_ps_wakeup(priv);
-        htc_stop(priv->htc);
+
+        del_timer_sync(&priv->tx.cleanup_timer);
+        ath9k_htc_tx_drain(priv);
+
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
         WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
         WMI_CMD(WMI_STOP_RECV_CMDID);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "(%u MHz) -> (%u MHz), HT: %d, HT40: %d\n",
-                  priv->ah->curchan->channel,
-                  channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf));
+        ath9k_wmi_event_drain(priv);
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n",
+                priv->ah->curchan->channel,
+                channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf),
+                fastcc);
+
+        if (!fastcc)
+                caldata = &priv->caldata;
 
-        caldata = &priv->caldata[channel->hw_value];
         ret = ath9k_hw_reset(ah, hchan, caldata, fastcc);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u Mhz) "
-                          "reset status %d\n", channel->center_freq, ret);
+                ath_err(common,
+                        "Unable to reset channel (%u Mhz) reset status %d\n",
+                        channel->center_freq, ret);
                 goto err;
         }
 
-        ath_update_txpow(priv);
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
 
         WMI_CMD(WMI_START_RECV_CMDID);
         if (ret)
@@ -179,51 +304,159 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
 
         htc_start(priv->htc);
 
-        priv->op_flags &= ~OP_FULL_RESET;
+        if (!(priv->op_flags & OP_SCANNING) &&
+            !(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
+                ath9k_htc_vif_reconfig(priv);
+
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
+
 err:
         ath9k_htc_ps_restore(priv);
         return ret;
 }
 
-static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv)
+/*
+ * Monitor mode handling is a tad complicated because the firmware requires
+ * an interface to be created exclusively, while mac80211 doesn't associate
+ * an interface with the mode.
+ *
+ * So, for now, only one monitor interface can be configured.
+ */
+static void __ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         struct ath9k_htc_target_vif hvif;
         int ret = 0;
         u8 cmd_rsp;
 
-        if (priv->nvifs > 0)
-                return -ENOBUFS;
+        memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
+        memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
+        hvif.index = priv->mon_vif_idx;
+        WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
+        if (ret) {
+                ath_err(common, "Unable to remove monitor interface at idx: %d\n",
+                        priv->mon_vif_idx);
+        }
 
+        priv->nvifs--;
+        priv->vif_slot &= ~(1 << priv->mon_vif_idx);
+}
+
+static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_target_vif hvif;
+        struct ath9k_htc_target_sta tsta;
+        int ret = 0, sta_idx;
+        u8 cmd_rsp;
+
+        if ((priv->nvifs >= ATH9K_HTC_MAX_VIF) ||
+            (priv->nstations >= ATH9K_HTC_MAX_STA)) {
+                ret = -ENOBUFS;
+                goto err_vif;
+        }
+
+        sta_idx = ffz(priv->sta_slot);
+        if ((sta_idx < 0) || (sta_idx > ATH9K_HTC_MAX_STA)) {
+                ret = -ENOBUFS;
+                goto err_vif;
+        }
+
+        /*
+         * Add an interface.
+         */
         memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
         memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
 
-        hvif.opmode = cpu_to_be32(HTC_M_MONITOR);
-        priv->ah->opmode = NL80211_IFTYPE_MONITOR;
-        hvif.index = priv->nvifs;
+        hvif.opmode = HTC_M_MONITOR;
+        hvif.index = ffz(priv->vif_slot);
 
         WMI_CMD_BUF(WMI_VAP_CREATE_CMDID, &hvif);
         if (ret)
-                return ret;
+                goto err_vif;
+
+        /*
+         * Assign the monitor interface index as a special case here.
+         * This is needed when the interface is brought down.
+         */
+        priv->mon_vif_idx = hvif.index;
+        priv->vif_slot |= (1 << hvif.index);
+
+        /*
+         * Set the hardware mode to monitor only if there are no
+         * other interfaces.
+         */
+        if (!priv->nvifs)
+                priv->ah->opmode = NL80211_IFTYPE_MONITOR;
 
         priv->nvifs++;
+
+        /*
+         * Associate a station with the interface for packet injection.
+         */
+        memset(&tsta, 0, sizeof(struct ath9k_htc_target_sta));
+
+        memcpy(&tsta.macaddr, common->macaddr, ETH_ALEN);
+
+        tsta.is_vif_sta = 1;
+        tsta.sta_index = sta_idx;
+        tsta.vif_index = hvif.index;
+        tsta.maxampdu = cpu_to_be16(0xffff);
+
+        WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
+        if (ret) {
+                ath_err(common, "Unable to add station entry for monitor mode\n");
+                goto err_sta;
+        }
+
+        priv->sta_slot |= (1 << sta_idx);
+        priv->nstations++;
+        priv->vif_sta_pos[priv->mon_vif_idx] = sta_idx;
+        priv->ah->is_monitoring = true;
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attached a monitor interface at idx: %d, sta idx: %d\n",
+                priv->mon_vif_idx, sta_idx);
+
         return 0;
+
+err_sta:
+        /*
+         * Remove the interface from the target.
+         */
+        __ath9k_htc_remove_monitor_interface(priv);
+err_vif:
+        ath_dbg(common, ATH_DBG_FATAL, "Unable to attach a monitor interface\n");
+
+        return ret;
 }
 
 static int ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct ath9k_htc_target_vif hvif;
         int ret = 0;
-        u8 cmd_rsp;
+        u8 cmd_rsp, sta_idx;
 
-        memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
-        memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
-        hvif.index = 0; /* Should do for now */
-        WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
-        priv->nvifs--;
+        __ath9k_htc_remove_monitor_interface(priv);
 
-        return ret;
+        sta_idx = priv->vif_sta_pos[priv->mon_vif_idx];
+
+        WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
+        if (ret) {
+                ath_err(common, "Unable to remove station entry for monitor mode\n");
+                return ret;
+        }
+
+        priv->sta_slot &= ~(1 << sta_idx);
+        priv->nstations--;
+        priv->ah->is_monitoring = false;
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Removed a monitor interface at idx: %d, sta idx: %d\n",
+                priv->mon_vif_idx, sta_idx);
+
+        return 0;
 }
 
 static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
@@ -234,47 +467,65 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
         struct ath9k_htc_target_sta tsta;
         struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
         struct ath9k_htc_sta *ista;
-        int ret;
+        int ret, sta_idx;
         u8 cmd_rsp;
+        u16 maxampdu;
 
         if (priv->nstations >= ATH9K_HTC_MAX_STA)
                 return -ENOBUFS;
 
+        sta_idx = ffz(priv->sta_slot);
+        if ((sta_idx < 0) || (sta_idx > ATH9K_HTC_MAX_STA))
+                return -ENOBUFS;
+
         memset(&tsta, 0, sizeof(struct ath9k_htc_target_sta));
 
         if (sta) {
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
                 memcpy(&tsta.macaddr, sta->addr, ETH_ALEN);
                 memcpy(&tsta.bssid, common->curbssid, ETH_ALEN);
-                tsta.associd = common->curaid;
                 tsta.is_vif_sta = 0;
-                tsta.valid = true;
-                ista->index = priv->nstations;
+                ista->index = sta_idx;
         } else {
                 memcpy(&tsta.macaddr, vif->addr, ETH_ALEN);
                 tsta.is_vif_sta = 1;
         }
 
-        tsta.sta_index = priv->nstations;
+        tsta.sta_index = sta_idx;
         tsta.vif_index = avp->index;
-        tsta.maxampdu = 0xffff;
-        if (sta && sta->ht_cap.ht_supported)
-                tsta.flags = cpu_to_be16(ATH_HTC_STA_HT);
+
+        if (!sta) {
+                tsta.maxampdu = cpu_to_be16(0xffff);
+        } else {
+                maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
+                                 sta->ht_cap.ampdu_factor);
+                tsta.maxampdu = cpu_to_be16(maxampdu);
+        }
 
         WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
         if (ret) {
                 if (sta)
-                        ath_print(common, ATH_DBG_FATAL,
-                          "Unable to add station entry for: %pM\n", sta->addr);
+                        ath_err(common,
+                                "Unable to add station entry for: %pM\n",
+                                sta->addr);
                 return ret;
         }
 
-        if (sta)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Added a station entry for: %pM (idx: %d)\n",
-                          sta->addr, tsta.sta_index);
+        if (sta) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Added a station entry for: %pM (idx: %d)\n",
+                        sta->addr, tsta.sta_index);
+        } else {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Added a station entry for VIF %d (idx: %d)\n",
+                        avp->index, tsta.sta_index);
+        }
 
+        priv->sta_slot |= (1 << sta_idx);
         priv->nstations++;
+        if (!sta)
+                priv->vif_sta_pos[avp->index] = sta_idx;
+
         return 0;
 }
 
@@ -283,6 +534,7 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv,
                                     struct ieee80211_sta *sta)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_vif *avp = (struct ath9k_htc_vif *) vif->drv_priv;
         struct ath9k_htc_sta *ista;
         int ret;
         u8 cmd_rsp, sta_idx;
@@ -291,28 +543,36 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv,
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
                 sta_idx = ista->index;
         } else {
-                sta_idx = 0;
+                sta_idx = priv->vif_sta_pos[avp->index];
         }
 
         WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
         if (ret) {
                 if (sta)
-                        ath_print(common, ATH_DBG_FATAL,
-                          "Unable to remove station entry for: %pM\n",
-                          sta->addr);
+                        ath_err(common,
+                                "Unable to remove station entry for: %pM\n",
+                                sta->addr);
                 return ret;
         }
 
-        if (sta)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Removed a station entry for: %pM (idx: %d)\n",
-                          sta->addr, sta_idx);
+        if (sta) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Removed a station entry for: %pM (idx: %d)\n",
+                        sta->addr, sta_idx);
+        } else {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Removed a station entry for VIF %d (idx: %d)\n",
+                        avp->index, sta_idx);
+        }
 
+        priv->sta_slot &= ~(1 << sta_idx);
         priv->nstations--;
+
         return 0;
 }
 
-static int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv)
+int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv,
+                                u8 enable_coex)
 {
         struct ath9k_htc_cap_target tcap;
         int ret;
@@ -320,13 +580,9 @@ static int ath9k_htc_update_cap_target(struct ath9k_htc_priv *priv)
 
         memset(&tcap, 0, sizeof(struct ath9k_htc_cap_target));
 
-        /* FIXME: Values are hardcoded */
-        tcap.flags = 0x240c40;
-        tcap.flags_ext = 0x80601000;
-        tcap.ampdu_limit = 0xffff0000;
-        tcap.ampdu_subframes = 20;
-        tcap.tx_chainmask_legacy = priv->ah->caps.tx_chainmask;
-        tcap.protmode = 1;
+        tcap.ampdu_limit = cpu_to_be32(0xffff);
+        tcap.ampdu_subframes = 0xff;
+        tcap.enable_coex = enable_coex;
         tcap.tx_chainmask = priv->ah->caps.tx_chainmask;
 
         WMI_CMD_BUF(WMI_TARGET_IC_UPDATE_CMDID, &tcap);
@@ -391,8 +647,8 @@ static int ath9k_htc_send_rate_cmd(struct ath9k_htc_priv *priv,
 
         WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, trate);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize Rate information on target\n");
+                ath_err(common,
+                        "Unable to initialize Rate information on target\n");
         }
 
         return ret;
@@ -409,9 +665,9 @@ static void ath9k_htc_init_rate(struct ath9k_htc_priv *priv,
         ath9k_htc_setup_rate(priv, sta, &trate);
         ret = ath9k_htc_send_rate_cmd(priv, &trate);
         if (!ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Updated target sta: %pM, rate caps: 0x%X\n",
-                          sta->addr, be32_to_cpu(trate.capflags));
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Updated target sta: %pM, rate caps: 0x%X\n",
+                        sta->addr, be32_to_cpu(trate.capflags));
 }
 
 static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
@@ -436,9 +692,9 @@ static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
 
         ret = ath9k_htc_send_rate_cmd(priv, &trate);
         if (!ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Updated target sta: %pM, rate caps: 0x%X\n",
-                          bss_conf->bssid, be32_to_cpu(trate.capflags));
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Updated target sta: %pM, rate caps: 0x%X\n",
+                        bss_conf->bssid, be32_to_cpu(trate.capflags));
 }
 
 static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
@@ -465,229 +721,27 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
 
         WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr);
         if (ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unable to %s TX aggregation for (%pM, %d)\n",
-                          (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unable to %s TX aggregation for (%pM, %d)\n",
+                        (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
         else
-                ath_print(common, ATH_DBG_CONFIG,
-                          "%s TX aggregation for (%pM, %d)\n",
-                          (aggr.aggr_enable) ? "Starting" : "Stopping",
-                          sta->addr, tid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "%s TX aggregation for (%pM, %d)\n",
+                        (aggr.aggr_enable) ? "Starting" : "Stopping",
+                        sta->addr, tid);
 
-        spin_lock_bh(&priv->tx_lock);
+        spin_lock_bh(&priv->tx.tx_lock);
         ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP;
-        spin_unlock_bh(&priv->tx_lock);
+        spin_unlock_bh(&priv->tx.tx_lock);
 
         return ret;
 }
 
-/*********/
-/* DEBUG */
-/*********/
-
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-
-static int ath9k_debugfs_open(struct inode *inode, struct file *file)
-{
-        file->private_data = inode->i_private;
-        return 0;
-}
-
-static ssize_t read_file_tgt_stats(struct file *file, char __user *user_buf,
-                                   size_t count, loff_t *ppos)
-{
-        struct ath9k_htc_priv *priv = file->private_data;
-        struct ath9k_htc_target_stats cmd_rsp;
-        char buf[512];
-        unsigned int len = 0;
-        int ret = 0;
-
-        memset(&cmd_rsp, 0, sizeof(cmd_rsp));
-
-        WMI_CMD(WMI_TGT_STATS_CMDID);
-        if (ret)
-                return -EINVAL;
-
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Short Retries",
-                        be32_to_cpu(cmd_rsp.tx_shortretry));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Long Retries",
-                        be32_to_cpu(cmd_rsp.tx_longretry));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Xretries",
-                        be32_to_cpu(cmd_rsp.tx_xretries));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Unaggr. Xretries",
-                        be32_to_cpu(cmd_rsp.ht_txunaggr_xretry));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Xretries (HT)",
-                        be32_to_cpu(cmd_rsp.ht_tx_xretries));
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%19s : %10u\n", "TX Rate", priv->debug.txrate);
-
-        if (len > sizeof(buf))
-                len = sizeof(buf);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
-static const struct file_operations fops_tgt_stats = {
-        .read = read_file_tgt_stats,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
-                              size_t count, loff_t *ppos)
-{
-        struct ath9k_htc_priv *priv = file->private_data;
-        char buf[512];
-        unsigned int len = 0;
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "Buffers queued",
-                        priv->debug.tx_stats.buf_queued);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "Buffers completed",
-                        priv->debug.tx_stats.buf_completed);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs queued",
-                        priv->debug.tx_stats.skb_queued);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs completed",
-                        priv->debug.tx_stats.skb_completed);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs dropped",
-                        priv->debug.tx_stats.skb_dropped);
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "BE queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_BE]);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "BK queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_BK]);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "VI queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_VI]);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "VO queued",
-                        priv->debug.tx_stats.queue_stats[WME_AC_VO]);
-
-        if (len > sizeof(buf))
-                len = sizeof(buf);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
-static const struct file_operations fops_xmit = {
-        .read = read_file_xmit,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-static ssize_t read_file_recv(struct file *file, char __user *user_buf,
-                              size_t count, loff_t *ppos)
-{
-        struct ath9k_htc_priv *priv = file->private_data;
-        char buf[512];
-        unsigned int len = 0;
-
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs allocated",
-                        priv->debug.rx_stats.skb_allocated);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs completed",
-                        priv->debug.rx_stats.skb_completed);
-        len += snprintf(buf + len, sizeof(buf) - len,
-                        "%20s : %10u\n", "SKBs Dropped",
-                        priv->debug.rx_stats.skb_dropped);
-
-        if (len > sizeof(buf))
-                len = sizeof(buf);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
-static const struct file_operations fops_recv = {
-        .read = read_file_recv,
-        .open = ath9k_debugfs_open,
-        .owner = THIS_MODULE
-};
-
-int ath9k_htc_init_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
-
-        priv->debug.debugfs_phy = debugfs_create_dir(wiphy_name(priv->hw->wiphy),
-                                                     ath9k_debugfs_root);
-        if (!priv->debug.debugfs_phy)
-                goto err;
-
-        priv->debug.debugfs_tgt_stats = debugfs_create_file("tgt_stats", S_IRUSR,
-                                                    priv->debug.debugfs_phy,
-                                                    priv, &fops_tgt_stats);
-        if (!priv->debug.debugfs_tgt_stats)
-                goto err;
-
-
-        priv->debug.debugfs_xmit = debugfs_create_file("xmit", S_IRUSR,
-                                                       priv->debug.debugfs_phy,
-                                                       priv, &fops_xmit);
-        if (!priv->debug.debugfs_xmit)
-                goto err;
-
-        priv->debug.debugfs_recv = debugfs_create_file("recv", S_IRUSR,
-                                                       priv->debug.debugfs_phy,
-                                                       priv, &fops_recv);
-        if (!priv->debug.debugfs_recv)
-                goto err;
-
-        return 0;
-
-err:
-        ath9k_htc_exit_debug(ah);
-        return -ENOMEM;
-}
-
-void ath9k_htc_exit_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-        debugfs_remove(priv->debug.debugfs_recv);
-        debugfs_remove(priv->debug.debugfs_xmit);
-        debugfs_remove(priv->debug.debugfs_tgt_stats);
-        debugfs_remove(priv->debug.debugfs_phy);
-}
-
-int ath9k_htc_debug_create_root(void)
-{
-        ath9k_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
-
-        return 0;
-}
-
-void ath9k_htc_debug_remove_root(void)
-{
-        debugfs_remove(ath9k_debugfs_root);
-        ath9k_debugfs_root = NULL;
-}
-
-#endif /* CONFIG_ATH9K_HTC_DEBUGFS */
-
 /*******/
 /* ANI */
 /*******/
 
-static void ath_start_ani(struct ath9k_htc_priv *priv)
+void ath9k_htc_start_ani(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         unsigned long timestamp = jiffies_to_msecs(jiffies);
@@ -696,15 +750,22 @@ static void ath_start_ani(struct ath9k_htc_priv *priv)
         common->ani.shortcal_timer = timestamp;
         common->ani.checkani_timer = timestamp;
 
-        ieee80211_queue_delayed_work(common->hw, &priv->ath9k_ani_work,
+        priv->op_flags |= OP_ANI_RUNNING;
+
+        ieee80211_queue_delayed_work(common->hw, &priv->ani_work,
                                      msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 }
 
-void ath9k_ani_work(struct work_struct *work)
+void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv)
+{
+        cancel_delayed_work_sync(&priv->ani_work);
+        priv->op_flags &= ~OP_ANI_RUNNING;
+}
+
+void ath9k_htc_ani_work(struct work_struct *work)
 {
         struct ath9k_htc_priv *priv =
-                container_of(work, struct ath9k_htc_priv,
-                             ath9k_ani_work.work);
+                container_of(work, struct ath9k_htc_priv, ani_work.work);
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
         bool longcal = false;
@@ -713,7 +774,8 @@ void ath9k_ani_work(struct work_struct *work)
         unsigned int timestamp = jiffies_to_msecs(jiffies);
         u32 cal_interval, short_cal_interval;
 
-        short_cal_interval = ATH_STA_SHORT_CALINTERVAL;
+        short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
+                ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 
         /* Only calibrate if awake */
         if (ah->power_mode != ATH9K_PM_AWAKE)
@@ -722,7 +784,7 @@ void ath9k_ani_work(struct work_struct *work)
         /* Long calibration runs independently of short calibration. */
         if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
                 longcal = true;
-                ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
+                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -731,8 +793,8 @@ void ath9k_ani_work(struct work_struct *work)
                 if ((timestamp - common->ani.shortcal_timer) >=
                     short_cal_interval) {
                         shortcal = true;
-                        ath_print(common, ATH_DBG_ANI,
-                                  "shortcal @%lu\n", jiffies);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -761,23 +823,12 @@ void ath9k_ani_work(struct work_struct *work)
                         ath9k_hw_ani_monitor(ah, ah->curchan);
 
                 /* Perform calibration if necessary */
-                if (longcal || shortcal) {
+                if (longcal || shortcal)
                         common->ani.caldone =
                                 ath9k_hw_calibrate(ah, ah->curchan,
                                                    common->rx_chainmask,
                                                    longcal);
 
-                        if (longcal)
-                                common->ani.noise_floor =
-                                        ath9k_hw_getchan_noise(ah, ah->curchan);
-
-                        ath_print(common, ATH_DBG_ANI,
-                                  " calibrate chan %u/%x nf: %d\n",
-                                  ah->curchan->channel,
-                                  ah->curchan->channelFlags,
-                                  common->ani.noise_floor);
-                }
-
                 ath9k_htc_ps_restore(priv);
         }
 
@@ -793,330 +844,20 @@ set_timer:
         if (!common->ani.caldone)
                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 
-        ieee80211_queue_delayed_work(common->hw, &priv->ath9k_ani_work,
+        ieee80211_queue_delayed_work(common->hw, &priv->ani_work,
                                      msecs_to_jiffies(cal_interval));
 }
 
-/*******/
-/* LED */
-/*******/
-
-static void ath9k_led_blink_work(struct work_struct *work)
-{
-        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
-                                                   ath9k_led_blink_work.work);
-
-        if (!(priv->op_flags & OP_LED_ASSOCIATED))
-                return;
-
-        if ((priv->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
-            (priv->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
-                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
-        else
-                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
-                                  (priv->op_flags & OP_LED_ON) ? 1 : 0);
-
-        ieee80211_queue_delayed_work(priv->hw,
-                                     &priv->ath9k_led_blink_work,
-                                     (priv->op_flags & OP_LED_ON) ?
-                                     msecs_to_jiffies(priv->led_off_duration) :
-                                     msecs_to_jiffies(priv->led_on_duration));
-
-        priv->led_on_duration = priv->led_on_cnt ?
-                max((ATH_LED_ON_DURATION_IDLE - priv->led_on_cnt), 25) :
-                ATH_LED_ON_DURATION_IDLE;
-        priv->led_off_duration = priv->led_off_cnt ?
-                max((ATH_LED_OFF_DURATION_IDLE - priv->led_off_cnt), 10) :
-                ATH_LED_OFF_DURATION_IDLE;
-        priv->led_on_cnt = priv->led_off_cnt = 0;
-
-        if (priv->op_flags & OP_LED_ON)
-                priv->op_flags &= ~OP_LED_ON;
-        else
-                priv->op_flags |= OP_LED_ON;
-}
-
-static void ath9k_led_brightness_work(struct work_struct *work)
-{
-        struct ath_led *led = container_of(work, struct ath_led,
-                                           brightness_work.work);
-        struct ath9k_htc_priv *priv = led->priv;
-
-        switch (led->brightness) {
-        case LED_OFF:
-                if (led->led_type == ATH_LED_ASSOC ||
-                    led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
-                                          (led->led_type == ATH_LED_RADIO));
-                        priv->op_flags &= ~OP_LED_ASSOCIATED;
-                        if (led->led_type == ATH_LED_RADIO)
-                                priv->op_flags &= ~OP_LED_ON;
-                } else {
-                        priv->led_off_cnt++;
-                }
-                break;
-        case LED_FULL:
-                if (led->led_type == ATH_LED_ASSOC) {
-                        priv->op_flags |= OP_LED_ASSOCIATED;
-                        ieee80211_queue_delayed_work(priv->hw,
-                                             &priv->ath9k_led_blink_work, 0);
-                } else if (led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
-                        priv->op_flags |= OP_LED_ON;
-                } else {
-                        priv->led_on_cnt++;
-                }
-                break;
-        default:
-                break;
-        }
-}
-
-static void ath9k_led_brightness(struct led_classdev *led_cdev,
-                                 enum led_brightness brightness)
-{
-        struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
-        struct ath9k_htc_priv *priv = led->priv;
-
-        led->brightness = brightness;
-        if (!(priv->op_flags & OP_LED_DEINIT))
-                ieee80211_queue_delayed_work(priv->hw,
-                                             &led->brightness_work, 0);
-}
-
-static void ath9k_led_stop_brightness(struct ath9k_htc_priv *priv)
-{
-        cancel_delayed_work_sync(&priv->radio_led.brightness_work);
-        cancel_delayed_work_sync(&priv->assoc_led.brightness_work);
-        cancel_delayed_work_sync(&priv->tx_led.brightness_work);
-        cancel_delayed_work_sync(&priv->rx_led.brightness_work);
-}
-
-static int ath9k_register_led(struct ath9k_htc_priv *priv, struct ath_led *led,
-                              char *trigger)
-{
-        int ret;
-
-        led->priv = priv;
-        led->led_cdev.name = led->name;
-        led->led_cdev.default_trigger = trigger;
-        led->led_cdev.brightness_set = ath9k_led_brightness;
-
-        ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &led->led_cdev);
-        if (ret)
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL,
-                          "Failed to register led:%s", led->name);
-        else
-                led->registered = 1;
-
-        INIT_DELAYED_WORK(&led->brightness_work, ath9k_led_brightness_work);
-
-        return ret;
-}
-
-static void ath9k_unregister_led(struct ath_led *led)
-{
-        if (led->registered) {
-                led_classdev_unregister(&led->led_cdev);
-                led->registered = 0;
-        }
-}
-
-void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
-{
-        priv->op_flags |= OP_LED_DEINIT;
-        ath9k_unregister_led(&priv->assoc_led);
-        priv->op_flags &= ~OP_LED_ASSOCIATED;
-        ath9k_unregister_led(&priv->tx_led);
-        ath9k_unregister_led(&priv->rx_led);
-        ath9k_unregister_led(&priv->radio_led);
-}
-
-void ath9k_init_leds(struct ath9k_htc_priv *priv)
-{
-        char *trigger;
-        int ret;
-
-        if (AR_SREV_9287(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_9287;
-        else if (AR_SREV_9271(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_9271;
-        else if (AR_DEVID_7010(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_7010;
-        else
-                priv->ah->led_pin = ATH_LED_PIN_DEF;
-
-        /* Configure gpio 1 for output */
-        ath9k_hw_cfg_output(priv->ah, priv->ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        /* LED off, active low */
-        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
-
-        INIT_DELAYED_WORK(&priv->ath9k_led_blink_work, ath9k_led_blink_work);
-
-        trigger = ieee80211_get_radio_led_name(priv->hw);
-        snprintf(priv->radio_led.name, sizeof(priv->radio_led.name),
-                "ath9k-%s::radio", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->radio_led, trigger);
-        priv->radio_led.led_type = ATH_LED_RADIO;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_assoc_led_name(priv->hw);
-        snprintf(priv->assoc_led.name, sizeof(priv->assoc_led.name),
-                "ath9k-%s::assoc", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->assoc_led, trigger);
-        priv->assoc_led.led_type = ATH_LED_ASSOC;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_tx_led_name(priv->hw);
-        snprintf(priv->tx_led.name, sizeof(priv->tx_led.name),
-                "ath9k-%s::tx", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->tx_led, trigger);
-        priv->tx_led.led_type = ATH_LED_TX;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_rx_led_name(priv->hw);
-        snprintf(priv->rx_led.name, sizeof(priv->rx_led.name),
-                "ath9k-%s::rx", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->rx_led, trigger);
-        priv->rx_led.led_type = ATH_LED_RX;
-        if (ret)
-                goto fail;
-
-        priv->op_flags &= ~OP_LED_DEINIT;
-
-        return;
-
-fail:
-        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
-        ath9k_deinit_leds(priv);
-}
-
-/*******************/
-/*      Rfkill     */
-/*******************/
-
-static bool ath_is_rfkill_set(struct ath9k_htc_priv *priv)
-{
-        return ath9k_hw_gpio_get(priv->ah, priv->ah->rfkill_gpio) ==
-                priv->ah->rfkill_polarity;
-}
-
-static void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        bool blocked = !!ath_is_rfkill_set(priv);
-
-        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
-}
-
-void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
-{
-        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
-                wiphy_rfkill_start_polling(priv->hw->wiphy);
-}
-
-static void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        int ret;
-        u8 cmd_rsp;
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        /* Reset the HW */
-        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, ah->curchan->channel);
-        }
-
-        ath_update_txpow(priv);
-
-        /* Start RX */
-        WMI_CMD(WMI_START_RECV_CMDID);
-        ath9k_host_rx_init(priv);
-
-        /* Start TX */
-        htc_start(priv->htc);
-        spin_lock_bh(&priv->tx_lock);
-        priv->tx_queues_stop = false;
-        spin_unlock_bh(&priv->tx_lock);
-        ieee80211_wake_queues(hw);
-
-        WMI_CMD(WMI_ENABLE_INTR_CMDID);
-
-        /* Enable LED */
-        ath9k_hw_cfg_output(ah, ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
-}
-
-static void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        int ret;
-        u8 cmd_rsp;
-
-        ath9k_htc_ps_wakeup(priv);
-
-        /* Disable LED */
-        ath9k_hw_set_gpio(ah, ah->led_pin, 1);
-        ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
-
-        WMI_CMD(WMI_DISABLE_INTR_CMDID);
-
-        /* Stop TX */
-        ieee80211_stop_queues(hw);
-        htc_stop(priv->htc);
-        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
-        skb_queue_purge(&priv->tx_queue);
-
-        /* Stop RX */
-        WMI_CMD(WMI_STOP_RECV_CMDID);
-
-        /*
-         * The MIB counters have to be disabled here,
-         * since the target doesn't do it.
-         */
-        ath9k_hw_disable_mib_counters(ah);
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        /* Reset the HW */
-        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, ah->curchan->channel);
-        }
-
-        /* Disable the PHY */
-        ath9k_hw_phy_disable(ah);
-
-        ath9k_htc_ps_restore(priv);
-        ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
-}
-
 /**********************/
 /* mac80211 Callbacks */
 /**********************/
 
-static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+static void ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 {
         struct ieee80211_hdr *hdr;
         struct ath9k_htc_priv *priv = hw->priv;
-        int padpos, padsize, ret;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        int padpos, padsize, ret, slot;
 
         hdr = (struct ieee80211_hdr *) skb->data;
 
@@ -1124,33 +865,34 @@ static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         padpos = ath9k_cmn_padpos(hdr->frame_control);
         padsize = padpos & 3;
         if (padsize && skb->len > padpos) {
-                if (skb_headroom(skb) < padsize)
-                        return -1;
+                if (skb_headroom(skb) < padsize) {
+                        ath_dbg(common, ATH_DBG_XMIT, "No room for padding\n");
+                        goto fail_tx;
+                }
                 skb_push(skb, padsize);
                 memmove(skb->data, skb->data + padsize, padpos);
         }
 
-        ret = ath9k_htc_tx_start(priv, skb);
-        if (ret != 0) {
-                if (ret == -ENOMEM) {
-                        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                                  "Stopping TX queues\n");
-                        ieee80211_stop_queues(hw);
-                        spin_lock_bh(&priv->tx_lock);
-                        priv->tx_queues_stop = true;
-                        spin_unlock_bh(&priv->tx_lock);
-                } else {
-                        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                                  "Tx failed");
-                }
+        slot = ath9k_htc_tx_get_slot(priv);
+        if (slot < 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "No free TX slot\n");
                 goto fail_tx;
         }
 
-        return 0;
+        ret = ath9k_htc_tx_start(priv, skb, slot, false);
+        if (ret != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "Tx failed\n");
+                goto clear_slot;
+        }
+
+        ath9k_htc_check_stop_queues(priv);
+
+        return;
 
+clear_slot:
+        ath9k_htc_tx_clear_slot(priv, slot);
 fail_tx:
         dev_kfree_skb_any(skb);
-        return 0;
 }
 
 static int ath9k_htc_start(struct ieee80211_hw *hw)
@@ -1167,9 +909,9 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
 
         mutex_lock(&priv->mutex);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Starting driver with initial channel: %d MHz\n",
-                  curchan->center_freq);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Starting driver with initial channel: %d MHz\n",
+                curchan->center_freq);
 
         /* Ensure that HW is awake before flushing RX */
         ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
@@ -1178,20 +920,18 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
         /* setup initial channel */
         init_channel = ath9k_cmn_get_curchannel(hw, ah);
 
-        /* Reset SERDES registers */
-        ath9k_hw_configpcipowersave(ah, 0, 0);
-
         ath9k_hw_htc_resetinit(ah);
         ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, curchan->center_freq);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, curchan->center_freq);
                 mutex_unlock(&priv->mutex);
                 return ret;
         }
 
-        ath_update_txpow(priv);
+        ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
+                               &priv->curtxpow);
 
         mode = ath9k_htc_get_curmode(priv, init_channel);
         htc_mode = cpu_to_be16(mode);
@@ -1201,15 +941,29 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
 
         ath9k_host_rx_init(priv);
 
+        ret = ath9k_htc_update_cap_target(priv, 0);
+        if (ret)
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Failed to update capability in target\n");
+
         priv->op_flags &= ~OP_INVALID;
         htc_start(priv->htc);
 
-        spin_lock_bh(&priv->tx_lock);
-        priv->tx_queues_stop = false;
-        spin_unlock_bh(&priv->tx_lock);
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
+        spin_unlock_bh(&priv->tx.tx_lock);
 
         ieee80211_wake_queues(hw);
 
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
+
+        if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) {
+                ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
+                                           AR_STOMP_LOW_WLAN_WGHT);
+                ath9k_hw_btcoex_enable(ah);
+                ath_htc_resume_btcoex_work(priv);
+        }
         mutex_unlock(&priv->mutex);
 
         return ret;
@@ -1220,49 +974,60 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
         struct ath9k_htc_priv *priv = hw->priv;
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
-        int ret = 0;
+        int ret __attribute__ ((unused));
         u8 cmd_rsp;
 
         mutex_lock(&priv->mutex);
 
         if (priv->op_flags & OP_INVALID) {
-                ath_print(common, ATH_DBG_ANY, "Device not present\n");
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&priv->mutex);
                 return;
         }
 
-        /* Cancel all the running timers/work .. */
-        cancel_work_sync(&priv->ps_work);
-        cancel_delayed_work_sync(&priv->ath9k_ani_work);
-        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
-        ath9k_led_stop_brightness(priv);
-
         ath9k_htc_ps_wakeup(priv);
-        htc_stop(priv->htc);
+
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
         WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
         WMI_CMD(WMI_STOP_RECV_CMDID);
-        skb_queue_purge(&priv->tx_queue);
 
-        /* Remove monitor interface here */
-        if (ah->opmode == NL80211_IFTYPE_MONITOR) {
-                if (ath9k_htc_remove_monitor_interface(priv))
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to remove monitor interface\n");
-                else
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "Monitor interface removed\n");
+        tasklet_kill(&priv->rx_tasklet);
+
+        del_timer_sync(&priv->tx.cleanup_timer);
+        ath9k_htc_tx_drain(priv);
+        ath9k_wmi_event_drain(priv);
+
+        mutex_unlock(&priv->mutex);
+
+        /* Cancel all the running timers/work .. */
+        cancel_work_sync(&priv->fatal_work);
+        cancel_work_sync(&priv->ps_work);
+
+#ifdef CONFIG_MAC80211_LEDS
+        cancel_work_sync(&priv->led_work);
+#endif
+        ath9k_htc_stop_ani(priv);
+
+        mutex_lock(&priv->mutex);
+
+        if (ah->btcoex_hw.enabled) {
+                ath9k_hw_btcoex_disable(ah);
+                if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
+                        ath_htc_cancel_btcoex_work(priv);
         }
 
+        /* Remove a monitor interface if it's present. */
+        if (priv->ah->is_monitoring)
+                ath9k_htc_remove_monitor_interface(priv);
+
         ath9k_hw_phy_disable(ah);
         ath9k_hw_disable(ah);
-        ath9k_hw_configpcipowersave(ah, 1, 1);
         ath9k_htc_ps_restore(priv);
         ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
 
         priv->op_flags |= OP_INVALID;
 
-        ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
         mutex_unlock(&priv->mutex);
 }
 
@@ -1278,10 +1043,24 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
 
         mutex_lock(&priv->mutex);
 
-        /* Only one interface for now */
-        if (priv->nvifs > 0) {
-                ret = -ENOBUFS;
-                goto out;
+        if (priv->nvifs >= ATH9K_HTC_MAX_VIF) {
+                mutex_unlock(&priv->mutex);
+                return -ENOBUFS;
+        }
+
+        if (priv->num_ibss_vif ||
+            (priv->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
+                ath_err(common, "IBSS coexistence with other modes is not allowed\n");
+                mutex_unlock(&priv->mutex);
+                return -ENOBUFS;
+        }
+
+        if (((vif->type == NL80211_IFTYPE_AP) ||
+             (vif->type == NL80211_IFTYPE_ADHOC)) &&
+            ((priv->num_ap_vif + priv->num_ibss_vif) >= ATH9K_HTC_MAX_BCN_VIF)) {
+                ath_err(common, "Max. number of beaconing interfaces reached\n");
+                mutex_unlock(&priv->mutex);
+                return -ENOBUFS;
         }
 
         ath9k_htc_ps_wakeup(priv);
@@ -1290,46 +1069,60 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
 
         switch (vif->type) {
         case NL80211_IFTYPE_STATION:
-                hvif.opmode = cpu_to_be32(HTC_M_STA);
+                hvif.opmode = HTC_M_STA;
                 break;
         case NL80211_IFTYPE_ADHOC:
-                hvif.opmode = cpu_to_be32(HTC_M_IBSS);
+                hvif.opmode = HTC_M_IBSS;
+                break;
+        case NL80211_IFTYPE_AP:
+                hvif.opmode = HTC_M_HOSTAP;
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
+                ath_err(common,
                         "Interface type %d not yet supported\n", vif->type);
                 ret = -EOPNOTSUPP;
                 goto out;
         }
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Attach a VIF of type: %d\n", vif->type);
-
-        priv->ah->opmode = vif->type;
-
         /* Index starts from zero on the target */
-        avp->index = hvif.index = priv->nvifs;
+        avp->index = hvif.index = ffz(priv->vif_slot);
         hvif.rtsthreshold = cpu_to_be16(2304);
         WMI_CMD_BUF(WMI_VAP_CREATE_CMDID, &hvif);
         if (ret)
                 goto out;
 
-        priv->nvifs++;
-
         /*
          * We need a node in target to tx mgmt frames
          * before association.
          */
         ret = ath9k_htc_add_station(priv, vif, NULL);
-        if (ret)
+        if (ret) {
+                WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
                 goto out;
+        }
 
-        ret = ath9k_htc_update_cap_target(priv);
-        if (ret)
-                ath_print(common, ATH_DBG_CONFIG, "Failed to update"
-                          " capability in target \n");
+        ath9k_htc_set_bssid_mask(priv, vif);
+
+        priv->vif_slot |= (1 << avp->index);
+        priv->nvifs++;
+
+        INC_VIF(priv, vif->type);
+
+        if ((vif->type == NL80211_IFTYPE_AP) ||
+            (vif->type == NL80211_IFTYPE_ADHOC))
+                ath9k_htc_assign_bslot(priv, vif);
+
+        ath9k_htc_set_opmode(priv);
+
+        if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
+            !(priv->op_flags & OP_ANI_RUNNING)) {
+                ath9k_hw_set_tsfadjust(priv->ah, 1);
+                ath9k_htc_start_ani(priv);
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attach a VIF of type: %d at idx: %d\n", vif->type, avp->index);
 
-        priv->vif = vif;
 out:
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1347,8 +1140,6 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw,
         int ret = 0;
         u8 cmd_rsp;
 
-        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
-
         mutex_lock(&priv->mutex);
         ath9k_htc_ps_wakeup(priv);
 
@@ -1356,10 +1147,37 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw,
         memcpy(&hvif.myaddr, vif->addr, ETH_ALEN);
         hvif.index = avp->index;
         WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
+        if (ret) {
+                ath_err(common, "Unable to remove interface at idx: %d\n",
+                        avp->index);
+        }
         priv->nvifs--;
+        priv->vif_slot &= ~(1 << avp->index);
 
         ath9k_htc_remove_station(priv, vif, NULL);
-        priv->vif = NULL;
+
+        DEC_VIF(priv, vif->type);
+
+        if ((vif->type == NL80211_IFTYPE_AP) ||
+            (vif->type == NL80211_IFTYPE_ADHOC))
+                ath9k_htc_remove_bslot(priv, vif);
+
+        ath9k_htc_set_opmode(priv);
+
+        ath9k_htc_set_bssid_mask(priv, vif);
+
+        /*
+         * Stop ANI only if there are no associated station interfaces.
+         */
+        if ((vif->type == NL80211_IFTYPE_AP) && (priv->num_ap_vif == 0)) {
+                priv->rearm_ani = false;
+                ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                   ath9k_htc_vif_iter, priv);
+                if (!priv->rearm_ani)
+                        ath9k_htc_stop_ani(priv);
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface at idx: %d\n", avp->index);
 
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1384,30 +1202,44 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 mutex_unlock(&priv->htc_pm_lock);
 
                 if (enable_radio) {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "not-idle: enabling radio\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "not-idle: enabling radio\n");
                         ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
                         ath9k_htc_radio_enable(hw);
                 }
         }
 
+        /*
+         * Monitor interface should be added before
+         * IEEE80211_CONF_CHANGE_CHANNEL is handled.
+         */
+        if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
+                if ((conf->flags & IEEE80211_CONF_MONITOR) &&
+                    !priv->ah->is_monitoring)
+                        ath9k_htc_add_monitor_interface(priv);
+                else if (priv->ah->is_monitoring)
+                        ath9k_htc_remove_monitor_interface(priv);
+        }
+
         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
                 struct ieee80211_channel *curchan = hw->conf.channel;
                 int pos = curchan->hw_value;
 
-                ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
-                          curchan->center_freq);
+                ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
+                        curchan->center_freq);
 
-                ath9k_cmn_update_ichannel(hw, &priv->ah->channels[pos]);
+                ath9k_cmn_update_ichannel(&priv->ah->channels[pos],
+                                          hw->conf.channel,
+                                          hw->conf.channel_type);
 
                 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to set channel\n");
+                        ath_err(common, "Unable to set channel\n");
                         mutex_unlock(&priv->mutex);
                         return -EINVAL;
                 }
 
         }
+
         if (changed & IEEE80211_CONF_CHANGE_PS) {
                 if (conf->flags & IEEE80211_CONF_PS) {
                         ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
@@ -1419,15 +1251,10 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 }
         }
 
-        if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
-                if (conf->flags & IEEE80211_CONF_MONITOR) {
-                        if (ath9k_htc_add_monitor_interface(priv))
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Failed to set monitor mode\n");
-                        else
-                                ath_print(common, ATH_DBG_CONFIG,
-                                          "HW opmode set to Monitor mode\n");
-                }
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                priv->txpowlimit = 2 * conf->power_level;
+                ath9k_cmn_update_txpow(priv->ah, priv->curtxpow,
+                                       priv->txpowlimit, &priv->curtxpow);
         }
 
         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
@@ -1438,8 +1265,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 }
                 mutex_unlock(&priv->htc_pm_lock);
 
-                ath_print(common, ATH_DBG_CONFIG,
-                          "idle: disabling radio\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "idle: disabling radio\n");
                 ath9k_htc_radio_disable(hw);
         }
 
@@ -1455,6 +1282,7 @@ out:
         FIF_PSPOLL |                            \
         FIF_OTHER_BSS |                         \
         FIF_BCN_PRBRESP_PROMISC |               \
+        FIF_PROBE_REQ |                         \
         FIF_FCSFAIL)
 
 static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
@@ -1475,8 +1303,8 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
         rfilt = ath9k_htc_calcrxfilter(priv);
         ath9k_hw_setrxfilter(priv->ah, rfilt);
 
-        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
-                  "Set HW RX filter: 0x%x\n", rfilt);
+        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
+                "Set HW RX filter: 0x%x\n", rfilt);
 
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1505,10 +1333,13 @@ static int ath9k_htc_sta_remove(struct ieee80211_hw *hw,
                                 struct ieee80211_sta *sta)
 {
         struct ath9k_htc_priv *priv = hw->priv;
+        struct ath9k_htc_sta *ista;
         int ret;
 
         mutex_lock(&priv->mutex);
         ath9k_htc_ps_wakeup(priv);
+        ista = (struct ath9k_htc_sta *) sta->drv_priv;
+        htc_sta_drain(priv->htc, ista->index);
         ret = ath9k_htc_remove_station(priv, vif, sta);
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1539,15 +1370,14 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, u16 queue,
 
         qnum = get_hw_qnum(queue, priv->hwq_map);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Configure tx [queue/hwq] [%d/%d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, qnum, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Configure tx [queue/hwq] [%d/%d],  aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                queue, qnum, params->aifs, params->cw_min,
+                params->cw_max, params->txop);
 
         ret = ath_htc_txq_update(priv, qnum, &qi);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+                ath_err(common, "TXQ Update failed\n");
                 goto out;
         }
 
@@ -1575,25 +1405,26 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
                 return -ENOSPC;
 
         mutex_lock(&priv->mutex);
-        ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
         ath9k_htc_ps_wakeup(priv);
 
         switch (cmd) {
         case SET_KEY:
-                ret = ath9k_cmn_key_config(common, vif, sta, key);
+                ret = ath_key_config(common, vif, sta, key);
                 if (ret >= 0) {
                         key->hw_key_idx = ret;
                         /* push IV and Michael MIC generation to stack */
                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
-                        if (key->alg == ALG_TKIP)
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
-                        if (priv->ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
+                        if (priv->ah->sw_mgmt_crypto &&
+                            key->cipher == WLAN_CIPHER_SUITE_CCMP)
                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
                         ret = 0;
                 }
                 break;
         case DISABLE_KEY:
-                ath9k_cmn_key_delete(common, key);
+                ath_key_delete(common, key);
                 break;
         default:
                 ret = -EINVAL;
@@ -1605,6 +1436,37 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
         return ret;
 }
 
+static void ath9k_htc_set_bssid(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+
+        ath9k_hw_write_associd(priv->ah);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "BSSID: %pM aid: 0x%x\n",
+                common->curbssid, common->curaid);
+}
+
+static void ath9k_htc_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+
+        if ((vif->type == NL80211_IFTYPE_STATION) && bss_conf->assoc) {
+                common->curaid = bss_conf->aid;
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+        }
+}
+
+static void ath9k_htc_choose_set_bssid(struct ath9k_htc_priv *priv)
+{
+        if (priv->num_sta_assoc_vif == 1) {
+                ieee80211_iterate_active_interfaces_atomic(priv->hw,
+                                                           ath9k_htc_bss_iter, priv);
+                ath9k_htc_set_bssid(priv);
+        }
+}
+
 static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
                                        struct ieee80211_vif *vif,
                                        struct ieee80211_bss_conf *bss_conf,
@@ -1618,61 +1480,66 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
         ath9k_htc_ps_wakeup(priv);
 
         if (changed & BSS_CHANGED_ASSOC) {
-                common->curaid = bss_conf->assoc ?
-                                 bss_conf->aid : 0;
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
                         bss_conf->assoc);
 
-                if (bss_conf->assoc) {
-                        priv->op_flags |= OP_ASSOCIATED;
-                        ath_start_ani(priv);
-                } else {
-                        priv->op_flags &= ~OP_ASSOCIATED;
-                        cancel_delayed_work_sync(&priv->ath9k_ani_work);
+                bss_conf->assoc ?
+                        priv->num_sta_assoc_vif++ : priv->num_sta_assoc_vif--;
+
+                if (priv->ah->opmode == NL80211_IFTYPE_STATION) {
+                        if (bss_conf->assoc && (priv->num_sta_assoc_vif == 1))
+                                ath9k_htc_start_ani(priv);
+                        else if (priv->num_sta_assoc_vif == 0)
+                                ath9k_htc_stop_ani(priv);
                 }
         }
 
         if (changed & BSS_CHANGED_BSSID) {
-                /* Set BSSID */
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                ath9k_hw_write_associd(ah);
-
-                ath_print(common, ATH_DBG_CONFIG,
-                          "BSSID: %pM aid: 0x%x\n",
-                          common->curbssid, common->curaid);
+                if (priv->ah->opmode == NL80211_IFTYPE_ADHOC) {
+                        common->curaid = bss_conf->aid;
+                        memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                        ath9k_htc_set_bssid(priv);
+                } else if (priv->ah->opmode == NL80211_IFTYPE_STATION) {
+                        ath9k_htc_choose_set_bssid(priv);
+                }
         }
 
-        if ((changed & BSS_CHANGED_BEACON_INT) ||
-            (changed & BSS_CHANGED_BEACON) ||
-            ((changed & BSS_CHANGED_BEACON_ENABLED) &&
-            bss_conf->enable_beacon)) {
+        if ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Beacon enabled for BSS: %pM\n", bss_conf->bssid);
+                ath9k_htc_set_tsfadjust(priv, vif);
                 priv->op_flags |= OP_ENABLE_BEACON;
                 ath9k_htc_beacon_config(priv, vif);
         }
 
-        if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
-            !bss_conf->enable_beacon) {
-                priv->op_flags &= ~OP_ENABLE_BEACON;
-                ath9k_htc_beacon_config(priv, vif);
-        }
-
-        if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
-                          bss_conf->use_short_preamble);
-                if (bss_conf->use_short_preamble)
-                        priv->op_flags |= OP_PREAMBLE_SHORT;
-                else
-                        priv->op_flags &= ~OP_PREAMBLE_SHORT;
+        if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) {
+                /*
+                 * Disable SWBA interrupt only if there are no
+                 * AP/IBSS interfaces.
+                 */
+                if ((priv->num_ap_vif <= 1) || priv->num_ibss_vif) {
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Beacon disabled for BSS: %pM\n",
+                                bss_conf->bssid);
+                        priv->op_flags &= ~OP_ENABLE_BEACON;
+                        ath9k_htc_beacon_config(priv, vif);
+                }
         }
 
-        if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
-                          bss_conf->use_cts_prot);
-                if (bss_conf->use_cts_prot &&
-                    hw->conf.channel->band != IEEE80211_BAND_5GHZ)
-                        priv->op_flags |= OP_PROTECT_ENABLE;
-                else
-                        priv->op_flags &= ~OP_PROTECT_ENABLE;
+        if (changed & BSS_CHANGED_BEACON_INT) {
+                /*
+                 * Reset the HW TSF for the first AP interface.
+                 */
+                if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
+                    (priv->nvifs == 1) &&
+                    (priv->num_ap_vif == 1) &&
+                    (vif->type == NL80211_IFTYPE_AP)) {
+                        priv->op_flags |= OP_TSF_RESET;
+                }
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Beacon interval changed for BSS: %pM\n",
+                        bss_conf->bssid);
+                ath9k_htc_beacon_config(priv, vif);
         }
 
         if (changed & BSS_CHANGED_ERP_SLOT) {
@@ -1731,12 +1598,15 @@ static int ath9k_htc_ampdu_action(struct ieee80211_hw *hw,
                                   struct ieee80211_vif *vif,
                                   enum ieee80211_ampdu_mlme_action action,
                                   struct ieee80211_sta *sta,
-                                  u16 tid, u16 *ssn)
+                                  u16 tid, u16 *ssn, u8 buf_size)
 {
         struct ath9k_htc_priv *priv = hw->priv;
         struct ath9k_htc_sta *ista;
         int ret = 0;
 
+        mutex_lock(&priv->mutex);
+        ath9k_htc_ps_wakeup(priv);
+
         switch (action) {
         case IEEE80211_AMPDU_RX_START:
                 break;
@@ -1753,15 +1623,17 @@ static int ath9k_htc_ampdu_action(struct ieee80211_hw *hw,
                 break;
         case IEEE80211_AMPDU_TX_OPERATIONAL:
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
-                spin_lock_bh(&priv->tx_lock);
+                spin_lock_bh(&priv->tx.tx_lock);
                 ista->tid_state[tid] = AGGR_OPERATIONAL;
-                spin_unlock_bh(&priv->tx_lock);
+                spin_unlock_bh(&priv->tx.tx_lock);
                 break;
         default:
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL,
-                          "Unknown AMPDU action\n");
+                ath_err(ath9k_hw_common(priv->ah), "Unknown AMPDU action\n");
         }
 
+        ath9k_htc_ps_restore(priv);
+        mutex_unlock(&priv->mutex);
+
         return ret;
 }
 
@@ -1774,7 +1646,7 @@ static void ath9k_htc_sw_scan_start(struct ieee80211_hw *hw)
         priv->op_flags |= OP_SCANNING;
         spin_unlock_bh(&priv->beacon_lock);
         cancel_work_sync(&priv->ps_work);
-        cancel_delayed_work_sync(&priv->ath9k_ani_work);
+        ath9k_htc_stop_ani(priv);
         mutex_unlock(&priv->mutex);
 }
 
@@ -1783,14 +1655,11 @@ static void ath9k_htc_sw_scan_complete(struct ieee80211_hw *hw)
         struct ath9k_htc_priv *priv = hw->priv;
 
         mutex_lock(&priv->mutex);
-        ath9k_htc_ps_wakeup(priv);
         spin_lock_bh(&priv->beacon_lock);
         priv->op_flags &= ~OP_SCANNING;
         spin_unlock_bh(&priv->beacon_lock);
-        priv->op_flags |= OP_FULL_RESET;
-        if (priv->op_flags & OP_ASSOCIATED)
-                ath9k_htc_beacon_config(priv, priv->vif);
-        ath_start_ani(priv);
+        ath9k_htc_ps_wakeup(priv);
+        ath9k_htc_vif_reconfig(priv);
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
 }
@@ -1813,6 +1682,55 @@ static void ath9k_htc_set_coverage_class(struct ieee80211_hw *hw,
         mutex_unlock(&priv->mutex);
 }
 
+/*
+ * Currently, this is used only for selecting the minimum rate
+ * for management frames, rate selection for data frames remain
+ * unaffected.
+ */
+static int ath9k_htc_set_bitrate_mask(struct ieee80211_hw *hw,
+                                      struct ieee80211_vif *vif,
+                                      const struct cfg80211_bitrate_mask *mask)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_target_rate_mask tmask;
+        struct ath9k_htc_vif *avp = (void *)vif->drv_priv;
+        int ret = 0;
+        u8 cmd_rsp;
+
+        memset(&tmask, 0, sizeof(struct ath9k_htc_target_rate_mask));
+
+        tmask.vif_index = avp->index;
+        tmask.band = IEEE80211_BAND_2GHZ;
+        tmask.mask = cpu_to_be32(mask->control[IEEE80211_BAND_2GHZ].legacy);
+
+        WMI_CMD_BUF(WMI_BITRATE_MASK_CMDID, &tmask);
+        if (ret) {
+                ath_err(common,
+                        "Unable to set 2G rate mask for "
+                        "interface at idx: %d\n", avp->index);
+                goto out;
+        }
+
+        tmask.band = IEEE80211_BAND_5GHZ;
+        tmask.mask = cpu_to_be32(mask->control[IEEE80211_BAND_5GHZ].legacy);
+
+        WMI_CMD_BUF(WMI_BITRATE_MASK_CMDID, &tmask);
+        if (ret) {
+                ath_err(common,
+                        "Unable to set 5G rate mask for "
+                        "interface at idx: %d\n", avp->index);
+                goto out;
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Set bitrate masks: 0x%x, 0x%x\n",
+                mask->control[IEEE80211_BAND_2GHZ].legacy,
+                mask->control[IEEE80211_BAND_5GHZ].legacy);
+out:
+        return ret;
+}
+
 struct ieee80211_ops ath9k_htc_ops = {
         .tx                 = ath9k_htc_tx,
         .start              = ath9k_htc_start,
@@ -1835,4 +1753,5 @@ struct ieee80211_ops ath9k_htc_ops = {
         .set_rts_threshold  = ath9k_htc_set_rts_threshold,
         .rfkill_poll        = ath9k_htc_rfkill_poll_state,
         .set_coverage_class = ath9k_htc_set_coverage_class,
+        .set_bitrate_mask   = ath9k_htc_set_bitrate_mask,
 };
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 2a6e45a293a9..2d81c700e201 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,8 +20,15 @@
 /* TX */
 /******/
 
+static const int subtype_txq_to_hwq[] = {
+        [WME_AC_BE] = ATH_TXQ_AC_BE,
+        [WME_AC_BK] = ATH_TXQ_AC_BK,
+        [WME_AC_VI] = ATH_TXQ_AC_VI,
+        [WME_AC_VO] = ATH_TXQ_AC_VO,
+};
+
 #define ATH9K_HTC_INIT_TXQ(subtype) do {                        \
-                qi.tqi_subtype = subtype;                       \
+                qi.tqi_subtype = subtype_txq_to_hwq[subtype];   \
                 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;             \
                 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;            \
                 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;            \
@@ -46,6 +53,138 @@ int get_hw_qnum(u16 queue, int *hwq_map)
         }
 }
 
+void ath9k_htc_check_stop_queues(struct ath9k_htc_priv *priv)
+{
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.queued_cnt++;
+        if ((priv->tx.queued_cnt >= ATH9K_HTC_TX_THRESHOLD) &&
+            !(priv->tx.flags & ATH9K_HTC_OP_TX_QUEUES_STOP)) {
+                priv->tx.flags |= ATH9K_HTC_OP_TX_QUEUES_STOP;
+                ieee80211_stop_queues(priv->hw);
+        }
+        spin_unlock_bh(&priv->tx.tx_lock);
+}
+
+void ath9k_htc_check_wake_queues(struct ath9k_htc_priv *priv)
+{
+        spin_lock_bh(&priv->tx.tx_lock);
+        if ((priv->tx.queued_cnt < ATH9K_HTC_TX_THRESHOLD) &&
+            (priv->tx.flags & ATH9K_HTC_OP_TX_QUEUES_STOP)) {
+                priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
+                ieee80211_wake_queues(priv->hw);
+        }
+        spin_unlock_bh(&priv->tx.tx_lock);
+}
+
+int ath9k_htc_tx_get_slot(struct ath9k_htc_priv *priv)
+{
+        int slot;
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        slot = find_first_zero_bit(priv->tx.tx_slot, MAX_TX_BUF_NUM);
+        if (slot >= MAX_TX_BUF_NUM) {
+                spin_unlock_bh(&priv->tx.tx_lock);
+                return -ENOBUFS;
+        }
+        __set_bit(slot, priv->tx.tx_slot);
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        return slot;
+}
+
+void ath9k_htc_tx_clear_slot(struct ath9k_htc_priv *priv, int slot)
+{
+        spin_lock_bh(&priv->tx.tx_lock);
+        __clear_bit(slot, priv->tx.tx_slot);
+        spin_unlock_bh(&priv->tx.tx_lock);
+}
+
+static inline enum htc_endpoint_id get_htc_epid(struct ath9k_htc_priv *priv,
+                                                u16 qnum)
+{
+        enum htc_endpoint_id epid;
+
+        switch (qnum) {
+        case 0:
+                TX_QSTAT_INC(WME_AC_VO);
+                epid = priv->data_vo_ep;
+                break;
+        case 1:
+                TX_QSTAT_INC(WME_AC_VI);
+                epid = priv->data_vi_ep;
+                break;
+        case 2:
+                TX_QSTAT_INC(WME_AC_BE);
+                epid = priv->data_be_ep;
+                break;
+        case 3:
+        default:
+                TX_QSTAT_INC(WME_AC_BK);
+                epid = priv->data_bk_ep;
+                break;
+        }
+
+        return epid;
+}
+
+static inline struct sk_buff_head*
+get_htc_epid_queue(struct ath9k_htc_priv *priv, u8 epid)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct sk_buff_head *epid_queue = NULL;
+
+        if (epid == priv->mgmt_ep)
+                epid_queue = &priv->tx.mgmt_ep_queue;
+        else if (epid == priv->cab_ep)
+                epid_queue = &priv->tx.cab_ep_queue;
+        else if (epid == priv->data_be_ep)
+                epid_queue = &priv->tx.data_be_queue;
+        else if (epid == priv->data_bk_ep)
+                epid_queue = &priv->tx.data_bk_queue;
+        else if (epid == priv->data_vi_ep)
+                epid_queue = &priv->tx.data_vi_queue;
+        else if (epid == priv->data_vo_ep)
+                epid_queue = &priv->tx.data_vo_queue;
+        else
+                ath_err(common, "Invalid EPID: %d\n", epid);
+
+        return epid_queue;
+}
+
+/*
+ * Removes the driver header and returns the TX slot number
+ */
+static inline int strip_drv_header(struct ath9k_htc_priv *priv,
+                                   struct sk_buff *skb)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        int slot;
+
+        tx_ctl = HTC_SKB_CB(skb);
+
+        if (tx_ctl->epid == priv->mgmt_ep) {
+                struct tx_mgmt_hdr *tx_mhdr =
+                        (struct tx_mgmt_hdr *)skb->data;
+                slot = tx_mhdr->cookie;
+                skb_pull(skb, sizeof(struct tx_mgmt_hdr));
+        } else if ((tx_ctl->epid == priv->data_bk_ep) ||
+                   (tx_ctl->epid == priv->data_be_ep) ||
+                   (tx_ctl->epid == priv->data_vi_ep) ||
+                   (tx_ctl->epid == priv->data_vo_ep) ||
+                   (tx_ctl->epid == priv->cab_ep)) {
+                struct tx_frame_hdr *tx_fhdr =
+                        (struct tx_frame_hdr *)skb->data;
+                slot = tx_fhdr->cookie;
+                skb_pull(skb, sizeof(struct tx_frame_hdr));
+        } else {
+                ath_err(common, "Unsupported EPID: %d\n", tx_ctl->epid);
+                slot = -EINVAL;
+        }
+
+        return slot;
+}
+
 int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
                        struct ath9k_tx_queue_info *qinfo)
 {
@@ -62,8 +201,8 @@ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
         qi.tqi_readyTime = qinfo->tqi_readyTime;
 
         if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unable to update hardware queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(ah),
+                        "Unable to update hardware queue %u!\n", qnum);
                 error = -EIO;
         } else {
                 ath9k_hw_resettxqueue(ah, qnum);
@@ -72,241 +211,592 @@ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
         return error;
 }
 
-int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, struct sk_buff *skb)
+static void ath9k_htc_tx_mgmt(struct ath9k_htc_priv *priv,
+                              struct ath9k_htc_vif *avp,
+                              struct sk_buff *skb,
+                              u8 sta_idx, u8 vif_idx, u8 slot)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_mgmt *mgmt;
+        struct ieee80211_hdr *hdr;
+        struct tx_mgmt_hdr mgmt_hdr;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        u8 *tx_fhdr;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        hdr = (struct ieee80211_hdr *) skb->data;
+
+        memset(tx_ctl, 0, sizeof(*tx_ctl));
+        memset(&mgmt_hdr, 0, sizeof(struct tx_mgmt_hdr));
+
+        /*
+         * Set the TSF adjust value for probe response
+         * frame also.
+         */
+        if (avp && unlikely(ieee80211_is_probe_resp(hdr->frame_control))) {
+                mgmt = (struct ieee80211_mgmt *)skb->data;
+                mgmt->u.probe_resp.timestamp = avp->tsfadjust;
+        }
+
+        tx_ctl->type = ATH9K_HTC_MGMT;
+
+        mgmt_hdr.node_idx = sta_idx;
+        mgmt_hdr.vif_idx = vif_idx;
+        mgmt_hdr.tidno = 0;
+        mgmt_hdr.flags = 0;
+        mgmt_hdr.cookie = slot;
+
+        mgmt_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
+        if (mgmt_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
+                mgmt_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
+        else
+                mgmt_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+
+        tx_fhdr = skb_push(skb, sizeof(mgmt_hdr));
+        memcpy(tx_fhdr, (u8 *) &mgmt_hdr, sizeof(mgmt_hdr));
+        tx_ctl->epid = priv->mgmt_ep;
+}
+
+static void ath9k_htc_tx_data(struct ath9k_htc_priv *priv,
+                              struct ieee80211_vif *vif,
+                              struct sk_buff *skb,
+                              u8 sta_idx, u8 vif_idx, u8 slot,
+                              bool is_cab)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_hdr *hdr;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        struct tx_frame_hdr tx_hdr;
+        u32 flags = 0;
+        u8 *qc, *tx_fhdr;
+        u16 qnum;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        hdr = (struct ieee80211_hdr *) skb->data;
+
+        memset(tx_ctl, 0, sizeof(*tx_ctl));
+        memset(&tx_hdr, 0, sizeof(struct tx_frame_hdr));
+
+        tx_hdr.node_idx = sta_idx;
+        tx_hdr.vif_idx = vif_idx;
+        tx_hdr.cookie = slot;
+
+        /*
+         * This is a bit redundant but it helps to get
+         * the per-packet index quickly when draining the
+         * TX queue in the HIF layer. Otherwise we would
+         * have to parse the packet contents ...
+         */
+        tx_ctl->sta_idx = sta_idx;
+
+        if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+                tx_ctl->type = ATH9K_HTC_AMPDU;
+                tx_hdr.data_type = ATH9K_HTC_AMPDU;
+        } else {
+                tx_ctl->type = ATH9K_HTC_NORMAL;
+                tx_hdr.data_type = ATH9K_HTC_NORMAL;
+        }
+
+        if (ieee80211_is_data_qos(hdr->frame_control)) {
+                qc = ieee80211_get_qos_ctl(hdr);
+                tx_hdr.tidno = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
+        }
+
+        /* Check for RTS protection */
+        if (priv->hw->wiphy->rts_threshold != (u32) -1)
+                if (skb->len > priv->hw->wiphy->rts_threshold)
+                        flags |= ATH9K_HTC_TX_RTSCTS;
+
+        /* CTS-to-self */
+        if (!(flags & ATH9K_HTC_TX_RTSCTS) &&
+            (vif && vif->bss_conf.use_cts_prot))
+                flags |= ATH9K_HTC_TX_CTSONLY;
+
+        tx_hdr.flags = cpu_to_be32(flags);
+        tx_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
+        if (tx_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
+                tx_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
+        else
+                tx_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+
+        tx_fhdr = skb_push(skb, sizeof(tx_hdr));
+        memcpy(tx_fhdr, (u8 *) &tx_hdr, sizeof(tx_hdr));
+
+        if (is_cab) {
+                CAB_STAT_INC;
+                tx_ctl->epid = priv->cab_ep;
+                return;
+        }
+
+        qnum = skb_get_queue_mapping(skb);
+        tx_ctl->epid = get_htc_epid(priv, qnum);
+}
+
+int ath9k_htc_tx_start(struct ath9k_htc_priv *priv,
+                       struct sk_buff *skb,
+                       u8 slot, bool is_cab)
 {
         struct ieee80211_hdr *hdr;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         struct ieee80211_sta *sta = tx_info->control.sta;
+        struct ieee80211_vif *vif = tx_info->control.vif;
         struct ath9k_htc_sta *ista;
-        struct ath9k_htc_tx_ctl tx_ctl;
-        enum htc_endpoint_id epid;
-        u16 qnum;
-        __le16 fc;
-        u8 *tx_fhdr;
+        struct ath9k_htc_vif *avp = NULL;
         u8 sta_idx, vif_idx;
 
         hdr = (struct ieee80211_hdr *) skb->data;
-        fc = hdr->frame_control;
 
-        if (tx_info->control.vif &&
-                        (struct ath9k_htc_vif *) tx_info->control.vif->drv_priv)
-                vif_idx = ((struct ath9k_htc_vif *)
-                                tx_info->control.vif->drv_priv)->index;
-        else
-                vif_idx = priv->nvifs;
+        /*
+         * Find out on which interface this packet has to be
+         * sent out.
+         */
+        if (vif) {
+                avp = (struct ath9k_htc_vif *) vif->drv_priv;
+                vif_idx = avp->index;
+        } else {
+                if (!priv->ah->is_monitoring) {
+                        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
+                                "VIF is null, but no monitor interface !\n");
+                        return -EINVAL;
+                }
+
+                vif_idx = priv->mon_vif_idx;
+        }
 
+        /*
+         * Find out which station this packet is destined for.
+         */
         if (sta) {
                 ista = (struct ath9k_htc_sta *) sta->drv_priv;
                 sta_idx = ista->index;
         } else {
-                sta_idx = 0;
+                sta_idx = priv->vif_sta_pos[vif_idx];
         }
 
-        memset(&tx_ctl, 0, sizeof(struct ath9k_htc_tx_ctl));
+        if (ieee80211_is_data(hdr->frame_control))
+                ath9k_htc_tx_data(priv, vif, skb,
+                                  sta_idx, vif_idx, slot, is_cab);
+        else
+                ath9k_htc_tx_mgmt(priv, avp, skb,
+                                  sta_idx, vif_idx, slot);
 
-        if (ieee80211_is_data(fc)) {
-                struct tx_frame_hdr tx_hdr;
-                u8 *qc;
 
-                memset(&tx_hdr, 0, sizeof(struct tx_frame_hdr));
+        return htc_send(priv->htc, skb);
+}
 
-                tx_hdr.node_idx = sta_idx;
-                tx_hdr.vif_idx = vif_idx;
+static inline bool __ath9k_htc_check_tx_aggr(struct ath9k_htc_priv *priv,
+                                             struct ath9k_htc_sta *ista, u8 tid)
+{
+        bool ret = false;
 
-                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
-                        tx_ctl.type = ATH9K_HTC_AMPDU;
-                        tx_hdr.data_type = ATH9K_HTC_AMPDU;
-                } else {
-                        tx_ctl.type = ATH9K_HTC_NORMAL;
-                        tx_hdr.data_type = ATH9K_HTC_NORMAL;
-                }
+        spin_lock_bh(&priv->tx.tx_lock);
+        if ((tid < ATH9K_HTC_MAX_TID) && (ista->tid_state[tid] == AGGR_STOP))
+                ret = true;
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        return ret;
+}
+
+static void ath9k_htc_check_tx_aggr(struct ath9k_htc_priv *priv,
+                                    struct ieee80211_vif *vif,
+                                    struct sk_buff *skb)
+{
+        struct ieee80211_sta *sta;
+        struct ieee80211_hdr *hdr;
+        __le16 fc;
+
+        hdr = (struct ieee80211_hdr *) skb->data;
+        fc = hdr->frame_control;
+
+        rcu_read_lock();
+
+        sta = ieee80211_find_sta(vif, hdr->addr1);
+        if (!sta) {
+                rcu_read_unlock();
+                return;
+        }
+
+        if (sta && conf_is_ht(&priv->hw->conf) &&
+            !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
+                if (ieee80211_is_data_qos(fc)) {
+                        u8 *qc, tid;
+                        struct ath9k_htc_sta *ista;
 
-                if (ieee80211_is_data(fc)) {
                         qc = ieee80211_get_qos_ctl(hdr);
-                        tx_hdr.tidno = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
+                        tid = qc[0] & 0xf;
+                        ista = (struct ath9k_htc_sta *)sta->drv_priv;
+                        if (__ath9k_htc_check_tx_aggr(priv, ista, tid)) {
+                                ieee80211_start_tx_ba_session(sta, tid, 0);
+                                spin_lock_bh(&priv->tx.tx_lock);
+                                ista->tid_state[tid] = AGGR_PROGRESS;
+                                spin_unlock_bh(&priv->tx.tx_lock);
+                        }
                 }
+        }
 
-                /* Check for RTS protection */
-                if (priv->hw->wiphy->rts_threshold != (u32) -1)
-                        if (skb->len > priv->hw->wiphy->rts_threshold)
-                                tx_hdr.flags |= ATH9K_HTC_TX_RTSCTS;
+        rcu_read_unlock();
+}
 
-                /* CTS-to-self */
-                if (!(tx_hdr.flags & ATH9K_HTC_TX_RTSCTS) &&
-                    (priv->op_flags & OP_PROTECT_ENABLE))
-                        tx_hdr.flags |= ATH9K_HTC_TX_CTSONLY;
+static void ath9k_htc_tx_process(struct ath9k_htc_priv *priv,
+                                 struct sk_buff *skb,
+                                 struct __wmi_event_txstatus *txs)
+{
+        struct ieee80211_vif *vif;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        struct ieee80211_tx_info *tx_info;
+        struct ieee80211_tx_rate *rate;
+        struct ieee80211_conf *cur_conf = &priv->hw->conf;
+        bool txok;
+        int slot;
 
-                tx_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
-                if (tx_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
-                        tx_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
-                else
-                        tx_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+        slot = strip_drv_header(priv, skb);
+        if (slot < 0) {
+                dev_kfree_skb_any(skb);
+                return;
+        }
 
-                tx_fhdr = skb_push(skb, sizeof(tx_hdr));
-                memcpy(tx_fhdr, (u8 *) &tx_hdr, sizeof(tx_hdr));
+        tx_ctl = HTC_SKB_CB(skb);
+        txok = tx_ctl->txok;
+        tx_info = IEEE80211_SKB_CB(skb);
+        vif = tx_info->control.vif;
+        rate = &tx_info->status.rates[0];
 
-                qnum = skb_get_queue_mapping(skb);
+        memset(&tx_info->status, 0, sizeof(tx_info->status));
 
-                switch (qnum) {
-                case 0:
-                        TX_QSTAT_INC(WME_AC_VO);
-                        epid = priv->data_vo_ep;
-                        break;
-                case 1:
-                        TX_QSTAT_INC(WME_AC_VI);
-                        epid = priv->data_vi_ep;
-                        break;
-                case 2:
-                        TX_QSTAT_INC(WME_AC_BE);
-                        epid = priv->data_be_ep;
-                        break;
-                case 3:
-                default:
-                        TX_QSTAT_INC(WME_AC_BK);
-                        epid = priv->data_bk_ep;
-                        break;
-                }
-        } else {
-                struct tx_mgmt_hdr mgmt_hdr;
+        /*
+         * URB submission failed for this frame, it never reached
+         * the target.
+         */
+        if (!txok || !vif || !txs)
+                goto send_mac80211;
+
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_ACK)
+                tx_info->flags |= IEEE80211_TX_STAT_ACK;
 
-                memset(&mgmt_hdr, 0, sizeof(struct tx_mgmt_hdr));
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_FILT)
+                tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
 
-                tx_ctl.type = ATH9K_HTC_NORMAL;
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_RTC_CTS)
+                rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
 
-                mgmt_hdr.node_idx = sta_idx;
-                mgmt_hdr.vif_idx = vif_idx;
-                mgmt_hdr.tidno = 0;
-                mgmt_hdr.flags = 0;
+        rate->count = 1;
+        rate->idx = MS(txs->ts_rate, ATH9K_HTC_TXSTAT_RATE);
 
-                mgmt_hdr.key_type = ath9k_cmn_get_hw_crypto_keytype(skb);
-                if (mgmt_hdr.key_type == ATH9K_KEY_TYPE_CLEAR)
-                        mgmt_hdr.keyix = (u8) ATH9K_TXKEYIX_INVALID;
-                else
-                        mgmt_hdr.keyix = tx_info->control.hw_key->hw_key_idx;
+        if (txs->ts_flags & ATH9K_HTC_TXSTAT_MCS) {
+                rate->flags |= IEEE80211_TX_RC_MCS;
 
-                tx_fhdr = skb_push(skb, sizeof(mgmt_hdr));
-                memcpy(tx_fhdr, (u8 *) &mgmt_hdr, sizeof(mgmt_hdr));
-                epid = priv->mgmt_ep;
+                if (txs->ts_flags & ATH9K_HTC_TXSTAT_CW40)
+                        rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
+                if (txs->ts_flags & ATH9K_HTC_TXSTAT_SGI)
+                        rate->flags |= IEEE80211_TX_RC_SHORT_GI;
+        } else {
+                if (cur_conf->channel->band == IEEE80211_BAND_5GHZ)
+                        rate->idx += 4; /* No CCK rates */
         }
 
-        return htc_send(priv->htc, skb, epid, &tx_ctl);
+        ath9k_htc_check_tx_aggr(priv, vif, skb);
+
+send_mac80211:
+        spin_lock_bh(&priv->tx.tx_lock);
+        if (WARN_ON(--priv->tx.queued_cnt < 0))
+                priv->tx.queued_cnt = 0;
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        ath9k_htc_tx_clear_slot(priv, slot);
+
+        /* Send status to mac80211 */
+        ieee80211_tx_status(priv->hw, skb);
 }
 
-static bool ath9k_htc_check_tx_aggr(struct ath9k_htc_priv *priv,
-                                    struct ath9k_htc_sta *ista, u8 tid)
+static inline void ath9k_htc_tx_drainq(struct ath9k_htc_priv *priv,
+                                       struct sk_buff_head *queue)
 {
-        bool ret = false;
+        struct sk_buff *skb;
 
-        spin_lock_bh(&priv->tx_lock);
-        if ((tid < ATH9K_HTC_MAX_TID) && (ista->tid_state[tid] == AGGR_STOP))
-                ret = true;
-        spin_unlock_bh(&priv->tx_lock);
+        while ((skb = skb_dequeue(queue)) != NULL) {
+                ath9k_htc_tx_process(priv, skb, NULL);
+        }
+}
 
-        return ret;
+void ath9k_htc_tx_drain(struct ath9k_htc_priv *priv)
+{
+        struct ath9k_htc_tx_event *event, *tmp;
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags |= ATH9K_HTC_OP_TX_DRAIN;
+        spin_unlock_bh(&priv->tx.tx_lock);
+
+        /*
+         * Ensure that all pending TX frames are flushed,
+         * and that the TX completion/failed tasklets is killed.
+         */
+        htc_stop(priv->htc);
+        tasklet_kill(&priv->wmi->wmi_event_tasklet);
+        tasklet_kill(&priv->tx_failed_tasklet);
+
+        ath9k_htc_tx_drainq(priv, &priv->tx.mgmt_ep_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.cab_ep_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_be_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_bk_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_vi_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.data_vo_queue);
+        ath9k_htc_tx_drainq(priv, &priv->tx.tx_failed);
+
+        /*
+         * The TX cleanup timer has already been killed.
+         */
+        spin_lock_bh(&priv->wmi->event_lock);
+        list_for_each_entry_safe(event, tmp, &priv->wmi->pending_tx_events, list) {
+                list_del(&event->list);
+                kfree(event);
+        }
+        spin_unlock_bh(&priv->wmi->event_lock);
+
+        spin_lock_bh(&priv->tx.tx_lock);
+        priv->tx.flags &= ~ATH9K_HTC_OP_TX_DRAIN;
+        spin_unlock_bh(&priv->tx.tx_lock);
 }
 
-void ath9k_tx_tasklet(unsigned long data)
+void ath9k_tx_failed_tasklet(unsigned long data)
 {
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
-        struct ieee80211_sta *sta;
-        struct ieee80211_hdr *hdr;
-        struct ieee80211_tx_info *tx_info;
-        struct sk_buff *skb = NULL;
-        __le16 fc;
 
-        while ((skb = skb_dequeue(&priv->tx_queue)) != NULL) {
+        spin_lock_bh(&priv->tx.tx_lock);
+        if (priv->tx.flags & ATH9K_HTC_OP_TX_DRAIN) {
+                spin_unlock_bh(&priv->tx.tx_lock);
+                return;
+        }
+        spin_unlock_bh(&priv->tx.tx_lock);
 
-                hdr = (struct ieee80211_hdr *) skb->data;
-                fc = hdr->frame_control;
-                tx_info = IEEE80211_SKB_CB(skb);
+        ath9k_htc_tx_drainq(priv, &priv->tx.tx_failed);
+}
 
-                memset(&tx_info->status, 0, sizeof(tx_info->status));
+static inline bool check_cookie(struct ath9k_htc_priv *priv,
+                                struct sk_buff *skb,
+                                u8 cookie, u8 epid)
+{
+        u8 fcookie = 0;
+
+        if (epid == priv->mgmt_ep) {
+                struct tx_mgmt_hdr *hdr;
+                hdr = (struct tx_mgmt_hdr *) skb->data;
+                fcookie = hdr->cookie;
+        } else if ((epid == priv->data_bk_ep) ||
+                   (epid == priv->data_be_ep) ||
+                   (epid == priv->data_vi_ep) ||
+                   (epid == priv->data_vo_ep) ||
+                   (epid == priv->cab_ep)) {
+                struct tx_frame_hdr *hdr;
+                hdr = (struct tx_frame_hdr *) skb->data;
+                fcookie = hdr->cookie;
+        }
 
-                rcu_read_lock();
+        if (fcookie == cookie)
+                return true;
 
-                sta = ieee80211_find_sta(priv->vif, hdr->addr1);
-                if (!sta) {
-                        rcu_read_unlock();
-                        ieee80211_tx_status(priv->hw, skb);
-                        continue;
+        return false;
+}
+
+static struct sk_buff* ath9k_htc_tx_get_packet(struct ath9k_htc_priv *priv,
+                                               struct __wmi_event_txstatus *txs)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct sk_buff_head *epid_queue;
+        struct sk_buff *skb, *tmp;
+        unsigned long flags;
+        u8 epid = MS(txs->ts_rate, ATH9K_HTC_TXSTAT_EPID);
+
+        epid_queue = get_htc_epid_queue(priv, epid);
+        if (!epid_queue)
+                return NULL;
+
+        spin_lock_irqsave(&epid_queue->lock, flags);
+        skb_queue_walk_safe(epid_queue, skb, tmp) {
+                if (check_cookie(priv, skb, txs->cookie, epid)) {
+                        __skb_unlink(skb, epid_queue);
+                        spin_unlock_irqrestore(&epid_queue->lock, flags);
+                        return skb;
                 }
+        }
+        spin_unlock_irqrestore(&epid_queue->lock, flags);
 
-                /* Check if we need to start aggregation */
+        ath_dbg(common, ATH_DBG_XMIT,
+                "No matching packet for cookie: %d, epid: %d\n",
+                txs->cookie, epid);
 
-                if (sta && conf_is_ht(&priv->hw->conf) &&
-                    !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
-                        if (ieee80211_is_data_qos(fc)) {
-                                u8 *qc, tid;
-                                struct ath9k_htc_sta *ista;
+        return NULL;
+}
 
-                                qc = ieee80211_get_qos_ctl(hdr);
-                                tid = qc[0] & 0xf;
-                                ista = (struct ath9k_htc_sta *)sta->drv_priv;
+void ath9k_htc_txstatus(struct ath9k_htc_priv *priv, void *wmi_event)
+{
+        struct wmi_event_txstatus *txs = (struct wmi_event_txstatus *)wmi_event;
+        struct __wmi_event_txstatus *__txs;
+        struct sk_buff *skb;
+        struct ath9k_htc_tx_event *tx_pend;
+        int i;
 
-                                if (ath9k_htc_check_tx_aggr(priv, ista, tid)) {
-                                        ieee80211_start_tx_ba_session(sta, tid);
-                                        spin_lock_bh(&priv->tx_lock);
-                                        ista->tid_state[tid] = AGGR_PROGRESS;
-                                        spin_unlock_bh(&priv->tx_lock);
-                                }
-                        }
-                }
+        for (i = 0; i < txs->cnt; i++) {
+                WARN_ON(txs->cnt > HTC_MAX_TX_STATUS);
 
-                rcu_read_unlock();
+                __txs = &txs->txstatus[i];
+
+                skb = ath9k_htc_tx_get_packet(priv, __txs);
+                if (!skb) {
+                        /*
+                         * Store this event, so that the TX cleanup
+                         * routine can check later for the needed packet.
+                         */
+                        tx_pend = kzalloc(sizeof(struct ath9k_htc_tx_event),
+                                          GFP_ATOMIC);
+                        if (!tx_pend)
+                                continue;
+
+                        memcpy(&tx_pend->txs, __txs,
+                               sizeof(struct __wmi_event_txstatus));
 
-                /* Send status to mac80211 */
-                ieee80211_tx_status(priv->hw, skb);
+                        spin_lock(&priv->wmi->event_lock);
+                        list_add_tail(&tx_pend->list,
+                                      &priv->wmi->pending_tx_events);
+                        spin_unlock(&priv->wmi->event_lock);
+
+                        continue;
+                }
+
+                ath9k_htc_tx_process(priv, skb, __txs);
         }
 
         /* Wake TX queues if needed */
-        spin_lock_bh(&priv->tx_lock);
-        if (priv->tx_queues_stop) {
-                priv->tx_queues_stop = false;
-                spin_unlock_bh(&priv->tx_lock);
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                          "Waking up TX queues\n");
-                ieee80211_wake_queues(priv->hw);
-                return;
-        }
-        spin_unlock_bh(&priv->tx_lock);
+        ath9k_htc_check_wake_queues(priv);
 }
 
 void ath9k_htc_txep(void *drv_priv, struct sk_buff *skb,
                     enum htc_endpoint_id ep_id, bool txok)
 {
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) drv_priv;
-        struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct ieee80211_tx_info *tx_info;
+        struct ath9k_htc_tx_ctl *tx_ctl;
+        struct sk_buff_head *epid_queue;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        tx_ctl->txok = txok;
+        tx_ctl->timestamp = jiffies;
 
-        if (!skb)
+        if (!txok) {
+                skb_queue_tail(&priv->tx.tx_failed, skb);
+                tasklet_schedule(&priv->tx_failed_tasklet);
                 return;
+        }
 
-        if (ep_id == priv->mgmt_ep) {
-                skb_pull(skb, sizeof(struct tx_mgmt_hdr));
-        } else if ((ep_id == priv->data_bk_ep) ||
-                   (ep_id == priv->data_be_ep) ||
-                   (ep_id == priv->data_vi_ep) ||
-                   (ep_id == priv->data_vo_ep)) {
-                skb_pull(skb, sizeof(struct tx_frame_hdr));
-        } else {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unsupported TX EPID: %d\n", ep_id);
+        epid_queue = get_htc_epid_queue(priv, ep_id);
+        if (!epid_queue) {
                 dev_kfree_skb_any(skb);
                 return;
         }
 
-        tx_info = IEEE80211_SKB_CB(skb);
+        skb_queue_tail(epid_queue, skb);
+}
 
-        if (txok)
-                tx_info->flags |= IEEE80211_TX_STAT_ACK;
+static inline bool check_packet(struct ath9k_htc_priv *priv, struct sk_buff *skb)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_tx_ctl *tx_ctl;
+
+        tx_ctl = HTC_SKB_CB(skb);
+
+        if (time_after(jiffies,
+                       tx_ctl->timestamp +
+                       msecs_to_jiffies(ATH9K_HTC_TX_TIMEOUT_INTERVAL))) {
+                ath_dbg(common, ATH_DBG_XMIT,
+                        "Dropping a packet due to TX timeout\n");
+                return true;
+        }
 
-        skb_queue_tail(&priv->tx_queue, skb);
-        tasklet_schedule(&priv->tx_tasklet);
+        return false;
+}
+
+static void ath9k_htc_tx_cleanup_queue(struct ath9k_htc_priv *priv,
+                                       struct sk_buff_head *epid_queue)
+{
+        bool process = false;
+        unsigned long flags;
+        struct sk_buff *skb, *tmp;
+        struct sk_buff_head queue;
+
+        skb_queue_head_init(&queue);
+
+        spin_lock_irqsave(&epid_queue->lock, flags);
+        skb_queue_walk_safe(epid_queue, skb, tmp) {
+                if (check_packet(priv, skb)) {
+                        __skb_unlink(skb, epid_queue);
+                        __skb_queue_tail(&queue, skb);
+                        process = true;
+                }
+        }
+        spin_unlock_irqrestore(&epid_queue->lock, flags);
+
+        if (process) {
+                skb_queue_walk_safe(&queue, skb, tmp) {
+                        __skb_unlink(skb, &queue);
+                        ath9k_htc_tx_process(priv, skb, NULL);
+                }
+        }
+}
+
+void ath9k_htc_tx_cleanup_timer(unsigned long data)
+{
+        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) data;
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_tx_event *event, *tmp;
+        struct sk_buff *skb;
+
+        spin_lock(&priv->wmi->event_lock);
+        list_for_each_entry_safe(event, tmp, &priv->wmi->pending_tx_events, list) {
+
+                skb = ath9k_htc_tx_get_packet(priv, &event->txs);
+                if (skb) {
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Found packet for cookie: %d, epid: %d\n",
+                                event->txs.cookie,
+                                MS(event->txs.ts_rate, ATH9K_HTC_TXSTAT_EPID));
+
+                        ath9k_htc_tx_process(priv, skb, &event->txs);
+                        list_del(&event->list);
+                        kfree(event);
+                        continue;
+                }
+
+                if (++event->count >= ATH9K_HTC_TX_TIMEOUT_COUNT) {
+                        list_del(&event->list);
+                        kfree(event);
+                }
+        }
+        spin_unlock(&priv->wmi->event_lock);
+
+        /*
+         * Check if status-pending packets have to be cleaned up.
+         */
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.mgmt_ep_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.cab_ep_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_be_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_bk_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_vi_queue);
+        ath9k_htc_tx_cleanup_queue(priv, &priv->tx.data_vo_queue);
+
+        /* Wake TX queues if needed */
+        ath9k_htc_check_wake_queues(priv);
+
+        mod_timer(&priv->tx.cleanup_timer,
+                  jiffies + msecs_to_jiffies(ATH9K_HTC_TX_CLEANUP_INTERVAL));
 }
 
 int ath9k_tx_init(struct ath9k_htc_priv *priv)
 {
-        skb_queue_head_init(&priv->tx_queue);
+        skb_queue_head_init(&priv->tx.mgmt_ep_queue);
+        skb_queue_head_init(&priv->tx.cab_ep_queue);
+        skb_queue_head_init(&priv->tx.data_be_queue);
+        skb_queue_head_init(&priv->tx.data_bk_queue);
+        skb_queue_head_init(&priv->tx.data_vi_queue);
+        skb_queue_head_init(&priv->tx.data_vo_queue);
+        skb_queue_head_init(&priv->tx.tx_failed);
         return 0;
 }
 
@@ -330,9 +820,8 @@ bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype)
                 return false;
 
         if (qnum >= ARRAY_SIZE(priv->hwq_map)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "qnum %u out of range, max %u!\n",
-                          qnum, (unsigned int)ARRAY_SIZE(priv->hwq_map));
+                ath_err(common, "qnum %u out of range, max %zu!\n",
+                        qnum, ARRAY_SIZE(priv->hwq_map));
                 ath9k_hw_releasetxqueue(ah, qnum);
                 return false;
         }
@@ -369,8 +858,7 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv)
                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
                 | ATH9K_RX_FILTER_MCAST;
 
-        /* If not a STA, enable processing of Probe Requests */
-        if (ah->opmode != NL80211_IFTYPE_STATION)
+        if (priv->rxfilter & FIF_PROBE_REQ)
                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 
         /*
@@ -380,20 +868,29 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv)
          */
         if (((ah->opmode != NL80211_IFTYPE_AP) &&
              (priv->rxfilter & FIF_PROMISC_IN_BSS)) ||
-            (ah->opmode == NL80211_IFTYPE_MONITOR))
+            ah->is_monitoring)
                 rfilt |= ATH9K_RX_FILTER_PROM;
 
         if (priv->rxfilter & FIF_CONTROL)
                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 
         if ((ah->opmode == NL80211_IFTYPE_STATION) &&
+            (priv->nvifs <= 1) &&
             !(priv->rxfilter & FIF_BCN_PRBRESP_PROMISC))
                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
         else
                 rfilt |= ATH9K_RX_FILTER_BEACON;
 
-        if (conf_is_ht(&priv->hw->conf))
+        if (conf_is_ht(&priv->hw->conf)) {
                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
+                rfilt |= ATH9K_RX_FILTER_UNCOMP_BA_BAR;
+        }
+
+        if (priv->rxfilter & FIF_PSPOLL)
+                rfilt |= ATH9K_RX_FILTER_PSPOLL;
+
+        if (priv->nvifs > 1)
+                rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
 
         return rfilt;
 
@@ -406,21 +903,12 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv)
 static void ath9k_htc_opmode_init(struct ath9k_htc_priv *priv)
 {
         struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
         u32 rfilt, mfilt[2];
 
         /* configure rx filter */
         rfilt = ath9k_htc_calcrxfilter(priv);
         ath9k_hw_setrxfilter(ah, rfilt);
 
-        /* configure bssid mask */
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                ath_hw_setbssidmask(common);
-
-        /* configure operational mode */
-        ath9k_hw_setopmode(ah);
-
         /* calculate and install multicast filter */
         mfilt[0] = mfilt[1] = ~0;
         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
@@ -484,9 +972,9 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
         int last_rssi = ATH_RSSI_DUMMY_MARKER;
         __le16 fc;
 
-        if (skb->len <= HTC_RX_FRAME_HEADER_SIZE) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Corrupted RX frame, dropping\n");
+        if (skb->len < HTC_RX_FRAME_HEADER_SIZE) {
+                ath_err(common, "Corrupted RX frame, dropping (len: %d)\n",
+                        skb->len);
                 goto rx_next;
         }
 
@@ -494,13 +982,14 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
 
         if (be16_to_cpu(rxstatus->rs_datalen) -
             (skb->len - HTC_RX_FRAME_HEADER_SIZE) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Corrupted RX data len, dropping "
-                          "(dlen: %d, skblen: %d)\n",
-                          rxstatus->rs_datalen, skb->len);
+                ath_err(common,
+                        "Corrupted RX data len, dropping (dlen: %d, skblen: %d)\n",
+                        rxstatus->rs_datalen, skb->len);
                 goto rx_next;
         }
 
+        ath9k_htc_err_stat_rx(priv, rxstatus);
+
         /* Get the RX status information */
         memcpy(&rxbuf->rxstatus, rxstatus, HTC_RX_FRAME_HEADER_SIZE);
         skb_pull(skb, HTC_RX_FRAME_HEADER_SIZE);
@@ -573,31 +1062,29 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
         ath9k_process_rate(hw, rx_status, rxbuf->rxstatus.rs_rate,
                            rxbuf->rxstatus.rs_flags);
 
-        if (priv->op_flags & OP_ASSOCIATED) {
-                if (rxbuf->rxstatus.rs_rssi != ATH9K_RSSI_BAD &&
-                    !rxbuf->rxstatus.rs_moreaggr)
-                        ATH_RSSI_LPF(priv->rx.last_rssi,
-                                     rxbuf->rxstatus.rs_rssi);
+        if (rxbuf->rxstatus.rs_rssi != ATH9K_RSSI_BAD &&
+            !rxbuf->rxstatus.rs_moreaggr)
+                ATH_RSSI_LPF(priv->rx.last_rssi,
+                             rxbuf->rxstatus.rs_rssi);
 
-                last_rssi = priv->rx.last_rssi;
+        last_rssi = priv->rx.last_rssi;
 
-                if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
-                        rxbuf->rxstatus.rs_rssi = ATH_EP_RND(last_rssi,
-                                                             ATH_RSSI_EP_MULTIPLIER);
+        if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
+                rxbuf->rxstatus.rs_rssi = ATH_EP_RND(last_rssi,
+                                                     ATH_RSSI_EP_MULTIPLIER);
 
-                if (rxbuf->rxstatus.rs_rssi < 0)
-                        rxbuf->rxstatus.rs_rssi = 0;
+        if (rxbuf->rxstatus.rs_rssi < 0)
+                rxbuf->rxstatus.rs_rssi = 0;
 
-                if (ieee80211_is_beacon(fc))
-                        priv->ah->stats.avgbrssi = rxbuf->rxstatus.rs_rssi;
-        }
+        if (ieee80211_is_beacon(fc))
+                priv->ah->stats.avgbrssi = rxbuf->rxstatus.rs_rssi;
 
         rx_status->mactime = be64_to_cpu(rxbuf->rxstatus.rs_tstamp);
         rx_status->band = hw->conf.channel->band;
         rx_status->freq = hw->conf.channel->center_freq;
         rx_status->signal =  rxbuf->rxstatus.rs_rssi + ATH_DEFAULT_NOISE_FLOOR;
         rx_status->antenna = rxbuf->rxstatus.rs_antenna;
-        rx_status->flag |= RX_FLAG_TSFT;
+        rx_status->flag |= RX_FLAG_MACTIME_MPDU;
 
         return true;
 
@@ -680,8 +1167,8 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb,
         spin_unlock(&priv->rx.rxbuflock);
 
         if (rxbuf == NULL) {
-                ath_print(common, ATH_DBG_ANY,
-                          "No free RX buffer\n");
+                ath_dbg(common, ATH_DBG_ANY,
+                        "No free RX buffer\n");
                 goto err;
         }
 
@@ -723,8 +1210,7 @@ int ath9k_rx_init(struct ath9k_htc_priv *priv)
         for (i = 0; i < ATH9K_HTC_RXBUF; i++) {
                 rxbuf = kzalloc(sizeof(struct ath9k_htc_rxbuf), GFP_KERNEL);
                 if (rxbuf == NULL) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to allocate RX buffers\n");
+                        ath_err(common, "Unable to allocate RX buffers\n");
                         goto err;
                 }
                 list_add_tail(&rxbuf->list, &priv->rx.rxbuf);
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
index 705c0f342e1c..1b90ed8795c3 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,8 +17,8 @@
 #include "htc.h"
 
 static int htc_issue_send(struct htc_target *target, struct sk_buff* skb,
-                          u16 len, u8 flags, u8 epid,
-                          struct ath9k_htc_tx_ctl *tx_ctl)
+                          u16 len, u8 flags, u8 epid)
+
 {
         struct htc_frame_hdr *hdr;
         struct htc_endpoint *endpoint = &target->endpoint[epid];
@@ -30,8 +30,8 @@ static int htc_issue_send(struct htc_target *target, struct sk_buff* skb,
         hdr->flags = flags;
         hdr->payload_len = cpu_to_be16(len);
 
-        status = target->hif->send(target->hif_dev, endpoint->ul_pipeid, skb,
-                                   tx_ctl);
+        status = target->hif->send(target->hif_dev, endpoint->ul_pipeid, skb);
+
         return status;
 }
 
@@ -162,7 +162,7 @@ static int htc_config_pipe_credits(struct htc_target *target)
 
         target->htc_flags |= HTC_OP_CONFIG_PIPE_CREDITS;
 
-        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0, NULL);
+        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0);
         if (ret)
                 goto err;
 
@@ -197,7 +197,7 @@ static int htc_setup_complete(struct htc_target *target)
 
         target->htc_flags |= HTC_OP_START_WAIT;
 
-        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0, NULL);
+        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0);
         if (ret)
                 goto err;
 
@@ -268,7 +268,7 @@ int htc_connect_service(struct htc_target *target,
         conn_msg->dl_pipeid = endpoint->dl_pipeid;
         conn_msg->ul_pipeid = endpoint->ul_pipeid;
 
-        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0, NULL);
+        ret = htc_issue_send(target, skb, skb->len, 0, ENDPOINT0);
         if (ret)
                 goto err;
 
@@ -286,35 +286,33 @@ err:
         return ret;
 }
 
-int htc_send(struct htc_target *target, struct sk_buff *skb,
-             enum htc_endpoint_id epid, struct ath9k_htc_tx_ctl *tx_ctl)
+int htc_send(struct htc_target *target, struct sk_buff *skb)
 {
-        return htc_issue_send(target, skb, skb->len, 0, epid, tx_ctl);
+        struct ath9k_htc_tx_ctl *tx_ctl;
+
+        tx_ctl = HTC_SKB_CB(skb);
+        return htc_issue_send(target, skb, skb->len, 0, tx_ctl->epid);
 }
 
-void htc_stop(struct htc_target *target)
+int htc_send_epid(struct htc_target *target, struct sk_buff *skb,
+                  enum htc_endpoint_id epid)
 {
-        enum htc_endpoint_id epid;
-        struct htc_endpoint *endpoint;
+        return htc_issue_send(target, skb, skb->len, 0, epid);
+}
 
-        for (epid = ENDPOINT0; epid < ENDPOINT_MAX; epid++) {
-                endpoint = &target->endpoint[epid];
-                if (endpoint->service_id != 0)
-                        target->hif->stop(target->hif_dev, endpoint->ul_pipeid);
-        }
+void htc_stop(struct htc_target *target)
+{
+        target->hif->stop(target->hif_dev);
 }
 
 void htc_start(struct htc_target *target)
 {
-        enum htc_endpoint_id epid;
-        struct htc_endpoint *endpoint;
+        target->hif->start(target->hif_dev);
+}
 
-        for (epid = ENDPOINT0; epid < ENDPOINT_MAX; epid++) {
-                endpoint = &target->endpoint[epid];
-                if (endpoint->service_id != 0)
-                        target->hif->start(target->hif_dev,
-                                           endpoint->ul_pipeid);
-        }
+void htc_sta_drain(struct htc_target *target, u8 idx)
+{
+        target->hif->sta_drain(target->hif_dev, idx);
 }
 
 void ath9k_htc_txcompletion_cb(struct htc_target *htc_handle,
@@ -360,7 +358,7 @@ ret:
  * HTC Messages are handled directly here and the obtained SKB
  * is freed.
  *
- * Sevice messages (Data, WMI) passed to the corresponding
+ * Service messages (Data, WMI) passed to the corresponding
  * endpoint RX handlers, which have to free the SKB.
  */
 void ath9k_htc_rx_msg(struct htc_target *htc_handle,
@@ -462,9 +460,10 @@ void ath9k_htc_hw_free(struct htc_target *htc)
 }
 
 int ath9k_htc_hw_init(struct htc_target *target,
-                      struct device *dev, u16 devid)
+                      struct device *dev, u16 devid,
+                      char *product, u32 drv_info)
 {
-        if (ath9k_htc_probe_device(target, dev, devid)) {
+        if (ath9k_htc_probe_device(target, dev, devid, product, drv_info)) {
                 printk(KERN_ERR "Failed to initialize the device\n");
                 return -ENODEV;
         }
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.h b/drivers/net/wireless/ath/ath9k/htc_hst.h
index faba6790328b..e1ffbb6bd636 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.h
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -33,10 +33,10 @@ struct ath9k_htc_hif {
         u8 control_dl_pipe;
         u8 control_ul_pipe;
 
-        void (*start) (void *hif_handle, u8 pipe);
-        void (*stop) (void *hif_handle, u8 pipe);
-        int (*send) (void *hif_handle, u8 pipe, struct sk_buff *buf,
-                     struct ath9k_htc_tx_ctl *tx_ctl);
+        void (*start) (void *hif_handle);
+        void (*stop) (void *hif_handle);
+        void (*sta_drain) (void *hif_handle, u8 idx);
+        int (*send) (void *hif_handle, u8 pipe, struct sk_buff *buf);
 };
 
 enum htc_endpoint_id {
@@ -77,41 +77,16 @@ struct htc_config_pipe_msg {
         u8 credits;
 } __packed;
 
-struct htc_packet {
-        void *pktcontext;
-        u8 *buf;
-        u8 *buf_payload;
-        u32 buflen;
-        u32 payload_len;
-
-        int endpoint;
-        int status;
-
-        void *context;
-        u32 reserved;
-};
-
 struct htc_ep_callbacks {
         void *priv;
         void (*tx) (void *, struct sk_buff *, enum htc_endpoint_id, bool txok);
         void (*rx) (void *, struct sk_buff *, enum htc_endpoint_id);
 };
 
-#define HTC_TX_QUEUE_SIZE 256
-
-struct htc_txq {
-        struct sk_buff *buf[HTC_TX_QUEUE_SIZE];
-        u32 txqdepth;
-        u16 txbuf_cnt;
-        u16 txq_head;
-        u16 txq_tail;
-};
-
 struct htc_endpoint {
         u16 service_id;
 
         struct htc_ep_callbacks ep_callbacks;
-        struct htc_txq htc_txq;
         u32 max_txqdepth;
         int max_msglen;
 
@@ -123,11 +98,6 @@ struct htc_endpoint {
 #define HTC_CONTROL_BUFFER_SIZE \
         (HTC_MAX_CONTROL_MESSAGE_LENGTH + sizeof(struct htc_frame_hdr))
 
-struct htc_control_buf {
-        struct htc_packet htc_pkt;
-        u8 buf[HTC_CONTROL_BUFFER_SIZE];
-};
-
 #define HTC_OP_START_WAIT           BIT(0)
 #define HTC_OP_CONFIG_PIPE_CREDITS  BIT(1)
 
@@ -224,10 +194,12 @@ int htc_init(struct htc_target *target);
 int htc_connect_service(struct htc_target *target,
                           struct htc_service_connreq *service_connreq,
                           enum htc_endpoint_id *conn_rsp_eid);
-int htc_send(struct htc_target *target, struct sk_buff *skb,
-             enum htc_endpoint_id eid, struct ath9k_htc_tx_ctl *tx_ctl);
+int htc_send(struct htc_target *target, struct sk_buff *skb);
+int htc_send_epid(struct htc_target *target, struct sk_buff *skb,
+                  enum htc_endpoint_id epid);
 void htc_stop(struct htc_target *target);
 void htc_start(struct htc_target *target);
+void htc_sta_drain(struct htc_target *target, u8 idx);
 
 void ath9k_htc_rx_msg(struct htc_target *htc_handle,
                       struct sk_buff *skb, u32 len, u8 pipe_id);
@@ -239,7 +211,8 @@ struct htc_target *ath9k_htc_hw_alloc(void *hif_handle,
                                       struct device *dev);
 void ath9k_htc_hw_free(struct htc_target *htc);
 int ath9k_htc_hw_init(struct htc_target *target,
-                      struct device *dev, u16 devid);
+                      struct device *dev, u16 devid, char *product,
+                      u32 drv_info);
 void ath9k_htc_hw_deinit(struct htc_target *target, bool hot_unplug);
 
 #endif /* HTC_HST_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index ffecbadaea4a..2f3e07263fcb 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -116,27 +116,21 @@ static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
         ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
 }
 
-static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
-                                                 u32 burstDuration)
+static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
 {
-        ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
+        ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
 }
 
-static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
-                                                   u32 vmf)
+static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                struct ath_hw_antcomb_conf *antconf)
 {
-        ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
+        ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf);
 }
 
-static inline void ath9k_hw_procmibevent(struct ath_hw *ah)
+static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                struct ath_hw_antcomb_conf *antconf)
 {
-        ath9k_hw_ops(ah)->ani_proc_mib_event(ah);
-}
-
-static inline void ath9k_hw_ani_monitor(struct ath_hw *ah,
-                                        struct ath9k_channel *chan)
-{
-        ath9k_hw_ops(ah)->ani_monitor(ah, chan);
+        ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
 }
 
 /* Private hardware call ops */
@@ -234,11 +228,6 @@ static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
         return ath9k_hw_private_ops(ah)->rfbus_done(ah);
 }
 
-static inline void ath9k_enable_rfkill(struct ath_hw *ah)
-{
-        return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
-}
-
 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
 {
         if (!ath9k_hw_private_ops(ah)->restore_chainmask)
@@ -276,15 +265,4 @@ static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
         ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
 }
 
-static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
-                                            enum ath9k_cal_types calType)
-{
-        return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
-}
-
-static inline void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
-{
-        ath9k_hw_private_ops(ah)->ani_reset(ah, is_scanning);
-}
-
 #endif /* ATH9K_HW_OPS_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 3384ca164562..1be7c8bbef84 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
 }
 
-static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-
-        return priv_ops->macversion_supported(ah->hw_version.macVersion);
-}
-
 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
                                         struct ath9k_channel *chan)
 {
@@ -88,29 +81,32 @@ static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
 /* Helper Functions */
 /********************/
 
-static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
+static void ath9k_hw_set_clockrate(struct ath_hw *ah)
 {
         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+        struct ath_common *common = ath9k_hw_common(ah);
+        unsigned int clockrate;
 
         if (!ah->curchan) /* should really check for CCK instead */
-                return usecs *ATH9K_CLOCK_RATE_CCK;
-        if (conf->channel->band == IEEE80211_BAND_2GHZ)
-                return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
-
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
-                return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
+                clockrate = ATH9K_CLOCK_RATE_CCK;
+        else if (conf->channel->band == IEEE80211_BAND_2GHZ)
+                clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
+        else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
+                clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
         else
-                return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
+                clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
+
+        if (conf_is_ht40(conf))
+                clockrate *= 2;
+
+        common->clockrate = clockrate;
 }
 
 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 {
-        struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+        struct ath_common *common = ath9k_hw_common(ah);
 
-        if (conf_is_ht40(conf))
-                return ath9k_hw_mac_clks(ah, usecs) * 2;
-        else
-                return ath9k_hw_mac_clks(ah, usecs);
+        return usecs * common->clockrate;
 }
 
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
@@ -126,14 +122,28 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
                 udelay(AH_TIME_QUANTUM);
         }
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
-                  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
-                  timeout, reg, REG_READ(ah, reg), mask, val);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
+                "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
+                timeout, reg, REG_READ(ah, reg), mask, val);
 
         return false;
 }
 EXPORT_SYMBOL(ath9k_hw_wait);
 
+void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                          int column, unsigned int *writecnt)
+{
+        int r;
+
+        ENABLE_REGWRITE_BUFFER(ah);
+        for (r = 0; r < array->ia_rows; r++) {
+                REG_WRITE(ah, INI_RA(array, r, 0),
+                          INI_RA(array, r, column));
+                DO_DELAY(*writecnt);
+        }
+        REGWRITE_BUFFER_FLUSH(ah);
+}
+
 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 {
         u32 retval;
@@ -146,25 +156,6 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
         return retval;
 }
 
-bool ath9k_get_channel_edges(struct ath_hw *ah,
-                             u16 flags, u16 *low,
-                             u16 *high)
-{
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
-
-        if (flags & CHANNEL_5GHZ) {
-                *low = pCap->low_5ghz_chan;
-                *high = pCap->high_5ghz_chan;
-                return true;
-        }
-        if ((flags & CHANNEL_2GHZ)) {
-                *low = pCap->low_2ghz_chan;
-                *high = pCap->high_2ghz_chan;
-                return true;
-        }
-        return false;
-}
-
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                            u8 phy, int kbps,
                            u32 frameLen, u16 rateix,
@@ -208,8 +199,8 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                 }
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unknown phy %u (rate ix %u)\n", phy, rateix);
+                ath_err(ath9k_hw_common(ah),
+                        "Unknown phy %u (rate ix %u)\n", phy, rateix);
                 txTime = 0;
                 break;
         }
@@ -256,6 +247,17 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
 {
         u32 val;
 
+        switch (ah->hw_version.devid) {
+        case AR5416_AR9100_DEVID:
+                ah->hw_version.macVersion = AR_SREV_VERSION_9100;
+                break;
+        case AR9300_DEVID_AR9340:
+                ah->hw_version.macVersion = AR_SREV_VERSION_9340;
+                val = REG_READ(ah, AR_SREV);
+                ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
+                return;
+        }
+
         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 
         if (val == 0xFF) {
@@ -281,11 +283,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
 
 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 {
-        if (AR_SREV_9100(ah))
+        if (!AR_SREV_5416(ah))
                 return;
 
-        ENABLE_REGWRITE_BUFFER(ah);
-
         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -297,9 +297,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 
         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
-
-        REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /* This should work for all families including legacy */
@@ -308,10 +305,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         u32 regAddr[2] = { AR_STA_ID0 };
         u32 regHold[2];
-        u32 patternData[4] = { 0x55555555,
-                               0xaaaaaaaa,
-                               0x66666666,
-                               0x99999999 };
+        static const u32 patternData[4] = {
+                0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
+        };
         int i, j, loop_max;
 
         if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@ -330,11 +326,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                         REG_WRITE(ah, addr, wrData);
                         rdData = REG_READ(ah, addr);
                         if (rdData != wrData) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "address test failed "
-                                          "addr: 0x%08x - wr:0x%08x != "
-                                          "rd:0x%08x\n",
-                                          addr, wrData, rdData);
+                                ath_err(common,
+                                        "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+                                        addr, wrData, rdData);
                                 return false;
                         }
                 }
@@ -343,11 +337,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                         REG_WRITE(ah, addr, wrData);
                         rdData = REG_READ(ah, addr);
                         if (wrData != rdData) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "address test failed "
-                                          "addr: 0x%08x - wr:0x%08x != "
-                                          "rd:0x%08x\n",
-                                          addr, wrData, rdData);
+                                ath_err(common,
+                                        "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+                                        addr, wrData, rdData);
                                 return false;
                         }
                 }
@@ -371,10 +363,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
         ah->config.pcie_clock_req = 0;
         ah->config.pcie_waen = 0;
         ah->config.analog_shiftreg = 1;
-        ah->config.ofdm_trig_low = 200;
-        ah->config.ofdm_trig_high = 500;
-        ah->config.cck_trig_high = 200;
-        ah->config.cck_trig_low = 100;
         ah->config.enable_ani = true;
 
         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
@@ -382,10 +370,8 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
                 ah->config.spurchans[i][1] = AR_NO_SPUR;
         }
 
-        if (ah->hw_version.devid != AR2427_DEVID_PCIE)
-                ah->config.ht_enable = 1;
-        else
-                ah->config.ht_enable = 0;
+        /* PAPRD needs some more work to be enabled */
+        ah->config.paprd_disable = 1;
 
         ah->config.rx_intr_mitigation = true;
         ah->config.pcieSerDesWrite = true;
@@ -421,17 +407,14 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
         ah->hw_version.magic = AR5416_MAGIC;
         ah->hw_version.subvendorid = 0;
 
-        ah->ah_flags = 0;
-        if (!AR_SREV_9100(ah))
-                ah->ah_flags = AH_USE_EEPROM;
-
         ah->atim_window = 0;
         ah->sta_id1_defaults =
                 AR_STA_ID1_CRPT_MIC_ENABLE |
                 AR_STA_ID1_MCAST_KSRCH;
-        ah->beacon_interval = 100;
+        if (AR_SREV_9100(ah))
+                ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
         ah->enable_32kHz_clock = DONT_USE_32KHZ;
-        ah->slottime = (u32) -1;
+        ah->slottime = 20;
         ah->globaltxtimeout = (u32) -1;
         ah->power_mode = ATH9K_PM_UNDEFINED;
 }
@@ -442,7 +425,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
         u32 sum;
         int i;
         u16 eeval;
-        u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
+        static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 
         sum = 0;
         for (i = 0; i < 3; i++) {
@@ -459,9 +442,10 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 
 static int ath9k_hw_post_init(struct ath_hw *ah)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
         int ecode;
 
-        if (!AR_SREV_9271(ah)) {
+        if (common->bus_ops->ath_bus_type != ATH_USB) {
                 if (!ath9k_hw_chip_test(ah))
                         return -ENODEV;
         }
@@ -476,20 +460,20 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
         if (ecode != 0)
                 return ecode;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
-                  "Eeprom VER: %d, REV: %d\n",
-                  ah->eep_ops->get_eeprom_ver(ah),
-                  ah->eep_ops->get_eeprom_rev(ah));
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
+                "Eeprom VER: %d, REV: %d\n",
+                ah->eep_ops->get_eeprom_ver(ah),
+                ah->eep_ops->get_eeprom_rev(ah));
 
         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
         if (ecode) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Failed allocating banks for "
-                          "external radio\n");
+                ath_err(ath9k_hw_common(ah),
+                        "Failed allocating banks for external radio\n");
+                ath9k_hw_rf_free_ext_banks(ah);
                 return ecode;
         }
 
-        if (!AR_SREV_9100(ah)) {
+        if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
                 ath9k_hw_ani_setup(ah);
                 ath9k_hw_ani_init(ah);
         }
@@ -511,12 +495,19 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         int r = 0;
 
-        if (ah->hw_version.devid == AR5416_AR9100_DEVID)
-                ah->hw_version.macVersion = AR_SREV_VERSION_9100;
+        ath9k_hw_read_revisions(ah);
+
+        /*
+         * Read back AR_WA into a permanent copy and set bits 14 and 17.
+         * We need to do this to avoid RMW of this register. We cannot
+         * read the reg when chip is asleep.
+         */
+        ah->WARegVal = REG_READ(ah, AR_WA);
+        ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
+                         AR_WA_ASPM_TIMER_BASED_DISABLE);
 
         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Couldn't reset chip\n");
+                ath_err(common, "Couldn't reset chip\n");
                 return -EIO;
         }
 
@@ -526,7 +517,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         ath9k_hw_attach_ops(ah);
 
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
-                ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
+                ath_err(common, "Couldn't wakeup chip\n");
                 return -EIO;
         }
 
@@ -542,7 +533,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
                 }
         }
 
-        ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
+        ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
                 ah->config.serialize_regmode);
 
         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
@@ -550,36 +541,40 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         else
                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 
-        if (!ath9k_hw_macversion_supported(ah)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Mac Chip Rev 0x%02x.%x is not supported by "
-                          "this driver\n", ah->hw_version.macVersion,
-                          ah->hw_version.macRev);
+        switch (ah->hw_version.macVersion) {
+        case AR_SREV_VERSION_5416_PCI:
+        case AR_SREV_VERSION_5416_PCIE:
+        case AR_SREV_VERSION_9160:
+        case AR_SREV_VERSION_9100:
+        case AR_SREV_VERSION_9280:
+        case AR_SREV_VERSION_9285:
+        case AR_SREV_VERSION_9287:
+        case AR_SREV_VERSION_9271:
+        case AR_SREV_VERSION_9300:
+        case AR_SREV_VERSION_9485:
+        case AR_SREV_VERSION_9340:
+                break;
+        default:
+                ath_err(common,
+                        "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
+                        ah->hw_version.macVersion, ah->hw_version.macRev);
                 return -EOPNOTSUPP;
         }
 
-        if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
+        if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
                 ah->is_pciexpress = false;
 
         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
         ath9k_hw_init_cal_settings(ah);
 
         ah->ani_function = ATH9K_ANI_ALL;
-        if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
         if (!AR_SREV_9300_20_OR_LATER(ah))
                 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 
         ath9k_hw_init_mode_regs(ah);
 
-        /*
-         * Read back AR_WA into a permanent copy and set bits 14 and 17.
-         * We need to do this to avoid RMW of this register. We cannot
-         * read the reg when chip is asleep.
-         */
-        ah->WARegVal = REG_READ(ah, AR_WA);
-        ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
-                         AR_WA_ASPM_TIMER_BASED_DISABLE);
 
         if (ah->is_pciexpress)
                 ath9k_hw_configpcipowersave(ah, 0, 0);
@@ -600,8 +595,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
 
         r = ath9k_hw_init_macaddr(ah);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to initialize MAC address\n");
+                ath_err(common, "Failed to initialize MAC address\n");
                 return r;
         }
 
@@ -635,21 +629,22 @@ int ath9k_hw_init(struct ath_hw *ah)
         case AR9287_DEVID_PCIE:
         case AR2427_DEVID_PCIE:
         case AR9300_DEVID_PCIE:
+        case AR9300_DEVID_AR9485_PCIE:
+        case AR9300_DEVID_AR9340:
                 break;
         default:
                 if (common->bus_ops->ath_bus_type == ATH_USB)
                         break;
-                ath_print(common, ATH_DBG_FATAL,
-                          "Hardware device ID 0x%04x not supported\n",
-                          ah->hw_version.devid);
+                ath_err(common, "Hardware device ID 0x%04x not supported\n",
+                        ah->hw_version.devid);
                 return -EOPNOTSUPP;
         }
 
         ret = __ath9k_hw_init(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize hardware; "
-                          "initialization status: %d\n", ret);
+                ath_err(common,
+                        "Unable to initialize hardware; initialization status: %d\n",
+                        ret);
                 return ret;
         }
 
@@ -676,16 +671,101 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
+u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
+{
+        REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
+        udelay(100);
+        REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
+
+        while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
+                udelay(100);
+
+        return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
+}
+EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
+
 static void ath9k_hw_init_pll(struct ath_hw *ah,
                               struct ath9k_channel *chan)
 {
-        u32 pll = ath9k_hw_compute_pll_control(ah, chan);
+        u32 pll;
+
+        if (AR_SREV_9485(ah)) {
+
+                /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_DPLL2_KD, 0x40);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_DPLL2_KI, 0x4);
+
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
+                              AR_CH0_BB_DPLL1_REFDIV, 0x5);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
+                              AR_CH0_BB_DPLL1_NINI, 0x58);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
+                              AR_CH0_BB_DPLL1_NFRAC, 0x0);
+
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_OUTDIV, 0x1);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
+
+                /* program BB PLL phase_shift to 0x6 */
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
+                              AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
+
+                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+                              AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
+                udelay(1000);
+        } else if (AR_SREV_9340(ah)) {
+                u32 regval, pll2_divint, pll2_divfrac, refdiv;
+
+                REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
+                udelay(1000);
+
+                REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
+                udelay(100);
+
+                if (ah->is_clk_25mhz) {
+                        pll2_divint = 0x54;
+                        pll2_divfrac = 0x1eb85;
+                        refdiv = 3;
+                } else {
+                        pll2_divint = 88;
+                        pll2_divfrac = 0;
+                        refdiv = 5;
+                }
+
+                regval = REG_READ(ah, AR_PHY_PLL_MODE);
+                regval |= (0x1 << 16);
+                REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
+                udelay(100);
+
+                REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
+                          (pll2_divint << 18) | pll2_divfrac);
+                udelay(100);
+
+                regval = REG_READ(ah, AR_PHY_PLL_MODE);
+                regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
+                         (0x4 << 26) | (0x18 << 19);
+                REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
+                REG_WRITE(ah, AR_PHY_PLL_MODE,
+                          REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
+                udelay(1000);
+        }
+
+        pll = ath9k_hw_compute_pll_control(ah, chan);
 
         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
+        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+                udelay(1000);
+
         /* Switch the core clock for ar9271 to 117Mhz */
         if (AR_SREV_9271(ah)) {
                 udelay(500);
@@ -695,17 +775,34 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
         udelay(RTC_PLL_SETTLE_DELAY);
 
         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
+
+        if (AR_SREV_9340(ah)) {
+                if (ah->is_clk_25mhz) {
+                        REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
+                        REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
+                        REG_WRITE(ah,  AR_SLP32_INC, 0x0001e7ae);
+                } else {
+                        REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
+                        REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
+                        REG_WRITE(ah,  AR_SLP32_INC, 0x0001e800);
+                }
+                udelay(100);
+        }
 }
 
 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
                                           enum nl80211_iftype opmode)
 {
+        u32 sync_default = AR_INTR_SYNC_DEFAULT;
         u32 imr_reg = AR_IMR_TXERR |
                 AR_IMR_TXURN |
                 AR_IMR_RXERR |
                 AR_IMR_RXORN |
                 AR_IMR_BCNMISC;
 
+        if (AR_SREV_9340(ah))
+                sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
+
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 imr_reg |= AR_IMR_RXOK_HP;
                 if (ah->config.rx_intr_mitigation)
@@ -736,12 +833,11 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 
         if (!AR_SREV_9100(ah)) {
                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
-                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
@@ -775,8 +871,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 {
         if (tu > 0xFFFF) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                          "bad global tx timeout %u\n", tu);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                        "bad global tx timeout %u\n", tu);
                 ah->globaltxtimeout = (u32) -1;
                 return false;
         } else {
@@ -793,12 +889,11 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
         int slottime;
         int sifstime;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
-                  ah->misc_mode);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
+                ah->misc_mode);
 
         if (ah->misc_mode != 0)
-                REG_WRITE(ah, AR_PCU_MISC,
-                          REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
+                REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
 
         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
                 sifstime = 16;
@@ -819,7 +914,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
                 acktimeout += 64 - sifstime - ah->slottime;
 
-        ath9k_hw_setslottime(ah, slottime);
+        ath9k_hw_setslottime(ah, ah->slottime);
         ath9k_hw_set_ack_timeout(ah, acktimeout);
         ath9k_hw_set_cts_timeout(ah, acktimeout);
         if (ah->globaltxtimeout != (u32) -1)
@@ -866,26 +961,21 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        u32 regval;
 
         ENABLE_REGWRITE_BUFFER(ah);
 
         /*
          * set AHB_MODE not to do cacheline prefetches
         */
-        if (!AR_SREV_9300_20_OR_LATER(ah)) {
-                regval = REG_READ(ah, AR_AHB_MODE);
-                REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
-        }
+        if (!AR_SREV_9300_20_OR_LATER(ah))
+                REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
 
         /*
          * let mac dma reads be in 128 byte chunks
          */
-        regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
-        REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
+        REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         /*
          * Restore TX Trigger Level to its pre-reset value.
@@ -900,8 +990,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
         /*
          * let mac dma writes be in 128 byte chunks
          */
-        regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
-        REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
+        REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
 
         /*
          * Setup receive FIFO threshold to hold off TX activities
@@ -933,7 +1022,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
         }
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah))
                 ath9k_hw_reset_txstatus_ring(ah);
@@ -941,27 +1029,27 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 
 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 {
-        u32 val;
+        u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
+        u32 set = AR_STA_ID1_KSRCH_MODE;
 
-        val = REG_READ(ah, AR_STA_ID1);
-        val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
         switch (opmode) {
-        case NL80211_IFTYPE_AP:
-                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
-                          | AR_STA_ID1_KSRCH_MODE);
-                REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
-                break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
-                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
-                          | AR_STA_ID1_KSRCH_MODE);
+                set |= AR_STA_ID1_ADHOC;
                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
                 break;
+        case NL80211_IFTYPE_AP:
+                set |= AR_STA_ID1_STA_AP;
+                /* fall through */
         case NL80211_IFTYPE_STATION:
-        case NL80211_IFTYPE_MONITOR:
-                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
+                REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+                break;
+        default:
+                if (!ah->is_monitoring)
+                        set = 0;
                 break;
         }
+        REG_RMW(ah, AR_STA_ID1, set, mask);
 }
 
 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
@@ -987,10 +1075,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
         u32 tmpReg;
 
         if (AR_SREV_9100(ah)) {
-                u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
-                val &= ~AR_RTC_DERIVED_CLK_PERIOD;
-                val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
-                REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
+                REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
+                              AR_RTC_DERIVED_CLK_PERIOD, 1);
                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
         }
 
@@ -1031,14 +1117,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
         REG_WRITE(ah, AR_RTC_RC, rst_flags);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         udelay(50);
 
         REG_WRITE(ah, AR_RTC_RC, 0);
         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "RTC stuck in MAC reset\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "RTC stuck in MAC reset\n");
                 return false;
         }
 
@@ -1067,10 +1152,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
 
         REG_WRITE(ah, AR_RTC_RESET, 0);
-        udelay(2);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         if (!AR_SREV_9300_20_OR_LATER(ah))
                 udelay(2);
@@ -1085,13 +1168,11 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
                            AR_RTC_STATUS_M,
                            AR_RTC_STATUS_ON,
                            AH_WAIT_TIMEOUT)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "RTC not waking up\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "RTC not waking up\n");
                 return false;
         }
 
-        ath9k_hw_read_revisions(ah);
-
         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
 }
 
@@ -1146,16 +1227,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
 
         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
                 if (ath9k_hw_numtxpending(ah, qnum)) {
-                        ath_print(common, ATH_DBG_QUEUE,
-                                  "Transmit frames pending on "
-                                  "queue %d\n", qnum);
+                        ath_dbg(common, ATH_DBG_QUEUE,
+                                "Transmit frames pending on queue %d\n", qnum);
                         return false;
                 }
         }
 
         if (!ath9k_hw_rfbus_req(ah)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Could not kill baseband RX\n");
+                ath_err(common, "Could not kill baseband RX\n");
                 return false;
         }
 
@@ -1163,17 +1242,17 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
 
         r = ath9k_hw_rf_set_freq(ah, chan);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to set channel\n");
+                ath_err(common, "Failed to set channel\n");
                 return false;
         }
+        ath9k_hw_set_clockrate(ah);
 
         ah->eep_ops->set_txpower(ah, chan,
                              ath9k_regd_get_ctl(regulatory, chan),
                              channel->max_antenna_gain * 2,
                              channel->max_power * 2,
                              min((u32) MAX_RATE_POWER,
-                             (u32) regulatory->power_limit));
+                             (u32) regulatory->power_limit), false);
 
         ath9k_hw_rfbus_done(ah);
 
@@ -1185,12 +1264,26 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
         return true;
 }
 
+static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
+{
+        u32 gpio_mask = ah->gpio_mask;
+        int i;
+
+        for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
+                if (!(gpio_mask & 1))
+                        continue;
+
+                ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+                ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
+        }
+}
+
 bool ath9k_hw_check_alive(struct ath_hw *ah)
 {
         int count = 50;
         u32 reg;
 
-        if (AR_SREV_9285_10_OR_LATER(ah))
+        if (AR_SREV_9285_12_OR_LATER(ah))
                 return true;
 
         do {
@@ -1227,19 +1320,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ah->txchainmask = common->tx_chainmask;
         ah->rxchainmask = common->rx_chainmask;
 
-        if (!ah->chip_fullsleep) {
-                ath9k_hw_abortpcurecv(ah);
-                if (!ath9k_hw_stopdmarecv(ah)) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                "Failed to stop receive dma\n");
-                        bChannelChange = false;
-                }
-        }
-
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                 return -EIO;
 
-        if (curchan && !ah->chip_fullsleep && ah->caldata)
+        if (curchan && !ah->chip_fullsleep)
                 ath9k_hw_getnf(ah, curchan);
 
         ah->caldata = caldata;
@@ -1258,11 +1342,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
             (chan->channel != ah->curchan->channel) &&
             ((chan->channelFlags & CHANNEL_ALL) ==
              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
-            !AR_SREV_9280(ah)) {
+            (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
 
                 if (ath9k_hw_channel_change(ah, chan)) {
                         ath9k_hw_loadnf(ah, ah->curchan);
                         ath9k_hw_start_nfcal(ah, true);
+                        if (AR_SREV_9271(ah))
+                                ar9002_hw_load_ani_reg(ah, chan);
                         return 0;
                 }
         }
@@ -1284,6 +1370,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
         ath9k_hw_mark_phy_inactive(ah);
 
+        ah->paprd_table_write_done = false;
+
         /* Only required on the first reset */
         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
                 REG_WRITE(ah,
@@ -1293,7 +1381,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         }
 
         if (!ath9k_hw_chip_reset(ah, chan)) {
-                ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
+                ath_err(common, "Chip reset failed\n");
                 return -EINVAL;
         }
 
@@ -1310,7 +1398,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (tsf)
                 ath9k_hw_settsf64(ah, tsf);
 
-        if (AR_SREV_9280_10_OR_LATER(ah))
+        if (AR_SREV_9280_20_OR_LATER(ah))
                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
 
         if (!AR_SREV_9300_20_OR_LATER(ah))
@@ -1354,8 +1442,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ath9k_hw_spur_mitigate_freq(ah, chan);
         ah->eep_ops->set_board_values(ah, chan);
 
-        ath9k_hw_set_operating_mode(ah, ah->opmode);
-
         ENABLE_REGWRITE_BUFFER(ah);
 
         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
@@ -1372,22 +1458,24 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
+
+        ath9k_hw_set_operating_mode(ah, ah->opmode);
 
         r = ath9k_hw_rf_set_freq(ah, chan);
         if (r)
                 return r;
 
+        ath9k_hw_set_clockrate(ah);
+
         ENABLE_REGWRITE_BUFFER(ah);
 
         for (i = 0; i < AR_NUM_DCU; i++)
                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         ah->intr_txqs = 0;
-        for (i = 0; i < ah->caps.total_queues; i++)
+        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
                 ath9k_hw_resettxqueue(ah, i);
 
         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
@@ -1395,7 +1483,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ath9k_hw_init_qos(ah);
 
         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
-                ath9k_enable_rfkill(ah);
+                ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 
         ath9k_hw_init_global_settings(ah);
 
@@ -1404,8 +1492,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 ar9002_hw_enable_wep_aggregation(ah);
         }
 
-        REG_WRITE(ah, AR_STA_ID1,
-                  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
+        REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
 
         ath9k_hw_set_dma(ah);
 
@@ -1432,7 +1519,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         /*
          * For big endian systems turn on swapping for descriptors
@@ -1441,13 +1527,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 u32 mask;
                 mask = REG_READ(ah, AR_CFG);
                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
-                        ath_print(common, ATH_DBG_RESET,
+                        ath_dbg(common, ATH_DBG_RESET,
                                 "CFG Byte Swap Set 0x%x\n", mask);
                 } else {
                         mask =
                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
                         REG_WRITE(ah, AR_CFG, mask);
-                        ath_print(common, ATH_DBG_RESET,
+                        ath_dbg(common, ATH_DBG_RESET,
                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
                 }
         } else {
@@ -1459,7 +1545,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
                 }
 #ifdef __BIG_ENDIAN
-                else
+                else if (AR_SREV_9340(ah))
+                        REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
+                else
                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
 #endif
         }
@@ -1467,289 +1555,17 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (ah->btcoex_hw.enabled)
                 ath9k_hw_btcoex_enable(ah);
 
-        if (AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
                 ar9003_hw_bb_watchdog_config(ah);
 
-        return 0;
-}
-EXPORT_SYMBOL(ath9k_hw_reset);
-
-/************************/
-/* Key Cache Management */
-/************************/
-
-bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
-{
-        u32 keyType;
-
-        if (entry >= ah->caps.keycache_size) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "keychache entry %u out of range\n", entry);
-                return false;
+                ar9003_hw_disable_phy_restart(ah);
         }
 
-        keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
+        ath9k_hw_apply_gpio_override(ah);
 
-        REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
-        REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
-        REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
-
-        if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
-                u16 micentry = entry + 64;
-
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
-
-        }
-
-        return true;
-}
-EXPORT_SYMBOL(ath9k_hw_keyreset);
-
-static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
-{
-        u32 macHi, macLo;
-        u32 unicast_flag = AR_KEYTABLE_VALID;
-
-        if (entry >= ah->caps.keycache_size) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "keychache entry %u out of range\n", entry);
-                return false;
-        }
-
-        if (mac != NULL) {
-                /*
-                 * AR_KEYTABLE_VALID indicates that the address is a unicast
-                 * address, which must match the transmitter address for
-                 * decrypting frames.
-                 * Not setting this bit allows the hardware to use the key
-                 * for multicast frame decryption.
-                 */
-                if (mac[0] & 0x01)
-                        unicast_flag = 0;
-
-                macHi = (mac[5] << 8) | mac[4];
-                macLo = (mac[3] << 24) |
-                        (mac[2] << 16) |
-                        (mac[1] << 8) |
-                        mac[0];
-                macLo >>= 1;
-                macLo |= (macHi & 1) << 31;
-                macHi >>= 1;
-        } else {
-                macLo = macHi = 0;
-        }
-        REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
-        REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
-
-        return true;
-}
-
-bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
-                                 const struct ath9k_keyval *k,
-                                 const u8 *mac)
-{
-        const struct ath9k_hw_capabilities *pCap = &ah->caps;
-        struct ath_common *common = ath9k_hw_common(ah);
-        u32 key0, key1, key2, key3, key4;
-        u32 keyType;
-
-        if (entry >= pCap->keycache_size) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "keycache entry %u out of range\n", entry);
-                return false;
-        }
-
-        switch (k->kv_type) {
-        case ATH9K_CIPHER_AES_OCB:
-                keyType = AR_KEYTABLE_TYPE_AES;
-                break;
-        case ATH9K_CIPHER_AES_CCM:
-                if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "AES-CCM not supported by mac rev 0x%x\n",
-                                  ah->hw_version.macRev);
-                        return false;
-                }
-                keyType = AR_KEYTABLE_TYPE_CCM;
-                break;
-        case ATH9K_CIPHER_TKIP:
-                keyType = AR_KEYTABLE_TYPE_TKIP;
-                if (ATH9K_IS_MIC_ENABLED(ah)
-                    && entry + 64 >= pCap->keycache_size) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "entry %u inappropriate for TKIP\n", entry);
-                        return false;
-                }
-                break;
-        case ATH9K_CIPHER_WEP:
-                if (k->kv_len < WLAN_KEY_LEN_WEP40) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "WEP key length %u too small\n", k->kv_len);
-                        return false;
-                }
-                if (k->kv_len <= WLAN_KEY_LEN_WEP40)
-                        keyType = AR_KEYTABLE_TYPE_40;
-                else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
-                        keyType = AR_KEYTABLE_TYPE_104;
-                else
-                        keyType = AR_KEYTABLE_TYPE_128;
-                break;
-        case ATH9K_CIPHER_CLR:
-                keyType = AR_KEYTABLE_TYPE_CLR;
-                break;
-        default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "cipher %u not supported\n", k->kv_type);
-                return false;
-        }
-
-        key0 = get_unaligned_le32(k->kv_val + 0);
-        key1 = get_unaligned_le16(k->kv_val + 4);
-        key2 = get_unaligned_le32(k->kv_val + 6);
-        key3 = get_unaligned_le16(k->kv_val + 10);
-        key4 = get_unaligned_le32(k->kv_val + 12);
-        if (k->kv_len <= WLAN_KEY_LEN_WEP104)
-                key4 &= 0xff;
-
-        /*
-         * Note: Key cache registers access special memory area that requires
-         * two 32-bit writes to actually update the values in the internal
-         * memory. Consequently, the exact order and pairs used here must be
-         * maintained.
-         */
-
-        if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
-                u16 micentry = entry + 64;
-
-                /*
-                 * Write inverted key[47:0] first to avoid Michael MIC errors
-                 * on frames that could be sent or received at the same time.
-                 * The correct key will be written in the end once everything
-                 * else is ready.
-                 */
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
-
-                /* Write key[95:48] */
-                REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
-                REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
-
-                /* Write key[127:96] and key type */
-                REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
-                REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
-
-                /* Write MAC address for the entry */
-                (void) ath9k_hw_keysetmac(ah, entry, mac);
-
-                if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
-                        /*
-                         * TKIP uses two key cache entries:
-                         * Michael MIC TX/RX keys in the same key cache entry
-                         * (idx = main index + 64):
-                         * key0 [31:0] = RX key [31:0]
-                         * key1 [15:0] = TX key [31:16]
-                         * key1 [31:16] = reserved
-                         * key2 [31:0] = RX key [63:32]
-                         * key3 [15:0] = TX key [15:0]
-                         * key3 [31:16] = reserved
-                         * key4 [31:0] = TX key [63:32]
-                         */
-                        u32 mic0, mic1, mic2, mic3, mic4;
-
-                        mic0 = get_unaligned_le32(k->kv_mic + 0);
-                        mic2 = get_unaligned_le32(k->kv_mic + 4);
-                        mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
-                        mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
-                        mic4 = get_unaligned_le32(k->kv_txmic + 4);
-
-                        /* Write RX[31:0] and TX[31:16] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
-
-                        /* Write RX[63:32] and TX[15:0] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
-
-                        /* Write TX[63:32] and keyType(reserved) */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
-                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
-                                  AR_KEYTABLE_TYPE_CLR);
-
-                } else {
-                        /*
-                         * TKIP uses four key cache entries (two for group
-                         * keys):
-                         * Michael MIC TX/RX keys are in different key cache
-                         * entries (idx = main index + 64 for TX and
-                         * main index + 32 + 96 for RX):
-                         * key0 [31:0] = TX/RX MIC key [31:0]
-                         * key1 [31:0] = reserved
-                         * key2 [31:0] = TX/RX MIC key [63:32]
-                         * key3 [31:0] = reserved
-                         * key4 [31:0] = reserved
-                         *
-                         * Upper layer code will call this function separately
-                         * for TX and RX keys when these registers offsets are
-                         * used.
-                         */
-                        u32 mic0, mic2;
-
-                        mic0 = get_unaligned_le32(k->kv_mic + 0);
-                        mic2 = get_unaligned_le32(k->kv_mic + 4);
-
-                        /* Write MIC key[31:0] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
-
-                        /* Write MIC key[63:32] */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
-                        REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
-
-                        /* Write TX[63:32] and keyType(reserved) */
-                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
-                        REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
-                                  AR_KEYTABLE_TYPE_CLR);
-                }
-
-                /* MAC address registers are reserved for the MIC entry */
-                REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
-                REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
-
-                /*
-                 * Write the correct (un-inverted) key[47:0] last to enable
-                 * TKIP now that all other registers are set with correct
-                 * values.
-                 */
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
-        } else {
-                /* Write key[47:0] */
-                REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
-                REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
-
-                /* Write key[95:48] */
-                REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
-                REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
-
-                /* Write key[127:96] and key type */
-                REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
-                REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
-
-                /* Write MAC address for the entry */
-                (void) ath9k_hw_keysetmac(ah, entry, mac);
-        }
-
-        return true;
+        return 0;
 }
-EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
+EXPORT_SYMBOL(ath9k_hw_reset);
 
 /******************************/
 /* Power Management (Chipset) */
@@ -1852,9 +1668,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
                                     AR_RTC_FORCE_WAKE_EN);
                 }
                 if (i == 0) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "Failed to wakeup in %uus\n",
-                                  POWER_UP_TIME / 20);
+                        ath_err(ath9k_hw_common(ah),
+                                "Failed to wakeup in %uus\n",
+                                POWER_UP_TIME / 20);
                         return false;
                 }
         }
@@ -1878,8 +1694,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
         if (ah->power_mode == mode)
                 return status;
 
-        ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
-                  modes[ah->power_mode], modes[mode]);
+        ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
+                modes[ah->power_mode], modes[mode]);
 
         switch (mode) {
         case ATH9K_PM_AWAKE:
@@ -1893,12 +1709,20 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
                 ath9k_set_power_network_sleep(ah, setChip);
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unknown power mode %u\n", mode);
+                ath_err(common, "Unknown power mode %u\n", mode);
                 return false;
         }
         ah->power_mode = mode;
 
+        /*
+         * XXX: If this warning never comes up after a while then
+         * simply keep the ATH_DBG_WARN_ON_ONCE() but make
+         * ath9k_hw_setpower() return type void.
+         */
+
+        if (!(ah->ah_flags & AH_UNPLUGGED))
+                ATH_DBG_WARN_ON_ONCE(!status);
+
         return status;
 }
 EXPORT_SYMBOL(ath9k_hw_setpower);
@@ -1911,60 +1735,39 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
 {
         int flags = 0;
 
-        ah->beacon_interval = beacon_period;
-
         ENABLE_REGWRITE_BUFFER(ah);
 
         switch (ah->opmode) {
-        case NL80211_IFTYPE_STATION:
-        case NL80211_IFTYPE_MONITOR:
-                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
-                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
-                REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
-                flags |= AR_TBTT_TIMER_EN;
-                break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
                 REG_SET_BIT(ah, AR_TXCFG,
                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
-                REG_WRITE(ah, AR_NEXT_NDP_TIMER,
-                          TU_TO_USEC(next_beacon +
-                                     (ah->atim_window ? ah->
-                                      atim_window : 1)));
+                REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
+                          TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
                 flags |= AR_NDP_TIMER_EN;
         case NL80211_IFTYPE_AP:
-                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
-                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
-                          TU_TO_USEC(next_beacon -
-                                     ah->config.
-                                     dma_beacon_response_time));
-                REG_WRITE(ah, AR_NEXT_SWBA,
-                          TU_TO_USEC(next_beacon -
-                                     ah->config.
-                                     sw_beacon_response_time));
+                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
+                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
+                          TU_TO_USEC(ah->config.dma_beacon_response_time));
+                REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
+                          TU_TO_USEC(ah->config.sw_beacon_response_time));
                 flags |=
                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
-                          "%s: unsupported opmode: %d\n",
-                          __func__, ah->opmode);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
+                        "%s: unsupported opmode: %d\n",
+                        __func__, ah->opmode);
                 return;
                 break;
         }
 
-        REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
-        REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
-        REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
-        REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
+        REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
+        REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
+        REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
+        REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
-
-        beacon_period &= ~ATH9K_BEACON_ENA;
-        if (beacon_period & ATH9K_BEACON_RESET_TSF) {
-                ath9k_hw_reset_tsf(ah);
-        }
 
         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
 }
@@ -1987,7 +1790,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         REG_RMW_FIELD(ah, AR_RSSI_THR,
                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
@@ -2006,10 +1808,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
         else
                 nextTbtt = bs->bs_nexttbtt;
 
-        ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
-        ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
-        ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
-        ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
+        ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
+        ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
+        ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
+        ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -2033,7 +1835,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
         REG_SET_BIT(ah, AR_TIMER_MODE,
                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
@@ -2055,18 +1856,17 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
-        u16 capField = 0, eeval;
+        u16 eeval;
+        u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
         regulatory->current_rd = eeval;
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
-        if (AR_SREV_9285_10_OR_LATER(ah))
+        if (AR_SREV_9285_12_OR_LATER(ah))
                 eeval |= AR9285_RDEXT_DEFAULT;
         regulatory->current_rd_ext = eeval;
 
-        capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
-
         if (ah->opmode != NL80211_IFTYPE_AP &&
             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
                 if (regulatory->current_rd == 0x64 ||
@@ -2074,48 +1874,22 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                         regulatory->current_rd += 5;
                 else if (regulatory->current_rd == 0x41)
                         regulatory->current_rd = 0x43;
-                ath_print(common, ATH_DBG_REGULATORY,
-                          "regdomain mapped to 0x%x\n", regulatory->current_rd);
+                ath_dbg(common, ATH_DBG_REGULATORY,
+                        "regdomain mapped to 0x%x\n", regulatory->current_rd);
         }
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "no band has been marked as supported in EEPROM.\n");
+                ath_err(common,
+                        "no band has been marked as supported in EEPROM\n");
                 return -EINVAL;
         }
 
-        bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
+        if (eeval & AR5416_OPFLAGS_11A)
+                pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
 
-        if (eeval & AR5416_OPFLAGS_11A) {
-                set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
-                if (ah->config.ht_enable) {
-                        if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
-                                set_bit(ATH9K_MODE_11NA_HT20,
-                                        pCap->wireless_modes);
-                        if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
-                                set_bit(ATH9K_MODE_11NA_HT40PLUS,
-                                        pCap->wireless_modes);
-                                set_bit(ATH9K_MODE_11NA_HT40MINUS,
-                                        pCap->wireless_modes);
-                        }
-                }
-        }
-
-        if (eeval & AR5416_OPFLAGS_11G) {
-                set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
-                if (ah->config.ht_enable) {
-                        if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
-                                set_bit(ATH9K_MODE_11NG_HT20,
-                                        pCap->wireless_modes);
-                        if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
-                                set_bit(ATH9K_MODE_11NG_HT40PLUS,
-                                        pCap->wireless_modes);
-                                set_bit(ATH9K_MODE_11NG_HT40MINUS,
-                                        pCap->wireless_modes);
-                        }
-                }
-        }
+        if (eeval & AR5416_OPFLAGS_11G)
+                pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
 
         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
         /*
@@ -2127,63 +1901,32 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
             !(AR_SREV_9271(ah)))
                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
+        else if (AR_SREV_9100(ah))
+                pCap->rx_chainmask = 0x7;
         else
                 /* Use rx_chainmask from EEPROM. */
                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
 
-        if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
-                ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
+        ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
 
-        pCap->low_2ghz_chan = 2312;
-        pCap->high_2ghz_chan = 2732;
-
-        pCap->low_5ghz_chan = 4920;
-        pCap->high_5ghz_chan = 6100;
-
-        pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
+        /* enable key search for every frame in an aggregate */
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
 
-        pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
-        pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
+        common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
 
-        if (ah->config.ht_enable)
+        if (ah->hw_version.devid != AR2427_DEVID_PCIE)
                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
         else
                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
 
-        pCap->hw_caps |= ATH9K_HW_CAP_GTT;
-        pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
-        pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
-        pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
-
-        if (capField & AR_EEPROM_EEPCAP_MAXQCU)
-                pCap->total_queues =
-                        MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
-        else
-                pCap->total_queues = ATH9K_NUM_TX_QUEUES;
-
-        if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
-                pCap->keycache_size =
-                        1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
-        else
-                pCap->keycache_size = AR_KEYTABLE_SIZE;
-
-        pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
-
-        if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
-                pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
-        else
-                pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
-
         if (AR_SREV_9271(ah))
                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
         else if (AR_DEVID_7010(ah))
                 pCap->num_gpio_pins = AR7010_NUM_GPIO;
-        else if (AR_SREV_9285_10_OR_LATER(ah))
+        else if (AR_SREV_9285_12_OR_LATER(ah))
                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
-        else if (AR_SREV_9280_10_OR_LATER(ah))
+        else if (AR_SREV_9280_20_OR_LATER(ah))
                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
         else
                 pCap->num_gpio_pins = AR_NUM_GPIO;
@@ -2195,8 +1938,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                 pCap->rts_aggr_limit = (8 * 1024);
         }
 
-        pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
-
 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
@@ -2218,52 +1959,40 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         else
                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
 
-        if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
-                pCap->reg_cap =
-                        AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
-                        AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
-                        AR_EEPROM_EEREGCAP_EN_KK_U2 |
-                        AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
-        } else {
-                pCap->reg_cap =
-                        AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
-                        AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
-        }
-
-        /* Advertise midband for AR5416 with FCC midband set in eeprom */
-        if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
-            AR_SREV_5416(ah))
-                pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
-
-        pCap->num_antcfg_5ghz =
-                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
-        pCap->num_antcfg_2ghz =
-                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
-
-        if (AR_SREV_9280_10_OR_LATER(ah) &&
-            ath9k_hw_btcoex_supported(ah)) {
-                btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
-                btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
-
-                if (AR_SREV_9285(ah)) {
+        if (common->btcoex_enabled) {
+                if (AR_SREV_9300_20_OR_LATER(ah)) {
                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
-                        btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
-                } else {
-                        btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
+                        btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
+                        btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
+                        btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
+                } else if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
+                        btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
+
+                        if (AR_SREV_9285(ah)) {
+                                btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
+                                btcoex_hw->btpriority_gpio =
+                                                ATH_BTPRIORITY_GPIO_9285;
+                        } else {
+                                btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
+                        }
                 }
         } else {
                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
         }
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
-                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
-                                 ATH9K_HW_CAP_FASTCLOCK;
+                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
+                if (!AR_SREV_9485(ah))
+                        pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
+
                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
                 pCap->txs_len = sizeof(struct ar9003_txs);
-                if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
+                if (!ah->config.paprd_disable &&
+                    ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
                         pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
         } else {
                 pCap->tx_desc_len = sizeof(struct ath_desc);
@@ -2277,9 +2006,59 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         if (AR_SREV_9300_20_OR_LATER(ah))
                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
 
-        if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
+
+        if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
 
+        if (AR_SREV_9285(ah))
+                if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
+                        ant_div_ctl1 =
+                                ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                        if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
+                                pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
+                }
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
+                        pCap->hw_caps |= ATH9K_HW_CAP_APM;
+        }
+
+
+        if (AR_SREV_9485(ah)) {
+                ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                /*
+                 * enable the diversity-combining algorithm only when
+                 * both enable_lna_div and enable_fast_div are set
+                 *              Table for Diversity
+                 * ant_div_alt_lnaconf          bit 0-1
+                 * ant_div_main_lnaconf         bit 2-3
+                 * ant_div_alt_gaintb           bit 4
+                 * ant_div_main_gaintb          bit 5
+                 * enable_ant_div_lnadiv        bit 6
+                 * enable_ant_fast_div          bit 7
+                 */
+                if ((ant_div_ctl1 >> 0x6) == 0x3)
+                        pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
+        }
+
+        if (AR_SREV_9485_10(ah)) {
+                pCap->pcie_lcr_extsync_en = true;
+                pCap->pcie_lcr_offset = 0x80;
+        }
+
+        tx_chainmask = pCap->tx_chainmask;
+        rx_chainmask = pCap->rx_chainmask;
+        while (tx_chainmask || rx_chainmask) {
+                if (tx_chainmask & BIT(0))
+                        pCap->max_txchains++;
+                if (rx_chainmask & BIT(0))
+                        pCap->max_rxchains++;
+
+                tx_chainmask >>= 1;
+                rx_chainmask >>= 1;
+        }
+
         return 0;
 }
 
@@ -2350,14 +2129,15 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
                 val = REG_READ(ah, AR7010_GPIO_IN);
                 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
         } else if (AR_SREV_9300_20_OR_LATER(ah))
-                return MS_REG_READ(AR9300, gpio) != 0;
+                return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
+                        AR_GPIO_BIT(gpio)) != 0;
         else if (AR_SREV_9271(ah))
                 return MS_REG_READ(AR9271, gpio) != 0;
-        else if (AR_SREV_9287_10_OR_LATER(ah))
+        else if (AR_SREV_9287_11_OR_LATER(ah))
                 return MS_REG_READ(AR9287, gpio) != 0;
-        else if (AR_SREV_9285_10_OR_LATER(ah))
+        else if (AR_SREV_9285_12_OR_LATER(ah))
                 return MS_REG_READ(AR9285, gpio) != 0;
-        else if (AR_SREV_9280_10_OR_LATER(ah))
+        else if (AR_SREV_9280_20_OR_LATER(ah))
                 return MS_REG_READ(AR928X, gpio) != 0;
         else
                 return MS_REG_READ(AR, gpio) != 0;
@@ -2449,14 +2229,11 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
         REG_WRITE(ah, AR_PHY_ERR, phybits);
 
         if (phybits)
-                REG_WRITE(ah, AR_RXCFG,
-                          REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+                REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
         else
-                REG_WRITE(ah, AR_RXCFG,
-                          REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
+                REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
 
@@ -2483,7 +2260,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_disable);
 
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath9k_channel *chan = ah->curchan;
@@ -2496,7 +2273,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), test);
 }
 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
 
@@ -2556,8 +2333,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
 {
         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
                            AH_TSF_WRITE_TIMEOUT))
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
 
         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
 }
@@ -2648,9 +2425,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
 
         if (timer == NULL) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Failed to allocate memory"
-                          "for hw timer[%d]\n", timer_index);
+                ath_err(ath9k_hw_common(ah),
+                        "Failed to allocate memory for hw timer[%d]\n",
+                        timer_index);
                 return NULL;
         }
 
@@ -2667,11 +2444,11 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
 
 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
                               struct ath_gen_timer *timer,
-                              u32 timer_next,
+                              u32 trig_timeout,
                               u32 timer_period)
 {
         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
-        u32 tsf;
+        u32 tsf, timer_next;
 
         BUG_ON(!timer_period);
 
@@ -2679,16 +2456,11 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 
         tsf = ath9k_hw_gettsf32(ah);
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
-                  "curent tsf %x period %x"
-                  "timer_next %x\n", tsf, timer_period, timer_next);
+        timer_next = tsf + trig_timeout;
 
-        /*
-         * Pull timer_next forward if the current TSF already passed it
-         * because of software latency
-         */
-        if (timer_next < tsf)
-                timer_next = tsf + timer_period;
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
+                "current tsf %x period %x timer_next %x\n",
+                tsf, timer_period, timer_next);
 
         /*
          * Program generic timer registers
@@ -2761,8 +2533,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
                 index = rightmost_index(timer_table, &thresh_mask);
                 timer = timer_table->timers[index];
                 BUG_ON(!timer);
-                ath_print(common, ATH_DBG_HWTIMER,
-                          "TSF overflow for Gen timer %d\n", index);
+                ath_dbg(common, ATH_DBG_HWTIMER,
+                        "TSF overflow for Gen timer %d\n", index);
                 timer->overflow(timer->arg);
         }
 
@@ -2770,8 +2542,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
                 index = rightmost_index(timer_table, &trigger_mask);
                 timer = timer_table->timers[index];
                 BUG_ON(!timer);
-                ath_print(common, ATH_DBG_HWTIMER,
-                          "Gen timer[%d] trigger\n", index);
+                ath_dbg(common, ATH_DBG_HWTIMER,
+                        "Gen timer[%d] trigger\n", index);
                 timer->trigger(timer->arg);
         }
 }
@@ -2802,6 +2574,7 @@ static struct {
         { AR_SREV_VERSION_9287,         "9287" },
         { AR_SREV_VERSION_9271,         "9271" },
         { AR_SREV_VERSION_9300,         "9300" },
+        { AR_SREV_VERSION_9485,         "9485" },
 };
 
 /* For devices with external radios */
@@ -2854,7 +2627,7 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
         int used;
 
         /* chipsets >= AR9280 are single-chip */
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 used = snprintf(hw_name, len,
                                "Atheros AR%s Rev:%x",
                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 399f7c1283cd..4b157c53d1a8 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -30,7 +30,6 @@
 #include "btcoex.h"
 
 #include "../regd.h"
-#include "../debug.h"
 
 #define ATHEROS_VENDOR_ID       0x168c
 
@@ -44,6 +43,8 @@
 #define AR9287_DEVID_PCI        0x002d
 #define AR9287_DEVID_PCIE       0x002e
 #define AR9300_DEVID_PCIE       0x0030
+#define AR9300_DEVID_AR9340     0x0031
+#define AR9300_DEVID_AR9485_PCIE 0x0032
 
 #define AR5416_AR9100_DEVID     0x000b
 
@@ -55,64 +56,62 @@
 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
 
+#define AR9300_NUM_BT_WEIGHTS   4
+#define AR9300_NUM_WLAN_WEIGHTS 4
+
 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 
 #define ATH_DEFAULT_NOISE_FLOOR -95
 
 #define ATH9K_RSSI_BAD                  -128
 
+#define ATH9K_NUM_CHANNELS      38
+
 /* Register read/write primitives */
 #define REG_WRITE(_ah, _reg, _val) \
-        ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
+        (_ah)->reg_ops.write((_ah), (_val), (_reg))
 
 #define REG_READ(_ah, _reg) \
-        ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
+        (_ah)->reg_ops.read((_ah), (_reg))
 
-#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
-        do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
-        } while (0)
+#define REG_READ_MULTI(_ah, _addr, _val, _cnt)          \
+        (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
+
+#define REG_RMW(_ah, _reg, _set, _clr) \
+        (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
 
-#define DISABLE_REGWRITE_BUFFER(_ah)                                    \
+#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
         do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
+                if ((_ah)->reg_ops.enable_write_buffer) \
+                        (_ah)->reg_ops.enable_write_buffer((_ah)); \
         } while (0)
 
 #define REGWRITE_BUFFER_FLUSH(_ah)                                      \
         do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->write_flush((_ah));  \
+                if ((_ah)->reg_ops.write_flush)         \
+                        (_ah)->reg_ops.write_flush((_ah));      \
         } while (0)
 
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
-#define REG_RMW(_a, _r, _set, _clr)    \
-        REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
 #define REG_RMW_FIELD(_a, _r, _f, _v) \
-        REG_WRITE(_a, _r, \
-        (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
+        REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
 #define REG_READ_FIELD(_a, _r, _f) \
         (((REG_READ(_a, _r) & _f) >> _f##_S))
 #define REG_SET_BIT(_a, _r, _f) \
-        REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
+        REG_RMW(_a, _r, (_f), 0)
 #define REG_CLR_BIT(_a, _r, _f) \
-        REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
+        REG_RMW(_a, _r, 0, (_f))
 
-#define DO_DELAY(x) do {                        \
-                if ((++(x) % 64) == 0)          \
-                        udelay(1);              \
+#define DO_DELAY(x) do {                                        \
+                if (((++(x) % 64) == 0) &&                      \
+                    (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
+                        != ATH_USB))                            \
+                        udelay(1);                              \
         } while (0)
 
-#define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
-                int r;                                                  \
-                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
-                        REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
-                                  INI_RA((iniarray), r, (column)));     \
-                        DO_DELAY(regWr);                                \
-                }                                                       \
-        } while (0)
+#define REG_WRITE_ARRAY(iniarray, column, regWr) \
+        ath9k_hw_write_array(ah, iniarray, column, &(regWr))
 
 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
@@ -126,7 +125,7 @@
 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 
 #define BASE_ACTIVATE_DELAY         100
-#define RTC_PLL_SETTLE_DELAY        100
+#define RTC_PLL_SETTLE_DELAY        (AR_SREV_9340(ah) ? 1000 : 100)
 #define COEF_SCALE_S                24
 #define HT40_CHANNEL_CENTER_SHIFT   10
 
@@ -161,6 +160,13 @@
 #define PAPRD_GAIN_TABLE_ENTRIES    32
 #define PAPRD_TABLE_SZ              24
 
+enum ath_hw_txq_subtype {
+        ATH_TXQ_AC_BE = 0,
+        ATH_TXQ_AC_BK = 1,
+        ATH_TXQ_AC_VI = 2,
+        ATH_TXQ_AC_VO = 3,
+};
+
 enum ath_ini_subsys {
         ATH_INI_PRE = 0,
         ATH_INI_CORE,
@@ -168,64 +174,39 @@ enum ath_ini_subsys {
         ATH_INI_NUM_SPLIT,
 };
 
-enum wireless_mode {
-        ATH9K_MODE_11A = 0,
-        ATH9K_MODE_11G,
-        ATH9K_MODE_11NA_HT20,
-        ATH9K_MODE_11NG_HT20,
-        ATH9K_MODE_11NA_HT40PLUS,
-        ATH9K_MODE_11NA_HT40MINUS,
-        ATH9K_MODE_11NG_HT40PLUS,
-        ATH9K_MODE_11NG_HT40MINUS,
-        ATH9K_MODE_MAX,
-};
-
 enum ath9k_hw_caps {
-        ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
-        ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
-        ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
-        ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
-        ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
-        ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
-        ATH9K_HW_CAP_VEOL                       = BIT(6),
-        ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
-        ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
-        ATH9K_HW_CAP_HT                         = BIT(9),
-        ATH9K_HW_CAP_GTT                        = BIT(10),
-        ATH9K_HW_CAP_FASTCC                     = BIT(11),
-        ATH9K_HW_CAP_RFSILENT                   = BIT(12),
-        ATH9K_HW_CAP_CST                        = BIT(13),
-        ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
-        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
-        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
-        ATH9K_HW_CAP_EDMA                       = BIT(17),
-        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(18),
-        ATH9K_HW_CAP_LDPC                       = BIT(19),
-        ATH9K_HW_CAP_FASTCLOCK                  = BIT(20),
-        ATH9K_HW_CAP_SGI_20                     = BIT(21),
-        ATH9K_HW_CAP_PAPRD                      = BIT(22),
+        ATH9K_HW_CAP_HT                         = BIT(0),
+        ATH9K_HW_CAP_RFSILENT                   = BIT(1),
+        ATH9K_HW_CAP_CST                        = BIT(2),
+        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
+        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
+        ATH9K_HW_CAP_EDMA                       = BIT(6),
+        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(7),
+        ATH9K_HW_CAP_LDPC                       = BIT(8),
+        ATH9K_HW_CAP_FASTCLOCK                  = BIT(9),
+        ATH9K_HW_CAP_SGI_20                     = BIT(10),
+        ATH9K_HW_CAP_PAPRD                      = BIT(11),
+        ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
+        ATH9K_HW_CAP_2GHZ                       = BIT(13),
+        ATH9K_HW_CAP_5GHZ                       = BIT(14),
+        ATH9K_HW_CAP_APM                        = BIT(15),
 };
 
 struct ath9k_hw_capabilities {
         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
-        DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
-        u16 total_queues;
-        u16 keycache_size;
-        u16 low_5ghz_chan, high_5ghz_chan;
-        u16 low_2ghz_chan, high_2ghz_chan;
         u16 rts_aggr_limit;
         u8 tx_chainmask;
         u8 rx_chainmask;
-        u16 tx_triglevel_max;
-        u16 reg_cap;
+        u8 max_txchains;
+        u8 max_rxchains;
         u8 num_gpio_pins;
-        u8 num_antcfg_2ghz;
-        u8 num_antcfg_5ghz;
         u8 rx_hp_qdepth;
         u8 rx_lp_qdepth;
         u8 rx_status_len;
         u8 tx_desc_len;
         u8 txs_len;
+        u16 pcie_lcr_offset;
+        bool pcie_lcr_extsync_en;
 };
 
 struct ath9k_ops_config {
@@ -239,7 +220,7 @@ struct ath9k_ops_config {
         u8 pcie_clock_req;
         u32 pcie_waen;
         u8 analog_shiftreg;
-        u8 ht_enable;
+        u8 paprd_disable;
         u32 ofdm_trig_low;
         u32 ofdm_trig_high;
         u32 cck_trig_high;
@@ -251,7 +232,6 @@ struct ath9k_ops_config {
 #define SPUR_DISABLE            0
 #define SPUR_ENABLE_IOCTL       1
 #define SPUR_ENABLE_EEPROM      2
-#define AR_EEPROM_MODAL_SPURS   5
 #define AR_SPUR_5413_1          1640
 #define AR_SPUR_5413_2          1200
 #define AR_NO_SPUR              0x8000
@@ -352,9 +332,9 @@ struct ath9k_hw_cal_data {
         int32_t CalValid;
         int8_t iCoff;
         int8_t qCoff;
-        int16_t rawNoiseFloor;
         bool paprd_done;
         bool nfcal_pending;
+        bool nfcal_interference;
         u16 small_signal_gain[AR9300_MAX_CHAINS];
         u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
@@ -362,9 +342,11 @@ struct ath9k_hw_cal_data {
 
 struct ath9k_channel {
         struct ieee80211_channel *chan;
+        struct ar5416AniState ani;
         u16 channel;
         u32 channelFlags;
         u32 chanmode;
+        s16 noisefloor;
 };
 
 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
@@ -422,8 +404,6 @@ struct ath9k_beacon_state {
         u32 bs_nextdtim;
         u32 bs_intval;
 #define ATH9K_BEACON_PERIOD       0x0000ffff
-#define ATH9K_BEACON_ENA          0x00800000
-#define ATH9K_BEACON_RESET_TSF    0x01000000
 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
         u32 bs_dtimperiod;
         u16 bs_cfpperiod;
@@ -457,6 +437,7 @@ struct ath9k_hw_version {
         u16 analog5GhzRev;
         u16 analog2GhzRev;
         u16 subsysid;
+        enum ath_usb_dev usbdev;
 };
 
 /* Generic TSF timer definitions */
@@ -494,6 +475,50 @@ struct ath_gen_timer_table {
         } timer_mask;
 };
 
+struct ath_hw_antcomb_conf {
+        u8 main_lna_conf;
+        u8 alt_lna_conf;
+        u8 fast_div_bias;
+        u8 main_gaintb;
+        u8 alt_gaintb;
+        int lna1_lna2_delta;
+        u8 div_group;
+};
+
+/**
+ * struct ath_hw_radar_conf - radar detection initialization parameters
+ *
+ * @pulse_inband: threshold for checking the ratio of in-band power
+ *      to total power for short radar pulses (half dB steps)
+ * @pulse_inband_step: threshold for checking an in-band power to total
+ *      power ratio increase for short radar pulses (half dB steps)
+ * @pulse_height: threshold for detecting the beginning of a short
+ *      radar pulse (dB step)
+ * @pulse_rssi: threshold for detecting if a short radar pulse is
+ *      gone (dB step)
+ * @pulse_maxlen: maximum pulse length (0.8 us steps)
+ *
+ * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
+ * @radar_inband: threshold for checking the ratio of in-band power
+ *      to total power for long radar pulses (half dB steps)
+ * @fir_power: threshold for detecting the end of a long radar pulse (dB)
+ *
+ * @ext_channel: enable extension channel radar detection
+ */
+struct ath_hw_radar_conf {
+        unsigned int pulse_inband;
+        unsigned int pulse_inband_step;
+        unsigned int pulse_height;
+        unsigned int pulse_rssi;
+        unsigned int pulse_maxlen;
+
+        unsigned int radar_rssi;
+        unsigned int radar_inband;
+        int fir_power;
+
+        bool ext_channel;
+};
+
 /**
  * struct ath_hw_private_ops - callbacks used internally by hardware code
  *
@@ -505,7 +530,6 @@ struct ath_gen_timer_table {
  *
  * @init_mode_regs: Initializes mode registers
  * @init_mode_gain_regs: Initialize TX/RX gain registers
- * @macversion_supported: If this specific mac revision is supported
  *
  * @rf_set_freq: change frequency
  * @spur_mitigate_freq: spur mitigation
@@ -517,14 +541,6 @@ struct ath_gen_timer_table {
  * @setup_calibration: set up calibration
  * @iscal_supported: used to query if a type of calibration is supported
  *
- * @ani_reset: reset ANI parameters to default values
- * @ani_lower_immunity: lower the noise immunity level. The level controls
- *      the power-based packet detection on hardware. If a power jump is
- *      detected the adapter takes it as an indication that a packet has
- *      arrived. The level ranges from 0-5. Each level corresponds to a
- *      few dB more of noise immunity. If you have a strong time-varying
- *      interference that is causing false detections (OFDM timing errors or
- *      CCK timing errors) the level can be increased.
  * @ani_cache_ini_regs: cache the values for ANI from the initial
  *      register settings through the register initialization.
  */
@@ -535,11 +551,8 @@ struct ath_hw_private_ops {
 
         void (*init_mode_regs)(struct ath_hw *ah);
         void (*init_mode_gain_regs)(struct ath_hw *ah);
-        bool (*macversion_supported)(u32 macversion);
         void (*setup_calibration)(struct ath_hw *ah,
                                   struct ath9k_cal_list *currCal);
-        bool (*iscal_supported)(struct ath_hw *ah,
-                                enum ath9k_cal_types calType);
 
         /* PHY ops */
         int (*rf_set_freq)(struct ath_hw *ah,
@@ -561,7 +574,6 @@ struct ath_hw_private_ops {
         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
         bool (*rfbus_req)(struct ath_hw *ah);
         void (*rfbus_done)(struct ath_hw *ah);
-        void (*enable_rfkill)(struct ath_hw *ah);
         void (*restore_chainmask)(struct ath_hw *ah);
         void (*set_diversity)(struct ath_hw *ah, bool value);
         u32 (*compute_pll_control)(struct ath_hw *ah,
@@ -569,10 +581,10 @@ struct ath_hw_private_ops {
         bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
                             int param);
         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
+        void (*set_radar_params)(struct ath_hw *ah,
+                                 struct ath_hw_radar_conf *conf);
 
         /* ANI */
-        void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
-        void (*ani_lower_immunity)(struct ath_hw *ah);
         void (*ani_cache_ini_regs)(struct ath_hw *ah);
 };
 
@@ -584,11 +596,6 @@ struct ath_hw_private_ops {
  *
  * @config_pci_powersave:
  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
- *
- * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
- *      thresholds being reached or having overflowed.
- * @ani_monitor: called periodically by the core driver to collect
- *      MIB stats and adjust ANI if specific thresholds have been reached.
  */
 struct ath_hw_ops {
         void (*config_pci_powersave)(struct ath_hw *ah,
@@ -625,13 +632,12 @@ struct ath_hw_ops {
                                    u32 numDelims);
         void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
         void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
-        void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
-                                     u32 burstDuration);
-        void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
-                                       u32 vmf);
+        void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
+        void (*antdiv_comb_conf_get)(struct ath_hw *ah,
+                        struct ath_hw_antcomb_conf *antconf);
+        void (*antdiv_comb_conf_set)(struct ath_hw *ah,
+                        struct ath_hw_antcomb_conf *antconf);
 
-        void (*ani_proc_mib_event)(struct ath_hw *ah);
-        void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
 };
 
 struct ath_nf_limits {
@@ -640,13 +646,19 @@ struct ath_nf_limits {
         s16 nominal;
 };
 
+/* ah_flags */
+#define AH_USE_EEPROM   0x1
+#define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
+
 struct ath_hw {
+        struct ath_ops reg_ops;
+
         struct ieee80211_hw *hw;
         struct ath_common common;
         struct ath9k_hw_version hw_version;
         struct ath9k_ops_config config;
         struct ath9k_hw_capabilities caps;
-        struct ath9k_channel channels[38];
+        struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
         struct ath9k_channel *curchan;
 
         union {
@@ -659,6 +671,7 @@ struct ath_hw {
 
         bool sw_mgmt_crypto;
         bool is_pciexpress;
+        bool is_monitoring;
         bool need_an_top2_fixup;
         u16 tx_trig_level;
 
@@ -692,10 +705,9 @@ struct ath_hw {
         u32 atim_window;
 
         /* Calibration */
-        enum ath9k_cal_types supp_cals;
+        u32 supp_cals;
         struct ath9k_cal_list iq_caldata;
         struct ath9k_cal_list adcgain_caldata;
-        struct ath9k_cal_list adcdc_calinitdata;
         struct ath9k_cal_list adcdc_caldata;
         struct ath9k_cal_list tempCompCalData;
         struct ath9k_cal_list *cal_list;
@@ -755,17 +767,13 @@ struct ath_hw {
         u32 *bank6Temp;
 
         u8 txpower_limit;
-        int16_t txpower_indexoffset;
         int coverage_class;
-        u32 beacon_interval;
         u32 slottime;
         u32 globaltxtimeout;
 
         /* ANI */
         u32 proc_phyerr;
         u32 aniperiod;
-        struct ar5416AniState *curani;
-        struct ar5416AniState ani[255];
         int totalSizeDesired[5];
         int coarse_high[5];
         int coarse_low[5];
@@ -774,15 +782,21 @@ struct ath_hw {
 
         /* Bluetooth coexistance */
         struct ath_btcoex_hw btcoex_hw;
+        u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
+        u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
 
         u32 intr_txqs;
         u8 txchainmask;
         u8 rxchainmask;
 
+        struct ath_hw_radar_conf radar_conf;
+
         u32 originalGain[22];
         int initPDADC;
         int PDADCdelta;
-        u8 led_pin;
+        int led_pin;
+        u32 gpio_mask;
+        u32 gpio_val;
 
         struct ar5416IniArray iniModes;
         struct ar5416IniArray iniCommon;
@@ -798,6 +812,7 @@ struct ath_hw {
         struct ar5416IniArray iniPcieSerdes;
         struct ar5416IniArray iniPcieSerdesLowPower;
         struct ar5416IniArray iniModesAdditional;
+        struct ar5416IniArray iniModesAdditional_40M;
         struct ar5416IniArray iniModesRxGain;
         struct ar5416IniArray iniModesTxGain;
         struct ar5416IniArray iniModes_9271_1_0_only;
@@ -827,7 +842,13 @@ struct ath_hw {
 
         u32 bb_watchdog_last_status;
         u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
+        u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
 
+        unsigned int paprd_target_power;
+        unsigned int paprd_training_power;
+        unsigned int paprd_ratemask;
+        unsigned int paprd_ratemask_ht40;
+        bool paprd_table_write_done;
         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
         /*
@@ -836,6 +857,19 @@ struct ath_hw {
          * this register when in sleep states.
          */
         u32 WARegVal;
+
+        /* Enterprise mode cap */
+        u32 ent_mode;
+
+        bool is_clk_25mhz;
+};
+
+struct ath_bus_ops {
+        enum ath_bus_type ath_bus_type;
+        void (*read_cachesize)(struct ath_common *common, int *csz);
+        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
+        void (*bt_coex_prep)(struct ath_common *common);
+        void (*extn_synch_en)(struct ath_common *common);
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -858,10 +892,9 @@ static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
         return &ah->ops;
 }
 
-static inline int sign_extend(int val, const int nbits)
+static inline u8 get_streams(int mask)
 {
-        int order = BIT(nbits-1);
-        return (val ^ order) - order;
+        return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
 }
 
 /* Initialization, Detach, Reset */
@@ -873,12 +906,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 
-/* Key Cache Management */
-bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
-bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
-                                 const struct ath9k_keyval *k,
-                                 const u8 *mac);
-
 /* GPIO / RFKILL / Antennae */
 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
@@ -890,8 +917,9 @@ void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 
 /* General Operation */
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
+void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                          int column, unsigned int *writecnt);
 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
-bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                            u8 phy, int kbps,
                            u32 frameLen, u16 rateix, bool shortPreamble);
@@ -902,16 +930,18 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 bool ath9k_hw_disable(struct ath_hw *ah);
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
 void ath9k_hw_setopmode(struct ath_hw *ah);
 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 void ath9k_hw_write_associd(struct ath_hw *ah);
+u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 void ath9k_hw_init_global_settings(struct ath_hw *ah);
+u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
@@ -934,7 +964,6 @@ void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 
 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 void ath_gen_timer_isr(struct ath_hw *hw);
-u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 
 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 
@@ -962,6 +991,7 @@ void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
+void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
                                         struct ath9k_hw_cal_data *caldata,
@@ -984,6 +1014,7 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
 void ar9002_hw_attach_ops(struct ath_hw *ah);
 void ar9003_hw_attach_ops(struct ath_hw *ah);
 
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
 /*
  * ANI work can be shared between all families but a next
  * generation implementation of ANI will be used only for AR9003 only
@@ -992,8 +1023,9 @@ void ar9003_hw_attach_ops(struct ath_hw *ah);
  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
  */
 extern int modparam_force_new_ani;
-void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
-void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah);
+void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
+void ath9k_hw_proc_mib_event(struct ath_hw *ah);
+void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
 
 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 #define ATH_PCIE_CAP_LINK_L0S   1
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 243c1775f343..45c585a337e9 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,6 +15,7 @@
  */
 
 #include <linux/slab.h>
+#include <linux/ath9k_platform.h>
 
 #include "ath9k.h"
 
@@ -29,17 +30,23 @@ static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
 module_param_named(debug, ath9k_debug, uint, 0);
 MODULE_PARM_DESC(debug, "Debugging mask");
 
-int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
+int ath9k_modparam_nohwcrypt;
+module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
 
-int led_blink = 1;
+int led_blink;
 module_param_named(blink, led_blink, int, 0444);
 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
 
+static int ath9k_btcoex_enable;
+module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
+MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
+
+bool is_ath9k_unloaded;
 /* We use the hw_value as an index into our private channel structure */
 
 #define CHAN2G(_freq, _idx)  { \
+        .band = IEEE80211_BAND_2GHZ, \
         .center_freq = (_freq), \
         .hw_value = (_idx), \
         .max_power = 20, \
@@ -56,7 +63,7 @@ MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  * on 5 MHz steps, we support the channels which we know
  * we have calibration data for all cards though to make
  * this static */
-static struct ieee80211_channel ath9k_2ghz_chantable[] = {
+static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
         CHAN2G(2412, 0), /* Channel 1 */
         CHAN2G(2417, 1), /* Channel 2 */
         CHAN2G(2422, 2), /* Channel 3 */
@@ -77,7 +84,7 @@ static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  * on 5 MHz steps, we support the channels which we know
  * we have calibration data for all cards though to make
  * this static */
-static struct ieee80211_channel ath9k_5ghz_chantable[] = {
+static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
         /* _We_ call this UNII 1 */
         CHAN5G(5180, 14), /* Channel 36 */
         CHAN5G(5200, 15), /* Channel 40 */
@@ -134,6 +141,21 @@ static struct ieee80211_rate ath9k_legacy_rates[] = {
         RATE(540, 0x0c, 0),
 };
 
+#ifdef CONFIG_MAC80211_LEDS
+static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
+        { .throughput = 0 * 1024, .blink_time = 334 },
+        { .throughput = 1 * 1024, .blink_time = 260 },
+        { .throughput = 5 * 1024, .blink_time = 220 },
+        { .throughput = 10 * 1024, .blink_time = 190 },
+        { .throughput = 20 * 1024, .blink_time = 170 },
+        { .throughput = 50 * 1024, .blink_time = 150 },
+        { .throughput = 70 * 1024, .blink_time = 130 },
+        { .throughput = 100 * 1024, .blink_time = 110 },
+        { .throughput = 200 * 1024, .blink_time = 80 },
+        { .throughput = 300 * 1024, .blink_time = 50 },
+};
+#endif
+
 static void ath9k_deinit_softc(struct ath_softc *sc);
 
 /*
@@ -174,10 +196,27 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
         return val;
 }
 
-static const struct ath_ops ath9k_common_ops = {
-        .read = ath9k_ioread32,
-        .write = ath9k_iowrite32,
-};
+static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
+{
+        struct ath_hw *ah = (struct ath_hw *) hw_priv;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        unsigned long uninitialized_var(flags);
+        u32 val;
+
+        if (ah->config.serialize_regmode == SER_REG_MODE_ON)
+                spin_lock_irqsave(&sc->sc_serial_rw, flags);
+
+        val = ioread32(sc->mem + reg_offset);
+        val &= ~clr;
+        val |= set;
+        iowrite32(val, sc->mem + reg_offset);
+
+        if (ah->config.serialize_regmode == SER_REG_MODE_ON)
+                spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
+
+        return val;
+}
 
 /**************************/
 /*     Initialization     */
@@ -206,12 +245,14 @@ static void setup_ht_cap(struct ath_softc *sc,
         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 
-        if (AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9485(ah))
+                max_streams = 1;
+        else if (AR_SREV_9300_20_OR_LATER(ah))
                 max_streams = 3;
         else
                 max_streams = 2;
 
-        if (AR_SREV_9280_10_OR_LATER(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah)) {
                 if (max_streams >= 2)
                         ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
                 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
@@ -222,9 +263,9 @@ static void setup_ht_cap(struct ath_softc *sc,
         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "TX streams %d, RX streams: %d\n",
-                  tx_streams, rx_streams);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "TX streams %d, RX streams: %d\n",
+                tx_streams, rx_streams);
 
         if (tx_streams != rx_streams) {
                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -242,8 +283,7 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
                               struct regulatory_request *request)
 {
         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
 
         return ath_reg_notifier_apply(wiphy, request, reg);
@@ -267,8 +307,8 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
         struct ath_buf *bf;
         int i, bsize, error, desc_len;
 
-        ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
-                  name, nbuf, ndesc);
+        ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
+                name, nbuf, ndesc);
 
         INIT_LIST_HEAD(head);
 
@@ -279,8 +319,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 
         /* ath_desc must be a multiple of DWORDs */
         if ((desc_len % 4) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "ath_desc not DWORD aligned\n");
+                ath_err(common, "ath_desc not DWORD aligned\n");
                 BUG_ON((desc_len % 4) != 0);
                 error = -ENOMEM;
                 goto fail;
@@ -314,9 +353,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
                 goto fail;
         }
         ds = (u8 *) dd->dd_desc;
-        ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
-                  name, ds, (u32) dd->dd_desc_len,
-                  ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
+        ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
+                name, ds, (u32) dd->dd_desc_len,
+                ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 
         /* allocate buffers */
         bsize = sizeof(struct ath_buf) * nbuf;
@@ -362,26 +401,20 @@ fail:
 #undef DS2PHYS
 }
 
-static void ath9k_init_crypto(struct ath_softc *sc)
+void ath9k_init_crypto(struct ath_softc *sc)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
         /* Get the hardware key cache size. */
-        common->keymax = sc->sc_ah->caps.keycache_size;
-        if (common->keymax > ATH_KEYMAX) {
-                ath_print(common, ATH_DBG_ANY,
-                          "Warning, using only %u entries in %u key cache\n",
-                          ATH_KEYMAX, common->keymax);
-                common->keymax = ATH_KEYMAX;
-        }
+        common->keymax = AR_KEYTABLE_SIZE;
 
         /*
          * Reset the key cache since some parts do not
          * reset the contents on initial power up.
          */
         for (i = 0; i < common->keymax; i++)
-                ath9k_hw_keyreset(sc->sc_ah, (u16) i);
+                ath_hw_keyreset(common, (u16) i);
 
         /*
          * Check whether the separate key cache entries
@@ -389,13 +422,14 @@ static void ath9k_init_crypto(struct ath_softc *sc)
          * With split mic keys the number of stations is limited
          * to 27 otherwise 59.
          */
-        if (!(sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA))
-                common->splitmic = 1;
+        if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
+                common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
 }
 
 static int ath9k_init_btcoex(struct ath_softc *sc)
 {
-        int r, qnum;
+        struct ath_txq *txq;
+        int r;
 
         switch (sc->sc_ah->btcoex_hw.scheme) {
         case ATH_BTCOEX_CFG_NONE:
@@ -408,8 +442,8 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
                 r = ath_init_btcoex_timer(sc);
                 if (r)
                         return -1;
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
+                txq = sc->tx.txq_map[WME_AC_BE];
+                ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
                 break;
         default:
@@ -422,65 +456,36 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
 
 static int ath9k_init_queues(struct ath_softc *sc)
 {
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
-        for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
-                sc->tx.hwq_map[i] = -1;
-
         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
-        if (sc->beacon.beaconq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup a beacon xmit queue\n");
-                goto err;
-        }
-
         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
-        if (sc->beacon.cabq == NULL) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup CAB xmit queue\n");
-                goto err;
-        }
 
         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
         ath_cabq_update(sc);
 
-        if (!ath_tx_setup(sc, WME_AC_BK)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BK traffic\n");
-                goto err;
-        }
-
-        if (!ath_tx_setup(sc, WME_AC_BE)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BE traffic\n");
-                goto err;
-        }
-        if (!ath_tx_setup(sc, WME_AC_VI)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VI traffic\n");
-                goto err;
-        }
-        if (!ath_tx_setup(sc, WME_AC_VO)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VO traffic\n");
-                goto err;
+        for (i = 0; i < WME_NUM_AC; i++) {
+                sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
+                sc->tx.txq_map[i]->mac80211_qnum = i;
         }
-
         return 0;
-
-err:
-        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
-                if (ATH_TXQ_SETUP(sc, i))
-                        ath_tx_cleanupq(sc, &sc->tx.txq[i]);
-
-        return -EIO;
 }
 
-static void ath9k_init_channels_rates(struct ath_softc *sc)
+static int ath9k_init_channels_rates(struct ath_softc *sc)
 {
-        if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
-                sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
+        void *channels;
+
+        BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
+                     ARRAY_SIZE(ath9k_5ghz_chantable) !=
+                     ATH9K_NUM_CHANNELS);
+
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
+                channels = kmemdup(ath9k_2ghz_chantable,
+                        sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
+                if (!channels)
+                    return -ENOMEM;
+
+                sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
                 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
                 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
                         ARRAY_SIZE(ath9k_2ghz_chantable);
@@ -489,8 +494,16 @@ static void ath9k_init_channels_rates(struct ath_softc *sc)
                         ARRAY_SIZE(ath9k_legacy_rates);
         }
 
-        if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
-                sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
+                channels = kmemdup(ath9k_5ghz_chantable,
+                        sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
+                if (!channels) {
+                        if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
+                                kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
+                        return -ENOMEM;
+                }
+
+                sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
                         ARRAY_SIZE(ath9k_5ghz_chantable);
@@ -499,6 +512,7 @@ static void ath9k_init_channels_rates(struct ath_softc *sc)
                 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
         }
+        return 0;
 }
 
 static void ath9k_init_misc(struct ath_softc *sc)
@@ -506,7 +520,6 @@ static void ath9k_init_misc(struct ath_softc *sc)
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
-        common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
 
         sc->config.txpowlimit = ATH_TXPOWER_MAX;
@@ -522,20 +535,21 @@ static void ath9k_init_misc(struct ath_softc *sc)
         ath9k_hw_set_diversity(sc->sc_ah, true);
         sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
 
-        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
+        memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 
         sc->beacon.slottime = ATH9K_SLOT_TIME_9;
 
-        for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
+        for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
                 sc->beacon.bslot[i] = NULL;
-                sc->beacon.bslot_aphy[i] = NULL;
-        }
+
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
+                sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
 }
 
 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
                             const struct ath_bus_ops *bus_ops)
 {
+        struct ath9k_platform_data *pdata = sc->dev->platform_data;
         struct ath_hw *ah = NULL;
         struct ath_common *common;
         int ret = 0, i;
@@ -545,23 +559,41 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (!ah)
                 return -ENOMEM;
 
+        ah->hw = sc->hw;
         ah->hw_version.devid = devid;
         ah->hw_version.subsysid = subsysid;
+        ah->reg_ops.read = ath9k_ioread32;
+        ah->reg_ops.write = ath9k_iowrite32;
+        ah->reg_ops.rmw = ath9k_reg_rmw;
         sc->sc_ah = ah;
 
+        if (!pdata) {
+                ah->ah_flags |= AH_USE_EEPROM;
+                sc->sc_ah->led_pin = -1;
+        } else {
+                sc->sc_ah->gpio_mask = pdata->gpio_mask;
+                sc->sc_ah->gpio_val = pdata->gpio_val;
+                sc->sc_ah->led_pin = pdata->led_pin;
+                ah->is_clk_25mhz = pdata->is_clk_25mhz;
+        }
+
         common = ath9k_hw_common(ah);
-        common->ops = &ath9k_common_ops;
+        common->ops = &ah->reg_ops;
         common->bus_ops = bus_ops;
         common->ah = ah;
         common->hw = sc->hw;
         common->priv = sc;
         common->debug_mask = ath9k_debug;
+        common->btcoex_enabled = ath9k_btcoex_enable == 1;
+        spin_lock_init(&common->cc_lock);
 
-        spin_lock_init(&sc->wiphy_lock);
-        spin_lock_init(&sc->sc_resetlock);
         spin_lock_init(&sc->sc_serial_rw);
         spin_lock_init(&sc->sc_pm_lock);
         mutex_init(&sc->mutex);
+#ifdef CONFIG_ATH9K_DEBUGFS
+        spin_lock_init(&sc->nodes_lock);
+        INIT_LIST_HEAD(&sc->nodes);
+#endif
         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
                      (unsigned long)sc);
@@ -578,12 +610,8 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (ret)
                 goto err_hw;
 
-        ret = ath9k_init_debug(ah);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to create debugfs files\n");
-                goto err_debug;
-        }
+        if (pdata && pdata->macaddr)
+                memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
 
         ret = ath9k_init_queues(sc);
         if (ret)
@@ -593,8 +621,11 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (ret)
                 goto err_btcoex;
 
+        ret = ath9k_init_channels_rates(sc);
+        if (ret)
+                goto err_btcoex;
+
         ath9k_init_crypto(sc);
-        ath9k_init_channels_rates(sc);
         ath9k_init_misc(sc);
 
         return 0;
@@ -604,12 +635,8 @@ err_btcoex:
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 err_queues:
-        ath9k_exit_debug(ah);
-err_debug:
         ath9k_hw_deinit(ah);
 err_hw:
-        tasklet_kill(&sc->intr_tq);
-        tasklet_kill(&sc->bcon_tasklet);
 
         kfree(ah);
         sc->sc_ah = NULL;
@@ -617,6 +644,37 @@ err_hw:
         return ret;
 }
 
+static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
+{
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *chan;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
+        int i;
+
+        sband = &sc->sbands[band];
+        for (i = 0; i < sband->n_channels; i++) {
+                chan = &sband->channels[i];
+                ah->curchan = &ah->channels[chan->hw_value];
+                ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
+                ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
+                chan->max_power = reg->max_power_level / 2;
+        }
+}
+
+static void ath9k_init_txpower_limits(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *curchan = ah->curchan;
+
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
+                ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
+                ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
+
+        ah->curchan = curchan;
+}
+
 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -632,16 +690,22 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
                  hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
 
-        if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
+        if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
 
         hw->wiphy->interface_modes =
+                BIT(NL80211_IFTYPE_P2P_GO) |
+                BIT(NL80211_IFTYPE_P2P_CLIENT) |
                 BIT(NL80211_IFTYPE_AP) |
+                BIT(NL80211_IFTYPE_WDS) |
                 BIT(NL80211_IFTYPE_STATION) |
                 BIT(NL80211_IFTYPE_ADHOC) |
                 BIT(NL80211_IFTYPE_MESH_POINT);
 
-        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        if (AR_SREV_5416(sc->sc_ah))
+                hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+
+        hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
 
         hw->queues = 4;
         hw->max_rates = 4;
@@ -651,19 +715,21 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         hw->sta_data_size = sizeof(struct ath_node);
         hw->vif_data_size = sizeof(struct ath_vif);
 
+#ifdef CONFIG_ATH9K_RATE_CONTROL
         hw->rate_control_algorithm = "ath9k_rate_control";
+#endif
 
-        if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &sc->sbands[IEEE80211_BAND_2GHZ];
-        if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
+        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
                         &sc->sbands[IEEE80211_BAND_5GHZ];
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
-                if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
+                if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
-                if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
+                if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
         }
 
@@ -706,11 +772,26 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (error != 0)
                 goto error_rx;
 
+        ath9k_init_txpower_limits(sc);
+
+#ifdef CONFIG_MAC80211_LEDS
+        /* must be initialized before ieee80211_register_hw */
+        sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
+                IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
+                ARRAY_SIZE(ath9k_tpt_blink));
+#endif
+
         /* Register with mac80211 */
         error = ieee80211_register_hw(hw);
         if (error)
                 goto error_register;
 
+        error = ath9k_init_debug(ah);
+        if (error) {
+                ath_err(common, "Unable to create debugfs files\n");
+                goto error_world;
+        }
+
         /* Handle world regulatory */
         if (!ath_is_world_regd(reg)) {
                 error = regulatory_hint(hw->wiphy, reg->alpha2);
@@ -720,9 +801,8 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
 
         INIT_WORK(&sc->hw_check_work, ath_hw_check);
         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
-        INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
-        INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
-        sc->wiphy_scheduler_int = msecs_to_jiffies(500);
+        INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
+        sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
 
         ath_init_leds(sc);
         ath_start_rfkill_poll(sc);
@@ -751,6 +831,12 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
 {
         int i = 0;
 
+        if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
+                kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
+
+        if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
+                kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
+
         if ((sc->btcoex.no_stomp_timer) &&
             sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
                 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
@@ -759,12 +845,8 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 
-        ath9k_exit_debug(sc->sc_ah);
         ath9k_hw_deinit(sc->sc_ah);
 
-        tasklet_kill(&sc->intr_tq);
-        tasklet_kill(&sc->bcon_tasklet);
-
         kfree(sc->sc_ah);
         sc->sc_ah = NULL;
 }
@@ -772,27 +854,18 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
 void ath9k_deinit_device(struct ath_softc *sc)
 {
         struct ieee80211_hw *hw = sc->hw;
-        int i = 0;
 
         ath9k_ps_wakeup(sc);
 
         wiphy_rfkill_stop_polling(sc->hw->wiphy);
         ath_deinit_leds(sc);
 
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
-                        continue;
-                sc->sec_wiphy[i] = NULL;
-                ieee80211_unregister_hw(aphy->hw);
-                ieee80211_free_hw(aphy->hw);
-        }
+        ath9k_ps_restore(sc);
 
         ieee80211_unregister_hw(hw);
         ath_rx_cleanup(sc);
         ath_tx_cleanup(sc);
         ath9k_deinit_softc(sc);
-        kfree(sc->sec_wiphy);
 }
 
 void ath_descdma_cleanup(struct ath_softc *sc,
@@ -825,20 +898,12 @@ static int __init ath9k_init(void)
                 goto err_out;
         }
 
-        error = ath9k_debug_create_root();
-        if (error) {
-                printk(KERN_ERR
-                        "ath9k: Unable to create debugfs root: %d\n",
-                        error);
-                goto err_rate_unregister;
-        }
-
         error = ath_pci_init();
         if (error < 0) {
                 printk(KERN_ERR
                         "ath9k: No PCI devices found, driver not installed.\n");
                 error = -ENODEV;
-                goto err_remove_root;
+                goto err_rate_unregister;
         }
 
         error = ath_ahb_init();
@@ -852,8 +917,6 @@ static int __init ath9k_init(void)
  err_pci_exit:
         ath_pci_exit();
 
- err_remove_root:
-        ath9k_debug_remove_root();
  err_rate_unregister:
         ath_rate_control_unregister();
  err_out:
@@ -863,9 +926,9 @@ module_init(ath9k_init);
 
 static void __exit ath9k_exit(void)
 {
+        is_ath9k_unloaded = true;
         ath_ahb_exit();
         ath_pci_exit();
-        ath9k_debug_remove_root();
         ath_rate_control_unregister();
         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
 }
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index e955bb9d98cb..c2091f1f4096 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,11 +20,11 @@
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                                         struct ath9k_tx_queue_info *qi)
 {
-        ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
-                  "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
-                  ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
-                  ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
-                  ah->txurn_interrupt_mask);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
+                "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
+                ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
+                ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
+                ah->txurn_interrupt_mask);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -40,7 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -57,8 +56,8 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf);
 
 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
 {
-        ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
-                  "Enable TXE on queue: %u\n", q);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
+                "Enable TXE on queue: %u\n", q);
         REG_WRITE(ah, AR_Q_TXE, 1 << q);
 }
 EXPORT_SYMBOL(ath9k_hw_txstart);
@@ -118,12 +117,11 @@ EXPORT_SYMBOL(ath9k_hw_numtxpending);
 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
 {
         u32 txcfg, curLevel, newLevel;
-        enum ath9k_int omask;
 
         if (ah->tx_trig_level >= ah->config.max_txtrig_level)
                 return false;
 
-        omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
+        ath9k_hw_disable_interrupts(ah);
 
         txcfg = REG_READ(ah, AR_TXCFG);
         curLevel = MS(txcfg, AR_FTRIG);
@@ -137,7 +135,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
                 REG_WRITE(ah, AR_TXCFG,
                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
 
-        ath9k_hw_set_interrupts(ah, omask);
+        ath9k_hw_enable_interrupts(ah);
 
         ah->tx_trig_level = newLevel;
 
@@ -145,85 +143,59 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
 }
 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
 
-bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
+void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
 {
-#define ATH9K_TX_STOP_DMA_TIMEOUT       4000    /* usec */
-#define ATH9K_TIME_QUANTUM              100     /* usec */
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
-        struct ath9k_tx_queue_info *qi;
-        u32 tsfLow, j, wait;
-        u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
+        int i, q;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
+        REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
 
-        qi = &ah->txq[q];
-        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                          "inactive queue: %u\n", q);
-                return false;
-        }
+        REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
+        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+        REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
 
-        REG_WRITE(ah, AR_Q_TXD, 1 << q);
+        for (q = 0; q < AR_NUM_QCU; q++) {
+                for (i = 0; i < 1000; i++) {
+                        if (i)
+                                udelay(5);
 
-        for (wait = wait_time; wait != 0; wait--) {
-                if (ath9k_hw_numtxpending(ah, q) == 0)
-                        break;
-                udelay(ATH9K_TIME_QUANTUM);
+                        if (!ath9k_hw_numtxpending(ah, q))
+                                break;
+                }
         }
 
-        if (ath9k_hw_numtxpending(ah, q)) {
-                ath_print(common, ATH_DBG_QUEUE,
-                          "%s: Num of pending TX Frames %d on Q %d\n",
-                          __func__, ath9k_hw_numtxpending(ah, q), q);
-
-                for (j = 0; j < 2; j++) {
-                        tsfLow = REG_READ(ah, AR_TSF_L32);
-                        REG_WRITE(ah, AR_QUIET2,
-                                  SM(10, AR_QUIET2_QUIET_DUR));
-                        REG_WRITE(ah, AR_QUIET_PERIOD, 100);
-                        REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
-                        REG_SET_BIT(ah, AR_TIMER_MODE,
-                                       AR_QUIET_TIMER_EN);
-
-                        if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
-                                break;
+        REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
+        REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+        REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
 
-                        ath_print(common, ATH_DBG_QUEUE,
-                                  "TSF has moved while trying to set "
-                                  "quiet time TSF: 0x%08x\n", tsfLow);
-                }
+        REG_WRITE(ah, AR_Q_TXD, 0);
+}
+EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
 
-                REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
+{
+#define ATH9K_TX_STOP_DMA_TIMEOUT       1000    /* usec */
+#define ATH9K_TIME_QUANTUM              100     /* usec */
+        int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
+        int wait;
 
-                udelay(200);
-                REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
+        REG_WRITE(ah, AR_Q_TXD, 1 << q);
 
-                wait = wait_time;
-                while (ath9k_hw_numtxpending(ah, q)) {
-                        if ((--wait) == 0) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Failed to stop TX DMA in 100 "
-                                          "msec after killing last frame\n");
-                                break;
-                        }
+        for (wait = wait_time; wait != 0; wait--) {
+                if (wait != wait_time)
                         udelay(ATH9K_TIME_QUANTUM);
-                }
 
-                REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+                if (ath9k_hw_numtxpending(ah, q) == 0)
+                        break;
         }
 
         REG_WRITE(ah, AR_Q_TXD, 0);
+
         return wait != 0;
 
 #undef ATH9K_TX_STOP_DMA_TIMEOUT
 #undef ATH9K_TIME_QUANTUM
 }
-EXPORT_SYMBOL(ath9k_hw_stoptxdma);
+EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
 
 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
 {
@@ -237,23 +209,16 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
 {
         u32 cw;
         struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath9k_tx_queue_info *qi;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
-
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Set TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
 
         qi->tqi_ver = qinfo->tqi_ver;
         qi->tqi_subtype = qinfo->tqi_subtype;
@@ -308,19 +273,12 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
                             struct ath9k_tx_queue_info *qinfo)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath9k_tx_queue_info *qi;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
-
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Get TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
@@ -348,45 +306,41 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
 {
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info *qi;
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         int q;
 
         switch (type) {
         case ATH9K_TX_QUEUE_BEACON:
-                q = pCap->total_queues - 1;
+                q = ATH9K_NUM_TX_QUEUES - 1;
                 break;
         case ATH9K_TX_QUEUE_CAB:
-                q = pCap->total_queues - 2;
+                q = ATH9K_NUM_TX_QUEUES - 2;
                 break;
         case ATH9K_TX_QUEUE_PSPOLL:
                 q = 1;
                 break;
         case ATH9K_TX_QUEUE_UAPSD:
-                q = pCap->total_queues - 3;
+                q = ATH9K_NUM_TX_QUEUES - 3;
                 break;
         case ATH9K_TX_QUEUE_DATA:
-                for (q = 0; q < pCap->total_queues; q++)
+                for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
                         if (ah->txq[q].tqi_type ==
                             ATH9K_TX_QUEUE_INACTIVE)
                                 break;
-                if (q == pCap->total_queues) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "No available TX queue\n");
+                if (q == ATH9K_NUM_TX_QUEUES) {
+                        ath_err(common, "No available TX queue\n");
                         return -1;
                 }
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "Invalid TX queue type: %u\n", type);
+                ath_err(common, "Invalid TX queue type: %u\n", type);
                 return -1;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
 
         qi = &ah->txq[q];
         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "TX queue: %u already active\n", q);
+                ath_err(common, "TX queue: %u already active\n", q);
                 return -1;
         }
         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -413,23 +367,17 @@ EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
 
 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
 {
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info *qi;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Release TXQ, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
 
         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
         ah->txok_interrupt_mask &= ~(1 << q);
@@ -445,26 +393,19 @@ EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
 
 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
 {
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_channel *chan = ah->curchan;
         struct ath9k_tx_queue_info *qi;
         u32 cwMin, chanCwMin, value;
 
-        if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                          "invalid queue: %u\n", q);
-                return false;
-        }
-
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Reset TXQ, inactive queue: %u\n", q);
                 return true;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
 
         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                 if (chan && IS_CHAN_B(chan))
@@ -489,19 +430,21 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                   SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
 
         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
-        REG_WRITE(ah, AR_DMISC(q),
-                  AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
 
-        REGWRITE_BUFFER_FLUSH(ah);
+        if (AR_SREV_9340(ah))
+                REG_WRITE(ah, AR_DMISC(q),
+                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
+        else
+                REG_WRITE(ah, AR_DMISC(q),
+                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
 
         if (qi->tqi_cbrPeriod) {
                 REG_WRITE(ah, AR_QCBRCFG(q),
                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
                           SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
-                REG_WRITE(ah, AR_QMISC(q),
-                          REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
-                          (qi->tqi_cbrOverflowLimit ?
-                           AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
+                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
+                            (qi->tqi_cbrOverflowLimit ?
+                             AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
         }
         if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
@@ -509,51 +452,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                           AR_Q_RDYTIMECFG_EN);
         }
 
-        REGWRITE_BUFFER_FLUSH(ah);
-
         REG_WRITE(ah, AR_DCHNTIME(q),
                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
 
         if (qi->tqi_burstTime
-            && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
-                REG_WRITE(ah, AR_QMISC(q),
-                          REG_READ(ah, AR_QMISC(q)) |
-                          AR_Q_MISC_RDYTIME_EXP_POLICY);
+            && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
+                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
 
-        }
-
-        if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
-                REG_WRITE(ah, AR_DMISC(q),
-                          REG_READ(ah, AR_DMISC(q)) |
-                          AR_D_MISC_POST_FR_BKOFF_DIS);
-        }
+        if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
+                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
 
         REGWRITE_BUFFER_FLUSH(ah);
-        DISABLE_REGWRITE_BUFFER(ah);
 
-        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
-                REG_WRITE(ah, AR_DMISC(q),
-                          REG_READ(ah, AR_DMISC(q)) |
-                          AR_D_MISC_FRAG_BKOFF_EN);
-        }
+        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
+                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
+
         switch (qi->tqi_type) {
         case ATH9K_TX_QUEUE_BEACON:
                 ENABLE_REGWRITE_BUFFER(ah);
 
-                REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
-                          | AR_Q_MISC_FSP_DBA_GATED
-                          | AR_Q_MISC_BEACON_USE
-                          | AR_Q_MISC_CBR_INCR_DIS1);
+                REG_SET_BIT(ah, AR_QMISC(q),
+                            AR_Q_MISC_FSP_DBA_GATED
+                            | AR_Q_MISC_BEACON_USE
+                            | AR_Q_MISC_CBR_INCR_DIS1);
 
-                REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
-                          | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
+                REG_SET_BIT(ah, AR_DMISC(q),
+                            (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
-                          | AR_D_MISC_BEACON_USE
-                          | AR_D_MISC_POST_FR_BKOFF_DIS);
+                            | AR_D_MISC_BEACON_USE
+                            | AR_D_MISC_POST_FR_BKOFF_DIS);
 
                 REGWRITE_BUFFER_FLUSH(ah);
-                DISABLE_REGWRITE_BUFFER(ah);
 
                 /*
                  * cwmin and cwmax should be 0 for beacon queue
@@ -570,42 +500,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
         case ATH9K_TX_QUEUE_CAB:
                 ENABLE_REGWRITE_BUFFER(ah);
 
-                REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
-                          | AR_Q_MISC_FSP_DBA_GATED
-                          | AR_Q_MISC_CBR_INCR_DIS1
-                          | AR_Q_MISC_CBR_INCR_DIS0);
+                REG_SET_BIT(ah, AR_QMISC(q),
+                            AR_Q_MISC_FSP_DBA_GATED
+                            | AR_Q_MISC_CBR_INCR_DIS1
+                            | AR_Q_MISC_CBR_INCR_DIS0);
                 value = (qi->tqi_readyTime -
                          (ah->config.sw_beacon_response_time -
                           ah->config.dma_beacon_response_time) -
                          ah->config.additional_swba_backoff) * 1024;
                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
                           value | AR_Q_RDYTIMECFG_EN);
-                REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
-                          | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
+                REG_SET_BIT(ah, AR_DMISC(q),
+                            (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
 
                 REGWRITE_BUFFER_FLUSH(ah);
-                DISABLE_REGWRITE_BUFFER(ah);
 
                 break;
         case ATH9K_TX_QUEUE_PSPOLL:
-                REG_WRITE(ah, AR_QMISC(q),
-                          REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
+                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
                 break;
         case ATH9K_TX_QUEUE_UAPSD:
-                REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
-                          AR_D_MISC_POST_FR_BKOFF_DIS);
+                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
                 break;
         default:
                 break;
         }
 
         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
-                REG_WRITE(ah, AR_DMISC(q),
-                          REG_READ(ah, AR_DMISC(q)) |
-                          SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
-                             AR_D_MISC_ARB_LOCKOUT_CNTRL) |
-                          AR_D_MISC_POST_FR_BKOFF_DIS);
+                REG_SET_BIT(ah, AR_DMISC(q),
+                            SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
+                               AR_D_MISC_ARB_LOCKOUT_CNTRL) |
+                            AR_D_MISC_POST_FR_BKOFF_DIS);
         }
 
         if (AR_SREV_9300_20_OR_LATER(ah))
@@ -703,6 +629,12 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
                 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
 
         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
+                /*
+                 * Treat these errors as mutually exclusive to avoid spurious
+                 * extra error reports from the hardware. If a CRC error is
+                 * reported, then decryption and MIC errors are irrelevant,
+                 * the frame is going to be dropped either way
+                 */
                 if (ads.ds_rxstatus8 & AR_CRCErr)
                         rs->rs_status |= ATH9K_RXERR_CRC;
                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
@@ -713,6 +645,9 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
                         rs->rs_status |= ATH9K_RXERR_DECRYPT;
                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
                         rs->rs_status |= ATH9K_RXERR_MIC;
+
+                if (ads.ds_rxstatus8 & AR_KeyMiss)
+                        rs->rs_status |= ATH9K_RXERR_DECRYPT;
         }
 
         return 0;
@@ -741,9 +676,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
                                      AR_DIAG_RX_ABORT));
 
                         reg = REG_READ(ah, AR_OBS_BUS_1);
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "RX failed to go idle in 10 ms RXSM=0x%x\n",
-                                  reg);
+                        ath_err(ath9k_hw_common(ah),
+                                "RX failed to go idle in 10 ms RXSM=0x%x\n",
+                                reg);
 
                         return false;
                 }
@@ -772,14 +707,6 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
 }
 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
 
-void ath9k_hw_stoppcurecv(struct ath_hw *ah)
-{
-        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
-
-        ath9k_hw_disable_mib_counters(ah);
-}
-EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
-
 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
 {
         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
@@ -788,35 +715,51 @@ void ath9k_hw_abortpcurecv(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
 
-bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
+bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
 {
 #define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
-#define AH_RX_TIME_QUANTUM     100     /* usec */
         struct ath_common *common = ath9k_hw_common(ah);
+        u32 mac_status, last_mac_status = 0;
         int i;
 
+        /* Enable access to the DMA observation bus */
+        REG_WRITE(ah, AR_MACMISC,
+                  ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
+                   (AR_MACMISC_MISC_OBS_BUS_1 <<
+                    AR_MACMISC_MISC_OBS_BUS_MSB_S)));
+
         REG_WRITE(ah, AR_CR, AR_CR_RXD);
 
         /* Wait for rx enable bit to go low */
         for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
                 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
                         break;
+
+                if (!AR_SREV_9300_20_OR_LATER(ah)) {
+                        mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
+                        if (mac_status == 0x1c0 && mac_status == last_mac_status) {
+                                *reset = true;
+                                break;
+                        }
+
+                        last_mac_status = mac_status;
+                }
+
                 udelay(AH_TIME_QUANTUM);
         }
 
         if (i == 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "DMA failed to stop in %d ms "
-                          "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
-                          AH_RX_STOP_DMA_TIMEOUT / 1000,
-                          REG_READ(ah, AR_CR),
-                          REG_READ(ah, AR_DIAG_SW));
+                ath_err(common,
+                        "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
+                        AH_RX_STOP_DMA_TIMEOUT / 1000,
+                        REG_READ(ah, AR_CR),
+                        REG_READ(ah, AR_DIAG_SW),
+                        REG_READ(ah, AR_DMADBG_7));
                 return false;
         } else {
                 return true;
         }
 
-#undef AH_RX_TIME_QUANTUM
 #undef AH_RX_STOP_DMA_TIMEOUT
 }
 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
@@ -854,28 +797,61 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_intrpend);
 
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                              enum ath9k_int ints)
+void ath9k_hw_disable_interrupts(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
+        REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+        (void) REG_READ(ah, AR_IER);
+        if (!AR_SREV_9100(ah)) {
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+                (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+                (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
+        }
+}
+EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
+
+void ath9k_hw_enable_interrupts(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u32 sync_default = AR_INTR_SYNC_DEFAULT;
+
+        if (!(ah->imask & ATH9K_INT_GLOBAL))
+                return;
+
+        if (AR_SREV_9340(ah))
+                sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
+
+        ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
+        REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+        if (!AR_SREV_9100(ah)) {
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
+                          AR_INTR_MAC_IRQ);
+                REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
+                REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
+        }
+        ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+                REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+}
+EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
+
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
 {
         enum ath9k_int omask = ah->imask;
         u32 mask, mask2;
         struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
-
-        if (omask & ATH9K_INT_GLOBAL) {
-                ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
-                REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
-                (void) REG_READ(ah, AR_IER);
-                if (!AR_SREV_9100(ah)) {
-                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
-                        (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+        if (!(ints & ATH9K_INT_GLOBAL))
+                ath9k_hw_disable_interrupts(ah);
 
-                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-                        (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
-                }
-        }
+        ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
 
         /* TODO: global int Ref count */
         mask = ints & ATH9K_INT_COMMON;
@@ -914,6 +890,9 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         mask |= AR_IMR_GENTMR;
         }
 
+        if (ints & ATH9K_INT_GENTIMER)
+                mask |= AR_IMR_GENTMR;
+
         if (ints & (ATH9K_INT_BMISC)) {
                 mask |= AR_IMR_BCNMISC;
                 if (ints & ATH9K_INT_TIM)
@@ -936,7 +915,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         mask2 |= AR_IMR_S2_CST;
         }
 
-        ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+        ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
         REG_WRITE(ah, AR_IMR, mask);
         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
@@ -951,24 +930,9 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
         }
 
-        if (ints & ATH9K_INT_GLOBAL) {
-                ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
-                REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
-                if (!AR_SREV_9100(ah)) {
-                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
-                                  AR_INTR_MAC_IRQ);
-                        REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
-
-
-                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
-                                  AR_INTR_SYNC_DEFAULT);
-                        REG_WRITE(ah, AR_INTR_SYNC_MASK,
-                                  AR_INTR_SYNC_DEFAULT);
-                }
-                ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
-                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
-        }
+        if (ints & ATH9K_INT_GLOBAL)
+                ath9k_hw_enable_interrupts(ah);
 
-        return omask;
+        return;
 }
 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 2633896d3998..8e848c4d16ba 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -104,13 +104,11 @@ struct ath_tx_status {
         u32 ts_tstamp;
         u16 ts_seqnum;
         u8 ts_status;
-        u8 ts_ratecode;
         u8 ts_rateindex;
         int8_t ts_rssi;
         u8 ts_shortretry;
         u8 ts_longretry;
         u8 ts_virtcol;
-        u8 ts_antenna;
         u8 ts_flags;
         int8_t ts_rssi_ctl0;
         int8_t ts_rssi_ctl1;
@@ -121,7 +119,6 @@ struct ath_tx_status {
         u8 qid;
         u16 desc_id;
         u8 tid;
-        u8 pad[2];
         u32 ba_low;
         u32 ba_high;
         u32 evm0;
@@ -240,9 +237,8 @@ struct ath_desc {
         u32 ds_ctl1;
         u32 ds_hw[20];
         void *ds_vdata;
-} __packed;
+} __packed __aligned(4);
 
-#define ATH9K_TXDESC_CLRDMASK           0x0001
 #define ATH9K_TXDESC_NOACK              0x0002
 #define ATH9K_TXDESC_RTSENA             0x0004
 #define ATH9K_TXDESC_CTSENA             0x0008
@@ -310,7 +306,7 @@ struct ar5416_desc {
                         u32 status8;
                 } rx;
         } u;
-} __packed;
+} __packed __aligned(4);
 
 #define AR5416DESC(_ds)         ((struct ar5416_desc *)(_ds))
 #define AR5416DESC_CONST(_ds)   ((const struct ar5416_desc *)(_ds))
@@ -642,6 +638,8 @@ enum ath9k_rx_filter {
         ATH9K_RX_FILTER_PHYERR = 0x00000100,
         ATH9K_RX_FILTER_MYBEACON = 0x00000200,
         ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
+        ATH9K_RX_FILTER_COMP_BA = 0x00000800,
+        ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
         ATH9K_RX_FILTER_PSPOLL = 0x00004000,
         ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
         ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
@@ -660,17 +658,6 @@ struct ath9k_11n_rate_series {
         u32 RateFlags;
 };
 
-struct ath9k_keyval {
-        u8 kv_type;
-        u8 kv_pad;
-        u16 kv_len;
-        u8 kv_val[16]; /* TK */
-        u8 kv_mic[8]; /* Michael MIC key */
-        u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
-                         * supports both MIC keys in the same key cache entry;
-                         * in that case, kv_mic is the RX key) */
-};
-
 enum ath9k_key_type {
         ATH9K_KEY_TYPE_CLEAR,
         ATH9K_KEY_TYPE_WEP,
@@ -678,18 +665,9 @@ enum ath9k_key_type {
         ATH9K_KEY_TYPE_TKIP,
 };
 
-enum ath9k_cipher {
-        ATH9K_CIPHER_WEP = 0,
-        ATH9K_CIPHER_AES_OCB = 1,
-        ATH9K_CIPHER_AES_CCM = 2,
-        ATH9K_CIPHER_CKIP = 3,
-        ATH9K_CIPHER_TKIP = 4,
-        ATH9K_CIPHER_CLR = 5,
-        ATH9K_CIPHER_MIC = 127
-};
-
 struct ath_hw;
 struct ath9k_channel;
+enum ath9k_int;
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
@@ -697,7 +675,8 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
-bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
+bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
+void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
                             const struct ath9k_tx_queue_info *qinfo);
@@ -714,15 +693,15 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
-void ath9k_hw_stoppcurecv(struct ath_hw *ah);
 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
-bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
+bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);
 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
 
 /* Interrupt Handling */
 bool ath9k_hw_intrpend(struct ath_hw *ah);
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                       enum ath9k_int ints);
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
+void ath9k_hw_enable_interrupts(struct ath_hw *ah);
+void ath9k_hw_disable_interrupts(struct ath_hw *ah);
 
 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
 
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 3caa32316e7b..2ca351fe6d3c 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,50 +15,10 @@
  */
 
 #include <linux/nl80211.h>
+#include <linux/delay.h>
 #include "ath9k.h"
 #include "btcoex.h"
 
-static void ath_cache_conf_rate(struct ath_softc *sc,
-                                struct ieee80211_conf *conf)
-{
-        switch (conf->channel->band) {
-        case IEEE80211_BAND_2GHZ:
-                if (conf_is_ht20(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
-                else if (conf_is_ht40_minus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
-                else if (conf_is_ht40_plus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
-                else
-                        sc->cur_rate_mode = ATH9K_MODE_11G;
-                break;
-        case IEEE80211_BAND_5GHZ:
-                if (conf_is_ht20(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
-                else if (conf_is_ht40_minus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
-                else if (conf_is_ht40_plus(conf))
-                        sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
-                else
-                        sc->cur_rate_mode = ATH9K_MODE_11A;
-                break;
-        default:
-                BUG_ON(1);
-                break;
-        }
-}
-
-static void ath_update_txpow(struct ath_softc *sc)
-{
-        struct ath_hw *ah = sc->sc_ah;
-
-        if (sc->curtxpow != sc->config.txpowlimit) {
-                ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
-                /* read back in case value is clamped */
-                sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
-        }
-}
-
 static u8 parse_mpdudensity(u8 mpdudensity)
 {
         /*
@@ -94,17 +54,19 @@ static u8 parse_mpdudensity(u8 mpdudensity)
         }
 }
 
-static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
-                                                struct ieee80211_hw *hw)
+static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
 {
-        struct ieee80211_channel *curchan = hw->conf.channel;
-        struct ath9k_channel *channel;
-        u8 chan_idx;
+        bool pending = false;
+
+        spin_lock_bh(&txq->axq_lock);
+
+        if (txq->axq_depth || !list_empty(&txq->axq_acq))
+                pending = true;
+        else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
+                pending = !list_empty(&txq->txq_fifo_pending);
 
-        chan_idx = curchan->hw_value;
-        channel = &sc->sc_ah->channels[chan_idx];
-        ath9k_update_ichannel(sc, hw, channel);
-        return channel;
+        spin_unlock_bh(&txq->axq_lock);
+        return pending;
 }
 
 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
@@ -121,26 +83,46 @@ bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 
 void ath9k_ps_wakeup(struct ath_softc *sc)
 {
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         unsigned long flags;
+        enum ath9k_power_mode power_mode;
 
         spin_lock_irqsave(&sc->sc_pm_lock, flags);
         if (++sc->ps_usecount != 1)
                 goto unlock;
 
+        power_mode = sc->sc_ah->power_mode;
         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 
+        /*
+         * While the hardware is asleep, the cycle counters contain no
+         * useful data. Better clear them now so that they don't mess up
+         * survey data results.
+         */
+        if (power_mode != ATH9K_PM_AWAKE) {
+                spin_lock(&common->cc_lock);
+                ath_hw_cycle_counters_update(common);
+                memset(&common->cc_survey, 0, sizeof(common->cc_survey));
+                spin_unlock(&common->cc_lock);
+        }
+
  unlock:
         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 }
 
 void ath9k_ps_restore(struct ath_softc *sc)
 {
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         unsigned long flags;
 
         spin_lock_irqsave(&sc->sc_pm_lock, flags);
         if (--sc->ps_usecount != 0)
                 goto unlock;
 
+        spin_lock(&common->cc_lock);
+        ath_hw_cycle_counters_update(common);
+        spin_unlock(&common->cc_lock);
+
         if (sc->ps_idle)
                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
         else if (sc->ps_enabled &&
@@ -175,6 +157,63 @@ static void ath_start_ani(struct ath_common *common)
                         msecs_to_jiffies((u32)ah->config.ani_poll_interval));
 }
 
+static void ath_update_survey_nf(struct ath_softc *sc, int channel)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *chan = &ah->channels[channel];
+        struct survey_info *survey = &sc->survey[channel];
+
+        if (chan->noisefloor) {
+                survey->filled |= SURVEY_INFO_NOISE_DBM;
+                survey->noise = chan->noisefloor;
+        }
+}
+
+/*
+ * Updates the survey statistics and returns the busy time since last
+ * update in %, if the measurement duration was long enough for the
+ * result to be useful, -1 otherwise.
+ */
+static int ath_update_survey_stats(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int pos = ah->curchan - &ah->channels[0];
+        struct survey_info *survey = &sc->survey[pos];
+        struct ath_cycle_counters *cc = &common->cc_survey;
+        unsigned int div = common->clockrate * 1000;
+        int ret = 0;
+
+        if (!ah->curchan)
+                return -1;
+
+        if (ah->power_mode == ATH9K_PM_AWAKE)
+                ath_hw_cycle_counters_update(common);
+
+        if (cc->cycles > 0) {
+                survey->filled |= SURVEY_INFO_CHANNEL_TIME |
+                        SURVEY_INFO_CHANNEL_TIME_BUSY |
+                        SURVEY_INFO_CHANNEL_TIME_RX |
+                        SURVEY_INFO_CHANNEL_TIME_TX;
+                survey->channel_time += cc->cycles / div;
+                survey->channel_time_busy += cc->rx_busy / div;
+                survey->channel_time_rx += cc->rx_frame / div;
+                survey->channel_time_tx += cc->tx_frame / div;
+        }
+
+        if (cc->cycles < div)
+                return -1;
+
+        if (cc->cycles > 0)
+                ret = cc->rx_busy * 100 / cc->cycles;
+
+        memset(cc, 0, sizeof(*cc));
+
+        ath_update_survey_nf(sc, pos);
+
+        return ret;
+}
+
 /*
  * Set/change channels.  If the channel is really being changed, it's done
  * by reseting the chip.  To accomplish this we must first cleanup any pending
@@ -183,7 +222,6 @@ static void ath_start_ani(struct ath_common *common)
 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                     struct ath9k_channel *hchan)
 {
-        struct ath_wiphy *aphy = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_conf *conf = &common->hw->conf;
@@ -195,13 +233,18 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
         if (sc->sc_flags & SC_OP_INVALID)
                 return -EIO;
 
+        sc->hw_busy_count = 0;
+
         del_timer_sync(&common->ani.timer);
         cancel_work_sync(&sc->paprd_work);
         cancel_work_sync(&sc->hw_check_work);
         cancel_delayed_work_sync(&sc->tx_complete_work);
+        cancel_delayed_work_sync(&sc->hw_pll_work);
 
         ath9k_ps_wakeup(sc);
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         /*
          * This is only performed if the channel settings have
          * actually changed.
@@ -211,9 +254,14 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
          * hardware at the new frequency, and then re-enable
          * the relevant bits of the h/w.
          */
-        ath9k_hw_set_interrupts(ah, 0);
-        ath_drain_all_txq(sc, false);
-        stopped = ath_stoprecv(sc);
+        ath9k_hw_disable_interrupts(ah);
+        stopped = ath_drain_all_txq(sc, false);
+
+        if (!ath_stoprecv(sc))
+                stopped = false;
+
+        if (!ath9k_hw_check_alive(ah))
+                stopped = false;
 
         /* XXX: do not flush receive queue here. We don't want
          * to flush data frames already in queue because of
@@ -223,44 +271,45 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                 fastcc = false;
 
         if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
-                caldata = &aphy->caldata;
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
-                  sc->sc_ah->curchan->channel,
-                  channel->center_freq, conf_is_ht40(conf));
+                caldata = &sc->caldata;
 
-        spin_lock_bh(&sc->sc_resetlock);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
+                sc->sc_ah->curchan->channel,
+                channel->center_freq, conf_is_ht40(conf),
+                fastcc);
 
         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
-                spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
                 goto ps_restore;
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to restart recv logic\n");
+                ath_err(common, "Unable to restart recv logic\n");
                 r = -EIO;
                 goto ps_restore;
         }
 
-        ath_cache_conf_rate(sc, &hw->conf);
-        ath_update_txpow(sc);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                               sc->config.txpowlimit, &sc->curtxpow);
         ath9k_hw_set_interrupts(ah, ah->imask);
 
-        if (!(sc->sc_flags & (SC_OP_OFFCHANNEL | SC_OP_SCANNING))) {
-                ath_start_ani(common);
+        if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
+                if (sc->sc_flags & SC_OP_BEACONS)
+                        ath_set_beacon(sc);
                 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
-                ath_beacon_config(sc, NULL);
+                ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
+                ath_start_ani(common);
         }
 
  ps_restore:
+        ieee80211_wake_queues(hw);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
         return r;
 }
@@ -269,6 +318,7 @@ static void ath_paprd_activate(struct ath_softc *sc)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
+        struct ath_common *common = ath9k_hw_common(ah);
         int chain;
 
         if (!caldata || !caldata->paprd_done)
@@ -277,7 +327,7 @@ static void ath_paprd_activate(struct ath_softc *sc)
         ath9k_ps_wakeup(sc);
         ar9003_paprd_enable(ah, false);
         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
-                if (!(ah->caps.tx_chainmask & BIT(chain)))
+                if (!(common->tx_chainmask & BIT(chain)))
                         continue;
 
                 ar9003_paprd_populate_single_table(ah, caldata, chain);
@@ -287,6 +337,46 @@ static void ath_paprd_activate(struct ath_softc *sc)
         ath9k_ps_restore(sc);
 }
 
+static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
+{
+        struct ieee80211_hw *hw = sc->hw;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath_tx_control txctl;
+        int time_left;
+
+        memset(&txctl, 0, sizeof(txctl));
+        txctl.txq = sc->tx.txq_map[WME_AC_BE];
+
+        memset(tx_info, 0, sizeof(*tx_info));
+        tx_info->band = hw->conf.channel->band;
+        tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
+        tx_info->control.rates[0].idx = 0;
+        tx_info->control.rates[0].count = 1;
+        tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
+        tx_info->control.rates[1].idx = -1;
+
+        init_completion(&sc->paprd_complete);
+        txctl.paprd = BIT(chain);
+
+        if (ath_tx_start(hw, skb, &txctl) != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
+                dev_kfree_skb_any(skb);
+                return false;
+        }
+
+        time_left = wait_for_completion_timeout(&sc->paprd_complete,
+                        msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
+
+        if (!time_left)
+                ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
+                        "Timeout waiting for paprd training on TX chain %d\n",
+                        chain);
+
+        return !!time_left;
+}
+
 void ath_paprd_calibrate(struct work_struct *work)
 {
         struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
@@ -294,27 +384,23 @@ void ath_paprd_calibrate(struct work_struct *work)
         struct ath_hw *ah = sc->sc_ah;
         struct ieee80211_hdr *hdr;
         struct sk_buff *skb = NULL;
-        struct ieee80211_tx_info *tx_info;
-        int band = hw->conf.channel->band;
-        struct ieee80211_supported_band *sband = &sc->sbands[band];
-        struct ath_tx_control txctl;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
-        int qnum, ftype;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ftype;
         int chain_ok = 0;
         int chain;
         int len = 1800;
-        int time_left;
-        int i;
 
         if (!caldata)
                 return;
 
+        if (ar9003_paprd_init_table(ah) < 0)
+                return;
+
         skb = alloc_skb(len, GFP_KERNEL);
         if (!skb)
                 return;
 
-        tx_info = IEEE80211_SKB_CB(skb);
-
         skb_put(skb, len);
         memset(skb->data, 0, len);
         hdr = (struct ieee80211_hdr *)skb->data;
@@ -325,40 +411,25 @@ void ath_paprd_calibrate(struct work_struct *work)
         memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
         memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
 
-        memset(&txctl, 0, sizeof(txctl));
-        qnum = sc->tx.hwq_map[WME_AC_BE];
-        txctl.txq = &sc->tx.txq[qnum];
-
         ath9k_ps_wakeup(sc);
-        ar9003_paprd_init_table(ah);
         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
-                if (!(ah->caps.tx_chainmask & BIT(chain)))
+                if (!(common->tx_chainmask & BIT(chain)))
                         continue;
 
                 chain_ok = 0;
-                memset(tx_info, 0, sizeof(*tx_info));
-                tx_info->band = band;
 
-                for (i = 0; i < 4; i++) {
-                        tx_info->control.rates[i].idx = sband->n_bitrates - 1;
-                        tx_info->control.rates[i].count = 6;
-                }
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Sending PAPRD frame for thermal measurement "
+                        "on chain %d\n", chain);
+                if (!ath_paprd_send_frame(sc, skb, chain))
+                        goto fail_paprd;
 
-                init_completion(&sc->paprd_complete);
                 ar9003_paprd_setup_gain_table(ah, chain);
-                txctl.paprd = BIT(chain);
-                if (ath_tx_start(hw, skb, &txctl) != 0)
-                        break;
 
-                time_left = wait_for_completion_timeout(&sc->paprd_complete,
-                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
-                if (!time_left) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                                  "Timeout waiting for paprd training on "
-                                  "TX chain %d\n",
-                                  chain);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Sending PAPRD training frame on chain %d\n", chain);
+                if (!ath_paprd_send_frame(sc, skb, chain))
                         goto fail_paprd;
-                }
 
                 if (!ar9003_paprd_is_done(ah))
                         break;
@@ -395,7 +466,13 @@ void ath_ani_calibrate(unsigned long data)
         bool shortcal = false;
         bool aniflag = false;
         unsigned int timestamp = jiffies_to_msecs(jiffies);
-        u32 cal_interval, short_cal_interval;
+        u32 cal_interval, short_cal_interval, long_cal_interval;
+        unsigned long flags;
+
+        if (ah->caldata && ah->caldata->nfcal_interference)
+                long_cal_interval = ATH_LONG_CALINTERVAL_INT;
+        else
+                long_cal_interval = ATH_LONG_CALINTERVAL;
 
         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
@@ -407,9 +484,9 @@ void ath_ani_calibrate(unsigned long data)
         ath9k_ps_wakeup(sc);
 
         /* Long calibration runs independently of short calibration. */
-        if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
+        if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
                 longcal = true;
-                ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
+                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -417,8 +494,8 @@ void ath_ani_calibrate(unsigned long data)
         if (!common->ani.caldone) {
                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
                         shortcal = true;
-                        ath_print(common, ATH_DBG_ANI,
-                                  "shortcal @%lu\n", jiffies);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -441,8 +518,12 @@ void ath_ani_calibrate(unsigned long data)
         /* Skip all processing if there's nothing to do. */
         if (longcal || shortcal || aniflag) {
                 /* Call ANI routine if necessary */
-                if (aniflag)
+                if (aniflag) {
+                        spin_lock_irqsave(&common->cc_lock, flags);
                         ath9k_hw_ani_monitor(ah, ah->curchan);
+                        ath_update_survey_stats(sc);
+                        spin_unlock_irqrestore(&common->cc_lock, flags);
+                }
 
                 /* Perform calibration if necessary */
                 if (longcal || shortcal) {
@@ -451,16 +532,6 @@ void ath_ani_calibrate(unsigned long data)
                                                    ah->curchan,
                                                    common->rx_chainmask,
                                                    longcal);
-
-                        if (longcal)
-                                common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
-                                                                     ah->curchan);
-
-                        ath_print(common, ATH_DBG_ANI,
-                                  " calibrate chan %u/%x nf: %d\n",
-                                  ah->curchan->channel,
-                                  ah->curchan->channelFlags,
-                                  common->ani.noise_floor);
                 }
         }
 
@@ -483,49 +554,31 @@ set_timer:
         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
                 if (!ah->caldata->paprd_done)
                         ieee80211_queue_work(sc->hw, &sc->paprd_work);
-                else
+                else if (!ah->paprd_table_write_done)
                         ath_paprd_activate(sc);
         }
 }
 
-/*
- * Update tx/rx chainmask. For legacy association,
- * hard code chainmask to 1x1, for 11n association, use
- * the chainmask configuration, for bt coexistence, use
- * the chainmask configuration even in legacy mode.
- */
-void ath_update_chainmask(struct ath_softc *sc, int is_ht)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
-            (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
-                common->tx_chainmask = ah->caps.tx_chainmask;
-                common->rx_chainmask = ah->caps.rx_chainmask;
-        } else {
-                common->tx_chainmask = 1;
-                common->rx_chainmask = 1;
-        }
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "tx chmask: %d, rx chmask: %d\n",
-                  common->tx_chainmask,
-                  common->rx_chainmask);
-}
-
 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 {
         struct ath_node *an;
-
+        struct ath_hw *ah = sc->sc_ah;
         an = (struct ath_node *)sta->drv_priv;
 
+#ifdef CONFIG_ATH9K_DEBUGFS
+        spin_lock(&sc->nodes_lock);
+        list_add(&an->list, &sc->nodes);
+        spin_unlock(&sc->nodes_lock);
+        an->sta = sta;
+#endif
+        if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
+                sc->sc_flags |= SC_OP_ENABLE_APM;
+
         if (sc->sc_flags & SC_OP_TXAGGR) {
                 ath_tx_node_init(sc, an);
                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
                                      sta->ht_cap.ampdu_factor);
                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
-                an->last_rssi = ATH_RSSI_DUMMY_MARKER;
         }
 }
 
@@ -533,6 +586,13 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 
+#ifdef CONFIG_ATH9K_DEBUGFS
+        spin_lock(&sc->nodes_lock);
+        list_del(&an->list);
+        spin_unlock(&sc->nodes_lock);
+        an->sta = NULL;
+#endif
+
         if (sc->sc_flags & SC_OP_TXAGGR)
                 ath_tx_node_cleanup(sc, an);
 }
@@ -540,22 +600,67 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 void ath_hw_check(struct work_struct *work)
 {
         struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
-        int i;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        unsigned long flags;
+        int busy;
 
         ath9k_ps_wakeup(sc);
+        if (ath9k_hw_check_alive(sc->sc_ah))
+                goto out;
 
-        for (i = 0; i < 3; i++) {
-                if (ath9k_hw_check_alive(sc->sc_ah))
-                        goto out;
+        spin_lock_irqsave(&common->cc_lock, flags);
+        busy = ath_update_survey_stats(sc);
+        spin_unlock_irqrestore(&common->cc_lock, flags);
 
-                msleep(1);
-        }
-        ath_reset(sc, false);
+        ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
+                "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
+        if (busy >= 99) {
+                if (++sc->hw_busy_count >= 3)
+                        ath_reset(sc, true);
+        } else if (busy >= 0)
+                sc->hw_busy_count = 0;
 
 out:
         ath9k_ps_restore(sc);
 }
 
+static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
+{
+        static int count;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+
+        if (pll_sqsum >= 0x40000) {
+                count++;
+                if (count == 3) {
+                        /* Rx is hung for more than 500ms. Reset it */
+                        ath_dbg(common, ATH_DBG_RESET,
+                                "Possible RX hang, resetting");
+                        ath_reset(sc, true);
+                        count = 0;
+                }
+        } else
+                count = 0;
+}
+
+void ath_hw_pll_work(struct work_struct *work)
+{
+        struct ath_softc *sc = container_of(work, struct ath_softc,
+                                            hw_pll_work.work);
+        u32 pll_sqsum;
+
+        if (AR_SREV_9485(sc->sc_ah)) {
+
+                ath9k_ps_wakeup(sc);
+                pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
+                ath9k_ps_restore(sc);
+
+                ath_hw_pll_rx_hang_check(sc, pll_sqsum);
+
+                ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
+        }
+}
+
+
 void ath9k_tasklet(unsigned long data)
 {
         struct ath_softc *sc = (struct ath_softc *)data;
@@ -565,17 +670,37 @@ void ath9k_tasklet(unsigned long data)
         u32 status = sc->intrstatus;
         u32 rxmask;
 
-        ath9k_ps_wakeup(sc);
-
-        if (status & ATH9K_INT_FATAL) {
-                ath_reset(sc, false);
-                ath9k_ps_restore(sc);
+        if ((status & ATH9K_INT_FATAL) ||
+            (status & ATH9K_INT_BB_WATCHDOG)) {
+                ath_reset(sc, true);
                 return;
         }
 
-        if (!ath9k_hw_check_alive(ah))
+        ath9k_ps_wakeup(sc);
+        spin_lock(&sc->sc_pcu_lock);
+
+        /*
+         * Only run the baseband hang check if beacons stop working in AP or
+         * IBSS mode, because it has a high false positive rate. For station
+         * mode it should not be necessary, since the upper layers will detect
+         * this through a beacon miss automatically and the following channel
+         * change will trigger a hardware reset anyway
+         */
+        if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
+            !ath9k_hw_check_alive(ah))
                 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 
+        if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
+                /*
+                 * TSF sync does not look correct; remain awake to sync with
+                 * the next Beacon.
+                 */
+                ath_dbg(common, ATH_DBG_PS,
+                        "TSFOOR - Sync with next Beacon\n");
+                sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
+                                PS_TSFOOR_SYNC;
+        }
+
         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
                           ATH9K_INT_RXORN);
@@ -583,15 +708,12 @@ void ath9k_tasklet(unsigned long data)
                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 
         if (status & rxmask) {
-                spin_lock_bh(&sc->rx.rxflushlock);
-
                 /* Check for high priority Rx first */
                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
                     (status & ATH9K_INT_RXHP))
                         ath_rx_tasklet(sc, 0, true);
 
                 ath_rx_tasklet(sc, 0, false);
-                spin_unlock_bh(&sc->rx.rxflushlock);
         }
 
         if (status & ATH9K_INT_TX) {
@@ -601,22 +723,14 @@ void ath9k_tasklet(unsigned long data)
                         ath_tx_tasklet(sc);
         }
 
-        if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
-                /*
-                 * TSF sync does not look correct; remain awake to sync with
-                 * the next Beacon.
-                 */
-                ath_print(common, ATH_DBG_PS,
-                          "TSFOOR - Sync with next Beacon\n");
-                sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
-        }
-
         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
                 if (status & ATH9K_INT_GENTIMER)
                         ath_gen_timer_isr(sc->sc_ah);
 
         /* re-enable hardware interrupt */
-        ath9k_hw_set_interrupts(ah, ah->imask);
+        ath9k_hw_enable_interrupts(ah);
+
+        spin_unlock(&sc->sc_pcu_lock);
         ath9k_ps_restore(sc);
 }
 
@@ -624,6 +738,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 {
 #define SCHED_INTR (                            \
                 ATH9K_INT_FATAL |               \
+                ATH9K_INT_BB_WATCHDOG |         \
                 ATH9K_INT_RXORN |               \
                 ATH9K_INT_RXEOL |               \
                 ATH9K_INT_RX |                  \
@@ -637,6 +752,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 
         struct ath_softc *sc = dev;
         struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
         enum ath9k_int status;
         bool sched = false;
 
@@ -686,7 +802,12 @@ irqreturn_t ath_isr(int irq, void *dev)
 
         if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
             (status & ATH9K_INT_BB_WATCHDOG)) {
+
+                spin_lock(&common->cc_lock);
+                ath_hw_cycle_counters_update(common);
                 ar9003_hw_bb_watchdog_dbg_info(ah);
+                spin_unlock(&common->cc_lock);
+
                 goto chip_reset;
         }
 
@@ -709,18 +830,22 @@ irqreturn_t ath_isr(int irq, void *dev)
                  * interrupt; otherwise it will continue to
                  * fire.
                  */
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 /*
                  * Let the hal handle the event. We assume
                  * it will clear whatever condition caused
                  * the interrupt.
                  */
-                ath9k_hw_procmibevent(ah);
-                ath9k_hw_set_interrupts(ah, ah->imask);
+                spin_lock(&common->cc_lock);
+                ath9k_hw_proc_mib_event(ah);
+                spin_unlock(&common->cc_lock);
+                ath9k_hw_enable_interrupts(ah);
         }
 
         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                 if (status & ATH9K_INT_TIM_TIMER) {
+                        if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
+                                goto chip_reset;
                         /* Clear RxAbort bit so that we can
                          * receive frames */
                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
@@ -733,8 +858,8 @@ chip_reset:
         ath_debug_stat_interrupt(sc, status);
 
         if (sched) {
-                /* turn off every interrupt except SWBA */
-                ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
+                /* turn off every interrupt */
+                ath9k_hw_disable_interrupts(ah);
                 tasklet_schedule(&sc->intr_tq);
         }
 
@@ -743,88 +868,6 @@ chip_reset:
 #undef SCHED_INTR
 }
 
-static u32 ath_get_extchanmode(struct ath_softc *sc,
-                               struct ieee80211_channel *chan,
-                               enum nl80211_channel_type channel_type)
-{
-        u32 chanmode = 0;
-
-        switch (chan->band) {
-        case IEEE80211_BAND_2GHZ:
-                switch(channel_type) {
-                case NL80211_CHAN_NO_HT:
-                case NL80211_CHAN_HT20:
-                        chanmode = CHANNEL_G_HT20;
-                        break;
-                case NL80211_CHAN_HT40PLUS:
-                        chanmode = CHANNEL_G_HT40PLUS;
-                        break;
-                case NL80211_CHAN_HT40MINUS:
-                        chanmode = CHANNEL_G_HT40MINUS;
-                        break;
-                }
-                break;
-        case IEEE80211_BAND_5GHZ:
-                switch(channel_type) {
-                case NL80211_CHAN_NO_HT:
-                case NL80211_CHAN_HT20:
-                        chanmode = CHANNEL_A_HT20;
-                        break;
-                case NL80211_CHAN_HT40PLUS:
-                        chanmode = CHANNEL_A_HT40PLUS;
-                        break;
-                case NL80211_CHAN_HT40MINUS:
-                        chanmode = CHANNEL_A_HT40MINUS;
-                        break;
-                }
-                break;
-        default:
-                break;
-        }
-
-        return chanmode;
-}
-
-static void ath9k_bss_assoc_info(struct ath_softc *sc,
-                                 struct ieee80211_vif *vif,
-                                 struct ieee80211_bss_conf *bss_conf)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if (bss_conf->assoc) {
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Bss Info ASSOC %d, bssid: %pM\n",
-                           bss_conf->aid, common->curbssid);
-
-                /* New association, store aid */
-                common->curaid = bss_conf->aid;
-                ath9k_hw_write_associd(ah);
-
-                /*
-                 * Request a re-configuration of Beacon related timers
-                 * on the receipt of the first Beacon frame (i.e.,
-                 * after time sync with the AP).
-                 */
-                sc->ps_flags |= PS_BEACON_SYNC;
-
-                /* Configure the beacon */
-                ath_beacon_config(sc, vif);
-
-                /* Reset rssi stats */
-                sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
-
-                sc->sc_flags |= SC_OP_ANI_RUN;
-                ath_start_ani(common);
-        } else {
-                ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
-                common->curaid = 0;
-                /* Stop ANI */
-                sc->sc_flags &= ~SC_OP_ANI_RUN;
-                del_timer_sync(&common->ani.timer);
-        }
-}
-
 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
 {
         struct ath_hw *ah = sc->sc_ah;
@@ -833,30 +876,28 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
         int r;
 
         ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ath9k_hw_configpcipowersave(ah, 0, 0);
 
         if (!ah->curchan)
-                ah->curchan = ath_get_curchannel(sc, sc->hw);
+                ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
+                ath_err(common,
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
-        ath_update_txpow(sc);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                               sc->config.txpowlimit, &sc->curtxpow);
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to restart recv logic\n");
-                return;
+                ath_err(common, "Unable to restart recv logic\n");
+                goto out;
         }
-
         if (sc->sc_flags & SC_OP_BEACONS)
-                ath_beacon_config(sc, NULL);    /* restart beacons */
+                ath_set_beacon(sc);     /* restart beacons */
 
         /* Re-Enable  interrupts */
         ath9k_hw_set_interrupts(ah, ah->imask);
@@ -867,6 +908,11 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
 
         ieee80211_wake_queues(hw);
+        ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
+
+out:
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
 }
 
@@ -877,6 +923,10 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
         int r;
 
         ath9k_ps_wakeup(sc);
+        cancel_delayed_work_sync(&sc->hw_pll_work);
+
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ieee80211_stop_queues(hw);
 
         /*
@@ -889,29 +939,29 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
         }
 
         /* Disable interrupts */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
 
         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
+
         ath_stoprecv(sc);               /* turn off frame recv */
         ath_flushrecv(sc);              /* flush recv queue */
 
         if (!ah->curchan)
-                ah->curchan = ath_get_curchannel(sc, hw);
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
         if (r) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         ath9k_hw_phy_disable(ah);
+
         ath9k_hw_configpcipowersave(ah, 1, 1);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
         ath9k_ps_restore(sc);
-        ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
 }
 
 int ath_reset(struct ath_softc *sc, bool retry_tx)
@@ -921,38 +971,40 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         struct ieee80211_hw *hw = sc->hw;
         int r;
 
+        sc->hw_busy_count = 0;
+
         /* Stop ANI */
         del_timer_sync(&common->ani.timer);
 
+        ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ieee80211_stop_queues(hw);
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath_drain_all_txq(sc, retry_tx);
+
         ath_stoprecv(sc);
         ath_flushrecv(sc);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
         if (r)
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d\n", r);
-        spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d\n", r);
 
         if (ath_startrecv(sc) != 0)
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to start recv logic\n");
+                ath_err(common, "Unable to start recv logic\n");
 
         /*
          * We may be doing a reset in response to a request
          * that changes the channel so update any state that
          * might change as a result.
          */
-        ath_cache_conf_rate(sc, &hw->conf);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                               sc->config.txpowlimit, &sc->curtxpow);
 
-        ath_update_txpow(sc);
-
-        if (sc->sc_flags & SC_OP_BEACONS)
-                ath_beacon_config(sc, NULL);    /* restart beacons */
+        if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
+                ath_set_beacon(sc);     /* restart beacons */
 
         ath9k_hw_set_interrupts(ah, ah->imask);
 
@@ -968,133 +1020,40 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         }
 
         ieee80211_wake_queues(hw);
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         /* Start ANI */
         ath_start_ani(common);
+        ath9k_ps_restore(sc);
 
         return r;
 }
 
-static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
-{
-        int qnum;
-
-        switch (queue) {
-        case 0:
-                qnum = sc->tx.hwq_map[WME_AC_VO];
-                break;
-        case 1:
-                qnum = sc->tx.hwq_map[WME_AC_VI];
-                break;
-        case 2:
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                break;
-        case 3:
-                qnum = sc->tx.hwq_map[WME_AC_BK];
-                break;
-        default:
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                break;
-        }
-
-        return qnum;
-}
-
-int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
-{
-        int qnum;
-
-        switch (queue) {
-        case WME_AC_VO:
-                qnum = 0;
-                break;
-        case WME_AC_VI:
-                qnum = 1;
-                break;
-        case WME_AC_BE:
-                qnum = 2;
-                break;
-        case WME_AC_BK:
-                qnum = 3;
-                break;
-        default:
-                qnum = -1;
-                break;
-        }
-
-        return qnum;
-}
-
-/* XXX: Remove me once we don't depend on ath9k_channel for all
- * this redundant data */
-void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
-                           struct ath9k_channel *ichan)
-{
-        struct ieee80211_channel *chan = hw->conf.channel;
-        struct ieee80211_conf *conf = &hw->conf;
-
-        ichan->channel = chan->center_freq;
-        ichan->chan = chan;
-
-        if (chan->band == IEEE80211_BAND_2GHZ) {
-                ichan->chanmode = CHANNEL_G;
-                ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
-        } else {
-                ichan->chanmode = CHANNEL_A;
-                ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
-        }
-
-        if (conf_is_ht(conf))
-                ichan->chanmode = ath_get_extchanmode(sc, chan,
-                                            conf->channel_type);
-}
-
 /**********************/
 /* mac80211 callbacks */
 /**********************/
 
 static int ath9k_start(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_channel *curchan = hw->conf.channel;
         struct ath9k_channel *init_channel;
         int r;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Starting driver with initial channel: %d MHz\n",
-                  curchan->center_freq);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Starting driver with initial channel: %d MHz\n",
+                curchan->center_freq);
 
-        mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
 
-        if (ath9k_wiphy_started(sc)) {
-                if (sc->chan_idx == curchan->hw_value) {
-                        /*
-                         * Already on the operational channel, the new wiphy
-                         * can be marked active.
-                         */
-                        aphy->state = ATH_WIPHY_ACTIVE;
-                        ieee80211_wake_queues(hw);
-                } else {
-                        /*
-                         * Another wiphy is on another channel, start the new
-                         * wiphy in paused state.
-                         */
-                        aphy->state = ATH_WIPHY_PAUSED;
-                        ieee80211_stop_queues(hw);
-                }
-                mutex_unlock(&sc->mutex);
-                return 0;
-        }
-        aphy->state = ATH_WIPHY_ACTIVE;
+        mutex_lock(&sc->mutex);
 
         /* setup initial channel */
-
         sc->chan_idx = curchan->hw_value;
 
-        init_channel = ath_get_curchannel(sc, hw);
+        init_channel = ath9k_cmn_get_curchannel(hw, ah);
 
         /* Reset SERDES registers */
         ath9k_hw_configpcipowersave(ah, 0, 0);
@@ -1106,23 +1065,22 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * be followed by initialization of the appropriate bits
          * and then setup of the interrupt mask.
          */
-        spin_lock_bh(&sc->sc_resetlock);
+        spin_lock_bh(&sc->sc_pcu_lock);
         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", r,
-                          curchan->center_freq);
-                spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        r, curchan->center_freq);
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 goto mutex_unlock;
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         /*
          * This is needed only to setup initial state
          * but it's best done after a reset.
          */
-        ath_update_txpow(sc);
+        ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                        sc->config.txpowlimit, &sc->curtxpow);
 
         /*
          * Setup the hardware after reset:
@@ -1132,11 +1090,12 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * here except setup the interrupt mask.
          */
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to start recv logic\n");
+                ath_err(common, "Unable to start recv logic\n");
                 r = -EIO;
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 goto mutex_unlock;
         }
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         /* Setup our intr mask. */
         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
@@ -1150,15 +1109,13 @@ static int ath9k_start(struct ieee80211_hw *hw)
         else
                 ah->imask |= ATH9K_INT_RX;
 
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
-                ah->imask |= ATH9K_INT_GTT;
+        ah->imask |= ATH9K_INT_GTT;
 
         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
                 ah->imask |= ATH9K_INT_CST;
 
-        ath_cache_conf_rate(sc, &hw->conf);
-
         sc->sc_flags &= ~SC_OP_INVALID;
+        sc->sc_ah->is_monitoring = false;
 
         /* Disable BMISS interrupt when we're not associated */
         ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
@@ -1180,30 +1137,23 @@ static int ath9k_start(struct ieee80211_hw *hw)
                         ath9k_btcoex_timer_resume(sc);
         }
 
+        if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
+                common->bus_ops->extn_synch_en(common);
+
 mutex_unlock:
         mutex_unlock(&sc->mutex);
 
+        ath9k_ps_restore(sc);
+
         return r;
 }
 
-static int ath9k_tx(struct ieee80211_hw *hw,
-                    struct sk_buff *skb)
+static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 {
-        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_tx_control txctl;
-        int padpos, padsize;
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
-        int qnum;
-
-        if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
-                ath_print(common, ATH_DBG_XMIT,
-                          "ath9k: %s: TX in unexpected wiphy state "
-                          "%d\n", wiphy_name(hw->wiphy), aphy->state);
-                goto exit;
-        }
 
         if (sc->ps_enabled) {
                 /*
@@ -1213,8 +1163,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
                 if (ieee80211_is_data(hdr->frame_control) &&
                     !ieee80211_is_nullfunc(hdr->frame_control) &&
                     !ieee80211_has_pm(hdr->frame_control)) {
-                        ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
-                                  "while in PS mode\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Add PM=1 for a TX frame while in PS mode\n");
                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
                 }
         }
@@ -1229,12 +1179,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                         ath9k_hw_setrxabort(sc->sc_ah, 0);
                 if (ieee80211_is_pspoll(hdr->frame_control)) {
-                        ath_print(common, ATH_DBG_PS,
-                                  "Sending PS-Poll to pick a buffered frame\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Sending PS-Poll to pick a buffered frame\n");
                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
                 } else {
-                        ath_print(common, ATH_DBG_PS,
-                                  "Wake up to complete TX\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Wake up to complete TX\n");
                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
                 }
                 /*
@@ -1246,85 +1196,39 @@ static int ath9k_tx(struct ieee80211_hw *hw,
         }
 
         memset(&txctl, 0, sizeof(struct ath_tx_control));
+        txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 
-        /*
-         * As a temporary workaround, assign seq# here; this will likely need
-         * to be cleaned up to work better with Beacon transmission and virtual
-         * BSSes.
-         */
-        if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
-                if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
-                        sc->tx.seq_no += 0x10;
-                hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
-                hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
-        }
-
-        /* Add the padding after the header if this is not already done */
-        padpos = ath9k_cmn_padpos(hdr->frame_control);
-        padsize = padpos & 3;
-        if (padsize && skb->len>padpos) {
-                if (skb_headroom(skb) < padsize)
-                        return -1;
-                skb_push(skb, padsize);
-                memmove(skb->data, skb->data + padsize, padpos);
-        }
-
-        qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
-        txctl.txq = &sc->tx.txq[qnum];
-
-        ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
+        ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
 
         if (ath_tx_start(hw, skb, &txctl) != 0) {
-                ath_print(common, ATH_DBG_XMIT, "TX failed\n");
+                ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
                 goto exit;
         }
 
-        return 0;
+        return;
 exit:
         dev_kfree_skb_any(skb);
-        return 0;
 }
 
 static void ath9k_stop(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
-        int i;
 
         mutex_lock(&sc->mutex);
 
-        aphy->state = ATH_WIPHY_INACTIVE;
-
-        if (led_blink)
-                cancel_delayed_work_sync(&sc->ath_led_blink_work);
-
         cancel_delayed_work_sync(&sc->tx_complete_work);
+        cancel_delayed_work_sync(&sc->hw_pll_work);
         cancel_work_sync(&sc->paprd_work);
         cancel_work_sync(&sc->hw_check_work);
 
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i])
-                        break;
-        }
-
-        if (i == sc->num_sec_wiphy) {
-                cancel_delayed_work_sync(&sc->wiphy_work);
-                cancel_work_sync(&sc->chan_work);
-        }
-
         if (sc->sc_flags & SC_OP_INVALID) {
-                ath_print(common, ATH_DBG_ANY, "Device not present\n");
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&sc->mutex);
                 return;
         }
 
-        if (ath9k_wiphy_started(sc)) {
-                mutex_unlock(&sc->mutex);
-                return; /* another wiphy still in use */
-        }
-
         /* Ensure HW is awake when we try to shut it down. */
         ath9k_ps_wakeup(sc);
 
@@ -1334,9 +1238,14 @@ static void ath9k_stop(struct ieee80211_hw *hw)
                         ath9k_btcoex_timer_pause(sc);
         }
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
+        /* prevent tasklets to enable interrupts once we disable them */
+        ah->imask &= ~ATH9K_INT_GLOBAL;
+
         /* make sure h/w will not generate any interrupt
          * before setting the invalid flag. */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
 
         if (!(sc->sc_flags & SC_OP_INVALID)) {
                 ath_drain_all_txq(sc, false);
@@ -1345,153 +1254,325 @@ static void ath9k_stop(struct ieee80211_hw *hw)
         } else
                 sc->rx.rxlink = NULL;
 
+        if (sc->rx.frag) {
+                dev_kfree_skb_any(sc->rx.frag);
+                sc->rx.frag = NULL;
+        }
+
         /* disable HAL and put h/w to sleep */
         ath9k_hw_disable(ah);
         ath9k_hw_configpcipowersave(ah, 1, 1);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
+        /* we can now sync irq and kill any running tasklets, since we already
+         * disabled interrupts and not holding a spin lock */
+        synchronize_irq(sc->irq);
+        tasklet_kill(&sc->intr_tq);
+        tasklet_kill(&sc->bcon_tasklet);
+
         ath9k_ps_restore(sc);
 
-        /* Finally, put the chip in FULL SLEEP mode */
-        ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
+        sc->ps_idle = true;
+        ath_radio_disable(sc, hw);
 
         sc->sc_flags |= SC_OP_INVALID;
 
         mutex_unlock(&sc->mutex);
 
-        ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
 }
 
-static int ath9k_add_interface(struct ieee80211_hw *hw,
-                               struct ieee80211_vif *vif)
+bool ath9k_uses_beacons(int type)
+{
+        switch (type) {
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_MESH_POINT:
+                return true;
+        default:
+                return false;
+        }
+}
+
+static void ath9k_reclaim_beacon(struct ath_softc *sc,
+                                 struct ieee80211_vif *vif)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
         struct ath_vif *avp = (void *)vif->drv_priv;
-        enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
-        int ret = 0;
 
-        mutex_lock(&sc->mutex);
+        ath9k_set_beaconing_status(sc, false);
+        ath_beacon_return(sc, avp);
+        ath9k_set_beaconing_status(sc, true);
+        sc->sc_flags &= ~SC_OP_BEACONS;
+}
 
-        if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
-            sc->nvifs > 0) {
-                ret = -ENOBUFS;
-                goto out;
-        }
+static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath9k_vif_iter_data *iter_data = data;
+        int i;
+
+        if (iter_data->hw_macaddr)
+                for (i = 0; i < ETH_ALEN; i++)
+                        iter_data->mask[i] &=
+                                ~(iter_data->hw_macaddr[i] ^ mac[i]);
 
         switch (vif->type) {
+        case NL80211_IFTYPE_AP:
+                iter_data->naps++;
+                break;
         case NL80211_IFTYPE_STATION:
-                ic_opmode = NL80211_IFTYPE_STATION;
+                iter_data->nstations++;
                 break;
         case NL80211_IFTYPE_ADHOC:
-        case NL80211_IFTYPE_AP:
+                iter_data->nadhocs++;
+                break;
         case NL80211_IFTYPE_MESH_POINT:
-                if (sc->nbcnvifs >= ATH_BCBUF) {
-                        ret = -ENOBUFS;
-                        goto out;
-                }
-                ic_opmode = vif->type;
+                iter_data->nmeshes++;
+                break;
+        case NL80211_IFTYPE_WDS:
+                iter_data->nwds++;
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                        "Interface type %d not yet supported\n", vif->type);
-                ret = -EOPNOTSUPP;
-                goto out;
+                iter_data->nothers++;
+                break;
         }
+}
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Attach a VIF of type: %d\n", ic_opmode);
+/* Called with sc->mutex held. */
+void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               struct ath9k_vif_iter_data *iter_data)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        /*
+         * Use the hardware MAC address as reference, the hardware uses it
+         * together with the BSSID mask when matching addresses.
+         */
+        memset(iter_data, 0, sizeof(*iter_data));
+        iter_data->hw_macaddr = common->macaddr;
+        memset(&iter_data->mask, 0xff, ETH_ALEN);
 
-        /* Set the VIF opmode */
-        avp->av_opmode = ic_opmode;
-        avp->av_bslot = -1;
+        if (vif)
+                ath9k_vif_iter(iter_data, vif->addr, vif);
 
-        sc->nvifs++;
+        /* Get list of all active MAC addresses */
+        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
+                                                   iter_data);
+}
+
+/* Called with sc->mutex held. */
+static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
+                                          struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_vif_iter_data iter_data;
 
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                ath9k_set_bssid_mask(hw);
+        ath9k_calculate_iter_data(hw, vif, &iter_data);
 
-        if (sc->nvifs > 1)
-                goto out; /* skip global settings for secondary vif */
+        /* Set BSSID mask. */
+        memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
+        ath_hw_setbssidmask(common);
 
-        if (ic_opmode == NL80211_IFTYPE_AP) {
+        /* Set op-mode & TSF */
+        if (iter_data.naps > 0) {
                 ath9k_hw_set_tsfadjust(ah, 1);
                 sc->sc_flags |= SC_OP_TSF_RESET;
+                ah->opmode = NL80211_IFTYPE_AP;
+        } else {
+                ath9k_hw_set_tsfadjust(ah, 0);
+                sc->sc_flags &= ~SC_OP_TSF_RESET;
+
+                if (iter_data.nmeshes)
+                        ah->opmode = NL80211_IFTYPE_MESH_POINT;
+                else if (iter_data.nwds)
+                        ah->opmode = NL80211_IFTYPE_AP;
+                else if (iter_data.nadhocs)
+                        ah->opmode = NL80211_IFTYPE_ADHOC;
+                else
+                        ah->opmode = NL80211_IFTYPE_STATION;
         }
 
-        /* Set the device opmode */
-        ah->opmode = ic_opmode;
-
         /*
          * Enable MIB interrupts when there are hardware phy counters.
-         * Note we only do this (at the moment) for station mode.
          */
-        if ((vif->type == NL80211_IFTYPE_STATION) ||
-            (vif->type == NL80211_IFTYPE_ADHOC) ||
-            (vif->type == NL80211_IFTYPE_MESH_POINT)) {
+        if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
                 if (ah->config.enable_ani)
                         ah->imask |= ATH9K_INT_MIB;
                 ah->imask |= ATH9K_INT_TSFOOR;
+        } else {
+                ah->imask &= ~ATH9K_INT_MIB;
+                ah->imask &= ~ATH9K_INT_TSFOOR;
         }
 
         ath9k_hw_set_interrupts(ah, ah->imask);
 
-        if (vif->type == NL80211_IFTYPE_AP    ||
-            vif->type == NL80211_IFTYPE_ADHOC ||
-            vif->type == NL80211_IFTYPE_MONITOR) {
+        /* Set up ANI */
+        if ((iter_data.naps + iter_data.nadhocs) > 0) {
+                sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
                 sc->sc_flags |= SC_OP_ANI_RUN;
                 ath_start_ani(common);
+        } else {
+                sc->sc_flags &= ~SC_OP_ANI_RUN;
+                del_timer_sync(&common->ani.timer);
         }
+}
+
+/* Called with sc->mutex held, vif counts set up properly. */
+static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
+                                   struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+
+        ath9k_calculate_summary_state(hw, vif);
+
+        if (ath9k_uses_beacons(vif->type)) {
+                int error;
+                /* This may fail because upper levels do not have beacons
+                 * properly configured yet.  That's OK, we assume it
+                 * will be properly configured and then we will be notified
+                 * in the info_changed method and set up beacons properly
+                 * there.
+                 */
+                ath9k_set_beaconing_status(sc, false);
+                error = ath_beacon_alloc(sc, vif);
+                if (!error)
+                        ath_beacon_config(sc, vif);
+                ath9k_set_beaconing_status(sc, true);
+        }
+}
 
+
+static int ath9k_add_interface(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret = 0;
+
+        ath9k_ps_wakeup(sc);
+        mutex_lock(&sc->mutex);
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_STATION:
+        case NL80211_IFTYPE_WDS:
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_MESH_POINT:
+                break;
+        default:
+                ath_err(common, "Interface type %d not yet supported\n",
+                        vif->type);
+                ret = -EOPNOTSUPP;
+                goto out;
+        }
+
+        if (ath9k_uses_beacons(vif->type)) {
+                if (sc->nbcnvifs >= ATH_BCBUF) {
+                        ath_err(common, "Not enough beacon buffers when adding"
+                                " new interface of type: %i\n",
+                                vif->type);
+                        ret = -ENOBUFS;
+                        goto out;
+                }
+        }
+
+        if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
+            ((vif->type == NL80211_IFTYPE_ADHOC) &&
+             sc->nvifs > 0)) {
+                ath_err(common, "Cannot create ADHOC interface when other"
+                        " interfaces already exist.\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attach a VIF of type: %d\n", vif->type);
+
+        sc->nvifs++;
+
+        ath9k_do_vif_add_setup(hw, vif);
 out:
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
         return ret;
 }
 
-static void ath9k_remove_interface(struct ieee80211_hw *hw,
-                                   struct ieee80211_vif *vif)
+static int ath9k_change_interface(struct ieee80211_hw *hw,
+                                  struct ieee80211_vif *vif,
+                                  enum nl80211_iftype new_type,
+                                  bool p2p)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_vif *avp = (void *)vif->drv_priv;
-        int i;
-
-        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
+        int ret = 0;
 
+        ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
 
-        /* Stop ANI */
-        sc->sc_flags &= ~SC_OP_ANI_RUN;
-        del_timer_sync(&common->ani.timer);
-
-        /* Reclaim beacon resources */
-        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
-                ath9k_ps_wakeup(sc);
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                ath9k_ps_restore(sc);
+        /* See if new interface type is valid. */
+        if ((new_type == NL80211_IFTYPE_ADHOC) &&
+            (sc->nvifs > 1)) {
+                ath_err(common, "When using ADHOC, it must be the only"
+                        " interface.\n");
+                ret = -EINVAL;
+                goto out;
         }
 
-        ath_beacon_return(sc, avp);
-        sc->sc_flags &= ~SC_OP_BEACONS;
-
-        for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
-                if (sc->beacon.bslot[i] == vif) {
-                        printk(KERN_DEBUG "%s: vif had allocated beacon "
-                               "slot\n", __func__);
-                        sc->beacon.bslot[i] = NULL;
-                        sc->beacon.bslot_aphy[i] = NULL;
+        if (ath9k_uses_beacons(new_type) &&
+            !ath9k_uses_beacons(vif->type)) {
+                if (sc->nbcnvifs >= ATH_BCBUF) {
+                        ath_err(common, "No beacon slot available\n");
+                        ret = -ENOBUFS;
+                        goto out;
                 }
         }
 
+        /* Clean up old vif stuff */
+        if (ath9k_uses_beacons(vif->type))
+                ath9k_reclaim_beacon(sc, vif);
+
+        /* Add new settings */
+        vif->type = new_type;
+        vif->p2p = p2p;
+
+        ath9k_do_vif_add_setup(hw, vif);
+out:
+        ath9k_ps_restore(sc);
+        mutex_unlock(&sc->mutex);
+        return ret;
+}
+
+static void ath9k_remove_interface(struct ieee80211_hw *hw,
+                                   struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+
+        ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
+
+        ath9k_ps_wakeup(sc);
+        mutex_lock(&sc->mutex);
+
         sc->nvifs--;
 
+        /* Reclaim beacon resources */
+        if (ath9k_uses_beacons(vif->type))
+                ath9k_reclaim_beacon(sc, vif);
+
+        ath9k_calculate_summary_state(hw, NULL);
+
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 }
 
-void ath9k_enable_ps(struct ath_softc *sc)
+static void ath9k_enable_ps(struct ath_softc *sc)
 {
         struct ath_hw *ah = sc->sc_ah;
 
@@ -1505,14 +1586,33 @@ void ath9k_enable_ps(struct ath_softc *sc)
         }
 }
 
+static void ath9k_disable_ps(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+
+        sc->ps_enabled = false;
+        ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
+        if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
+                ath9k_hw_setrxabort(ah, 0);
+                sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
+                                  PS_WAIT_FOR_CAB |
+                                  PS_WAIT_FOR_PSPOLL_DATA |
+                                  PS_WAIT_FOR_TX_ACK);
+                if (ah->imask & ATH9K_INT_TIM_TIMER) {
+                        ah->imask &= ~ATH9K_INT_TIM_TIMER;
+                        ath9k_hw_set_interrupts(ah, ah->imask);
+                }
+        }
+
+}
+
 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ieee80211_conf *conf = &hw->conf;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
-        bool disable_radio;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_conf *conf = &hw->conf;
+        bool disable_radio = false;
 
         mutex_lock(&sc->mutex);
 
@@ -1523,29 +1623,13 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
          * the end.
          */
         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
-                bool enable_radio;
-                bool all_wiphys_idle;
-                bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
-
-                spin_lock_bh(&sc->wiphy_lock);
-                all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
-                ath9k_set_wiphy_idle(aphy, idle);
-
-                enable_radio = (!idle && all_wiphys_idle);
-
-                /*
-                 * After we unlock here its possible another wiphy
-                 * can be re-renabled so to account for that we will
-                 * only disable the radio toward the end of this routine
-                 * if by then all wiphys are still idle.
-                 */
-                spin_unlock_bh(&sc->wiphy_lock);
-
-                if (enable_radio) {
-                        sc->ps_idle = false;
+                sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
+                if (!sc->ps_idle) {
                         ath_radio_enable(sc, hw);
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "not-idle: enabling radio\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "not-idle: enabling radio\n");
+                } else {
+                        disable_radio = true;
                 }
         }
 
@@ -1556,96 +1640,100 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
          */
         if (changed & IEEE80211_CONF_CHANGE_PS) {
-                if (conf->flags & IEEE80211_CONF_PS) {
-                        sc->ps_flags |= PS_ENABLED;
-                        /*
-                         * At this point we know hardware has received an ACK
-                         * of a previously sent null data frame.
-                         */
-                        if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
-                                sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
-                                ath9k_enable_ps(sc);
-                        }
-                } else {
-                        sc->ps_enabled = false;
-                        sc->ps_flags &= ~(PS_ENABLED |
-                                          PS_NULLFUNC_COMPLETED);
-                        ath9k_setpower(sc, ATH9K_PM_AWAKE);
-                        if (!(ah->caps.hw_caps &
-                              ATH9K_HW_CAP_AUTOSLEEP)) {
-                                ath9k_hw_setrxabort(sc->sc_ah, 0);
-                                sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
-                                                  PS_WAIT_FOR_CAB |
-                                                  PS_WAIT_FOR_PSPOLL_DATA |
-                                                  PS_WAIT_FOR_TX_ACK);
-                                if (ah->imask & ATH9K_INT_TIM_TIMER) {
-                                        ah->imask &= ~ATH9K_INT_TIM_TIMER;
-                                        ath9k_hw_set_interrupts(sc->sc_ah,
-                                                        ah->imask);
-                                }
-                        }
-                }
+                unsigned long flags;
+                spin_lock_irqsave(&sc->sc_pm_lock, flags);
+                if (conf->flags & IEEE80211_CONF_PS)
+                        ath9k_enable_ps(sc);
+                else
+                        ath9k_disable_ps(sc);
+                spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
         }
 
         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
                 if (conf->flags & IEEE80211_CONF_MONITOR) {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "HW opmode set to Monitor mode\n");
-                        sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor mode is enabled\n");
+                        sc->sc_ah->is_monitoring = true;
+                } else {
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor mode is disabled\n");
+                        sc->sc_ah->is_monitoring = false;
                 }
         }
 
         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
                 struct ieee80211_channel *curchan = hw->conf.channel;
                 int pos = curchan->hw_value;
+                int old_pos = -1;
+                unsigned long flags;
+
+                if (ah->curchan)
+                        old_pos = ah->curchan - &ah->channels[0];
 
-                aphy->chan_idx = pos;
-                aphy->chan_is_ht = conf_is_ht(conf);
                 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
                         sc->sc_flags |= SC_OP_OFFCHANNEL;
                 else
                         sc->sc_flags &= ~SC_OP_OFFCHANNEL;
 
-                if (aphy->state == ATH_WIPHY_SCAN ||
-                    aphy->state == ATH_WIPHY_ACTIVE)
-                        ath9k_wiphy_pause_all_forced(sc, aphy);
-                else {
-                        /*
-                         * Do not change operational channel based on a paused
-                         * wiphy changes.
-                         */
-                        goto skip_chan_change;
-                }
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Set channel: %d MHz type: %d\n",
+                        curchan->center_freq, conf->channel_type);
 
-                ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
-                          curchan->center_freq);
+                ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
+                                          curchan, conf->channel_type);
 
-                /* XXX: remove me eventualy */
-                ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
+                /* update survey stats for the old channel before switching */
+                spin_lock_irqsave(&common->cc_lock, flags);
+                ath_update_survey_stats(sc);
+                spin_unlock_irqrestore(&common->cc_lock, flags);
 
-                ath_update_chainmask(sc, conf_is_ht(conf));
+                /*
+                 * If the operating channel changes, change the survey in-use flags
+                 * along with it.
+                 * Reset the survey data for the new channel, unless we're switching
+                 * back to the operating channel from an off-channel operation.
+                 */
+                if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
+                    sc->cur_survey != &sc->survey[pos]) {
+
+                        if (sc->cur_survey)
+                                sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
+
+                        sc->cur_survey = &sc->survey[pos];
+
+                        memset(sc->cur_survey, 0, sizeof(struct survey_info));
+                        sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
+                } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
+                        memset(&sc->survey[pos], 0, sizeof(struct survey_info));
+                }
 
                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to set channel\n");
+                        ath_err(common, "Unable to set channel\n");
                         mutex_unlock(&sc->mutex);
                         return -EINVAL;
                 }
+
+                /*
+                 * The most recent snapshot of channel->noisefloor for the old
+                 * channel is only available after the hardware reset. Copy it to
+                 * the survey stats now.
+                 */
+                if (old_pos >= 0)
+                        ath_update_survey_nf(sc, old_pos);
         }
 
-skip_chan_change:
         if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Set power: %d\n", conf->power_level);
                 sc->config.txpowlimit = 2 * conf->power_level;
-                ath_update_txpow(sc);
+                ath9k_ps_wakeup(sc);
+                ath9k_cmn_update_txpow(ah, sc->curtxpow,
+                                       sc->config.txpowlimit, &sc->curtxpow);
+                ath9k_ps_restore(sc);
         }
 
-        spin_lock_bh(&sc->wiphy_lock);
-        disable_radio = ath9k_all_wiphys_idle(sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-
         if (disable_radio) {
-                ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
-                sc->ps_idle = true;
+                ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
                 ath_radio_disable(sc, hw);
         }
 
@@ -1661,6 +1749,7 @@ skip_chan_change:
         FIF_PSPOLL |                            \
         FIF_OTHER_BSS |                         \
         FIF_BCN_PRBRESP_PROMISC |               \
+        FIF_PROBE_REQ |                         \
         FIF_FCSFAIL)
 
 /* FIXME: sc->sc_full_reset ? */
@@ -1669,8 +1758,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
                                    unsigned int *total_flags,
                                    u64 multicast)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         u32 rfilt;
 
         changed_flags &= SUPPORTED_FILTERS;
@@ -1682,46 +1770,92 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
         ath9k_ps_restore(sc);
 
-        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                  "Set HW RX filter: 0x%x\n", rfilt);
+        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                "Set HW RX filter: 0x%x\n", rfilt);
 }
 
 static int ath9k_sta_add(struct ieee80211_hw *hw,
                          struct ieee80211_vif *vif,
                          struct ieee80211_sta *sta)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_node *an = (struct ath_node *) sta->drv_priv;
+        struct ieee80211_key_conf ps_key = { };
 
         ath_node_attach(sc, sta);
 
+        if (vif->type != NL80211_IFTYPE_AP &&
+            vif->type != NL80211_IFTYPE_AP_VLAN)
+                return 0;
+
+        an->ps_key = ath_key_config(common, vif, sta, &ps_key);
+
         return 0;
 }
 
+static void ath9k_del_ps_key(struct ath_softc *sc,
+                             struct ieee80211_vif *vif,
+                             struct ieee80211_sta *sta)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_node *an = (struct ath_node *) sta->drv_priv;
+        struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
+
+        if (!an->ps_key)
+            return;
+
+        ath_key_delete(common, &ps_key);
+}
+
 static int ath9k_sta_remove(struct ieee80211_hw *hw,
                             struct ieee80211_vif *vif,
                             struct ieee80211_sta *sta)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
+        ath9k_del_ps_key(sc, vif, sta);
         ath_node_detach(sc, sta);
 
         return 0;
 }
 
+static void ath9k_sta_notify(struct ieee80211_hw *hw,
+                         struct ieee80211_vif *vif,
+                         enum sta_notify_cmd cmd,
+                         struct ieee80211_sta *sta)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_node *an = (struct ath_node *) sta->drv_priv;
+
+        switch (cmd) {
+        case STA_NOTIFY_SLEEP:
+                an->sleeping = true;
+                if (ath_tx_aggr_sleep(sc, an))
+                        ieee80211_sta_set_tim(sta);
+                break;
+        case STA_NOTIFY_AWAKE:
+                an->sleeping = false;
+                ath_tx_aggr_wakeup(sc, an);
+                break;
+        }
+}
+
 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
                          const struct ieee80211_tx_queue_params *params)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_txq *txq;
         struct ath9k_tx_queue_info qi;
-        int ret = 0, qnum;
+        int ret = 0;
 
         if (queue >= WME_NUM_AC)
                 return 0;
 
+        txq = sc->tx.txq_map[queue];
+
+        ath9k_ps_wakeup(sc);
         mutex_lock(&sc->mutex);
 
         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -1730,23 +1864,22 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
         qi.tqi_cwmin = params->cw_min;
         qi.tqi_cwmax = params->cw_max;
         qi.tqi_burstTime = params->txop;
-        qnum = ath_get_hal_qnum(queue, sc);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Configure tx [queue/halq] [%d/%d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, qnum, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                queue, txq->axq_qnum, params->aifs, params->cw_min,
+                params->cw_max, params->txop);
 
-        ret = ath_txq_update(sc, qnum, &qi);
+        ret = ath_txq_update(sc, txq->axq_qnum, &qi);
         if (ret)
-                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+                ath_err(common, "TXQ Update failed\n");
 
         if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
-                if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
+                if (queue == WME_AC_BE && !ret)
                         ath_beaconq_config(sc);
 
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 
         return ret;
 }
@@ -1757,34 +1890,51 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
                          struct ieee80211_sta *sta,
                          struct ieee80211_key_conf *key)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int ret = 0;
 
-        if (modparam_nohwcrypt)
+        if (ath9k_modparam_nohwcrypt)
                 return -ENOSPC;
 
+        if (vif->type == NL80211_IFTYPE_ADHOC &&
+            (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
+             key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
+            !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
+                /*
+                 * For now, disable hw crypto for the RSN IBSS group keys. This
+                 * could be optimized in the future to use a modified key cache
+                 * design to support per-STA RX GTK, but until that gets
+                 * implemented, use of software crypto for group addressed
+                 * frames is a acceptable to allow RSN IBSS to be used.
+                 */
+                return -EOPNOTSUPP;
+        }
+
         mutex_lock(&sc->mutex);
         ath9k_ps_wakeup(sc);
-        ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
 
         switch (cmd) {
         case SET_KEY:
-                ret = ath9k_cmn_key_config(common, vif, sta, key);
+                if (sta)
+                        ath9k_del_ps_key(sc, vif, sta);
+
+                ret = ath_key_config(common, vif, sta, key);
                 if (ret >= 0) {
                         key->hw_key_idx = ret;
                         /* push IV and Michael MIC generation to stack */
                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
-                        if (key->alg == ALG_TKIP)
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
-                        if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
+                        if (sc->sc_ah->sw_mgmt_crypto &&
+                            key->cipher == WLAN_CIPHER_SUITE_CCMP)
                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
                         ret = 0;
                 }
                 break;
         case DISABLE_KEY:
-                ath9k_cmn_key_delete(common, key);
+                ath_key_delete(common, key);
                 break;
         default:
                 ret = -EINVAL;
@@ -1795,51 +1945,123 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
 
         return ret;
 }
+static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
+{
+        struct ath_softc *sc = data;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath_vif *avp = (void *)vif->drv_priv;
+
+        switch (sc->sc_ah->opmode) {
+        case NL80211_IFTYPE_ADHOC:
+                /* There can be only one vif available */
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                common->curaid = bss_conf->aid;
+                ath9k_hw_write_associd(sc->sc_ah);
+                /* configure beacon */
+                if (bss_conf->enable_beacon)
+                        ath_beacon_config(sc, vif);
+                break;
+        case NL80211_IFTYPE_STATION:
+                /*
+                 * Skip iteration if primary station vif's bss info
+                 * was not changed
+                 */
+                if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
+                        break;
+
+                if (bss_conf->assoc) {
+                        sc->sc_flags |= SC_OP_PRIM_STA_VIF;
+                        avp->primary_sta_vif = true;
+                        memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                        common->curaid = bss_conf->aid;
+                        ath9k_hw_write_associd(sc->sc_ah);
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Bss Info ASSOC %d, bssid: %pM\n",
+                                bss_conf->aid, common->curbssid);
+                        ath_beacon_config(sc, vif);
+                        /*
+                         * Request a re-configuration of Beacon related timers
+                         * on the receipt of the first Beacon frame (i.e.,
+                         * after time sync with the AP).
+                         */
+                        sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
+                        /* Reset rssi stats */
+                        sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
+                        sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
+
+                        sc->sc_flags |= SC_OP_ANI_RUN;
+                        ath_start_ani(common);
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct ath_vif *avp = (void *)vif->drv_priv;
+
+        /* Reconfigure bss info */
+        if (avp->primary_sta_vif && !bss_conf->assoc) {
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Bss Info DISASSOC %d, bssid %pM\n",
+                        common->curaid, common->curbssid);
+                sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
+                avp->primary_sta_vif = false;
+                memset(common->curbssid, 0, ETH_ALEN);
+                common->curaid = 0;
+        }
+
+        ieee80211_iterate_active_interfaces_atomic(
+                        sc->hw, ath9k_bss_iter, sc);
+
+        /*
+         * None of station vifs are associated.
+         * Clear bssid & aid
+         */
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+            !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
+                ath9k_hw_write_associd(sc->sc_ah);
+                /* Stop ANI */
+                sc->sc_flags &= ~SC_OP_ANI_RUN;
+                del_timer_sync(&common->ani.timer);
+        }
+}
 
 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
                                    struct ieee80211_vif *vif,
                                    struct ieee80211_bss_conf *bss_conf,
                                    u32 changed)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_vif *avp = (void *)vif->drv_priv;
         int slottime;
         int error;
 
+        ath9k_ps_wakeup(sc);
         mutex_lock(&sc->mutex);
 
         if (changed & BSS_CHANGED_BSSID) {
-                /* Set BSSID */
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
-                common->curaid = 0;
-                ath9k_hw_write_associd(ah);
-
-                /* Set aggregation protection mode parameters */
-                sc->config.ath_aggr_prot = 0;
+                ath9k_config_bss(sc, vif);
 
-                /* Only legacy IBSS for now */
-                if (vif->type == NL80211_IFTYPE_ADHOC)
-                        ath_update_chainmask(sc, 0);
-
-                ath_print(common, ATH_DBG_CONFIG,
-                          "BSSID: %pM aid: 0x%x\n",
-                          common->curbssid, common->curaid);
-
-                /* need to reconfigure the beacon */
-                sc->sc_flags &= ~SC_OP_BEACONS ;
+                ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
+                        common->curbssid, common->curaid);
         }
 
         /* Enable transmission of beacons (AP, IBSS, MESH) */
         if ((changed & BSS_CHANGED_BEACON) ||
             ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                error = ath_beacon_alloc(aphy, vif);
+                ath9k_set_beaconing_status(sc, false);
+                error = ath_beacon_alloc(sc, vif);
                 if (!error)
                         ath_beacon_config(sc, vif);
+                ath9k_set_beaconing_status(sc, true);
         }
 
         if (changed & BSS_CHANGED_ERP_SLOT) {
@@ -1862,29 +2084,32 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         /* Disable transmission of beacons */
-        if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
+        if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
+            !bss_conf->enable_beacon) {
+                ath9k_set_beaconing_status(sc, false);
+                avp->is_bslot_active = false;
+                ath9k_set_beaconing_status(sc, true);
+        }
 
         if (changed & BSS_CHANGED_BEACON_INT) {
-                sc->beacon_interval = bss_conf->beacon_int;
                 /*
                  * In case of AP mode, the HW TSF has to be reset
                  * when the beacon interval changes.
                  */
                 if (vif->type == NL80211_IFTYPE_AP) {
                         sc->sc_flags |= SC_OP_TSF_RESET;
-                        ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                        error = ath_beacon_alloc(aphy, vif);
+                        ath9k_set_beaconing_status(sc, false);
+                        error = ath_beacon_alloc(sc, vif);
                         if (!error)
                                 ath_beacon_config(sc, vif);
-                } else {
+                        ath9k_set_beaconing_status(sc, true);
+                } else
                         ath_beacon_config(sc, vif);
-                }
         }
 
         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
-                          bss_conf->use_short_preamble);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
+                        bss_conf->use_short_preamble);
                 if (bss_conf->use_short_preamble)
                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
                 else
@@ -1892,8 +2117,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
-                          bss_conf->use_cts_prot);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
+                        bss_conf->use_cts_prot);
                 if (bss_conf->use_cts_prot &&
                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -1901,23 +2126,19 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
         }
 
-        if (changed & BSS_CHANGED_ASSOC) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
-                        bss_conf->assoc);
-                ath9k_bss_assoc_info(sc, vif, bss_conf);
-        }
-
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 }
 
 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
 {
+        struct ath_softc *sc = hw->priv;
         u64 tsf;
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
 
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
         tsf = ath9k_hw_gettsf64(sc->sc_ah);
+        ath9k_ps_restore(sc);
         mutex_unlock(&sc->mutex);
 
         return tsf;
@@ -1925,18 +2146,18 @@ static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
 
 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
         ath9k_hw_settsf64(sc->sc_ah, tsf);
+        ath9k_ps_restore(sc);
         mutex_unlock(&sc->mutex);
 }
 
 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
         mutex_lock(&sc->mutex);
 
@@ -1951,10 +2172,9 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                               struct ieee80211_vif *vif,
                               enum ieee80211_ampdu_mlme_action action,
                               struct ieee80211_sta *sta,
-                              u16 tid, u16 *ssn)
+                              u16 tid, u16 *ssn, u8 buf_size)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         int ret = 0;
 
         local_bh_disable();
@@ -1967,9 +2187,13 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
         case IEEE80211_AMPDU_RX_STOP:
                 break;
         case IEEE80211_AMPDU_TX_START:
+                if (!(sc->sc_flags & SC_OP_TXAGGR))
+                        return -EOPNOTSUPP;
+
                 ath9k_ps_wakeup(sc);
-                ath_tx_aggr_start(sc, sta, tid, ssn);
-                ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+                ret = ath_tx_aggr_start(sc, sta, tid, ssn);
+                if (!ret)
+                        ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
                 ath9k_ps_restore(sc);
                 break;
         case IEEE80211_AMPDU_TX_STOP:
@@ -1984,8 +2208,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                 ath9k_ps_restore(sc);
                 break;
         default:
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unknown AMPDU action\n");
+                ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
         }
 
         local_bh_enable();
@@ -1996,71 +2219,158 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
                              struct survey_info *survey)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ieee80211_conf *conf = &hw->conf;
+        struct ath_softc *sc = hw->priv;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *chan;
+        unsigned long flags;
+        int pos;
 
-         if (idx != 0)
+        spin_lock_irqsave(&common->cc_lock, flags);
+        if (idx == 0)
+                ath_update_survey_stats(sc);
+
+        sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
+        if (sband && idx >= sband->n_channels) {
+                idx -= sband->n_channels;
+                sband = NULL;
+        }
+
+        if (!sband)
+                sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
+
+        if (!sband || idx >= sband->n_channels) {
+                spin_unlock_irqrestore(&common->cc_lock, flags);
                 return -ENOENT;
+        }
 
-        survey->channel = conf->channel;
-        survey->filled = SURVEY_INFO_NOISE_DBM;
-        survey->noise = common->ani.noise_floor;
+        chan = &sband->channels[idx];
+        pos = chan->hw_value;
+        memcpy(survey, &sc->survey[pos], sizeof(*survey));
+        survey->channel = chan;
+        spin_unlock_irqrestore(&common->cc_lock, flags);
 
         return 0;
 }
 
-static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
+static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
 
         mutex_lock(&sc->mutex);
-        if (ath9k_wiphy_scanning(sc)) {
-                /*
-                 * There is a race here in mac80211 but fixing it requires
-                 * we revisit how we handle the scan complete callback.
-                 * After mac80211 fixes we will not have configured hardware
-                 * to the home channel nor would we have configured the RX
-                 * filter yet.
-                 */
+        ah->coverage_class = coverage_class;
+        ath9k_hw_init_global_settings(ah);
+        mutex_unlock(&sc->mutex);
+}
+
+static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
+{
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int timeout = 200; /* ms */
+        int i, j;
+        bool drain_txq;
+
+        mutex_lock(&sc->mutex);
+        cancel_delayed_work_sync(&sc->tx_complete_work);
+
+        if (sc->sc_flags & SC_OP_INVALID) {
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&sc->mutex);
                 return;
         }
 
-        aphy->state = ATH_WIPHY_SCAN;
-        ath9k_wiphy_pause_all_forced(sc, aphy);
-        sc->sc_flags |= SC_OP_SCANNING;
+        if (drop)
+                timeout = 1;
+
+        for (j = 0; j < timeout; j++) {
+                bool npend = false;
+
+                if (j)
+                        usleep_range(1000, 2000);
+
+                for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+                        if (!ATH_TXQ_SETUP(sc, i))
+                                continue;
+
+                        npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
+
+                        if (npend)
+                                break;
+                }
+
+                if (!npend)
+                    goto out;
+        }
+
+        ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+        drain_txq = ath_drain_all_txq(sc, false);
+        spin_unlock_bh(&sc->sc_pcu_lock);
+        if (!drain_txq)
+                ath_reset(sc, false);
+        ath9k_ps_restore(sc);
+        ieee80211_wake_queues(hw);
+
+out:
+        ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
         mutex_unlock(&sc->mutex);
 }
 
-/*
- * XXX: this requires a revisit after the driver
- * scan_complete gets moved to another place/removed in mac80211.
- */
-static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
+static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
+        int i;
 
-        mutex_lock(&sc->mutex);
-        aphy->state = ATH_WIPHY_ACTIVE;
-        sc->sc_flags &= ~SC_OP_SCANNING;
-        mutex_unlock(&sc->mutex);
+        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+                if (!ATH_TXQ_SETUP(sc, i))
+                        continue;
+
+                if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
+                        return true;
+        }
+        return false;
 }
 
-static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
+int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
+        struct ieee80211_vif *vif;
+        struct ath_vif *avp;
+        struct ath_buf *bf;
+        struct ath_tx_status ts;
+        int status;
+
+        vif = sc->beacon.bslot[0];
+        if (!vif)
+                return 0;
 
-        mutex_lock(&sc->mutex);
-        ah->coverage_class = coverage_class;
-        ath9k_hw_init_global_settings(ah);
-        mutex_unlock(&sc->mutex);
+        avp = (void *)vif->drv_priv;
+        if (!avp->is_bslot_active)
+                return 0;
+
+        if (!sc->beacon.tx_processed) {
+                tasklet_disable(&sc->bcon_tasklet);
+
+                bf = avp->av_bcbuf;
+                if (!bf || !bf->bf_mpdu)
+                        goto skip;
+
+                status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
+                if (status == -EINPROGRESS)
+                        goto skip;
+
+                sc->beacon.tx_processed = true;
+                sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
+
+skip:
+                tasklet_enable(&sc->bcon_tasklet);
+        }
+
+        return sc->beacon.tx_last;
 }
 
 struct ieee80211_ops ath9k_ops = {
@@ -2068,11 +2378,13 @@ struct ieee80211_ops ath9k_ops = {
         .start              = ath9k_start,
         .stop               = ath9k_stop,
         .add_interface      = ath9k_add_interface,
+        .change_interface   = ath9k_change_interface,
         .remove_interface   = ath9k_remove_interface,
         .config             = ath9k_config,
         .configure_filter   = ath9k_configure_filter,
         .sta_add            = ath9k_sta_add,
         .sta_remove         = ath9k_sta_remove,
+        .sta_notify         = ath9k_sta_notify,
         .conf_tx            = ath9k_conf_tx,
         .bss_info_changed   = ath9k_bss_info_changed,
         .set_key            = ath9k_set_key,
@@ -2081,8 +2393,9 @@ struct ieee80211_ops ath9k_ops = {
         .reset_tsf          = ath9k_reset_tsf,
         .ampdu_action       = ath9k_ampdu_action,
         .get_survey         = ath9k_get_survey,
-        .sw_scan_start      = ath9k_sw_scan_start,
-        .sw_scan_complete   = ath9k_sw_scan_complete,
         .rfkill_poll        = ath9k_rfkill_poll_state,
         .set_coverage_class = ath9k_set_coverage_class,
+        .flush              = ath9k_flush,
+        .tx_frames_pending  = ath9k_tx_frames_pending,
+        .tx_last_beacon = ath9k_tx_last_beacon,
 };
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index b5b651413e77..3bad0b2cf9a3 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,6 +16,7 @@
 
 #include <linux/nl80211.h>
 #include <linux/pci.h>
+#include <linux/ath9k_platform.h>
 #include "ath9k.h"
 
 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
@@ -29,6 +30,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
+        { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
         { 0 }
 };
 
@@ -42,7 +44,7 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
         *csz = (int)u8tmp;
 
         /*
-         * This check was put in to avoid "unplesant" consequences if
+         * This check was put in to avoid "unpleasant" consequences if
          * the bootrom has not fully initialized all PCI devices.
          * Sometimes the cache line size register is not set
          */
@@ -53,21 +55,35 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
 
 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 {
-        struct ath_hw *ah = (struct ath_hw *) common->ah;
-
-        common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
-
-        if (!ath9k_hw_wait(ah,
-                           AR_EEPROM_STATUS_DATA,
-                           AR_EEPROM_STATUS_DATA_BUSY |
-                           AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
-                           AH_WAIT_TIMEOUT)) {
-                return false;
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        struct ath9k_platform_data *pdata = sc->dev->platform_data;
+
+        if (pdata) {
+                if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
+                        ath_err(common,
+                                "%s: eeprom read failed, offset %08x is out of range\n",
+                                __func__, off);
+                }
+
+                *data = pdata->eeprom_data[off];
+        } else {
+                struct ath_hw *ah = (struct ath_hw *) common->ah;
+
+                common->ops->read(ah, AR5416_EEPROM_OFFSET +
+                                      (off << AR5416_EEPROM_S));
+
+                if (!ath9k_hw_wait(ah,
+                                   AR_EEPROM_STATUS_DATA,
+                                   AR_EEPROM_STATUS_DATA_BUSY |
+                                   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
+                                   AH_WAIT_TIMEOUT)) {
+                        return false;
+                }
+
+                *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
+                           AR_EEPROM_STATUS_DATA_VAL);
         }
 
-        *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
-                   AR_EEPROM_STATUS_DATA_VAL);
-
         return true;
 }
 
@@ -80,7 +96,7 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
         struct pci_dev *pdev = to_pci_dev(sc->dev);
         u8 aspm;
 
-        if (!pdev->is_pcie)
+        if (!pci_is_pcie(pdev))
                 return;
 
         pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
@@ -88,17 +104,28 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
         pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
 }
 
+static void ath_pci_extn_synch_enable(struct ath_common *common)
+{
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        struct pci_dev *pdev = to_pci_dev(sc->dev);
+        u8 lnkctl;
+
+        pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
+        lnkctl |= PCI_EXP_LNKCTL_ES;
+        pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
+}
+
 static const struct ath_bus_ops ath_pci_bus_ops = {
         .ath_bus_type = ATH_PCI,
         .read_cachesize = ath_pci_read_cachesize,
         .eeprom_read = ath_pci_eeprom_read,
         .bt_coex_prep = ath_pci_bt_coex_prep,
+        .extn_synch_en = ath_pci_extn_synch_enable,
 };
 
 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
         void __iomem *mem;
-        struct ath_wiphy *aphy;
         struct ath_softc *sc;
         struct ieee80211_hw *hw;
         u8 csz;
@@ -170,8 +197,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
                 goto err_iomap;
         }
 
-        hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
-                                sizeof(struct ath_softc), &ath9k_ops);
+        hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
         if (!hw) {
                 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
                 ret = -ENOMEM;
@@ -181,11 +207,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         SET_IEEE80211_DEV(hw, &pdev->dev);
         pci_set_drvdata(pdev, hw);
 
-        aphy = hw->priv;
-        sc = (struct ath_softc *) (aphy + 1);
-        aphy->sc = sc;
-        aphy->hw = hw;
-        sc->pri_wiphy = aphy;
+        sc = hw->priv;
         sc->hw = hw;
         sc->dev = &pdev->dev;
         sc->mem = mem;
@@ -232,10 +254,11 @@ err_dma:
 static void ath_pci_remove(struct pci_dev *pdev)
 {
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         void __iomem *mem = sc->mem;
 
+        if (!is_ath9k_unloaded)
+                sc->sc_ah->ah_flags |= AH_UNPLUGGED;
         ath9k_deinit_device(sc);
         free_irq(sc->irq, sc);
         ieee80211_free_hw(sc->hw);
@@ -247,34 +270,29 @@ static void ath_pci_remove(struct pci_dev *pdev)
 
 #ifdef CONFIG_PM
 
-static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+static int ath_pci_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
 
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
-        pci_save_state(pdev);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, PCI_D3hot);
+        /* The device has to be moved to FULLSLEEP forcibly.
+         * Otherwise the chip never moved to full sleep,
+         * when no interface is up.
+         */
+        ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 
         return 0;
 }
 
-static int ath_pci_resume(struct pci_dev *pdev)
+static int ath_pci_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
+        struct ath_softc *sc = hw->priv;
         u32 val;
-        int err;
-
-        pci_restore_state(pdev);
-
-        err = pci_enable_device(pdev);
-        if (err)
-                return err;
 
         /*
          * Suspend/Resume resets the PCI configuration space, so we have to
@@ -290,10 +308,37 @@ static int ath_pci_resume(struct pci_dev *pdev)
                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
+          /*
+           * Reset key cache to sane defaults (all entries cleared) instead of
+           * semi-random values after suspend/resume.
+           */
+        ath9k_ps_wakeup(sc);
+        ath9k_init_crypto(sc);
+        ath9k_ps_restore(sc);
+
+        sc->ps_idle = true;
+        ath_radio_disable(sc, hw);
+
         return 0;
 }
 
-#endif /* CONFIG_PM */
+static const struct dev_pm_ops ath9k_pm_ops = {
+        .suspend = ath_pci_suspend,
+        .resume = ath_pci_resume,
+        .freeze = ath_pci_suspend,
+        .thaw = ath_pci_resume,
+        .poweroff = ath_pci_suspend,
+        .restore = ath_pci_resume,
+};
+
+#define ATH9K_PM_OPS    (&ath9k_pm_ops)
+
+#else /* !CONFIG_PM */
+
+#define ATH9K_PM_OPS    NULL
+
+#endif /* !CONFIG_PM */
+
 
 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 
@@ -302,10 +347,7 @@ static struct pci_driver ath_pci_driver = {
         .id_table   = ath_pci_id_table,
         .probe      = ath_pci_probe,
         .remove     = ath_pci_remove,
-#ifdef CONFIG_PM
-        .suspend    = ath_pci_suspend,
-        .resume     = ath_pci_resume,
-#endif /* CONFIG_PM */
+        .driver.pm  = ATH9K_PM_OPS,
 };
 
 int ath_pci_init(void)
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index e724c2c1ae2a..8b380305b0fc 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -37,29 +37,15 @@
 #define AR_PHY_CLC_Q0        0x0000ffd0
 #define AR_PHY_CLC_Q0_S      5
 
-#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
-                int r;                                                  \
-                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
-                        REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
-                        DO_DELAY(regWr);                                \
-                }                                                       \
-        } while (0)
-
-#define ATH9K_IS_MIC_ENABLED(ah)                                        \
-        ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
-
 #define ANTSWAP_AB 0x0001
 #define REDUCE_CHAIN_0 0x00000050
 #define REDUCE_CHAIN_1 0x00000051
 #define AR_PHY_CHIP_ID 0x9818
 
-#define RF_BANK_SETUP(_bank, _iniarray, _col) do {                      \
-                int i;                                                  \
-                for (i = 0; i < (_iniarray)->ia_rows; i++)              \
-                        (_bank)[i] = INI_RA((_iniarray), i, _col);;     \
-        } while (0)
-
 #define AR_PHY_TIMING11_SPUR_FREQ_SD            0x3FF00000
 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S          20
 
+#define AR_PHY_PLL_CONTROL 0x16180
+#define AR_PHY_PLL_MODE 0x16184
+
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index e49be733d546..ba7f36ab0a74 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2004 Video54 Technologies, Inc.
- * Copyright (c) 2004-2009 Atheros Communications, Inc.
+ * Copyright (c) 2004-2011 Atheros Communications, Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -302,7 +302,7 @@ static const struct ath_rate_table ar5416_11ng_ratetable = {
                 [64] = {  RC_INVALID, WLAN_RC_PHY_HT_40_TS, 243000,
                         205100, 20, 20, 8, 64, 65, 65 }, /* 243 Mb */
                 [65] = {  RC_INVALID, WLAN_RC_PHY_HT_40_TS_HGI, 270000,
-                        224700, 20, 20, 8, 64, 65, 65 }, /* 170 Mb */
+                        224700, 20, 20, 8, 64, 65, 65 }, /* 270 Mb */
                 [66] = {  RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 324000,
                         263100, 21, 21, 8, 66, 67, 67 }, /* 324 Mb */
                 [67] = {  RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 360000,
@@ -378,39 +378,9 @@ static const struct ath_rate_table ar5416_11g_ratetable = {
         0,   /* Phy rates allowed initially */
 };
 
-static const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX] = {
-        [ATH9K_MODE_11A] = &ar5416_11a_ratetable,
-        [ATH9K_MODE_11G] = &ar5416_11g_ratetable,
-        [ATH9K_MODE_11NA_HT20] = &ar5416_11na_ratetable,
-        [ATH9K_MODE_11NG_HT20] = &ar5416_11ng_ratetable,
-        [ATH9K_MODE_11NA_HT40PLUS] = &ar5416_11na_ratetable,
-        [ATH9K_MODE_11NA_HT40MINUS] = &ar5416_11na_ratetable,
-        [ATH9K_MODE_11NG_HT40PLUS] = &ar5416_11ng_ratetable,
-        [ATH9K_MODE_11NG_HT40MINUS] = &ar5416_11ng_ratetable,
-};
-
 static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
                                 struct ieee80211_tx_rate *rate);
 
-static inline int8_t median(int8_t a, int8_t b, int8_t c)
-{
-        if (a >= b) {
-                if (b >= c)
-                        return b;
-                else if (a > c)
-                        return c;
-                else
-                        return a;
-        } else {
-                if (a >= c)
-                        return a;
-                else if (b >= c)
-                        return c;
-                else
-                        return b;
-        }
-}
-
 static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
                                    struct ath_rate_priv *ath_rc_priv)
 {
@@ -430,7 +400,7 @@ static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
         }
 }
 
-static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
+static void ath_rc_init_valid_rate_idx(struct ath_rate_priv *ath_rc_priv)
 {
         u8 i;
 
@@ -438,7 +408,7 @@ static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
                 ath_rc_priv->valid_rate_index[i] = 0;
 }
 
-static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv,
+static inline void ath_rc_set_valid_rate_idx(struct ath_rate_priv *ath_rc_priv,
                                            u8 index, int valid_tx_rate)
 {
         BUG_ON(index > ath_rc_priv->rate_table_size);
@@ -519,7 +489,7 @@ static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv,
 
                         ath_rc_priv->valid_phy_rateidx[phy][valid_rate_count] = i;
                         ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                        ath_rc_set_valid_txmask(ath_rc_priv, i, 1);
+                        ath_rc_set_valid_rate_idx(ath_rc_priv, i, 1);
                         hi = i;
                 }
         }
@@ -538,7 +508,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
         for (i = 0; i < rateset->rs_nrates; i++) {
                 for (j = 0; j < rate_table->rate_cnt; j++) {
                         u32 phy = rate_table->info[j].phy;
-                        u16 rate_flags = rate_table->info[i].rate_flags;
+                        u16 rate_flags = rate_table->info[j].rate_flags;
                         u8 rate = rateset->rs_rates[i];
                         u8 dot11rate = rate_table->info[j].dot11rate;
 
@@ -562,7 +532,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
                                 ath_rc_priv->valid_phy_rateidx[phy]
                                         [valid_rate_count] = j;
                                 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                                ath_rc_set_valid_txmask(ath_rc_priv, j, 1);
+                                ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
                                 hi = A_MAX(hi, j);
                         }
                 }
@@ -598,7 +568,7 @@ static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv,
                         ath_rc_priv->valid_phy_rateidx[phy]
                                 [ath_rc_priv->valid_phy_ratecnt[phy]] = j;
                         ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                        ath_rc_set_valid_txmask(ath_rc_priv, j, 1);
+                        ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
                         hi = A_MAX(hi, j);
                 }
         }
@@ -719,7 +689,8 @@ static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table,
 
         if (WLAN_RC_PHY_HT(rate_table->info[rix].phy)) {
                 rate->flags |= IEEE80211_TX_RC_MCS;
-                if (WLAN_RC_PHY_40(rate_table->info[rix].phy))
+                if (WLAN_RC_PHY_40(rate_table->info[rix].phy) &&
+                    conf_is_ht40(&txrc->hw->conf))
                         rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
                 if (WLAN_RC_PHY_SGI(rate_table->info[rix].phy))
                         rate->flags |= IEEE80211_TX_RC_SHORT_GI;
@@ -791,7 +762,7 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
          */
         try_per_rate = 4;
 
-        rate_table = sc->cur_rate_table;
+        rate_table = ath_rc_priv->rate_table;
         rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
 
         /*
@@ -822,7 +793,7 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
 
                 tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
         } else {
-                /* Set the choosen rate. No RTS for first series entry. */
+                /* Set the chosen rate. No RTS for first series entry. */
                 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
                                        try_per_rate, rix, 0);
         }
@@ -884,17 +855,16 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
         ath_rc_rate_set_rtscts(sc, rate_table, tx_info);
 }
 
-static bool ath_rc_update_per(struct ath_softc *sc,
+static void ath_rc_update_per(struct ath_softc *sc,
                               const struct ath_rate_table *rate_table,
                               struct ath_rate_priv *ath_rc_priv,
                                   struct ieee80211_tx_info *tx_info,
                               int tx_rate, int xretries, int retries,
                               u32 now_msec)
 {
-        bool state_change = false;
         int count, n_bad_frames;
         u8 last_per;
-        static u32 nretry_to_per_lookup[10] = {
+        static const u32 nretry_to_per_lookup[10] = {
                 100 * 0 / 1,
                 100 * 1 / 4,
                 100 * 1 / 2,
@@ -1022,8 +992,16 @@ static bool ath_rc_update_per(struct ath_softc *sc,
 
                 }
         }
+}
 
-        return state_change;
+static void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
+                                   int xretries, int retries, u8 per)
+{
+        struct ath_rc_stats *stats = &rc->rcstats[rix];
+
+        stats->xretries += xretries;
+        stats->retries += retries;
+        stats->per = per;
 }
 
 /* Update PER, RSSI and whatever else that the code thinks it is doing.
@@ -1037,8 +1015,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
         u32 now_msec = jiffies_to_msecs(jiffies);
         int rate;
         u8 last_per;
-        bool state_change = false;
-        const struct ath_rate_table *rate_table = sc->cur_rate_table;
+        const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
         int size = ath_rc_priv->rate_table_size;
 
         if ((tx_rate < 0) || (tx_rate > rate_table->rate_cnt))
@@ -1047,9 +1024,9 @@ static void ath_rc_update_ht(struct ath_softc *sc,
         last_per = ath_rc_priv->per[tx_rate];
 
         /* Update PER first */
-        state_change = ath_rc_update_per(sc, rate_table, ath_rc_priv,
-                                         tx_info, tx_rate, xretries,
-                                         retries, now_msec);
+        ath_rc_update_per(sc, rate_table, ath_rc_priv,
+                          tx_info, tx_rate, xretries,
+                          retries, now_msec);
 
         /*
          * If this rate looks bad (high PER) then stop using it for
@@ -1098,7 +1075,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
                 ath_rc_priv->per_down_time = now_msec;
         }
 
-        ath_debug_stat_retries(sc, tx_rate, xretries, retries,
+        ath_debug_stat_retries(ath_rc_priv, tx_rate, xretries, retries,
                                ath_rc_priv->per[tx_rate]);
 
 }
@@ -1107,13 +1084,12 @@ static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
                                 struct ieee80211_tx_rate *rate)
 {
         int rix = 0, i = 0;
-        int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
+        static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
 
         if (!(rate->flags & IEEE80211_TX_RC_MCS))
                 return rate->idx;
 
-        while (rate->idx > mcs_rix_off[i] &&
-              i < sizeof(mcs_rix_off)/sizeof(int)) {
+        while (i < ARRAY_SIZE(mcs_rix_off) && rate->idx > mcs_rix_off[i]) {
                 rix++; i++;
         }
 
@@ -1140,7 +1116,7 @@ static void ath_rc_tx_status(struct ath_softc *sc,
         u8 flags;
         u32 i = 0, rix;
 
-        rate_table = sc->cur_rate_table;
+        rate_table = ath_rc_priv->rate_table;
 
         /*
          * If the first rate is not the final index, there
@@ -1190,39 +1166,23 @@ static void ath_rc_tx_status(struct ath_softc *sc,
 static const
 struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
                                              enum ieee80211_band band,
-                                             bool is_ht,
-                                             bool is_cw_40)
+                                             bool is_ht)
 {
-        int mode = 0;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 
         switch(band) {
         case IEEE80211_BAND_2GHZ:
-                mode = ATH9K_MODE_11G;
                 if (is_ht)
-                        mode = ATH9K_MODE_11NG_HT20;
-                if (is_cw_40)
-                        mode = ATH9K_MODE_11NG_HT40PLUS;
-                break;
+                        return &ar5416_11ng_ratetable;
+                return &ar5416_11g_ratetable;
         case IEEE80211_BAND_5GHZ:
-                mode = ATH9K_MODE_11A;
                 if (is_ht)
-                        mode = ATH9K_MODE_11NA_HT20;
-                if (is_cw_40)
-                        mode = ATH9K_MODE_11NA_HT40PLUS;
-                break;
+                        return &ar5416_11na_ratetable;
+                return &ar5416_11a_ratetable;
         default:
-                ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
+                ath_dbg(common, ATH_DBG_CONFIG, "Invalid band\n");
                 return NULL;
         }
-
-        BUG_ON(mode >= ATH9K_MODE_MAX);
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Choosing rate table for mode: %d\n", mode);
-
-        sc->cur_rate_mode = mode;
-        return hw_rate_table[mode];
 }
 
 static void ath_rc_init(struct ath_softc *sc,
@@ -1246,7 +1206,7 @@ static void ath_rc_init(struct ath_softc *sc,
         }
 
         /* Determine the valid rates */
-        ath_rc_init_valid_txmask(ath_rc_priv);
+        ath_rc_init_valid_rate_idx(ath_rc_priv);
 
         for (i = 0; i < WLAN_RC_PHY_MAX; i++) {
                 for (j = 0; j < MAX_TX_RATE_PHY; j++)
@@ -1293,11 +1253,11 @@ static void ath_rc_init(struct ath_softc *sc,
         ath_rc_priv->max_valid_rate = k;
         ath_rc_sort_validrates(rate_table, ath_rc_priv);
         ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
-        sc->cur_rate_table = rate_table;
+        ath_rc_priv->rate_table = rate_table;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "RC Initialized with capabilities: 0x%x\n",
-                  ath_rc_priv->ht_cap);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "RC Initialized with capabilities: 0x%x\n",
+                ath_rc_priv->ht_cap);
 }
 
 static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1320,10 +1280,35 @@ static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
         return caps;
 }
 
+static bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an,
+                              u8 tidno)
+{
+        struct ath_atx_tid *txtid;
+
+        if (!(sc->sc_flags & SC_OP_TXAGGR))
+                return false;
+
+        txtid = ATH_AN_2_TID(an, tidno);
+
+        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
+                        return true;
+        return false;
+}
+
+
 /***********************************/
 /* mac80211 Rate Control callbacks */
 /***********************************/
 
+static void ath_debug_stat_rc(struct ath_rate_priv *rc, int final_rate)
+{
+        struct ath_rc_stats *stats;
+
+        stats = &rc->rcstats[final_rate];
+        stats->success++;
+}
+
+
 static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
                           struct ieee80211_sta *sta, void *priv_sta,
                           struct sk_buff *skb)
@@ -1332,14 +1317,14 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
         struct ath_rate_priv *ath_rc_priv = priv_sta;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         struct ieee80211_hdr *hdr;
-        int final_ts_idx = 0, tx_status = 0, is_underrun = 0;
+        int final_ts_idx = 0, tx_status = 0;
         int long_retry = 0;
         __le16 fc;
         int i;
 
         hdr = (struct ieee80211_hdr *)skb->data;
         fc = hdr->frame_control;
-        for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
+        for (i = 0; i < sc->hw->max_rates; i++) {
                 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i];
                 if (!rate->count)
                         break;
@@ -1359,32 +1344,23 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
         if (tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED)
                 return;
 
-        /*
-         * If an underrun error is seen assume it as an excessive retry only
-         * if max frame trigger level has been reached (2 KB for singel stream,
-         * and 4 KB for dual stream). Adjust the long retry as if the frame was
-         * tried hw->max_rate_tries times to affect how ratectrl updates PER for
-         * the failed rate. In case of congestion on the bus penalizing these
-         * type of underruns should help hardware actually transmit new frames
-         * successfully by eventually preferring slower rates. This itself
-         * should also alleviate congestion on the bus.
-         */
-        if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
-            (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
-                tx_status = 1;
-                is_underrun = 1;
+        if (!(tx_info->flags & IEEE80211_TX_STAT_AMPDU)) {
+                tx_info->status.ampdu_ack_len =
+                        (tx_info->flags & IEEE80211_TX_STAT_ACK ? 1 : 0);
+                tx_info->status.ampdu_len = 1;
         }
 
-        if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
+        if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
                 tx_status = 1;
 
         ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
-                         (is_underrun) ? sc->hw->max_rate_tries : long_retry);
+                         long_retry);
 
         /* Check if aggregation has to be enabled for this tid */
         if (conf_is_ht(&sc->hw->conf) &&
             !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
-                if (ieee80211_is_data_qos(fc)) {
+                if (ieee80211_is_data_qos(fc) &&
+                    skb_get_queue_mapping(skb) != IEEE80211_AC_VO) {
                         u8 *qc, tid;
                         struct ath_node *an;
 
@@ -1393,12 +1369,13 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
                         an = (struct ath_node *)sta->drv_priv;
 
                         if(ath_tx_aggr_check(sc, an, tid))
-                                ieee80211_start_tx_ba_session(sta, tid);
+                                ieee80211_start_tx_ba_session(sta, tid, 0);
                 }
         }
 
-        ath_debug_stat_rc(sc, ath_rc_get_rateindex(sc->cur_rate_table,
-                &tx_info->status.rates[final_ts_idx]));
+        ath_debug_stat_rc(ath_rc_priv,
+                ath_rc_get_rateindex(ath_rc_priv->rate_table,
+                        &tx_info->status.rates[final_ts_idx]));
 }
 
 static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
@@ -1429,23 +1406,17 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
                 ath_rc_priv->neg_ht_rates.rs_nrates = j;
         }
 
-        is_cw40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
+        is_cw40 = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
 
         if (is_cw40)
-                is_sgi = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
+                is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
         else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
-                is_sgi = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
+                is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
 
         /* Choose rate table first */
 
-        if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) {
-                rate_table = ath_choose_rate_table(sc, sband->band,
-                                      sta->ht_cap.ht_supported, is_cw40);
-        } else {
-                rate_table = hw_rate_table[sc->cur_rate_mode];
-        }
+        rate_table = ath_choose_rate_table(sc, sband->band,
+                              sta->ht_cap.ht_supported);
 
         ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta, is_cw40, is_sgi);
         ath_rc_init(sc, priv_sta, sband, sta, rate_table);
@@ -1459,10 +1430,8 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
         struct ath_rate_priv *ath_rc_priv = priv_sta;
         const struct ath_rate_table *rate_table = NULL;
         bool oper_cw40 = false, oper_sgi;
-        bool local_cw40 = (ath_rc_priv->ht_cap & WLAN_RC_40_FLAG) ?
-                true : false;
-        bool local_sgi = (ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG) ?
-                true : false;
+        bool local_cw40 = !!(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG);
+        bool local_sgi = !!(ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG);
 
         /* FIXME: Handle AP mode later when we support CWM */
 
@@ -1485,24 +1454,109 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
 
                 if ((local_cw40 != oper_cw40) || (local_sgi != oper_sgi)) {
                         rate_table = ath_choose_rate_table(sc, sband->band,
-                                                   sta->ht_cap.ht_supported,
-                                                   oper_cw40);
+                                                   sta->ht_cap.ht_supported);
                         ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta,
                                                    oper_cw40, oper_sgi);
                         ath_rc_init(sc, priv_sta, sband, sta, rate_table);
 
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                                  "Operating HT Bandwidth changed to: %d\n",
-                                  sc->hw->conf.channel_type);
-                        sc->cur_rate_table = hw_rate_table[sc->cur_rate_mode];
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                                "Operating HT Bandwidth changed to: %d\n",
+                                sc->hw->conf.channel_type);
+                }
+        }
+}
+
+#ifdef CONFIG_ATH9K_DEBUGFS
+
+static int ath9k_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
+                                size_t count, loff_t *ppos)
+{
+        struct ath_rate_priv *rc = file->private_data;
+        char *buf;
+        unsigned int len = 0, max;
+        int i = 0;
+        ssize_t retval;
+
+        if (rc->rate_table == NULL)
+                return 0;
+
+        max = 80 + rc->rate_table->rate_cnt * 1024 + 1;
+        buf = kmalloc(max, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += sprintf(buf, "%6s %6s %6s "
+                       "%10s %10s %10s %10s\n",
+                       "HT", "MCS", "Rate",
+                       "Success", "Retries", "XRetries", "PER");
+
+        for (i = 0; i < rc->rate_table->rate_cnt; i++) {
+                u32 ratekbps = rc->rate_table->info[i].ratekbps;
+                struct ath_rc_stats *stats = &rc->rcstats[i];
+                char mcs[5];
+                char htmode[5];
+                int used_mcs = 0, used_htmode = 0;
+
+                if (WLAN_RC_PHY_HT(rc->rate_table->info[i].phy)) {
+                        used_mcs = snprintf(mcs, 5, "%d",
+                                rc->rate_table->info[i].ratecode);
+
+                        if (WLAN_RC_PHY_40(rc->rate_table->info[i].phy))
+                                used_htmode = snprintf(htmode, 5, "HT40");
+                        else if (WLAN_RC_PHY_20(rc->rate_table->info[i].phy))
+                                used_htmode = snprintf(htmode, 5, "HT20");
+                        else
+                                used_htmode = snprintf(htmode, 5, "????");
                 }
+
+                mcs[used_mcs] = '\0';
+                htmode[used_htmode] = '\0';
+
+                len += snprintf(buf + len, max - len,
+                        "%6s %6s %3u.%d: "
+                        "%10u %10u %10u %10u\n",
+                        htmode,
+                        mcs,
+                        ratekbps / 1000,
+                        (ratekbps % 1000) / 100,
+                        stats->success,
+                        stats->retries,
+                        stats->xretries,
+                        stats->per);
         }
+
+        if (len > max)
+                len = max;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+        return retval;
 }
 
+static const struct file_operations fops_rcstat = {
+        .read = read_file_rcstat,
+        .open = ath9k_debugfs_open,
+        .owner = THIS_MODULE
+};
+
+static void ath_rate_add_sta_debugfs(void *priv, void *priv_sta,
+                                     struct dentry *dir)
+{
+        struct ath_rate_priv *rc = priv_sta;
+        debugfs_create_file("rc_stats", S_IRUGO, dir, rc, &fops_rcstat);
+}
+
+#endif /* CONFIG_ATH9K_DEBUGFS */
+
 static void *ath_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        return aphy->sc;
+        return hw->priv;
 }
 
 static void ath_rate_free(void *priv)
@@ -1517,13 +1571,11 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
 
         rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
         if (!rate_priv) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to allocate private rc structure\n");
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to allocate private rc structure\n");
                 return NULL;
         }
 
-        rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
-
         return rate_priv;
 }
 
@@ -1545,6 +1597,9 @@ static struct rate_control_ops ath_rate_ops = {
         .free = ath_rate_free,
         .alloc_sta = ath_rate_alloc_sta,
         .free_sta = ath_rate_free_sta,
+#ifdef CONFIG_ATH9K_DEBUGFS
+        .add_sta_debugfs = ath_rate_add_sta_debugfs,
+#endif
 };
 
 int ath_rate_control_register(void)
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index dc1082654501..c3d850207bee 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2004 Sam Leffler, Errno Consulting
  * Copyright (c) 2004 Video54 Technologies, Inc.
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -135,20 +135,21 @@ enum {
 
 /**
  * struct ath_rate_table - Rate Control table
- * @valid: valid for use in rate control
- * @valid_single_stream: valid for use in rate control for
- *      single stream operation
- * @phy: CCK/OFDM
+ * @rate_cnt: total number of rates for the given wireless mode
+ * @mcs_start: MCS rate index offset
+ * @rate_flags: Rate Control flags
+ * @phy: CCK/OFDM/HT20/HT40
  * @ratekbps: rate in Kbits per second
  * @user_ratekbps: user rate in Kbits per second
  * @ratecode: rate that goes into HW descriptors
- * @short_preamble: Mask for enabling short preamble in ratecode for CCK
  * @dot11rate: value that goes into supported
  *      rates info element of MLME
  * @ctrl_rate: Index of next lower basic rate, used for duration computation
- * @max_4ms_framelen: maximum frame length(bytes) for tx duration
+ * @cw40index: Index of rates having 40MHz channel width
+ * @sgi_index: Index of rates having Short Guard Interval
+ * @ht_index: high throughput rates having 40MHz channel width and
+ *      Short Guard Interval
  * @probe_interval: interval for rate control to probe for other rates
- * @rssi_reduce_interval: interval for rate control to reduce rssi
  * @initial_ratemax: initial ratemax value
  */
 struct ath_rate_table {
@@ -175,6 +176,13 @@ struct ath_rateset {
         u8 rs_rates[ATH_RATE_MAX];
 };
 
+struct ath_rc_stats {
+        u32 success;
+        u32 retries;
+        u32 xretries;
+        u8 per;
+};
+
 /**
  * struct ath_rate_priv - Rate Control priv data
  * @state: RC state
@@ -187,7 +195,6 @@ struct ath_rateset {
  * @rate_max_phy: phy index for the max rate
  * @per: PER for every valid rate in %
  * @probe_interval: interval for ratectrl to probe for other rates
- * @prev_data_rix: rate idx of last data frame
  * @ht_cap: HT capabilities
  * @neg_rates: Negotatied rates
  * @neg_ht_rates: Negotiated HT rates
@@ -206,17 +213,13 @@ struct ath_rate_priv {
         u32 probe_time;
         u32 per_down_time;
         u32 probe_interval;
-        u32 prev_data_rix;
-        u32 tx_triglevel_max;
         struct ath_rateset neg_rates;
         struct ath_rateset neg_ht_rates;
-        struct ath_rate_softc *asc;
-};
+        const struct ath_rate_table *rate_table;
 
-#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
-#define ATH_TX_INFO_FRAME_TYPE_PAUSE    (1 << 1)
-#define ATH_TX_INFO_XRETRY              (1 << 3)
-#define ATH_TX_INFO_UNDERRUN            (1 << 4)
+        struct dentry *debugfs_rcstats;
+        struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
+};
 
 enum ath9k_internal_frame_type {
         ATH9K_IFT_NOT_INTERNAL,
@@ -224,7 +227,18 @@ enum ath9k_internal_frame_type {
         ATH9K_IFT_UNPAUSE
 };
 
+#ifdef CONFIG_ATH9K_RATE_CONTROL
 int ath_rate_control_register(void);
 void ath_rate_control_unregister(void);
+#else
+static inline int ath_rate_control_register(void)
+{
+        return 0;
+}
+
+static inline void ath_rate_control_unregister(void)
+{
+}
+#endif
 
 #endif /* RC_H */
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index a3fc987ebab0..07e35e59c9e3 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,31 +19,46 @@
 
 #define SKB_CB_ATHBUF(__skb)    (*((struct ath_buf **)__skb->cb))
 
-static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
+static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
+                                               int mindelta, int main_rssi_avg,
+                                               int alt_rssi_avg, int pkt_count)
 {
-        return sc->ps_enabled &&
-               (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
+        return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
+                (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
+                (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
 }
 
-static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
-                                             struct ieee80211_hdr *hdr)
+static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
+                                        int curr_main_set, int curr_alt_set,
+                                        int alt_rssi_avg, int main_rssi_avg)
 {
-        struct ieee80211_hw *hw = sc->pri_wiphy->hw;
-        int i;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
-                        continue;
-                if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
-                    == 0) {
-                        hw = aphy->hw;
-                        break;
-                }
+        bool result = false;
+        switch (div_group) {
+        case 0:
+                if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
+                        result = true;
+                break;
+        case 1:
+                if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
+                        (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
+                                (alt_rssi_avg >= (main_rssi_avg - 5))) ||
+                        ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
+                        (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
+                                (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
+                                                        (alt_rssi_avg >= 4))
+                        result = true;
+                else
+                        result = false;
+                break;
         }
-        spin_unlock_bh(&sc->wiphy_lock);
-        return hw;
+
+        return result;
+}
+
+static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
+{
+        return sc->ps_enabled &&
+               (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
 }
 
 /*
@@ -87,7 +102,6 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
                 *sc->rx.rxlink = bf->bf_daddr;
 
         sc->rx.rxlink = &ds->ds_link;
-        ath9k_hw_rxena(ah);
 }
 
 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
@@ -110,8 +124,7 @@ static void ath_opmode_init(struct ath_softc *sc)
         ath9k_hw_setrxfilter(ah, rfilt);
 
         /* configure bssid mask */
-        if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
-                ath_hw_setbssidmask(common);
+        ath_hw_setbssidmask(common);
 
         /* configure operational mode */
         ath9k_hw_setopmode(ah);
@@ -157,7 +170,7 @@ static void ath_rx_addbuffer_edma(struct ath_softc *sc,
         u32 nbuf = 0;
 
         if (list_empty(&sc->rx.rxbuf)) {
-                ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
+                ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
                 return;
         }
 
@@ -222,11 +235,6 @@ static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
         int error = 0, i;
         u32 size;
 
-
-        common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
-                                     ah->caps.rx_status_len,
-                                     min(common->cachelsz, (u16)64));
-
         ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
                                     ah->caps.rx_status_len);
 
@@ -260,7 +268,8 @@ static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
                                                 bf->bf_buf_addr))) {
                                 dev_kfree_skb_any(skb);
                                 bf->bf_mpdu = NULL;
-                                ath_print(common, ATH_DBG_FATAL,
+                                bf->bf_buf_addr = 0;
+                                ath_err(common,
                                         "dma_mapping_error() on RX init\n");
                                 error = -ENOMEM;
                                 goto rx_init_fail;
@@ -288,19 +297,17 @@ static void ath_edma_start_recv(struct ath_softc *sc)
         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
                               sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
 
-        spin_unlock_bh(&sc->rx.rxbuflock);
-
         ath_opmode_init(sc);
 
-        ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_SCANNING));
+        ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+
+        spin_unlock_bh(&sc->rx.rxbuflock);
 }
 
 static void ath_edma_stop_recv(struct ath_softc *sc)
 {
-        spin_lock_bh(&sc->rx.rxbuflock);
         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
-        spin_unlock_bh(&sc->rx.rxbuflock);
 }
 
 int ath_rx_init(struct ath_softc *sc, int nbufs)
@@ -310,27 +317,27 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
         struct ath_buf *bf;
         int error = 0;
 
-        spin_lock_init(&sc->rx.rxflushlock);
+        spin_lock_init(&sc->sc_pcu_lock);
         sc->sc_flags &= ~SC_OP_RXFLUSH;
         spin_lock_init(&sc->rx.rxbuflock);
 
+        common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
+                             sc->sc_ah->caps.rx_status_len;
+
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 return ath_rx_edma_init(sc, nbufs);
         } else {
-                common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
-                                min(common->cachelsz, (u16)64));
-
-                ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
-                                common->cachelsz, common->rx_bufsize);
+                ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
+                        common->cachelsz, common->rx_bufsize);
 
                 /* Initialize rx descriptors */
 
                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
                                 "rx", nbufs, 1, 0);
                 if (error != 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "failed to allocate rx descriptors: %d\n",
-                                  error);
+                        ath_err(common,
+                                "failed to allocate rx descriptors: %d\n",
+                                error);
                         goto err;
                 }
 
@@ -350,12 +357,12 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
                                                         bf->bf_buf_addr))) {
                                 dev_kfree_skb_any(skb);
                                 bf->bf_mpdu = NULL;
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "dma_mapping_error() on RX init\n");
+                                bf->bf_buf_addr = 0;
+                                ath_err(common,
+                                        "dma_mapping_error() on RX init\n");
                                 error = -ENOMEM;
                                 goto err;
                         }
-                        bf->bf_dmacontext = bf->bf_buf_addr;
                 }
                 sc->rx.rxlink = NULL;
         }
@@ -385,6 +392,8 @@ void ath_rx_cleanup(struct ath_softc *sc)
                                                 common->rx_bufsize,
                                                 DMA_FROM_DEVICE);
                                 dev_kfree_skb(skb);
+                                bf->bf_buf_addr = 0;
+                                bf->bf_mpdu = NULL;
                         }
                 }
 
@@ -422,8 +431,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
                 | ATH9K_RX_FILTER_MCAST;
 
-        /* If not a STA, enable processing of Probe Requests */
-        if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
+        if (sc->rx.rxfilter & FIF_PROBE_REQ)
                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 
         /*
@@ -431,32 +439,27 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
          * mode interface or when in monitor mode. AP mode does not need this
          * since it receives all in-BSS frames anyway.
          */
-        if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
-             (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
+        if (sc->sc_ah->is_monitoring)
                 rfilt |= ATH9K_RX_FILTER_PROM;
 
         if (sc->rx.rxfilter & FIF_CONTROL)
                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 
         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+            (sc->nvifs <= 1) &&
             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
         else
                 rfilt |= ATH9K_RX_FILTER_BEACON;
 
-        if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
-            AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
-            (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+        if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
             (sc->rx.rxfilter & FIF_PSPOLL))
                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
 
         if (conf_is_ht(&sc->hw->conf))
                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
 
-        if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
-                /* TODO: only needed if more than one BSSID is in use in
-                 * station/adhoc mode */
+        if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
                 /* The following may also be needed for other older chips */
                 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
                         rfilt |= ATH9K_RX_FILTER_PROM;
@@ -496,9 +499,10 @@ int ath_startrecv(struct ath_softc *sc)
         ath9k_hw_rxena(ah);
 
 start_recv:
-        spin_unlock_bh(&sc->rx.rxbuflock);
         ath_opmode_init(sc);
-        ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_SCANNING));
+        ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+
+        spin_unlock_bh(&sc->rx.rxbuflock);
 
         return 0;
 }
@@ -506,29 +510,36 @@ start_recv:
 bool ath_stoprecv(struct ath_softc *sc)
 {
         struct ath_hw *ah = sc->sc_ah;
-        bool stopped;
+        bool stopped, reset = false;
 
-        ath9k_hw_stoppcurecv(ah);
+        spin_lock_bh(&sc->rx.rxbuflock);
+        ath9k_hw_abortpcurecv(ah);
         ath9k_hw_setrxfilter(ah, 0);
-        stopped = ath9k_hw_stopdmarecv(ah);
+        stopped = ath9k_hw_stopdmarecv(ah, &reset);
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                 ath_edma_stop_recv(sc);
         else
                 sc->rx.rxlink = NULL;
+        spin_unlock_bh(&sc->rx.rxbuflock);
 
-        return stopped;
+        if (!(ah->ah_flags & AH_UNPLUGGED) &&
+            unlikely(!stopped)) {
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Could not stop RX, we could be "
+                        "confusing the DMA engine when we start RX up\n");
+                ATH_DBG_WARN_ON_ONCE(!stopped);
+        }
+        return stopped && !reset;
 }
 
 void ath_flushrecv(struct ath_softc *sc)
 {
-        spin_lock_bh(&sc->rx.rxflushlock);
         sc->sc_flags |= SC_OP_RXFLUSH;
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                 ath_rx_tasklet(sc, 1, true);
         ath_rx_tasklet(sc, 1, false);
         sc->sc_flags &= ~SC_OP_RXFLUSH;
-        spin_unlock_bh(&sc->rx.rxflushlock);
 }
 
 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
@@ -572,17 +583,23 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                 return;
 
         mgmt = (struct ieee80211_mgmt *)skb->data;
-        if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
+        if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
+                /* TODO:  This doesn't work well if you have stations
+                 * associated to two different APs because curbssid
+                 * is just the last AP that any of the stations associated
+                 * with.
+                 */
                 return; /* not from our current AP */
+        }
 
         sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
 
         if (sc->ps_flags & PS_BEACON_SYNC) {
                 sc->ps_flags &= ~PS_BEACON_SYNC;
-                ath_print(common, ATH_DBG_PS,
-                          "Reconfigure Beacon timers based on "
-                          "timestamp from the AP\n");
-                ath_beacon_config(sc, NULL);
+                ath_dbg(common, ATH_DBG_PS,
+                        "Reconfigure Beacon timers based on timestamp from the AP\n");
+                ath_set_beacon(sc);
+                sc->ps_flags &= ~PS_TSFOOR_SYNC;
         }
 
         if (ath_beacon_dtim_pending_cab(skb)) {
@@ -593,8 +610,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                  * a backup trigger for returning into NETWORK SLEEP state,
                  * so we are waiting for it as well.
                  */
-                ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
-                          "buffered broadcast/multicast frame(s)\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
                 return;
         }
@@ -606,8 +623,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                  * been delivered.
                  */
                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
-                ath_print(common, ATH_DBG_PS,
-                          "PS wait for CAB frames timed out\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "PS wait for CAB frames timed out\n");
         }
 }
 
@@ -631,16 +648,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
                  * No more broadcast/multicast frames to be received at this
                  * point.
                  */
-                sc->ps_flags &= ~PS_WAIT_FOR_CAB;
-                ath_print(common, ATH_DBG_PS,
-                          "All PS CAB frames received, back to sleep\n");
+                sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
+                ath_dbg(common, ATH_DBG_PS,
+                        "All PS CAB frames received, back to sleep\n");
         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
                    !is_multicast_ether_addr(hdr->addr1) &&
                    !ieee80211_has_morefrags(hdr->frame_control)) {
                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
-                ath_print(common, ATH_DBG_PS,
-                          "Going back to sleep after having received "
-                          "PS-Poll data (0x%lx)\n",
+                ath_dbg(common, ATH_DBG_PS,
+                        "Going back to sleep after having received PS-Poll data (0x%lx)\n",
                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                         PS_WAIT_FOR_CAB |
                                         PS_WAIT_FOR_PSPOLL_DATA |
@@ -648,38 +664,6 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
         }
 }
 
-static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
-                                    struct ath_softc *sc, struct sk_buff *skb,
-                                    struct ieee80211_rx_status *rxs)
-{
-        struct ieee80211_hdr *hdr;
-
-        hdr = (struct ieee80211_hdr *)skb->data;
-
-        /* Send the frame to mac80211 */
-        if (is_multicast_ether_addr(hdr->addr1)) {
-                int i;
-                /*
-                 * Deliver broadcast/multicast frames to all suitable
-                 * virtual wiphys.
-                 */
-                /* TODO: filter based on channel configuration */
-                for (i = 0; i < sc->num_sec_wiphy; i++) {
-                        struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                        struct sk_buff *nskb;
-                        if (aphy == NULL)
-                                continue;
-                        nskb = skb_copy(skb, GFP_ATOMIC);
-                        if (!nskb)
-                                continue;
-                        ieee80211_rx(aphy->hw, nskb);
-                }
-                ieee80211_rx(sc->hw, skb);
-        } else
-                /* Deliver unicast frames based on receiver address */
-                ieee80211_rx(hw, skb);
-}
-
 static bool ath_edma_get_buffers(struct ath_softc *sc,
                                  enum ath9k_rx_qtype qtype)
 {
@@ -829,6 +813,10 @@ static bool ath9k_rx_accept(struct ath_common *common,
                             struct ath_rx_status *rx_stats,
                             bool *decrypt_error)
 {
+#define is_mc_or_valid_tkip_keyix ((is_mc ||                    \
+                (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
+                test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
+
         struct ath_hw *ah = common->ah;
         __le16 fc;
         u8 rx_status_len = ah->caps.rx_status_len;
@@ -845,15 +833,9 @@ static bool ath9k_rx_accept(struct ath_common *common,
         if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
                 return false;
 
-        /*
-         * rs_more indicates chained descriptors which can be used
-         * to link buffers together for a sort of scatter-gather
-         * operation.
-         * reject the frame, we don't support scatter-gather yet and
-         * the frame is probably corrupt anyway
-         */
+        /* Only use error bits from the last fragment */
         if (rx_stats->rs_more)
-                return false;
+                return true;
 
         /*
          * The rx_stats->rs_status will not be set until the end of the
@@ -870,22 +852,28 @@ static bool ath9k_rx_accept(struct ath_common *common,
                 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
                         *decrypt_error = true;
                 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
-                        if (ieee80211_is_ctl(fc))
-                                /*
-                                 * Sometimes, we get invalid
-                                 * MIC failures on valid control frames.
-                                 * Remove these mic errors.
-                                 */
-                                rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
-                        else
+                        bool is_mc;
+                        /*
+                         * The MIC error bit is only valid if the frame
+                         * is not a control frame or fragment, and it was
+                         * decrypted using a valid TKIP key.
+                         */
+                        is_mc = !!is_multicast_ether_addr(hdr->addr1);
+
+                        if (!ieee80211_is_ctl(fc) &&
+                            !ieee80211_has_morefrags(fc) &&
+                            !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
+                            is_mc_or_valid_tkip_keyix)
                                 rxs->flag |= RX_FLAG_MMIC_ERROR;
+                        else
+                                rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
                 }
                 /*
                  * Reject error frames with the exception of
                  * decryption and MIC failures. For monitor mode,
                  * we also ignore the CRC error.
                  */
-                if (ah->opmode == NL80211_IFTYPE_MONITOR) {
+                if (ah->is_monitoring) {
                         if (rx_stats->rs_status &
                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
                               ATH9K_RXERR_CRC))
@@ -939,8 +927,9 @@ static int ath9k_process_rate(struct ath_common *common,
          * No valid hardware bitrate found -- we should not get here
          * because hardware has already validated this frame as OK.
          */
-        ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
-                  "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
+        ath_dbg(common, ATH_DBG_XMIT,
+                "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
+                rx_stats->rs_rate);
 
         return -EINVAL;
 }
@@ -950,32 +939,30 @@ static void ath9k_process_rssi(struct ath_common *common,
                                struct ieee80211_hdr *hdr,
                                struct ath_rx_status *rx_stats)
 {
+        struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = common->ah;
-        struct ieee80211_sta *sta;
-        struct ath_node *an;
-        int last_rssi = ATH_RSSI_DUMMY_MARKER;
+        int last_rssi;
         __le16 fc;
 
-        fc = hdr->frame_control;
+        if ((ah->opmode != NL80211_IFTYPE_STATION) &&
+            (ah->opmode != NL80211_IFTYPE_ADHOC))
+                return;
 
-        rcu_read_lock();
-        /*
-         * XXX: use ieee80211_find_sta! This requires quite a bit of work
-         * under the current ath9k virtual wiphy implementation as we have
-         * no way of tying a vif to wiphy. Typically vifs are attached to
-         * at least one sdata of a wiphy on mac80211 but with ath9k virtual
-         * wiphy you'd have to iterate over every wiphy and each sdata.
-         */
-        sta = ieee80211_find_sta_by_hw(hw, hdr->addr2);
-        if (sta) {
-                an = (struct ath_node *) sta->drv_priv;
-                if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
-                   !rx_stats->rs_moreaggr)
-                        ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
-                last_rssi = an->last_rssi;
+        fc = hdr->frame_control;
+        if (!ieee80211_is_beacon(fc) ||
+            compare_ether_addr(hdr->addr3, common->curbssid)) {
+                /* TODO:  This doesn't work well if you have stations
+                 * associated to two different APs because curbssid
+                 * is just the last AP that any of the stations associated
+                 * with.
+                 */
+                return;
         }
-        rcu_read_unlock();
 
+        if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
+                ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
+
+        last_rssi = sc->last_rssi;
         if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
                 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
                                               ATH_RSSI_EP_MULTIPLIER);
@@ -983,8 +970,7 @@ static void ath9k_process_rssi(struct ath_common *common,
                 rx_stats->rs_rssi = 0;
 
         /* Update Beacon RSSI, this is used by ANI. */
-        if (ieee80211_is_beacon(fc))
-                ah->stats.avgbrssi = rx_stats->rs_rssi;
+        ah->stats.avgbrssi = rx_stats->rs_rssi;
 }
 
 /*
@@ -1008,6 +994,10 @@ static int ath9k_rx_skb_preprocess(struct ath_common *common,
         if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
                 return -EINVAL;
 
+        /* Only use status info from the last fragment */
+        if (rx_stats->rs_more)
+                return 0;
+
         ath9k_process_rssi(common, hw, hdr, rx_stats);
 
         if (ath9k_process_rate(common, hw, rx_stats, rx_status))
@@ -1017,7 +1007,7 @@ static int ath9k_rx_skb_preprocess(struct ath_common *common,
         rx_status->freq = hw->conf.channel->center_freq;
         rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
         rx_status->antenna = rx_stats->rs_antenna;
-        rx_status->flag |= RX_FLAG_TSFT;
+        rx_status->flag |= RX_FLAG_MACTIME_MPDU;
 
         return 0;
 }
@@ -1073,19 +1063,641 @@ static void ath9k_rx_skb_postprocess(struct ath_common *common,
                 rxs->flag &= ~RX_FLAG_DECRYPTED;
 }
 
+static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
+                                      struct ath_hw_antcomb_conf ant_conf,
+                                      int main_rssi_avg)
+{
+        antcomb->quick_scan_cnt = 0;
+
+        if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
+                antcomb->rssi_lna2 = main_rssi_avg;
+        else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
+                antcomb->rssi_lna1 = main_rssi_avg;
+
+        switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
+        case (0x10): /* LNA2 A-B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
+                break;
+        case (0x20): /* LNA1 A-B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
+                break;
+        case (0x21): /* LNA1 LNA2 */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                break;
+        case (0x12): /* LNA2 LNA1 */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                break;
+        case (0x13): /* LNA2 A+B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
+                break;
+        case (0x23): /* LNA1 A+B */
+                antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                antcomb->first_quick_scan_conf =
+                        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
+                                struct ath_hw_antcomb_conf *div_ant_conf,
+                                int main_rssi_avg, int alt_rssi_avg,
+                                int alt_ratio)
+{
+        /* alt_good */
+        switch (antcomb->quick_scan_cnt) {
+        case 0:
+                /* set alt to main, and alt to first conf */
+                div_ant_conf->main_lna_conf = antcomb->main_conf;
+                div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
+                break;
+        case 1:
+                /* set alt to main, and alt to first conf */
+                div_ant_conf->main_lna_conf = antcomb->main_conf;
+                div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
+                antcomb->rssi_first = main_rssi_avg;
+                antcomb->rssi_second = alt_rssi_avg;
+
+                if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
+                        /* main is LNA1 */
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->first_ratio = true;
+                        else
+                                antcomb->first_ratio = false;
+                } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->first_ratio = true;
+                        else
+                                antcomb->first_ratio = false;
+                } else {
+                        if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
+                            (alt_rssi_avg > main_rssi_avg +
+                            ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
+                            (alt_rssi_avg > main_rssi_avg)) &&
+                            (antcomb->total_pkt_count > 50))
+                                antcomb->first_ratio = true;
+                        else
+                                antcomb->first_ratio = false;
+                }
+                break;
+        case 2:
+                antcomb->alt_good = false;
+                antcomb->scan_not_start = false;
+                antcomb->scan = false;
+                antcomb->rssi_first = main_rssi_avg;
+                antcomb->rssi_third = alt_rssi_avg;
+
+                if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
+                        antcomb->rssi_lna1 = alt_rssi_avg;
+                else if (antcomb->second_quick_scan_conf ==
+                         ATH_ANT_DIV_COMB_LNA2)
+                        antcomb->rssi_lna2 = alt_rssi_avg;
+                else if (antcomb->second_quick_scan_conf ==
+                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
+                        if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
+                                antcomb->rssi_lna2 = main_rssi_avg;
+                        else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
+                                antcomb->rssi_lna1 = main_rssi_avg;
+                }
+
+                if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
+                    ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
+                        div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
+                else
+                        div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
+
+                if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->second_ratio = true;
+                        else
+                                antcomb->second_ratio = false;
+                } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
+                        if (ath_is_alt_ant_ratio_better(alt_ratio,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
+                                                ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
+                                                main_rssi_avg, alt_rssi_avg,
+                                                antcomb->total_pkt_count))
+                                antcomb->second_ratio = true;
+                        else
+                                antcomb->second_ratio = false;
+                } else {
+                        if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
+                            (alt_rssi_avg > main_rssi_avg +
+                            ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
+                            (alt_rssi_avg > main_rssi_avg)) &&
+                            (antcomb->total_pkt_count > 50))
+                                antcomb->second_ratio = true;
+                        else
+                                antcomb->second_ratio = false;
+                }
+
+                /* set alt to the conf with maximun ratio */
+                if (antcomb->first_ratio && antcomb->second_ratio) {
+                        if (antcomb->rssi_second > antcomb->rssi_third) {
+                                /* first alt*/
+                                if ((antcomb->first_quick_scan_conf ==
+                                    ATH_ANT_DIV_COMB_LNA1) ||
+                                    (antcomb->first_quick_scan_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2))
+                                        /* Set alt LNA1 or LNA2*/
+                                        if (div_ant_conf->main_lna_conf ==
+                                            ATH_ANT_DIV_COMB_LNA2)
+                                                div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA1;
+                                        else
+                                                div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA2;
+                                else
+                                        /* Set alt to A+B or A-B */
+                                        div_ant_conf->alt_lna_conf =
+                                                antcomb->first_quick_scan_conf;
+                        } else if ((antcomb->second_quick_scan_conf ==
+                                   ATH_ANT_DIV_COMB_LNA1) ||
+                                   (antcomb->second_quick_scan_conf ==
+                                   ATH_ANT_DIV_COMB_LNA2)) {
+                                /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        } else {
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf =
+                                        antcomb->second_quick_scan_conf;
+                        }
+                } else if (antcomb->first_ratio) {
+                        /* first alt */
+                        if ((antcomb->first_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA1) ||
+                            (antcomb->first_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA2))
+                                        /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA2;
+                        else
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf =
+                                                antcomb->first_quick_scan_conf;
+                } else if (antcomb->second_ratio) {
+                                /* second alt */
+                        if ((antcomb->second_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA1) ||
+                            (antcomb->second_quick_scan_conf ==
+                            ATH_ANT_DIV_COMB_LNA2))
+                                /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        else
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf =
+                                                antcomb->second_quick_scan_conf;
+                } else {
+                        /* main is largest */
+                        if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
+                            (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
+                                /* Set alt LNA1 or LNA2 */
+                                if (div_ant_conf->main_lna_conf ==
+                                    ATH_ANT_DIV_COMB_LNA2)
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA1;
+                                else
+                                        div_ant_conf->alt_lna_conf =
+                                                        ATH_ANT_DIV_COMB_LNA2;
+                        else
+                                /* Set alt to A+B or A-B */
+                                div_ant_conf->alt_lna_conf = antcomb->main_conf;
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
+                struct ath_ant_comb *antcomb, int alt_ratio)
+{
+        if (ant_conf->div_group == 0) {
+                /* Adjust the fast_div_bias based on main and alt lna conf */
+                switch ((ant_conf->main_lna_conf << 4) |
+                                ant_conf->alt_lna_conf) {
+                case (0x01): /* A-B LNA2 */
+                        ant_conf->fast_div_bias = 0x3b;
+                        break;
+                case (0x02): /* A-B LNA1 */
+                        ant_conf->fast_div_bias = 0x3d;
+                        break;
+                case (0x03): /* A-B A+B */
+                        ant_conf->fast_div_bias = 0x1;
+                        break;
+                case (0x10): /* LNA2 A-B */
+                        ant_conf->fast_div_bias = 0x7;
+                        break;
+                case (0x12): /* LNA2 LNA1 */
+                        ant_conf->fast_div_bias = 0x2;
+                        break;
+                case (0x13): /* LNA2 A+B */
+                        ant_conf->fast_div_bias = 0x7;
+                        break;
+                case (0x20): /* LNA1 A-B */
+                        ant_conf->fast_div_bias = 0x6;
+                        break;
+                case (0x21): /* LNA1 LNA2 */
+                        ant_conf->fast_div_bias = 0x0;
+                        break;
+                case (0x23): /* LNA1 A+B */
+                        ant_conf->fast_div_bias = 0x6;
+                        break;
+                case (0x30): /* A+B A-B */
+                        ant_conf->fast_div_bias = 0x1;
+                        break;
+                case (0x31): /* A+B LNA2 */
+                        ant_conf->fast_div_bias = 0x3b;
+                        break;
+                case (0x32): /* A+B LNA1 */
+                        ant_conf->fast_div_bias = 0x3d;
+                        break;
+                default:
+                        break;
+                }
+        } else if (ant_conf->div_group == 2) {
+                /* Adjust the fast_div_bias based on main and alt_lna_conf */
+                switch ((ant_conf->main_lna_conf << 4) |
+                                ant_conf->alt_lna_conf) {
+                case (0x01): /* A-B LNA2 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x02): /* A-B LNA1 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x03): /* A-B A+B */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x10): /* LNA2 A-B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x12): /* LNA2 LNA1 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x13): /* LNA2 A+B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x20): /* LNA1 A-B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x21): /* LNA1 LNA2 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x23): /* LNA1 A+B */
+                        if (!(antcomb->scan) &&
+                                (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
+                                ant_conf->fast_div_bias = 0x1;
+                        else
+                                ant_conf->fast_div_bias = 0x2;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x30): /* A+B A-B */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x31): /* A+B LNA2 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                case (0x32): /* A+B LNA1 */
+                        ant_conf->fast_div_bias = 0x1;
+                        ant_conf->main_gaintb = 0;
+                        ant_conf->alt_gaintb = 0;
+                        break;
+                default:
+                        break;
+                }
+
+        }
+
+}
+
+/* Antenna diversity and combining */
+static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
+{
+        struct ath_hw_antcomb_conf div_ant_conf;
+        struct ath_ant_comb *antcomb = &sc->ant_comb;
+        int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
+        int curr_main_set;
+        int main_rssi = rs->rs_rssi_ctl0;
+        int alt_rssi = rs->rs_rssi_ctl1;
+        int rx_ant_conf,  main_ant_conf;
+        bool short_scan = false;
+
+        rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
+                       ATH_ANT_RX_MASK;
+        main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
+                         ATH_ANT_RX_MASK;
+
+        /* Record packet only when both main_rssi and  alt_rssi is positive */
+        if (main_rssi > 0 && alt_rssi > 0) {
+                antcomb->total_pkt_count++;
+                antcomb->main_total_rssi += main_rssi;
+                antcomb->alt_total_rssi  += alt_rssi;
+                if (main_ant_conf == rx_ant_conf)
+                        antcomb->main_recv_cnt++;
+                else
+                        antcomb->alt_recv_cnt++;
+        }
+
+        /* Short scan check */
+        if (antcomb->scan && antcomb->alt_good) {
+                if (time_after(jiffies, antcomb->scan_start_time +
+                    msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
+                        short_scan = true;
+                else
+                        if (antcomb->total_pkt_count ==
+                            ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
+                                alt_ratio = ((antcomb->alt_recv_cnt * 100) /
+                                            antcomb->total_pkt_count);
+                                if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
+                                        short_scan = true;
+                        }
+        }
+
+        if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
+            rs->rs_moreaggr) && !short_scan)
+                return;
+
+        if (antcomb->total_pkt_count) {
+                alt_ratio = ((antcomb->alt_recv_cnt * 100) /
+                             antcomb->total_pkt_count);
+                main_rssi_avg = (antcomb->main_total_rssi /
+                                 antcomb->total_pkt_count);
+                alt_rssi_avg = (antcomb->alt_total_rssi /
+                                 antcomb->total_pkt_count);
+        }
+
+
+        ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
+        curr_alt_set = div_ant_conf.alt_lna_conf;
+        curr_main_set = div_ant_conf.main_lna_conf;
+
+        antcomb->count++;
+
+        if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
+                if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
+                        ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
+                                                  main_rssi_avg);
+                        antcomb->alt_good = true;
+                } else {
+                        antcomb->alt_good = false;
+                }
+
+                antcomb->count = 0;
+                antcomb->scan = true;
+                antcomb->scan_not_start = true;
+        }
+
+        if (!antcomb->scan) {
+                if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
+                                        alt_ratio, curr_main_set, curr_alt_set,
+                                        alt_rssi_avg, main_rssi_avg)) {
+                        if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
+                                /* Switch main and alt LNA */
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                        } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        }
+
+                        goto div_comb_done;
+                } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
+                           (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
+                        /* Set alt to another LNA */
+                        if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                        else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+
+                        goto div_comb_done;
+                }
+
+                if ((alt_rssi_avg < (main_rssi_avg +
+                                                div_ant_conf.lna1_lna2_delta)))
+                        goto div_comb_done;
+        }
+
+        if (!antcomb->scan_not_start) {
+                switch (curr_alt_set) {
+                case ATH_ANT_DIV_COMB_LNA2:
+                        antcomb->rssi_lna2 = alt_rssi_avg;
+                        antcomb->rssi_lna1 = main_rssi_avg;
+                        antcomb->scan = true;
+                        /* set to A+B */
+                        div_ant_conf.main_lna_conf =
+                                ATH_ANT_DIV_COMB_LNA1;
+                        div_ant_conf.alt_lna_conf  =
+                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                        break;
+                case ATH_ANT_DIV_COMB_LNA1:
+                        antcomb->rssi_lna1 = alt_rssi_avg;
+                        antcomb->rssi_lna2 = main_rssi_avg;
+                        antcomb->scan = true;
+                        /* set to A+B */
+                        div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
+                        div_ant_conf.alt_lna_conf  =
+                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                        break;
+                case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
+                        antcomb->rssi_add = alt_rssi_avg;
+                        antcomb->scan = true;
+                        /* set to A-B */
+                        div_ant_conf.alt_lna_conf =
+                                ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                        break;
+                case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
+                        antcomb->rssi_sub = alt_rssi_avg;
+                        antcomb->scan = false;
+                        if (antcomb->rssi_lna2 >
+                            (antcomb->rssi_lna1 +
+                            ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
+                                /* use LNA2 as main LNA */
+                                if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
+                                    (antcomb->rssi_add > antcomb->rssi_sub)) {
+                                        /* set to A+B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                        div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                                } else if (antcomb->rssi_sub >
+                                           antcomb->rssi_lna1) {
+                                        /* set to A-B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                                } else {
+                                        /* set to LNA1 */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                }
+                        } else {
+                                /* use LNA1 as main LNA */
+                                if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
+                                    (antcomb->rssi_add > antcomb->rssi_sub)) {
+                                        /* set to A+B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                        div_ant_conf.alt_lna_conf  =
+                                                ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
+                                } else if (antcomb->rssi_sub >
+                                           antcomb->rssi_lna1) {
+                                        /* set to A-B */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
+                                } else {
+                                        /* set to LNA2 */
+                                        div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                        div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                }
+                        }
+                        break;
+                default:
+                        break;
+                }
+        } else {
+                if (!antcomb->alt_good) {
+                        antcomb->scan_not_start = false;
+                        /* Set alt to another LNA */
+                        if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                        } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
+                                div_ant_conf.main_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA1;
+                                div_ant_conf.alt_lna_conf =
+                                                ATH_ANT_DIV_COMB_LNA2;
+                        }
+                        goto div_comb_done;
+                }
+        }
+
+        ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
+                                           main_rssi_avg, alt_rssi_avg,
+                                           alt_ratio);
+
+        antcomb->quick_scan_cnt++;
+
+div_comb_done:
+        ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
+        ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
+
+        antcomb->scan_start_time = jiffies;
+        antcomb->total_pkt_count = 0;
+        antcomb->main_total_rssi = 0;
+        antcomb->alt_total_rssi = 0;
+        antcomb->main_recv_cnt = 0;
+        antcomb->alt_recv_cnt = 0;
+}
+
 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
 {
         struct ath_buf *bf;
-        struct sk_buff *skb = NULL, *requeue_skb;
+        struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
         struct ieee80211_rx_status *rxs;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         /*
-         * The hw can techncically differ from common->hw when using ath9k
+         * The hw can technically differ from common->hw when using ath9k
          * virtual wiphy so to account for that we iterate over the active
          * wiphys and find the appropriate wiphy and therefore hw.
          */
-        struct ieee80211_hw *hw = NULL;
+        struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_hdr *hdr;
         int retval;
         bool decrypt_error = false;
@@ -1096,6 +1708,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
         u8 rx_status_len = ah->caps.rx_status_len;
         u64 tsf = 0;
         u32 tsf_lower = 0;
+        unsigned long flags;
 
         if (edma)
                 dma_type = DMA_BIDIRECTIONAL;
@@ -1126,10 +1739,17 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 if (!skb)
                         continue;
 
-                hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
-                rxs =  IEEE80211_SKB_RXCB(skb);
+                /*
+                 * Take frame header from the first fragment and RX status from
+                 * the last one.
+                 */
+                if (sc->rx.frag)
+                        hdr_skb = sc->rx.frag;
+                else
+                        hdr_skb = skb;
 
-                hw = ath_get_virt_hw(sc, hdr);
+                hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
+                rxs = IEEE80211_SKB_RXCB(hdr_skb);
 
                 ath_debug_stat_rx(sc, &rs);
 
@@ -1138,12 +1758,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                  * chain it back at the queue without processing it.
                  */
                 if (flush)
-                        goto requeue;
+                        goto requeue_drop_frag;
 
                 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
                                                  rxs, &decrypt_error);
                 if (retval)
-                        goto requeue;
+                        goto requeue_drop_frag;
 
                 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
                 if (rs.rs_tstamp > tsf_lower &&
@@ -1163,7 +1783,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                  * skb and put it at the tail of the sc->rx.rxbuf list for
                  * processing. */
                 if (!requeue_skb)
-                        goto requeue;
+                        goto requeue_drop_frag;
 
                 /* Unmap the frame */
                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
@@ -1174,8 +1794,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 if (ah->caps.rx_status_len)
                         skb_pull(skb, ah->caps.rx_status_len);
 
-                ath9k_rx_skb_postprocess(common, skb, &rs,
-                                         rxs, decrypt_error);
+                if (!rs.rs_more)
+                        ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
+                                                 rxs, decrypt_error);
 
                 /* We will now give hardware our shiny new allocated skb */
                 bf->bf_mpdu = requeue_skb;
@@ -1186,12 +1807,43 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                           bf->bf_buf_addr))) {
                         dev_kfree_skb_any(requeue_skb);
                         bf->bf_mpdu = NULL;
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "dma_mapping_error() on RX\n");
-                        ath_rx_send_to_mac80211(hw, sc, skb, rxs);
+                        bf->bf_buf_addr = 0;
+                        ath_err(common, "dma_mapping_error() on RX\n");
+                        ieee80211_rx(hw, skb);
                         break;
                 }
-                bf->bf_dmacontext = bf->bf_buf_addr;
+
+                if (rs.rs_more) {
+                        /*
+                         * rs_more indicates chained descriptors which can be
+                         * used to link buffers together for a sort of
+                         * scatter-gather operation.
+                         */
+                        if (sc->rx.frag) {
+                                /* too many fragments - cannot handle frame */
+                                dev_kfree_skb_any(sc->rx.frag);
+                                dev_kfree_skb_any(skb);
+                                skb = NULL;
+                        }
+                        sc->rx.frag = skb;
+                        goto requeue;
+                }
+
+                if (sc->rx.frag) {
+                        int space = skb->len - skb_tailroom(hdr_skb);
+
+                        sc->rx.frag = NULL;
+
+                        if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
+                                dev_kfree_skb(skb);
+                                goto requeue_drop_frag;
+                        }
+
+                        skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
+                                                  skb->len);
+                        dev_kfree_skb_any(skb);
+                        skb = hdr_skb;
+                }
 
                 /*
                  * change the default rx antenna if rx diversity chooses the
@@ -1204,14 +1856,25 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                         sc->rx.rxotherant = 0;
                 }
 
-                if (unlikely(ath9k_check_auto_sleep(sc) ||
-                             (sc->ps_flags & (PS_WAIT_FOR_BEACON |
+                spin_lock_irqsave(&sc->sc_pm_lock, flags);
+
+                if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                               PS_WAIT_FOR_CAB |
-                                              PS_WAIT_FOR_PSPOLL_DATA))))
+                                              PS_WAIT_FOR_PSPOLL_DATA)) ||
+                                                ath9k_check_auto_sleep(sc))
                         ath_rx_ps(sc, skb);
+                spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 
-                ath_rx_send_to_mac80211(hw, sc, skb, rxs);
+                if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
+                        ath_ant_comb_scan(sc, &rs);
 
+                ieee80211_rx(hw, skb);
+
+requeue_drop_frag:
+                if (sc->rx.frag) {
+                        dev_kfree_skb_any(sc->rx.frag);
+                        sc->rx.frag = NULL;
+                }
 requeue:
                 if (edma) {
                         list_add_tail(&bf->list, &sc->rx.rxbuf);
@@ -1219,6 +1882,7 @@ requeue:
                 } else {
                         list_move_tail(&bf->list, &sc->rx.rxbuf);
                         ath_rx_buf_link(sc, bf);
+                        ath9k_hw_rxena(ah);
                 }
         } while (1);
 
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index d01c4adab8d6..c18ee9921fb1 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -107,12 +107,6 @@
 #define AR_RXCFG_DMASZ_256B  6
 #define AR_RXCFG_DMASZ_512B  7
 
-#define AR_MIBC              0x0040
-#define AR_MIBC_COW          0x00000001
-#define AR_MIBC_FMC          0x00000002
-#define AR_MIBC_CMC          0x00000004
-#define AR_MIBC_MCS          0x00000008
-
 #define AR_TOPS              0x0044
 #define AR_TOPS_MASK         0x0000FFFF
 
@@ -699,7 +693,7 @@
 #define AR_RC_APB            0x00000002
 #define AR_RC_HOSTIF         0x00000100
 
-#define AR_WA                           0x4004
+#define AR_WA                   (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
 #define AR_WA_BIT6                      (1 << 6)
 #define AR_WA_BIT7                      (1 << 7)
 #define AR_WA_BIT23                     (1 << 23)
@@ -709,6 +703,7 @@
 #define AR_WA_RESET_EN                  (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
 #define AR_WA_ANALOG_SHIFT              (1 << 20)
 #define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
+#define AR_WA_BIT22                     (1 << 22)
 #define AR9285_WA_DEFAULT               0x004a050b
 #define AR9280_WA_DEFAULT               0x0040073b
 #define AR_WA_DEFAULT                   0x0000073f
@@ -717,7 +712,7 @@
 #define AR_PM_STATE                 0x4008
 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
 
-#define AR_HOST_TIMEOUT             0x4018
+#define AR_HOST_TIMEOUT             (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
 #define AR_HOST_TIMEOUT_APB_CNTR    0x0000FFFF
 #define AR_HOST_TIMEOUT_APB_CNTR_S  0
 #define AR_HOST_TIMEOUT_LCL_CNTR    0xFFFF0000
@@ -747,7 +742,8 @@
 #define EEPROM_PROTECT_WP_1024_2047   0x8000
 
 #define AR_SREV \
-        ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020)
+        ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
+                                        ? 0x400c : 0x4020))
 
 #define AR_SREV_ID \
         ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
@@ -792,6 +788,10 @@
 #define AR_SREV_REVISION_9271_11        1
 #define AR_SREV_VERSION_9300            0x1c0
 #define AR_SREV_REVISION_9300_20        2 /* 2.0 and 2.1 */
+#define AR_SREV_VERSION_9485            0x240
+#define AR_SREV_REVISION_9485_10        0
+#define AR_SREV_REVISION_9485_11        1
+#define AR_SREV_VERSION_9340            0x300
 
 #define AR_SREV_5416(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -819,49 +819,23 @@
          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
 #define AR_SREV_9280(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
-#define AR_SREV_9280_10_OR_LATER(_ah) \
+#define AR_SREV_9280_20_OR_LATER(_ah) \
         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
 #define AR_SREV_9280_20(_ah) \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
-                ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))
-#define AR_SREV_9280_20_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
-        ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)))
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
 
 #define AR_SREV_9285(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
-#define AR_SREV_9285_10_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
-#define AR_SREV_9285_11(_ah) \
-        (AR_SREV_9285(ah) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11))
-#define AR_SREV_9285_11_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
-         (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
-                               AR_SREV_REVISION_9285_11)))
-#define AR_SREV_9285_12(_ah) \
-        (AR_SREV_9285(ah) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12))
 #define AR_SREV_9285_12_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
-         (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
-                               AR_SREV_REVISION_9285_12)))
+        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
 
 #define AR_SREV_9287(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
-#define AR_SREV_9287_10_OR_LATER(_ah) \
+#define AR_SREV_9287_11_OR_LATER(_ah) \
         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
-#define AR_SREV_9287_10(_ah) \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_10))
 #define AR_SREV_9287_11(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
-#define AR_SREV_9287_11_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
-         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
-          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_11)))
 #define AR_SREV_9287_12(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
@@ -885,22 +859,36 @@
 
 #define AR_SREV_9300(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
-#define AR_SREV_9300_20(_ah) \
-        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
-         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
 #define AR_SREV_9300_20_OR_LATER(_ah) \
-        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
-         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
-          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
+        ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
+
+#define AR_SREV_9485(_ah) \
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
+#define AR_SREV_9485_10(_ah) \
+        (AR_SREV_9485(_ah) && \
+         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
+#define AR_SREV_9485_11(_ah) \
+        (AR_SREV_9485(_ah) && \
+         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
+#define AR_SREV_9485_OR_LATER(_ah) \
+        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
+
+#define AR_SREV_9340(_ah) \
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
 
 #define AR_SREV_9285E_20(_ah) \
     (AR_SREV_9285_12_OR_LATER(_ah) && \
      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
 
+enum ath_usb_dev {
+        AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
+        AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
+        STORAGE_DEVICE = 3,
+};
+
 #define AR_DEVID_7010(_ah) \
-        (((_ah)->hw_version.devid == 0x7010) || \
-         ((_ah)->hw_version.devid == 0x7015) || \
-         ((_ah)->hw_version.devid == 0x9018))
+        (((_ah)->hw_version.usbdev == AR9280_USB) || \
+         ((_ah)->hw_version.usbdev == AR9287_USB))
 
 #define AR_RADIO_SREV_MAJOR                   0xf0
 #define AR_RAD5133_SREV_MAJOR                 0xc0
@@ -929,11 +917,11 @@
 #define AR_INTR_SPURIOUS                      0xFFFFFFFF
 
 
-#define AR_INTR_SYNC_CAUSE_CLR                0x4028
+#define AR_INTR_SYNC_CAUSE                    (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
+#define AR_INTR_SYNC_CAUSE_CLR                (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
 
-#define AR_INTR_SYNC_CAUSE                    0x4028
 
-#define AR_INTR_SYNC_ENABLE                   0x402c
+#define AR_INTR_SYNC_ENABLE                   (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
 #define AR_INTR_SYNC_ENABLE_GPIO              0xFFFC0000
 #define AR_INTR_SYNC_ENABLE_GPIO_S            18
 
@@ -973,24 +961,24 @@ enum {
 
 };
 
-#define AR_INTR_ASYNC_MASK                       0x4030
+#define AR_INTR_ASYNC_MASK                       (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
 #define AR_INTR_ASYNC_MASK_GPIO                  0xFFFC0000
 #define AR_INTR_ASYNC_MASK_GPIO_S                18
 
-#define AR_INTR_SYNC_MASK                        0x4034
+#define AR_INTR_SYNC_MASK                        (AR_SREV_9340(ah) ? 0x401c : 0x4034)
 #define AR_INTR_SYNC_MASK_GPIO                   0xFFFC0000
 #define AR_INTR_SYNC_MASK_GPIO_S                 18
 
-#define AR_INTR_ASYNC_CAUSE_CLR                  0x4038
-#define AR_INTR_ASYNC_CAUSE                      0x4038
+#define AR_INTR_ASYNC_CAUSE_CLR                  (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
+#define AR_INTR_ASYNC_CAUSE                      (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
 
-#define AR_INTR_ASYNC_ENABLE                     0x403c
+#define AR_INTR_ASYNC_ENABLE                     (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
 #define AR_INTR_ASYNC_ENABLE_GPIO                0xFFFC0000
 #define AR_INTR_ASYNC_ENABLE_GPIO_S              18
 
 #define AR_PCIE_SERDES                           0x4040
 #define AR_PCIE_SERDES2                          0x4044
-#define AR_PCIE_PM_CTRL                          0x4014
+#define AR_PCIE_PM_CTRL                          (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
 #define AR_PCIE_PM_CTRL_ENA                      0x00080000
 
 #define AR_NUM_GPIO                              14
@@ -1001,7 +989,7 @@ enum {
 #define AR9300_NUM_GPIO                          17
 #define AR7010_NUM_GPIO                          16
 
-#define AR_GPIO_IN_OUT                           0x4048
+#define AR_GPIO_IN_OUT                           (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
 #define AR_GPIO_IN_VAL                           0x0FFFC000
 #define AR_GPIO_IN_VAL_S                         14
 #define AR928X_GPIO_IN_VAL                       0x000FFC00
@@ -1012,12 +1000,15 @@ enum {
 #define AR9287_GPIO_IN_VAL_S                     11
 #define AR9271_GPIO_IN_VAL                       0xFFFF0000
 #define AR9271_GPIO_IN_VAL_S                     16
-#define AR9300_GPIO_IN_VAL                       0x0001FFFF
-#define AR9300_GPIO_IN_VAL_S                     0
 #define AR7010_GPIO_IN_VAL                       0x0000FFFF
 #define AR7010_GPIO_IN_VAL_S                     0
 
-#define AR_GPIO_OE_OUT                           (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
+#define AR_GPIO_IN                               (AR_SREV_9340(ah) ? 0x402c : 0x404c)
+#define AR9300_GPIO_IN_VAL                       0x0001FFFF
+#define AR9300_GPIO_IN_VAL_S                     0
+
+#define AR_GPIO_OE_OUT                           (AR_SREV_9340(ah) ? 0x4030 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
 #define AR_GPIO_OE_OUT_DRV                       0x3
 #define AR_GPIO_OE_OUT_DRV_NO                    0x0
 #define AR_GPIO_OE_OUT_DRV_LOW                   0x1
@@ -1039,11 +1030,13 @@ enum {
 #define AR7010_GPIO_INT_MASK                     0x52024
 #define AR7010_GPIO_FUNCTION                     0x52028
 
-#define AR_GPIO_INTR_POL                         (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
+#define AR_GPIO_INTR_POL                         (AR_SREV_9340(ah) ? 0x4038 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
 #define AR_GPIO_INTR_POL_VAL                     0x0001FFFF
 #define AR_GPIO_INTR_POL_VAL_S                   0
 
-#define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
+#define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9340(ah) ? 0x403c : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF     0x00000004
 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S       2
 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF    0x00000008
@@ -1061,13 +1054,15 @@ enum {
 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE        0x00010000
 #define AR_GPIO_JTAG_DISABLE                     0x00020000
 
-#define AR_GPIO_INPUT_MUX1                       (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
+#define AR_GPIO_INPUT_MUX1                       (AR_SREV_9340(ah) ? 0x4040 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE             0x000f0000
 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S           16
 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY           0x00000f00
 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S         8
 
-#define AR_GPIO_INPUT_MUX2                       (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
+#define AR_GPIO_INPUT_MUX2                       (AR_SREV_9340(ah) ? 0x4044 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
 #define AR_GPIO_INPUT_MUX2_CLK25                 0x0000000f
 #define AR_GPIO_INPUT_MUX2_CLK25_S               0
 #define AR_GPIO_INPUT_MUX2_RFSILENT              0x000000f0
@@ -1075,13 +1070,18 @@ enum {
 #define AR_GPIO_INPUT_MUX2_RTC_RESET             0x00000f00
 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S           8
 
-#define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
-#define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
-#define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
+#define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9340(ah) ? 0x4048 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
+#define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9340(ah) ? 0x404c : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
+#define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9340(ah) ? 0x4050 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
 
-#define AR_INPUT_STATE                           (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
+#define AR_INPUT_STATE                           (AR_SREV_9340(ah) ? 0x4054 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
 
-#define AR_EEPROM_STATUS_DATA                    (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
+#define AR_EEPROM_STATUS_DATA                    (AR_SREV_9340(ah) ? 0x40c8 : \
+                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
 #define AR_EEPROM_STATUS_DATA_VAL                0x0000ffff
 #define AR_EEPROM_STATUS_DATA_VAL_S              0
 #define AR_EEPROM_STATUS_DATA_BUSY               0x00010000
@@ -1089,17 +1089,54 @@ enum {
 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS        0x00040000
 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS      0x00080000
 
-#define AR_OBS                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
+#define AR_OBS                  (AR_SREV_9340(ah) ? 0x405c : \
+                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
 
 #define AR_GPIO_PDPU                             (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
 
-#define AR_PCIE_MSI                              (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
+#define AR_PCIE_MSI                             (AR_SREV_9340(ah) ? 0x40d8 : \
+                                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
 #define AR_PCIE_MSI_ENABLE                       0x00000001
 
-#define AR_INTR_PRIO_SYNC_ENABLE  0x40c4
-#define AR_INTR_PRIO_ASYNC_MASK   0x40c8
-#define AR_INTR_PRIO_SYNC_MASK    0x40cc
-#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
+#define AR_INTR_PRIO_SYNC_ENABLE  (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
+#define AR_INTR_PRIO_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
+#define AR_INTR_PRIO_SYNC_MASK    (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
+#define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
+#define AR_ENT_OTP                0x40d8
+#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
+#define AR_ENT_OTP_MPSD         0x00800000
+
+#define AR_CH0_BB_DPLL1          0x16180
+#define AR_CH0_BB_DPLL1_REFDIV   0xF8000000
+#define AR_CH0_BB_DPLL1_REFDIV_S 27
+#define AR_CH0_BB_DPLL1_NINI     0x07FC0000
+#define AR_CH0_BB_DPLL1_NINI_S   18
+#define AR_CH0_BB_DPLL1_NFRAC    0x0003FFFF
+#define AR_CH0_BB_DPLL1_NFRAC_S  0
+
+#define AR_CH0_BB_DPLL2              0x16184
+#define AR_CH0_BB_DPLL2_LOCAL_PLL       0x40000000
+#define AR_CH0_BB_DPLL2_LOCAL_PLL_S     30
+#define AR_CH0_DPLL2_KI              0x3C000000
+#define AR_CH0_DPLL2_KI_S            26
+#define AR_CH0_DPLL2_KD              0x03F80000
+#define AR_CH0_DPLL2_KD_S            19
+#define AR_CH0_BB_DPLL2_EN_NEGTRIG   0x00040000
+#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
+#define AR_CH0_BB_DPLL2_PLL_PWD      0x00010000
+#define AR_CH0_BB_DPLL2_PLL_PWD_S    16
+#define AR_CH0_BB_DPLL2_OUTDIV       0x0000E000
+#define AR_CH0_BB_DPLL2_OUTDIV_S     13
+
+#define AR_CH0_BB_DPLL3          0x16188
+#define AR_CH0_BB_DPLL3_PHASE_SHIFT     0x3F800000
+#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S   23
+
+#define AR_CH0_DDR_DPLL2         0x16244
+#define AR_CH0_DDR_DPLL3         0x16248
+#define AR_CH0_DPLL3_PHASE_SHIFT     0x3F800000
+#define AR_CH0_DPLL3_PHASE_SHIFT_S   23
+#define AR_PHY_CCA_NOM_VAL_2GHZ      -118
 
 #define AR_RTC_9300_PLL_DIV          0x000003ff
 #define AR_RTC_9300_PLL_DIV_S        0
@@ -1137,12 +1174,21 @@ enum {
 #define AR_RTC_PLL_CONTROL \
         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
 
+#define AR_RTC_PLL_CONTROL2     0x703c
+
 #define AR_RTC_PLL_DIV          0x0000001f
 #define AR_RTC_PLL_DIV_S        0
 #define AR_RTC_PLL_DIV2         0x00000020
 #define AR_RTC_PLL_REFDIV_5     0x000000c0
 #define AR_RTC_PLL_CLKSEL       0x00000300
 #define AR_RTC_PLL_CLKSEL_S     8
+#define AR_RTC_PLL_BYPASS       0x00010000
+
+#define PLL3 0x16188
+#define PLL3_DO_MEAS_MASK 0x40000000
+#define PLL4 0x1618c
+#define PLL4_MEAS_DONE    0x8
+#define SQSUM_DVC_MASK 0x007ffff8
 
 #define AR_RTC_RESET \
         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
@@ -1183,7 +1229,8 @@ enum {
 
 /* RTC_DERIVED_* - only for AR9100 */
 
-#define AR_RTC_DERIVED_CLK           (AR_RTC_BASE + 0x0038)
+#define AR_RTC_DERIVED_CLK \
+        (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
 #define AR_RTC_DERIVED_CLK_PERIOD    0x0000fffe
 #define AR_RTC_DERIVED_CLK_PERIOD_S  1
 
@@ -1389,6 +1436,7 @@ enum {
 #define AR_STA_ID1_PCF             0x00100000
 #define AR_STA_ID1_USE_DEFANT      0x00200000
 #define AR_STA_ID1_DEFANT_UPDATE   0x00400000
+#define AR_STA_ID1_AR9100_BA_FIX   0x00400000
 #define AR_STA_ID1_RTS_USE_DEF     0x00800000
 #define AR_STA_ID1_ACKCTS_6MB      0x01000000
 #define AR_STA_ID1_BASE_RATE_11B   0x02000000
@@ -1550,11 +1598,6 @@ enum {
 #define AR_TPC_CHIRP           0x003f0000
 #define AR_TPC_CHIRP_S         0x16
 
-#define AR_TFCNT           0x80ec
-#define AR_RFCNT           0x80f0
-#define AR_RCCNT           0x80f4
-#define AR_CCCNT           0x80f8
-
 #define AR_QUIET1          0x80fc
 #define AR_QUIET1_NEXT_QUIET_S         0
 #define AR_QUIET1_NEXT_QUIET_M         0x0000ffff
@@ -1605,6 +1648,7 @@ enum {
 #define AR_PCU_TBTT_PROTECT        0x00200000
 #define AR_PCU_CLEAR_VMF           0x01000000
 #define AR_PCU_CLEAR_BA_VALID      0x04000000
+#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
 
 #define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
 #define AR_PCU_BT_ANT_PREVENT_RX_S 20
@@ -1665,6 +1709,22 @@ enum {
 #define AR_BTCOEX_WL_WGHT          0xffff0000
 #define AR_BTCOEX_WL_WGHT_S        16
 
+#define AR_BT_COEX_WL_WEIGHTS0     0x8174
+#define AR_BT_COEX_WL_WEIGHTS1     0x81c4
+
+#define AR_BT_COEX_BT_WEIGHTS0     0x83ac
+#define AR_BT_COEX_BT_WEIGHTS1     0x83b0
+#define AR_BT_COEX_BT_WEIGHTS2     0x83b4
+#define AR_BT_COEX_BT_WEIGHTS3     0x83b8
+
+#define AR9300_BT_WGHT                     0xcccc4444
+#define AR9300_STOMP_ALL_WLAN_WGHT0        0xfffffff0
+#define AR9300_STOMP_ALL_WLAN_WGHT1        0xfffffff0
+#define AR9300_STOMP_LOW_WLAN_WGHT0        0x88888880
+#define AR9300_STOMP_LOW_WLAN_WGHT1        0x88888880
+#define AR9300_STOMP_NONE_WLAN_WGHT0       0x00000000
+#define AR9300_STOMP_NONE_WLAN_WGHT1       0x00000000
+
 #define AR_BT_COEX_MODE2           0x817c
 #define AR_BT_BCN_MISS_THRESH      0x000000ff
 #define AR_BT_BCN_MISS_THRESH_S    0
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
deleted file mode 100644
index fd20241f57d8..000000000000
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ /dev/null
@@ -1,752 +0,0 @@
-/*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/slab.h>
-
-#include "ath9k.h"
-
-struct ath9k_vif_iter_data {
-        int count;
-        u8 *addr;
-};
-
-static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
-{
-        struct ath9k_vif_iter_data *iter_data = data;
-        u8 *nbuf;
-
-        nbuf = krealloc(iter_data->addr, (iter_data->count + 1) * ETH_ALEN,
-                        GFP_ATOMIC);
-        if (nbuf == NULL)
-                return;
-
-        memcpy(nbuf + iter_data->count * ETH_ALEN, mac, ETH_ALEN);
-        iter_data->addr = nbuf;
-        iter_data->count++;
-}
-
-void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
-{
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath9k_vif_iter_data iter_data;
-        int i, j;
-        u8 mask[ETH_ALEN];
-
-        /*
-         * Add primary MAC address even if it is not in active use since it
-         * will be configured to the hardware as the starting point and the
-         * BSSID mask will need to be changed if another address is active.
-         */
-        iter_data.addr = kmalloc(ETH_ALEN, GFP_ATOMIC);
-        if (iter_data.addr) {
-                memcpy(iter_data.addr, common->macaddr, ETH_ALEN);
-                iter_data.count = 1;
-        } else
-                iter_data.count = 0;
-
-        /* Get list of all active MAC addresses */
-        spin_lock_bh(&sc->wiphy_lock);
-        ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
-                                                   &iter_data);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] == NULL)
-                        continue;
-                ieee80211_iterate_active_interfaces_atomic(
-                        sc->sec_wiphy[i]->hw, ath9k_vif_iter, &iter_data);
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        /* Generate an address mask to cover all active addresses */
-        memset(mask, 0, ETH_ALEN);
-        for (i = 0; i < iter_data.count; i++) {
-                u8 *a1 = iter_data.addr + i * ETH_ALEN;
-                for (j = i + 1; j < iter_data.count; j++) {
-                        u8 *a2 = iter_data.addr + j * ETH_ALEN;
-                        mask[0] |= a1[0] ^ a2[0];
-                        mask[1] |= a1[1] ^ a2[1];
-                        mask[2] |= a1[2] ^ a2[2];
-                        mask[3] |= a1[3] ^ a2[3];
-                        mask[4] |= a1[4] ^ a2[4];
-                        mask[5] |= a1[5] ^ a2[5];
-                }
-        }
-
-        kfree(iter_data.addr);
-
-        /* Invert the mask and configure hardware */
-        common->bssidmask[0] = ~mask[0];
-        common->bssidmask[1] = ~mask[1];
-        common->bssidmask[2] = ~mask[2];
-        common->bssidmask[3] = ~mask[3];
-        common->bssidmask[4] = ~mask[4];
-        common->bssidmask[5] = ~mask[5];
-
-        ath_hw_setbssidmask(common);
-}
-
-int ath9k_wiphy_add(struct ath_softc *sc)
-{
-        int i, error;
-        struct ath_wiphy *aphy;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ieee80211_hw *hw;
-        u8 addr[ETH_ALEN];
-
-        hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy), &ath9k_ops);
-        if (hw == NULL)
-                return -ENOMEM;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] == NULL)
-                        break;
-        }
-
-        if (i == sc->num_sec_wiphy) {
-                /* No empty slot available; increase array length */
-                struct ath_wiphy **n;
-                n = krealloc(sc->sec_wiphy,
-                             (sc->num_sec_wiphy + 1) *
-                             sizeof(struct ath_wiphy *),
-                             GFP_ATOMIC);
-                if (n == NULL) {
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        ieee80211_free_hw(hw);
-                        return -ENOMEM;
-                }
-                n[i] = NULL;
-                sc->sec_wiphy = n;
-                sc->num_sec_wiphy++;
-        }
-
-        SET_IEEE80211_DEV(hw, sc->dev);
-
-        aphy = hw->priv;
-        aphy->sc = sc;
-        aphy->hw = hw;
-        sc->sec_wiphy[i] = aphy;
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        memcpy(addr, common->macaddr, ETH_ALEN);
-        addr[0] |= 0x02; /* Locally managed address */
-        /*
-         * XOR virtual wiphy index into the least significant bits to generate
-         * a different MAC address for each virtual wiphy.
-         */
-        addr[5] ^= i & 0xff;
-        addr[4] ^= (i & 0xff00) >> 8;
-        addr[3] ^= (i & 0xff0000) >> 16;
-
-        SET_IEEE80211_PERM_ADDR(hw, addr);
-
-        ath9k_set_hw_capab(sc, hw);
-
-        error = ieee80211_register_hw(hw);
-
-        if (error == 0) {
-                /* Make sure wiphy scheduler is started (if enabled) */
-                ath9k_wiphy_set_scheduler(sc, sc->wiphy_scheduler_int);
-        }
-
-        return error;
-}
-
-int ath9k_wiphy_del(struct ath_wiphy *aphy)
-{
-        struct ath_softc *sc = aphy->sc;
-        int i;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (aphy == sc->sec_wiphy[i]) {
-                        sc->sec_wiphy[i] = NULL;
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        ieee80211_unregister_hw(aphy->hw);
-                        ieee80211_free_hw(aphy->hw);
-                        return 0;
-                }
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-        return -ENOENT;
-}
-
-static int ath9k_send_nullfunc(struct ath_wiphy *aphy,
-                               struct ieee80211_vif *vif, const u8 *bssid,
-                               int ps)
-{
-        struct ath_softc *sc = aphy->sc;
-        struct ath_tx_control txctl;
-        struct sk_buff *skb;
-        struct ieee80211_hdr *hdr;
-        __le16 fc;
-        struct ieee80211_tx_info *info;
-
-        skb = dev_alloc_skb(24);
-        if (skb == NULL)
-                return -ENOMEM;
-        hdr = (struct ieee80211_hdr *) skb_put(skb, 24);
-        memset(hdr, 0, 24);
-        fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC |
-                         IEEE80211_FCTL_TODS);
-        if (ps)
-                fc |= cpu_to_le16(IEEE80211_FCTL_PM);
-        hdr->frame_control = fc;
-        memcpy(hdr->addr1, bssid, ETH_ALEN);
-        memcpy(hdr->addr2, aphy->hw->wiphy->perm_addr, ETH_ALEN);
-        memcpy(hdr->addr3, bssid, ETH_ALEN);
-
-        info = IEEE80211_SKB_CB(skb);
-        memset(info, 0, sizeof(*info));
-        info->flags = IEEE80211_TX_CTL_REQ_TX_STATUS;
-        info->control.vif = vif;
-        info->control.rates[0].idx = 0;
-        info->control.rates[0].count = 4;
-        info->control.rates[1].idx = -1;
-
-        memset(&txctl, 0, sizeof(struct ath_tx_control));
-        txctl.txq = &sc->tx.txq[sc->tx.hwq_map[WME_AC_VO]];
-        txctl.frame_type = ps ? ATH9K_IFT_PAUSE : ATH9K_IFT_UNPAUSE;
-
-        if (ath_tx_start(aphy->hw, skb, &txctl) != 0)
-                goto exit;
-
-        return 0;
-exit:
-        dev_kfree_skb_any(skb);
-        return -1;
-}
-
-static bool __ath9k_wiphy_pausing(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state == ATH_WIPHY_PAUSING)
-                return true;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_PAUSING)
-                        return true;
-        }
-        return false;
-}
-
-static bool ath9k_wiphy_pausing(struct ath_softc *sc)
-{
-        bool ret;
-        spin_lock_bh(&sc->wiphy_lock);
-        ret = __ath9k_wiphy_pausing(sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-        return ret;
-}
-
-static bool __ath9k_wiphy_scanning(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state == ATH_WIPHY_SCAN)
-                return true;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_SCAN)
-                        return true;
-        }
-        return false;
-}
-
-bool ath9k_wiphy_scanning(struct ath_softc *sc)
-{
-        bool ret;
-        spin_lock_bh(&sc->wiphy_lock);
-        ret = __ath9k_wiphy_scanning(sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-        return ret;
-}
-
-static int __ath9k_wiphy_unpause(struct ath_wiphy *aphy);
-
-/* caller must hold wiphy_lock */
-static void __ath9k_wiphy_unpause_ch(struct ath_wiphy *aphy)
-{
-        if (aphy == NULL)
-                return;
-        if (aphy->chan_idx != aphy->sc->chan_idx)
-                return; /* wiphy not on the selected channel */
-        __ath9k_wiphy_unpause(aphy);
-}
-
-static void ath9k_wiphy_unpause_channel(struct ath_softc *sc)
-{
-        int i;
-        spin_lock_bh(&sc->wiphy_lock);
-        __ath9k_wiphy_unpause_ch(sc->pri_wiphy);
-        for (i = 0; i < sc->num_sec_wiphy; i++)
-                __ath9k_wiphy_unpause_ch(sc->sec_wiphy[i]);
-        spin_unlock_bh(&sc->wiphy_lock);
-}
-
-void ath9k_wiphy_chan_work(struct work_struct *work)
-{
-        struct ath_softc *sc = container_of(work, struct ath_softc, chan_work);
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_wiphy *aphy = sc->next_wiphy;
-
-        if (aphy == NULL)
-                return;
-
-        /*
-         * All pending interfaces paused; ready to change
-         * channels.
-         */
-
-        /* Change channels */
-        mutex_lock(&sc->mutex);
-        /* XXX: remove me eventually */
-        ath9k_update_ichannel(sc, aphy->hw,
-                              &sc->sc_ah->channels[sc->chan_idx]);
-
-        /* sync hw configuration for hw code */
-        common->hw = aphy->hw;
-
-        ath_update_chainmask(sc, sc->chan_is_ht);
-        if (ath_set_channel(sc, aphy->hw,
-                            &sc->sc_ah->channels[sc->chan_idx]) < 0) {
-                printk(KERN_DEBUG "ath9k: Failed to set channel for new "
-                       "virtual wiphy\n");
-                mutex_unlock(&sc->mutex);
-                return;
-        }
-        mutex_unlock(&sc->mutex);
-
-        ath9k_wiphy_unpause_channel(sc);
-}
-
-/*
- * ath9k version of ieee80211_tx_status() for TX frames that are generated
- * internally in the driver.
- */
-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
-        struct ath_wiphy *aphy = hw->priv;
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-
-        if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
-            aphy->state == ATH_WIPHY_PAUSING) {
-                if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
-                        printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
-                               "frame\n", wiphy_name(hw->wiphy));
-                        /*
-                         * The AP did not reply; ignore this to allow us to
-                         * continue.
-                         */
-                }
-                aphy->state = ATH_WIPHY_PAUSED;
-                if (!ath9k_wiphy_pausing(aphy->sc)) {
-                        /*
-                         * Drop from tasklet to work to allow mutex for channel
-                         * change.
-                         */
-                        ieee80211_queue_work(aphy->sc->hw,
-                                   &aphy->sc->chan_work);
-                }
-        }
-
-        dev_kfree_skb(skb);
-}
-
-static void ath9k_mark_paused(struct ath_wiphy *aphy)
-{
-        struct ath_softc *sc = aphy->sc;
-        aphy->state = ATH_WIPHY_PAUSED;
-        if (!__ath9k_wiphy_pausing(sc))
-                ieee80211_queue_work(sc->hw, &sc->chan_work);
-}
-
-static void ath9k_pause_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
-{
-        struct ath_wiphy *aphy = data;
-        struct ath_vif *avp = (void *) vif->drv_priv;
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_STATION:
-                if (!vif->bss_conf.assoc) {
-                        ath9k_mark_paused(aphy);
-                        break;
-                }
-                /* TODO: could avoid this if already in PS mode */
-                if (ath9k_send_nullfunc(aphy, vif, avp->bssid, 1)) {
-                        printk(KERN_DEBUG "%s: failed to send PS nullfunc\n",
-                               __func__);
-                        ath9k_mark_paused(aphy);
-                }
-                break;
-        case NL80211_IFTYPE_AP:
-                /* Beacon transmission is paused by aphy->state change */
-                ath9k_mark_paused(aphy);
-                break;
-        default:
-                break;
-        }
-}
-
-/* caller must hold wiphy_lock */
-static int __ath9k_wiphy_pause(struct ath_wiphy *aphy)
-{
-        ieee80211_stop_queues(aphy->hw);
-        aphy->state = ATH_WIPHY_PAUSING;
-        /*
-         * TODO: handle PAUSING->PAUSED for the case where there are multiple
-         * active vifs (now we do it on the first vif getting ready; should be
-         * on the last)
-         */
-        ieee80211_iterate_active_interfaces_atomic(aphy->hw, ath9k_pause_iter,
-                                                   aphy);
-        return 0;
-}
-
-int ath9k_wiphy_pause(struct ath_wiphy *aphy)
-{
-        int ret;
-        spin_lock_bh(&aphy->sc->wiphy_lock);
-        ret = __ath9k_wiphy_pause(aphy);
-        spin_unlock_bh(&aphy->sc->wiphy_lock);
-        return ret;
-}
-
-static void ath9k_unpause_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
-{
-        struct ath_wiphy *aphy = data;
-        struct ath_vif *avp = (void *) vif->drv_priv;
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_STATION:
-                if (!vif->bss_conf.assoc)
-                        break;
-                ath9k_send_nullfunc(aphy, vif, avp->bssid, 0);
-                break;
-        case NL80211_IFTYPE_AP:
-                /* Beacon transmission is re-enabled by aphy->state change */
-                break;
-        default:
-                break;
-        }
-}
-
-/* caller must hold wiphy_lock */
-static int __ath9k_wiphy_unpause(struct ath_wiphy *aphy)
-{
-        ieee80211_iterate_active_interfaces_atomic(aphy->hw,
-                                                   ath9k_unpause_iter, aphy);
-        aphy->state = ATH_WIPHY_ACTIVE;
-        ieee80211_wake_queues(aphy->hw);
-        return 0;
-}
-
-int ath9k_wiphy_unpause(struct ath_wiphy *aphy)
-{
-        int ret;
-        spin_lock_bh(&aphy->sc->wiphy_lock);
-        ret = __ath9k_wiphy_unpause(aphy);
-        spin_unlock_bh(&aphy->sc->wiphy_lock);
-        return ret;
-}
-
-static void __ath9k_wiphy_mark_all_paused(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state != ATH_WIPHY_INACTIVE)
-                sc->pri_wiphy->state = ATH_WIPHY_PAUSED;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state != ATH_WIPHY_INACTIVE)
-                        sc->sec_wiphy[i]->state = ATH_WIPHY_PAUSED;
-        }
-}
-
-/* caller must hold wiphy_lock */
-static void __ath9k_wiphy_pause_all(struct ath_softc *sc)
-{
-        int i;
-        if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE)
-                __ath9k_wiphy_pause(sc->pri_wiphy);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_ACTIVE)
-                        __ath9k_wiphy_pause(sc->sec_wiphy[i]);
-        }
-}
-
-int ath9k_wiphy_select(struct ath_wiphy *aphy)
-{
-        struct ath_softc *sc = aphy->sc;
-        bool now;
-
-        spin_lock_bh(&sc->wiphy_lock);
-        if (__ath9k_wiphy_scanning(sc)) {
-                /*
-                 * For now, we are using mac80211 sw scan and it expects to
-                 * have full control over channel changes, so avoid wiphy
-                 * scheduling during a scan. This could be optimized if the
-                 * scanning control were moved into the driver.
-                 */
-                spin_unlock_bh(&sc->wiphy_lock);
-                return -EBUSY;
-        }
-        if (__ath9k_wiphy_pausing(sc)) {
-                if (sc->wiphy_select_failures == 0)
-                        sc->wiphy_select_first_fail = jiffies;
-                sc->wiphy_select_failures++;
-                if (time_after(jiffies, sc->wiphy_select_first_fail + HZ / 2))
-                {
-                        printk(KERN_DEBUG "ath9k: Previous wiphy select timed "
-                               "out; disable/enable hw to recover\n");
-                        __ath9k_wiphy_mark_all_paused(sc);
-                        /*
-                         * TODO: this workaround to fix hardware is unlikely to
-                         * be specific to virtual wiphy changes. It can happen
-                         * on normal channel change, too, and as such, this
-                         * should really be made more generic. For example,
-                         * tricker radio disable/enable on GTT interrupt burst
-                         * (say, 10 GTT interrupts received without any TX
-                         * frame being completed)
-                         */
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        ath_radio_disable(sc, aphy->hw);
-                        ath_radio_enable(sc, aphy->hw);
-                        /* Only the primary wiphy hw is used for queuing work */
-                        ieee80211_queue_work(aphy->sc->hw,
-                                   &aphy->sc->chan_work);
-                        return -EBUSY; /* previous select still in progress */
-                }
-                spin_unlock_bh(&sc->wiphy_lock);
-                return -EBUSY; /* previous select still in progress */
-        }
-        sc->wiphy_select_failures = 0;
-
-        /* Store the new channel */
-        sc->chan_idx = aphy->chan_idx;
-        sc->chan_is_ht = aphy->chan_is_ht;
-        sc->next_wiphy = aphy;
-
-        __ath9k_wiphy_pause_all(sc);
-        now = !__ath9k_wiphy_pausing(aphy->sc);
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        if (now) {
-                /* Ready to request channel change immediately */
-                ieee80211_queue_work(aphy->sc->hw, &aphy->sc->chan_work);
-        }
-
-        /*
-         * wiphys will be unpaused in ath9k_tx_status() once channel has been
-         * changed if any wiphy needs time to become paused.
-         */
-
-        return 0;
-}
-
-bool ath9k_wiphy_started(struct ath_softc *sc)
-{
-        int i;
-        spin_lock_bh(&sc->wiphy_lock);
-        if (sc->pri_wiphy->state != ATH_WIPHY_INACTIVE) {
-                spin_unlock_bh(&sc->wiphy_lock);
-                return true;
-        }
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state != ATH_WIPHY_INACTIVE) {
-                        spin_unlock_bh(&sc->wiphy_lock);
-                        return true;
-                }
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-        return false;
-}
-
-static void ath9k_wiphy_pause_chan(struct ath_wiphy *aphy,
-                                   struct ath_wiphy *selected)
-{
-        if (selected->state == ATH_WIPHY_SCAN) {
-                if (aphy == selected)
-                        return;
-                /*
-                 * Pause all other wiphys for the duration of the scan even if
-                 * they are on the current channel now.
-                 */
-        } else if (aphy->chan_idx == selected->chan_idx)
-                return;
-        aphy->state = ATH_WIPHY_PAUSED;
-        ieee80211_stop_queues(aphy->hw);
-}
-
-void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
-                                  struct ath_wiphy *selected)
-{
-        int i;
-        spin_lock_bh(&sc->wiphy_lock);
-        if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE)
-                ath9k_wiphy_pause_chan(sc->pri_wiphy, selected);
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                if (sc->sec_wiphy[i] &&
-                    sc->sec_wiphy[i]->state == ATH_WIPHY_ACTIVE)
-                        ath9k_wiphy_pause_chan(sc->sec_wiphy[i], selected);
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-}
-
-void ath9k_wiphy_work(struct work_struct *work)
-{
-        struct ath_softc *sc = container_of(work, struct ath_softc,
-                                            wiphy_work.work);
-        struct ath_wiphy *aphy = NULL;
-        bool first = true;
-
-        spin_lock_bh(&sc->wiphy_lock);
-
-        if (sc->wiphy_scheduler_int == 0) {
-                /* wiphy scheduler is disabled */
-                spin_unlock_bh(&sc->wiphy_lock);
-                return;
-        }
-
-try_again:
-        sc->wiphy_scheduler_index++;
-        while (sc->wiphy_scheduler_index <= sc->num_sec_wiphy) {
-                aphy = sc->sec_wiphy[sc->wiphy_scheduler_index - 1];
-                if (aphy && aphy->state != ATH_WIPHY_INACTIVE)
-                        break;
-
-                sc->wiphy_scheduler_index++;
-                aphy = NULL;
-        }
-        if (aphy == NULL) {
-                sc->wiphy_scheduler_index = 0;
-                if (sc->pri_wiphy->state == ATH_WIPHY_INACTIVE) {
-                        if (first) {
-                                first = false;
-                                goto try_again;
-                        }
-                        /* No wiphy is ready to be scheduled */
-                } else
-                        aphy = sc->pri_wiphy;
-        }
-
-        spin_unlock_bh(&sc->wiphy_lock);
-
-        if (aphy &&
-            aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN &&
-            ath9k_wiphy_select(aphy)) {
-                printk(KERN_DEBUG "ath9k: Failed to schedule virtual wiphy "
-                       "change\n");
-        }
-
-        ieee80211_queue_delayed_work(sc->hw,
-                                     &sc->wiphy_work,
-                                     sc->wiphy_scheduler_int);
-}
-
-void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int)
-{
-        cancel_delayed_work_sync(&sc->wiphy_work);
-        sc->wiphy_scheduler_int = msecs_to_jiffies(msec_int);
-        if (sc->wiphy_scheduler_int)
-                ieee80211_queue_delayed_work(sc->hw, &sc->wiphy_work,
-                                             sc->wiphy_scheduler_int);
-}
-
-/* caller must hold wiphy_lock */
-bool ath9k_all_wiphys_idle(struct ath_softc *sc)
-{
-        unsigned int i;
-        if (!sc->pri_wiphy->idle)
-                return false;
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (!aphy)
-                        continue;
-                if (!aphy->idle)
-                        return false;
-        }
-        return true;
-}
-
-/* caller must hold wiphy_lock */
-void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle)
-{
-        struct ath_softc *sc = aphy->sc;
-
-        aphy->idle = idle;
-        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                  "Marking %s as %s\n",
-                  wiphy_name(aphy->hw->wiphy),
-                  idle ? "idle" : "not-idle");
-}
-/* Only bother starting a queue on an active virtual wiphy */
-bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue)
-{
-        struct ieee80211_hw *hw = sc->pri_wiphy->hw;
-        unsigned int i;
-        bool txq_started = false;
-
-        spin_lock_bh(&sc->wiphy_lock);
-
-        /* Start the primary wiphy */
-        if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE) {
-                ieee80211_wake_queue(hw, skb_queue);
-                txq_started = true;
-                goto unlock;
-        }
-
-        /* Now start the secondary wiphy queues */
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (!aphy)
-                        continue;
-                if (aphy->state != ATH_WIPHY_ACTIVE)
-                        continue;
-
-                hw = aphy->hw;
-                ieee80211_wake_queue(hw, skb_queue);
-                txq_started = true;
-                break;
-        }
-
-unlock:
-        spin_unlock_bh(&sc->wiphy_lock);
-        return txq_started;
-}
-
-/* Go ahead and propagate information to all virtual wiphys, it won't hurt */
-void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue)
-{
-        struct ieee80211_hw *hw = sc->pri_wiphy->hw;
-        unsigned int i;
-
-        spin_lock_bh(&sc->wiphy_lock);
-
-        /* Stop the primary wiphy */
-        ieee80211_stop_queue(hw, skb_queue);
-
-        /* Now stop the secondary wiphy queues */
-        for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (!aphy)
-                        continue;
-                hw = aphy->hw;
-                ieee80211_stop_queue(hw, skb_queue);
-        }
-        spin_unlock_bh(&sc->wiphy_lock);
-}
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c
index 6260faa658a2..35422fc1f2ce 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.c
+++ b/drivers/net/wireless/ath/ath9k/wmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -23,20 +23,18 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_ECHO_CMDID";
         case WMI_ACCESS_MEMORY_CMDID:
                 return "WMI_ACCESS_MEMORY_CMDID";
+        case WMI_GET_FW_VERSION:
+                return "WMI_GET_FW_VERSION";
         case WMI_DISABLE_INTR_CMDID:
                 return "WMI_DISABLE_INTR_CMDID";
         case WMI_ENABLE_INTR_CMDID:
                 return "WMI_ENABLE_INTR_CMDID";
-        case WMI_RX_LINK_CMDID:
-                return "WMI_RX_LINK_CMDID";
         case WMI_ATH_INIT_CMDID:
                 return "WMI_ATH_INIT_CMDID";
         case WMI_ABORT_TXQ_CMDID:
                 return "WMI_ABORT_TXQ_CMDID";
         case WMI_STOP_TX_DMA_CMDID:
                 return "WMI_STOP_TX_DMA_CMDID";
-        case WMI_STOP_DMA_RECV_CMDID:
-                return "WMI_STOP_DMA_RECV_CMDID";
         case WMI_ABORT_TX_DMA_CMDID:
                 return "WMI_ABORT_TX_DMA_CMDID";
         case WMI_DRAIN_TXQ_CMDID:
@@ -51,8 +49,6 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_FLUSH_RECV_CMDID";
         case WMI_SET_MODE_CMDID:
                 return "WMI_SET_MODE_CMDID";
-        case WMI_RESET_CMDID:
-                return "WMI_RESET_CMDID";
         case WMI_NODE_CREATE_CMDID:
                 return "WMI_NODE_CREATE_CMDID";
         case WMI_NODE_REMOVE_CMDID:
@@ -61,8 +57,6 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_VAP_REMOVE_CMDID";
         case WMI_VAP_CREATE_CMDID:
                 return "WMI_VAP_CREATE_CMDID";
-        case WMI_BEACON_UPDATE_CMDID:
-                return "WMI_BEACON_UPDATE_CMDID";
         case WMI_REG_READ_CMDID:
                 return "WMI_REG_READ_CMDID";
         case WMI_REG_WRITE_CMDID:
@@ -71,20 +65,22 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
                 return "WMI_RC_STATE_CHANGE_CMDID";
         case WMI_RC_RATE_UPDATE_CMDID:
                 return "WMI_RC_RATE_UPDATE_CMDID";
-        case WMI_DEBUG_INFO_CMDID:
-                return "WMI_DEBUG_INFO_CMDID";
-        case WMI_HOST_ATTACH:
-                return "WMI_HOST_ATTACH";
         case WMI_TARGET_IC_UPDATE_CMDID:
                 return "WMI_TARGET_IC_UPDATE_CMDID";
-        case WMI_TGT_STATS_CMDID:
-                return "WMI_TGT_STATS_CMDID";
         case WMI_TX_AGGR_ENABLE_CMDID:
                 return "WMI_TX_AGGR_ENABLE_CMDID";
         case WMI_TGT_DETACH_CMDID:
                 return "WMI_TGT_DETACH_CMDID";
-        case WMI_TGT_TXQ_ENABLE_CMDID:
-                return "WMI_TGT_TXQ_ENABLE_CMDID";
+        case WMI_NODE_UPDATE_CMDID:
+                return "WMI_NODE_UPDATE_CMDID";
+        case WMI_INT_STATS_CMDID:
+                return "WMI_INT_STATS_CMDID";
+        case WMI_TX_STATS_CMDID:
+                return "WMI_TX_STATS_CMDID";
+        case WMI_RX_STATS_CMDID:
+                return "WMI_RX_STATS_CMDID";
+        case WMI_BITRATE_MASK_CMDID:
+                return "WMI_BITRATE_MASK_CMDID";
         }
 
         return "Bogus";
@@ -100,9 +96,15 @@ struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv)
 
         wmi->drv_priv = priv;
         wmi->stopped = false;
+        skb_queue_head_init(&wmi->wmi_event_queue);
+        spin_lock_init(&wmi->wmi_lock);
+        spin_lock_init(&wmi->event_lock);
         mutex_init(&wmi->op_mutex);
         mutex_init(&wmi->multi_write_mutex);
         init_completion(&wmi->cmd_wait);
+        INIT_LIST_HEAD(&wmi->pending_tx_events);
+        tasklet_init(&wmi->wmi_event_tasklet, ath9k_wmi_event_tasklet,
+                     (unsigned long)wmi);
 
         return wmi;
 }
@@ -118,59 +120,75 @@ void ath9k_deinit_wmi(struct ath9k_htc_priv *priv)
         kfree(priv->wmi);
 }
 
-void ath9k_wmi_tasklet(unsigned long data)
+void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv)
 {
-        struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
-        struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct wmi_cmd_hdr *hdr;
-        struct wmi_swba *swba_hdr;
-        enum wmi_event_id event;
-        struct sk_buff *skb;
-        void *wmi_event;
         unsigned long flags;
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-        __be32 txrate;
-#endif
 
+        tasklet_kill(&priv->wmi->wmi_event_tasklet);
         spin_lock_irqsave(&priv->wmi->wmi_lock, flags);
-        skb = priv->wmi->wmi_skb;
+        __skb_queue_purge(&priv->wmi->wmi_event_queue);
         spin_unlock_irqrestore(&priv->wmi->wmi_lock, flags);
+}
 
-        hdr = (struct wmi_cmd_hdr *) skb->data;
-        event = be16_to_cpu(hdr->command_id);
-        wmi_event = skb_pull(skb, sizeof(struct wmi_cmd_hdr));
-
-        ath_print(common, ATH_DBG_WMI,
-                  "WMI Event: 0x%x\n", event);
-
-        switch (event) {
-        case WMI_TGT_RDY_EVENTID:
-                break;
-        case WMI_SWBA_EVENTID:
-                swba_hdr = (struct wmi_swba *) wmi_event;
-                ath9k_htc_swba(priv, swba_hdr->beacon_pending);
-                break;
-        case WMI_FATAL_EVENTID:
-                break;
-        case WMI_TXTO_EVENTID:
-                break;
-        case WMI_BMISS_EVENTID:
-                break;
-        case WMI_WLAN_TXCOMP_EVENTID:
-                break;
-        case WMI_DELBA_EVENTID:
-                break;
-        case WMI_TXRATE_EVENTID:
-#ifdef CONFIG_ATH9K_HTC_DEBUGFS
-                txrate = ((struct wmi_event_txrate *)wmi_event)->txrate;
-                priv->debug.txrate = be32_to_cpu(txrate);
-#endif
-                break;
-        default:
-                break;
-        }
+void ath9k_wmi_event_tasklet(unsigned long data)
+{
+        struct wmi *wmi = (struct wmi *)data;
+        struct ath9k_htc_priv *priv = wmi->drv_priv;
+        struct wmi_cmd_hdr *hdr;
+        void *wmi_event;
+        struct wmi_event_swba *swba;
+        struct sk_buff *skb = NULL;
+        unsigned long flags;
+        u16 cmd_id;
 
-        kfree_skb(skb);
+        do {
+                spin_lock_irqsave(&wmi->wmi_lock, flags);
+                skb = __skb_dequeue(&wmi->wmi_event_queue);
+                if (!skb) {
+                        spin_unlock_irqrestore(&wmi->wmi_lock, flags);
+                        return;
+                }
+                spin_unlock_irqrestore(&wmi->wmi_lock, flags);
+
+                hdr = (struct wmi_cmd_hdr *) skb->data;
+                cmd_id = be16_to_cpu(hdr->command_id);
+                wmi_event = skb_pull(skb, sizeof(struct wmi_cmd_hdr));
+
+                switch (cmd_id) {
+                case WMI_SWBA_EVENTID:
+                        swba = (struct wmi_event_swba *) wmi_event;
+                        ath9k_htc_swba(priv, swba);
+                        break;
+                case WMI_FATAL_EVENTID:
+                        ieee80211_queue_work(wmi->drv_priv->hw,
+                                             &wmi->drv_priv->fatal_work);
+                        break;
+                case WMI_TXSTATUS_EVENTID:
+                        spin_lock_bh(&priv->tx.tx_lock);
+                        if (priv->tx.flags & ATH9K_HTC_OP_TX_DRAIN) {
+                                spin_unlock_bh(&priv->tx.tx_lock);
+                                break;
+                        }
+                        spin_unlock_bh(&priv->tx.tx_lock);
+
+                        ath9k_htc_txstatus(priv, wmi_event);
+                        break;
+                default:
+                        break;
+                }
+
+                kfree_skb(skb);
+        } while (1);
+}
+
+void ath9k_fatal_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   fatal_work);
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+
+        ath_dbg(common, ATH_DBG_FATAL, "FATAL Event received, resetting device\n");
+        ath9k_htc_reset(priv);
 }
 
 static void ath9k_wmi_rsp_callback(struct wmi *wmi, struct sk_buff *skb)
@@ -198,9 +216,9 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb,
 
         if (cmd_id & 0x1000) {
                 spin_lock(&wmi->wmi_lock);
-                wmi->wmi_skb = skb;
+                __skb_queue_tail(&wmi->wmi_event_queue, skb);
                 spin_unlock(&wmi->wmi_lock);
-                tasklet_schedule(&wmi->drv_priv->wmi_tasklet);
+                tasklet_schedule(&wmi->wmi_event_tasklet);
                 return;
         }
 
@@ -259,7 +277,7 @@ static int ath9k_wmi_cmd_issue(struct wmi *wmi,
         hdr->command_id = cpu_to_be16(cmd);
         hdr->seq_no = cpu_to_be16(++wmi->tx_seq_id);
 
-        return htc_send(wmi->htc, skb, wmi->ctrl_epid, NULL);
+        return htc_send_epid(wmi->htc, skb, wmi->ctrl_epid);
 }
 
 int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
@@ -276,7 +294,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
         int time_left, ret = 0;
         unsigned long flags;
 
-        if (wmi->drv_priv->op_flags & OP_UNPLUGGED)
+        if (ah->ah_flags & AH_UNPLUGGED)
                 return 0;
 
         skb = alloc_skb(headroom + cmd_len, GFP_ATOMIC);
@@ -312,9 +330,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
 
         time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout);
         if (!time_left) {
-                ath_print(common, ATH_DBG_WMI,
-                          "Timeout waiting for WMI command: %s\n",
-                          wmi_cmd_to_name(cmd_id));
+                ath_dbg(common, ATH_DBG_WMI,
+                        "Timeout waiting for WMI command: %s\n",
+                        wmi_cmd_to_name(cmd_id));
                 mutex_unlock(&wmi->op_mutex);
                 return -ETIMEDOUT;
         }
@@ -324,8 +342,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
         return 0;
 
 out:
-        ath_print(common, ATH_DBG_WMI,
-                  "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
+        ath_dbg(common, ATH_DBG_WMI,
+                "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
         mutex_unlock(&wmi->op_mutex);
         kfree_skb(skb);
 
diff --git a/drivers/net/wireless/ath/ath9k/wmi.h b/drivers/net/wireless/ath/ath9k/wmi.h
index 765db5faa2d3..fde6da619f30 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.h
+++ b/drivers/net/wireless/ath/ath9k/wmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,7 +17,6 @@
 #ifndef WMI_H
 #define WMI_H
 
-
 struct wmi_event_txrate {
         __be32 txrate;
         struct {
@@ -31,8 +30,52 @@ struct wmi_cmd_hdr {
         __be16 seq_no;
 } __packed;
 
-struct wmi_swba {
+struct wmi_fw_version {
+        __be16 major;
+        __be16 minor;
+
+} __packed;
+
+struct wmi_event_swba {
+        __be64 tsf;
         u8 beacon_pending;
+};
+
+/*
+ * 64 - HTC header - WMI header - 1 / txstatus
+ * And some other hdr. space is also accounted for.
+ * 12 seems to be the magic number.
+ */
+#define HTC_MAX_TX_STATUS 12
+
+#define ATH9K_HTC_TXSTAT_ACK        BIT(0)
+#define ATH9K_HTC_TXSTAT_FILT       BIT(1)
+#define ATH9K_HTC_TXSTAT_RTC_CTS    BIT(2)
+#define ATH9K_HTC_TXSTAT_MCS        BIT(3)
+#define ATH9K_HTC_TXSTAT_CW40       BIT(4)
+#define ATH9K_HTC_TXSTAT_SGI        BIT(5)
+
+/*
+ * Legacy rates are indicated as indices.
+ * HT rates are indicated as dot11 numbers.
+ * This allows us to resrict the rate field
+ * to 4 bits.
+ */
+#define ATH9K_HTC_TXSTAT_RATE       0x0f
+#define ATH9K_HTC_TXSTAT_RATE_S     0
+
+#define ATH9K_HTC_TXSTAT_EPID       0xf0
+#define ATH9K_HTC_TXSTAT_EPID_S     4
+
+struct __wmi_event_txstatus {
+        u8 cookie;
+        u8 ts_rate; /* Also holds EP ID */
+        u8 ts_flags;
+};
+
+struct wmi_event_txstatus {
+        u8 cnt;
+        struct __wmi_event_txstatus txstatus[HTC_MAX_TX_STATUS];
 } __packed;
 
 enum wmi_cmd_id {
@@ -40,13 +83,12 @@ enum wmi_cmd_id {
         WMI_ACCESS_MEMORY_CMDID,
 
         /* Commands to Target */
+        WMI_GET_FW_VERSION,
         WMI_DISABLE_INTR_CMDID,
         WMI_ENABLE_INTR_CMDID,
-        WMI_RX_LINK_CMDID,
         WMI_ATH_INIT_CMDID,
         WMI_ABORT_TXQ_CMDID,
         WMI_STOP_TX_DMA_CMDID,
-        WMI_STOP_DMA_RECV_CMDID,
         WMI_ABORT_TX_DMA_CMDID,
         WMI_DRAIN_TXQ_CMDID,
         WMI_DRAIN_TXQ_ALL_CMDID,
@@ -54,23 +96,22 @@ enum wmi_cmd_id {
         WMI_STOP_RECV_CMDID,
         WMI_FLUSH_RECV_CMDID,
         WMI_SET_MODE_CMDID,
-        WMI_RESET_CMDID,
         WMI_NODE_CREATE_CMDID,
         WMI_NODE_REMOVE_CMDID,
         WMI_VAP_REMOVE_CMDID,
         WMI_VAP_CREATE_CMDID,
-        WMI_BEACON_UPDATE_CMDID,
         WMI_REG_READ_CMDID,
         WMI_REG_WRITE_CMDID,
         WMI_RC_STATE_CHANGE_CMDID,
         WMI_RC_RATE_UPDATE_CMDID,
-        WMI_DEBUG_INFO_CMDID,
-        WMI_HOST_ATTACH,
         WMI_TARGET_IC_UPDATE_CMDID,
-        WMI_TGT_STATS_CMDID,
         WMI_TX_AGGR_ENABLE_CMDID,
         WMI_TGT_DETACH_CMDID,
-        WMI_TGT_TXQ_ENABLE_CMDID,
+        WMI_NODE_UPDATE_CMDID,
+        WMI_INT_STATS_CMDID,
+        WMI_TX_STATS_CMDID,
+        WMI_RX_STATS_CMDID,
+        WMI_BITRATE_MASK_CMDID,
 };
 
 enum wmi_event_id {
@@ -79,9 +120,8 @@ enum wmi_event_id {
         WMI_FATAL_EVENTID,
         WMI_TXTO_EVENTID,
         WMI_BMISS_EVENTID,
-        WMI_WLAN_TXCOMP_EVENTID,
         WMI_DELBA_EVENTID,
-        WMI_TXRATE_EVENTID,
+        WMI_TXSTATUS_EVENTID,
 };
 
 #define MAX_CMD_NUMBER 62
@@ -91,6 +131,12 @@ struct register_write {
         __be32 val;
 };
 
+struct ath9k_htc_tx_event {
+        int count;
+        struct __wmi_event_txstatus txs;
+        struct list_head list;
+};
+
 struct wmi {
         struct ath9k_htc_priv *drv_priv;
         struct htc_target *htc;
@@ -98,12 +144,16 @@ struct wmi {
         struct mutex op_mutex;
         struct completion cmd_wait;
         enum wmi_cmd_id last_cmd_id;
+        struct sk_buff_head wmi_event_queue;
+        struct tasklet_struct wmi_event_tasklet;
         u16 tx_seq_id;
         u8 *cmd_rsp_buf;
         u32 cmd_rsp_len;
         bool stopped;
 
-        struct sk_buff *wmi_skb;
+        struct list_head pending_tx_events;
+        spinlock_t event_lock;
+
         spinlock_t wmi_lock;
 
         atomic_t mwrite_cnt;
@@ -120,7 +170,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
                   u8 *cmd_buf, u32 cmd_len,
                   u8 *rsp_buf, u32 rsp_len,
                   u32 timeout);
-void ath9k_wmi_tasklet(unsigned long data);
+void ath9k_wmi_event_tasklet(unsigned long data);
+void ath9k_fatal_work(struct work_struct *work);
+void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv);
 
 #define WMI_CMD(_wmi_cmd)                                               \
         do {                                                            \
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 4dda14e36227..33443bcaa8d9 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -19,7 +19,6 @@
 
 #define BITS_PER_BYTE           8
 #define OFDM_PLCP_BITS          22
-#define HT_RC_2_MCS(_rc)        ((_rc) & 0x1f)
 #define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
 #define L_STF                   8
 #define L_LTF                   8
@@ -32,7 +31,6 @@
 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
 
-#define OFDM_SIFS_TIME              16
 
 static u16 bits_per_symbol[][2] = {
         /* 20MHz 40MHz */
@@ -48,19 +46,20 @@ static u16 bits_per_symbol[][2] = {
 
 #define IS_HT_RATE(_rate)     ((_rate) & 0x80)
 
-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
-                                  struct ath_atx_tid *tid,
-                                  struct list_head *bf_head);
+static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+                               struct ath_atx_tid *tid,
+                               struct list_head *bf_head);
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                                 struct ath_txq *txq, struct list_head *bf_q,
                                 struct ath_tx_status *ts, int txok, int sendbar);
 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                              struct list_head *head);
-static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
-static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
-                              struct ath_tx_status *ts, int txok);
-static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
-                             int nbad, int txok, bool update_rc);
+static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
+static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_status *ts, int nframes, int nbad,
+                             int txok, bool update_rc);
+static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
+                              int seqno);
 
 enum {
         MCS_HT20,
@@ -122,7 +121,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
 
 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
-        struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
+        struct ath_txq *txq = tid->ac->txq;
 
         WARN_ON(!tid->paused);
 
@@ -138,23 +137,40 @@ unlock:
         spin_unlock_bh(&txq->axq_lock);
 }
 
+static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        BUILD_BUG_ON(sizeof(struct ath_frame_info) >
+                     sizeof(tx_info->rate_driver_data));
+        return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
+}
+
 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
-        struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
+        struct ath_txq *txq = tid->ac->txq;
         struct ath_buf *bf;
         struct list_head bf_head;
-        INIT_LIST_HEAD(&bf_head);
+        struct ath_tx_status ts;
+        struct ath_frame_info *fi;
 
-        WARN_ON(!tid->paused);
+        INIT_LIST_HEAD(&bf_head);
 
+        memset(&ts, 0, sizeof(ts));
         spin_lock_bh(&txq->axq_lock);
-        tid->paused = false;
 
         while (!list_empty(&tid->buf_q)) {
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
-                BUG_ON(bf_isretried(bf));
                 list_move_tail(&bf->list, &bf_head);
-                ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
+
+                spin_unlock_bh(&txq->axq_lock);
+                fi = get_frame_info(bf->bf_mpdu);
+                if (fi->retries) {
+                        ath_tx_update_baw(sc, tid, fi->seqno);
+                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
+                } else {
+                        ath_tx_send_normal(sc, txq, NULL, &bf_head);
+                }
+                spin_lock_bh(&txq->axq_lock);
         }
 
         spin_unlock_bh(&txq->axq_lock);
@@ -168,27 +184,22 @@ static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
         index  = ATH_BA_INDEX(tid->seq_start, seqno);
         cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
 
-        tid->tx_buf[cindex] = NULL;
+        __clear_bit(cindex, tid->tx_buf);
 
-        while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
+        while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
                 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
                 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
         }
 }
 
 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
-                             struct ath_buf *bf)
+                             u16 seqno)
 {
         int index, cindex;
 
-        if (bf_isretried(bf))
-                return;
-
-        index  = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
+        index  = ATH_BA_INDEX(tid->seq_start, seqno);
         cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
-
-        BUG_ON(tid->tx_buf[cindex] != NULL);
-        tid->tx_buf[cindex] = bf;
+        __set_bit(cindex, tid->tx_buf);
 
         if (index >= ((tid->baw_tail - tid->baw_head) &
                 (ATH_TID_MAX_BUFS - 1))) {
@@ -210,6 +221,7 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
         struct ath_buf *bf;
         struct list_head bf_head;
         struct ath_tx_status ts;
+        struct ath_frame_info *fi;
 
         memset(&ts, 0, sizeof(ts));
         INIT_LIST_HEAD(&bf_head);
@@ -221,8 +233,9 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
                 list_move_tail(&bf->list, &bf_head);
 
-                if (bf_isretried(bf))
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                fi = get_frame_info(bf->bf_mpdu);
+                if (fi->retries)
+                        ath_tx_update_baw(sc, tid, fi->seqno);
 
                 spin_unlock(&txq->axq_lock);
                 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
@@ -234,16 +247,15 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
 }
 
 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
-                             struct ath_buf *bf)
+                             struct sk_buff *skb)
 {
-        struct sk_buff *skb;
+        struct ath_frame_info *fi = get_frame_info(skb);
         struct ieee80211_hdr *hdr;
 
-        bf->bf_state.bf_type |= BUF_RETRY;
-        bf->bf_retries++;
         TX_STAT_INC(txq->axq_qnum, a_retries);
+        if (fi->retries++ > 0)
+                return;
 
-        skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
 }
@@ -284,24 +296,54 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
 
         ATH_TXBUF_RESET(tbf);
 
-        tbf->aphy = bf->aphy;
         tbf->bf_mpdu = bf->bf_mpdu;
         tbf->bf_buf_addr = bf->bf_buf_addr;
         memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
         tbf->bf_state = bf->bf_state;
-        tbf->bf_dmacontext = bf->bf_dmacontext;
 
         return tbf;
 }
 
+static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
+                                struct ath_tx_status *ts, int txok,
+                                int *nframes, int *nbad)
+{
+        struct ath_frame_info *fi;
+        u16 seq_st = 0;
+        u32 ba[WME_BA_BMP_SIZE >> 5];
+        int ba_index;
+        int isaggr = 0;
+
+        *nbad = 0;
+        *nframes = 0;
+
+        isaggr = bf_isaggr(bf);
+        if (isaggr) {
+                seq_st = ts->ts_seqnum;
+                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
+        }
+
+        while (bf) {
+                fi = get_frame_info(bf->bf_mpdu);
+                ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
+
+                (*nframes)++;
+                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
+                        (*nbad)++;
+
+                bf = bf->bf_next;
+        }
+}
+
+
 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                  struct ath_buf *bf, struct list_head *bf_q,
-                                 struct ath_tx_status *ts, int txok)
+                                 struct ath_tx_status *ts, int txok, bool retry)
 {
         struct ath_node *an = NULL;
         struct sk_buff *skb;
         struct ieee80211_sta *sta;
-        struct ieee80211_hw *hw;
+        struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_hdr *hdr;
         struct ieee80211_tx_info *tx_info;
         struct ath_atx_tid *tid = NULL;
@@ -312,19 +354,21 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
         bool rc_update = true;
         struct ieee80211_tx_rate rates[4];
+        struct ath_frame_info *fi;
+        int nframes;
+        u8 tidno;
+        bool clear_filter;
 
         skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
 
         tx_info = IEEE80211_SKB_CB(skb);
-        hw = bf->aphy->hw;
 
         memcpy(rates, tx_info->control.rates, sizeof(rates));
 
         rcu_read_lock();
 
-        /* XXX: use ieee80211_find_sta! */
-        sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
+        sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
         if (!sta) {
                 rcu_read_unlock();
 
@@ -337,7 +381,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                             !bf->bf_stale || bf_next != NULL)
                                 list_move_tail(&bf->list, &bf_head);
 
-                        ath_tx_rc_status(bf, ts, 0, 0, false);
+                        ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
                                 0, 0);
 
@@ -347,14 +391,15 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         }
 
         an = (struct ath_node *)sta->drv_priv;
-        tid = ATH_AN_2_TID(an, bf->bf_tidno);
+        tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+        tid = ATH_AN_2_TID(an, tidno);
 
         /*
          * The hardware occasionally sends a tx status for the wrong TID.
          * In this case, the BA status cannot be considered valid and all
          * subframes need to be retransmitted
          */
-        if (bf->bf_tidno != ts->tid)
+        if (tidno != ts->tid)
                 txok = false;
 
         isaggr = bf_isaggr(bf);
@@ -380,15 +425,16 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         INIT_LIST_HEAD(&bf_pending);
         INIT_LIST_HEAD(&bf_head);
 
-        nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
+        ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
         while (bf) {
-                txfail = txpending = 0;
+                txfail = txpending = sendbar = 0;
                 bf_next = bf->bf_next;
 
                 skb = bf->bf_mpdu;
                 tx_info = IEEE80211_SKB_CB(skb);
+                fi = get_frame_info(skb);
 
-                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
+                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
                         /* transmit completion, subframe is
                          * acked by block ack */
                         acked_cnt++;
@@ -396,23 +442,24 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         /* transmit completion */
                         acked_cnt++;
                 } else {
-                        if (!(tid->state & AGGR_CLEANUP) &&
-                            !bf_last->bf_tx_aborted) {
-                                if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
-                                        ath_tx_set_retry(sc, txq, bf);
-                                        txpending = 1;
-                                } else {
-                                        bf->bf_state.bf_type |= BUF_XRETRY;
-                                        txfail = 1;
-                                        sendbar = 1;
-                                        txfail_cnt++;
-                                }
-                        } else {
+                        if ((tid->state & AGGR_CLEANUP) || !retry) {
                                 /*
                                  * cleanup in progress, just fail
                                  * the un-acked sub-frames
                                  */
                                 txfail = 1;
+                        } else if (fi->retries < ATH_MAX_SW_RETRIES) {
+                                if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
+                                    !an->sleeping)
+                                        ath_tx_set_retry(sc, txq, bf->bf_mpdu);
+
+                                clear_filter = true;
+                                txpending = 1;
+                        } else {
+                                bf->bf_state.bf_type |= BUF_XRETRY;
+                                txfail = 1;
+                                sendbar = 1;
+                                txfail_cnt++;
                         }
                 }
 
@@ -431,27 +478,28 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         list_move_tail(&bf->list, &bf_head);
                 }
 
-                if (!txpending) {
+                if (!txpending || (tid->state & AGGR_CLEANUP)) {
                         /*
                          * complete the acked-ones/xretried ones; update
                          * block-ack window
                          */
                         spin_lock_bh(&txq->axq_lock);
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                        ath_tx_update_baw(sc, tid, fi->seqno);
                         spin_unlock_bh(&txq->axq_lock);
 
                         if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
                                 memcpy(tx_info->control.rates, rates, sizeof(rates));
-                                ath_tx_rc_status(bf, ts, nbad, txok, true);
+                                ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
                                 rc_update = false;
                         } else {
-                                ath_tx_rc_status(bf, ts, nbad, txok, false);
+                                ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
                         }
 
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
                                 !txfail, sendbar);
                 } else {
                         /* retry the un-acked ones */
+                        ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
                         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
                                 if (bf->bf_next == NULL && bf_last->bf_stale) {
                                         struct ath_buf *tbf;
@@ -464,14 +512,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                          */
                                         if (!tbf) {
                                                 spin_lock_bh(&txq->axq_lock);
-                                                ath_tx_update_baw(sc, tid,
-                                                                bf->bf_seqno);
+                                                ath_tx_update_baw(sc, tid, fi->seqno);
                                                 spin_unlock_bh(&txq->axq_lock);
 
                                                 bf->bf_state.bf_type |=
                                                         BUF_XRETRY;
-                                                ath_tx_rc_status(bf, ts, nbad,
-                                                                0, false);
+                                                ath_tx_rc_status(sc, bf, ts, nframes,
+                                                                nbad, 0, false);
                                                 ath_tx_complete_buf(sc, bf, txq,
                                                                     &bf_head,
                                                                     ts, 0, 0);
@@ -503,28 +550,33 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
 
         /* prepend un-acked frames to the beginning of the pending frame queue */
         if (!list_empty(&bf_pending)) {
+                if (an->sleeping)
+                        ieee80211_sta_set_tim(sta);
+
                 spin_lock_bh(&txq->axq_lock);
+                if (clear_filter)
+                        tid->ac->clear_ps_filter = true;
                 list_splice(&bf_pending, &tid->buf_q);
                 ath_tx_queue_tid(txq, tid);
                 spin_unlock_bh(&txq->axq_lock);
         }
 
         if (tid->state & AGGR_CLEANUP) {
+                ath_tx_flush_tid(sc, tid);
+
                 if (tid->baw_head == tid->baw_tail) {
                         tid->state &= ~AGGR_ADDBA_COMPLETE;
                         tid->state &= ~AGGR_CLEANUP;
-
-                        /* send buffered frames as singles */
-                        ath_tx_flush_tid(sc, tid);
                 }
-                rcu_read_unlock();
-                return;
         }
 
         rcu_read_unlock();
 
-        if (needreset)
+        if (needreset) {
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 ath_reset(sc, false);
+                spin_lock_bh(&sc->sc_pcu_lock);
+        }
 }
 
 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
@@ -585,8 +637,8 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
                                  (u32)ATH_AMPDU_LIMIT_MAX);
 
         /*
-         * h/w can accept aggregates upto 16 bit lengths (65535).
-         * The IE, however can hold upto 65536, which shows up here
+         * h/w can accept aggregates up to 16 bit lengths (65535).
+         * The IE, however can hold up to 65536, which shows up here
          * as zero. Ignore 65536 since we  are constrained by hw.
          */
         if (tid->an->maxampdu)
@@ -608,6 +660,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
         u16 minlen;
         u8 flags, rix;
         int width, streams, half_gi, ndelim, mindelim;
+        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
 
         /* Select standard number of delimiters based on frame length alone */
         ndelim = ATH_AGGR_GET_NDELIM(frmlen);
@@ -618,7 +671,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
          * TODO - this could be improved to be dependent on the rate.
          *      The hardware can keep up at lower rates, but not higher rates
          */
-        if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
+        if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
+            !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
                 ndelim += ATH_AGGR_ENCRYPTDELIM;
 
         /*
@@ -662,7 +716,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                                              struct ath_txq *txq,
                                              struct ath_atx_tid *tid,
-                                             struct list_head *bf_q)
+                                             struct list_head *bf_q,
+                                             int *aggr_len)
 {
 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
         struct ath_buf *bf, *bf_first, *bf_prev = NULL;
@@ -670,14 +725,17 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
         u16 aggr_limit = 0, al = 0, bpad = 0,
                 al_delta, h_baw = tid->baw_size / 2;
         enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
+        struct ieee80211_tx_info *tx_info;
+        struct ath_frame_info *fi;
 
         bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
 
         do {
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
+                fi = get_frame_info(bf->bf_mpdu);
 
                 /* do not step over block-ack window */
-                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
+                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
                         status = ATH_AGGR_BAW_CLOSED;
                         break;
                 }
@@ -688,7 +746,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                 }
 
                 /* do not exceed aggregation limit */
-                al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
+                al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
 
                 if (nframes &&
                     (aggr_limit < (al + bpad + al_delta + prev_al))) {
@@ -696,6 +754,11 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                         break;
                 }
 
+                tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
+                if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
+                        !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
+                        break;
+
                 /* do not exceed subframe limit */
                 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
                         status = ATH_AGGR_LIMITED;
@@ -710,14 +773,15 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                  * Get the delimiters needed to meet the MPDU
                  * density for this node.
                  */
-                ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
+                ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
                 bpad = PADBYTES(al_delta) + (ndelim << 2);
 
                 bf->bf_next = NULL;
                 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
 
                 /* link buffers of this frame to the aggregate */
-                ath_tx_addto_baw(sc, tid, bf);
+                if (!fi->retries)
+                        ath_tx_addto_baw(sc, tid, fi->seqno);
                 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
                 list_move_tail(&bf->list, bf_q);
                 if (bf_prev) {
@@ -729,8 +793,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
 
         } while (!list_empty(&tid->buf_q));
 
-        bf_first->bf_al = al;
-        bf_first->bf_nframes = nframes;
+        *aggr_len = al;
 
         return status;
 #undef PADBYTES
@@ -741,7 +804,9 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
 {
         struct ath_buf *bf;
         enum ATH_AGGR_STATUS status;
+        struct ath_frame_info *fi;
         struct list_head bf_q;
+        int aggr_len;
 
         do {
                 if (list_empty(&tid->buf_q))
@@ -749,7 +814,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
 
                 INIT_LIST_HEAD(&bf_q);
 
-                status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
+                status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
 
                 /*
                  * no frames picked up to be aggregated;
@@ -761,19 +826,26 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 bf = list_first_entry(&bf_q, struct ath_buf, list);
                 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
 
+                if (tid->ac->clear_ps_filter) {
+                        tid->ac->clear_ps_filter = false;
+                        ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
+                }
+
                 /* if only one frame, send as non-aggregate */
-                if (bf->bf_nframes == 1) {
+                if (bf == bf->bf_lastbf) {
+                        fi = get_frame_info(bf->bf_mpdu);
+
                         bf->bf_state.bf_type &= ~BUF_AGGR;
                         ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
-                        ath_buf_set_rate(sc, bf);
+                        ath_buf_set_rate(sc, bf, fi->framelen);
                         ath_tx_txqaddbuf(sc, txq, &bf_q);
                         continue;
                 }
 
                 /* setup first desc of aggregate */
                 bf->bf_state.bf_type |= BUF_AGGR;
-                ath_buf_set_rate(sc, bf);
-                ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
+                ath_buf_set_rate(sc, bf, aggr_len);
+                ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
 
                 /* anchor last desc of aggregate */
                 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
@@ -781,34 +853,37 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 ath_tx_txqaddbuf(sc, txq, &bf_q);
                 TX_STAT_INC(txq->axq_qnum, a_aggr);
 
-        } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
+        } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
                  status != ATH_AGGR_BAW_CLOSED);
 }
 
-void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
-                       u16 tid, u16 *ssn)
+int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
+                      u16 tid, u16 *ssn)
 {
         struct ath_atx_tid *txtid;
         struct ath_node *an;
 
         an = (struct ath_node *)sta->drv_priv;
         txtid = ATH_AN_2_TID(an, tid);
+
+        if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
+                return -EAGAIN;
+
         txtid->state |= AGGR_ADDBA_PROGRESS;
         txtid->paused = true;
-        *ssn = txtid->seq_start;
+        *ssn = txtid->seq_start = txtid->seq_next;
+
+        memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
+        txtid->baw_head = txtid->baw_tail = 0;
+
+        return 0;
 }
 
 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
         struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
-        struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
-        struct ath_tx_status ts;
-        struct ath_buf *bf;
-        struct list_head bf_head;
-
-        memset(&ts, 0, sizeof(ts));
-        INIT_LIST_HEAD(&bf_head);
+        struct ath_txq *txq = txtid->ac->txq;
 
         if (txtid->state & AGGR_CLEANUP)
                 return;
@@ -818,30 +893,82 @@ void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
                 return;
         }
 
-        /* drop all software retried frames and mark this TID */
         spin_lock_bh(&txq->axq_lock);
         txtid->paused = true;
-        while (!list_empty(&txtid->buf_q)) {
-                bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
-                if (!bf_isretried(bf)) {
-                        /*
-                         * NB: it's based on the assumption that
-                         * software retried frame will always stay
-                         * at the head of software queue.
-                         */
-                        break;
-                }
-                list_move_tail(&bf->list, &bf_head);
-                ath_tx_update_baw(sc, txtid, bf->bf_seqno);
-                ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
-        }
-        spin_unlock_bh(&txq->axq_lock);
 
-        if (txtid->baw_head != txtid->baw_tail) {
+        /*
+         * If frames are still being transmitted for this TID, they will be
+         * cleaned up during tx completion. To prevent race conditions, this
+         * TID can only be reused after all in-progress subframes have been
+         * completed.
+         */
+        if (txtid->baw_head != txtid->baw_tail)
                 txtid->state |= AGGR_CLEANUP;
-        } else {
+        else
                 txtid->state &= ~AGGR_ADDBA_COMPLETE;
-                ath_tx_flush_tid(sc, txtid);
+        spin_unlock_bh(&txq->axq_lock);
+
+        ath_tx_flush_tid(sc, txtid);
+}
+
+bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
+{
+        struct ath_atx_tid *tid;
+        struct ath_atx_ac *ac;
+        struct ath_txq *txq;
+        bool buffered = false;
+        int tidno;
+
+        for (tidno = 0, tid = &an->tid[tidno];
+             tidno < WME_NUM_TID; tidno++, tid++) {
+
+                if (!tid->sched)
+                        continue;
+
+                ac = tid->ac;
+                txq = ac->txq;
+
+                spin_lock_bh(&txq->axq_lock);
+
+                if (!list_empty(&tid->buf_q))
+                        buffered = true;
+
+                tid->sched = false;
+                list_del(&tid->list);
+
+                if (ac->sched) {
+                        ac->sched = false;
+                        list_del(&ac->list);
+                }
+
+                spin_unlock_bh(&txq->axq_lock);
+        }
+
+        return buffered;
+}
+
+void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
+{
+        struct ath_atx_tid *tid;
+        struct ath_atx_ac *ac;
+        struct ath_txq *txq;
+        int tidno;
+
+        for (tidno = 0, tid = &an->tid[tidno];
+             tidno < WME_NUM_TID; tidno++, tid++) {
+
+                ac = tid->ac;
+                txq = ac->txq;
+
+                spin_lock_bh(&txq->axq_lock);
+                ac->clear_ps_filter = true;
+
+                if (!list_empty(&tid->buf_q) && !tid->paused) {
+                        ath_tx_queue_tid(txq, tid);
+                        ath_txq_schedule(sc, txq);
+                }
+
+                spin_unlock_bh(&txq->axq_lock);
         }
 }
 
@@ -862,20 +989,6 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
         }
 }
 
-bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
-{
-        struct ath_atx_tid *txtid;
-
-        if (!(sc->sc_flags & SC_OP_TXAGGR))
-                return false;
-
-        txtid = ATH_AN_2_TID(an, tidno);
-
-        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
-                        return true;
-        return false;
-}
-
 /********************/
 /* Queue Management */
 /********************/
@@ -902,10 +1015,16 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info qi;
-        int qnum, i;
+        static const int subtype_txq_to_hwq[] = {
+                [WME_AC_BE] = ATH_TXQ_AC_BE,
+                [WME_AC_BK] = ATH_TXQ_AC_BK,
+                [WME_AC_VI] = ATH_TXQ_AC_VI,
+                [WME_AC_VO] = ATH_TXQ_AC_VO,
+        };
+        int axq_qnum, i;
 
         memset(&qi, 0, sizeof(qi));
-        qi.tqi_subtype = subtype;
+        qi.tqi_subtype = subtype_txq_to_hwq[subtype];
         qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
         qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
         qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
@@ -936,40 +1055,40 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
                         qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
                                         TXQ_FLAG_TXDESCINT_ENABLE;
         }
-        qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
-        if (qnum == -1) {
+        axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
+        if (axq_qnum == -1) {
                 /*
                  * NB: don't print a message, this happens
                  * normally on parts with too few tx queues
                  */
                 return NULL;
         }
-        if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "qnum %u out of range, max %u!\n",
-                          qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
-                ath9k_hw_releasetxqueue(ah, qnum);
+        if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
+                ath_err(common, "qnum %u out of range, max %zu!\n",
+                        axq_qnum, ARRAY_SIZE(sc->tx.txq));
+                ath9k_hw_releasetxqueue(ah, axq_qnum);
                 return NULL;
         }
-        if (!ATH_TXQ_SETUP(sc, qnum)) {
-                struct ath_txq *txq = &sc->tx.txq[qnum];
+        if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
+                struct ath_txq *txq = &sc->tx.txq[axq_qnum];
 
-                txq->axq_class = subtype;
-                txq->axq_qnum = qnum;
+                txq->axq_qnum = axq_qnum;
+                txq->mac80211_qnum = -1;
                 txq->axq_link = NULL;
                 INIT_LIST_HEAD(&txq->axq_q);
                 INIT_LIST_HEAD(&txq->axq_acq);
                 spin_lock_init(&txq->axq_lock);
                 txq->axq_depth = 0;
+                txq->axq_ampdu_depth = 0;
                 txq->axq_tx_inprogress = false;
-                sc->tx.txqsetup |= 1<<qnum;
+                sc->tx.txqsetup |= 1<<axq_qnum;
 
                 txq->txq_headidx = txq->txq_tailidx = 0;
                 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
                         INIT_LIST_HEAD(&txq->txq_fifo[i]);
                 INIT_LIST_HEAD(&txq->txq_fifo_pending);
         }
-        return &sc->tx.txq[qnum];
+        return &sc->tx.txq[axq_qnum];
 }
 
 int ath_txq_update(struct ath_softc *sc, int qnum,
@@ -999,8 +1118,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
         qi.tqi_readyTime = qinfo->tqi_readyTime;
 
         if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to update hardware queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to update hardware queue %u!\n", qnum);
                 error = -EIO;
         } else {
                 ath9k_hw_resettxqueue(ah, qnum);
@@ -1012,6 +1131,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
 int ath_cabq_update(struct ath_softc *sc)
 {
         struct ath9k_tx_queue_info qi;
+        struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
         int qnum = sc->beacon.cabq->axq_qnum;
 
         ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
@@ -1023,13 +1143,19 @@ int ath_cabq_update(struct ath_softc *sc)
         else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
                 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
 
-        qi.tqi_readyTime = (sc->beacon_interval *
+        qi.tqi_readyTime = (cur_conf->beacon_interval *
                             sc->config.cabqReadytime) / 100;
         ath_txq_update(sc, qnum, &qi);
 
         return 0;
 }
 
+static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
+    return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
+}
+
 /*
  * Drain a given TX queue (could be Beacon or Data)
  *
@@ -1076,8 +1202,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
 
                 lastbf = bf->bf_lastbf;
-                if (!retry_tx)
-                        lastbf->bf_tx_aborted = true;
 
                 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                         list_cut_position(&bf_head,
@@ -1090,11 +1214,13 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
 
                 txq->axq_depth--;
-
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
+                                             retry_tx);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
         }
@@ -1103,15 +1229,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
         txq->axq_tx_inprogress = false;
         spin_unlock_bh(&txq->axq_lock);
 
-        /* flush any pending frames if aggregation is enabled */
-        if (sc->sc_flags & SC_OP_TXAGGR) {
-                if (!retry_tx) {
-                        spin_lock_bh(&txq->axq_lock);
-                        ath_txq_drain_pending_buffers(sc, txq);
-                        spin_unlock_bh(&txq->axq_lock);
-                }
-        }
-
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 spin_lock_bh(&txq->axq_lock);
                 while (!list_empty(&txq->txq_fifo_pending)) {
@@ -1124,7 +1241,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
 
                         if (bf_isampdu(bf))
                                 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
-                                                     &ts, 0);
+                                                     &ts, 0, retry_tx);
                         else
                                 ath_tx_complete_buf(sc, bf, txq, &bf_head,
                                                     &ts, 0, 0);
@@ -1132,9 +1249,18 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
                 spin_unlock_bh(&txq->axq_lock);
         }
+
+        /* flush any pending frames if aggregation is enabled */
+        if (sc->sc_flags & SC_OP_TXAGGR) {
+                if (!retry_tx) {
+                        spin_lock_bh(&txq->axq_lock);
+                        ath_txq_drain_pending_buffers(sc, txq);
+                        spin_unlock_bh(&txq->axq_lock);
+                }
+        }
 }
 
-void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
+bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -1142,39 +1268,36 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
         int i, npend = 0;
 
         if (sc->sc_flags & SC_OP_INVALID)
-                return;
+                return true;
 
-        /* Stop beacon queue */
-        ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
+        ath9k_hw_abort_tx_dma(ah);
 
-        /* Stop data queues */
+        /* Check if any queue remains active */
         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
-                if (ATH_TXQ_SETUP(sc, i)) {
-                        txq = &sc->tx.txq[i];
-                        ath9k_hw_stoptxdma(ah, txq->axq_qnum);
-                        npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
-                }
+                if (!ATH_TXQ_SETUP(sc, i))
+                        continue;
+
+                npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
         }
 
-        if (npend) {
-                int r;
+        if (npend)
+                ath_err(common, "Failed to stop TX DMA!\n");
 
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to stop TX DMA. Resetting hardware!\n");
+        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+                if (!ATH_TXQ_SETUP(sc, i))
+                        continue;
 
-                spin_lock_bh(&sc->sc_resetlock);
-                r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
-                if (r)
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to reset hardware; reset status %d\n",
-                                  r);
-                spin_unlock_bh(&sc->sc_resetlock);
+                /*
+                 * The caller will resume queues with ieee80211_wake_queues.
+                 * Mark the queue as not stopped to prevent ath_tx_complete
+                 * from waking the queue too early.
+                 */
+                txq = &sc->tx.txq[i];
+                txq->stopped = false;
+                ath_draintxq(sc, txq, retry_tx);
         }
 
-        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
-                if (ATH_TXQ_SETUP(sc, i))
-                        ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
-        }
+        return !npend;
 }
 
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
@@ -1183,65 +1306,60 @@ void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
         sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
 }
 
+/* For each axq_acq entry, for each tid, try to schedule packets
+ * for transmit until ampdu_depth has reached min Q depth.
+ */
 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
 {
-        struct ath_atx_ac *ac;
-        struct ath_atx_tid *tid;
+        struct ath_atx_ac *ac, *ac_tmp, *last_ac;
+        struct ath_atx_tid *tid, *last_tid;
 
-        if (list_empty(&txq->axq_acq))
+        if (list_empty(&txq->axq_acq) ||
+            txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
                 return;
 
         ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
-        list_del(&ac->list);
-        ac->sched = false;
-
-        do {
-                if (list_empty(&ac->tid_q))
-                        return;
+        last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
 
-                tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
-                list_del(&tid->list);
-                tid->sched = false;
+        list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
+                last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
+                list_del(&ac->list);
+                ac->sched = false;
 
-                if (tid->paused)
-                        continue;
+                while (!list_empty(&ac->tid_q)) {
+                        tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
+                                               list);
+                        list_del(&tid->list);
+                        tid->sched = false;
 
-                ath_tx_sched_aggr(sc, txq, tid);
+                        if (tid->paused)
+                                continue;
 
-                /*
-                 * add tid to round-robin queue if more frames
-                 * are pending for the tid
-                 */
-                if (!list_empty(&tid->buf_q))
-                        ath_tx_queue_tid(txq, tid);
+                        ath_tx_sched_aggr(sc, txq, tid);
 
-                break;
-        } while (!list_empty(&ac->tid_q));
+                        /*
+                         * add tid to round-robin queue if more frames
+                         * are pending for the tid
+                         */
+                        if (!list_empty(&tid->buf_q))
+                                ath_tx_queue_tid(txq, tid);
 
-        if (!list_empty(&ac->tid_q)) {
-                if (!ac->sched) {
-                        ac->sched = true;
-                        list_add_tail(&ac->list, &txq->axq_acq);
+                        if (tid == last_tid ||
+                            txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
+                                break;
                 }
-        }
-}
 
-int ath_tx_setup(struct ath_softc *sc, int haltype)
-{
-        struct ath_txq *txq;
+                if (!list_empty(&ac->tid_q)) {
+                        if (!ac->sched) {
+                                ac->sched = true;
+                                list_add_tail(&ac->list, &txq->axq_acq);
+                        }
+                }
 
-        if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "HAL AC %u out of range, max %zu!\n",
-                         haltype, ARRAY_SIZE(sc->tx.hwq_map));
-                return 0;
+                if (ac == last_ac ||
+                    txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
+                        return;
         }
-        txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
-        if (txq != NULL) {
-                sc->tx.hwq_map[haltype] = txq->axq_qnum;
-                return 1;
-        } else
-                return 0;
 }
 
 /***********/
@@ -1269,8 +1387,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
 
         bf = list_first_entry(head, struct ath_buf, list);
 
-        ath_print(common, ATH_DBG_QUEUE,
-                  "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
+        ath_dbg(common, ATH_DBG_QUEUE,
+                "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
@@ -1278,49 +1396,49 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                         return;
                 }
                 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "Initializing tx fifo %d which "
-                                  "is non-empty\n",
-                                  txq->txq_headidx);
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Initializing tx fifo %d which is non-empty\n",
+                                txq->txq_headidx);
                 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
                 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
                 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
+                TX_STAT_INC(txq->axq_qnum, puttxbuf);
                 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-                ath_print(common, ATH_DBG_XMIT,
-                          "TXDP[%u] = %llx (%p)\n",
-                          txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
+                ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
+                        txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
         } else {
                 list_splice_tail_init(head, &txq->axq_q);
 
                 if (txq->axq_link == NULL) {
+                        TX_STAT_INC(txq->axq_qnum, puttxbuf);
                         ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-                        ath_print(common, ATH_DBG_XMIT,
-                                        "TXDP[%u] = %llx (%p)\n",
-                                        txq->axq_qnum, ito64(bf->bf_daddr),
-                                        bf->bf_desc);
+                        ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
+                                txq->axq_qnum, ito64(bf->bf_daddr),
+                                bf->bf_desc);
                 } else {
                         *txq->axq_link = bf->bf_daddr;
-                        ath_print(common, ATH_DBG_XMIT,
-                                        "link[%u] (%p)=%llx (%p)\n",
-                                        txq->axq_qnum, txq->axq_link,
-                                        ito64(bf->bf_daddr), bf->bf_desc);
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "link[%u] (%p)=%llx (%p)\n",
+                                txq->axq_qnum, txq->axq_link,
+                                ito64(bf->bf_daddr), bf->bf_desc);
                 }
                 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
                                        &txq->axq_link);
+                TX_STAT_INC(txq->axq_qnum, txstart);
                 ath9k_hw_txstart(ah, txq->axq_qnum);
         }
         txq->axq_depth++;
+        if (bf_is_ampdu_not_probing(bf))
+                txq->axq_ampdu_depth++;
 }
 
 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
-                              struct list_head *bf_head,
-                              struct ath_tx_control *txctl)
+                              struct ath_buf *bf, struct ath_tx_control *txctl)
 {
-        struct ath_buf *bf;
+        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
+        struct list_head bf_head;
 
-        bf = list_first_entry(bf_head, struct ath_buf, list);
         bf->bf_state.bf_type |= BUF_AMPDU;
-        TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
 
         /*
          * Do not queue to h/w when any of the following conditions is true:
@@ -1330,56 +1448,49 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
          * - h/w queue depth exceeds low water mark
          */
         if (!list_empty(&tid->buf_q) || tid->paused ||
-            !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
-            txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
+            !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
+            txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
                 /*
                  * Add this frame to software queue for scheduling later
                  * for aggregation.
                  */
-                list_move_tail(&bf->list, &tid->buf_q);
+                TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
+                list_add_tail(&bf->list, &tid->buf_q);
                 ath_tx_queue_tid(txctl->txq, tid);
                 return;
         }
 
+        INIT_LIST_HEAD(&bf_head);
+        list_add(&bf->list, &bf_head);
+
         /* Add sub-frame to BAW */
-        ath_tx_addto_baw(sc, tid, bf);
+        if (!fi->retries)
+                ath_tx_addto_baw(sc, tid, fi->seqno);
 
         /* Queue to h/w without aggregation */
-        bf->bf_nframes = 1;
+        TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
         bf->bf_lastbf = bf;
-        ath_buf_set_rate(sc, bf);
-        ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
+        ath_buf_set_rate(sc, bf, fi->framelen);
+        ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
 }
 
-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
-                                  struct ath_atx_tid *tid,
-                                  struct list_head *bf_head)
+static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+                               struct ath_atx_tid *tid,
+                               struct list_head *bf_head)
 {
+        struct ath_frame_info *fi;
         struct ath_buf *bf;
 
         bf = list_first_entry(bf_head, struct ath_buf, list);
         bf->bf_state.bf_type &= ~BUF_AMPDU;
 
         /* update starting sequence number for subsequent ADDBA request */
-        INCR(tid->seq_start, IEEE80211_SEQ_MAX);
-
-        bf->bf_nframes = 1;
-        bf->bf_lastbf = bf;
-        ath_buf_set_rate(sc, bf);
-        ath_tx_txqaddbuf(sc, txq, bf_head);
-        TX_STAT_INC(txq->axq_qnum, queued);
-}
-
-static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
-                               struct list_head *bf_head)
-{
-        struct ath_buf *bf;
-
-        bf = list_first_entry(bf_head, struct ath_buf, list);
+        if (tid)
+                INCR(tid->seq_start, IEEE80211_SEQ_MAX);
 
         bf->bf_lastbf = bf;
-        bf->bf_nframes = 1;
-        ath_buf_set_rate(sc, bf);
+        fi = get_frame_info(bf->bf_mpdu);
+        ath_buf_set_rate(sc, bf, fi->framelen);
         ath_tx_txqaddbuf(sc, txq, bf_head);
         TX_STAT_INC(txq->axq_qnum, queued);
 }
@@ -1407,67 +1518,65 @@ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
         return htype;
 }
 
-static int get_hw_crypto_keytype(struct sk_buff *skb)
-{
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-
-        if (tx_info->control.hw_key) {
-                if (tx_info->control.hw_key->alg == ALG_WEP)
-                        return ATH9K_KEY_TYPE_WEP;
-                else if (tx_info->control.hw_key->alg == ALG_TKIP)
-                        return ATH9K_KEY_TYPE_TKIP;
-                else if (tx_info->control.hw_key->alg == ALG_CCMP)
-                        return ATH9K_KEY_TYPE_AES;
-        }
-
-        return ATH9K_KEY_TYPE_CLEAR;
-}
-
-static void assign_aggr_tid_seqno(struct sk_buff *skb,
-                                  struct ath_buf *bf)
+static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
+                             int framelen)
 {
+        struct ath_softc *sc = hw->priv;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_sta *sta = tx_info->control.sta;
+        struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
         struct ieee80211_hdr *hdr;
-        struct ath_node *an;
+        struct ath_frame_info *fi = get_frame_info(skb);
+        struct ath_node *an = NULL;
         struct ath_atx_tid *tid;
-        __le16 fc;
-        u8 *qc;
+        enum ath9k_key_type keytype;
+        u16 seqno = 0;
+        u8 tidno;
 
-        if (!tx_info->control.sta)
-                return;
+        keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
+
+        if (sta)
+                an = (struct ath_node *) sta->drv_priv;
 
-        an = (struct ath_node *)tx_info->control.sta->drv_priv;
         hdr = (struct ieee80211_hdr *)skb->data;
-        fc = hdr->frame_control;
+        if (an && ieee80211_is_data_qos(hdr->frame_control) &&
+                conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
 
-        if (ieee80211_is_data_qos(fc)) {
-                qc = ieee80211_get_qos_ctl(hdr);
-                bf->bf_tidno = qc[0] & 0xf;
+                tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+
+                /*
+                 * Override seqno set by upper layer with the one
+                 * in tx aggregation state.
+                 */
+                tid = ATH_AN_2_TID(an, tidno);
+                seqno = tid->seq_next;
+                hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
+                INCR(tid->seq_next, IEEE80211_SEQ_MAX);
         }
 
-        /*
-         * For HT capable stations, we save tidno for later use.
-         * We also override seqno set by upper layer with the one
-         * in tx aggregation state.
-         */
-        tid = ATH_AN_2_TID(an, bf->bf_tidno);
-        hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
-        bf->bf_seqno = tid->seq_next;
-        INCR(tid->seq_next, IEEE80211_SEQ_MAX);
+        memset(fi, 0, sizeof(*fi));
+        if (hw_key)
+                fi->keyix = hw_key->hw_key_idx;
+        else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
+                fi->keyix = an->ps_key;
+        else
+                fi->keyix = ATH9K_TXKEYIX_INVALID;
+        fi->keytype = keytype;
+        fi->framelen = framelen;
+        fi->seqno = seqno;
 }
 
-static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
+static int setup_tx_flags(struct sk_buff *skb)
 {
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         int flags = 0;
 
-        flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
         flags |= ATH9K_TXDESC_INTREQ;
 
         if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
                 flags |= ATH9K_TXDESC_NOACK;
 
-        if (use_ldpc)
+        if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
                 flags |= ATH9K_TXDESC_LDPC;
 
         return flags;
@@ -1479,13 +1588,11 @@ static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
  * width  - 0 for 20 MHz, 1 for 40 MHz
  * half_gi - to use 4us v/s 3.6 us for symbol time
  */
-static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
+static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
                             int width, int half_gi, bool shortPreamble)
 {
         u32 nbits, nsymbits, duration, nsymbols;
-        int streams, pktlen;
-
-        pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
+        int streams;
 
         /* find number of symbols: PLCP + data */
         streams = HT_RC_2_STREAMS(rix);
@@ -1504,7 +1611,19 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
         return duration;
 }
 
-static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
+u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *curchan = ah->curchan;
+        if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
+                        (curchan->channelFlags & CHANNEL_5GHZ) &&
+                        (chainmask == 0x7) && (rate < 0x90))
+                return 0x3;
+        else
+                return chainmask;
+}
+
+static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath9k_11n_rate_series series[4];
@@ -1544,10 +1663,8 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 
                 rix = rates[i].idx;
                 series[i].Tries = rates[i].count;
-                series[i].ChSel = common->tx_chainmask;
 
-                if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
-                    (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
+                    if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
                         series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
                         flags |= ATH9K_TXDESC_RTSENA;
                 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
@@ -1567,14 +1684,16 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
                         /* MCS rates */
                         series[i].Rate = rix | 0x80;
-                        series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
+                        series[i].ChSel = ath_txchainmask_reduction(sc,
+                                        common->tx_chainmask, series[i].Rate);
+                        series[i].PktDuration = ath_pkt_duration(sc, rix, len,
                                  is_40, is_sgi, is_sp);
                         if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
                                 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
                         continue;
                 }
 
-                /* legcay rates */
+                /* legacy rates */
                 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
                     !(rate->flags & IEEE80211_RATE_ERP_G))
                         phy = WLAN_RC_PHY_CCK;
@@ -1590,12 +1709,18 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                         is_sp = false;
                 }
 
+                if (bf->bf_state.bfs_paprd)
+                        series[i].ChSel = common->tx_chainmask;
+                else
+                        series[i].ChSel = ath_txchainmask_reduction(sc,
+                                        common->tx_chainmask, series[i].Rate);
+
                 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
-                        phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
+                        phy, rate->bitrate * 100, len, rix, is_sp);
         }
 
         /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
-        if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
+        if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
                 flags &= ~ATH9K_TXDESC_RTSENA;
 
         /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
@@ -1608,122 +1733,49 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                                      !is_pspoll, ctsrate,
                                      0, series, 4, flags);
 
-        if (sc->config.ath_aggr_prot && flags)
-                ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
 }
 
-static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
-                                struct sk_buff *skb,
-                                struct ath_tx_control *txctl)
+static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
+                                           struct ath_txq *txq,
+                                           struct sk_buff *skb)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-        int hdrlen;
-        __le16 fc;
-        int padpos, padsize;
-        bool use_ldpc = false;
-
-        tx_info->pad[0] = 0;
-        switch (txctl->frame_type) {
-        case ATH9K_IFT_NOT_INTERNAL:
-                break;
-        case ATH9K_IFT_PAUSE:
-                tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
-                /* fall through */
-        case ATH9K_IFT_UNPAUSE:
-                tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
-                break;
-        }
-        hdrlen = ieee80211_get_hdrlen_from_skb(skb);
-        fc = hdr->frame_control;
-
-        ATH_TXBUF_RESET(bf);
-
-        bf->aphy = aphy;
-        bf->bf_frmlen = skb->len + FCS_LEN;
-        /* Remove the padding size from bf_frmlen, if any */
-        padpos = ath9k_cmn_padpos(hdr->frame_control);
-        padsize = padpos & 3;
-        if (padsize && skb->len>padpos+padsize) {
-                bf->bf_frmlen -= padsize;
-        }
-
-        if (!txctl->paprd && conf_is_ht(&hw->conf)) {
-                bf->bf_state.bf_type |= BUF_HT;
-                if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
-                        use_ldpc = true;
-        }
-
-        bf->bf_state.bfs_paprd = txctl->paprd;
-        if (txctl->paprd)
-                bf->bf_state.bfs_paprd_timestamp = jiffies;
-        bf->bf_flags = setup_tx_flags(skb, use_ldpc);
+        struct ath_softc *sc = hw->priv;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_frame_info *fi = get_frame_info(skb);
+        struct ath_buf *bf;
+        struct ath_desc *ds;
+        int frm_type;
 
-        bf->bf_keytype = get_hw_crypto_keytype(skb);
-        if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
-                bf->bf_frmlen += tx_info->control.hw_key->icv_len;
-                bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
-        } else {
-                bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
+        bf = ath_tx_get_buffer(sc);
+        if (!bf) {
+                ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
+                return NULL;
         }
 
-        if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
-            (sc->sc_flags & SC_OP_TXAGGR))
-                assign_aggr_tid_seqno(skb, bf);
+        ATH_TXBUF_RESET(bf);
 
+        bf->bf_flags = setup_tx_flags(skb);
         bf->bf_mpdu = skb;
 
-        bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
-                                           skb->len, DMA_TO_DEVICE);
-        if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
+        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+                                         skb->len, DMA_TO_DEVICE);
+        if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 bf->bf_mpdu = NULL;
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "dma_mapping_error() on TX\n");
-                return -ENOMEM;
+                bf->bf_buf_addr = 0;
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "dma_mapping_error() on TX\n");
+                ath_tx_return_buffer(sc, bf);
+                return NULL;
         }
 
-        bf->bf_buf_addr = bf->bf_dmacontext;
-
-        /* tag if this is a nullfunc frame to enable PS when AP acks it */
-        if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
-                bf->bf_isnullfunc = true;
-                sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
-        } else
-                bf->bf_isnullfunc = false;
-
-        bf->bf_tx_aborted = false;
-
-        return 0;
-}
-
-/* FIXME: tx power */
-static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
-                             struct ath_tx_control *txctl)
-{
-        struct sk_buff *skb = bf->bf_mpdu;
-        struct ieee80211_tx_info *tx_info =  IEEE80211_SKB_CB(skb);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-        struct ath_node *an = NULL;
-        struct list_head bf_head;
-        struct ath_desc *ds;
-        struct ath_atx_tid *tid;
-        struct ath_hw *ah = sc->sc_ah;
-        int frm_type;
-        __le16 fc;
-
         frm_type = get_hw_packet_type(skb);
-        fc = hdr->frame_control;
-
-        INIT_LIST_HEAD(&bf_head);
-        list_add_tail(&bf->list, &bf_head);
 
         ds = bf->bf_desc;
         ath9k_hw_set_desc_link(ah, ds, 0);
 
-        ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
-                               bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
+        ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
+                               fi->keyix, fi->keytype, bf->bf_flags);
 
         ath9k_hw_filltxdesc(ah, ds,
                             skb->len,   /* segment length */
@@ -1731,109 +1783,83 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
                             true,       /* last segment */
                             ds,         /* first descriptor */
                             bf->bf_buf_addr,
-                            txctl->txq->axq_qnum);
-
-        if (bf->bf_state.bfs_paprd)
-                ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
-
-        spin_lock_bh(&txctl->txq->axq_lock);
-
-        if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
-            tx_info->control.sta) {
-                an = (struct ath_node *)tx_info->control.sta->drv_priv;
-                tid = ATH_AN_2_TID(an, bf->bf_tidno);
-
-                if (!ieee80211_is_data_qos(fc)) {
-                        ath_tx_send_normal(sc, txctl->txq, &bf_head);
-                        goto tx_done;
-                }
+                            txq->axq_qnum);
 
-                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
-                        /*
-                         * Try aggregation if it's a unicast data frame
-                         * and the destination is HT capable.
-                         */
-                        ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
-                } else {
-                        /*
-                         * Send this frame as regular when ADDBA
-                         * exchange is neither complete nor pending.
-                         */
-                        ath_tx_send_ht_normal(sc, txctl->txq,
-                                              tid, &bf_head);
-                }
-        } else {
-                ath_tx_send_normal(sc, txctl->txq, &bf_head);
-        }
 
-tx_done:
-        spin_unlock_bh(&txctl->txq->axq_lock);
+        return bf;
 }
 
-/* Upon failure caller should free skb */
-int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
-                 struct ath_tx_control *txctl)
+/* FIXME: tx power */
+static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_control *txctl)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_txq *txq = txctl->txq;
-        struct ath_buf *bf;
-        int q, r;
+        struct sk_buff *skb = bf->bf_mpdu;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+        struct list_head bf_head;
+        struct ath_atx_tid *tid = NULL;
+        u8 tidno;
 
-        bf = ath_tx_get_buffer(sc);
-        if (!bf) {
-                ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
-                return -1;
+        spin_lock_bh(&txctl->txq->axq_lock);
+        if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
+                ieee80211_is_data_qos(hdr->frame_control)) {
+                tidno = ieee80211_get_qos_ctl(hdr)[0] &
+                        IEEE80211_QOS_CTL_TID_MASK;
+                tid = ATH_AN_2_TID(txctl->an, tidno);
+
+                WARN_ON(tid->ac->txq != txctl->txq);
         }
 
-        r = ath_tx_setup_buffer(hw, bf, skb, txctl);
-        if (unlikely(r)) {
-                ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
+        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
+                /*
+                 * Try aggregation if it's a unicast data frame
+                 * and the destination is HT capable.
+                 */
+                ath_tx_send_ampdu(sc, tid, bf, txctl);
+        } else {
+                INIT_LIST_HEAD(&bf_head);
+                list_add_tail(&bf->list, &bf_head);
 
-                /* upon ath_tx_processq() this TX queue will be resumed, we
-                 * guarantee this will happen by knowing beforehand that
-                 * we will at least have to run TX completionon one buffer
-                 * on the queue */
-                spin_lock_bh(&txq->axq_lock);
-                if (!txq->stopped && txq->axq_depth > 1) {
-                        ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-                        txq->stopped = 1;
-                }
-                spin_unlock_bh(&txq->axq_lock);
+                bf->bf_state.bfs_ftype = txctl->frame_type;
+                bf->bf_state.bfs_paprd = txctl->paprd;
 
-                ath_tx_return_buffer(sc, bf);
+                if (bf->bf_state.bfs_paprd)
+                        ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
+                                                   bf->bf_state.bfs_paprd);
 
-                return r;
-        }
+                if (txctl->paprd)
+                        bf->bf_state.bfs_paprd_timestamp = jiffies;
 
-        q = skb_get_queue_mapping(skb);
-        if (q >= 4)
-                q = 0;
+                if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
+                        ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
 
-        spin_lock_bh(&txq->axq_lock);
-        if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
-                ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-                txq->stopped = 1;
+                ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
         }
-        spin_unlock_bh(&txq->axq_lock);
 
-        ath_tx_start_dma(sc, bf, txctl);
-
-        return 0;
+        spin_unlock_bh(&txctl->txq->axq_lock);
 }
 
-void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
+/* Upon failure caller should free skb */
+int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+                 struct ath_tx_control *txctl)
 {
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
-        int padpos, padsize;
         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-        struct ath_tx_control txctl;
+        struct ieee80211_sta *sta = info->control.sta;
+        struct ieee80211_vif *vif = info->control.vif;
+        struct ath_softc *sc = hw->priv;
+        struct ath_txq *txq = txctl->txq;
+        struct ath_buf *bf;
+        int padpos, padsize;
+        int frmlen = skb->len + FCS_LEN;
+        int q;
 
-        memset(&txctl, 0, sizeof(struct ath_tx_control));
+        /* NOTE:  sta can be NULL according to net/mac80211.h */
+        if (sta)
+                txctl->an = (struct ath_node *)sta->drv_priv;
+
+        if (info->control.hw_key)
+                frmlen += info->control.hw_key->icv_len;
 
         /*
          * As a temporary workaround, assign seq# here; this will likely need
@@ -1850,30 +1876,42 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
         /* Add the padding after the header if this is not already done */
         padpos = ath9k_cmn_padpos(hdr->frame_control);
         padsize = padpos & 3;
-        if (padsize && skb->len>padpos) {
-                if (skb_headroom(skb) < padsize) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "TX CABQ padding failed\n");
-                        dev_kfree_skb_any(skb);
-                        return;
-                }
+        if (padsize && skb->len > padpos) {
+                if (skb_headroom(skb) < padsize)
+                        return -ENOMEM;
+
                 skb_push(skb, padsize);
                 memmove(skb->data, skb->data + padsize, padpos);
         }
 
-        txctl.txq = sc->beacon.cabq;
+        if ((vif && vif->type != NL80211_IFTYPE_AP &&
+                    vif->type != NL80211_IFTYPE_AP_VLAN) ||
+            !ieee80211_is_data(hdr->frame_control))
+                info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
 
-        ath_print(common, ATH_DBG_XMIT,
-                  "transmitting CABQ packet, skb: %p\n", skb);
+        setup_frame_info(hw, skb, frmlen);
 
-        if (ath_tx_start(hw, skb, &txctl) != 0) {
-                ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
-                goto exit;
+        /*
+         * At this point, the vif, hw_key and sta pointers in the tx control
+         * info are no longer valid (overwritten by the ath_frame_info data.
+         */
+
+        bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
+        if (unlikely(!bf))
+                return -ENOMEM;
+
+        q = skb_get_queue_mapping(skb);
+        spin_lock_bh(&txq->axq_lock);
+        if (txq == sc->tx.txq_map[q] &&
+            ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
+                ieee80211_stop_queue(sc->hw, q);
+                txq->stopped = 1;
         }
+        spin_unlock_bh(&txq->axq_lock);
+
+        ath_tx_start_dma(sc, bf, txctl);
 
-        return;
-exit:
-        dev_kfree_skb_any(skb);
+        return 0;
 }
 
 /*****************/
@@ -1881,7 +1919,7 @@ exit:
 /*****************/
 
 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
-                            struct ath_wiphy *aphy, int tx_flags)
+                            int tx_flags, int ftype, struct ath_txq *txq)
 {
         struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -1889,10 +1927,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
         struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
         int q, padpos, padsize;
 
-        ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
-
-        if (aphy)
-                hw = aphy->hw;
+        ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
 
         if (tx_flags & ATH_TX_BAR)
                 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
@@ -1915,27 +1950,28 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
         if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
                 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
-                ath_print(common, ATH_DBG_PS,
-                          "Going back to sleep after having "
-                          "received TX status (0x%lx)\n",
+                ath_dbg(common, ATH_DBG_PS,
+                        "Going back to sleep after having received TX status (0x%lx)\n",
                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                         PS_WAIT_FOR_CAB |
                                         PS_WAIT_FOR_PSPOLL_DATA |
                                         PS_WAIT_FOR_TX_ACK));
         }
 
-        if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
-                ath9k_tx_status(hw, skb);
-        else {
-                q = skb_get_queue_mapping(skb);
-                if (q >= 4)
-                        q = 0;
-
-                if (--sc->tx.pending_frames[q] < 0)
-                        sc->tx.pending_frames[q] = 0;
+        q = skb_get_queue_mapping(skb);
+        if (txq == sc->tx.txq_map[q]) {
+                spin_lock_bh(&txq->axq_lock);
+                if (WARN_ON(--txq->pending_frames < 0))
+                        txq->pending_frames = 0;
 
-                ieee80211_tx_status(hw, skb);
+                if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
+                        ieee80211_wake_queue(sc->hw, q);
+                        txq->stopped = 0;
+                }
+                spin_unlock_bh(&txq->axq_lock);
         }
+
+        ieee80211_tx_status(hw, skb);
 }
 
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
@@ -1956,19 +1992,25 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                         tx_flags |= ATH_TX_XRETRY;
         }
 
-        dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
+        dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
+        bf->bf_buf_addr = 0;
 
         if (bf->bf_state.bfs_paprd) {
                 if (time_after(jiffies,
-                               bf->bf_state.bfs_paprd_timestamp +
-                               msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
+                                bf->bf_state.bfs_paprd_timestamp +
+                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
                         dev_kfree_skb_any(skb);
                 else
                         complete(&sc->paprd_complete);
         } else {
-                ath_tx_complete(sc, skb, bf->aphy, tx_flags);
-                ath_debug_stat_tx(sc, txq, bf, ts);
+                ath_debug_stat_tx(sc, bf, ts, txq);
+                ath_tx_complete(sc, skb, tx_flags,
+                                bf->bf_state.bfs_ftype, txq);
         }
+        /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
+         * accidentally reference it later.
+         */
+        bf->bf_mpdu = NULL;
 
         /*
          * Return the list of ath_buf of this mpdu to free queue
@@ -1978,42 +2020,15 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
         spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
 }
 
-static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
-                              struct ath_tx_status *ts, int txok)
-{
-        u16 seq_st = 0;
-        u32 ba[WME_BA_BMP_SIZE >> 5];
-        int ba_index;
-        int nbad = 0;
-        int isaggr = 0;
-
-        if (bf->bf_lastbf->bf_tx_aborted)
-                return 0;
-
-        isaggr = bf_isaggr(bf);
-        if (isaggr) {
-                seq_st = ts->ts_seqnum;
-                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
-        }
-
-        while (bf) {
-                ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
-                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
-                        nbad++;
-
-                bf = bf->bf_next;
-        }
-
-        return nbad;
-}
-
-static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
-                             int nbad, int txok, bool update_rc)
+static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_status *ts, int nframes, int nbad,
+                             int txok, bool update_rc)
 {
         struct sk_buff *skb = bf->bf_mpdu;
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-        struct ieee80211_hw *hw = bf->aphy->hw;
+        struct ieee80211_hw *hw = sc->hw;
+        struct ath_hw *ah = sc->sc_ah;
         u8 i, tx_rateindex;
 
         if (txok)
@@ -2024,21 +2039,35 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
 
         if (ts->ts_status & ATH9K_TXERR_FILT)
                 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
-        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
+        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
                 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
 
+                BUG_ON(nbad > nframes);
+
+                tx_info->status.ampdu_len = nframes;
+                tx_info->status.ampdu_ack_len = nframes - nbad;
+        }
+
         if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
             (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
-                if (ieee80211_is_data(hdr->frame_control)) {
-                        if (ts->ts_flags &
-                            (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
-                                tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
-                        if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
-                            (ts->ts_status & ATH9K_TXERR_FIFO))
-                                tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
-                        tx_info->status.ampdu_len = bf->bf_nframes;
-                        tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
-                }
+                /*
+                 * If an underrun error is seen assume it as an excessive
+                 * retry only if max frame trigger level has been reached
+                 * (2 KB for single stream, and 4 KB for dual stream).
+                 * Adjust the long retry as if the frame was tried
+                 * hw->max_rate_tries times to affect how rate control updates
+                 * PER for the failed rate.
+                 * In case of congestion on the bus penalizing this type of
+                 * underruns should help hardware actually transmit new frames
+                 * successfully by eventually preferring slower rates.
+                 * This itself should also alleviate congestion on the bus.
+                 */
+                if (ieee80211_is_data(hdr->frame_control) &&
+                    (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
+                                     ATH9K_TX_DELIM_UNDERRUN)) &&
+                    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
+                        tx_info->status.rates[tx_rateindex].count =
+                                hw->max_rate_tries;
         }
 
         for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
@@ -2049,22 +2078,6 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
         tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
 }
 
-static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
-{
-        int qnum;
-
-        qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
-        if (qnum == -1)
-                return;
-
-        spin_lock_bh(&txq->axq_lock);
-        if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
-                if (ath_mac80211_start_queue(sc, qnum))
-                        txq->stopped = 0;
-        }
-        spin_unlock_bh(&txq->axq_lock);
-}
-
 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 {
         struct ath_hw *ah = sc->sc_ah;
@@ -2076,14 +2089,16 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
         int txok;
         int status;
 
-        ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
-                  txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
-                  txq->axq_link);
+        ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
+                txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
+                txq->axq_link);
 
         for (;;) {
                 spin_lock_bh(&txq->axq_lock);
                 if (list_empty(&txq->axq_q)) {
                         txq->axq_link = NULL;
+                        if (sc->sc_flags & SC_OP_TXAGGR)
+                                ath_txq_schedule(sc, txq);
                         spin_unlock_bh(&txq->axq_lock);
                         break;
                 }
@@ -2118,18 +2133,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                         spin_unlock_bh(&txq->axq_lock);
                         break;
                 }
-
-                /*
-                 * We now know the nullfunc frame has been ACKed so we
-                 * can disable RX.
-                 */
-                if (bf->bf_isnullfunc &&
-                    (ts.ts_status & ATH9K_TX_ACKED)) {
-                        if ((sc->ps_flags & PS_ENABLED))
-                                ath9k_enable_ps(sc);
-                        else
-                                sc->ps_flags |= PS_NULLFUNC_COMPLETED;
-                }
+                TX_STAT_INC(txq->axq_qnum, txprocdesc);
 
                 /*
                  * Remove ath_buf's of the same transmit unit from txq,
@@ -2147,6 +2151,10 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                 txq->axq_tx_inprogress = false;
                 if (bf_held)
                         list_del(&bf_held->list);
+
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
+
                 spin_unlock_bh(&txq->axq_lock);
 
                 if (bf_held)
@@ -2159,17 +2167,17 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                          */
                         if (ts.ts_status & ATH9K_TXERR_XRETRY)
                                 bf->bf_state.bf_type |= BUF_XRETRY;
-                        ath_tx_rc_status(bf, &ts, 0, txok, true);
+                        ath_tx_rc_status(sc, bf, &ts, 1, txok ? 0 : 1, txok, true);
                 }
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
+                                             true);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
 
-                ath_wake_mac80211_queue(sc, txq);
-
                 spin_lock_bh(&txq->axq_lock);
+
                 if (sc->sc_flags & SC_OP_TXAGGR)
                         ath_txq_schedule(sc, txq);
                 spin_unlock_bh(&txq->axq_lock);
@@ -2183,6 +2191,9 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
         struct ath_txq *txq;
         int i;
         bool needreset = false;
+#ifdef CONFIG_ATH9K_DEBUGFS
+        sc->tx_complete_poll_work_seen++;
+#endif
 
         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
                 if (ATH_TXQ_SETUP(sc, i)) {
@@ -2201,11 +2212,9 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
                 }
 
         if (needreset) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
-                          "tx hung, resetting the chip\n");
-                ath9k_ps_wakeup(sc);
-                ath_reset(sc, false);
-                ath9k_ps_restore(sc);
+                ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
+                        "tx hung, resetting the chip\n");
+                ath_reset(sc, true);
         }
 
         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2243,8 +2252,8 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
                 if (status == -EINPROGRESS)
                         break;
                 if (status == -EIO) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "Error processing tx status\n");
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Error processing tx status\n");
                         break;
                 }
 
@@ -2270,45 +2279,38 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
                 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
                 txq->axq_depth--;
                 txq->axq_tx_inprogress = false;
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
 
-                /*
-                 * Make sure null func frame is acked before configuring
-                 * hw into ps mode.
-                 */
-                if (bf->bf_isnullfunc && txok) {
-                        if ((sc->ps_flags & PS_ENABLED))
-                                ath9k_enable_ps(sc);
-                        else
-                                sc->ps_flags |= PS_NULLFUNC_COMPLETED;
-                }
-
                 if (!bf_isampdu(bf)) {
                         if (txs.ts_status & ATH9K_TXERR_XRETRY)
                                 bf->bf_state.bf_type |= BUF_XRETRY;
-                        ath_tx_rc_status(bf, &txs, 0, txok, true);
+                        ath_tx_rc_status(sc, bf, &txs, 1, txok ? 0 : 1, txok, true);
                 }
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
+                                             txok, true);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head,
                                             &txs, txok, 0);
 
-                ath_wake_mac80211_queue(sc, txq);
-
                 spin_lock_bh(&txq->axq_lock);
+
                 if (!list_empty(&txq->txq_fifo_pending)) {
                         INIT_LIST_HEAD(&bf_head);
                         bf = list_first_entry(&txq->txq_fifo_pending,
-                                struct ath_buf, list);
-                        list_cut_position(&bf_head, &txq->txq_fifo_pending,
-                                &bf->bf_lastbf->list);
+                                              struct ath_buf, list);
+                        list_cut_position(&bf_head,
+                                          &txq->txq_fifo_pending,
+                                          &bf->bf_lastbf->list);
                         ath_tx_txqaddbuf(sc, txq, &bf_head);
                 } else if (sc->sc_flags & SC_OP_TXAGGR)
                         ath_txq_schedule(sc, txq);
+
                 spin_unlock_bh(&txq->axq_lock);
         }
 }
@@ -2362,16 +2364,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
         error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
                                   "tx", nbufs, 1, 1);
         if (error != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to allocate tx descriptors: %d\n", error);
+                ath_err(common,
+                        "Failed to allocate tx descriptors: %d\n", error);
                 goto err;
         }
 
         error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
                                   "beacon", ATH_BCBUF, 1, 1);
         if (error != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to allocate beacon descriptors: %d\n", error);
+                ath_err(common,
+                        "Failed to allocate beacon descriptors: %d\n", error);
                 goto err;
         }
 
@@ -2429,7 +2431,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
         for (acno = 0, ac = &an->ac[acno];
              acno < WME_NUM_AC; acno++, ac++) {
                 ac->sched    = false;
-                ac->qnum = sc->tx.hwq_map[acno];
+                ac->txq = sc->tx.txq_map[acno];
                 INIT_LIST_HEAD(&ac->tid_q);
         }
 }
@@ -2439,17 +2441,13 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
         struct ath_atx_ac *ac;
         struct ath_atx_tid *tid;
         struct ath_txq *txq;
-        int i, tidno;
+        int tidno;
 
         for (tidno = 0, tid = &an->tid[tidno];
              tidno < WME_NUM_TID; tidno++, tid++) {
-                i = tid->ac->qnum;
 
-                if (!ATH_TXQ_SETUP(sc, i))
-                        continue;
-
-                txq = &sc->tx.txq[i];
                 ac = tid->ac;
+                txq = ac->txq;
 
                 spin_lock_bh(&txq->axq_lock);