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-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h226
1 files changed, 143 insertions, 83 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index d01c4adab8d6..c18ee9921fb1 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -107,12 +107,6 @@
107#define AR_RXCFG_DMASZ_256B 6 107#define AR_RXCFG_DMASZ_256B 6
108#define AR_RXCFG_DMASZ_512B 7 108#define AR_RXCFG_DMASZ_512B 7
109 109
110#define AR_MIBC 0x0040
111#define AR_MIBC_COW 0x00000001
112#define AR_MIBC_FMC 0x00000002
113#define AR_MIBC_CMC 0x00000004
114#define AR_MIBC_MCS 0x00000008
115
116#define AR_TOPS 0x0044 110#define AR_TOPS 0x0044
117#define AR_TOPS_MASK 0x0000FFFF 111#define AR_TOPS_MASK 0x0000FFFF
118 112
@@ -699,7 +693,7 @@
699#define AR_RC_APB 0x00000002 693#define AR_RC_APB 0x00000002
700#define AR_RC_HOSTIF 0x00000100 694#define AR_RC_HOSTIF 0x00000100
701 695
702#define AR_WA 0x4004 696#define AR_WA (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
703#define AR_WA_BIT6 (1 << 6) 697#define AR_WA_BIT6 (1 << 6)
704#define AR_WA_BIT7 (1 << 7) 698#define AR_WA_BIT7 (1 << 7)
705#define AR_WA_BIT23 (1 << 23) 699#define AR_WA_BIT23 (1 << 23)
@@ -709,6 +703,7 @@
709#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ 703#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
710#define AR_WA_ANALOG_SHIFT (1 << 20) 704#define AR_WA_ANALOG_SHIFT (1 << 20)
711#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 705#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */
706#define AR_WA_BIT22 (1 << 22)
712#define AR9285_WA_DEFAULT 0x004a050b 707#define AR9285_WA_DEFAULT 0x004a050b
713#define AR9280_WA_DEFAULT 0x0040073b 708#define AR9280_WA_DEFAULT 0x0040073b
714#define AR_WA_DEFAULT 0x0000073f 709#define AR_WA_DEFAULT 0x0000073f
@@ -717,7 +712,7 @@
717#define AR_PM_STATE 0x4008 712#define AR_PM_STATE 0x4008
718#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 713#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
719 714
720#define AR_HOST_TIMEOUT 0x4018 715#define AR_HOST_TIMEOUT (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
721#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 716#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF
722#define AR_HOST_TIMEOUT_APB_CNTR_S 0 717#define AR_HOST_TIMEOUT_APB_CNTR_S 0
723#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 718#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000
@@ -747,7 +742,8 @@
747#define EEPROM_PROTECT_WP_1024_2047 0x8000 742#define EEPROM_PROTECT_WP_1024_2047 0x8000
748 743
749#define AR_SREV \ 744#define AR_SREV \
750 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) 745 ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
746 ? 0x400c : 0x4020))
751 747
752#define AR_SREV_ID \ 748#define AR_SREV_ID \
753 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 749 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
@@ -792,6 +788,10 @@
792#define AR_SREV_REVISION_9271_11 1 788#define AR_SREV_REVISION_9271_11 1
793#define AR_SREV_VERSION_9300 0x1c0 789#define AR_SREV_VERSION_9300 0x1c0
794#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 790#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
791#define AR_SREV_VERSION_9485 0x240
792#define AR_SREV_REVISION_9485_10 0
793#define AR_SREV_REVISION_9485_11 1
794#define AR_SREV_VERSION_9340 0x300
795 795
796#define AR_SREV_5416(_ah) \ 796#define AR_SREV_5416(_ah) \
797 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 797 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -819,49 +819,23 @@
819 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) 819 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
820#define AR_SREV_9280(_ah) \ 820#define AR_SREV_9280(_ah) \
821 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 821 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
822#define AR_SREV_9280_10_OR_LATER(_ah) \ 822#define AR_SREV_9280_20_OR_LATER(_ah) \
823 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) 823 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
824#define AR_SREV_9280_20(_ah) \ 824#define AR_SREV_9280_20(_ah) \
825 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ 825 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
826 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))
827#define AR_SREV_9280_20_OR_LATER(_ah) \
828 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \
829 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \
830 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)))
831 826
832#define AR_SREV_9285(_ah) \ 827#define AR_SREV_9285(_ah) \
833 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) 828 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
834#define AR_SREV_9285_10_OR_LATER(_ah) \
835 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
836#define AR_SREV_9285_11(_ah) \
837 (AR_SREV_9285(ah) && \
838 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11))
839#define AR_SREV_9285_11_OR_LATER(_ah) \
840 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \
841 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
842 AR_SREV_REVISION_9285_11)))
843#define AR_SREV_9285_12(_ah) \
844 (AR_SREV_9285(ah) && \
845 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12))
846#define AR_SREV_9285_12_OR_LATER(_ah) \ 829#define AR_SREV_9285_12_OR_LATER(_ah) \
847 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ 830 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
848 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \
849 AR_SREV_REVISION_9285_12)))
850 831
851#define AR_SREV_9287(_ah) \ 832#define AR_SREV_9287(_ah) \
852 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287)) 833 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
853#define AR_SREV_9287_10_OR_LATER(_ah) \ 834#define AR_SREV_9287_11_OR_LATER(_ah) \
854 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287)) 835 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
855#define AR_SREV_9287_10(_ah) \
856 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
857 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_10))
858#define AR_SREV_9287_11(_ah) \ 836#define AR_SREV_9287_11(_ah) \
859 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 837 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
860 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11)) 838 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
861#define AR_SREV_9287_11_OR_LATER(_ah) \
862 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
863 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
864 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_11)))
865#define AR_SREV_9287_12(_ah) \ 839#define AR_SREV_9287_12(_ah) \
866 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 840 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
867 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12)) 841 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
@@ -885,22 +859,36 @@
885 859
886#define AR_SREV_9300(_ah) \ 860#define AR_SREV_9300(_ah) \
887 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300)) 861 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
888#define AR_SREV_9300_20(_ah) \
889 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
890 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
891#define AR_SREV_9300_20_OR_LATER(_ah) \ 862#define AR_SREV_9300_20_OR_LATER(_ah) \
892 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \ 863 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
893 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \ 864
894 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20))) 865#define AR_SREV_9485(_ah) \
866 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
867#define AR_SREV_9485_10(_ah) \
868 (AR_SREV_9485(_ah) && \
869 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
870#define AR_SREV_9485_11(_ah) \
871 (AR_SREV_9485(_ah) && \
872 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
873#define AR_SREV_9485_OR_LATER(_ah) \
874 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
875
876#define AR_SREV_9340(_ah) \
877 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
895 878
896#define AR_SREV_9285E_20(_ah) \ 879#define AR_SREV_9285E_20(_ah) \
897 (AR_SREV_9285_12_OR_LATER(_ah) && \ 880 (AR_SREV_9285_12_OR_LATER(_ah) && \
898 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 881 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
899 882
883enum ath_usb_dev {
884 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
885 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
886 STORAGE_DEVICE = 3,
887};
888
900#define AR_DEVID_7010(_ah) \ 889#define AR_DEVID_7010(_ah) \
901 (((_ah)->hw_version.devid == 0x7010) || \ 890 (((_ah)->hw_version.usbdev == AR9280_USB) || \
902 ((_ah)->hw_version.devid == 0x7015) || \ 891 ((_ah)->hw_version.usbdev == AR9287_USB))
903 ((_ah)->hw_version.devid == 0x9018))
904 892
905#define AR_RADIO_SREV_MAJOR 0xf0 893#define AR_RADIO_SREV_MAJOR 0xf0
906#define AR_RAD5133_SREV_MAJOR 0xc0 894#define AR_RAD5133_SREV_MAJOR 0xc0
@@ -929,11 +917,11 @@
929#define AR_INTR_SPURIOUS 0xFFFFFFFF 917#define AR_INTR_SPURIOUS 0xFFFFFFFF
930 918
931 919
932#define AR_INTR_SYNC_CAUSE_CLR 0x4028 920#define AR_INTR_SYNC_CAUSE (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
921#define AR_INTR_SYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
933 922
934#define AR_INTR_SYNC_CAUSE 0x4028
935 923
936#define AR_INTR_SYNC_ENABLE 0x402c 924#define AR_INTR_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
937#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 925#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
938#define AR_INTR_SYNC_ENABLE_GPIO_S 18 926#define AR_INTR_SYNC_ENABLE_GPIO_S 18
939 927
@@ -973,24 +961,24 @@ enum {
973 961
974}; 962};
975 963
976#define AR_INTR_ASYNC_MASK 0x4030 964#define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
977#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 965#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000
978#define AR_INTR_ASYNC_MASK_GPIO_S 18 966#define AR_INTR_ASYNC_MASK_GPIO_S 18
979 967
980#define AR_INTR_SYNC_MASK 0x4034 968#define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034)
981#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 969#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
982#define AR_INTR_SYNC_MASK_GPIO_S 18 970#define AR_INTR_SYNC_MASK_GPIO_S 18
983 971
984#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 972#define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
985#define AR_INTR_ASYNC_CAUSE 0x4038 973#define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
986 974
987#define AR_INTR_ASYNC_ENABLE 0x403c 975#define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
988#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 976#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000
989#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 977#define AR_INTR_ASYNC_ENABLE_GPIO_S 18
990 978
991#define AR_PCIE_SERDES 0x4040 979#define AR_PCIE_SERDES 0x4040
992#define AR_PCIE_SERDES2 0x4044 980#define AR_PCIE_SERDES2 0x4044
993#define AR_PCIE_PM_CTRL 0x4014 981#define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
994#define AR_PCIE_PM_CTRL_ENA 0x00080000 982#define AR_PCIE_PM_CTRL_ENA 0x00080000
995 983
996#define AR_NUM_GPIO 14 984#define AR_NUM_GPIO 14
@@ -1001,7 +989,7 @@ enum {
1001#define AR9300_NUM_GPIO 17 989#define AR9300_NUM_GPIO 17
1002#define AR7010_NUM_GPIO 16 990#define AR7010_NUM_GPIO 16
1003 991
1004#define AR_GPIO_IN_OUT 0x4048 992#define AR_GPIO_IN_OUT (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
1005#define AR_GPIO_IN_VAL 0x0FFFC000 993#define AR_GPIO_IN_VAL 0x0FFFC000
1006#define AR_GPIO_IN_VAL_S 14 994#define AR_GPIO_IN_VAL_S 14
1007#define AR928X_GPIO_IN_VAL 0x000FFC00 995#define AR928X_GPIO_IN_VAL 0x000FFC00
@@ -1012,12 +1000,15 @@ enum {
1012#define AR9287_GPIO_IN_VAL_S 11 1000#define AR9287_GPIO_IN_VAL_S 11
1013#define AR9271_GPIO_IN_VAL 0xFFFF0000 1001#define AR9271_GPIO_IN_VAL 0xFFFF0000
1014#define AR9271_GPIO_IN_VAL_S 16 1002#define AR9271_GPIO_IN_VAL_S 16
1015#define AR9300_GPIO_IN_VAL 0x0001FFFF
1016#define AR9300_GPIO_IN_VAL_S 0
1017#define AR7010_GPIO_IN_VAL 0x0000FFFF 1003#define AR7010_GPIO_IN_VAL 0x0000FFFF
1018#define AR7010_GPIO_IN_VAL_S 0 1004#define AR7010_GPIO_IN_VAL_S 0
1019 1005
1020#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c) 1006#define AR_GPIO_IN (AR_SREV_9340(ah) ? 0x402c : 0x404c)
1007#define AR9300_GPIO_IN_VAL 0x0001FFFF
1008#define AR9300_GPIO_IN_VAL_S 0
1009
1010#define AR_GPIO_OE_OUT (AR_SREV_9340(ah) ? 0x4030 : \
1011 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
1021#define AR_GPIO_OE_OUT_DRV 0x3 1012#define AR_GPIO_OE_OUT_DRV 0x3
1022#define AR_GPIO_OE_OUT_DRV_NO 0x0 1013#define AR_GPIO_OE_OUT_DRV_NO 0x0
1023#define AR_GPIO_OE_OUT_DRV_LOW 0x1 1014#define AR_GPIO_OE_OUT_DRV_LOW 0x1
@@ -1039,11 +1030,13 @@ enum {
1039#define AR7010_GPIO_INT_MASK 0x52024 1030#define AR7010_GPIO_INT_MASK 0x52024
1040#define AR7010_GPIO_FUNCTION 0x52028 1031#define AR7010_GPIO_FUNCTION 0x52028
1041 1032
1042#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050) 1033#define AR_GPIO_INTR_POL (AR_SREV_9340(ah) ? 0x4038 : \
1034 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
1043#define AR_GPIO_INTR_POL_VAL 0x0001FFFF 1035#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
1044#define AR_GPIO_INTR_POL_VAL_S 0 1036#define AR_GPIO_INTR_POL_VAL_S 0
1045 1037
1046#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054) 1038#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9340(ah) ? 0x403c : \
1039 (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
1047#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 1040#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
1048#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 1041#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
1049#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 1042#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
@@ -1061,13 +1054,15 @@ enum {
1061#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 1054#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
1062#define AR_GPIO_JTAG_DISABLE 0x00020000 1055#define AR_GPIO_JTAG_DISABLE 0x00020000
1063 1056
1064#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058) 1057#define AR_GPIO_INPUT_MUX1 (AR_SREV_9340(ah) ? 0x4040 : \
1058 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
1065#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 1059#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
1066#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 1060#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
1067#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 1061#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
1068#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 1062#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
1069 1063
1070#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c) 1064#define AR_GPIO_INPUT_MUX2 (AR_SREV_9340(ah) ? 0x4044 : \
1065 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
1071#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 1066#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
1072#define AR_GPIO_INPUT_MUX2_CLK25_S 0 1067#define AR_GPIO_INPUT_MUX2_CLK25_S 0
1073#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 1068#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
@@ -1075,13 +1070,18 @@ enum {
1075#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 1070#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
1076#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 1071#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
1077 1072
1078#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060) 1073#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9340(ah) ? 0x4048 : \
1079#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064) 1074 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
1080#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068) 1075#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9340(ah) ? 0x404c : \
1076 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
1077#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9340(ah) ? 0x4050 : \
1078 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
1081 1079
1082#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c) 1080#define AR_INPUT_STATE (AR_SREV_9340(ah) ? 0x4054 : \
1081 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
1083 1082
1084#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c) 1083#define AR_EEPROM_STATUS_DATA (AR_SREV_9340(ah) ? 0x40c8 : \
1084 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
1085#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1085#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
1086#define AR_EEPROM_STATUS_DATA_VAL_S 0 1086#define AR_EEPROM_STATUS_DATA_VAL_S 0
1087#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1087#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
@@ -1089,17 +1089,54 @@ enum {
1089#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1089#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
1090#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1090#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
1091 1091
1092#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080) 1092#define AR_OBS (AR_SREV_9340(ah) ? 0x405c : \
1093 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
1093 1094
1094#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088) 1095#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
1095 1096
1096#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094) 1097#define AR_PCIE_MSI (AR_SREV_9340(ah) ? 0x40d8 : \
1098 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
1097#define AR_PCIE_MSI_ENABLE 0x00000001 1099#define AR_PCIE_MSI_ENABLE 0x00000001
1098 1100
1099#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 1101#define AR_INTR_PRIO_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
1100#define AR_INTR_PRIO_ASYNC_MASK 0x40c8 1102#define AR_INTR_PRIO_ASYNC_MASK (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
1101#define AR_INTR_PRIO_SYNC_MASK 0x40cc 1103#define AR_INTR_PRIO_SYNC_MASK (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
1102#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 1104#define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
1105#define AR_ENT_OTP 0x40d8
1106#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
1107#define AR_ENT_OTP_MPSD 0x00800000
1108
1109#define AR_CH0_BB_DPLL1 0x16180
1110#define AR_CH0_BB_DPLL1_REFDIV 0xF8000000
1111#define AR_CH0_BB_DPLL1_REFDIV_S 27
1112#define AR_CH0_BB_DPLL1_NINI 0x07FC0000
1113#define AR_CH0_BB_DPLL1_NINI_S 18
1114#define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF
1115#define AR_CH0_BB_DPLL1_NFRAC_S 0
1116
1117#define AR_CH0_BB_DPLL2 0x16184
1118#define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000
1119#define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30
1120#define AR_CH0_DPLL2_KI 0x3C000000
1121#define AR_CH0_DPLL2_KI_S 26
1122#define AR_CH0_DPLL2_KD 0x03F80000
1123#define AR_CH0_DPLL2_KD_S 19
1124#define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000
1125#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
1126#define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000
1127#define AR_CH0_BB_DPLL2_PLL_PWD_S 16
1128#define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000
1129#define AR_CH0_BB_DPLL2_OUTDIV_S 13
1130
1131#define AR_CH0_BB_DPLL3 0x16188
1132#define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000
1133#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23
1134
1135#define AR_CH0_DDR_DPLL2 0x16244
1136#define AR_CH0_DDR_DPLL3 0x16248
1137#define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000
1138#define AR_CH0_DPLL3_PHASE_SHIFT_S 23
1139#define AR_PHY_CCA_NOM_VAL_2GHZ -118
1103 1140
1104#define AR_RTC_9300_PLL_DIV 0x000003ff 1141#define AR_RTC_9300_PLL_DIV 0x000003ff
1105#define AR_RTC_9300_PLL_DIV_S 0 1142#define AR_RTC_9300_PLL_DIV_S 0
@@ -1137,12 +1174,21 @@ enum {
1137#define AR_RTC_PLL_CONTROL \ 1174#define AR_RTC_PLL_CONTROL \
1138 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1175 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
1139 1176
1177#define AR_RTC_PLL_CONTROL2 0x703c
1178
1140#define AR_RTC_PLL_DIV 0x0000001f 1179#define AR_RTC_PLL_DIV 0x0000001f
1141#define AR_RTC_PLL_DIV_S 0 1180#define AR_RTC_PLL_DIV_S 0
1142#define AR_RTC_PLL_DIV2 0x00000020 1181#define AR_RTC_PLL_DIV2 0x00000020
1143#define AR_RTC_PLL_REFDIV_5 0x000000c0 1182#define AR_RTC_PLL_REFDIV_5 0x000000c0
1144#define AR_RTC_PLL_CLKSEL 0x00000300 1183#define AR_RTC_PLL_CLKSEL 0x00000300
1145#define AR_RTC_PLL_CLKSEL_S 8 1184#define AR_RTC_PLL_CLKSEL_S 8
1185#define AR_RTC_PLL_BYPASS 0x00010000
1186
1187#define PLL3 0x16188
1188#define PLL3_DO_MEAS_MASK 0x40000000
1189#define PLL4 0x1618c
1190#define PLL4_MEAS_DONE 0x8
1191#define SQSUM_DVC_MASK 0x007ffff8
1146 1192
1147#define AR_RTC_RESET \ 1193#define AR_RTC_RESET \
1148 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 1194 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
@@ -1183,7 +1229,8 @@ enum {
1183 1229
1184/* RTC_DERIVED_* - only for AR9100 */ 1230/* RTC_DERIVED_* - only for AR9100 */
1185 1231
1186#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 1232#define AR_RTC_DERIVED_CLK \
1233 (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
1187#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 1234#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe
1188#define AR_RTC_DERIVED_CLK_PERIOD_S 1 1235#define AR_RTC_DERIVED_CLK_PERIOD_S 1
1189 1236
@@ -1389,6 +1436,7 @@ enum {
1389#define AR_STA_ID1_PCF 0x00100000 1436#define AR_STA_ID1_PCF 0x00100000
1390#define AR_STA_ID1_USE_DEFANT 0x00200000 1437#define AR_STA_ID1_USE_DEFANT 0x00200000
1391#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1438#define AR_STA_ID1_DEFANT_UPDATE 0x00400000
1439#define AR_STA_ID1_AR9100_BA_FIX 0x00400000
1392#define AR_STA_ID1_RTS_USE_DEF 0x00800000 1440#define AR_STA_ID1_RTS_USE_DEF 0x00800000
1393#define AR_STA_ID1_ACKCTS_6MB 0x01000000 1441#define AR_STA_ID1_ACKCTS_6MB 0x01000000
1394#define AR_STA_ID1_BASE_RATE_11B 0x02000000 1442#define AR_STA_ID1_BASE_RATE_11B 0x02000000
@@ -1550,11 +1598,6 @@ enum {
1550#define AR_TPC_CHIRP 0x003f0000 1598#define AR_TPC_CHIRP 0x003f0000
1551#define AR_TPC_CHIRP_S 0x16 1599#define AR_TPC_CHIRP_S 0x16
1552 1600
1553#define AR_TFCNT 0x80ec
1554#define AR_RFCNT 0x80f0
1555#define AR_RCCNT 0x80f4
1556#define AR_CCCNT 0x80f8
1557
1558#define AR_QUIET1 0x80fc 1601#define AR_QUIET1 0x80fc
1559#define AR_QUIET1_NEXT_QUIET_S 0 1602#define AR_QUIET1_NEXT_QUIET_S 0
1560#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1603#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
@@ -1605,6 +1648,7 @@ enum {
1605#define AR_PCU_TBTT_PROTECT 0x00200000 1648#define AR_PCU_TBTT_PROTECT 0x00200000
1606#define AR_PCU_CLEAR_VMF 0x01000000 1649#define AR_PCU_CLEAR_VMF 0x01000000
1607#define AR_PCU_CLEAR_BA_VALID 0x04000000 1650#define AR_PCU_CLEAR_BA_VALID 0x04000000
1651#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
1608 1652
1609#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1653#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
1610#define AR_PCU_BT_ANT_PREVENT_RX_S 20 1654#define AR_PCU_BT_ANT_PREVENT_RX_S 20
@@ -1665,6 +1709,22 @@ enum {
1665#define AR_BTCOEX_WL_WGHT 0xffff0000 1709#define AR_BTCOEX_WL_WGHT 0xffff0000
1666#define AR_BTCOEX_WL_WGHT_S 16 1710#define AR_BTCOEX_WL_WGHT_S 16
1667 1711
1712#define AR_BT_COEX_WL_WEIGHTS0 0x8174
1713#define AR_BT_COEX_WL_WEIGHTS1 0x81c4
1714
1715#define AR_BT_COEX_BT_WEIGHTS0 0x83ac
1716#define AR_BT_COEX_BT_WEIGHTS1 0x83b0
1717#define AR_BT_COEX_BT_WEIGHTS2 0x83b4
1718#define AR_BT_COEX_BT_WEIGHTS3 0x83b8
1719
1720#define AR9300_BT_WGHT 0xcccc4444
1721#define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0
1722#define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0
1723#define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880
1724#define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880
1725#define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000
1726#define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000
1727
1668#define AR_BT_COEX_MODE2 0x817c 1728#define AR_BT_COEX_MODE2 0x817c
1669#define AR_BT_BCN_MISS_THRESH 0x000000ff 1729#define AR_BT_BCN_MISS_THRESH 0x000000ff
1670#define AR_BT_BCN_MISS_THRESH_S 0 1730#define AR_BT_BCN_MISS_THRESH_S 0
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 12:35:24 -0400