1 files changed, 161 insertions, 129 deletions

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 399f7c1283cd..4b157c53d1a8 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -30,7 +30,6 @@
 #include "btcoex.h"
 
 #include "../regd.h"
-#include "../debug.h"
 
 #define ATHEROS_VENDOR_ID       0x168c
 
@@ -44,6 +43,8 @@
 #define AR9287_DEVID_PCI        0x002d
 #define AR9287_DEVID_PCIE       0x002e
 #define AR9300_DEVID_PCIE       0x0030
+#define AR9300_DEVID_AR9340     0x0031
+#define AR9300_DEVID_AR9485_PCIE 0x0032
 
 #define AR5416_AR9100_DEVID     0x000b
 
@@ -55,64 +56,62 @@
 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
 
+#define AR9300_NUM_BT_WEIGHTS   4
+#define AR9300_NUM_WLAN_WEIGHTS 4
+
 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 
 #define ATH_DEFAULT_NOISE_FLOOR -95
 
 #define ATH9K_RSSI_BAD                  -128
 
+#define ATH9K_NUM_CHANNELS      38
+
 /* Register read/write primitives */
 #define REG_WRITE(_ah, _reg, _val) \
-        ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
+        (_ah)->reg_ops.write((_ah), (_val), (_reg))
 
 #define REG_READ(_ah, _reg) \
-        ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
+        (_ah)->reg_ops.read((_ah), (_reg))
 
-#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
-        do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
-        } while (0)
+#define REG_READ_MULTI(_ah, _addr, _val, _cnt)          \
+        (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
+
+#define REG_RMW(_ah, _reg, _set, _clr) \
+        (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
 
-#define DISABLE_REGWRITE_BUFFER(_ah)                                    \
+#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
         do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
+                if ((_ah)->reg_ops.enable_write_buffer) \
+                        (_ah)->reg_ops.enable_write_buffer((_ah)); \
         } while (0)
 
 #define REGWRITE_BUFFER_FLUSH(_ah)                                      \
         do {                                                            \
-                if (AR_SREV_9271(_ah))                                  \
-                        ath9k_hw_common(_ah)->ops->write_flush((_ah));  \
+                if ((_ah)->reg_ops.write_flush)         \
+                        (_ah)->reg_ops.write_flush((_ah));      \
         } while (0)
 
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
-#define REG_RMW(_a, _r, _set, _clr)    \
-        REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
 #define REG_RMW_FIELD(_a, _r, _f, _v) \
-        REG_WRITE(_a, _r, \
-        (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
+        REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
 #define REG_READ_FIELD(_a, _r, _f) \
         (((REG_READ(_a, _r) & _f) >> _f##_S))
 #define REG_SET_BIT(_a, _r, _f) \
-        REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
+        REG_RMW(_a, _r, (_f), 0)
 #define REG_CLR_BIT(_a, _r, _f) \
-        REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
+        REG_RMW(_a, _r, 0, (_f))
 
-#define DO_DELAY(x) do {                        \
-                if ((++(x) % 64) == 0)          \
-                        udelay(1);              \
+#define DO_DELAY(x) do {                                        \
+                if (((++(x) % 64) == 0) &&                      \
+                    (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
+                        != ATH_USB))                            \
+                        udelay(1);                              \
         } while (0)
 
-#define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
-                int r;                                                  \
-                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
-                        REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
-                                  INI_RA((iniarray), r, (column)));     \
-                        DO_DELAY(regWr);                                \
-                }                                                       \
-        } while (0)
+#define REG_WRITE_ARRAY(iniarray, column, regWr) \
+        ath9k_hw_write_array(ah, iniarray, column, &(regWr))
 
 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
@@ -126,7 +125,7 @@
 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 
 #define BASE_ACTIVATE_DELAY         100
-#define RTC_PLL_SETTLE_DELAY        100
+#define RTC_PLL_SETTLE_DELAY        (AR_SREV_9340(ah) ? 1000 : 100)
 #define COEF_SCALE_S                24
 #define HT40_CHANNEL_CENTER_SHIFT   10
 
@@ -161,6 +160,13 @@
 #define PAPRD_GAIN_TABLE_ENTRIES    32
 #define PAPRD_TABLE_SZ              24
 
+enum ath_hw_txq_subtype {
+        ATH_TXQ_AC_BE = 0,
+        ATH_TXQ_AC_BK = 1,
+        ATH_TXQ_AC_VI = 2,
+        ATH_TXQ_AC_VO = 3,
+};
+
 enum ath_ini_subsys {
         ATH_INI_PRE = 0,
         ATH_INI_CORE,
@@ -168,64 +174,39 @@ enum ath_ini_subsys {
         ATH_INI_NUM_SPLIT,
 };
 
-enum wireless_mode {
-        ATH9K_MODE_11A = 0,
-        ATH9K_MODE_11G,
-        ATH9K_MODE_11NA_HT20,
-        ATH9K_MODE_11NG_HT20,
-        ATH9K_MODE_11NA_HT40PLUS,
-        ATH9K_MODE_11NA_HT40MINUS,
-        ATH9K_MODE_11NG_HT40PLUS,
-        ATH9K_MODE_11NG_HT40MINUS,
-        ATH9K_MODE_MAX,
-};
-
 enum ath9k_hw_caps {
-        ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
-        ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
-        ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
-        ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
-        ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
-        ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
-        ATH9K_HW_CAP_VEOL                       = BIT(6),
-        ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
-        ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
-        ATH9K_HW_CAP_HT                         = BIT(9),
-        ATH9K_HW_CAP_GTT                        = BIT(10),
-        ATH9K_HW_CAP_FASTCC                     = BIT(11),
-        ATH9K_HW_CAP_RFSILENT                   = BIT(12),
-        ATH9K_HW_CAP_CST                        = BIT(13),
-        ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
-        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
-        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
-        ATH9K_HW_CAP_EDMA                       = BIT(17),
-        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(18),
-        ATH9K_HW_CAP_LDPC                       = BIT(19),
-        ATH9K_HW_CAP_FASTCLOCK                  = BIT(20),
-        ATH9K_HW_CAP_SGI_20                     = BIT(21),
-        ATH9K_HW_CAP_PAPRD                      = BIT(22),
+        ATH9K_HW_CAP_HT                         = BIT(0),
+        ATH9K_HW_CAP_RFSILENT                   = BIT(1),
+        ATH9K_HW_CAP_CST                        = BIT(2),
+        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
+        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
+        ATH9K_HW_CAP_EDMA                       = BIT(6),
+        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(7),
+        ATH9K_HW_CAP_LDPC                       = BIT(8),
+        ATH9K_HW_CAP_FASTCLOCK                  = BIT(9),
+        ATH9K_HW_CAP_SGI_20                     = BIT(10),
+        ATH9K_HW_CAP_PAPRD                      = BIT(11),
+        ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
+        ATH9K_HW_CAP_2GHZ                       = BIT(13),
+        ATH9K_HW_CAP_5GHZ                       = BIT(14),
+        ATH9K_HW_CAP_APM                        = BIT(15),
 };
 
 struct ath9k_hw_capabilities {
         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
-        DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
-        u16 total_queues;
-        u16 keycache_size;
-        u16 low_5ghz_chan, high_5ghz_chan;
-        u16 low_2ghz_chan, high_2ghz_chan;
         u16 rts_aggr_limit;
         u8 tx_chainmask;
         u8 rx_chainmask;
-        u16 tx_triglevel_max;
-        u16 reg_cap;
+        u8 max_txchains;
+        u8 max_rxchains;
         u8 num_gpio_pins;
-        u8 num_antcfg_2ghz;
-        u8 num_antcfg_5ghz;
         u8 rx_hp_qdepth;
         u8 rx_lp_qdepth;
         u8 rx_status_len;
         u8 tx_desc_len;
         u8 txs_len;
+        u16 pcie_lcr_offset;
+        bool pcie_lcr_extsync_en;
 };
 
 struct ath9k_ops_config {
@@ -239,7 +220,7 @@ struct ath9k_ops_config {
         u8 pcie_clock_req;
         u32 pcie_waen;
         u8 analog_shiftreg;
-        u8 ht_enable;
+        u8 paprd_disable;
         u32 ofdm_trig_low;
         u32 ofdm_trig_high;
         u32 cck_trig_high;
@@ -251,7 +232,6 @@ struct ath9k_ops_config {
 #define SPUR_DISABLE            0
 #define SPUR_ENABLE_IOCTL       1
 #define SPUR_ENABLE_EEPROM      2
-#define AR_EEPROM_MODAL_SPURS   5
 #define AR_SPUR_5413_1          1640
 #define AR_SPUR_5413_2          1200
 #define AR_NO_SPUR              0x8000
@@ -352,9 +332,9 @@ struct ath9k_hw_cal_data {
         int32_t CalValid;
         int8_t iCoff;
         int8_t qCoff;
-        int16_t rawNoiseFloor;
         bool paprd_done;
         bool nfcal_pending;
+        bool nfcal_interference;
         u16 small_signal_gain[AR9300_MAX_CHAINS];
         u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
@@ -362,9 +342,11 @@ struct ath9k_hw_cal_data {
 
 struct ath9k_channel {
         struct ieee80211_channel *chan;
+        struct ar5416AniState ani;
         u16 channel;
         u32 channelFlags;
         u32 chanmode;
+        s16 noisefloor;
 };
 
 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
@@ -422,8 +404,6 @@ struct ath9k_beacon_state {
         u32 bs_nextdtim;
         u32 bs_intval;
 #define ATH9K_BEACON_PERIOD       0x0000ffff
-#define ATH9K_BEACON_ENA          0x00800000
-#define ATH9K_BEACON_RESET_TSF    0x01000000
 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
         u32 bs_dtimperiod;
         u16 bs_cfpperiod;
@@ -457,6 +437,7 @@ struct ath9k_hw_version {
         u16 analog5GhzRev;
         u16 analog2GhzRev;
         u16 subsysid;
+        enum ath_usb_dev usbdev;
 };
 
 /* Generic TSF timer definitions */
@@ -494,6 +475,50 @@ struct ath_gen_timer_table {
         } timer_mask;
 };
 
+struct ath_hw_antcomb_conf {
+        u8 main_lna_conf;
+        u8 alt_lna_conf;
+        u8 fast_div_bias;
+        u8 main_gaintb;
+        u8 alt_gaintb;
+        int lna1_lna2_delta;
+        u8 div_group;
+};
+
+/**
+ * struct ath_hw_radar_conf - radar detection initialization parameters
+ *
+ * @pulse_inband: threshold for checking the ratio of in-band power
+ *      to total power for short radar pulses (half dB steps)
+ * @pulse_inband_step: threshold for checking an in-band power to total
+ *      power ratio increase for short radar pulses (half dB steps)
+ * @pulse_height: threshold for detecting the beginning of a short
+ *      radar pulse (dB step)
+ * @pulse_rssi: threshold for detecting if a short radar pulse is
+ *      gone (dB step)
+ * @pulse_maxlen: maximum pulse length (0.8 us steps)
+ *
+ * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
+ * @radar_inband: threshold for checking the ratio of in-band power
+ *      to total power for long radar pulses (half dB steps)
+ * @fir_power: threshold for detecting the end of a long radar pulse (dB)
+ *
+ * @ext_channel: enable extension channel radar detection
+ */
+struct ath_hw_radar_conf {
+        unsigned int pulse_inband;
+        unsigned int pulse_inband_step;
+        unsigned int pulse_height;
+        unsigned int pulse_rssi;
+        unsigned int pulse_maxlen;
+
+        unsigned int radar_rssi;
+        unsigned int radar_inband;
+        int fir_power;
+
+        bool ext_channel;
+};
+
 /**
  * struct ath_hw_private_ops - callbacks used internally by hardware code
  *
@@ -505,7 +530,6 @@ struct ath_gen_timer_table {
  *
  * @init_mode_regs: Initializes mode registers
  * @init_mode_gain_regs: Initialize TX/RX gain registers
- * @macversion_supported: If this specific mac revision is supported
  *
  * @rf_set_freq: change frequency
  * @spur_mitigate_freq: spur mitigation
@@ -517,14 +541,6 @@ struct ath_gen_timer_table {
  * @setup_calibration: set up calibration
  * @iscal_supported: used to query if a type of calibration is supported
  *
- * @ani_reset: reset ANI parameters to default values
- * @ani_lower_immunity: lower the noise immunity level. The level controls
- *      the power-based packet detection on hardware. If a power jump is
- *      detected the adapter takes it as an indication that a packet has
- *      arrived. The level ranges from 0-5. Each level corresponds to a
- *      few dB more of noise immunity. If you have a strong time-varying
- *      interference that is causing false detections (OFDM timing errors or
- *      CCK timing errors) the level can be increased.
  * @ani_cache_ini_regs: cache the values for ANI from the initial
  *      register settings through the register initialization.
  */
@@ -535,11 +551,8 @@ struct ath_hw_private_ops {
 
         void (*init_mode_regs)(struct ath_hw *ah);
         void (*init_mode_gain_regs)(struct ath_hw *ah);
-        bool (*macversion_supported)(u32 macversion);
         void (*setup_calibration)(struct ath_hw *ah,
                                   struct ath9k_cal_list *currCal);
-        bool (*iscal_supported)(struct ath_hw *ah,
-                                enum ath9k_cal_types calType);
 
         /* PHY ops */
         int (*rf_set_freq)(struct ath_hw *ah,
@@ -561,7 +574,6 @@ struct ath_hw_private_ops {
         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
         bool (*rfbus_req)(struct ath_hw *ah);
         void (*rfbus_done)(struct ath_hw *ah);
-        void (*enable_rfkill)(struct ath_hw *ah);
         void (*restore_chainmask)(struct ath_hw *ah);
         void (*set_diversity)(struct ath_hw *ah, bool value);
         u32 (*compute_pll_control)(struct ath_hw *ah,
@@ -569,10 +581,10 @@ struct ath_hw_private_ops {
         bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
                             int param);
         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
+        void (*set_radar_params)(struct ath_hw *ah,
+                                 struct ath_hw_radar_conf *conf);
 
         /* ANI */
-        void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
-        void (*ani_lower_immunity)(struct ath_hw *ah);
         void (*ani_cache_ini_regs)(struct ath_hw *ah);
 };
 
@@ -584,11 +596,6 @@ struct ath_hw_private_ops {
  *
  * @config_pci_powersave:
  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
- *
- * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
- *      thresholds being reached or having overflowed.
- * @ani_monitor: called periodically by the core driver to collect
- *      MIB stats and adjust ANI if specific thresholds have been reached.
  */
 struct ath_hw_ops {
         void (*config_pci_powersave)(struct ath_hw *ah,
@@ -625,13 +632,12 @@ struct ath_hw_ops {
                                    u32 numDelims);
         void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
         void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
-        void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
-                                     u32 burstDuration);
-        void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
-                                       u32 vmf);
+        void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
+        void (*antdiv_comb_conf_get)(struct ath_hw *ah,
+                        struct ath_hw_antcomb_conf *antconf);
+        void (*antdiv_comb_conf_set)(struct ath_hw *ah,
+                        struct ath_hw_antcomb_conf *antconf);
 
-        void (*ani_proc_mib_event)(struct ath_hw *ah);
-        void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
 };
 
 struct ath_nf_limits {
@@ -640,13 +646,19 @@ struct ath_nf_limits {
         s16 nominal;
 };
 
+/* ah_flags */
+#define AH_USE_EEPROM   0x1
+#define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
+
 struct ath_hw {
+        struct ath_ops reg_ops;
+
         struct ieee80211_hw *hw;
         struct ath_common common;
         struct ath9k_hw_version hw_version;
         struct ath9k_ops_config config;
         struct ath9k_hw_capabilities caps;
-        struct ath9k_channel channels[38];
+        struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
         struct ath9k_channel *curchan;
 
         union {
@@ -659,6 +671,7 @@ struct ath_hw {
 
         bool sw_mgmt_crypto;
         bool is_pciexpress;
+        bool is_monitoring;
         bool need_an_top2_fixup;
         u16 tx_trig_level;
 
@@ -692,10 +705,9 @@ struct ath_hw {
         u32 atim_window;
 
         /* Calibration */
-        enum ath9k_cal_types supp_cals;
+        u32 supp_cals;
         struct ath9k_cal_list iq_caldata;
         struct ath9k_cal_list adcgain_caldata;
-        struct ath9k_cal_list adcdc_calinitdata;
         struct ath9k_cal_list adcdc_caldata;
         struct ath9k_cal_list tempCompCalData;
         struct ath9k_cal_list *cal_list;
@@ -755,17 +767,13 @@ struct ath_hw {
         u32 *bank6Temp;
 
         u8 txpower_limit;
-        int16_t txpower_indexoffset;
         int coverage_class;
-        u32 beacon_interval;
         u32 slottime;
         u32 globaltxtimeout;
 
         /* ANI */
         u32 proc_phyerr;
         u32 aniperiod;
-        struct ar5416AniState *curani;
-        struct ar5416AniState ani[255];
         int totalSizeDesired[5];
         int coarse_high[5];
         int coarse_low[5];
@@ -774,15 +782,21 @@ struct ath_hw {
 
         /* Bluetooth coexistance */
         struct ath_btcoex_hw btcoex_hw;
+        u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
+        u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
 
         u32 intr_txqs;
         u8 txchainmask;
         u8 rxchainmask;
 
+        struct ath_hw_radar_conf radar_conf;
+
         u32 originalGain[22];
         int initPDADC;
         int PDADCdelta;
-        u8 led_pin;
+        int led_pin;
+        u32 gpio_mask;
+        u32 gpio_val;
 
         struct ar5416IniArray iniModes;
         struct ar5416IniArray iniCommon;
@@ -798,6 +812,7 @@ struct ath_hw {
         struct ar5416IniArray iniPcieSerdes;
         struct ar5416IniArray iniPcieSerdesLowPower;
         struct ar5416IniArray iniModesAdditional;
+        struct ar5416IniArray iniModesAdditional_40M;
         struct ar5416IniArray iniModesRxGain;
         struct ar5416IniArray iniModesTxGain;
         struct ar5416IniArray iniModes_9271_1_0_only;
@@ -827,7 +842,13 @@ struct ath_hw {
 
         u32 bb_watchdog_last_status;
         u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
+        u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
 
+        unsigned int paprd_target_power;
+        unsigned int paprd_training_power;
+        unsigned int paprd_ratemask;
+        unsigned int paprd_ratemask_ht40;
+        bool paprd_table_write_done;
         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
         /*
@@ -836,6 +857,19 @@ struct ath_hw {
          * this register when in sleep states.
          */
         u32 WARegVal;
+
+        /* Enterprise mode cap */
+        u32 ent_mode;
+
+        bool is_clk_25mhz;
+};
+
+struct ath_bus_ops {
+        enum ath_bus_type ath_bus_type;
+        void (*read_cachesize)(struct ath_common *common, int *csz);
+        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
+        void (*bt_coex_prep)(struct ath_common *common);
+        void (*extn_synch_en)(struct ath_common *common);
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -858,10 +892,9 @@ static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
         return &ah->ops;
 }
 
-static inline int sign_extend(int val, const int nbits)
+static inline u8 get_streams(int mask)
 {
-        int order = BIT(nbits-1);
-        return (val ^ order) - order;
+        return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
 }
 
 /* Initialization, Detach, Reset */
@@ -873,12 +906,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 
-/* Key Cache Management */
-bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
-bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
-                                 const struct ath9k_keyval *k,
-                                 const u8 *mac);
-
 /* GPIO / RFKILL / Antennae */
 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
@@ -890,8 +917,9 @@ void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 
 /* General Operation */
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
+void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
+                          int column, unsigned int *writecnt);
 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
-bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                            u8 phy, int kbps,
                            u32 frameLen, u16 rateix, bool shortPreamble);
@@ -902,16 +930,18 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 bool ath9k_hw_disable(struct ath_hw *ah);
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
 void ath9k_hw_setopmode(struct ath_hw *ah);
 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 void ath9k_hw_write_associd(struct ath_hw *ah);
+u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 void ath9k_hw_init_global_settings(struct ath_hw *ah);
+u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
@@ -934,7 +964,6 @@ void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 
 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 void ath_gen_timer_isr(struct ath_hw *hw);
-u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 
 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 
@@ -962,6 +991,7 @@ void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
+void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
                                         struct ath9k_hw_cal_data *caldata,
@@ -984,6 +1014,7 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
 void ar9002_hw_attach_ops(struct ath_hw *ah);
 void ar9003_hw_attach_ops(struct ath_hw *ah);
 
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
 /*
  * ANI work can be shared between all families but a next
  * generation implementation of ANI will be used only for AR9003 only
@@ -992,8 +1023,9 @@ void ar9003_hw_attach_ops(struct ath_hw *ah);
  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
  */
 extern int modparam_force_new_ani;
-void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
-void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah);
+void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
+void ath9k_hw_proc_mib_event(struct ath_hw *ah);
+void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
 
 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 #define ATH_PCIE_CAP_LINK_L0S   1