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path: root/drivers/net/wireless/ath/ath9k/eeprom.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c259
1 files changed, 252 insertions, 7 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 1266333f586d..e61404dda8c5 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -89,6 +89,38 @@ bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
89 return false; 89 return false;
90} 90}
91 91
92void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
93 int eep_start_loc, int size)
94{
95 int i = 0, j, addr;
96 u32 addrdata[8];
97 u32 data[8];
98
99 for (addr = 0; addr < size; addr++) {
100 addrdata[i] = AR5416_EEPROM_OFFSET +
101 ((addr + eep_start_loc) << AR5416_EEPROM_S);
102 i++;
103 if (i == 8) {
104 REG_READ_MULTI(ah, addrdata, data, i);
105
106 for (j = 0; j < i; j++) {
107 *eep_data = data[j];
108 eep_data++;
109 }
110 i = 0;
111 }
112 }
113
114 if (i != 0) {
115 REG_READ_MULTI(ah, addrdata, data, i);
116
117 for (j = 0; j < i; j++) {
118 *eep_data = data[j];
119 eep_data++;
120 }
121 }
122}
123
92bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data) 124bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
93{ 125{
94 return common->bus_ops->eeprom_read(common, off, data); 126 return common->bus_ops->eeprom_read(common, off, data);
@@ -234,22 +266,22 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah,
234u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 266u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
235 bool is2GHz, int num_band_edges) 267 bool is2GHz, int num_band_edges)
236{ 268{
237 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 269 u16 twiceMaxEdgePower = MAX_RATE_POWER;
238 int i; 270 int i;
239 271
240 for (i = 0; (i < num_band_edges) && 272 for (i = 0; (i < num_band_edges) &&
241 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 273 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
242 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 274 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
243 twiceMaxEdgePower = pRdEdgesPower[i].tPower; 275 twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
244 break; 276 break;
245 } else if ((i > 0) && 277 } else if ((i > 0) &&
246 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, 278 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
247 is2GHz))) { 279 is2GHz))) {
248 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, 280 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
249 is2GHz) < freq && 281 is2GHz) < freq &&
250 pRdEdgesPower[i - 1].flag) { 282 CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
251 twiceMaxEdgePower = 283 twiceMaxEdgePower =
252 pRdEdgesPower[i - 1].tPower; 284 CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
253 } 285 }
254 break; 286 break;
255 } 287 }
@@ -273,12 +305,225 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
273 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 305 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
274 break; 306 break;
275 default: 307 default:
276 ath_print(common, ATH_DBG_EEPROM, 308 ath_dbg(common, ATH_DBG_EEPROM,
277 "Invalid chainmask configuration\n"); 309 "Invalid chainmask configuration\n");
278 break; 310 break;
279 } 311 }
280} 312}
281 313
314void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
315 struct ath9k_channel *chan,
316 void *pRawDataSet,
317 u8 *bChans, u16 availPiers,
318 u16 tPdGainOverlap,
319 u16 *pPdGainBoundaries, u8 *pPDADCValues,
320 u16 numXpdGains)
321{
322 int i, j, k;
323 int16_t ss;
324 u16 idxL = 0, idxR = 0, numPiers;
325 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
326 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
327 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
328 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
329 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
330 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
331
332 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
333 u8 minPwrT4[AR5416_NUM_PD_GAINS];
334 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
335 int16_t vpdStep;
336 int16_t tmpVal;
337 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
338 bool match;
339 int16_t minDelta = 0;
340 struct chan_centers centers;
341 int pdgain_boundary_default;
342 struct cal_data_per_freq *data_def = pRawDataSet;
343 struct cal_data_per_freq_4k *data_4k = pRawDataSet;
344 struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
345 bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
346 int intercepts;
347
348 if (AR_SREV_9287(ah))
349 intercepts = AR9287_PD_GAIN_ICEPTS;
350 else
351 intercepts = AR5416_PD_GAIN_ICEPTS;
352
353 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
354 ath9k_hw_get_channel_centers(ah, chan, &centers);
355
356 for (numPiers = 0; numPiers < availPiers; numPiers++) {
357 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
358 break;
359 }
360
361 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
362 IS_CHAN_2GHZ(chan)),
363 bChans, numPiers, &idxL, &idxR);
364
365 if (match) {
366 if (AR_SREV_9287(ah)) {
367 /* FIXME: array overrun? */
368 for (i = 0; i < numXpdGains; i++) {
369 minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
370 maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
371 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
372 data_9287[idxL].pwrPdg[i],
373 data_9287[idxL].vpdPdg[i],
374 intercepts,
375 vpdTableI[i]);
376 }
377 } else if (eeprom_4k) {
378 for (i = 0; i < numXpdGains; i++) {
379 minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
380 maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
381 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
382 data_4k[idxL].pwrPdg[i],
383 data_4k[idxL].vpdPdg[i],
384 intercepts,
385 vpdTableI[i]);
386 }
387 } else {
388 for (i = 0; i < numXpdGains; i++) {
389 minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
390 maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
391 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
392 data_def[idxL].pwrPdg[i],
393 data_def[idxL].vpdPdg[i],
394 intercepts,
395 vpdTableI[i]);
396 }
397 }
398 } else {
399 for (i = 0; i < numXpdGains; i++) {
400 if (AR_SREV_9287(ah)) {
401 pVpdL = data_9287[idxL].vpdPdg[i];
402 pPwrL = data_9287[idxL].pwrPdg[i];
403 pVpdR = data_9287[idxR].vpdPdg[i];
404 pPwrR = data_9287[idxR].pwrPdg[i];
405 } else if (eeprom_4k) {
406 pVpdL = data_4k[idxL].vpdPdg[i];
407 pPwrL = data_4k[idxL].pwrPdg[i];
408 pVpdR = data_4k[idxR].vpdPdg[i];
409 pPwrR = data_4k[idxR].pwrPdg[i];
410 } else {
411 pVpdL = data_def[idxL].vpdPdg[i];
412 pPwrL = data_def[idxL].pwrPdg[i];
413 pVpdR = data_def[idxR].vpdPdg[i];
414 pPwrR = data_def[idxR].pwrPdg[i];
415 }
416
417 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
418
419 maxPwrT4[i] =
420 min(pPwrL[intercepts - 1],
421 pPwrR[intercepts - 1]);
422
423
424 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
425 pPwrL, pVpdL,
426 intercepts,
427 vpdTableL[i]);
428 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
429 pPwrR, pVpdR,
430 intercepts,
431 vpdTableR[i]);
432
433 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
434 vpdTableI[i][j] =
435 (u8)(ath9k_hw_interpolate((u16)
436 FREQ2FBIN(centers.
437 synth_center,
438 IS_CHAN_2GHZ
439 (chan)),
440 bChans[idxL], bChans[idxR],
441 vpdTableL[i][j], vpdTableR[i][j]));
442 }
443 }
444 }
445
446 k = 0;
447
448 for (i = 0; i < numXpdGains; i++) {
449 if (i == (numXpdGains - 1))
450 pPdGainBoundaries[i] =
451 (u16)(maxPwrT4[i] / 2);
452 else
453 pPdGainBoundaries[i] =
454 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
455
456 pPdGainBoundaries[i] =
457 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
458
459 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
460 minDelta = pPdGainBoundaries[0] - 23;
461 pPdGainBoundaries[0] = 23;
462 } else {
463 minDelta = 0;
464 }
465
466 if (i == 0) {
467 if (AR_SREV_9280_20_OR_LATER(ah))
468 ss = (int16_t)(0 - (minPwrT4[i] / 2));
469 else
470 ss = 0;
471 } else {
472 ss = (int16_t)((pPdGainBoundaries[i - 1] -
473 (minPwrT4[i] / 2)) -
474 tPdGainOverlap + 1 + minDelta);
475 }
476 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
477 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
478
479 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
480 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
481 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
482 ss++;
483 }
484
485 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
486 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
487 (minPwrT4[i] / 2));
488 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
489 tgtIndex : sizeCurrVpdTable;
490
491 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
492 pPDADCValues[k++] = vpdTableI[i][ss++];
493 }
494
495 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
496 vpdTableI[i][sizeCurrVpdTable - 2]);
497 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
498
499 if (tgtIndex >= maxIndex) {
500 while ((ss <= tgtIndex) &&
501 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
502 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
503 (ss - maxIndex + 1) * vpdStep));
504 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
505 255 : tmpVal);
506 ss++;
507 }
508 }
509 }
510
511 if (eeprom_4k)
512 pdgain_boundary_default = 58;
513 else
514 pdgain_boundary_default = pPdGainBoundaries[i - 1];
515
516 while (i < AR5416_PD_GAINS_IN_MASK) {
517 pPdGainBoundaries[i] = pdgain_boundary_default;
518 i++;
519 }
520
521 while (k < AR5416_NUM_PDADC_VALUES) {
522 pPDADCValues[k] = pPDADCValues[k - 1];
523 k++;
524 }
525}
526
282int ath9k_hw_eeprom_init(struct ath_hw *ah) 527int ath9k_hw_eeprom_init(struct ath_hw *ah)
283{ 528{
284 int status; 529 int status;