1 files changed, 61 insertions, 77 deletions

diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index 55b4ac6d236f..d12b827033c1 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -26,7 +26,6 @@
  * Atheros presentations and papers like these:
  *
  * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
- *        http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
  *
  * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
  *
@@ -133,8 +132,8 @@
  * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
  * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
  * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
- * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i
- * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what
+ * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
+ * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what
  * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
  */
 #define AR5K_BSR                0x002c                  /* Register Address */
@@ -284,7 +283,7 @@
  */
 #define AR5K_ISR                0x001c                  /* Register Address [5210] */
 #define AR5K_PISR               0x0080                  /* Register Address [5211+] */
-#define AR5K_ISR_RXOK           0x00000001      /* Frame successfuly recieved */
+#define AR5K_ISR_RXOK           0x00000001      /* Frame successfuly received */
 #define AR5K_ISR_RXDESC         0x00000002      /* RX descriptor request */
 #define AR5K_ISR_RXERR          0x00000004      /* Receive error */
 #define AR5K_ISR_RXNOFRM        0x00000008      /* No frame received (receive timeout) */
@@ -373,12 +372,12 @@
 /*
  * Interrupt Mask Registers
  *
- * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
+ * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
  * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
  */
 #define AR5K_IMR                0x0020                  /* Register Address [5210] */
 #define AR5K_PIMR               0x00a0                  /* Register Address [5211+] */
-#define AR5K_IMR_RXOK           0x00000001      /* Frame successfuly recieved*/
+#define AR5K_IMR_RXOK           0x00000001      /* Frame successfuly received*/
 #define AR5K_IMR_RXDESC         0x00000002      /* RX descriptor request*/
 #define AR5K_IMR_RXERR          0x00000004      /* Receive error*/
 #define AR5K_IMR_RXNOFRM        0x00000008      /* No frame received (receive timeout)*/
@@ -687,16 +686,15 @@
 
 /*
  * DCU retry limit registers
+ * all these fields don't allow zero values
  */
 #define AR5K_DCU_RETRY_LMT_BASE         0x1080                  /* Register Address -Queue0 DCU_RETRY_LMT */
-#define AR5K_DCU_RETRY_LMT_SH_RETRY     0x0000000f      /* Short retry limit mask */
-#define AR5K_DCU_RETRY_LMT_SH_RETRY_S   0
-#define AR5K_DCU_RETRY_LMT_LG_RETRY     0x000000f0      /* Long retry limit mask */
-#define AR5K_DCU_RETRY_LMT_LG_RETRY_S   4
-#define AR5K_DCU_RETRY_LMT_SSH_RETRY    0x00003f00      /* Station short retry limit mask (?) */
-#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S  8
-#define AR5K_DCU_RETRY_LMT_SLG_RETRY    0x000fc000      /* Station long retry limit mask (?) */
-#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S  14
+#define AR5K_DCU_RETRY_LMT_RTS          0x0000000f      /* RTS failure limit. Transmission fails if no CTS is received for this number of times */
+#define AR5K_DCU_RETRY_LMT_RTS_S        0
+#define AR5K_DCU_RETRY_LMT_STA_RTS      0x00003f00      /* STA RTS failure limit. If exceeded CW reset */
+#define AR5K_DCU_RETRY_LMT_STA_RTS_S    8
+#define AR5K_DCU_RETRY_LMT_STA_DATA     0x000fc000      /* STA data failure limit. If exceeded CW reset. */
+#define AR5K_DCU_RETRY_LMT_STA_DATA_S   14
 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)  AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
 
 /*
@@ -788,6 +786,7 @@
 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE        0x00000007      /* LFSR Slice Select */
 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE        0x00000008      /* Turbo mode */
 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC     0x000003f0      /* SIFS Duration mask */
+#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S   4
 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR          0x000ffc00      /* USEC Duration mask */
 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S        10
 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY     0x00300000      /* DCU Arbiter delay mask */
@@ -896,7 +895,7 @@
 #define AR5K_PCICFG_SL_INTEN            0x00000800      /* Enable interrupts when asleep */
 #define AR5K_PCICFG_LED_BCTL            0x00001000      /* Led blink (?) [5210] */
 #define AR5K_PCICFG_RETRY_FIX           0x00001000      /* Enable pci core retry fix */
-#define AR5K_PCICFG_SL_INPEN            0x00002000      /* Sleep even whith pending interrupts*/
+#define AR5K_PCICFG_SL_INPEN            0x00002000      /* Sleep even with pending interrupts*/
 #define AR5K_PCICFG_SPWR_DN             0x00010000      /* Mask for power status */
 #define AR5K_PCICFG_LEDMODE             0x000e0000      /* Ledmode [5211+] */
 #define AR5K_PCICFG_LEDMODE_PROP        0x00000000      /* Blink on standard traffic [5211+] */
@@ -1064,7 +1063,7 @@
 /*
  * EEPROM command register
  */
-#define AR5K_EEPROM_CMD         0x6008                  /* Register Addres */
+#define AR5K_EEPROM_CMD         0x6008                  /* Register Address */
 #define AR5K_EEPROM_CMD_READ    0x00000001      /* EEPROM read */
 #define AR5K_EEPROM_CMD_WRITE   0x00000002      /* EEPROM write */
 #define AR5K_EEPROM_CMD_RESET   0x00000004      /* EEPROM reset */
@@ -1084,7 +1083,7 @@
 /*
  * EEPROM config register
  */
-#define AR5K_EEPROM_CFG                 0x6010                  /* Register Addres */
+#define AR5K_EEPROM_CFG                 0x6010                  /* Register Address */
 #define AR5K_EEPROM_CFG_SIZE            0x00000003              /* Size determination override */
 #define AR5K_EEPROM_CFG_SIZE_AUTO       0
 #define AR5K_EEPROM_CFG_SIZE_4KBIT      1
@@ -1126,7 +1125,7 @@
  * Second station id register (Upper 16 bits of MAC address + PCU settings)
  */
 #define AR5K_STA_ID1                    0x8004                  /* Register Address */
-#define AR5K_STA_ID1_ADDR_U16           0x0000ffff      /* Upper 16 bits of MAC addres */
+#define AR5K_STA_ID1_ADDR_U16           0x0000ffff      /* Upper 16 bits of MAC address */
 #define AR5K_STA_ID1_AP                 0x00010000      /* Set AP mode */
 #define AR5K_STA_ID1_ADHOC              0x00020000      /* Set Ad-Hoc mode */
 #define AR5K_STA_ID1_PWR_SV             0x00040000      /* Power save reporting */
@@ -1312,7 +1311,7 @@
 #define AR5K_IFS1_EIFS          0x03fff000
 #define AR5K_IFS1_EIFS_S        12
 #define AR5K_IFS1_CS_EN         0x04000000
-
+#define AR5K_IFS1_CS_EN_S       26
 
 /*
  * CFP duration register
@@ -1387,10 +1386,9 @@
 
 
 /*
- * PCU control register
+ * PCU Diagnostic register
  *
- * Only DIS_RX is used in the code, the rest i guess are
- * for tweaking/diagnostics.
+ * Used for tweaking/diagnostics.
  */
 #define AR5K_DIAG_SW_5210               0x8068                  /* Register Address [5210] */
 #define AR5K_DIAG_SW_5211               0x8048                  /* Register Address [5211+] */
@@ -1399,22 +1397,22 @@
 #define AR5K_DIAG_SW_DIS_WEP_ACK        0x00000001      /* Disable ACKs if WEP key is invalid */
 #define AR5K_DIAG_SW_DIS_ACK            0x00000002      /* Disable ACKs */
 #define AR5K_DIAG_SW_DIS_CTS            0x00000004      /* Disable CTSs */
-#define AR5K_DIAG_SW_DIS_ENC            0x00000008      /* Disable encryption */
-#define AR5K_DIAG_SW_DIS_DEC            0x00000010      /* Disable decryption */
-#define AR5K_DIAG_SW_DIS_TX             0x00000020      /* Disable transmit [5210] */
-#define AR5K_DIAG_SW_DIS_RX_5210        0x00000040      /* Disable recieve */
+#define AR5K_DIAG_SW_DIS_ENC            0x00000008      /* Disable HW encryption */
+#define AR5K_DIAG_SW_DIS_DEC            0x00000010      /* Disable HW decryption */
+#define AR5K_DIAG_SW_DIS_TX_5210        0x00000020      /* Disable transmit [5210] */
+#define AR5K_DIAG_SW_DIS_RX_5210        0x00000040      /* Disable receive */
 #define AR5K_DIAG_SW_DIS_RX_5211        0x00000020
 #define AR5K_DIAG_SW_DIS_RX             (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
-#define AR5K_DIAG_SW_LOOP_BACK_5210     0x00000080      /* Loopback (i guess it goes with DIS_TX) [5210] */
+#define AR5K_DIAG_SW_LOOP_BACK_5210     0x00000080      /* TX Data Loopback (i guess it goes with DIS_TX) [5210] */
 #define AR5K_DIAG_SW_LOOP_BACK_5211     0x00000040
 #define AR5K_DIAG_SW_LOOP_BACK          (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
-#define AR5K_DIAG_SW_CORR_FCS_5210      0x00000100      /* Corrupted FCS */
+#define AR5K_DIAG_SW_CORR_FCS_5210      0x00000100      /* Generate invalid TX FCS */
 #define AR5K_DIAG_SW_CORR_FCS_5211      0x00000080
 #define AR5K_DIAG_SW_CORR_FCS           (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
-#define AR5K_DIAG_SW_CHAN_INFO_5210     0x00000200      /* Dump channel info */
+#define AR5K_DIAG_SW_CHAN_INFO_5210     0x00000200      /* Add 56 bytes of channel info before the frame data in the RX buffer */
 #define AR5K_DIAG_SW_CHAN_INFO_5211     0x00000100
 #define AR5K_DIAG_SW_CHAN_INFO          (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
@@ -1426,17 +1424,17 @@
 #define AR5K_DIAG_SW_SCVRAM_SEED        0x0003f800      /* [5210] */
 #define AR5K_DIAG_SW_SCRAM_SEED_M       0x0001fc00      /* Scrambler seed mask */
 #define AR5K_DIAG_SW_SCRAM_SEED_S       10
-#define AR5K_DIAG_SW_DIS_SEQ_INC        0x00040000      /* Disable seqnum increment (?)[5210] */
+#define AR5K_DIAG_SW_DIS_SEQ_INC_5210   0x00040000      /* Disable seqnum increment (?)[5210] */
 #define AR5K_DIAG_SW_FRAME_NV0_5210     0x00080000
 #define AR5K_DIAG_SW_FRAME_NV0_5211     0x00020000      /* Accept frames of non-zero protocol number */
 #define AR5K_DIAG_SW_FRAME_NV0          (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
 #define AR5K_DIAG_SW_OBSPT_M            0x000c0000      /* Observation point select (?) */
 #define AR5K_DIAG_SW_OBSPT_S            18
-#define AR5K_DIAG_SW_RX_CLEAR_HIGH      0x0010000       /* Force RX Clear high */
-#define AR5K_DIAG_SW_IGNORE_CARR_SENSE  0x0020000       /* Ignore virtual carrier sense */
-#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH   0x0040000       /* Force channel idle high */
-#define AR5K_DIAG_SW_PHEAR_ME           0x0080000       /* ??? */
+#define AR5K_DIAG_SW_RX_CLEAR_HIGH      0x00100000      /* Ignore carrier sense */
+#define AR5K_DIAG_SW_IGNORE_CARR_SENSE  0x00200000      /* Ignore virtual carrier sense */
+#define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH  0x00400000      /* Force channel idle high */
+#define AR5K_DIAG_SW_PHEAR_ME           0x00800000      /* ??? */
 
 /*
  * TSF (clock) register (lower 32 bits)
@@ -1822,50 +1820,8 @@
 
 /*===5212 end===*/
 
-/*
- * Key table (WEP) register
- */
-#define AR5K_KEYTABLE_0_5210            0x9000
-#define AR5K_KEYTABLE_0_5211            0x8800
-#define AR5K_KEYTABLE_5210(_n)          (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
-#define AR5K_KEYTABLE_5211(_n)          (AR5K_KEYTABLE_0_5211 + ((_n) << 5))
-#define AR5K_KEYTABLE(_n)               (ah->ah_version == AR5K_AR5210 ? \
-                                        AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
-#define AR5K_KEYTABLE_OFF(_n, x)        (AR5K_KEYTABLE(_n) + (x << 2))
-#define AR5K_KEYTABLE_TYPE(_n)          AR5K_KEYTABLE_OFF(_n, 5)
-#define AR5K_KEYTABLE_TYPE_40           0x00000000
-#define AR5K_KEYTABLE_TYPE_104          0x00000001
-#define AR5K_KEYTABLE_TYPE_128          0x00000003
-#define AR5K_KEYTABLE_TYPE_TKIP         0x00000004      /* [5212+] */
-#define AR5K_KEYTABLE_TYPE_AES          0x00000005      /* [5211+] */
-#define AR5K_KEYTABLE_TYPE_CCM          0x00000006      /* [5212+] */
-#define AR5K_KEYTABLE_TYPE_NULL         0x00000007      /* [5211+] */
-#define AR5K_KEYTABLE_ANTENNA           0x00000008      /* [5212+] */
-#define AR5K_KEYTABLE_MAC0(_n)          AR5K_KEYTABLE_OFF(_n, 6)
-#define AR5K_KEYTABLE_MAC1(_n)          AR5K_KEYTABLE_OFF(_n, 7)
-#define AR5K_KEYTABLE_VALID             0x00008000
-
-/* If key type is TKIP and MIC is enabled
- * MIC key goes in offset entry + 64 */
-#define AR5K_KEYTABLE_MIC_OFFSET        64
-
-/* WEP 40-bit   = 40-bit  entered key + 24 bit IV = 64-bit
- * WEP 104-bit  = 104-bit entered key + 24-bit IV = 128-bit
- * WEP 128-bit  = 128-bit entered key + 24 bit IV = 152-bit
- *
- * Some vendors have introduced bigger WEP keys to address
- * security vulnerabilities in WEP. This includes:
- *
- * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit
- *
- * We can expand this if we find ar5k Atheros cards with a larger
- * key table size.
- */
 #define AR5K_KEYTABLE_SIZE_5210         64
 #define AR5K_KEYTABLE_SIZE_5211         128
-#define AR5K_KEYTABLE_SIZE              (ah->ah_version == AR5K_AR5210 ? \
-                                        AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
-
 
 /*===PHY REGISTERS===*/
 
@@ -1911,7 +1867,7 @@
 #define AR5K_PHY_TURBO                  0x9804                  /* Register Address */
 #define AR5K_PHY_TURBO_MODE             0x00000001      /* Enable turbo mode */
 #define AR5K_PHY_TURBO_SHORT            0x00000002      /* Set short symbols to turbo mode */
-#define AR5K_PHY_TURBO_MIMO             0x00000004      /* Set turbo for mimo mimo */
+#define AR5K_PHY_TURBO_MIMO             0x00000004      /* Set turbo for mimo */
 
 /*
  * PHY agility command register
@@ -2102,6 +2058,7 @@
 
 #define AR5K_PHY_SCAL                   0x9878
 #define AR5K_PHY_SCAL_32MHZ             0x0000000e
+#define AR5K_PHY_SCAL_32MHZ_5311        0x00000008
 #define AR5K_PHY_SCAL_32MHZ_2417        0x0000000a
 #define AR5K_PHY_SCAL_32MHZ_HB63        0x00000032
 
@@ -2288,6 +2245,8 @@
 #define AR5K_PHY_FRAME_CTL              (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
 /*---[5111+]---*/
+#define AR5K_PHY_FRAME_CTL_WIN_LEN      0x00000003      /* Force window length (?) */
+#define AR5K_PHY_FRAME_CTL_WIN_LEN_S    0
 #define AR5K_PHY_FRAME_CTL_TX_CLIP      0x00000038      /* Mask for tx clip (?) */
 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S    3
 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO  0x00010000      /* Prepend chan info */
@@ -2602,3 +2561,28 @@
  */
 #define AR5K_PHY_PDADC_TXPOWER_BASE     0xa280
 #define AR5K_PHY_PDADC_TXPOWER(_n)      (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
+
+/*
+ * Platform registers for WiSoC
+ */
+#define AR5K_AR5312_RESET               0xbc003020
+#define AR5K_AR5312_RESET_BB0_COLD      0x00000004
+#define AR5K_AR5312_RESET_BB1_COLD      0x00000200
+#define AR5K_AR5312_RESET_WMAC0         0x00002000
+#define AR5K_AR5312_RESET_BB0_WARM      0x00004000
+#define AR5K_AR5312_RESET_WMAC1         0x00020000
+#define AR5K_AR5312_RESET_BB1_WARM      0x00040000
+
+#define AR5K_AR5312_ENABLE              0xbc003080
+#define AR5K_AR5312_ENABLE_WLAN0    0x00000001
+#define AR5K_AR5312_ENABLE_WLAN1    0x00000008
+
+#define AR5K_AR2315_RESET               0xb1000004
+#define AR5K_AR2315_RESET_WMAC          0x00000001
+#define AR5K_AR2315_RESET_BB_WARM       0x00000002
+
+#define AR5K_AR2315_AHB_ARB_CTL         0xb1000008
+#define AR5K_AR2315_AHB_ARB_CTL_WLAN    0x00000002
+
+#define AR5K_AR2315_BYTESWAP    0xb100000c
+#define AR5K_AR2315_BYTESWAP_WMAC       0x00000002