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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
Commit message (Expand)AuthorAge
* drm/i915: Introduce a gmbus power domainVille Syrjälä2015-12-02
* Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/...Dave Airlie2015-11-07
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| * drm/i915/skl: disable display side power well support for nowImre Deak2015-11-06
* | Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...Dave Airlie2015-10-19
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| * drm/i915: Skip CHV PHY asserts until PHY has been fully resetVille Syrjälä2015-10-06
| * drm/i915: fixup runtime PM handling v2Jesse Barnes2015-09-30
| * drm/i915/skl: Block disable call for pw1 if dmc firmware is present.Animesh Manna2015-09-30
* | Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...Dave Airlie2015-10-15
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| * drm/i915/skl: Don't call intel_prepare_ddi when encoder list isn't yet initia...Rodrigo Vivi2015-09-28
* | drm/i915: make CSR firmware messages less verboseJesse Barnes2015-09-14
* | Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter2015-09-02
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| * drm/i915/skl: Adding DDI_E power well domainXiong Zhang2015-08-31
* | drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä2015-09-01
* | drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä2015-09-01
* | drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä2015-08-26
* | drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä2015-08-26
* | drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä2015-08-26
* | drm/i915: Implement PHY lane power gating for CHVVille Syrjälä2015-08-26
* | drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä2015-08-26
* | drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä2015-08-26
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* drm/i915: Extract a intel_power_well_disable() functionDamien Lespiau2015-08-05
* drm/i915: Extract a intel_power_well_enable() functionDamien Lespiau2015-08-05
* drm/i915: Refactor VLV display power well init/deinitVille Syrjälä2015-07-13
* drm/i915: Simplify CHV pipe A power well codeVille Syrjälä2015-07-13
* drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä2015-07-13
* drm/i915: Keep GMCH DPLL VGA mode always disabledVille Syrjälä2015-07-13
* drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä2015-05-28
* drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä2015-05-28
* drm/i915: Fix typo in intel_runtime_pm.cMasanari Iida2015-05-20
* Revert "drm/i915: Hack to tie both common lanes together on chv"Ville Syrjälä2015-05-08
* drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä2015-05-08
* drm/i915/skl: Make the Misc I/O power well part of the PLLS domainDamien Lespiau2015-05-08
* drm/i915/skl: Add the INIT power domain to the MISC I/O power wellDamien Lespiau2015-05-08
* drm/i915/skl: Assert the requirements to enter or exit DC6.Suketu Shah2015-05-08
* Implement enable/disable for Display C6 stateA.Sunil Kamath2015-05-08
* drm/i915/skl: Add DC6 Trigger sequence.Suketu Shah2015-05-08
* drm/i915/skl: Assert the requirements to enter or exit DC5.Suketu Shah2015-05-08
* drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath2015-05-08
* drm/i915/skl: Add DC5 Trigger SequenceSuketu Shah2015-05-08
* drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath2015-04-16
* drm/i915/bxt: Define BXT power domainsSatheeshakrishna M2015-04-14
* drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven2015-03-17
* drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau2015-03-17
* drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau2015-03-17
* drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau2015-03-17
* drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau2015-03-17
* drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau2015-03-17
* drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau2015-03-17
* drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M2015-02-13
* drm/i915/skl: Adding power domains for AUX controllersSatheeshakrishna M2015-01-27
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