drm/i915: Enable DPIO SUS clock gating on CHV

CHV has supports some form of automagic clock gating for the
DPIO SUS clock. We can simply enable the magic bits and the
hardware should take care of the rest.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4a43885e571d..ef043b2c06b2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -988,7 +988,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 
         /* Enable dynamic power down */
         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
-        tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN;
+        tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
+                DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
 
         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {