drm/i915/skl: Adding power domains for AUX controllers

Adding new power doamins for AUX controllers

v2: Added new power domains in power_domain_str per Imre's comment

v3: Added AUX power domains to older platforms

v4: Rebase on top of POWER_DOMAIN_PLLS.

v5: Modified to address review comments from Imre

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8bf7bb4a12bc..49695d7d51e3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -703,6 +703,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
         BIT(POWER_DOMAIN_PORT_CRT) |                    \
         BIT(POWER_DOMAIN_PLLS) |                        \
+        BIT(POWER_DOMAIN_AUX_A) |                       \
+        BIT(POWER_DOMAIN_AUX_B) |                       \
+        BIT(POWER_DOMAIN_AUX_C) |                       \
+        BIT(POWER_DOMAIN_AUX_D) |                       \
         BIT(POWER_DOMAIN_INIT))
 #define HSW_DISPLAY_POWER_DOMAINS (                             \
         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
@@ -724,24 +728,30 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
         BIT(POWER_DOMAIN_PORT_CRT) |            \
+        BIT(POWER_DOMAIN_AUX_B) |               \
+        BIT(POWER_DOMAIN_AUX_C) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_B) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_B) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_C) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_C) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define CHV_PIPE_A_POWER_DOMAINS (      \
@@ -761,20 +771,25 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_B) |               \
+        BIT(POWER_DOMAIN_AUX_C) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_D) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (  \
         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_D) |               \
         BIT(POWER_DOMAIN_INIT))
 
 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (  \
         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
+        BIT(POWER_DOMAIN_AUX_D) |               \
         BIT(POWER_DOMAIN_INIT))
 
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {