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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-05-26 13:22:39 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-05-28 05:13:50 -0400
commitfde61e4b80ff23a379210a5780e59ace4bd915e6 (patch)
tree13d44fcf848c192bea5c6df0556b7088df547010 /drivers/gpu/drm/i915/intel_runtime_pm.c
parentbc284542dad88046eefa3a8d4d9907529c4af9e0 (diff)
drm/i915: Throw out WIP CHV power well definitions
Expecting CHV power wells to be just an extended versions of the VLV power wells, a bunch of commented out power wells were added in anticipation when Punit folks would implement it all. Turns out they never did, and instead CHV has fewer power wells than VLV. Rip out all the #if 0'ed junk that's not needed. v2: Rename the "pipe-a" well to "display" to match VLV Clarify the pipe A power well relationship to pipes B and C (Deepak) Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c98
1 files changed, 4 insertions, 94 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 720b0c63b63c..1a45385f4d66 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
1233 BIT(POWER_DOMAIN_AUX_C) | \ 1233 BIT(POWER_DOMAIN_AUX_C) | \
1234 BIT(POWER_DOMAIN_INIT)) 1234 BIT(POWER_DOMAIN_INIT))
1235 1235
1236#define CHV_PIPE_A_POWER_DOMAINS ( \
1237 BIT(POWER_DOMAIN_PIPE_A) | \
1238 BIT(POWER_DOMAIN_INIT))
1239
1240#define CHV_PIPE_B_POWER_DOMAINS ( \
1241 BIT(POWER_DOMAIN_PIPE_B) | \
1242 BIT(POWER_DOMAIN_INIT))
1243
1244#define CHV_PIPE_C_POWER_DOMAINS ( \
1245 BIT(POWER_DOMAIN_PIPE_C) | \
1246 BIT(POWER_DOMAIN_INIT))
1247
1248#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1236#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1249 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1237 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1250 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1238 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
@@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
1260 BIT(POWER_DOMAIN_AUX_D) | \ 1248 BIT(POWER_DOMAIN_AUX_D) | \
1261 BIT(POWER_DOMAIN_INIT)) 1249 BIT(POWER_DOMAIN_INIT))
1262 1250
1263#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
1264 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1265 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1266 BIT(POWER_DOMAIN_AUX_D) | \
1267 BIT(POWER_DOMAIN_INIT))
1268
1269#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
1270 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1271 BIT(POWER_DOMAIN_AUX_D) | \
1272 BIT(POWER_DOMAIN_INIT))
1273
1274static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1251static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1275 .sync_hw = i9xx_always_on_power_well_noop, 1252 .sync_hw = i9xx_always_on_power_well_noop,
1276 .enable = i9xx_always_on_power_well_noop, 1253 .enable = i9xx_always_on_power_well_noop,
@@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = {
1428 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1405 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1429 .ops = &i9xx_always_on_power_well_ops, 1406 .ops = &i9xx_always_on_power_well_ops,
1430 }, 1407 },
1431#if 0
1432 { 1408 {
1433 .name = "display", 1409 .name = "display",
1434 .domains = VLV_DISPLAY_POWER_DOMAINS,
1435 .data = PUNIT_POWER_WELL_DISP2D,
1436 .ops = &vlv_display_power_well_ops,
1437 },
1438#endif
1439 {
1440 .name = "pipe-a",
1441 /* 1410 /*
1442 * FIXME: pipe A power well seems to be the new disp2d well. 1411 * Pipe A power well is the new disp2d well. Pipe B and C
1443 * At least all registers seem to be housed there. Figure 1412 * power wells don't actually exist. Pipe A power well is
1444 * out if this a a temporary situation in pre-production 1413 * required for any pipe to work.
1445 * hardware or a permanent state of affairs.
1446 */ 1414 */
1447 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, 1415 .domains = VLV_DISPLAY_POWER_DOMAINS,
1448 .data = PIPE_A, 1416 .data = PIPE_A,
1449 .ops = &chv_pipe_power_well_ops, 1417 .ops = &chv_pipe_power_well_ops,
1450 }, 1418 },
1451#if 0
1452 {
1453 .name = "pipe-b",
1454 .domains = CHV_PIPE_B_POWER_DOMAINS,
1455 .data = PIPE_B,
1456 .ops = &chv_pipe_power_well_ops,
1457 },
1458 {
1459 .name = "pipe-c",
1460 .domains = CHV_PIPE_C_POWER_DOMAINS,
1461 .data = PIPE_C,
1462 .ops = &chv_pipe_power_well_ops,
1463 },
1464#endif
1465 { 1419 {
1466 .name = "dpio-common-bc", 1420 .name = "dpio-common-bc",
1467 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1421 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
@@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = {
1474 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1428 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1475 .ops = &chv_dpio_cmn_power_well_ops, 1429 .ops = &chv_dpio_cmn_power_well_ops,
1476 }, 1430 },
1477#if 0
1478 {
1479 .name = "dpio-tx-b-01",
1480 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1481 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1482 .ops = &vlv_dpio_power_well_ops,
1483 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1484 },
1485 {
1486 .name = "dpio-tx-b-23",
1487 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1488 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1489 .ops = &vlv_dpio_power_well_ops,
1490 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1491 },
1492 {
1493 .name = "dpio-tx-c-01",
1494 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1495 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1496 .ops = &vlv_dpio_power_well_ops,
1497 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1498 },
1499 {
1500 .name = "dpio-tx-c-23",
1501 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1502 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1503 .ops = &vlv_dpio_power_well_ops,
1504 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1505 },
1506 {
1507 .name = "dpio-tx-d-01",
1508 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1509 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1510 .ops = &vlv_dpio_power_well_ops,
1511 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
1512 },
1513 {
1514 .name = "dpio-tx-d-23",
1515 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1516 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1517 .ops = &vlv_dpio_power_well_ops,
1518 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
1519 },
1520#endif
1521}; 1431};
1522 1432
1523static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1433static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,