diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-06-29 08:25:48 -0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-07-13 04:39:42 -0400 |
| commit | b8afb9113c519a8bd742f7df8c424b0af69a75cd (patch) | |
| tree | 09b7405799ac582089699d924e667a8b0e122f5a /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | f936ec34dea8da6f38340c1ae2cb35207d8d78cb (diff) | |
drm/i915: Keep GMCH DPLL VGA mode always disabled
We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL. Having VGA mode enabled even in unused
DPLLs can cause problems for CHV, so it seems wiser to always keep it
disabled. And let's just do that on all GMCH platforms to keep things
as similar as possible between them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1a45385f4d66..f0e6f49ee33a 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c | |||
| @@ -882,7 +882,7 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |||
| 882 | * display and the reference clock for VGA | 882 | * display and the reference clock for VGA |
| 883 | * hotplug / manual detection. | 883 | * hotplug / manual detection. |
| 884 | */ | 884 | */ |
| 885 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | 885 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | |
| 886 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | 886 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 887 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | 887 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 888 | 888 | ||
| @@ -933,13 +933,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |||
| 933 | */ | 933 | */ |
| 934 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | 934 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 935 | phy = DPIO_PHY0; | 935 | phy = DPIO_PHY0; |
| 936 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | 936 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | |
| 937 | DPLL_REFA_CLK_ENABLE_VLV); | 937 | DPLL_REFA_CLK_ENABLE_VLV); |
| 938 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | 938 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | |
| 939 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | 939 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 940 | } else { | 940 | } else { |
| 941 | phy = DPIO_PHY1; | 941 | phy = DPIO_PHY1; |
| 942 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | | 942 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS | |
| 943 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | 943 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 944 | } | 944 | } |
| 945 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | 945 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |