217 files changed, 44894 insertions, 12699 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf0a7aa..19d5891c48e3 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -11,12 +11,11 @@ config ARCH_OMAP2PLUS_TYPICAL
         select PM_RUNTIME
         select VFP
         select NEON if ARCH_OMAP3 || ARCH_OMAP4
-        select SERIAL_8250
-        select SERIAL_CORE_CONSOLE
-        select SERIAL_8250_CONSOLE
+        select SERIAL_OMAP
+        select SERIAL_OMAP_CONSOLE
         select I2C
         select I2C_OMAP
-        select MFD
+        select MFD_SUPPORT
         select MENELAUS if ARCH_OMAP2
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
@@ -35,7 +34,9 @@ config ARCH_OMAP3
         default y
         select CPU_V7
         select USB_ARCH_HAS_EHCI
-        select ARM_L1_CACHE_SHIFT_6
+        select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
+        select ARCH_HAS_OPP
+        select PM_OPP if PM
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -43,29 +44,41 @@ config ARCH_OMAP4
         depends on ARCH_OMAP2PLUS
         select CPU_V7
         select ARM_GIC
+        select LOCAL_TIMERS if SMP
+        select PL310_ERRATA_588369
+        select PL310_ERRATA_727915
+        select ARM_ERRATA_720789
+        select ARCH_HAS_OPP
+        select PM_OPP if PM
+        select USB_ARCH_HAS_EHCI
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
 
-config ARCH_OMAP2420
+config SOC_OMAP2420
         bool "OMAP2420 support"
         depends on ARCH_OMAP2
         default y
         select OMAP_DM_TIMER
         select ARCH_OMAP_OTG
 
-config ARCH_OMAP2430
+config SOC_OMAP2430
         bool "OMAP2430 support"
         depends on ARCH_OMAP2
         default y
         select ARCH_OMAP_OTG
 
-config ARCH_OMAP3430
+config SOC_OMAP3430
         bool "OMAP3430 support"
         depends on ARCH_OMAP3
         default y
         select ARCH_OMAP_OTG
 
+config SOC_OMAPTI816X
+        bool "TI816X support"
+        depends on ARCH_OMAP3
+        default y
+
 config OMAP_PACKAGE_ZAF
        bool
 
@@ -84,6 +97,12 @@ config OMAP_PACKAGE_CUS
 config OMAP_PACKAGE_CBP
        bool
 
+config OMAP_PACKAGE_CBL
+       bool
+
+config OMAP_PACKAGE_CBS
+       bool
+
 comment "OMAP Board Type"
         depends on ARCH_OMAP2PLUS
 
@@ -94,25 +113,25 @@ config MACH_OMAP_GENERIC
 
 config MACH_OMAP2_TUSB6010
         bool
-        depends on ARCH_OMAP2 && ARCH_OMAP2420
+        depends on ARCH_OMAP2 && SOC_OMAP2420
         default y if MACH_NOKIA_N8X0
 
 config MACH_OMAP_H4
         bool "OMAP 2420 H4 board"
-        depends on ARCH_OMAP2
+        depends on SOC_OMAP2420
         default y
         select OMAP_PACKAGE_ZAF
         select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
         bool "OMAP 2420 Apollon board"
-        depends on ARCH_OMAP2
+        depends on SOC_OMAP2420
         default y
         select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
         bool "OMAP 2430 SDP board"
-        depends on ARCH_OMAP2
+        depends on SOC_OMAP2430
         default y
         select OMAP_PACKAGE_ZAC
 
@@ -127,7 +146,6 @@ config MACH_DEVKIT8000
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CUS
-        select OMAP_MUX
 
 config MACH_OMAP_LDP
         bool "OMAP3 LDP board"
@@ -135,6 +153,26 @@ config MACH_OMAP_LDP
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_OMAP3530_LV_SOM
+        bool "OMAP3 Logic 3530 LV SOM board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+        default y
+        help
+         Support for the LogicPD OMAP3530 SOM Development kit
+         for full description please see the products webpage at
+         http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
+
+config MACH_OMAP3_TORPEDO
+        bool "OMAP3 Logic 35x Torpedo board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+        default y
+        help
+         Support for the LogicPD OMAP35x Torpedo Development kit
+         for full description please see the products webpage at
+         http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
+
 config MACH_OVERO
         bool "Gumstix Overo board"
         depends on ARCH_OMAP3
@@ -153,11 +191,17 @@ config MACH_OMAP3517EVM
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_CRANEBOARD
+        bool "AM3517/05 CRANE board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+
 config MACH_OMAP3_PANDORA
         bool "OMAP3 Pandora"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP3_TOUCHBOOK
         bool "OMAP3 Touch Book"
@@ -182,13 +226,19 @@ config MACH_NOKIA_N810_WIMAX
 
 config MACH_NOKIA_N8X0
         bool "Nokia N800/N810"
-        depends on ARCH_OMAP2420
+        depends on SOC_OMAP2420
         default y
         select OMAP_PACKAGE_ZAC
         select MACH_NOKIA_N800
         select MACH_NOKIA_N810
         select MACH_NOKIA_N810_WIMAX
 
+config MACH_NOKIA_RM680
+        bool "Nokia RM-680 board"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
         depends on ARCH_OMAP3
@@ -200,19 +250,32 @@ config MACH_OMAP_ZOOM2
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select SERIAL_8250
+        select SERIAL_CORE_CONSOLE
+        select SERIAL_8250_CONSOLE
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP_ZOOM3
         bool "OMAP3630 Zoom3 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBP
+        select SERIAL_8250
+        select SERIAL_CORE_CONSOLE
+        select SERIAL_8250_CONSOLE
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_CM_T35
         bool "CompuLab CM-T35 module"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CUS
-        select OMAP_MUX
+
+config MACH_CM_T3517
+        bool "CompuLab CM-T3517 module"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
 
 config MACH_IGEP0020
         bool "IGEP v2 board"
@@ -220,12 +283,18 @@ config MACH_IGEP0020
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_IGEP0030
+        bool "IGEP OMAP3 module"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+        select MACH_IGEP0020
+
 config MACH_SBC3530
         bool "OMAP3 SBC STALKER board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CUS
-        select OMAP_MUX
 
 config MACH_OMAP_3630SDP
         bool "OMAP3630 SDP board"
@@ -233,15 +302,26 @@ config MACH_OMAP_3630SDP
         default y
         select OMAP_PACKAGE_CBP
 
+config MACH_TI8168EVM
+        bool "TI8168 Evaluation Module"
+        depends on SOC_OMAPTI816X
+        default y
+
 config MACH_OMAP_4430SDP
         bool "OMAP 4430 SDP board"
         default y
         depends on ARCH_OMAP4
+        select OMAP_PACKAGE_CBL
+        select OMAP_PACKAGE_CBS
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP4_PANDA
         bool "OMAP4 Panda Board"
         default y
         depends on ARCH_OMAP4
+        select OMAP_PACKAGE_CBL
+        select OMAP_PACKAGE_CBS
+        select REGULATOR_FIXED_VOLTAGE
 
 config OMAP3_EMU
         bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 88d3a1e920f5..b14807794401 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,34 +3,36 @@
 #
 
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
+         common.o gpio.o dma.o wd_timer.o
 
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
                                           omap_hwmod_common_data.o
-prcm-common                             = prcm.o powerdomain.o
 clock-common                            = clock.o clock_common_data.o \
-                                          clockdomain.o clkt_dpll.o \
-                                          clkt_clksel.o
+                                          clkt_dpll.o clkt_clksel.o
 
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
+obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap44xx-smc.o omap4-common.o
 
-AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a
-AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a$(plus_sec)
 
 # Functions loaded to SRAM
-obj-$(CONFIG_ARCH_OMAP2420)             += sram242x.o
-obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
+obj-$(CONFIG_SOC_OMAP2420)              += sram242x.o
+obj-$(CONFIG_SOC_OMAP2430)              += sram243x.o
 obj-$(CONFIG_ARCH_OMAP3)                += sram34xx.o
 
 AFLAGS_sram242x.o                       :=-Wa,-march=armv6
@@ -38,59 +40,123 @@ AFLAGS_sram243x.o			:=-Wa,-march=armv6
 AFLAGS_sram34xx.o                       :=-Wa,-march=armv7-a
 
 # Pin multiplexing
-obj-$(CONFIG_ARCH_OMAP2420)             += mux2420.o
-obj-$(CONFIG_ARCH_OMAP2430)             += mux2430.o
+obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
+obj-$(CONFIG_SOC_OMAP2430)              += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += mux44xx.o
 
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
 
+# OPP table initialization
+ifeq ($(CONFIG_PM_OPP),y)
+obj-y                                   += opp.o
+obj-$(CONFIG_ARCH_OMAP3)                += opp3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += opp4xxx_data.o
+endif
+
 # Power Management
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o \
+                                           cpuidle34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
+obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
+obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
-AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a
+AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
+
+ifeq ($(CONFIG_PM_VERBOSE),y)
+CFLAGS_pm_bus.o                         += -DDEBUG
+endif
 
 endif
 
 # PRCM
-obj-$(CONFIG_ARCH_OMAP2)                += cm.o
-obj-$(CONFIG_ARCH_OMAP3)                += cm.o
-obj-$(CONFIG_ARCH_OMAP4)                += cm4xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
+                                           vc3xxx_data.o vp3xxx_data.o
+# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
+# will be removed once the OMAP4 part of the codebase is converted to
+# use OMAP4-specific PRCM functions.
+obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+                                           cm44xx.o prcm_mpu44xx.o \
+                                           prminst44xx.o vc44xx_data.o \
+                                           vp44xx_data.o
+
+# OMAP voltage domains
+ifeq ($(CONFIG_PM),y)
+voltagedomain-common                    := voltage.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
+obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common) \
+                                           voltagedomains3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common) \
+                                           voltagedomains44xx_data.o
+endif
+
+# OMAP powerdomain framework
+powerdomain-common                      += powerdomain.o powerdomain-common.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common) \
+                                           powerdomain2xxx_3xxx.o \
+                                           powerdomains2xxx_data.o \
+                                           powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common) \
+                                           powerdomain2xxx_3xxx.o \
+                                           powerdomains3xxx_data.o \
+                                           powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common) \
+                                           powerdomain44xx.o \
+                                           powerdomains44xx_data.o
+
+# PRCM clockdomain control
+obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
+                                           clockdomain2xxx_3xxx.o \
+                                           clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
+                                           clockdomain2xxx_3xxx.o \
+                                           clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
+                                           clockdomain44xx.o \
+                                           clockdomains44xx_data.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o \
                                            clkt2xxx_sys.o \
                                            clkt2xxx_dpllcore.o \
                                            clkt2xxx_virt_prcm_set.o \
-                                           clkt2xxx_apll.o clkt2xxx_osc.o
-obj-$(CONFIG_ARCH_OMAP2420)             += clock2420_data.o
-obj-$(CONFIG_ARCH_OMAP2430)             += clock2430.o clock2430_data.o
+                                           clkt2xxx_apll.o clkt2xxx_osc.o \
+                                           clkt2xxx_dpll.o clkt_iclk.o
+obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o \
                                            clock34xx.o clkt34xx_dpll3m2.o \
                                            clock3517.o clock36xx.o \
-                                           dpll3xxx.o clock3xxx_data.o
+                                           dpll3xxx.o clock3xxx_data.o \
+                                           clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o \
-                                           dpll3xxx.o
+                                           dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
-obj-$(CONFIG_ARCH_OMAP2420)             += opp2420_data.o
-obj-$(CONFIG_ARCH_OMAP2430)             += opp2430_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
-obj-$(CONFIG_ARCH_OMAP2420)             += omap_hwmod_2420_data.o
-obj-$(CONFIG_ARCH_OMAP2430)             += omap_hwmod_2430_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
 
+# L3 interconnect
+obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
+
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
 
@@ -102,6 +168,10 @@ obj-y					+= $(iommu-m) $(iommu-y)
 i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
 obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
 
+ifneq ($(CONFIG_TIDSPBRIDGE),)
+obj-y                                   += dsp.o
+endif
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
@@ -115,6 +185,10 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o \
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o \
                                            board-flash.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
+                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
@@ -125,46 +199,59 @@ obj-$(CONFIG_MACH_OMAP_3430SDP)		+= board-3430sdp.o \
                                            hsmmc.o \
                                            board-flash.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
+obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o \
+                                           sdram-nokia.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
-                                           board-rx51-sdram.o \
+                                           sdram-nokia.o \
                                            board-rx51-peripherals.o \
                                            board-rx51-video.o \
                                            hsmmc.o
-obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom2.o \
+obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o \
                                            board-zoom-peripherals.o \
+                                           board-zoom-display.o \
                                            board-flash.o \
                                            hsmmc.o \
                                            board-zoom-debugboard.o
-obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom3.o \
+obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o \
                                            board-zoom-peripherals.o \
+                                           board-zoom-display.o \
                                            board-flash.o \
                                            hsmmc.o \
                                            board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-3630sdp.o \
                                            board-zoom-peripherals.o \
+                                           board-zoom-display.o \
                                            board-flash.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
-                                           hsmmc.o
+                                           hsmmc.o \
+                                           omap_phy_internal.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o \
-                                           hsmmc.o
+                                           hsmmc.o \
+                                           omap_phy_internal.o
+
+obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o \
+                                           omap_phy_internal.o \
 
-obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
+obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
 
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
 # Platform specific device init code
 usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
 obj-y                                   += $(usbfs-m) $(usbfs-y)
 obj-y                                   += usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)       += usb-tusb6010.o
-obj-y                                   += usb-ehci.o
+obj-y                                   += usb-host.o
 
 onenand-$(CONFIG_MTD_ONENAND_OMAP2)     := gpmc-onenand.o
 obj-y                                   += $(onenand-m) $(onenand-y)
@@ -174,3 +261,12 @@ obj-y					+= $(nand-m) $(nand-y)
 
 smc91x-$(CONFIG_SMC91X)                 := gpmc-smc91x.o
 obj-y                                   += $(smc91x-m) $(smc91x-y)
+
+smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
+obj-y                                   += $(smsc911x-m) $(smsc911x-y)
+obj-$(CONFIG_ARCH_OMAP4)                += hwspinlock.o
+
+disp-$(CONFIG_OMAP2_DSS)                := display.o
+obj-y                                   += $(disp-m) $(disp-y)
+
+obj-y                                   += common-board-devices.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 8538e4131d27..5de6eac0a725 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -19,18 +19,20 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/mmc/host.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
+#include <linux/regulator/machine.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/gpio.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
@@ -39,6 +41,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define SDP2430_CS0_BASE        0x04000000
 #define SECONDARY_LCD_GPIO              147
@@ -134,19 +137,35 @@ static inline void board_smc91x_init(void)
 
 #endif
 
-static struct omap_board_config_kernel sdp2430_config[] = {
+static struct omap_board_config_kernel sdp2430_config[] __initdata = {
         {OMAP_TAG_LCD, &sdp2430_lcd_config},
 };
 
-static void __init omap_2430sdp_init_irq(void)
+static void __init omap_2430sdp_init_early(void)
 {
-        omap_board_config = sdp2430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp2430_config);
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 }
 
+static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data sdp2430_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(sdp2430_vmmc1_supplies),
+        .consumer_supplies      = &sdp2430_vmmc1_supplies[0],
+};
+
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -159,15 +178,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
 
         /* platform_data for children goes here */
         .gpio           = &sdp2430_gpio_data,
-};
-
-static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_24XX_SYS_NIRQ,
-                .platform_data = &sdp2430_twldata,
-        },
+        .vmmc1          = &sdp2430_vmmc1,
 };
 
 static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
@@ -182,15 +193,14 @@ static int __init omap2430_i2c_init(void)
 {
         omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
                         ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-        omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo,
-                        ARRAY_SIZE(sdp2430_i2c_boardinfo));
+        omap2_pmic_init("twl4030", &sdp2430_twldata);
         return 0;
 }
 
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .ext_clock      = 1,
@@ -198,11 +208,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {}      /* Terminator */
 };
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
 static struct omap_usb_config sdp2430_usb_config __initdata = {
         .otg            = 1,
 #ifdef  CONFIG_USB_GADGET_OMAP
@@ -217,16 +222,15 @@ static struct omap_usb_config sdp2430_usb_config __initdata = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap_2430sdp_init(void)
 {
-        int ret;
-
         omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
 
+        omap_board_config = sdp2430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp2430_config);
+
         omap2430_i2c_init();
 
         platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
@@ -235,14 +239,13 @@ static void __init omap_2430sdp_init(void)
         omap2_usbfs_init(&sdp2430_usb_config);
 
         omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
 
         board_smc91x_init();
 
         /* Turn off secondary LCD backlight */
-        ret = gpio_request(SECONDARY_LCD_GPIO, "Secondary LCD backlight");
-        if (ret == 0)
-                gpio_direction_output(SECONDARY_LCD_GPIO, 0);
+        gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
+                         "Secondary LCD backlight");
 }
 
 static void __init omap_2430sdp_map_io(void)
@@ -253,12 +256,11 @@ static void __init omap_2430sdp_map_io(void)
 
 MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap_2430sdp_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_2430sdp_init_irq,
+        .map_io         = omap_2430sdp_map_io,
+        .init_early     = omap_2430sdp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_2430sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 67b95b5f1a2f..5dac974be625 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -19,11 +19,11 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -36,17 +36,18 @@
 #include <plat/common.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
-#include <plat/control.h>
 #include <plat/gpmc-smc91x.h>
 
-#include <mach/board-flash.h>
-
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "control.h"
+#include "common-board-devices.h"
 
 #define CONFIG_DISABLE_HFCLK 1
 
@@ -58,25 +59,7 @@
 
 #define TWL4030_MSECURE_GPIO 22
 
-/* FIXME: These values need to be updated based on more profiling on 3430sdp*/
-static struct cpuidle_params omap3_cpuidle_params_table[] = {
-        /* C1 */
-        {1, 2, 2, 5},
-        /* C2 */
-        {1, 10, 10, 30},
-        /* C3 */
-        {1, 50, 50, 300},
-        /* C4 */
-        {1, 1500, 1800, 4000},
-        /* C5 */
-        {1, 2500, 7500, 12000},
-        /* C6 */
-        {1, 3000, 8500, 15000},
-        /* C7 */
-        {1, 10000, 30000, 300000},
-};
-
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_A),
@@ -122,63 +105,14 @@ static struct twl4030_keypad_data sdp3430_kp_data = {
         .rep            = 1,
 };
 
-static int ts_gpio;     /* Needed for ads7846_get_pendown_state */
-
-/**
- * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
- *
- * @return - void. If request gpio fails then Flag KERN_ERR.
- */
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) {
-                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
-                return;
-        }
-
-        gpio_direction_input(ts_gpio);
-        gpio_set_debounce(ts_gpio, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(ts_gpio);
-}
-
-static struct ads7846_platform_data tsc2046_config __initdata = {
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .wakeup                         = true,
-};
-
-
-static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
-        [0] = {
-                /*
-                 * TSC2046 operates at a max freqency of 2MHz, so
-                 * operate slightly below at 1.5MHz
-                 */
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &tsc2046_mcspi_config,
-                .irq                    = 0,
-                .platform_data          = &tsc2046_config,
-        },
-};
-
-
 #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO        8
 #define SDP3430_LCD_PANEL_ENABLE_GPIO           5
 
-static unsigned backlight_gpio;
-static unsigned enable_gpio;
+static struct gpio sdp3430_dss_gpios[] __initdata = {
+        {SDP3430_LCD_PANEL_ENABLE_GPIO,    GPIOF_OUT_INIT_LOW, "LCD reset"    },
+        {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
+};
+
 static int lcd_enabled;
 static int dvi_enabled;
 
@@ -186,29 +120,11 @@ static void __init sdp3430_display_init(void)
 {
         int r;
 
-        enable_gpio    = SDP3430_LCD_PANEL_ENABLE_GPIO;
-        backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
+        r = gpio_request_array(sdp3430_dss_gpios,
+                               ARRAY_SIZE(sdp3430_dss_gpios));
+        if (r)
+                printk(KERN_ERR "failed to get LCD control GPIOs\n");
 
-        r = gpio_request(enable_gpio, "LCD reset");
-        if (r) {
-                printk(KERN_ERR "failed to get LCD reset GPIO\n");
-                goto err0;
-        }
-
-        r = gpio_request(backlight_gpio, "LCD Backlight");
-        if (r) {
-                printk(KERN_ERR "failed to get LCD backlight GPIO\n");
-                goto err1;
-        }
-
-        gpio_direction_output(enable_gpio, 0);
-        gpio_direction_output(backlight_gpio, 0);
-
-        return;
-err1:
-        gpio_free(enable_gpio);
-err0:
-        return;
 }
 
 static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
@@ -218,8 +134,8 @@ static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_direction_output(enable_gpio, 1);
-        gpio_direction_output(backlight_gpio, 1);
+        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
+        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
 
         lcd_enabled = 1;
 
@@ -230,8 +146,8 @@ static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
         lcd_enabled = 0;
 
-        gpio_direction_output(enable_gpio, 0);
-        gpio_direction_output(backlight_gpio, 0);
+        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
+        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
 }
 
 static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
@@ -270,13 +186,18 @@ static struct omap_dss_device sdp3430_lcd_device = {
         .platform_disable       = sdp3430_panel_disable_lcd,
 };
 
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = sdp3430_panel_enable_dvi,
+        .platform_disable       = sdp3430_panel_disable_dvi,
+};
+
 static struct omap_dss_device sdp3430_dvi_device = {
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = sdp3430_panel_enable_dvi,
-        .platform_disable       = sdp3430_panel_disable_dvi,
 };
 
 static struct omap_dss_device sdp3430_tv_device = {
@@ -301,34 +222,13 @@ static struct omap_dss_board_info sdp3430_dss_data = {
         .default_device = &sdp3430_lcd_device,
 };
 
-static struct platform_device sdp3430_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &sdp3430_dss_data,
-        },
-};
-
-static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &sdp3430_dss_device.dev,
-};
-
-static struct platform_device *sdp3430_devices[] __initdata = {
-        &sdp3430_dss_device,
-};
-
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
 };
 
-static void __init omap_3430sdp_init_irq(void)
+static void __init omap_3430sdp_init_early(void)
 {
-        omap_board_config = sdp3430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
-        omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
-        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
 }
 
 static int sdp3430_batt_table[] = {
@@ -353,29 +253,17 @@ static struct omap2_hsmmc_info mmc[] = {
                 /* 8 bits (default) requires S6.3 == ON,
                  * so the SIM card isn't used; else 4 bits.
                  */
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 4,
         },
         {
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 7,
         },
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
-        .supply                 = "vmmc",
-};
-
-static struct regulator_consumer_supply sdp3430_vsim_supply = {
-        .supply                 = "vmmc_aux",
-};
-
-static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
-        .supply                 = "vmmc",
-};
-
 static int sdp3430_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -386,20 +274,11 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
         mmc[1].gpio_cd = gpio + 1;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
-         * regulators will be set up only *after* we return.
-         */
-        sdp3430_vmmc1_supply.dev = mmc[0].dev;
-        sdp3430_vsim_supply.dev = mmc[0].dev;
-        sdp3430_vmmc2_supply.dev = mmc[1].dev;
-
         /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
-        gpio_request(gpio + 7, "sub_lcd_en_bkl");
-        gpio_direction_output(gpio + 7, 0);
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
 
         /* gpio + 15 is "sub_lcd_nRST" (output) */
-        gpio_request(gpio + 15, "sub_lcd_nRST");
-        gpio_direction_output(gpio + 15, 0);
+        gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
 
         return 0;
 }
@@ -421,6 +300,35 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
         .irq_line       = 1,
 };
 
+/* regulator consumer mappings */
+
+/* ads7846 on SPI */
+static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
+
 /*
  * Apply all the fixed voltages since most versions of U-Boot
  * don't bother with that initialization.
@@ -463,6 +371,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies          = ARRAY_SIZE(sdp3430_vaux3_supplies),
+        .consumer_supplies              = sdp3430_vaux3_supplies,
 };
 
 /* VAUX4 for OMAP VDD_CSI2 (camera) */
@@ -489,8 +399,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc1_supplies),
+        .consumer_supplies      = sdp3430_vmmc1_supplies,
 };
 
 /* VMMC2 for MMC2 card */
@@ -504,8 +414,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vmmc2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc2_supplies),
+        .consumer_supplies      = sdp3430_vmmc2_supplies,
 };
 
 /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -519,8 +429,8 @@ static struct regulator_init_data sdp3430_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vsim_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vsim_supplies),
+        .consumer_supplies      = sdp3430_vsim_supplies,
 };
 
 /* VDAC for DSS driving S-Video */
@@ -534,16 +444,8 @@ static struct regulator_init_data sdp3430_vdac = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
-        {
-                .supply         = "vdds_dsi",
-                .dev            = &sdp3430_dss_device.dev,
-        }
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
+        .consumer_supplies      = sdp3430_vdda_dac_supplies,
 };
 
 static struct regulator_init_data sdp3430_vpll2 = {
@@ -561,9 +463,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
         .consumer_supplies      = sdp3430_vpll2_supplies,
 };
 
-static struct twl4030_codec_audio_data sdp3430_audio = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data sdp3430_audio;
 
 static struct twl4030_codec_data sdp3430_codec = {
         .audio_mclk = 26000000,
@@ -593,20 +493,10 @@ static struct twl4030_platform_data sdp3430_twldata = {
         .vpll2          = &sdp3430_vpll2,
 };
 
-static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &sdp3430_twldata,
-        },
-};
-
 static int __init omap3430_i2c_init(void)
 {
         /* i2c1 for PMIC only */
-        omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo,
-                        ARRAY_SIZE(sdp3430_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &sdp3430_twldata);
         /* i2c2 on camera connector (for sensor control) and optional isp1301 */
         omap_register_i2c_bus(2, 400, NULL, 0);
         /* i2c3 on display connector (for DVI, tfp410) */
@@ -647,11 +537,11 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = 57,
@@ -663,8 +553,106 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+
+static struct omap_device_pad serial1_pads[] __initdata = {
+        /*
+         * Note that off output enable is an active low
+         * signal. So setting this means pin is a
+         * input enabled in off mode
+         */
+        OMAP_MUX_STATIC("uart1_cts.uart1_cts",
+                         OMAP_PIN_INPUT |
+                         OMAP_PIN_OFF_INPUT_PULLDOWN |
+                         OMAP_OFFOUT_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart1_rts.uart1_rts",
+                         OMAP_PIN_OUTPUT |
+                         OMAP_OFF_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart1_rx.uart1_rx",
+                         OMAP_PIN_INPUT |
+                         OMAP_PIN_OFF_INPUT_PULLDOWN |
+                         OMAP_OFFOUT_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart1_tx.uart1_tx",
+                         OMAP_PIN_OUTPUT |
+                         OMAP_OFF_EN |
+                         OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
+                         OMAP_PIN_INPUT_PULLUP |
+                         OMAP_PIN_OFF_INPUT_PULLDOWN |
+                         OMAP_OFFOUT_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
+                         OMAP_PIN_OUTPUT |
+                         OMAP_OFF_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
+                         OMAP_PIN_INPUT |
+                         OMAP_PIN_OFF_INPUT_PULLDOWN |
+                         OMAP_OFFOUT_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
+                         OMAP_PIN_OUTPUT |
+                         OMAP_OFF_EN |
+                         OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial3_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
+                         OMAP_PIN_INPUT_PULLDOWN |
+                         OMAP_PIN_OFF_INPUT_PULLDOWN |
+                         OMAP_OFFOUT_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
+                         OMAP_PIN_OUTPUT |
+                         OMAP_OFF_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
+                         OMAP_PIN_INPUT |
+                         OMAP_PIN_OFF_INPUT_PULLDOWN |
+                         OMAP_OFFOUT_EN |
+                         OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
+                         OMAP_PIN_OUTPUT |
+                         OMAP_OFF_EN |
+                         OMAP_MUX_MODE0),
+};
+
+static struct omap_board_data serial1_data __initdata = {
+        .id             = 0,
+        .pads           = serial1_pads,
+        .pads_cnt       = ARRAY_SIZE(serial1_pads),
+};
+
+static struct omap_board_data serial2_data __initdata = {
+        .id             = 1,
+        .pads           = serial2_pads,
+        .pads_cnt       = ARRAY_SIZE(serial2_pads),
+};
+
+static struct omap_board_data serial3_data __initdata = {
+        .id             = 2,
+        .pads           = serial3_pads,
+        .pads_cnt       = ARRAY_SIZE(serial3_pads),
+};
+
+static inline void board_serial_init(void)
+{
+        omap_serial_init_port(&serial1_data);
+        omap_serial_init_port(&serial2_data);
+        omap_serial_init_port(&serial3_data);
+}
 #else
 #define board_mux       NULL
+
+static inline void board_serial_init(void)
+{
+        omap_serial_init();
+}
 #endif
 
 /*
@@ -787,42 +775,36 @@ static struct flash_partitions sdp_flash_partitions[] = {
         },
 };
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init omap_3430sdp_init(void)
 {
+        int gpio_pendown;
+
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = sdp3430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
         omap3430_i2c_init();
-        platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
+        omap_display_init(&sdp3430_dss_data);
         if (omap_rev() > OMAP3430_REV_ES1_0)
-                ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
+                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
         else
-                ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1;
-        sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
-        spi_register_board_info(sdp3430_spi_board_info,
-                                ARRAY_SIZE(sdp3430_spi_board_info));
-        ads7846_dev_init();
-        omap_serial_init();
-        usb_musb_init(&musb_board_data);
+                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
+        omap_ads7846_init(1, gpio_pendown, 310, NULL);
+        board_serial_init();
+        usb_musb_init(NULL);
         board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_3430);
+        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
-        usb_ehci_init(&ehci_pdata);
+        usbhs_init(&usbhs_bdata);
 }
 
 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_3430sdp_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_3430sdp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_3430sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index b359c3f7bb39..a5933cc15caa 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -11,6 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -21,8 +22,8 @@
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
-#include <mach/board-flash.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
@@ -54,11 +55,11 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = 126,
@@ -69,22 +70,17 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_config_kernel sdp_config[] __initdata = {
 };
 
-static void __init omap_sdp_init_irq(void)
+static void __init omap_sdp_init_early(void)
 {
-        omap_board_config = sdp_config;
-        omap_board_config_size = ARRAY_SIZE(sdp_config);
-        omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
-                        h8mbx00u0mer0em_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+                                  h8mbx00u0mer0em_sdrc_params);
 }
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 /*
@@ -208,21 +204,22 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        omap_serial_init();
+        omap_board_config = sdp_config;
+        omap_board_config_size = ARRAY_SIZE(sdp_config);
         zoom_peripherals_init();
+        zoom_display_init();
         board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_sdp);
+        board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
-        usb_ehci_init(&ehci_pdata);
+        usbhs_init(&usbhs_bdata);
 }
 
 MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_sdp_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_sdp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 9447644774c2..63de2d396e2d 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,8 +20,10 @@
 #include <linux/usb/otg.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
+#include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/leds.h>
+#include <linux/leds_pwm.h>
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -31,16 +33,109 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
-#include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include <plat/omap4-keypad.h>
+#include <video/omapdss.h>
+
+#include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
+#include "control.h"
+#include "common-board-devices.h"
 
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
 #define ETH_KS8851_QUART                138
+#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
+#define OMAP4_SFH7741_ENABLE_GPIO               188
+#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
+#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
+
+static const int sdp4430_keymap[] = {
+        KEY(0, 0, KEY_E),
+        KEY(0, 1, KEY_R),
+        KEY(0, 2, KEY_T),
+        KEY(0, 3, KEY_HOME),
+        KEY(0, 4, KEY_F5),
+        KEY(0, 5, KEY_UNKNOWN),
+        KEY(0, 6, KEY_I),
+        KEY(0, 7, KEY_LEFTSHIFT),
+
+        KEY(1, 0, KEY_D),
+        KEY(1, 1, KEY_F),
+        KEY(1, 2, KEY_G),
+        KEY(1, 3, KEY_SEND),
+        KEY(1, 4, KEY_F6),
+        KEY(1, 5, KEY_UNKNOWN),
+        KEY(1, 6, KEY_K),
+        KEY(1, 7, KEY_ENTER),
+
+        KEY(2, 0, KEY_X),
+        KEY(2, 1, KEY_C),
+        KEY(2, 2, KEY_V),
+        KEY(2, 3, KEY_END),
+        KEY(2, 4, KEY_F7),
+        KEY(2, 5, KEY_UNKNOWN),
+        KEY(2, 6, KEY_DOT),
+        KEY(2, 7, KEY_CAPSLOCK),
+
+        KEY(3, 0, KEY_Z),
+        KEY(3, 1, KEY_KPPLUS),
+        KEY(3, 2, KEY_B),
+        KEY(3, 3, KEY_F1),
+        KEY(3, 4, KEY_F8),
+        KEY(3, 5, KEY_UNKNOWN),
+        KEY(3, 6, KEY_O),
+        KEY(3, 7, KEY_SPACE),
+
+        KEY(4, 0, KEY_W),
+        KEY(4, 1, KEY_Y),
+        KEY(4, 2, KEY_U),
+        KEY(4, 3, KEY_F2),
+        KEY(4, 4, KEY_VOLUMEUP),
+        KEY(4, 5, KEY_UNKNOWN),
+        KEY(4, 6, KEY_L),
+        KEY(4, 7, KEY_LEFT),
+
+        KEY(5, 0, KEY_S),
+        KEY(5, 1, KEY_H),
+        KEY(5, 2, KEY_J),
+        KEY(5, 3, KEY_F3),
+        KEY(5, 4, KEY_F9),
+        KEY(5, 5, KEY_VOLUMEDOWN),
+        KEY(5, 6, KEY_M),
+        KEY(5, 7, KEY_RIGHT),
+
+        KEY(6, 0, KEY_Q),
+        KEY(6, 1, KEY_A),
+        KEY(6, 2, KEY_N),
+        KEY(6, 3, KEY_BACK),
+        KEY(6, 4, KEY_BACKSPACE),
+        KEY(6, 5, KEY_UNKNOWN),
+        KEY(6, 6, KEY_P),
+        KEY(6, 7, KEY_UP),
+
+        KEY(7, 0, KEY_PROG1),
+        KEY(7, 1, KEY_PROG2),
+        KEY(7, 2, KEY_PROG3),
+        KEY(7, 3, KEY_PROG4),
+        KEY(7, 4, KEY_F4),
+        KEY(7, 5, KEY_UNKNOWN),
+        KEY(7, 6, KEY_OK),
+        KEY(7, 7, KEY_DOWN),
+};
 
+static struct matrix_keymap_data sdp4430_keymap_data = {
+        .keymap                 = sdp4430_keymap,
+        .keymap_size            = ARRAY_SIZE(sdp4430_keymap),
+};
+
+static struct omap4_keypad_platform_data sdp4430_keypad_data = {
+        .keymap_data            = &sdp4430_keymap_data,
+        .rows                   = 8,
+        .cols                   = 8,
+};
 static struct gpio_led sdp4430_gpio_leds[] = {
         {
                 .name   = "omap4:green:debug0",
@@ -77,11 +172,69 @@ static struct gpio_led sdp4430_gpio_leds[] = {
 
 };
 
+static struct gpio_keys_button sdp4430_gpio_keys[] = {
+        {
+                .desc                   = "Proximity Sensor",
+                .type                   = EV_SW,
+                .code                   = SW_FRONT_PROXIMITY,
+                .gpio                   = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
+                .active_low             = 0,
+        }
+};
+
 static struct gpio_led_platform_data sdp4430_led_data = {
         .leds   = sdp4430_gpio_leds,
         .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
 };
 
+static struct led_pwm sdp4430_pwm_leds[] = {
+        {
+                .name           = "omap4:green:chrg",
+                .pwm_id         = 1,
+                .max_brightness = 255,
+                .pwm_period_ns  = 7812500,
+        },
+};
+
+static struct led_pwm_platform_data sdp4430_pwm_data = {
+        .num_leds       = ARRAY_SIZE(sdp4430_pwm_leds),
+        .leds           = sdp4430_pwm_leds,
+};
+
+static struct platform_device sdp4430_leds_pwm = {
+        .name   = "leds_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &sdp4430_pwm_data,
+        },
+};
+
+static int omap_prox_activate(struct device *dev)
+{
+        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
+        return 0;
+}
+
+static void omap_prox_deactivate(struct device *dev)
+{
+        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
+}
+
+static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
+        .buttons        = sdp4430_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(sdp4430_gpio_keys),
+        .enable         = omap_prox_activate,
+        .disable        = omap_prox_deactivate,
+};
+
+static struct platform_device sdp4430_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &sdp4430_gpio_keys_data,
+        },
+};
+
 static struct platform_device sdp4430_leds_gpio = {
         .name   = "leds-gpio",
         .id     = -1,
@@ -99,58 +252,22 @@ static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
         },
 };
 
-static int omap_ethernet_init(void)
+static struct gpio sdp4430_eth_gpios[] __initdata = {
+        { ETH_KS8851_POWER_ON,  GPIOF_OUT_INIT_HIGH,    "eth_power"     },
+        { ETH_KS8851_QUART,     GPIOF_OUT_INIT_HIGH,    "quart"         },
+        { ETH_KS8851_IRQ,       GPIOF_IN,               "eth_irq"       },
+};
+
+static int __init omap_ethernet_init(void)
 {
         int status;
 
         /* Request of GPIO lines */
+        status = gpio_request_array(sdp4430_eth_gpios,
+                                    ARRAY_SIZE(sdp4430_eth_gpios));
+        if (status)
+                pr_err("Cannot request ETH GPIOs\n");
 
-        status = gpio_request(ETH_KS8851_POWER_ON, "eth_power");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", ETH_KS8851_POWER_ON);
-                return status;
-        }
-
-        status = gpio_request(ETH_KS8851_QUART, "quart");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", ETH_KS8851_QUART);
-                goto error1;
-        }
-
-        status = gpio_request(ETH_KS8851_IRQ, "eth_irq");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", ETH_KS8851_IRQ);
-                goto error2;
-        }
-
-        /* Configuration of requested GPIO lines */
-
-        status = gpio_direction_output(ETH_KS8851_POWER_ON, 1);
-        if (status) {
-                pr_err("Cannot set output GPIO %d\n", ETH_KS8851_IRQ);
-                goto error3;
-        }
-
-        status = gpio_direction_output(ETH_KS8851_QUART, 1);
-        if (status) {
-                pr_err("Cannot set output GPIO %d\n", ETH_KS8851_QUART);
-                goto error3;
-        }
-
-        status = gpio_direction_input(ETH_KS8851_IRQ);
-        if (status) {
-                pr_err("Cannot set input GPIO %d\n", ETH_KS8851_IRQ);
-                goto error3;
-        }
-
-        return 0;
-
-error3:
-        gpio_free(ETH_KS8851_IRQ);
-error2:
-        gpio_free(ETH_KS8851_QUART);
-error1:
-        gpio_free(ETH_KS8851_POWER_ON);
         return status;
 }
 
@@ -161,7 +278,9 @@ static struct platform_device sdp4430_lcd_device = {
 
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_lcd_device,
+        &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
+        &sdp4430_leds_pwm,
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -172,36 +291,43 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
-static void __init omap_4430sdp_init_irq(void)
+static void __init omap_4430sdp_init_early(void)
 {
-        omap_board_config = sdp4430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp4430_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(1);
 #endif
-        gic_init_irq();
-        omap_gpio_init();
 }
 
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_PERIPHERAL,
+        .mode                   = MUSB_OTG,
         .power                  = 100,
 };
 
+static struct twl4030_usb_data omap4_usbphy_data = {
+        .phy_init       = omap4430_phy_init,
+        .phy_exit       = omap4430_phy_exit,
+        .phy_power      = omap4430_phy_power,
+        .phy_set_clock  = omap4430_phy_set_clk,
+        .phy_suspend    = omap4430_phy_suspend,
+};
+
 static struct omap2_hsmmc_info mmc[] = {
         {
-                .mmc            = 1,
-                .wires          = 8,
-                .gpio_wp        = -EINVAL,
-        },
-        {
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           =  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
+                .ocr_mask       = MMC_VDD_29_30,
+                .no_off_init    = true,
+        },
+        {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                .gpio_wp        = -EINVAL,
         },
         {}      /* Terminator */
 };
@@ -209,13 +335,13 @@ static struct omap2_hsmmc_info mmc[] = {
 static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
         {
                 .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.1",
+                .dev_name = "omap_hsmmc.1",
         },
 };
 static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
         {
                 .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.0",
+                .dev_name = "omap_hsmmc.0",
         },
 };
 
@@ -227,16 +353,27 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
         struct omap_mmc_platform_data *pdata = dev->platform_data;
 
         /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0)
+        if (pdev->id == 0) {
+                ret = twl6030_mmc_card_detect_config();
+                if (ret)
+                        pr_err("Failed configuring MMC1 card detect\n");
                 pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
                                                 MMCDETECT_INTR_OFFSET;
+                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+        }
         return ret;
 }
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 {
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        struct omap_mmc_platform_data *pdata;
 
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed %s\n", __func__);
+                return;
+        }
+        pdata = dev->platform_data;
         pdata->init =   omap4_twl6030_hsmmc_late_init;
 }
 
@@ -338,7 +475,6 @@ static struct regulator_init_data sdp4430_vana = {
         .constraints = {
                 .min_uV                 = 2100000,
                 .max_uV                 = 2100000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -350,7 +486,6 @@ static struct regulator_init_data sdp4430_vcxio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -362,7 +497,6 @@ static struct regulator_init_data sdp4430_vdac = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -382,6 +516,12 @@ static struct regulator_init_data sdp4430_vusb = {
         },
 };
 
+static struct regulator_init_data sdp4430_clk32kg = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+};
+
 static struct twl4030_platform_data sdp4430_twldata = {
         .irq_base       = TWL6030_IRQ_BASE,
         .irq_end        = TWL6030_IRQ_END,
@@ -397,48 +537,211 @@ static struct twl4030_platform_data sdp4430_twldata = {
         .vaux1          = &sdp4430_vaux1,
         .vaux2          = &sdp4430_vaux2,
         .vaux3          = &sdp4430_vaux3,
+        .clk32kg        = &sdp4430_clk32kg,
+        .usb            = &omap4_usbphy_data
 };
 
-static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
+static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("tmp105", 0x48),
+        },
         {
-                I2C_BOARD_INFO("twl6030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = OMAP44XX_IRQ_SYS_1N,
-                .platform_data = &sdp4430_twldata,
+                I2C_BOARD_INFO("bh1780", 0x29),
         },
 };
-static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
+static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
         {
-                I2C_BOARD_INFO("tmp105", 0x48),
+                I2C_BOARD_INFO("hmc5843", 0x1e),
         },
 };
 static int __init omap4_i2c_init(void)
 {
-        /*
-         * Phoenix Audio IC needs I2C1 to
-         * start with 400 KHz or less
-         */
-        omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo,
-                        ARRAY_SIZE(sdp4430_i2c_boardinfo));
+        omap4_pmic_init("twl6030", &sdp4430_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
-        omap_register_i2c_bus(4, 400, NULL, 0);
+        omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
+                                ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
         return 0;
 }
+
+static void __init omap_sfh7741prox_init(void)
+{
+        int error;
+
+        error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
+                                 GPIOF_OUT_INIT_LOW, "sfh7741");
+        if (error < 0)
+                pr_err("%s:failed to request GPIO %d, error %d\n",
+                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
+}
+
+static void sdp4430_hdmi_mux_init(void)
+{
+        /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+        omap_mux_init_signal("hdmi_hpd",
+                        OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_signal("hdmi_cec",
+                        OMAP_PIN_INPUT_PULLUP);
+        /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+        omap_mux_init_signal("hdmi_ddc_scl",
+                        OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_signal("hdmi_ddc_sda",
+                        OMAP_PIN_INPUT_PULLUP);
+}
+
+static struct gpio sdp4430_hdmi_gpios[] = {
+        { HDMI_GPIO_HPD,        GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_hpd"   },
+        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_ls_oe" },
+};
+
+static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
+{
+        int status;
+
+        status = gpio_request_array(sdp4430_hdmi_gpios,
+                                    ARRAY_SIZE(sdp4430_hdmi_gpios));
+        if (status)
+                pr_err("%s: Cannot request HDMI GPIOs\n", __func__);
+
+        return status;
+}
+
+static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
+{
+        gpio_free(HDMI_GPIO_LS_OE);
+        gpio_free(HDMI_GPIO_HPD);
+}
+
+static struct omap_dss_device sdp4430_hdmi_device = {
+        .name = "hdmi",
+        .driver_name = "hdmi_panel",
+        .type = OMAP_DISPLAY_TYPE_HDMI,
+        .clocks = {
+                .dispc  = {
+                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
+                },
+                .hdmi   = {
+                        .regn   = 15,
+                        .regm2  = 1,
+                },
+        },
+        .platform_enable = sdp4430_panel_enable_hdmi,
+        .platform_disable = sdp4430_panel_disable_hdmi,
+        .channel = OMAP_DSS_CHANNEL_DIGIT,
+};
+
+static struct omap_dss_device *sdp4430_dss_devices[] = {
+        &sdp4430_hdmi_device,
+};
+
+static struct omap_dss_board_info sdp4430_dss_data = {
+        .num_devices    = ARRAY_SIZE(sdp4430_dss_devices),
+        .devices        = sdp4430_dss_devices,
+        .default_device = &sdp4430_hdmi_device,
+};
+
+void omap_4430sdp_display_init(void)
+{
+        sdp4430_hdmi_mux_init();
+        omap_display_init(&sdp4430_dss_data);
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
+                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
+                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial3_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
+                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
+                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial4_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
+                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_board_data serial2_data __initdata = {
+        .id             = 1,
+        .pads           = serial2_pads,
+        .pads_cnt       = ARRAY_SIZE(serial2_pads),
+};
+
+static struct omap_board_data serial3_data __initdata = {
+        .id             = 2,
+        .pads           = serial3_pads,
+        .pads_cnt       = ARRAY_SIZE(serial3_pads),
+};
+
+static struct omap_board_data serial4_data __initdata = {
+        .id             = 3,
+        .pads           = serial4_pads,
+        .pads_cnt       = ARRAY_SIZE(serial4_pads),
+};
+
+static inline void board_serial_init(void)
+{
+        struct omap_board_data bdata;
+        bdata.flags     = 0;
+        bdata.pads      = NULL;
+        bdata.pads_cnt  = 0;
+        bdata.id        = 0;
+        /* pass dummy data for UART1 */
+        omap_serial_init_port(&bdata);
+
+        omap_serial_init_port(&serial2_data);
+        omap_serial_init_port(&serial3_data);
+        omap_serial_init_port(&serial4_data);
+}
+#else
+#define board_mux       NULL
+
+static inline void board_serial_init(void)
+{
+        omap_serial_init();
+}
+ #endif
+
 static void __init omap_4430sdp_init(void)
 {
         int status;
+        int package = OMAP_PACKAGE_CBS;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                package = OMAP_PACKAGE_CBL;
+        omap4_mux_init(board_mux, NULL, package);
+
+        omap_board_config = sdp4430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp4430_config);
 
         omap4_i2c_init();
+        omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-        omap_serial_init();
+        board_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
-        /* OMAP4 SDP uses internal transceiver so register nop transceiver */
-        usb_nop_xceiv_register();
-        /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
-        if (!cpu_is_omap44xx())
-                usb_musb_init(&musb_board_data);
+
+        usb_musb_init(&musb_board_data);
 
         status = omap_ethernet_init();
         if (status) {
@@ -448,6 +751,12 @@ static void __init omap_4430sdp_init(void)
                 spi_register_board_info(sdp4430_spi_board_info,
                                 ARRAY_SIZE(sdp4430_spi_board_info));
         }
+
+        status = omap4_keyboard_init(&sdp4430_keypad_data);
+        if (status)
+                pr_err("Keypad initialization failed: %d\n", status);
+
+        omap_4430sdp_display_init();
 }
 
 static void __init omap_4430sdp_map_io(void)
@@ -458,12 +767,11 @@ static void __init omap_4430sdp_map_io(void)
 
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap_4430sdp_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_4430sdp_init_irq,
+        .map_io         = omap_4430sdp_map_io,
+        .init_early     = omap_4430sdp_init_early,
+        .init_irq       = gic_init_irq,
         .init_machine   = omap_4430sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
new file mode 100644
index 000000000000..5e438a77cd72
--- /dev/null
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -0,0 +1,110 @@
+/*
+ * Support for AM3517/05 Craneboard
+ * http://www.mistralsolutions.com/products/craneboard.php
+ *
+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com>
+ * Author: R.Srinath <srinath@mistralsolutions.com>
+ *
+ * Based on mach-omap2/board-am3517evm.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/usb.h>
+
+#include "mux.h"
+#include "control.h"
+
+#define GPIO_USB_POWER          35
+#define GPIO_USB_NRESET         38
+
+
+/* Board initialization */
+static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init am3517_crane_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
+static struct usbhs_omap_board_data usbhs_bdata __initdata = {
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = GPIO_USB_NRESET,
+        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static void __init am3517_crane_init(void)
+{
+        int ret;
+
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+
+        omap_board_config = am3517_crane_config;
+        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
+
+        /* Configure GPIO for EHCI port */
+        if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
+                pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
+                        GPIO_USB_NRESET);
+                return;
+        }
+
+        if (omap_mux_init_gpio(GPIO_USB_POWER, OMAP_PIN_OUTPUT)) {
+                pr_err("Can not configure mux for GPIO_USB_POWER %d\n",
+                        GPIO_USB_POWER);
+                return;
+        }
+
+        ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
+                               "usb_ehci_enable");
+        if (ret < 0) {
+                pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
+                return;
+        }
+
+        usbhs_init(&usbhs_bdata);
+}
+
+MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
+        .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = am3517_crane_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = am3517_crane_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4d0f58592864..63af4171c043 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/i2c/pca953x.h>
@@ -32,25 +33,44 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include "mux.h"
+#include "control.h"
 
-#define AM35XX_EVM_PHY_MASK             (0xF)
 #define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
 
+static struct mdio_platform_data am3517_evm_mdio_pdata = {
+        .bus_freq       = AM35XX_EVM_MDIO_FREQUENCY,
+};
+
+static struct resource am3517_mdio_resources[] = {
+        {
+                .start  = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET,
+                .end    = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET +
+                          SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device am3517_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(am3517_mdio_resources),
+        .resource       = am3517_mdio_resources,
+        .dev.platform_data = &am3517_evm_mdio_pdata,
+};
+
 static struct emac_platform_data am3517_evm_emac_pdata = {
-        .phy_mask       = AM35XX_EVM_PHY_MASK,
-        .mdio_max_freq  = AM35XX_EVM_MDIO_FREQUENCY,
         .rmii_en        = 1,
 };
 
 static struct resource am3517_emac_resources[] = {
         {
                 .start  = AM35XX_IPSS_EMAC_BASE,
-                .end    = AM35XX_IPSS_EMAC_BASE + 0x3FFFF,
+                .end    = AM35XX_IPSS_EMAC_BASE + 0x2FFFF,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -106,14 +126,13 @@ static void am3517_disable_ethernet_int(void)
         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 }
 
-void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
+static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 {
         unsigned int regval;
 
         pdata->ctrl_reg_offset          = AM35XX_EMAC_CNTRL_OFFSET;
         pdata->ctrl_mod_reg_offset      = AM35XX_EMAC_CNTRL_MOD_OFFSET;
         pdata->ctrl_ram_offset          = AM35XX_EMAC_CNTRL_RAM_OFFSET;
-        pdata->mdio_reg_offset          = AM35XX_EMAC_MDIO_OFFSET;
         pdata->ctrl_ram_size            = AM35XX_EMAC_CNTRL_RAM_SIZE;
         pdata->version                  = EMAC_VERSION_2;
         pdata->hw_ram_addr              = AM35XX_EMAC_HW_RAM_ADDR;
@@ -121,6 +140,9 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
         pdata->interrupt_disable        = am3517_disable_ethernet_int;
         am3517_emac_device.dev.platform_data    = pdata;
         platform_device_register(&am3517_emac_device);
+        platform_device_register(&am3517_mdio_device);
+        clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
+                      NULL, &am3517_emac_device.dev);
 
         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
         regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
@@ -139,7 +161,6 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = {
         {
                 I2C_BOARD_INFO("s35390a", 0x30),
-                .type           = "s35390a",
         },
 };
 
@@ -153,19 +174,14 @@ static void __init am3517_evm_rtc_init(void)
         int r;
 
         omap_mux_init_gpio(GPIO_RTCS35390A_IRQ, OMAP_PIN_INPUT_PULLUP);
-        r = gpio_request(GPIO_RTCS35390A_IRQ, "rtcs35390a-irq");
+
+        r = gpio_request_one(GPIO_RTCS35390A_IRQ, GPIOF_IN, "rtcs35390a-irq");
         if (r < 0) {
                 printk(KERN_WARNING "failed to request GPIO#%d\n",
                                 GPIO_RTCS35390A_IRQ);
                 return;
         }
-        r = gpio_direction_input(GPIO_RTCS35390A_IRQ);
-        if (r < 0) {
-                printk(KERN_WARNING "GPIO#%d cannot be configured as input\n",
-                                GPIO_RTCS35390A_IRQ);
-                gpio_free(GPIO_RTCS35390A_IRQ);
-                return;
-        }
+
         am3517evm_i2c1_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ);
 }
 
@@ -179,6 +195,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
 };
 static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
         {
+                I2C_BOARD_INFO("tlv320aic23", 0x1A),
+        },
+        {
                 I2C_BOARD_INFO("tca6416", 0x21),
                 .platform_data = &am3517evm_gpio_expander_info_0,
         },
@@ -218,6 +237,15 @@ static int dvi_enabled;
 
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
                 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
+static struct gpio am3517_evm_dss_gpios[] __initdata = {
+        /* GPIO 182 = LCD Backlight Power */
+        { LCD_PANEL_BKLIGHT_PWR, GPIOF_OUT_INIT_HIGH, "lcd_backlight_pwr" },
+        /* GPIO 181 = LCD Panel PWM */
+        { LCD_PANEL_PWM,         GPIOF_OUT_INIT_HIGH, "lcd bl enable"     },
+        /* GPIO 176 = LCD Panel Power enable pin */
+        { LCD_PANEL_PWR,         GPIOF_OUT_INIT_HIGH, "dvi enable"        },
+};
+
 static void __init am3517_evm_display_init(void)
 {
         int r;
@@ -225,41 +253,15 @@ static void __init am3517_evm_display_init(void)
         omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP);
         omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN);
         omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN);
-        /*
-         * Enable GPIO 182 = LCD Backlight Power
-         */
-        r = gpio_request(LCD_PANEL_BKLIGHT_PWR, "lcd_backlight_pwr");
+
+        r = gpio_request_array(am3517_evm_dss_gpios,
+                               ARRAY_SIZE(am3517_evm_dss_gpios));
         if (r) {
-                printk(KERN_ERR "failed to get lcd_backlight_pwr\n");
+                printk(KERN_ERR "failed to get DSS panel control GPIOs\n");
                 return;
         }
-        gpio_direction_output(LCD_PANEL_BKLIGHT_PWR, 1);
-        /*
-         * Enable GPIO 181 = LCD Panel PWM
-         */
-        r = gpio_request(LCD_PANEL_PWM, "lcd_pwm");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_pwm\n");
-                goto err_1;
-        }
-        gpio_direction_output(LCD_PANEL_PWM, 1);
-        /*
-         * Enable GPIO 176 = LCD Panel Power enable pin
-         */
-        r = gpio_request(LCD_PANEL_PWR, "lcd_panel_pwr");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_pwr\n");
-                goto err_2;
-        }
-        gpio_direction_output(LCD_PANEL_PWR, 1);
 
         printk(KERN_INFO "Display initialized successfully\n");
-        return;
-
-err_2:
-        gpio_free(LCD_PANEL_PWM);
-err_1:
-        gpio_free(LCD_PANEL_BKLIGHT_PWR);
 }
 #else
 static void __init am3517_evm_display_init(void) {}
@@ -283,13 +285,18 @@ static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev)
         lcd_enabled = 0;
 }
 
+static struct panel_generic_dpi_data lcd_panel = {
+        .name                   = "sharp_lq",
+        .platform_enable        = am3517_evm_panel_enable_lcd,
+        .platform_disable       = am3517_evm_panel_disable_lcd,
+};
+
 static struct omap_dss_device am3517_evm_lcd_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "lcd",
-        .driver_name            = "sharp_lq_panel",
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &lcd_panel,
         .phy.dpi.data_lines     = 16,
-        .platform_enable        = am3517_evm_panel_enable_lcd,
-        .platform_disable       = am3517_evm_panel_disable_lcd,
 };
 
 static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev)
@@ -326,13 +333,18 @@ static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
         dvi_enabled = 0;
 }
 
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = am3517_evm_panel_enable_dvi,
+        .platform_disable       = am3517_evm_panel_disable_dvi,
+};
+
 static struct omap_dss_device am3517_evm_dvi_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = am3517_evm_panel_enable_dvi,
-        .platform_disable       = am3517_evm_panel_disable_dvi,
 };
 
 static struct omap_dss_device *am3517_evm_dss_devices[] = {
@@ -347,43 +359,53 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
         .default_device = &am3517_evm_lcd_device,
 };
 
-struct platform_device am3517_evm_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &am3517_evm_dss_data,
-        },
-};
-
 /*
  * Board initialization
  */
-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
-};
+static void __init am3517_evm_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
 
-static struct platform_device *am3517_evm_devices[] __initdata = {
-        &am3517_evm_dss_device,
+static struct omap_musb_board_data musb_board_data = {
+        .interface_type         = MUSB_INTERFACE_ULPI,
+        .mode                   = MUSB_OTG,
+        .power                  = 500,
+        .set_phy_power          = am35x_musb_phy_power,
+        .clear_irq              = am35x_musb_clear_irq,
+        .set_mode               = am35x_set_mode,
+        .reset                  = am35x_musb_reset,
 };
 
-static void __init am3517_evm_init_irq(void)
+static __init void am3517_evm_musb_init(void)
 {
-        omap_board_config = am3517_evm_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
+        u32 devconf2;
+
+        /*
+         * Set up USB clock/mode in the DEVCONF2 register.
+         */
+        devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
+        /* USB2.0 PHY reference clock is 13 MHz */
+        devconf2 &= ~(CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE);
+        devconf2 |=  CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | CONF2_VBDTCTEN
+                        | CONF2_DATPOL;
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+
+        usb_musb_init(&musb_board_data);
 }
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
                 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
 #else
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 #endif
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = 57,
@@ -393,10 +415,10 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* USB OTG DRVVBUS offset = 0x212 */
+        OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 
@@ -435,19 +457,22 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
         platform_device_register(&am3517_hecc_device);
 }
 
+static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
+};
+
 static void __init am3517_evm_init(void)
 {
+        omap_board_config = am3517_evm_config;
+        omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         am3517_evm_i2c_init();
-        platform_add_devices(am3517_evm_devices,
-                                ARRAY_SIZE(am3517_evm_devices));
-
+        omap_display_init(&am3517_evm_dss_data);
         omap_serial_init();
 
         /* Configure GPIO for EHCI port */
         omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
-        usb_ehci_init(&ehci_pdata);
+        usbhs_init(&usbhs_bdata);
         am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
         /* DSS */
         am3517_evm_display_init();
@@ -459,15 +484,17 @@ static void __init am3517_evm_init(void)
                                 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
         /*Ethernet*/
         am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
+
+        /* MUSB */
+        am3517_evm_musb_init();
 }
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = am3517_evm_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = am3517_evm_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = am3517_evm_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index c6421a72514a..b124bdfb4239 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -27,21 +27,21 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/smc91x.h>
+#include <linux/gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <mach/gpio.h>
 #include <plat/led.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
-#include <plat/control.h>
 
 #include "mux.h"
+#include "control.h"
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
@@ -202,6 +202,7 @@ static inline void __init apollon_init_smc91x(void)
         unsigned int rate;
         struct clk *gpmc_fck;
         int eth_cs;
+        int err;
 
         gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
         if (IS_ERR(gpmc_fck)) {
@@ -245,15 +246,13 @@ static inline void __init apollon_init_smc91x(void)
         apollon_smc91x_resources[0].end   = base + 0x30f;
         udelay(100);
 
-        omap_mux_init_gpio(74, 0);
-        if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
+        omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0);
+        err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq");
+        if (err) {
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         APOLLON_ETHR_GPIO_IRQ);
                 gpmc_cs_free(APOLLON_ETH_CS);
-                goto out;
         }
-        gpio_direction_input(APOLLON_ETHR_GPIO_IRQ);
-
 out:
         clk_disable(gpmc_fck);
         clk_put(gpmc_fck);
@@ -270,34 +269,29 @@ static struct omap_lcd_config apollon_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel apollon_config[] = {
+static struct omap_board_config_kernel apollon_config[] __initdata = {
         { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
 
-static void __init omap_apollon_init_irq(void)
+static void __init omap_apollon_init_early(void)
 {
-        omap_board_config = apollon_config;
-        omap_board_config_size = ARRAY_SIZE(apollon_config);
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
-        apollon_init_smc91x();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 }
 
+static struct gpio apollon_gpio_leds[] __initdata = {
+        { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
+        { LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6  */
+        { LED2_GPIO15, GPIOF_OUT_INIT_LOW, "LED2" }, /* LED2 - AA4  */
+};
+
 static void __init apollon_led_init(void)
 {
-        /* LED0 - AA10 */
         omap_mux_init_signal("vlynq_clk.gpio_13", 0);
-        gpio_request(LED0_GPIO13, "LED0");
-        gpio_direction_output(LED0_GPIO13, 0);
-        /* LED1  - AA6 */
         omap_mux_init_signal("vlynq_rx1.gpio_14", 0);
-        gpio_request(LED1_GPIO14, "LED1");
-        gpio_direction_output(LED1_GPIO14, 0);
-        /* LED2  - AA4 */
         omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
-        gpio_request(LED2_GPIO15, "LED2");
-        gpio_direction_output(LED2_GPIO15, 0);
+
+        gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
 }
 
 static void __init apollon_usb_init(void)
@@ -305,8 +299,7 @@ static void __init apollon_usb_init(void)
         /* USB device */
         /* DEVICE_SUSPEND */
         omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
-        gpio_request(12, "USB suspend");
-        gpio_direction_output(12, 0);
+        gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend");
         omap2_usbfs_init(&apollon_usb_config);
 }
 
@@ -314,8 +307,6 @@ static void __init apollon_usb_init(void)
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap_apollon_init(void)
@@ -323,7 +314,10 @@ static void __init omap_apollon_init(void)
         u32 v;
 
         omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+        omap_board_config = apollon_config;
+        omap_board_config_size = ARRAY_SIZE(apollon_config);
 
+        apollon_init_smc91x();
         apollon_led_init();
         apollon_flash_init();
         apollon_usb_init();
@@ -356,12 +350,11 @@ static void __init omap_apollon_map_io(void)
 
 MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap_apollon_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_apollon_init_irq,
+        .map_io         = omap_apollon_map_io,
+        .init_early     = omap_apollon_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_apollon_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e10bc109415c..77456dec93ea 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/mmc/host.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/tdo24m.h>
@@ -44,7 +45,8 @@
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/mcspi.h>
 
 #include <mach/hardware.h>
@@ -52,6 +54,7 @@
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define CM_T35_GPIO_PENDOWN     57
 
@@ -60,90 +63,30 @@
 #define SB_T35_SMSC911X_CS      4
 #define SB_T35_SMSC911X_GPIO    65
 
-#define NAND_BLOCK_SIZE         SZ_128K
-
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
+#include <plat/gpmc-smsc911x.h>
 
-static struct smsc911x_platform_config cm_t35_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource cm_t35_smsc911x_resources[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP_GPIO_IRQ(CM_T35_SMSC911X_GPIO),
-                .end    = OMAP_GPIO_IRQ(CM_T35_SMSC911X_GPIO),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct platform_device cm_t35_smsc911x_device = {
-        .name           = "smsc911x",
+static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(cm_t35_smsc911x_resources),
-        .resource       = cm_t35_smsc911x_resources,
-        .dev            = {
-                .platform_data = &cm_t35_smsc911x_config,
-        },
-};
-
-static struct resource sb_t35_smsc911x_resources[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP_GPIO_IRQ(SB_T35_SMSC911X_GPIO),
-                .end    = OMAP_GPIO_IRQ(SB_T35_SMSC911X_GPIO),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
+        .cs             = CM_T35_SMSC911X_CS,
+        .gpio_irq       = CM_T35_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
-static struct platform_device sb_t35_smsc911x_device = {
-        .name           = "smsc911x",
+static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
         .id             = 1,
-        .num_resources  = ARRAY_SIZE(sb_t35_smsc911x_resources),
-        .resource       = sb_t35_smsc911x_resources,
-        .dev            = {
-                .platform_data = &cm_t35_smsc911x_config,
-        },
+        .cs             = SB_T35_SMSC911X_CS,
+        .gpio_irq       = SB_T35_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
-static void __init cm_t35_init_smsc911x(struct platform_device *dev,
-                                        int cs, int irq_gpio)
-{
-        unsigned long cs_mem_base;
-
-        if (gpmc_cs_request(cs, SZ_16M, &cs_mem_base) < 0) {
-                pr_err("CM-T35: Failed request for GPMC mem for smsc911x\n");
-                return;
-        }
-
-        dev->resource[0].start = cs_mem_base + 0x0;
-        dev->resource[0].end   = cs_mem_base + 0xff;
-
-        if ((gpio_request(irq_gpio, "ETH IRQ") == 0) &&
-            (gpio_direction_input(irq_gpio) == 0)) {
-                gpio_export(irq_gpio, 0);
-        } else {
-                pr_err("CM-T35: could not obtain gpio for SMSC911X IRQ\n");
-                return;
-        }
-
-        platform_device_register(dev);
-}
-
 static void __init cm_t35_init_ethernet(void)
 {
-        cm_t35_init_smsc911x(&cm_t35_smsc911x_device,
-                             CM_T35_SMSC911X_CS, CM_T35_SMSC911X_GPIO);
-        cm_t35_init_smsc911x(&sb_t35_smsc911x_device,
-                             SB_T35_SMSC911X_CS, SB_T35_SMSC911X_GPIO);
+        gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
+        gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
 }
 #else
 static inline void __init cm_t35_init_ethernet(void) { return; }
@@ -233,71 +176,10 @@ static void __init cm_t35_init_nand(void)
 static inline void cm_t35_init_nand(void) {}
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
-        defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-#include <linux/spi/ads7846.h>
-
-#include <plat/mcspi.h>
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(CM_T35_GPIO_PENDOWN);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct spi_board_info cm_t35_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(CM_T35_GPIO_PENDOWN),
-                .platform_data          = &ads7846_config,
-        },
-};
-
-static void __init cm_t35_init_ads7846(void)
-{
-        if ((gpio_request(CM_T35_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) &&
-            (gpio_direction_input(CM_T35_GPIO_PENDOWN) == 0)) {
-                gpio_export(CM_T35_GPIO_PENDOWN, 0);
-        } else {
-                pr_err("CM-T35: could not obtain gpio for ADS7846_PENDOWN\n");
-                return;
-        }
-
-        spi_register_board_info(cm_t35_spi_board_info,
-                                ARRAY_SIZE(cm_t35_spi_board_info));
-}
-#else
-static inline void cm_t35_init_ads7846(void) {}
-#endif
-
 #define CM_T35_LCD_EN_GPIO 157
 #define CM_T35_LCD_BL_GPIO 58
 #define CM_T35_DVI_EN_GPIO 54
 
-static int lcd_bl_gpio;
-static int lcd_en_gpio;
-static int dvi_en_gpio;
-
 static int lcd_enabled;
 static int dvi_enabled;
 
@@ -308,8 +190,8 @@ static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(lcd_en_gpio, 1);
-        gpio_set_value(lcd_bl_gpio, 1);
+        gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
+        gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
 
         lcd_enabled = 1;
 
@@ -320,8 +202,8 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
         lcd_enabled = 0;
 
-        gpio_set_value(lcd_bl_gpio, 0);
-        gpio_set_value(lcd_en_gpio, 0);
+        gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
+        gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
 }
 
 static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
@@ -331,7 +213,7 @@ static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(dvi_en_gpio, 0);
+        gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
         dvi_enabled = 1;
 
         return 0;
@@ -339,7 +221,7 @@ static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
 
 static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
-        gpio_set_value(dvi_en_gpio, 1);
+        gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
         dvi_enabled = 0;
 }
 
@@ -352,22 +234,32 @@ static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
 {
 }
 
+static struct panel_generic_dpi_data lcd_panel = {
+        .name                   = "toppoly_tdo35s",
+        .platform_enable        = cm_t35_panel_enable_lcd,
+        .platform_disable       = cm_t35_panel_disable_lcd,
+};
+
 static struct omap_dss_device cm_t35_lcd_device = {
         .name                   = "lcd",
-        .driver_name            = "toppoly_tdo35s_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &lcd_panel,
         .phy.dpi.data_lines     = 18,
-        .platform_enable        = cm_t35_panel_enable_lcd,
-        .platform_disable       = cm_t35_panel_disable_lcd,
+};
+
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = cm_t35_panel_enable_dvi,
+        .platform_disable       = cm_t35_panel_disable_dvi,
 };
 
 static struct omap_dss_device cm_t35_dvi_device = {
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = cm_t35_panel_enable_dvi,
-        .platform_disable       = cm_t35_panel_disable_dvi,
 };
 
 static struct omap_dss_device cm_t35_tv_device = {
@@ -391,14 +283,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
         .default_device = &cm_t35_dvi_device,
 };
 
-static struct platform_device cm_t35_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &cm_t35_dss_data,
-        },
-};
-
 static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
         .turbo_mode     = 0,
         .single_channel = 1,    /* 0: slave, 1: master */
@@ -419,62 +303,38 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
         },
 };
 
+static struct gpio cm_t35_dss_gpios[] __initdata = {
+        { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,  "lcd enable"    },
+        { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW,  "lcd bl enable" },
+        { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable"    },
+};
+
 static void __init cm_t35_init_display(void)
 {
         int err;
 
-        lcd_en_gpio = CM_T35_LCD_EN_GPIO;
-        lcd_bl_gpio = CM_T35_LCD_BL_GPIO;
-        dvi_en_gpio = CM_T35_DVI_EN_GPIO;
-
         spi_register_board_info(cm_t35_lcd_spi_board_info,
                                 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
 
-        err = gpio_request(lcd_en_gpio, "LCD RST");
-        if (err) {
-                pr_err("CM-T35: failed to get LCD reset GPIO\n");
-                goto out;
-        }
-
-        err = gpio_request(lcd_bl_gpio, "LCD BL");
+        err = gpio_request_array(cm_t35_dss_gpios,
+                                 ARRAY_SIZE(cm_t35_dss_gpios));
         if (err) {
-                pr_err("CM-T35: failed to get LCD backlight control GPIO\n");
-                goto err_lcd_bl;
-        }
-
-        err = gpio_request(dvi_en_gpio, "DVI EN");
-        if (err) {
-                pr_err("CM-T35: failed to get DVI reset GPIO\n");
-                goto err_dvi_en;
+                pr_err("CM-T35: failed to request DSS control GPIOs\n");
+                return;
         }
 
-        gpio_export(lcd_en_gpio, 0);
-        gpio_export(lcd_bl_gpio, 0);
-        gpio_export(dvi_en_gpio, 0);
-        gpio_direction_output(lcd_en_gpio, 0);
-        gpio_direction_output(lcd_bl_gpio, 0);
-        gpio_direction_output(dvi_en_gpio, 1);
+        gpio_export(CM_T35_LCD_EN_GPIO, 0);
+        gpio_export(CM_T35_LCD_BL_GPIO, 0);
+        gpio_export(CM_T35_DVI_EN_GPIO, 0);
 
         msleep(50);
-        gpio_set_value(lcd_en_gpio, 1);
+        gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
 
-        err = platform_device_register(&cm_t35_dss_device);
+        err = omap_display_init(&cm_t35_dss_data);
         if (err) {
                 pr_err("CM-T35: failed to register DSS device\n");
-                goto err_dev_reg;
+                gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios));
         }
-
-        return;
-
-err_dev_reg:
-        gpio_free(dvi_en_gpio);
-err_dvi_en:
-        gpio_free(lcd_bl_gpio);
-err_lcd_bl:
-        gpio_free(lcd_en_gpio);
-out:
-
-        return;
 }
 
 static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
@@ -485,15 +345,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
         .supply                 = "vmmc_aux",
 };
 
-static struct regulator_consumer_supply cm_t35_vdac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &cm_t35_dss_device.dev,
-};
+static struct regulator_consumer_supply cm_t35_vdac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
 
-static struct regulator_consumer_supply cm_t35_vdvi_supply = {
-        .supply         = "vdvi",
-        .dev            = &cm_t35_dss_device.dev,
-};
+static struct regulator_consumer_supply cm_t35_vdvi_supply =
+        REGULATOR_SUPPLY("vdvi", "omapdss");
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data cm_t35_vmmc1 = {
@@ -558,7 +414,7 @@ static struct twl4030_usb_data cm_t35_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int cm_t35_keymap[] = {
+static uint32_t cm_t35_keymap[] = {
         KEY(0, 0, KEY_A),       KEY(0, 1, KEY_B),       KEY(0, 2, KEY_LEFT),
         KEY(1, 0, KEY_UP),      KEY(1, 1, KEY_ENTER),   KEY(1, 2, KEY_DOWN),
         KEY(2, 0, KEY_RIGHT),   KEY(2, 1, KEY_C),       KEY(2, 2, KEY_D),
@@ -579,14 +435,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
 
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .transceiver    = 1,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
@@ -595,14 +451,14 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+static struct usbhs_omap_board_data usbhs_bdata __initdata = {
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[0]  = OMAP_MAX_GPIO_LINES + 6,
+        .reset_gpio_port[1]  = OMAP_MAX_GPIO_LINES + 7,
         .reset_gpio_port[2]  = -EINVAL
 };
 
@@ -611,10 +467,8 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 {
         int wlan_rst = gpio + 2;
 
-        if ((gpio_request(wlan_rst, "WLAN RST") == 0) &&
-            (gpio_direction_output(wlan_rst, 1) == 0)) {
+        if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
                 gpio_export(wlan_rst, 0);
-
                 udelay(10);
                 gpio_set_value(wlan_rst, 0);
                 udelay(10);
@@ -631,12 +485,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
         cm_t35_vmmc1_supply.dev = mmc[0].dev;
         cm_t35_vsim_supply.dev = mmc[0].dev;
 
-        /* setup USB with proper PHY reset GPIOs */
-        ehci_pdata.reset_gpio_port[0] = gpio + 6;
-        ehci_pdata.reset_gpio_port[1] = gpio + 7;
-
-        usb_ehci_init(&ehci_pdata);
-
         return 0;
 }
 
@@ -661,35 +509,19 @@ static struct twl4030_platform_data cm_t35_twldata = {
         .vpll2          = &cm_t35_vpll2,
 };
 
-static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65930", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &cm_t35_twldata,
-        },
-};
-
 static void __init cm_t35_init_i2c(void)
 {
-        omap_register_i2c_bus(1, 2600, cm_t35_i2c_boardinfo,
-                              ARRAY_SIZE(cm_t35_i2c_boardinfo));
+        omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
 
-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
-};
-
-static void __init cm_t35_init_irq(void)
+static void __init cm_t35_init_early(void)
 {
-        omap_board_config = cm_t35_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
-
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* nCS and IRQ for CM-T35 ethernet */
         OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
@@ -787,34 +619,34 @@ static struct omap_board_mux board_mux[] __initdata = {
 
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+#endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
+static struct omap_board_config_kernel cm_t35_config[] __initdata = {
 };
 
 static void __init cm_t35_init(void)
 {
+        omap_board_config = cm_t35_config;
+        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
         cm_t35_init_i2c();
         cm_t35_init_nand();
-        cm_t35_init_ads7846();
+        omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
         cm_t35_init_ethernet();
         cm_t35_init_led();
         cm_t35_init_display();
 
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
+        usbhs_init(&usbhs_bdata);
 }
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = cm_t35_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = cm_t35_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = cm_t35_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
new file mode 100644
index 000000000000..c3a9fd35034a
--- /dev/null
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -0,0 +1,310 @@
+/*
+ * linux/arch/arm/mach-omap2/board-cm-t3517.c
+ *
+ * Support for the CompuLab CM-T3517 modules
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/rtc-v3020.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/can/platform/ti_hecc.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/usb.h>
+#include <plat/nand.h>
+#include <plat/gpmc.h>
+
+#include <mach/am35xx.h>
+
+#include "mux.h"
+#include "control.h"
+#include "common-board-devices.h"
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led cm_t3517_leds[] = {
+        [0] = {
+                .gpio                   = 186,
+                .name                   = "cm-t3517:green",
+                .default_trigger        = "heartbeat",
+                .active_low             = 0,
+        },
+};
+
+static struct gpio_led_platform_data cm_t3517_led_pdata = {
+        .num_leds       = ARRAY_SIZE(cm_t3517_leds),
+        .leds           = cm_t3517_leds,
+};
+
+static struct platform_device cm_t3517_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &cm_t3517_led_pdata,
+        },
+};
+
+static void __init cm_t3517_init_leds(void)
+{
+        platform_device_register(&cm_t3517_led_device);
+}
+#else
+static inline void cm_t3517_init_leds(void) {}
+#endif
+
+#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE)
+static struct resource cm_t3517_hecc_resources[] = {
+        {
+                .start  = AM35XX_IPSS_HECC_BASE,
+                .end    = AM35XX_IPSS_HECC_BASE + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_35XX_HECC0_IRQ,
+                .end    = INT_35XX_HECC0_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ti_hecc_platform_data cm_t3517_hecc_pdata = {
+        .scc_hecc_offset        = AM35XX_HECC_SCC_HECC_OFFSET,
+        .scc_ram_offset         = AM35XX_HECC_SCC_RAM_OFFSET,
+        .hecc_ram_offset        = AM35XX_HECC_RAM_OFFSET,
+        .mbx_offset             = AM35XX_HECC_MBOX_OFFSET,
+        .int_line               = AM35XX_HECC_INT_LINE,
+        .version                = AM35XX_HECC_VERSION,
+};
+
+static struct platform_device cm_t3517_hecc_device = {
+        .name           = "ti_hecc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(cm_t3517_hecc_resources),
+        .resource       = cm_t3517_hecc_resources,
+        .dev            = {
+                .platform_data  = &cm_t3517_hecc_pdata,
+        },
+};
+
+static void cm_t3517_init_hecc(void)
+{
+        platform_device_register(&cm_t3517_hecc_device);
+}
+#else
+static inline void cm_t3517_init_hecc(void) {}
+#endif
+
+#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
+#define RTC_IO_GPIO             (153)
+#define RTC_WR_GPIO             (154)
+#define RTC_RD_GPIO             (53)
+#define RTC_CS_GPIO             (163)
+#define RTC_CS_EN_GPIO          (160)
+
+struct v3020_platform_data cm_t3517_v3020_pdata = {
+        .use_gpio       = 1,
+        .gpio_cs        = RTC_CS_GPIO,
+        .gpio_wr        = RTC_WR_GPIO,
+        .gpio_rd        = RTC_RD_GPIO,
+        .gpio_io        = RTC_IO_GPIO,
+};
+
+static struct platform_device cm_t3517_rtc_device = {
+        .name           = "v3020",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cm_t3517_v3020_pdata,
+        }
+};
+
+static void __init cm_t3517_init_rtc(void)
+{
+        int err;
+
+        err = gpio_request_one(RTC_CS_EN_GPIO, GPIOF_OUT_INIT_HIGH,
+                               "rtc cs en");
+        if (err) {
+                pr_err("CM-T3517: rtc cs en gpio request failed: %d\n", err);
+                return;
+        }
+
+        platform_device_register(&cm_t3517_rtc_device);
+}
+#else
+static inline void cm_t3517_init_rtc(void) {}
+#endif
+
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+#define HSUSB1_RESET_GPIO       (146)
+#define HSUSB2_RESET_GPIO       (147)
+#define USB_HUB_RESET_GPIO      (152)
+
+static struct usbhs_omap_board_data cm_t3517_ehci_pdata __initdata = {
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
+        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
+        .reset_gpio_port[2]  = -EINVAL,
+};
+
+static int __init cm_t3517_init_usbh(void)
+{
+        int err;
+
+        err = gpio_request_one(USB_HUB_RESET_GPIO, GPIOF_OUT_INIT_LOW,
+                               "usb hub rst");
+        if (err) {
+                pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err);
+        } else {
+                udelay(10);
+                gpio_set_value(USB_HUB_RESET_GPIO, 1);
+                msleep(1);
+        }
+
+        usbhs_init(&cm_t3517_ehci_pdata);
+
+        return 0;
+}
+#else
+static inline int cm_t3517_init_usbh(void)
+{
+        return 0;
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+static struct mtd_partition cm_t3517_nand_partitions[] = {
+        {
+                .name           = "xloader",
+                .offset         = 0,                    /* Offset = 0x00000 */
+                .size           = 4 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "uboot",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+                .size           = 15 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "uboot environment",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
+                .size           = 2 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "linux",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2A0000 */
+                .size           = 32 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x6A0000 */
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_nand_platform_data cm_t3517_nand_data = {
+        .parts                  = cm_t3517_nand_partitions,
+        .nr_parts               = ARRAY_SIZE(cm_t3517_nand_partitions),
+        .dma_channel            = -1,   /* disable DMA in OMAP NAND driver */
+        .cs                     = 0,
+};
+
+static void __init cm_t3517_init_nand(void)
+{
+        if (gpmc_nand_init(&cm_t3517_nand_data) < 0)
+                pr_err("CM-T3517: NAND initialization failed\n");
+}
+#else
+static inline void cm_t3517_init_nand(void) {}
+#endif
+
+static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
+};
+
+static void __init cm_t3517_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        /* GPIO186 - Green LED */
+        OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* RTC GPIOs: */
+        /* IO - GPIO153 */
+        OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* WR# - GPIO154 */
+        OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* RD# - GPIO53 */
+        OMAP3_MUX(GPMC_NCS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* CS# - GPIO163 */
+        OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* CS EN - GPIO160 */
+        OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* HSUSB1 RESET */
+        OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* HSUSB2 RESET */
+        OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* CM-T3517 USB HUB nRESET */
+        OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#endif
+
+static void __init cm_t3517_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+        omap_board_config = cm_t3517_config;
+        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
+        cm_t3517_init_leds();
+        cm_t3517_init_nand();
+        cm_t3517_init_rtc();
+        cm_t3517_init_usbh();
+        cm_t3517_init_hecc();
+}
+
+MACHINE_START(CM_T3517, "Compulab CM-T3517")
+        .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = cm_t3517_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = cm_t3517_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a07086d6a0b2..34956ec83296 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -44,13 +45,12 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/dm9000.h>
 #include <linux/interrupt.h>
 
@@ -58,8 +58,8 @@
 
 #include "mux.h"
 #include "hsmmc.h"
-
-#define NAND_BLOCK_SIZE         SZ_128K
+#include "timer-gp.h"
+#include "common-board-devices.h"
 
 #define OMAP_DM9000_GPIO_IRQ    25
 #define OMAP3_DEVKIT_TS_GPIO    27
@@ -95,17 +95,10 @@ static struct mtd_partition devkit8000_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data devkit8000_nand_data = {
-        .options        = NAND_BUSWIDTH_16,
-        .parts          = devkit8000_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(devkit8000_nand_partitions),
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -113,58 +106,64 @@ static struct omap2_hsmmc_info mmc[] = {
 
 static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
 {
-        twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1);
-        twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
-
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
         return 0;
 }
 
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
 {
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
         return 0;
 }
 
 static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 
 static struct regulator_consumer_supply devkit8000_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 
 /* ads7846 on SPI */
 static struct regulator_consumer_supply devkit8000_vio_supply =
         REGULATOR_SUPPLY("vcc", "spi2.0");
 
+static struct panel_generic_dpi_data lcd_panel = {
+        .name                   = "generic",
+        .platform_enable        = devkit8000_panel_enable_lcd,
+        .platform_disable       = devkit8000_panel_disable_lcd,
+};
+
 static struct omap_dss_device devkit8000_lcd_device = {
         .name                   = "lcd",
-        .driver_name            = "generic_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &lcd_panel,
         .phy.dpi.data_lines     = 24,
-        .reset_gpio             = -EINVAL, /* will be replaced */
-        .platform_enable        = devkit8000_panel_enable_lcd,
-        .platform_disable       = devkit8000_panel_disable_lcd,
 };
+
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = devkit8000_panel_enable_dvi,
+        .platform_disable       = devkit8000_panel_disable_dvi,
+};
+
 static struct omap_dss_device devkit8000_dvi_device = {
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .reset_gpio             = -EINVAL, /* will be replaced */
-        .platform_enable        = devkit8000_panel_enable_dvi,
-        .platform_disable       = devkit8000_panel_disable_dvi,
 };
 
 static struct omap_dss_device devkit8000_tv_device = {
@@ -187,18 +186,10 @@ static struct omap_dss_board_info devkit8000_dss_data = {
         .default_device = &devkit8000_lcd_device,
 };
 
-static struct platform_device devkit8000_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &devkit8000_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss");
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
         KEY(2, 0, KEY_3),
@@ -236,28 +227,33 @@ static struct gpio_led gpio_leds[];
 static int devkit8000_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int ret;
+
         omap_mux_init_gpio(29, OMAP_PIN_INPUT);
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        devkit8000_vmmc1_supply.dev = mmc[0].dev;
-
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
 
-        /* gpio + 1 is "LCD_PWREN" (out, active high) */
-        devkit8000_lcd_device.reset_gpio = gpio + 1;
-        gpio_request(devkit8000_lcd_device.reset_gpio, "LCD_PWREN");
-        /* Disable until needed */
-        gpio_direction_output(devkit8000_lcd_device.reset_gpio, 0);
+        /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */
+        devkit8000_lcd_device.reset_gpio = gpio + TWL4030_GPIO_MAX + 0;
+        ret = gpio_request_one(devkit8000_lcd_device.reset_gpio,
+                               GPIOF_OUT_INIT_LOW, "LCD_PWREN");
+        if (ret < 0) {
+                devkit8000_lcd_device.reset_gpio = -EINVAL;
+                printk(KERN_ERR "Failed to request GPIO for LCD_PWRN\n");
+        }
 
         /* gpio + 7 is "DVI_PD" (out, active low) */
         devkit8000_dvi_device.reset_gpio = gpio + 7;
-        gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown");
-        /* Disable until needed */
-        gpio_direction_output(devkit8000_dvi_device.reset_gpio, 0);
+        ret = gpio_request_one(devkit8000_dvi_device.reset_gpio,
+                               GPIOF_OUT_INIT_LOW, "DVI PowerDown");
+        if (ret < 0) {
+                devkit8000_dvi_device.reset_gpio = -EINVAL;
+                printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n");
+        }
 
         return 0;
 }
@@ -267,14 +263,15 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
-        .pullups        = BIT(1),
-        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
+        .pulldowns      = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                 | BIT(15) | BIT(16) | BIT(17),
         .setup          = devkit8000_twl_gpio_setup,
 };
 
-static struct regulator_consumer_supply devkit8000_vpll1_supply =
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data devkit8000_vmmc1 = {
@@ -315,8 +312,8 @@ static struct regulator_init_data devkit8000_vpll1 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &devkit8000_vpll1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vpll1_supplies),
+        .consumer_supplies      = devkit8000_vpll1_supplies,
 };
 
 /* VAUX4 for ads7846 and nubs */
@@ -338,9 +335,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data devkit8000_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data devkit8000_audio_data;
 
 static struct twl4030_codec_data devkit8000_codec_data = {
         .audio_mclk = 26000000,
@@ -362,19 +357,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
         .keypad         = &devkit8000_kp_data,
 };
 
-static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65930", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &devkit8000_twldata,
-        },
-};
-
 static int __init devkit8000_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, devkit8000_i2c_boardinfo,
-                        ARRAY_SIZE(devkit8000_i2c_boardinfo));
+        omap3_pmic_init("tps65930", &devkit8000_twldata);
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -444,67 +429,21 @@ static struct platform_device keys_gpio = {
 };
 
 
+static void __init devkit8000_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
+}
+
 static void __init devkit8000_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
-static void __init devkit8000_ads7846_init(void)
-{
-        int gpio = OMAP3_DEVKIT_TS_GPIO;
-        int ret;
-
-        ret = gpio_request(gpio, "ads7846_pen_down");
-        if (ret < 0) {
-                printk(KERN_ERR "Failed to request GPIO %d for "
-                                "ads7846 pen down IRQ\n", gpio);
-                return;
-        }
-
-        gpio_direction_input(gpio);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_DEVKIT_TS_GPIO);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 5,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .settle_delay_usecs     = 150,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info devkit8000_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 2,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_DEVKIT_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        }
-};
-
 #define OMAP_DM9000_BASE        0x2c000000
 
 static struct resource omap_dm9000_resources[] = {
@@ -542,14 +481,14 @@ static void __init omap_dm9000_init(void)
 {
         unsigned char *eth_addr = omap_dm9000_platdata.dev_addr;
         struct omap_die_id odi;
+        int ret;
 
-        if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) {
+        ret = gpio_request_one(OMAP_DM9000_GPIO_IRQ, GPIOF_IN, "dm9000 irq");
+        if (ret < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n",
                         OMAP_DM9000_GPIO_IRQ);
                 return;
-                }
-
-        gpio_direction_input(OMAP_DM9000_GPIO_IRQ);
+        }
 
         /* init the mac address using DIE id */
         omap_get_die_id(&odi);
@@ -563,56 +502,16 @@ static void __init omap_dm9000_init(void)
 }
 
 static struct platform_device *devkit8000_devices[] __initdata = {
-        &devkit8000_dss_device,
         &leds_gpio,
         &keys_gpio,
         &omap_dm9000_dev,
 };
 
-static void __init devkit8000_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        if (nandcs < GPMC_CS_NUM) {
-                devkit8000_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&devkit8000_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = -EINVAL,
@@ -620,6 +519,7 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* nCS and IRQ for Devkit8000 ethernet */
         OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE0),
@@ -773,6 +673,7 @@ static struct omap_board_mux board_mux[] __initdata = {
 
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+#endif
 
 static void __init devkit8000_init(void)
 {
@@ -785,14 +686,14 @@ static void __init devkit8000_init(void)
         platform_add_devices(devkit8000_devices,
                         ARRAY_SIZE(devkit8000_devices));
 
-        spi_register_board_info(devkit8000_spi_board_info,
-        ARRAY_SIZE(devkit8000_spi_board_info));
+        omap_display_init(&devkit8000_dss_data);
 
-        devkit8000_ads7846_init();
+        omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
 
-        usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
-        devkit8000_flash_init();
+        usb_musb_init(NULL);
+        usbhs_init(&usbhs_bdata);
+        omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
+                             ARRAY_SIZE(devkit8000_nand_partitions));
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -800,11 +701,10 @@ static void __init devkit8000_init(void)
 }
 
 MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = devkit8000_init_early,
         .init_irq       = devkit8000_init_irq,
         .init_machine   = devkit8000_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index ac834aa7abf6..729892fdcf2e 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -1,5 +1,5 @@
 /*
- * board-sdp-flash.c
+ * board-flash.c
  * Modified from mach-omap2/board-3430sdp-flash.c
  *
  * Copyright (C) 2009 Nokia Corporation
@@ -16,12 +16,14 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
+#include <plat/irqs.h>
 
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/onenand.h>
 #include <plat/tc.h>
-#include <mach/board-flash.h>
+
+#include "board-flash.h"
 
 #define REG_FPGA_REV                    0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
@@ -72,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
                                         + FLASH_SIZE_SDPV1 - 1;
         }
         if (err < 0) {
-                printk(KERN_ERR "NOR: Can't request GPMC CS\n");
+                pr_err("NOR: Can't request GPMC CS\n");
                 return;
         }
         if (platform_device_register(&board_nor_device) < 0)
-                printk(KERN_ERR "Unable to register NOR device\n");
+                pr_err("Unable to register NOR device\n");
 }
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@@ -138,17 +140,21 @@ static struct omap_nand_platform_data board_nand_data = {
 };
 
 void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
+__init board_nand_init(struct mtd_partition *nand_parts,
+                        u8 nr_parts, u8 cs, int nand_type)
 {
         board_nand_data.cs              = cs;
         board_nand_data.parts           = nand_parts;
-        board_nand_data.nr_parts                = nr_parts;
+        board_nand_data.nr_parts        = nr_parts;
+        board_nand_data.devsize         = nand_type;
 
+        board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+        board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
         gpmc_nand_init(&board_nand_data);
 }
 #else
 void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
 {
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -188,12 +194,12 @@ unmap:
 }
 
 /**
- * sdp3430_flash_init - Identify devices connected to GPMC and register.
+ * board_flash_init - Identify devices connected to GPMC and register.
  *
  * @return - void.
  */
 void board_flash_init(struct flash_partitions partition_info[],
-                                        char chip_sel_board[][GPMC_CS_NUM])
+                        char chip_sel_board[][GPMC_CS_NUM], int nand_type)
 {
         u8              cs = 0;
         u8              norcs = GPMC_CS_NUM + 1;
@@ -207,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
          */
         idx = get_gpmc0_type();
         if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
-                printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
+                pr_err("%s: Invalid chip select: %d\n", __func__, cs);
                 return;
         }
         config_sel = (unsigned char *)(chip_sel_board[idx]);
@@ -231,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
         }
 
         if (norcs > GPMC_CS_NUM)
-                printk(KERN_INFO "NOR: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("NOR: Unable to find configuration in GPMC\n");
         else
                 board_nor_init(partition_info[0].parts,
                                 partition_info[0].nr_parts, norcs);
 
         if (onenandcs > GPMC_CS_NUM)
-                printk(KERN_INFO "OneNAND: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("OneNAND: Unable to find configuration in GPMC\n");
         else
                 board_onenand_init(partition_info[1].parts,
                                         partition_info[1].nr_parts, onenandcs);
 
         if (nandcs > GPMC_CS_NUM)
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("NAND: Unable to find configuration in GPMC\n");
         else
                 board_nand_init(partition_info[2].parts,
-                                partition_info[2].nr_parts, nandcs);
+                        partition_info[2].nr_parts, nandcs, nand_type);
 }
diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index b2242ae2bb6f..c240a3f8d163 100644
--- a/arch/arm/mach-omap2/include/mach/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -25,4 +25,6 @@ struct flash_partitions {
 };
 
 extern void board_flash_init(struct flash_partitions [],
-                                char chip_sel[][GPMC_CS_NUM]);
+                                char chip_sel[][GPMC_CS_NUM], int nand_type);
+extern void board_nand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs, int nand_type);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3482b99e8c86..73e3c31e8508 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,33 +33,44 @@
 static struct omap_board_config_kernel generic_config[] = {
 };
 
-static void __init omap_generic_init_irq(void)
+static void __init omap_generic_init_early(void)
 {
-        omap_board_config = generic_config;
-        omap_board_config_size = ARRAY_SIZE(generic_config);
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 }
 
 static void __init omap_generic_init(void)
 {
         omap_serial_init();
+        omap_board_config = generic_config;
+        omap_board_config_size = ARRAY_SIZE(generic_config);
 }
 
 static void __init omap_generic_map_io(void)
 {
-        omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
-        omap242x_map_common_io();
+        if (cpu_is_omap242x()) {
+                omap2_set_globals_242x();
+                omap242x_map_common_io();
+        } else if (cpu_is_omap243x()) {
+                omap2_set_globals_243x();
+                omap243x_map_common_io();
+        } else if (cpu_is_omap34xx()) {
+                omap2_set_globals_3xxx();
+                omap34xx_map_common_io();
+        } else if (cpu_is_omap44xx()) {
+                omap2_set_globals_443x();
+                omap44xx_map_common_io();
+        }
 }
 
+/* XXX This machine entry name should be updated */
 MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap_generic_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_generic_init_irq,
+        .map_io         = omap_generic_map_io,
+        .init_early     = omap_generic_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e09bd686389f..bac7933b8cbb 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -31,7 +31,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/control.h>
 #include <mach/gpio.h>
 #include <plat/usb.h>
 #include <plat/board.h>
@@ -42,6 +41,7 @@
 #include <plat/gpmc.h>
 
 #include "mux.h"
+#include "control.h"
 
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
@@ -51,38 +51,37 @@
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
 
-static int h4_keymap[] = {
+static const unsigned int h4_keymap[] = {
         KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
-        KEY(0, 2, KEY_A),
-        KEY(0, 3, KEY_B),
-        KEY(0, 4, KEY_C),
-        KEY(1, 0, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(2, 0, KEY_A),
+        KEY(3, 0, KEY_B),
+        KEY(4, 0, KEY_C),
+        KEY(0, 1, KEY_DOWN),
         KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_E),
-        KEY(1, 3, KEY_F),
-        KEY(1, 4, KEY_G),
-        KEY(2, 0, KEY_ENTER),
-        KEY(2, 1, KEY_I),
+        KEY(2, 1, KEY_E),
+        KEY(3, 1, KEY_F),
+        KEY(4, 1, KEY_G),
+        KEY(0, 2, KEY_ENTER),
+        KEY(1, 2, KEY_I),
         KEY(2, 2, KEY_J),
-        KEY(2, 3, KEY_K),
-        KEY(2, 4, KEY_3),
-        KEY(3, 0, KEY_M),
-        KEY(3, 1, KEY_N),
-        KEY(3, 2, KEY_O),
+        KEY(3, 2, KEY_K),
+        KEY(4, 2, KEY_3),
+        KEY(0, 3, KEY_M),
+        KEY(1, 3, KEY_N),
+        KEY(2, 3, KEY_O),
         KEY(3, 3, KEY_P),
-        KEY(3, 4, KEY_Q),
-        KEY(4, 0, KEY_R),
-        KEY(4, 1, KEY_4),
-        KEY(4, 2, KEY_T),
-        KEY(4, 3, KEY_U),
+        KEY(4, 3, KEY_Q),
+        KEY(0, 4, KEY_R),
+        KEY(1, 4, KEY_4),
+        KEY(2, 4, KEY_T),
+        KEY(3, 4, KEY_U),
         KEY(4, 4, KEY_ENTER),
-        KEY(5, 0, KEY_V),
-        KEY(5, 1, KEY_W),
-        KEY(5, 2, KEY_L),
-        KEY(5, 3, KEY_S),
-        KEY(5, 4, KEY_ENTER),
-        0
+        KEY(0, 5, KEY_V),
+        KEY(1, 5, KEY_W),
+        KEY(2, 5, KEY_L),
+        KEY(3, 5, KEY_S),
+        KEY(4, 5, KEY_ENTER),
 };
 
 static struct mtd_partition h4_partitions[] = {
@@ -136,12 +135,16 @@ static struct platform_device h4_flash_device = {
         .resource       = &h4_flash_resource,
 };
 
+static const struct matrix_keymap_data h4_keymap_data = {
+        .keymap         = h4_keymap,
+        .keymap_size    = ARRAY_SIZE(h4_keymap),
+};
+
 static struct omap_kp_platform_data h4_kp_data = {
         .rows           = 6,
         .cols           = 7,
-        .keymap         = h4_keymap,
-        .keymapsize     = ARRAY_SIZE(h4_keymap),
-        .rep            = 1,
+        .keymap_data    = &h4_keymap_data,
+        .rep            = true,
         .row_gpios      = row_gpios,
         .col_gpios      = col_gpios,
 };
@@ -283,18 +286,19 @@ static struct omap_usb_config h4_usb_config __initdata = {
         .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
 };
 
-static struct omap_board_config_kernel h4_config[] = {
+static struct omap_board_config_kernel h4_config[] __initdata = {
         { OMAP_TAG_LCD,         &h4_lcd_config },
 };
 
+static void __init omap_h4_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
 static void __init omap_h4_init_irq(void)
 {
-        omap_board_config = h4_config;
-        omap_board_config_size = ARRAY_SIZE(h4_config);
-        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
-        h4_init_flash();
 }
 
 static struct at24_platform_data m24c01 = {
@@ -321,14 +325,15 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap_h4_init(void)
 {
         omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
 
+        omap_board_config = h4_config;
+        omap_board_config_size = ARRAY_SIZE(h4_config);
+
         /*
          * Make sure the serial ports are muxed on at this point.
          * You have to mux them off in device drivers later on
@@ -366,6 +371,7 @@ static void __init omap_h4_init(void)
         platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
         omap2_usbfs_init(&h4_usb_config);
         omap_serial_init();
+        h4_init_flash();
 }
 
 static void __init omap_h4_map_io(void)
@@ -376,11 +382,10 @@ static void __init omap_h4_map_io(void)
 
 MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap_h4_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap_h4_map_io,
+        .init_early     = omap_h4_init_early,
         .init_irq       = omap_h4_init_irq,
         .init_machine   = omap_h4_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 175f04339761..0c1bfca3f731 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -17,9 +17,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
+#include <linux/input.h>
 
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 #include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -28,22 +31,84 @@
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/onenand.h>
 
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
+#include "common-board-devices.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
 #define IGEP2_GPIO_USBH_NRESET  24
-#define IGEP2_GPIO_LED0_GREEN   26
-#define IGEP2_GPIO_LED0_RED     27
-#define IGEP2_GPIO_LED1_RED     28
-#define IGEP2_GPIO_DVI_PUP      170
-#define IGEP2_GPIO_WIFI_NPD     94
-#define IGEP2_GPIO_WIFI_NRESET  95
+#define IGEP2_GPIO_LED0_GREEN   26
+#define IGEP2_GPIO_LED0_RED     27
+#define IGEP2_GPIO_LED1_RED     28
+#define IGEP2_GPIO_DVI_PUP      170
+
+#define IGEP2_RB_GPIO_WIFI_NPD     94
+#define IGEP2_RB_GPIO_WIFI_NRESET  95
+#define IGEP2_RB_GPIO_BT_NRESET    137
+#define IGEP2_RC_GPIO_WIFI_NPD     138
+#define IGEP2_RC_GPIO_WIFI_NRESET  139
+#define IGEP2_RC_GPIO_BT_NRESET    137
+
+#define IGEP3_GPIO_LED0_GREEN   54
+#define IGEP3_GPIO_LED0_RED     53
+#define IGEP3_GPIO_LED1_RED     16
+#define IGEP3_GPIO_USBH_NRESET  183
+
+/*
+ * IGEP2 Hardware Revision Table
+ *
+ *  --------------------------------------------------------------------------
+ * | Id. | Hw Rev.            | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET |
+ *  --------------------------------------------------------------------------
+ * |  0  | B                  |   high   |  gpio94  |   gpio95    |     -     |
+ * |  0  | B/C (B-compatible) |   high   |  gpio94  |   gpio95    |  gpio137  |
+ * |  1  | C                  |   low    |  gpio138 |   gpio139   |  gpio137  |
+ *  --------------------------------------------------------------------------
+ */
+
+#define IGEP2_BOARD_HWREV_B     0
+#define IGEP2_BOARD_HWREV_C     1
+#define IGEP3_BOARD_HWREV       2
+
+static u8 hwrev;
+
+static void __init igep2_get_revision(void)
+{
+        u8 ret;
+
+        if (machine_is_igep0030()) {
+                hwrev = IGEP3_BOARD_HWREV;
+                return;
+        }
+
+        omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT);
+
+        if (gpio_request_one(IGEP2_GPIO_LED1_RED, GPIOF_IN, "GPIO_HW0_REV")) {
+                pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n");
+                pr_err("IGEP2: Unknown Hardware Revision\n");
+                return;
+        }
+
+        ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
+        if (ret == 0) {
+                pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
+                hwrev = IGEP2_BOARD_HWREV_C;
+        } else if (ret ==  1) {
+                pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
+                hwrev = IGEP2_BOARD_HWREV_B;
+        } else {
+                pr_err("IGEP2: Unknown Hardware Revision\n");
+                hwrev = -1;
+        }
+
+        gpio_free(IGEP2_GPIO_LED1_RED);
+}
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
         defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
@@ -58,7 +123,7 @@
  * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
  */
 
-static struct mtd_partition igep2_onenand_partitions[] = {
+static struct mtd_partition igep_onenand_partitions[] = {
         {
                 .name           = "X-Loader",
                 .offset         = 0,
@@ -86,137 +151,82 @@ static struct mtd_partition igep2_onenand_partitions[] = {
         },
 };
 
-static int igep2_onenand_setup(void __iomem *onenand_base, int freq)
-{
-       /* nothing is required to be setup for onenand as of now */
-       return 0;
-}
-
-static struct omap_onenand_platform_data igep2_onenand_data = {
-        .parts = igep2_onenand_partitions,
-        .nr_parts = ARRAY_SIZE(igep2_onenand_partitions),
-        .onenand_setup = igep2_onenand_setup,
+static struct omap_onenand_platform_data igep_onenand_data = {
+        .parts = igep_onenand_partitions,
+        .nr_parts = ARRAY_SIZE(igep_onenand_partitions),
         .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
 };
 
-static struct platform_device igep2_onenand_device = {
+static struct platform_device igep_onenand_device = {
         .name           = "omap2-onenand",
         .id             = -1,
         .dev = {
-                .platform_data = &igep2_onenand_data,
+                .platform_data = &igep_onenand_data,
         },
 };
 
-void __init igep2_flash_init(void)
+static void __init igep_flash_init(void)
 {
-        u8              cs = 0;
-        u8              onenandcs = GPMC_CS_NUM + 1;
+        u8 cs = 0;
+        u8 onenandcs = GPMC_CS_NUM + 1;
 
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                u32 ret;
                 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 
                 /* Check if NAND/oneNAND is configured */
                 if ((ret & 0xC00) == 0x800)
                         /* NAND found */
-                        pr_err("IGEP v2: Unsupported NAND found\n");
+                        pr_err("IGEP: Unsupported NAND found\n");
                 else {
                         ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
                         if ((ret & 0x3F) == (ONENAND_MAP >> 24))
                                 /* ONENAND found */
                                 onenandcs = cs;
                 }
-                cs++;
         }
+
         if (onenandcs > GPMC_CS_NUM) {
-                pr_err("IGEP v2: Unable to find configuration in GPMC\n");
+                pr_err("IGEP: Unable to find configuration in GPMC\n");
                 return;
         }
 
-        if (onenandcs < GPMC_CS_NUM) {
-                igep2_onenand_data.cs = onenandcs;
-                if (platform_device_register(&igep2_onenand_device) < 0)
-                        pr_err("IGEP v2: Unable to register OneNAND device\n");
-        }
+        igep_onenand_data.cs = onenandcs;
+
+        if (platform_device_register(&igep_onenand_device) < 0)
+                pr_err("IGEP: Unable to register OneNAND device\n");
 }
 
 #else
-void __init igep2_flash_init(void) {}
+static void __init igep_flash_init(void) {}
 #endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
+#include <plat/gpmc-smsc911x.h>
 
-static struct smsc911x_platform_config igep2_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS  ,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource igep2_smsc911x_resources[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP_GPIO_IRQ(IGEP2_SMSC911X_GPIO),
-                .end    = OMAP_GPIO_IRQ(IGEP2_SMSC911X_GPIO),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct platform_device igep2_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(igep2_smsc911x_resources),
-        .resource       = igep2_smsc911x_resources,
-        .dev            = {
-                .platform_data = &igep2_smsc911x_config,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = IGEP2_SMSC911X_CS,
+        .gpio_irq       = IGEP2_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
 static inline void __init igep2_init_smsc911x(void)
 {
-        unsigned long cs_mem_base;
-
-        if (gpmc_cs_request(IGEP2_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
-                pr_err("IGEP v2: Failed request for GPMC mem for smsc911x\n");
-                gpmc_cs_free(IGEP2_SMSC911X_CS);
-                return;
-        }
-
-        igep2_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        igep2_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-
-        if ((gpio_request(IGEP2_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
-            (gpio_direction_input(IGEP2_SMSC911X_GPIO) == 0)) {
-                gpio_export(IGEP2_SMSC911X_GPIO, 0);
-        } else {
-                pr_err("IGEP v2: Could not obtain gpio for for SMSC911X IRQ\n");
-                return;
-        }
-
-        platform_device_register(&igep2_smsc911x_device);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 #else
 static inline void __init igep2_init_smsc911x(void) { }
 #endif
 
-static struct omap_board_config_kernel igep2_config[] __initdata = {
-};
-
-static struct regulator_consumer_supply igep2_vmmc1_supply = {
-        .supply         = "vmmc",
-};
-
-static struct regulator_consumer_supply igep2_vmmc2_supply = {
-        .supply         = "vmmc",
-};
+static struct regulator_consumer_supply igep_vmmc1_supply =
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
-static struct regulator_init_data igep2_vmmc1 = {
+static struct regulator_init_data igep_vmmc1 = {
         .constraints = {
                 .min_uV                 = 1850000,
                 .max_uV                 = 3150000,
@@ -227,14 +237,17 @@ static struct regulator_init_data igep2_vmmc1 = {
                                         | REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vmmc1_supply,
+        .consumer_supplies      = &igep_vmmc1_supply,
 };
 
-/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */
-static struct regulator_init_data igep2_vmmc2 = {
+static struct regulator_consumer_supply igep_vio_supply =
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+
+static struct regulator_init_data igep_vio = {
         .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = 1,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
@@ -242,50 +255,192 @@ static struct regulator_init_data igep2_vmmc2 = {
                                         | REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vmmc2_supply,
+        .consumer_supplies      = &igep_vio_supply,
+};
+
+static struct regulator_consumer_supply igep_vmmc2_supply =
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+static struct regulator_init_data igep_vmmc2 = {
+        .constraints            = {
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .always_on              = 1,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &igep_vmmc2_supply,
+};
+
+static struct fixed_voltage_config igep_vwlan = {
+        .supply_name            = "vwlan",
+        .microvolts             = 3300000,
+        .gpio                   = -EINVAL,
+        .enabled_at_boot        = 1,
+        .init_data              = &igep_vmmc2,
+};
+
+static struct platform_device igep_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &igep_vwlan,
+        },
 };
 
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
+#endif
         {}      /* Terminator */
 };
 
-static int igep2_twl_gpio_setup(struct device *dev,
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led igep_gpio_leds[] = {
+        [0] = {
+                .name                   = "gpio-led:red:d0",
+                .default_trigger        = "default-off"
+        },
+        [1] = {
+                .name                   = "gpio-led:green:d0",
+                .default_trigger        = "default-off",
+        },
+        [2] = {
+                .name                   = "gpio-led:red:d1",
+                .default_trigger        = "default-off",
+        },
+        [3] = {
+                .name                   = "gpio-led:green:d1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = -EINVAL, /* gets replaced */
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data igep_led_pdata = {
+        .leds           = igep_gpio_leds,
+        .num_leds       = ARRAY_SIZE(igep_gpio_leds),
+};
+
+static struct platform_device igep_led_device = {
+         .name   = "leds-gpio",
+         .id     = -1,
+         .dev    = {
+                 .platform_data  =  &igep_led_pdata,
+        },
+};
+
+static void __init igep_leds_init(void)
+{
+        if (machine_is_igep0020()) {
+                igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
+        } else {
+                igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
+        }
+
+        platform_device_register(&igep_led_device);
+}
+
+#else
+static struct gpio igep_gpio_leds[] __initdata = {
+        { -EINVAL,      GPIOF_OUT_INIT_LOW, "gpio-led:red:d0"   },
+        { -EINVAL,      GPIOF_OUT_INIT_LOW, "gpio-led:green:d0" },
+        { -EINVAL,      GPIOF_OUT_INIT_LOW, "gpio-led:red:d1"   },
+};
+
+static inline void igep_leds_init(void)
+{
+        int i;
+
+        if (machine_is_igep0020()) {
+                igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
+        } else {
+                igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
+        }
+
+        if (gpio_request_array(igep_gpio_leds, ARRAY_SIZE(igep_gpio_leds))) {
+                pr_warning("IGEP v2: Could not obtain leds gpios\n");
+                return;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(igep_gpio_leds); i++)
+                gpio_export(igep_gpio_leds[i].gpio, 0);
+}
+#endif
+
+static struct gpio igep2_twl_gpios[] = {
+        { -EINVAL, GPIOF_IN,            "GPIO_EHCI_NOC"  },
+        { -EINVAL, GPIOF_OUT_INIT_LOW,  "GPIO_USBH_CPEN" },
+};
+
+static int igep_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int ret;
+
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
-         * regulators will be set up only *after* we return.
-        */
-        igep2_vmmc1_supply.dev = mmc[0].dev;
-        igep2_vmmc2_supply.dev = mmc[1].dev;
+        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
+#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
+        ret = gpio_request_one(gpio + TWL4030_GPIO_MAX + 1, GPIOF_OUT_INIT_HIGH,
+                               "gpio-led:green:d1");
+        if (ret == 0)
+                gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
+        else
+                pr_warning("IGEP: Could not obtain gpio GPIO_LED1_GREEN\n");
+#else
+        igep_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
+#endif
+
+        if (machine_is_igep0030())
+                return 0;
+
+        /*
+         * REVISIT: need ehci-omap hooks for external VBUS
+         * power switch and overcurrent detect
+         */
+        igep2_twl_gpios[0].gpio = gpio + 1;
+
+        /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */
+        igep2_twl_gpios[1].gpio = gpio + TWL4030_GPIO_MAX;
+
+        ret = gpio_request_array(igep2_twl_gpios, ARRAY_SIZE(igep2_twl_gpios));
+        if (ret < 0)
+                pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
 
         return 0;
 };
 
-static struct twl4030_gpio_platform_data igep2_gpio_data = {
+static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
-        .use_leds       = false,
-        .setup          = igep2_twl_gpio_setup,
+        .use_leds       = true,
+        .setup          = igep_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data igep2_usb_data = {
+static struct twl4030_usb_data igep_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
@@ -301,13 +456,18 @@ static void igep2_disable_dvi(struct omap_dss_device *dssdev)
         gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0);
 }
 
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = igep2_enable_dvi,
+        .platform_disable       = igep2_disable_dvi,
+};
+
 static struct omap_dss_device igep2_dvi_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = igep2_enable_dvi,
-        .platform_disable       = igep2_disable_dvi,
 };
 
 static struct omap_dss_device *igep2_dss_devices[] = {
@@ -320,17 +480,9 @@ static struct omap_dss_board_info igep2_dss_data = {
         .default_device = &igep2_dvi_device,
 };
 
-static struct platform_device igep2_dss_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &igep2_dss_data,
-        },
-};
-
-static struct regulator_consumer_supply igep2_vpll2_supply = {
-        .supply = "vdds_dsi",
-        .dev    = &igep2_dss_device.dev,
+static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 
 static struct regulator_init_data igep2_vpll2 = {
@@ -344,123 +496,110 @@ static struct regulator_init_data igep2_vpll2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vpll2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(igep2_vpll2_supplies),
+        .consumer_supplies      = igep2_vpll2_supplies,
 };
 
 static void __init igep2_display_init(void)
 {
-        if (gpio_request(IGEP2_GPIO_DVI_PUP, "GPIO_DVI_PUP") &&
-            gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1))
+        int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
+                                   "GPIO_DVI_PUP");
+        if (err)
                 pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
 }
 
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-#include <linux/leds.h>
-
-static struct gpio_led igep2_gpio_leds[] = {
-        {
-                .name = "led0:red",
-                .gpio = IGEP2_GPIO_LED0_RED,
-        },
-        {
-                .name = "led0:green",
-                .default_trigger = "heartbeat",
-                .gpio = IGEP2_GPIO_LED0_GREEN,
-        },
-        {
-                .name = "led1:red",
-                .gpio = IGEP2_GPIO_LED1_RED,
-        },
-};
-
-static struct gpio_led_platform_data igep2_led_pdata = {
-        .leds           = igep2_gpio_leds,
-        .num_leds       = ARRAY_SIZE(igep2_gpio_leds),
-};
-
-static struct platform_device igep2_led_device = {
-         .name   = "leds-gpio",
-         .id     = -1,
-         .dev    = {
-                 .platform_data  =  &igep2_led_pdata,
-        },
+static struct platform_device *igep_devices[] __initdata = {
+        &igep_vwlan_device,
 };
 
-static void __init igep2_init_led(void)
+static void __init igep_init_early(void)
 {
-        platform_device_register(&igep2_led_device);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(m65kxxxxam_sdrc_params,
+                                  m65kxxxxam_sdrc_params);
 }
 
-#else
-static inline void igep2_init_led(void) {}
-#endif
+static struct twl4030_codec_audio_data igep2_audio_data;
 
-static struct platform_device *igep2_devices[] __initdata = {
-        &igep2_dss_device,
+static struct twl4030_codec_data igep2_codec_data = {
+        .audio_mclk = 26000000,
+        .audio = &igep2_audio_data,
 };
 
-static void __init igep2_init_irq(void)
-{
-        omap_board_config = igep2_config;
-        omap_board_config_size = ARRAY_SIZE(igep2_config);
-        omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
+static int igep2_keymap[] = {
+        KEY(0, 0, KEY_LEFT),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_A),
+        KEY(0, 3, KEY_B),
+        KEY(1, 0, KEY_DOWN),
+        KEY(1, 1, KEY_UP),
+        KEY(1, 2, KEY_E),
+        KEY(1, 3, KEY_F),
+        KEY(2, 0, KEY_ENTER),
+        KEY(2, 1, KEY_I),
+        KEY(2, 2, KEY_J),
+        KEY(2, 3, KEY_K),
+        KEY(3, 0, KEY_M),
+        KEY(3, 1, KEY_N),
+        KEY(3, 2, KEY_O),
+        KEY(3, 3, KEY_P)
+};
 
-static struct twl4030_codec_audio_data igep2_audio_data = {
-        .audio_mclk = 26000000,
+static struct matrix_keymap_data igep2_keymap_data = {
+        .keymap                 = igep2_keymap,
+        .keymap_size            = ARRAY_SIZE(igep2_keymap),
 };
 
-static struct twl4030_codec_data igep2_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &igep2_audio_data,
+static struct twl4030_keypad_data igep2_keypad_pdata = {
+        .keymap_data    = &igep2_keymap_data,
+        .rows           = 4,
+        .cols           = 4,
+        .rep            = 1,
 };
 
-static struct twl4030_platform_data igep2_twldata = {
+static struct twl4030_platform_data igep_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
 
         /* platform_data for children goes here */
-        .usb            = &igep2_usb_data,
-        .codec          = &igep2_codec_data,
-        .gpio           = &igep2_gpio_data,
-        .vmmc1          = &igep2_vmmc1,
-        .vmmc2          = &igep2_vmmc2,
-        .vpll2          = &igep2_vpll2,
-
+        .usb            = &igep_usb_data,
+        .gpio           = &igep_twl4030_gpio_pdata,
+        .vmmc1          = &igep_vmmc1,
+        .vio            = &igep_vio,
 };
 
-static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = {
+static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
         {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &igep2_twldata,
+                I2C_BOARD_INFO("eeprom", 0x50),
         },
 };
 
-static int __init igep2_i2c_init(void)
+static void __init igep_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, igep2_i2c_boardinfo,
-                        ARRAY_SIZE(igep2_i2c_boardinfo));
-        /* Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 100, NULL, 0);
-        return 0;
-}
+        int ret;
+
+        if (machine_is_igep0020()) {
+                /*
+                 * Bus 3 is attached to the DVI port where devices like the
+                 * pico DLP projector don't work reliably with 400kHz
+                 */
+                ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
+                                            ARRAY_SIZE(igep2_i2c3_boardinfo));
+                if (ret)
+                        pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
+
+                igep_twldata.codec      = &igep2_codec_data;
+                igep_twldata.keypad     = &igep2_keypad_pdata;
+                igep_twldata.vpll2      = &igep2_vpll2;
+        }
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
+        omap3_pmic_init("twl4030", &igep_twldata);
+}
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+static const struct usbhs_omap_board_data igep2_usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset = true,
         .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
@@ -468,77 +607,113 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2] = -EINVAL,
 };
 
+static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+
+        .phy_reset = true,
+        .reset_gpio_port[0] = -EINVAL,
+        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
+        .reset_gpio_port[2] = -EINVAL,
+};
+
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
-static void __init igep2_init(void)
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+static struct gpio igep_wlan_bt_gpios[] __initdata = {
+        { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NPD"    },
+        { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NRESET" },
+        { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_BT_NRESET"   },
+};
+
+static void __init igep_wlan_bt_init(void)
 {
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        igep2_i2c_init();
-        platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
-        omap_serial_init();
-        usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
+        int err;
+
+        /* GPIO's for WLAN-BT combo depends on hardware revision */
+        if (hwrev == IGEP2_BOARD_HWREV_B) {
+                igep_wlan_bt_gpios[0].gpio = IGEP2_RB_GPIO_WIFI_NPD;
+                igep_wlan_bt_gpios[1].gpio = IGEP2_RB_GPIO_WIFI_NRESET;
+                igep_wlan_bt_gpios[2].gpio = IGEP2_RB_GPIO_BT_NRESET;
+        } else if (hwrev == IGEP2_BOARD_HWREV_C || machine_is_igep0030()) {
+                igep_wlan_bt_gpios[0].gpio = IGEP2_RC_GPIO_WIFI_NPD;
+                igep_wlan_bt_gpios[1].gpio = IGEP2_RC_GPIO_WIFI_NRESET;
+                igep_wlan_bt_gpios[2].gpio = IGEP2_RC_GPIO_BT_NRESET;
+        } else
+                return;
 
-        igep2_flash_init();
-        igep2_init_led();
-        igep2_display_init();
-        igep2_init_smsc911x();
+        err = gpio_request_array(igep_wlan_bt_gpios,
+                                 ARRAY_SIZE(igep_wlan_bt_gpios));
+        if (err) {
+                pr_warning("IGEP2: Could not obtain WIFI/BT gpios\n");
+                return;
+        }
 
-        /* GPIO userspace leds */
-#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
-        if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED0_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
+        gpio_export(igep_wlan_bt_gpios[0].gpio, 0);
+        gpio_export(igep_wlan_bt_gpios[1].gpio, 0);
+        gpio_export(igep_wlan_bt_gpios[2].gpio, 0);
 
-        if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
+        gpio_set_value(igep_wlan_bt_gpios[1].gpio, 0);
+        udelay(10);
+        gpio_set_value(igep_wlan_bt_gpios[1].gpio, 1);
 
-        if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED1_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
+}
+#else
+static inline void __init igep_wlan_bt_init(void) { }
 #endif
 
-        /* GPIO W-LAN + Bluetooth combo module */
-        if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_WIFI_NPD, 0);
-/*              gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n");
-
-        if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_WIFI_NRESET, 0);
-                gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0);
-                udelay(10);
-                gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n");
+static void __init igep_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        /* Get IGEP2 hardware revision */
+        igep2_get_revision();
+        /* Register I2C busses and drivers */
+        igep_i2c_init();
+        platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
+        omap_serial_init();
+        usb_musb_init(NULL);
+
+        igep_flash_init();
+        igep_leds_init();
+
+        /*
+         * WLAN-BT combo module from MuRata which has a Marvell WLAN
+         * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
+         */
+        igep_wlan_bt_init();
+
+        if (machine_is_igep0020()) {
+                omap_display_init(&igep2_dss_data);
+                igep2_display_init();
+                igep2_init_smsc911x();
+                usbhs_init(&igep2_usbhs_bdata);
+        } else {
+                usbhs_init(&igep3_usbhs_bdata);
+        }
 }
 
 MACHINE_START(IGEP0020, "IGEP v2 board")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
+        .init_early     = igep_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = igep_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+        .boot_params    = 0x80000100,
         .reserve        = omap_reserve,
-        .init_irq       = igep2_init_irq,
-        .init_machine   = igep2_init,
+        .map_io         = omap3_map_io,
+        .init_early     = igep_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = igep_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 00d9b13b01c5..f7d6038075f0 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -22,11 +22,11 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,48 +41,21 @@
 #include <mach/board-zoom.h>
 
 #include <asm/delay.h>
-#include <plat/control.h>
 #include <plat/usb.h>
+#include <plat/gpmc-smsc911x.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "control.h"
+#include "common-board-devices.h"
 
 #define LDP_SMSC911X_CS         1
 #define LDP_SMSC911X_GPIO       152
 #define DEBUG_BASE              0x08000000
 #define LDP_ETHR_START          DEBUG_BASE
 
-static struct resource ldp_smsc911x_resources[] = {
-        [0] = {
-                .start  = LDP_ETHR_START,
-                .end    = LDP_ETHR_START + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct smsc911x_platform_config ldp_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device ldp_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(ldp_smsc911x_resources),
-        .resource       = ldp_smsc911x_resources,
-        .dev            = {
-                .platform_data = &ldp_smsc911x_config,
-        },
-};
-
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
         KEY(2, 0, KEY_3),
@@ -195,82 +168,16 @@ static struct platform_device ldp_gpio_keys_device = {
         },
 };
 
-static int ts_gpio;
-
-/**
- * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
- *
- * @return - void. If request gpio fails then Flag KERN_ERR.
- */
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(ts_gpio, "ads7846 irq") < 0) {
-                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
-                return;
-        }
-
-        gpio_direction_input(ts_gpio);
-        gpio_set_debounce(ts_gpio, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(ts_gpio);
-}
-
-static struct ads7846_platform_data tsc2046_config __initdata = {
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info ldp_spi_board_info[] __initdata = {
-        [0] = {
-                /*
-                 * TSC2046 operates at a max freqency of 2MHz, so
-                 * operate slightly below at 1.5MHz
-                 */
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &tsc2046_mcspi_config,
-                .irq                    = 0,
-                .platform_data          = &tsc2046_config,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = LDP_SMSC911X_CS,
+        .gpio_irq       = LDP_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT,
 };
 
 static inline void __init ldp_init_smsc911x(void)
 {
-        int eth_cs;
-        unsigned long cs_mem_base;
-        int eth_gpio = 0;
-
-        eth_cs = LDP_SMSC911X_CS;
-
-        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
-                return;
-        }
-
-        ldp_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        ldp_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-        udelay(100);
-
-        eth_gpio = LDP_SMSC911X_GPIO;
-
-        ldp_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
-
-        if (gpio_request(eth_gpio, "smsc911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                                eth_gpio);
-                return;
-        }
-        gpio_direction_input(eth_gpio);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 static struct platform_device ldp_lcd_device = {
@@ -286,14 +193,10 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
         { OMAP_TAG_LCD,         &ldp_lcd_config },
 };
 
-static void __init omap_ldp_init_irq(void)
+static void __init omap_ldp_init_early(void)
 {
-        omap_board_config = ldp_config;
-        omap_board_config_size = ARRAY_SIZE(ldp_config);
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
-        ldp_init_smsc911x();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 }
 
 static struct twl4030_usb_data ldp_usb_data = {
@@ -329,6 +232,26 @@ static struct regulator_init_data ldp_vmmc1 = {
         .consumer_supplies      = &ldp_vmmc1_supply,
 };
 
+/* ads7846 on SPI */
+static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
+
+/* VAUX1 */
+static struct regulator_init_data ldp_vaux1 = {
+        .constraints = {
+                .min_uV                 = 3000000,
+                .max_uV                 = 3000000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(ldp_vaux1_supplies),
+        .consumer_supplies              = ldp_vaux1_supplies,
+};
+
 static struct twl4030_platform_data ldp_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -337,23 +260,14 @@ static struct twl4030_platform_data ldp_twldata = {
         .madc           = &ldp_madc_data,
         .usb            = &ldp_usb_data,
         .vmmc1          = &ldp_vmmc1,
+        .vaux1          = &ldp_vaux1,
         .gpio           = &ldp_gpio_data,
         .keypad         = &ldp_kp_twl4030_data,
 };
 
-static struct i2c_board_info __initdata ldp_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &ldp_twldata,
-        },
-};
-
 static int __init omap_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, ldp_i2c_boardinfo,
-                        ARRAY_SIZE(ldp_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &ldp_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
@@ -362,7 +276,7 @@ static int __init omap_i2c_init(void)
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
@@ -370,7 +284,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
 };
 
 static struct platform_device *ldp_devices[] __initdata = {
-        &ldp_smsc911x_device,
         &ldp_lcd_device,
         &ldp_gpio_keys_device,
 };
@@ -379,16 +292,8 @@ static struct platform_device *ldp_devices[] __initdata = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static struct mtd_partition ldp_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
         {
@@ -424,17 +329,16 @@ static struct mtd_partition ldp_nand_partitions[] = {
 static void __init omap_ldp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = ldp_config;
+        omap_board_config_size = ARRAY_SIZE(ldp_config);
+        ldp_init_smsc911x();
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
-        ts_gpio = 54;
-        ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
-        spi_register_board_info(ldp_spi_board_info,
-                                ARRAY_SIZE(ldp_spi_board_info));
-        ads7846_dev_init();
+        omap_ads7846_init(1, 54, 310, NULL);
         omap_serial_init();
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         board_nand_init(ldp_nand_partitions,
-                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS);
+                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
         omap2_hsmmc_init(mmc);
         /* link regulators to MMC adapters */
@@ -442,12 +346,11 @@ static void __init omap_ldp_init(void)
 }
 
 MACHINE_START(OMAP_LDP, "OMAP LDP board")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_ldp_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_ldp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_ldp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index a3e2b49aa39f..8d74318ed495 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,6 +20,7 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -45,8 +46,7 @@ static struct device *mmc_device;
 #define TUSB6010_GPIO_ENABLE    0
 #define TUSB6010_DMACHAN        0x3f
 
-#if defined(CONFIG_USB_TUSB6010) || \
-        defined(CONFIG_USB_TUSB6010_MODULE)
+#ifdef CONFIG_USB_MUSB_TUSB6010
 /*
  * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
  * 1.5 V voltage regulators of PM companion chip. Companion chip will then
@@ -106,14 +106,13 @@ static void __init n8x0_usb_init(void)
         static char     announce[] __initdata = KERN_INFO "TUSB 6010\n";
 
         /* PM companion chip power control pin */
-        ret = gpio_request(TUSB6010_GPIO_ENABLE, "TUSB6010 enable");
+        ret = gpio_request_one(TUSB6010_GPIO_ENABLE, GPIOF_OUT_INIT_LOW,
+                               "TUSB6010 enable");
         if (ret != 0) {
                 printk(KERN_ERR "Could not get TUSB power GPIO%i\n",
                        TUSB6010_GPIO_ENABLE);
                 return;
         }
-        gpio_direction_output(TUSB6010_GPIO_ENABLE, 0);
-
         tusb_set_power(0);
 
         ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
@@ -133,7 +132,7 @@ err:
 
 static void __init n8x0_usb_init(void) {}
 
-#endif /*CONFIG_USB_TUSB6010 */
+#endif /*CONFIG_USB_MUSB_TUSB6010 */
 
 
 static struct omap2_mcspi_device_config p54spi_mcspi_config = {
@@ -183,23 +182,15 @@ static struct mtd_partition onenand_partitions[] = {
         },
 };
 
-static struct omap_onenand_platform_data board_onenand_data = {
-        .cs             = 0,
-        .gpio_irq       = 26,
-        .parts          = onenand_partitions,
-        .nr_parts       = ARRAY_SIZE(onenand_partitions),
-        .flags          = ONENAND_SYNC_READ,
+static struct omap_onenand_platform_data board_onenand_data[] = {
+        {
+                .cs             = 0,
+                .gpio_irq       = 26,
+                .parts          = onenand_partitions,
+                .nr_parts       = ARRAY_SIZE(onenand_partitions),
+                .flags          = ONENAND_SYNC_READ,
+        }
 };
-
-static void __init n8x0_onenand_init(void)
-{
-        gpmc_onenand_init(&board_onenand_data);
-}
-
-#else
-
-static void __init n8x0_onenand_init(void) {}
-
 #endif
 
 #if defined(CONFIG_MENELAUS) &&                                         \
@@ -383,15 +374,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
         omap_mmc_notify_cover_event(mmc_device, index, *openp);
 }
 
-void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state)
-{
-        if (mmc_device == NULL)
-                return;
-
-        slot1_cover_open = !closed_state;
-        omap_mmc_notify_cover_event(mmc_device, 0, closed_state);
-}
-
 static int n8x0_mmc_late_init(struct device *dev)
 {
         int r, bit, *openp;
@@ -511,8 +493,12 @@ static struct omap_mmc_platform_data mmc1_data = {
 
 static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
 
-void __init n8x0_mmc_init(void)
+static struct gpio n810_emmc_gpios[] __initdata = {
+        { N810_EMMC_VSD_GPIO, GPIOF_OUT_INIT_LOW,  "MMC slot 2 Vddf" },
+        { N810_EMMC_VIO_GPIO, GPIOF_OUT_INIT_LOW,  "MMC slot 2 Vdd"  },
+};
 
+static void __init n8x0_mmc_init(void)
 {
         int err;
 
@@ -529,42 +515,28 @@ void __init n8x0_mmc_init(void)
                 mmc1_data.slots[1].ban_openended = 1;
         }
 
-        err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch");
+        err = gpio_request_one(N8X0_SLOT_SWITCH_GPIO, GPIOF_OUT_INIT_LOW,
+                               "MMC slot switch");
         if (err)
                 return;
 
-        gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0);
-
         if (machine_is_nokia_n810()) {
-                err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf");
+                err = gpio_request_array(n810_emmc_gpios,
+                                         ARRAY_SIZE(n810_emmc_gpios));
                 if (err) {
                         gpio_free(N8X0_SLOT_SWITCH_GPIO);
                         return;
                 }
-                gpio_direction_output(N810_EMMC_VSD_GPIO, 0);
-
-                err = gpio_request(N810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
-                if (err) {
-                        gpio_free(N8X0_SLOT_SWITCH_GPIO);
-                        gpio_free(N810_EMMC_VSD_GPIO);
-                        return;
-                }
-                gpio_direction_output(N810_EMMC_VIO_GPIO, 0);
         }
 
         mmc_data[0] = &mmc1_data;
-        omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC);
+        omap242x_init_mmc(mmc_data);
 }
 #else
 
 void __init n8x0_mmc_init(void)
 {
 }
-
-void n8x0_mmc_slot1_cover_handler(void *arg, int state)
-{
-}
-
 #endif  /* CONFIG_MMC_OMAP */
 
 #ifdef CONFIG_MENELAUS
@@ -614,29 +586,35 @@ static int n8x0_menelaus_late_init(struct device *dev)
         return 0;
 }
 
-static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = {
+#else
+static int n8x0_menelaus_late_init(struct device *dev)
+{
+        return 0;
+}
+#endif
+
+static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
+        .late_init = n8x0_menelaus_late_init,
+};
+
+static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
         {
                 I2C_BOARD_INFO("menelaus", 0x72),
                 .irq = INT_24XX_SYS_NIRQ,
+                .platform_data = &n8x0_menelaus_platform_data,
         },
 };
 
-static struct menelaus_platform_data n8x0_menelaus_platform_data = {
-        .late_init = n8x0_menelaus_late_init,
+static struct aic3x_pdata n810_aic33_data __initdata = {
+        .gpio_reset = 118,
 };
 
-static void __init n8x0_menelaus_init(void)
-{
-        n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data;
-        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
-                              ARRAY_SIZE(n8x0_i2c_board_info_1));
-}
-
-#else
-static inline void __init n8x0_menelaus_init(void)
-{
-}
-#endif
+static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x18),
+                .platform_data = &n810_aic33_data,
+        },
+};
 
 static void __init n8x0_map_io(void)
 {
@@ -644,19 +622,58 @@ static void __init n8x0_map_io(void)
         omap242x_map_common_io();
 }
 
-static void __init n8x0_init_irq(void)
+static void __init n8x0_init_early(void)
 {
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 }
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* I2S codec port pins for McBSP block */
+        OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+        {
+                .name   = "uart3_rx_irrx.uart3_rx_irrx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_MUX_MODE0,
+                .idle   = OMAP_MUX_MODE3        /* Mux as GPIO for idle */
+        },
+};
+
+static inline void board_serial_init(void)
+{
+        struct omap_board_data bdata;
+
+        bdata.flags = 0;
+        bdata.pads = NULL;
+        bdata.pads_cnt = 0;
+
+        bdata.id = 0;
+        omap_serial_init_port(&bdata);
+
+        bdata.id = 1;
+        omap_serial_init_port(&bdata);
+
+        bdata.id = 2;
+        bdata.pads = serial2_pads;
+        bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
+        omap_serial_init_port(&bdata);
+}
+
 #else
-#define board_mux       NULL
+
+static inline void board_serial_init(void)
+{
+        omap_serial_init();
+}
+
 #endif
 
 static void __init n8x0_init_machine(void)
@@ -665,43 +682,44 @@ static void __init n8x0_init_machine(void)
         /* FIXME: add n810 spi devices */
         spi_register_board_info(n800_spi_board_info,
                                 ARRAY_SIZE(n800_spi_board_info));
-
-        omap_serial_init();
-        n8x0_menelaus_init();
-        n8x0_onenand_init();
+        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
+                              ARRAY_SIZE(n8x0_i2c_board_info_1));
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        if (machine_is_nokia_n810())
+                i2c_register_board_info(2, n810_i2c_board_info_2,
+                                        ARRAY_SIZE(n810_i2c_board_info_2));
+        board_serial_init();
+        gpmc_onenand_init(board_onenand_data);
         n8x0_mmc_init();
         n8x0_usb_init();
 }
 
 MACHINE_START(NOKIA_N800, "Nokia N800")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = n8x0_init_irq,
+        .map_io         = n8x0_map_io,
+        .init_early     = n8x0_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810, "Nokia N810")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = n8x0_init_irq,
+        .map_io         = n8x0_map_io,
+        .init_early     = n8x0_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = n8x0_init_irq,
+        .map_io         = n8x0_map_io,
+        .init_early     = n8x0_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 87969c7df652..7f21d24bd437 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -23,10 +23,12 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/opp.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -39,16 +41,94 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
+#include <plat/omap_device.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
+#include "pm.h"
+#include "common-board-devices.h"
 
-#define NAND_BLOCK_SIZE         SZ_128K
+/*
+ * OMAP3 Beagle revision
+ * Run time detection of Beagle revision is done by reading GPIO.
+ * GPIO ID -
+ *      AXBX    = GPIO173, GPIO172, GPIO171: 1 1 1
+ *      C1_3    = GPIO173, GPIO172, GPIO171: 1 1 0
+ *      C4      = GPIO173, GPIO172, GPIO171: 1 0 1
+ *      XM      = GPIO173, GPIO172, GPIO171: 0 0 0
+ */
+enum {
+        OMAP3BEAGLE_BOARD_UNKN = 0,
+        OMAP3BEAGLE_BOARD_AXBX,
+        OMAP3BEAGLE_BOARD_C1_3,
+        OMAP3BEAGLE_BOARD_C4,
+        OMAP3BEAGLE_BOARD_XM,
+};
+
+static u8 omap3_beagle_version;
+
+static u8 omap3_beagle_get_rev(void)
+{
+        return omap3_beagle_version;
+}
+
+static struct gpio omap3_beagle_rev_gpios[] __initdata = {
+        { 171, GPIOF_IN, "rev_id_0"    },
+        { 172, GPIOF_IN, "rev_id_1" },
+        { 173, GPIOF_IN, "rev_id_2"    },
+};
+
+static void __init omap3_beagle_init_rev(void)
+{
+        int ret;
+        u16 beagle_rev = 0;
+
+        omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
+
+        ret = gpio_request_array(omap3_beagle_rev_gpios,
+                                 ARRAY_SIZE(omap3_beagle_rev_gpios));
+        if (ret < 0) {
+                printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+                return;
+        }
+
+        beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
+                        | (gpio_get_value(173) << 2);
+
+        gpio_free_array(omap3_beagle_rev_gpios,
+                        ARRAY_SIZE(omap3_beagle_rev_gpios));
+
+        switch (beagle_rev) {
+        case 7:
+                printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
+                break;
+        case 6:
+                printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
+                break;
+        case 5:
+                printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
+                break;
+        case 0:
+                printk(KERN_INFO "OMAP3 Beagle Rev: xM\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
+                break;
+        default:
+                printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+        }
+}
 
 static struct mtd_partition omap3beagle_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
@@ -81,15 +161,6 @@ static struct mtd_partition omap3beagle_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data omap3beagle_nand_data = {
-        .options        = NAND_BUSWIDTH_16,
-        .parts          = omap3beagle_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(omap3beagle_nand_partitions),
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-        .nand_setup     = NULL,
-        .dev_ready      = NULL,
-};
-
 /* DSS */
 
 static int beagle_enable_dvi(struct omap_dss_device *dssdev)
@@ -106,14 +177,19 @@ static void beagle_disable_dvi(struct omap_dss_device *dssdev)
                 gpio_set_value(dssdev->reset_gpio, 0);
 }
 
+static struct panel_generic_dpi_data dvi_panel = {
+        .name = "generic",
+        .platform_enable = beagle_enable_dvi,
+        .platform_disable = beagle_disable_dvi,
+};
+
 static struct omap_dss_device beagle_dvi_device = {
         .type = OMAP_DISPLAY_TYPE_DPI,
         .name = "dvi",
-        .driver_name = "generic_panel",
+        .driver_name = "generic_dpi_panel",
+        .data = &dvi_panel,
         .phy.dpi.data_lines = 24,
-        .reset_gpio = 170,
-        .platform_enable = beagle_enable_dvi,
-        .platform_disable = beagle_disable_dvi,
+        .reset_gpio = -EINVAL,
 };
 
 static struct omap_dss_device beagle_tv_device = {
@@ -134,31 +210,22 @@ static struct omap_dss_board_info beagle_dss_data = {
         .default_device = &beagle_dvi_device,
 };
 
-static struct platform_device beagle_dss_device = {
-        .name          = "omapdss",
-        .id            = -1,
-        .dev            = {
-                .platform_data = &beagle_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply beagle_vdac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss");
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
 
-static struct regulator_consumer_supply beagle_vdvi_supply =
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
 
 static void __init beagle_display_init(void)
 {
         int r;
 
-        r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset");
-        if (r < 0) {
+        r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW,
+                             "DVI reset");
+        if (r < 0)
                 printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-                return;
-        }
-
-        gpio_direction_output(beagle_dvi_device.reset_gpio, 0);
 }
 
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -166,7 +233,7 @@ static void __init beagle_display_init(void)
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -185,7 +252,12 @@ static struct gpio_led gpio_leds[];
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+        int r, usb_pwr_level;
+
+        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+                mmc[0].gpio_wp = -EINVAL;
+        } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) ||
+                (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) {
                 omap_mux_init_gpio(23, OMAP_PIN_INPUT);
                 mmc[0].gpio_wp = 23;
         } else {
@@ -199,16 +271,42 @@ static int beagle_twl_gpio_setup(struct device *dev,
         beagle_vmmc1_supply.dev = mmc[0].dev;
         beagle_vsim_supply.dev = mmc[0].dev;
 
-        /* REVISIT: need ehci-omap hooks for external VBUS
-         * power switch and overcurrent detect
+        /*
+         * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
+         * high / others active low)
+         * DVI reset GPIO is different between beagle revisions
          */
+        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+                usb_pwr_level = GPIOF_OUT_INIT_HIGH;
+                beagle_dvi_device.reset_gpio = 129;
+                /*
+                 * gpio + 1 on Xm controls the TFP410's enable line (active low)
+                 * gpio + 2 control varies depending on the board rev as below:
+                 * P7/P8 revisions(prototype): Camera EN
+                 * A2+ revisions (production): LDO (DVI, serial, led blocks)
+                 */
+                r = gpio_request_one(gpio + 1, GPIOF_OUT_INIT_LOW,
+                                     "nDVI_PWR_EN");
+                if (r)
+                        pr_err("%s: unable to configure nDVI_PWR_EN\n",
+                                __func__);
+                r = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
+                                     "DVI_LDO_EN");
+                if (r)
+                        pr_err("%s: unable to configure DVI_LDO_EN\n",
+                                __func__);
+        } else {
+                usb_pwr_level = GPIOF_OUT_INIT_LOW;
+                beagle_dvi_device.reset_gpio = 170;
+                /*
+                 * REVISIT: need ehci-omap hooks for external VBUS
+                 * power switch and overcurrent detect
+                 */
+                if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
+                        pr_err("%s: unable to configure EHCI_nOC\n", __func__);
+        }
 
-        gpio_request(gpio + 1, "EHCI_nOC");
-        gpio_direction_input(gpio + 1);
-
-        /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        gpio_request_one(gpio + TWL4030_GPIO_MAX, usb_pwr_level, "nEN_USB_PWR");
 
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -282,17 +380,15 @@ static struct regulator_init_data beagle_vpll2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &beagle_vdvi_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(beagle_vdvi_supplies),
+        .consumer_supplies      = beagle_vdvi_supplies,
 };
 
 static struct twl4030_usb_data beagle_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data beagle_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data beagle_audio_data;
 
 static struct twl4030_codec_data beagle_codec_data = {
         .audio_mclk = 26000000,
@@ -313,22 +409,18 @@ static struct twl4030_platform_data beagle_twldata = {
         .vpll2          = &beagle_vpll2,
 };
 
-static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &beagle_twldata,
-        },
+static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+       {
+               I2C_BOARD_INFO("eeprom", 0x50),
+       },
 };
 
 static int __init omap3_beagle_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
-                        ARRAY_SIZE(beagle_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &beagle_twldata);
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 100, NULL, 0);
+        omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
         return 0;
 }
 
@@ -385,61 +477,31 @@ static struct platform_device keys_gpio = {
         },
 };
 
+static void __init omap3_beagle_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
+}
+
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_beagle_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
-        &beagle_dss_device,
 };
 
-static void __init omap3beagle_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                omap3beagle_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&omap3beagle_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = -EINVAL,
@@ -451,47 +513,90 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
+static void __init beagle_opp_init(void)
+{
+        int r = 0;
+
+        /* Initialize the omap3 opp table */
+        if (omap3_opp_init()) {
+                pr_err("%s: opp default init failed\n", __func__);
+                return;
+        }
+
+        /* Custom OPP enabled for XM */
+        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+                struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
+                struct omap_hwmod *dh = omap_hwmod_lookup("iva");
+                struct device *dev;
+
+                if (!mh || !dh) {
+                        pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
+                                __func__, mh, dh);
+                        return;
+                }
+                /* Enable MPU 1GHz and lower opps */
+                dev = &mh->od->pdev.dev;
+                r = opp_enable(dev, 800000000);
+                /* TODO: MPU 1GHz needs SR and ABB */
+
+                /* Enable IVA 800MHz and lower opps */
+                dev = &dh->od->pdev.dev;
+                r |= opp_enable(dev, 660000000);
+                /* TODO: DSP 800MHz needs SR and ABB */
+                if (r) {
+                        pr_err("%s: failed to enable higher opp %d\n",
+                                __func__, r);
+                        /*
+                         * Cleanup - disable the higher freqs - we dont care
+                         * about the results
+                         */
+                        dev = &mh->od->pdev.dev;
+                        opp_disable(dev, 800000000);
+                        dev = &dh->od->pdev.dev;
+                        opp_disable(dev, 660000000);
+                }
+        }
+        return;
+}
 
 static void __init omap3_beagle_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap3_beagle_init_rev();
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
+        omap_display_init(&beagle_dss_data);
         omap_serial_init();
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
-        gpio_request(170, "DVI_nPD");
         /* REVISIT leave DVI powered down until it's needed ... */
-        gpio_direction_output(170, true);
+        gpio_request_one(170, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
+
+        usb_musb_init(NULL);
+        usbhs_init(&usbhs_bdata);
+        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
+                             ARRAY_SIZE(omap3beagle_nand_partitions));
 
-        usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
-        omap3beagle_flash_init();
+        /* Ensure msecure is mux'd to be able to set the RTC. */
+        omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
         omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
         beagle_display_init();
+        beagle_opp_init();
 }
 
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3_beagle_init_early,
         .init_irq       = omap3_beagle_init_irq,
         .init_machine   = omap3_beagle_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d9c0a47a1..b4d43464a303 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -30,7 +30,10 @@
 #include <linux/usb/otg.h>
 #include <linux/smsc911x.h>
 
+#include <linux/wl12xx.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,11 +44,13 @@
 #include <plat/usb.h>
 #include <plat/common.h>
 #include <plat/mcspi.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define OMAP3_EVM_TS_GPIO       175
 #define OMAP3_EVM_EHCI_VBUS     22
@@ -56,6 +61,13 @@
 #define OMAP3EVM_ETHR_ID_REV    0x50
 #define OMAP3EVM_ETHR_GPIO_IRQ  176
 #define OMAP3EVM_SMSC911X_CS    5
+/*
+ * Eth Reset signal
+ *      64 = Generation 1 (<=RevD)
+ *      7 = Generation 2 (>=RevE)
+ */
+#define OMAP3EVM_GEN1_ETHR_GPIO_RST     64
+#define OMAP3EVM_GEN2_ETHR_GPIO_RST     7
 
 static u8 omap3_evm_version;
 
@@ -90,58 +102,35 @@ static void __init omap3_evm_get_revision(void)
 }
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-static struct resource omap3evm_smsc911x_resources[] = {
-        [0] =   {
-                .start  = OMAP3EVM_ETHR_START,
-                .end    = (OMAP3EVM_ETHR_START + OMAP3EVM_ETHR_SIZE - 1),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] =   {
-                .start  = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ),
-                .end    = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ),
-                .flags  = (IORESOURCE_IRQ | IRQF_TRIGGER_LOW),
-        },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS),
-};
+#include <plat/gpmc-smsc911x.h>
 
-static struct platform_device omap3evm_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(omap3evm_smsc911x_resources),
-        .resource       = &omap3evm_smsc911x_resources[0],
-        .dev            = {
-                .platform_data = &smsc911x_config,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = OMAP3EVM_SMSC911X_CS,
+        .gpio_irq       = OMAP3EVM_ETHR_GPIO_IRQ,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
 static inline void __init omap3evm_init_smsc911x(void)
 {
-        int eth_cs;
         struct clk *l3ck;
         unsigned int rate;
 
-        eth_cs = OMAP3EVM_SMSC911X_CS;
-
         l3ck = clk_get(NULL, "l3_ck");
         if (IS_ERR(l3ck))
                 rate = 100000000;
         else
                 rate = clk_get_rate(l3ck);
 
-        if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                        OMAP3EVM_ETHR_GPIO_IRQ);
-                return;
+        /* Configure ethernet controller reset gpio */
+        if (cpu_is_omap3430()) {
+                if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
+                        smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
+                else
+                        smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
         }
 
-        gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ);
-        platform_device_register(&omap3evm_smsc911x_device);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 #else
@@ -160,6 +149,15 @@ static inline void __init omap3evm_init_smsc911x(void) { return; }
 #define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
 #define OMAP3EVM_DVI_PANEL_EN_GPIO      199
 
+static struct gpio omap3_evm_dss_gpios[] __initdata = {
+        { OMAP3EVM_LCD_PANEL_RESB,  GPIOF_OUT_INIT_HIGH, "lcd_panel_resb"  },
+        { OMAP3EVM_LCD_PANEL_INI,   GPIOF_OUT_INIT_HIGH, "lcd_panel_ini"   },
+        { OMAP3EVM_LCD_PANEL_QVGA,  GPIOF_OUT_INIT_LOW,  "lcd_panel_qvga"  },
+        { OMAP3EVM_LCD_PANEL_LR,    GPIOF_OUT_INIT_HIGH, "lcd_panel_lr"    },
+        { OMAP3EVM_LCD_PANEL_UD,    GPIOF_OUT_INIT_HIGH, "lcd_panel_ud"    },
+        { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW,  "lcd_panel_envdd" },
+};
+
 static int lcd_enabled;
 static int dvi_enabled;
 
@@ -167,61 +165,10 @@ static void __init omap3_evm_display_init(void)
 {
         int r;
 
-        r = gpio_request(OMAP3EVM_LCD_PANEL_RESB, "lcd_panel_resb");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_resb\n");
-                return;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_RESB, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_INI, "lcd_panel_ini");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_ini\n");
-                goto err_1;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_INI, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_QVGA, "lcd_panel_qvga");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_qvga\n");
-                goto err_2;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_QVGA, 0);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_LR, "lcd_panel_lr");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_lr\n");
-                goto err_3;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_LR, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_UD, "lcd_panel_ud");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_ud\n");
-                goto err_4;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_UD, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_ENVDD, "lcd_panel_envdd");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_envdd\n");
-                goto err_5;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_ENVDD, 0);
-
-        return;
-
-err_5:
-        gpio_free(OMAP3EVM_LCD_PANEL_UD);
-err_4:
-        gpio_free(OMAP3EVM_LCD_PANEL_LR);
-err_3:
-        gpio_free(OMAP3EVM_LCD_PANEL_QVGA);
-err_2:
-        gpio_free(OMAP3EVM_LCD_PANEL_INI);
-err_1:
-        gpio_free(OMAP3EVM_LCD_PANEL_RESB);
-
+        r = gpio_request_array(omap3_evm_dss_gpios,
+                               ARRAY_SIZE(omap3_evm_dss_gpios));
+        if (r)
+                printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
 }
 
 static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
@@ -233,9 +180,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
         else
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
 
         lcd_enabled = 1;
         return 0;
@@ -246,9 +193,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
         else
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
 
         lcd_enabled = 0;
 }
@@ -287,7 +234,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
+        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
 
         dvi_enabled = 1;
         return 0;
@@ -295,18 +242,23 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
 
 static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
 {
-        gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
+        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
 
         dvi_enabled = 0;
 }
 
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = omap3_evm_enable_dvi,
+        .platform_disable       = omap3_evm_disable_dvi,
+};
+
 static struct omap_dss_device omap3_evm_dvi_device = {
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = omap3_evm_enable_dvi,
-        .platform_disable       = omap3_evm_disable_dvi,
 };
 
 static struct omap_dss_device *omap3_evm_dss_devices[] = {
@@ -321,14 +273,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
         .default_device = &omap3_evm_lcd_device,
 };
 
-static struct platform_device omap3_evm_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &omap3_evm_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
         .supply                 = "vmmc",
 };
@@ -370,10 +314,20 @@ static struct regulator_init_data omap3evm_vsim = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
         },
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        {
+                .name           = "wl1271",
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .nonremovable   = true,
+        },
+#endif
         {}      /* Terminator */
 };
 
@@ -404,6 +358,8 @@ static struct platform_device leds_gpio = {
 static int omap3evm_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int r, lcd_bl_en;
+
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
@@ -419,12 +375,14 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
          */
 
         /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
+                GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
+        r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
+        if (r)
+                printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
 
         /* gpio + 7 == DVI Enable */
-        gpio_request(gpio + 7, "EN_DVI");
-        gpio_direction_output(gpio + 7, 0);
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
 
         /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -446,7 +404,7 @@ static struct twl4030_usb_data omap3evm_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
         KEY(0, 2, KEY_ENTER),
@@ -484,19 +442,15 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = {
         .irq_line       = 1,
 };
 
-static struct twl4030_codec_audio_data omap3evm_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data omap3evm_audio_data;
 
 static struct twl4030_codec_data omap3evm_codec_data = {
         .audio_mclk = 26000000,
         .audio = &omap3evm_audio_data,
 };
 
-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &omap3_evm_dss_device.dev,
-};
+static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
 
 /* VDAC for DSS driving S-Video */
 static struct regulator_init_data omap3_evm_vdac = {
@@ -514,8 +468,10 @@ static struct regulator_init_data omap3_evm_vdac = {
 };
 
 /* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_evm_vpll2_supply =
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
 
 static struct regulator_init_data omap3_evm_vpll2 = {
         .constraints = {
@@ -527,10 +483,70 @@ static struct regulator_init_data omap3_evm_vpll2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies  = ARRAY_SIZE(omap3_evm_vpll2_supplies),
+        .consumer_supplies      = omap3_evm_vpll2_supplies,
+};
+
+/* ads7846 on SPI */
+static struct regulator_consumer_supply omap3evm_vio_supply =
+        REGULATOR_SUPPLY("vcc", "spi1.0");
+
+/* VIO for ads7846 */
+static struct regulator_init_data omap3evm_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
         .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3_evm_vpll2_supply,
+        .consumer_supplies      = &omap3evm_vio_supply,
 };
 
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+
+#define OMAP3EVM_WLAN_PMENA_GPIO        (150)
+#define OMAP3EVM_WLAN_IRQ_GPIO          (149)
+
+static struct regulator_consumer_supply omap3evm_vmmc2_supply =
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+/* VMMC2 for driving the WL12xx module */
+static struct regulator_init_data omap3evm_vmmc2 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies = &omap3evm_vmmc2_supply,
+};
+
+static struct fixed_voltage_config omap3evm_vwlan = {
+        .supply_name            = "vwl1271",
+        .microvolts             = 1800000, /* 1.80V */
+        .gpio                   = OMAP3EVM_WLAN_PMENA_GPIO,
+        .startup_delay          = 70000, /* 70ms */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &omap3evm_vmmc2,
+};
+
+static struct platform_device omap3evm_wlan_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &omap3evm_vwlan,
+        },
+};
+
+struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
+        .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
+        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
+};
+#endif
+
 static struct twl4030_platform_data omap3evm_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -543,99 +559,33 @@ static struct twl4030_platform_data omap3evm_twldata = {
         .codec          = &omap3evm_codec_data,
         .vdac           = &omap3_evm_vdac,
         .vpll2          = &omap3_evm_vpll2,
-};
-
-static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &omap3evm_twldata,
-        },
+        .vio            = &omap3evm_vio,
+        .vmmc1          = &omap3evm_vmmc1,
+        .vsim           = &omap3evm_vsim,
 };
 
 static int __init omap3_evm_i2c_init(void)
 {
-        /*
-         * REVISIT: These entries can be set in omap3evm_twl_data
-         * after a merge with MFD tree
-         */
-        omap3evm_twldata.vmmc1 = &omap3evm_vmmc1;
-        omap3evm_twldata.vsim = &omap3evm_vsim;
-
-        omap_register_i2c_bus(1, 2600, omap3evm_i2c_boardinfo,
-                        ARRAY_SIZE(omap3evm_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &omap3evm_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
 }
 
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0)
-                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
-
-        gpio_direction_input(OMAP3_EVM_TS_GPIO);
-        gpio_set_debounce(OMAP3_EVM_TS_GPIO, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_EVM_TS_GPIO);
-}
-
-struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .settle_delay_usecs     = 150,
-        .wakeup                         = true,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-struct spi_board_info omap3evm_spi_board_info[] = {
-        [0] = {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_EVM_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        },
-};
-
 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 };
 
-static void __init omap3_evm_init_irq(void)
+static void __init omap3_evm_init_early(void)
 {
-        omap_board_config = omap3_evm_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
 }
 
-static struct platform_device *omap3_evm_devices[] __initdata = {
-        &omap3_evm_dss_device,
-};
-
-static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
+static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         /* PHY reset GPIO will be runtime programmed based on EVM version */
@@ -645,16 +595,76 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
 };
 
 #ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
+static struct omap_board_mux omap35x_board_mux[] __initdata = {
         OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
                                 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
                                 OMAP_PIN_OFF_WAKEUPENABLE),
         OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
-                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_NONE),
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WLAN IRQ - GPIO 149 */
+        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* WLAN POWER ENABLE - GPIO 150 */
+        OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* MMC2 SDIO pin muxes for WL12xx */
+        OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+#endif
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static struct omap_board_mux omap36x_board_mux[] __initdata = {
+        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WLAN IRQ - GPIO 149 */
+        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* WLAN POWER ENABLE - GPIO 150 */
+        OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* MMC2 SDIO pin muxes for WL12xx */
+        OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+#endif
+
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
-#define board_mux       NULL
+#define omap35x_board_mux       NULL
+#define omap36x_board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
@@ -663,17 +673,26 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 100,
 };
 
+static struct gpio omap3_evm_ehci_gpios[] __initdata = {
+        { OMAP3_EVM_EHCI_VBUS,   GPIOF_OUT_INIT_HIGH,  "enable EHCI VBUS" },
+        { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW,   "select EHCI port" },
+};
+
 static void __init omap3_evm_init(void)
 {
         omap3_evm_get_revision();
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
-        omap3_evm_i2c_init();
+        if (cpu_is_omap3630())
+                omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
+        else
+                omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
 
-        platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
+        omap_board_config = omap3_evm_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
 
-        spi_register_board_info(omap3evm_spi_board_info,
-                                ARRAY_SIZE(omap3evm_spi_board_info));
+        omap3_evm_i2c_init();
+
+        omap_display_init(&omap3_evm_dss_data);
 
         omap_serial_init();
 
@@ -682,20 +701,16 @@ static void __init omap3_evm_init(void)
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
                 /* enable EHCI VBUS using GPIO22 */
-                omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
-                gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
-                gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
-                gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
-
+                omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
                 /* Select EHCI port on main board */
-                omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
-                gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
-                gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
-                gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
+                omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
+                                   OMAP_PIN_INPUT_PULLUP);
+                gpio_request_array(omap3_evm_ehci_gpios,
+                                   ARRAY_SIZE(omap3_evm_ehci_gpios));
 
                 /* setup EHCI phy reset config */
                 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
-                ehci_pdata.reset_gpio_port[1] = 21;
+                usbhs_bdata.reset_gpio_port[1] = 21;
 
                 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
                 musb_board_data.power = 500;
@@ -703,23 +718,29 @@ static void __init omap3_evm_init(void)
         } else {
                 /* setup EHCI phy reset on MDC */
                 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
-                ehci_pdata.reset_gpio_port[1] = 135;
+                usbhs_bdata.reset_gpio_port[1] = 135;
         }
         usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
-        ads7846_dev_init();
+        usbhs_init(&usbhs_bdata);
+        omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
         omap3evm_init_smsc911x();
         omap3_evm_display_init();
+
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WL12xx WLAN Init */
+        if (wl12xx_set_platform_data(&omap3evm_wlan_data))
+                pr_err("error setting wl12xx data\n");
+        platform_device_register(&omap3evm_wlan_regulator);
+#endif
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
         /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap3_evm_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3_evm_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap3_evm_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
new file mode 100644
index 000000000000..60d9be49dbab
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -0,0 +1,230 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3logic.c
+ *
+ * Copyright (C) 2010 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Copyright (C) 2010 Logic Product Development, Inc.
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Modified from Beagle, EVM, and RX51
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <linux/regulator/machine.h>
+
+#include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "timer-gp.h"
+#include "control.h"
+#include "common-board-devices.h"
+
+#include <plat/mux.h>
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc-smsc911x.h>
+#include <plat/gpmc.h>
+#include <plat/sdrc.h>
+
+#define OMAP3LOGIC_SMSC911X_CS                  1
+
+#define OMAP3530_LV_SOM_MMC_GPIO_CD             110
+#define OMAP3530_LV_SOM_MMC_GPIO_WP             126
+#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ       152
+
+#define OMAP3_TORPEDO_MMC_GPIO_CD               127
+#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ         129
+
+static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data omap3logic_vmmc1 = {
+        .constraints = {
+                .name                   = "VMMC1",
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &omap3logic_vmmc1_supply,
+};
+
+static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .pullups        = BIT(1),
+        .pulldowns      = BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
+                        | BIT(13) | BIT(15) | BIT(16) | BIT(17),
+};
+
+static struct twl4030_platform_data omap3logic_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .gpio           = &omap3logic_gpio_data,
+        .vmmc1          = &omap3logic_vmmc1,
+};
+
+static int __init omap3logic_i2c_init(void)
+{
+        omap3_pmic_init("twl4030", &omap3logic_twldata);
+        return 0;
+}
+
+static struct omap2_hsmmc_info __initdata board_mmc_info[] = {
+        {
+                .name           = "external",
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+
+static void __init board_mmc_init(void)
+{
+        if (machine_is_omap3530_lv_som()) {
+                /* OMAP3530 LV SOM board */
+                board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD;
+                board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP;
+                omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT);
+        } else if (machine_is_omap3_torpedo()) {
+                /* OMAP3 Torpedo board */
+                board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD;
+                omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT);
+        } else {
+                /* unsupported board */
+                printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+                return;
+        }
+
+        omap2_hsmmc_init(board_mmc_info);
+        /* link regulators to MMC adapters */
+        omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
+}
+
+static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
+        .cs             = OMAP3LOGIC_SMSC911X_CS,
+        .gpio_irq       = -EINVAL,
+        .gpio_reset     = -EINVAL,
+};
+
+/* TODO/FIXME (comment by Peter Barada, LogicPD):
+ * Fix the PBIAS voltage for Torpedo MMC1 pins that
+ * are used for other needs (IRQs, etc).            */
+static void omap3torpedo_fix_pbias_voltage(void)
+{
+        u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+        u32 reg;
+
+        if (machine_is_omap3_torpedo())
+        {
+                /* Set the bias for the pin */
+                reg = omap_ctrl_readl(control_pbias_offset);
+
+                reg &= ~OMAP343X_PBIASLITEPWRDNZ1;
+                omap_ctrl_writel(reg, control_pbias_offset);
+
+                /* 100ms delay required for PBIAS configuration */
+                msleep(100);
+
+                reg |= OMAP343X_PBIASLITEVMODE1;
+                reg |= OMAP343X_PBIASLITEPWRDNZ1;
+                omap_ctrl_writel(reg | 0x300, control_pbias_offset);
+        }
+}
+
+static inline void __init board_smsc911x_init(void)
+{
+        if (machine_is_omap3530_lv_som()) {
+                /* OMAP3530 LV SOM board */
+                board_smsc911x_data.gpio_irq =
+                                        OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ;
+                omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT);
+        } else if (machine_is_omap3_torpedo()) {
+                /* OMAP3 Torpedo board */
+                board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ;
+                omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT);
+        } else {
+                /* unsupported board */
+                printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+                return;
+        }
+
+        gpmc_smsc911x_init(&board_smsc911x_data);
+}
+
+static void __init omap3logic_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#endif
+
+static void __init omap3logic_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap3torpedo_fix_pbias_voltage();
+        omap3logic_i2c_init();
+        omap_serial_init();
+        board_mmc_init();
+        board_smsc911x_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3logic_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = omap3logic_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3logic_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = omap3logic_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index dd3af2be13be..23f71d40883e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -22,17 +22,19 @@
 #include <linux/platform_device.h>
 
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-#include <linux/spi/wl12xx.h>
+#include <linux/wl12xx.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
+#include <linux/regulator/fixed.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -40,23 +42,21 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <mach/gpio.h>
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/nand.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define PANDORA_WIFI_IRQ_GPIO           21
 #define PANDORA_WIFI_NRESET_GPIO        23
 #define OMAP3_PANDORA_TS_GPIO           94
 
-#define NAND_BLOCK_SIZE                 SZ_128K
-
 static struct mtd_partition omap3pandora_nand_partitions[] = {
         {
                 .name           = "xloader",
@@ -84,7 +84,8 @@ static struct mtd_partition omap3pandora_nand_partitions[] = {
 
 static struct omap_nand_platform_data pandora_nand_data = {
         .cs             = 0,
-        .devsize        = 1,    /* '0' for 8-bit, '1' for 16-bit device */
+        .devsize        = NAND_BUSWIDTH_16,
+        .xfer_type      = NAND_OMAP_PREFETCH_DMA,
         .parts          = omap3pandora_nand_partitions,
         .nr_parts       = ARRAY_SIZE(omap3pandora_nand_partitions),
 };
@@ -251,14 +252,6 @@ static struct omap_dss_board_info pandora_dss_data = {
         .default_device = &pandora_lcd_device,
 };
 
-static struct platform_device pandora_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &pandora_dss_data,
-        },
-};
-
 static void pandora_wl1251_init_card(struct mmc_card *card)
 {
         /*
@@ -276,14 +269,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card)
 static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 126,
                 .ext_clock      = 0,
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 127,
                 .ext_clock      = 1,
@@ -291,7 +284,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         },
         {
                 .mmc            = 3,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .init_card      = pandora_wl1251_init_card,
@@ -311,24 +304,13 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 
         /* gpio + 13 drives 32kHz buffer for wifi module */
         gpio_32khz = gpio + 13;
-        ret = gpio_request(gpio_32khz, "wifi 32kHz");
+        ret = gpio_request_one(gpio_32khz, GPIOF_OUT_INIT_HIGH, "wifi 32kHz");
         if (ret < 0) {
                 pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret);
-                goto fail;
-        }
-
-        ret = gpio_direction_output(gpio_32khz, 1);
-        if (ret < 0) {
-                pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret);
-                goto fail_direction;
+                return -ENODEV;
         }
 
         return 0;
-
-fail_direction:
-        gpio_free(gpio_32khz);
-fail:
-        return -ENODEV;
 }
 
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
@@ -339,17 +321,21 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
 };
 
 static struct regulator_consumer_supply pandora_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 static struct regulator_consumer_supply pandora_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+static struct regulator_consumer_supply pandora_vmmc3_supply =
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
 
 static struct regulator_consumer_supply pandora_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss");
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
 
 static struct regulator_consumer_supply pandora_vdds_supplies[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
         REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 
 static struct regulator_consumer_supply pandora_vcc_lcd_supply =
@@ -488,19 +474,46 @@ static struct regulator_init_data pandora_vsim = {
         .consumer_supplies      = &pandora_adac_supply,
 };
 
+/* Fixed regulator internal to Wifi module */
+static struct regulator_init_data pandora_vmmc3 = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &pandora_vmmc3_supply,
+};
+
+static struct fixed_voltage_config pandora_vwlan = {
+        .supply_name            = "vwlan",
+        .microvolts             = 1800000, /* 1.8V */
+        .gpio                   = PANDORA_WIFI_NRESET_GPIO,
+        .startup_delay          = 50000, /* 50ms */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &pandora_vmmc3,
+};
+
+static struct platform_device pandora_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &pandora_vwlan,
+        },
+};
+
 static struct twl4030_usb_data omap3pandora_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data omap3pandora_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data omap3pandora_audio_data;
 
 static struct twl4030_codec_data omap3pandora_codec_data = {
         .audio_mclk = 26000000,
         .audio = &omap3pandora_audio_data,
 };
 
+static struct twl4030_bci_platform_data pandora_bci_data;
+
 static struct twl4030_platform_data omap3pandora_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -516,15 +529,7 @@ static struct twl4030_platform_data omap3pandora_twldata = {
         .vaux4          = &pandora_vaux4,
         .vsim           = &pandora_vsim,
         .keypad         = &pandora_kp_data,
-};
-
-static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65950", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &omap3pandora_twldata,
-        },
+        .bci            = &pandora_bci_data,
 };
 
 static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
@@ -536,61 +541,15 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
 
 static int __init omap3pandora_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
-                        ARRAY_SIZE(omap3pandora_i2c_boardinfo));
+        omap3_pmic_init("tps65950", &omap3pandora_twldata);
         /* i2c2 pins are not connected */
         omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
                         ARRAY_SIZE(omap3pandora_i2c3_boardinfo));
         return 0;
 }
 
-static void __init omap3pandora_ads7846_init(void)
-{
-        int gpio = OMAP3_PANDORA_TS_GPIO;
-        int ret;
-
-        ret = gpio_request(gpio, "ads7846_pen_down");
-        if (ret < 0) {
-                printk(KERN_ERR "Failed to request GPIO %d for "
-                                "ads7846 pen down IRQ\n", gpio);
-                return;
-        }
-
-        gpio_direction_input(gpio);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_PANDORA_TS_GPIO);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
 static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        }, {
                 .modalias               = "tpo_td043mtea1_panel_spi",
                 .bus_num                = 1,
                 .chip_select            = 1,
@@ -599,64 +558,35 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         }
 };
 
-static void __init omap3pandora_init_irq(void)
+static void __init omap3pandora_init_early(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
 }
 
-static void pandora_wl1251_set_power(bool enable)
-{
-        /*
-         * Keep power always on until wl1251_sdio driver learns to re-init
-         * the chip after powering it down and back up.
-         */
-}
-
-static struct wl12xx_platform_data pandora_wl1251_pdata = {
-        .set_power      = pandora_wl1251_set_power,
-        .use_eeprom     = true,
-};
-
-static struct platform_device pandora_wl1251_data = {
-        .name           = "wl1251_data",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &pandora_wl1251_pdata,
-        },
-};
-
-static void pandora_wl1251_init(void)
+static void __init pandora_wl1251_init(void)
 {
+        struct wl12xx_platform_data pandora_wl1251_pdata;
         int ret;
 
-        ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq");
-        if (ret < 0)
-                goto fail;
+        memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
 
-        ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO);
+        ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq");
         if (ret < 0)
-                goto fail_irq;
+                goto fail;
 
         pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO);
         if (pandora_wl1251_pdata.irq < 0)
                 goto fail_irq;
 
-        ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset");
+        pandora_wl1251_pdata.use_eeprom = true;
+        ret = wl12xx_set_platform_data(&pandora_wl1251_pdata);
         if (ret < 0)
                 goto fail_irq;
 
-        /* start powered so that it probes with MMC subsystem */
-        ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1);
-        if (ret < 0)
-                goto fail_nreset;
-
         return;
 
-fail_nreset:
-        gpio_free(PANDORA_WIFI_NRESET_GPIO);
 fail_irq:
         gpio_free(PANDORA_WIFI_IRQ_GPIO);
 fail:
@@ -666,15 +596,14 @@ fail:
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
-        &pandora_dss_device,
-        &pandora_wl1251_data,
+        &pandora_vwlan_device,
 };
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = 16,
@@ -686,16 +615,8 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init omap3pandora_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -703,12 +624,13 @@ static void __init omap3pandora_init(void)
         pandora_wl1251_init();
         platform_add_devices(omap3pandora_devices,
                         ARRAY_SIZE(omap3pandora_devices));
+        omap_display_init(&pandora_dss_data);
         omap_serial_init();
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
-        omap3pandora_ads7846_init();
-        usb_ehci_init(&ehci_pdata);
-        usb_musb_init(&musb_board_data);
+        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
+        usbhs_init(&usbhs_bdata);
+        usb_musb_init(NULL);
         gpmc_nand_init(&pandora_nand_data);
 
         /* Ensure SDRC pins are mux'd for self-refresh */
@@ -717,12 +639,11 @@ static void __init omap3pandora_init(void)
 }
 
 MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap3pandora_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3pandora_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap3pandora_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index bcd01d278c65..0c108a212ea2 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -26,6 +26,7 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -38,13 +39,12 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/i2c/at24.h>
@@ -52,52 +52,29 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
+#include "common-board-devices.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#include <plat/gpmc-smsc911x.h>
+
 #define OMAP3STALKER_ETHR_START 0x2c000000
 #define OMAP3STALKER_ETHR_SIZE  1024
 #define OMAP3STALKER_ETHR_GPIO_IRQ      19
 #define OMAP3STALKER_SMC911X_CS 5
 
-static struct resource omap3stalker_smsc911x_resources[] = {
-        [0] = {
-               .start   = OMAP3STALKER_ETHR_START,
-               .end     =
-               (OMAP3STALKER_ETHR_START + OMAP3STALKER_ETHR_SIZE - 1),
-               .flags   = IORESOURCE_MEM,
-        },
-        [1] = {
-               .start   = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ),
-               .end     = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ),
-               .flags   = (IORESOURCE_IRQ | IRQF_TRIGGER_LOW),
-        },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = OMAP3STALKER_SMC911X_CS,
+        .gpio_irq       = OMAP3STALKER_ETHR_GPIO_IRQ,
+        .gpio_reset     = -EINVAL,
         .flags          = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS),
 };
 
-static struct platform_device omap3stalker_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(omap3stalker_smsc911x_resources),
-        .resource       = &omap3stalker_smsc911x_resources[0],
-        .dev            = {
-                .platform_data  = &smsc911x_config,
-        },
-};
-
 static inline void __init omap3stalker_init_eth(void)
 {
-        int eth_cs;
         struct clk *l3ck;
         unsigned int rate;
 
-        eth_cs = OMAP3STALKER_SMC911X_CS;
-
         l3ck = clk_get(NULL, "l3_ck");
         if (IS_ERR(l3ck))
                 rate = 100000000;
@@ -105,16 +82,7 @@ static inline void __init omap3stalker_init_eth(void)
                 rate = clk_get_rate(l3ck);
 
         omap_mux_init_gpio(19, OMAP_PIN_INPUT_PULLUP);
-        if (gpio_request(OMAP3STALKER_ETHR_GPIO_IRQ, "SMC911x irq") < 0) {
-                printk(KERN_ERR
-                       "Failed to request GPIO%d for smc911x IRQ\n",
-                       OMAP3STALKER_ETHR_GPIO_IRQ);
-                return;
-        }
-
-        gpio_direction_input(OMAP3STALKER_ETHR_GPIO_IRQ);
-
-        platform_device_register(&omap3stalker_smsc911x_device);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 #else
@@ -159,13 +127,18 @@ static void omap3_stalker_disable_lcd(struct omap_dss_device *dssdev)
         lcd_enabled = 0;
 }
 
+static struct panel_generic_dpi_data lcd_panel = {
+        .name                   = "generic",
+        .platform_enable        = omap3_stalker_enable_lcd,
+        .platform_disable       = omap3_stalker_disable_lcd,
+};
+
 static struct omap_dss_device omap3_stalker_lcd_device = {
         .name                   = "lcd",
-        .driver_name            = "generic_panel",
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &lcd_panel,
         .phy.dpi.data_lines     = 24,
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .platform_enable        = omap3_stalker_enable_lcd,
-        .platform_disable       = omap3_stalker_disable_lcd,
 };
 
 static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev)
@@ -207,13 +180,18 @@ static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev)
         dvi_enabled = 0;
 }
 
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = omap3_stalker_enable_dvi,
+        .platform_disable       = omap3_stalker_disable_dvi,
+};
+
 static struct omap_dss_device omap3_stalker_dvi_device = {
         .name                   = "dvi",
-        .driver_name            = "generic_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = omap3_stalker_enable_dvi,
-        .platform_disable       = omap3_stalker_disable_dvi,
 };
 
 static struct omap_dss_device *omap3_stalker_dss_devices[] = {
@@ -228,14 +206,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
         .default_device = &omap3_stalker_dvi_device,
 };
 
-static struct platform_device omap3_stalker_dss_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &omap3_stalker_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
         .supply         = "vmmc",
 };
@@ -275,7 +245,7 @@ static struct regulator_init_data omap3stalker_vsim = {
 static struct omap2_hsmmc_info mmc[] = {
         {
          .mmc           = 1,
-         .wires         = 4,
+         .caps          = MMC_CAP_4_BIT_DATA,
          .gpio_cd       = -EINVAL,
          .gpio_wp       = 23,
          },
@@ -361,12 +331,11 @@ omap3stalker_twl_gpio_setup(struct device *dev,
          */
 
         /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        gpio_request_one(gpio + TWL4030_GPIO_MAX, GPIOF_OUT_INIT_LOW,
+                         "EN_LCD_BKL");
 
         /* gpio + 7 == DVI Enable */
-        gpio_request(gpio + 7, "EN_DVI");
-        gpio_direction_output(gpio + 7, 0);
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
 
         /* TWL4030_GPIO_MAX + 1 == ledB (out, mmc0) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -389,7 +358,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
         KEY(0, 2, KEY_ENTER),
@@ -427,19 +396,15 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = {
         .irq_line       = 1,
 };
 
-static struct twl4030_codec_audio_data omap3stalker_audio_data = {
-        .audio_mclk     = 26000000,
-};
+static struct twl4030_codec_audio_data omap3stalker_audio_data;
 
 static struct twl4030_codec_data omap3stalker_codec_data = {
         .audio_mclk     = 26000000,
         .audio          = &omap3stalker_audio_data,
 };
 
-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &omap3_stalker_dss_device.dev,
-};
+static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
 
 /* VDAC for DSS driving S-Video */
 static struct regulator_init_data omap3_stalker_vdac = {
@@ -457,9 +422,9 @@ static struct regulator_init_data omap3_stalker_vdac = {
 };
 
 /* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
-        .supply         = "vdds_dsi",
-        .dev            = &omap3_stalker_lcd_device.dev,
+static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 
 static struct regulator_init_data omap3_stalker_vpll2 = {
@@ -473,8 +438,8 @@ static struct regulator_init_data omap3_stalker_vpll2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                 | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3_stalker_vpll2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
+        .consumer_supplies      = omap3_stalker_vpll2_supplies,
 };
 
 static struct twl4030_platform_data omap3stalker_twldata = {
@@ -489,15 +454,8 @@ static struct twl4030_platform_data omap3stalker_twldata = {
         .codec          = &omap3stalker_codec_data,
         .vdac           = &omap3_stalker_vdac,
         .vpll2          = &omap3_stalker_vpll2,
-};
-
-static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo[] = {
-        {
-         I2C_BOARD_INFO("twl4030", 0x48),
-         .flags         = I2C_CLIENT_WAKE,
-         .irq           = INT_34XX_SYS_NIRQ,
-         .platform_data = &omap3stalker_twldata,
-         },
+        .vmmc1          = &omap3stalker_vmmc1,
+        .vsim           = &omap3stalker_vsim,
 };
 
 static struct at24_platform_data fram_info = {
@@ -516,15 +474,7 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
 
 static int __init omap3_stalker_i2c_init(void)
 {
-        /*
-         * REVISIT: These entries can be set in omap3evm_twl_data
-         * after a merge with MFD tree
-         */
-        omap3stalker_twldata.vmmc1 = &omap3stalker_vmmc1;
-        omap3stalker_twldata.vsim = &omap3stalker_vsim;
-
-        omap_register_i2c_bus(1, 2600, omap3stalker_i2c_boardinfo,
-                              ARRAY_SIZE(omap3stalker_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &omap3stalker_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
                               ARRAY_SIZE(omap3stalker_i2c_boardinfo3));
@@ -532,74 +482,32 @@ static int __init omap3_stalker_i2c_init(void)
 }
 
 #define OMAP3_STALKER_TS_GPIO   175
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(OMAP3_STALKER_TS_GPIO, "ADS7846 pendown") < 0)
-                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
 
-        gpio_direction_input(OMAP3_STALKER_TS_GPIO);
-        gpio_set_debounce(OMAP3_STALKER_TS_GPIO, 310);
-}
+static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
+};
 
-static int ads7846_get_pendown_state(void)
+static void __init omap3_stalker_init_early(void)
 {
-        return !gpio_get_value(OMAP3_STALKER_TS_GPIO);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
 }
 
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .settle_delay_usecs     = 150,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode             = 0,
-        .single_channel         = 1,    /* 0: slave, 1: master */
-};
-
-struct spi_board_info omap3stalker_spi_board_info[] = {
-        [0] = {
-               .modalias        = "ads7846",
-               .bus_num         = 1,
-               .chip_select     = 0,
-               .max_speed_hz    = 1500000,
-               .controller_data = &ads7846_mcspi_config,
-               .irq             = OMAP_GPIO_IRQ(OMAP3_STALKER_TS_GPIO),
-               .platform_data   = &ads7846_config,
-        },
-};
-
-static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
-};
-
 static void __init omap3_stalker_init_irq(void)
 {
-        omap_board_config = omap3_stalker_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_stalker_devices[] __initdata = {
-        &omap3_stalker_dss_device,
         &keys_gpio,
 };
 
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+static struct usbhs_omap_board_data usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset = true,
         .reset_gpio_port[0] = -EINVAL,
@@ -615,32 +523,25 @@ static struct omap_board_mux board_mux[] __initdata = {
                   OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
         {.reg_offset = OMAP_MUX_TERMINATOR},
 };
-#else
-#define board_mux       NULL
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type = MUSB_INTERFACE_ULPI,
-        .mode           = MUSB_OTG,
-        .power          = 100,
-};
-
 static void __init omap3_stalker_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
+        omap_board_config = omap3_stalker_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
         omap3_stalker_i2c_init();
 
         platform_add_devices(omap3_stalker_devices,
                              ARRAY_SIZE(omap3_stalker_devices));
 
-        spi_register_board_info(omap3stalker_spi_board_info,
-                                ARRAY_SIZE(omap3stalker_spi_board_info));
+        omap_display_init(&omap3_stalker_dss_data);
 
         omap_serial_init();
-        usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
-        ads7846_dev_init();
+        usb_musb_init(NULL);
+        usbhs_init(&usbhs_bdata);
+        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
 
         omap_mux_init_gpio(21, OMAP_PIN_OUTPUT);
         omap_mux_init_gpio(18, OMAP_PIN_INPUT_PULLUP);
@@ -654,10 +555,9 @@ static void __init omap3_stalker_init(void)
 
 MACHINE_START(SBC3530, "OMAP3 STALKER")
         /* Maintainer: Jason Lam -lzg@ema-tech.com */
-        .phys_io                = 0x48000000,
-        .io_pg_offst            = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params            = 0x80000100,
         .map_io                 = omap3_map_io,
+        .init_early             = omap3_stalker_init_early,
         .init_irq               = omap3_stalker_init_irq,
         .init_machine           = omap3_stalker_init,
         .timer                  = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 663c62d271e8..5f649faf7377 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <plat/mcspi.h>
 #include <linux/spi/spi.h>
@@ -47,21 +48,20 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
+#include "common-board-devices.h"
 
 #include <asm/setup.h>
 
-#define NAND_BLOCK_SIZE         SZ_128K
-
 #define OMAP3_AC_GPIO           136
 #define OMAP3_TS_GPIO           162
 #define TB_BL_PWM_TIMER         9
 #define TB_KILL_POWER_GPIO      168
 
-unsigned long touchbook_revision;
+static unsigned long touchbook_revision;
 
 static struct mtd_partition omap3touchbook_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
@@ -94,21 +94,12 @@ static struct mtd_partition omap3touchbook_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data omap3touchbook_nand_data = {
-        .options        = NAND_BUSWIDTH_16,
-        .parts          = omap3touchbook_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(omap3touchbook_nand_partitions),
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-        .nand_setup     = NULL,
-        .dev_ready      = NULL,
-};
-
 #include "sdram-micron-mt46h32m32lf-6.h"
 
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -153,13 +144,11 @@ static int touchbook_twl_gpio_setup(struct device *dev,
         /* REVISIT: need ehci-omap hooks for external VBUS
          * power switch and overcurrent detect
          */
-
-        gpio_request(gpio + 1, "EHCI_nOC");
-        gpio_direction_input(gpio + 1);
+        gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC");
 
         /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        gpio_request_one(gpio + TWL4030_GPIO_MAX, GPIOF_OUT_INIT_LOW,
+                         "nEN_USB_PWR");
 
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -251,9 +240,7 @@ static struct twl4030_usb_data touchbook_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data touchbook_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data touchbook_audio_data;
 
 static struct twl4030_codec_data touchbook_codec_data = {
         .audio_mclk = 26000000,
@@ -274,15 +261,6 @@ static struct twl4030_platform_data touchbook_twldata = {
         .vpll2          = &touchbook_vpll2,
 };
 
-static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &touchbook_twldata,
-        },
-};
-
 static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
         {
                 I2C_BOARD_INFO("bq27200", 0x55),
@@ -292,8 +270,7 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
 static int __init omap3_touchbook_i2c_init(void)
 {
         /* Standard TouchBook bus */
-        omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
-                        ARRAY_SIZE(touchbook_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &touchbook_twldata);
 
         /* Additional TouchBook bus */
         omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
@@ -302,19 +279,7 @@ static int __init omap3_touchbook_i2c_init(void)
         return 0;
 }
 
-static void __init omap3_ads7846_init(void)
-{
-        if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
-                printk(KERN_ERR "Failed to request GPIO %d for "
-                                "ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
-                return;
-        }
-
-        gpio_direction_input(OMAP3_TS_GPIO);
-        gpio_set_debounce(OMAP3_TS_GPIO, 310);
-}
-
-static struct ads7846_platform_data ads7846_config = {
+static struct ads7846_platform_data ads7846_pdata = {
         .x_min                  = 100,
         .y_min                  = 265,
         .x_max                  = 3950,
@@ -328,23 +293,6 @@ static struct ads7846_platform_data ads7846_config = {
         .keep_vref_on           = 1,
 };
 
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 4,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        }
-};
-
 static struct gpio_led gpio_leds[] = {
         {
                 .name                   = "touchbook::usr0",
@@ -412,22 +360,21 @@ static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
+static void __init omap3_touchbook_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
+}
+
 static void __init omap3_touchbook_init_irq(void)
 {
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap_board_config = omap3_touchbook_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
@@ -436,44 +383,11 @@ static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &keys_gpio,
 };
 
-static void __init omap3touchbook_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                omap3touchbook_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&omap3touchbook_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = -EINVAL,
@@ -483,15 +397,10 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 
 static void omap3_touchbook_poweroff(void)
 {
-        int r;
+        int pwr_off = TB_KILL_POWER_GPIO;
 
-        r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
-        if (r < 0) {
+        if (gpio_request_one(pwr_off, GPIOF_OUT_INIT_LOW, "DVI reset") < 0)
                 printk(KERN_ERR "Unable to get kill power GPIO\n");
-                return;
-        }
-
-        gpio_direction_output(TB_KILL_POWER_GPIO, 0);
 }
 
 static int __init early_touchbook_revision(char *p)
@@ -503,14 +412,12 @@ static int __init early_touchbook_revision(char *p)
 }
 early_param("tbr", early_touchbook_revision);
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init omap3_touchbook_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = omap3_touchbook_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+
         pm_power_off = omap3_touchbook_poweroff;
 
         omap3_touchbook_i2c_init();
@@ -519,17 +426,15 @@ static void __init omap3_touchbook_init(void)
         omap_serial_init();
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
-        gpio_request(176, "DVI_nPD");
         /* REVISIT leave DVI powered down until it's needed ... */
-        gpio_direction_output(176, true);
+        gpio_request_one(176, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
 
         /* Touchscreen and accelerometer */
-        spi_register_board_info(omap3_ads7846_spi_board_info,
-                                ARRAY_SIZE(omap3_ads7846_spi_board_info));
-        omap3_ads7846_init();
-        usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
-        omap3touchbook_flash_init();
+        omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
+        usb_musb_init(NULL);
+        usbhs_init(&usbhs_bdata);
+        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
+                             ARRAY_SIZE(omap3touchbook_nand_partitions));
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -538,11 +443,10 @@ static void __init omap3_touchbook_init(void)
 
 MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3_touchbook_init_early,
         .init_irq       = omap3_touchbook_init_irq,
         .init_machine   = omap3_touchbook_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index c03d1d56db56..0cfe2005cb50 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -19,45 +19,165 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/wl12xx.h>
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <video/omapdss.h>
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
-#include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include <video/omap-panel-generic-dpi.h>
+#include "timer-gp.h"
+
 #include "hsmmc.h"
+#include "control.h"
+#include "mux.h"
+#include "common-board-devices.h"
+
+#define GPIO_HUB_POWER          1
+#define GPIO_HUB_NRESET         62
+#define GPIO_WIFI_PMENA         43
+#define GPIO_WIFI_IRQ           53
+#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
+#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
+
+/* wl127x BT, FM, GPS connectivity chip */
+static int wl1271_gpios[] = {46, -1, -1};
+static struct platform_device wl1271_device = {
+        .name   = "kim",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &wl1271_gpios,
+        },
+};
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "pandaboard::status1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 7,
+        },
+        {
+                .name                   = "pandaboard::status2",
+                .default_trigger        = "mmc0",
+                .gpio                   = 8,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
 
+static struct platform_device *panda_devices[] __initdata = {
+        &leds_gpio,
+        &wl1271_device,
+};
 
-static void __init omap4_panda_init_irq(void)
+static void __init omap4_panda_init_early(void)
 {
-        omap2_init_common_hw(NULL, NULL);
-        gic_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .phy_reset  = false,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static struct gpio panda_ehci_gpios[] __initdata = {
+        { GPIO_HUB_POWER,       GPIOF_OUT_INIT_LOW,  "hub_power"  },
+        { GPIO_HUB_NRESET,      GPIOF_OUT_INIT_LOW,  "hub_nreset" },
+};
+
+static void __init omap4_ehci_init(void)
+{
+        int ret;
+        struct clk *phy_ref_clk;
+
+        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
+        phy_ref_clk = clk_get(NULL, "auxclk3_ck");
+        if (IS_ERR(phy_ref_clk)) {
+                pr_err("Cannot request auxclk3\n");
+                return;
+        }
+        clk_set_rate(phy_ref_clk, 19200000);
+        clk_enable(phy_ref_clk);
+
+        /* disable the power to the usb hub prior to init and reset phy+hub */
+        ret = gpio_request_array(panda_ehci_gpios,
+                                 ARRAY_SIZE(panda_ehci_gpios));
+        if (ret) {
+                pr_err("Unable to initialize EHCI power/reset\n");
+                return;
+        }
+
+        gpio_export(GPIO_HUB_POWER, 0);
+        gpio_export(GPIO_HUB_NRESET, 0);
+        gpio_set_value(GPIO_HUB_NRESET, 1);
+
+        usbhs_init(&usbhs_bdata);
+
+        /* enable power to hub */
+        gpio_set_value(GPIO_HUB_POWER, 1);
 }
 
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_PERIPHERAL,
+        .mode                   = MUSB_OTG,
         .power                  = 100,
 };
 
+static struct twl4030_usb_data omap4_usbphy_data = {
+        .phy_init       = omap4430_phy_init,
+        .phy_exit       = omap4430_phy_exit,
+        .phy_power      = omap4430_phy_power,
+        .phy_set_clock  = omap4430_phy_set_clk,
+        .phy_suspend    = omap4430_phy_suspend,
+};
+
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+        },
+        {
+                .name           = "wl1271",
+                .mmc            = 5,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .ocr_mask       = MMC_VDD_165_195,
+                .nonremovable   = true,
         },
         {}      /* Terminator */
 };
@@ -65,14 +185,47 @@ static struct omap2_hsmmc_info mmc[] = {
 static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
         {
                 .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.0",
+                .dev_name = "omap_hsmmc.0",
         },
-        {
-                .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.1",
+};
+
+static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
+        .supply = "vmmc",
+        .dev_name = "omap_hsmmc.4",
+};
+
+static struct regulator_init_data panda_vmmc5 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &omap4_panda_vmmc5_supply,
+};
+
+static struct fixed_voltage_config panda_vwlan = {
+        .supply_name = "vwl1271",
+        .microvolts = 1800000, /* 1.8V */
+        .gpio = GPIO_WIFI_PMENA,
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,
+        .enabled_at_boot = 0,
+        .init_data = &panda_vmmc5,
+};
+
+static struct platform_device omap_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &panda_vwlan,
         },
 };
 
+struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
+        .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
+        /* PANDA ref clock is 38.4 MHz */
+        .board_ref_clock = 2,
+};
+
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
         int ret = 0;
@@ -80,16 +233,32 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
                                 struct platform_device, dev);
         struct omap_mmc_platform_data *pdata = dev->platform_data;
 
+        if (!pdata) {
+                dev_err(dev, "%s: NULL platform data\n", __func__);
+                return -EINVAL;
+        }
         /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0)
-                pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
-                                                MMCDETECT_INTR_OFFSET;
+        if (pdev->id == 0) {
+                ret = twl6030_mmc_card_detect_config();
+                 if (ret)
+                        dev_err(dev, "%s: Error card detect config(%d)\n",
+                                __func__, ret);
+                 else
+                        pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+        }
         return ret;
 }
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 {
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        struct omap_mmc_platform_data *pdata;
+
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
+                return;
+        }
+        pdata = dev->platform_data;
 
         pdata->init =   omap4_twl6030_hsmmc_late_init;
 }
@@ -105,19 +274,6 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
         return 0;
 }
 
-static struct regulator_init_data omap4_panda_vaux1 = {
-        .constraints = {
-                .min_uV                 = 1000000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
 static struct regulator_init_data omap4_panda_vaux2 = {
         .constraints = {
                 .min_uV                 = 1200000,
@@ -156,7 +312,7 @@ static struct regulator_init_data omap4_panda_vmmc = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 2,
+        .num_consumer_supplies  = 1,
         .consumer_supplies      = omap4_panda_vmmc_supply,
 };
 
@@ -173,24 +329,10 @@ static struct regulator_init_data omap4_panda_vpp = {
         },
 };
 
-static struct regulator_init_data omap4_panda_vusim = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 2900000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
 static struct regulator_init_data omap4_panda_vana = {
         .constraints = {
                 .min_uV                 = 2100000,
                 .max_uV                 = 2100000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -202,7 +344,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -214,7 +355,6 @@ static struct regulator_init_data omap4_panda_vdac = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -234,6 +374,12 @@ static struct regulator_init_data omap4_panda_vusb = {
         },
 };
 
+static struct regulator_init_data omap4_panda_clk32kg = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+};
+
 static struct twl4030_platform_data omap4_panda_twldata = {
         .irq_base       = TWL6030_IRQ_BASE,
         .irq_end        = TWL6030_IRQ_END,
@@ -241,49 +387,319 @@ static struct twl4030_platform_data omap4_panda_twldata = {
         /* Regulators */
         .vmmc           = &omap4_panda_vmmc,
         .vpp            = &omap4_panda_vpp,
-        .vusim          = &omap4_panda_vusim,
         .vana           = &omap4_panda_vana,
         .vcxio          = &omap4_panda_vcxio,
         .vdac           = &omap4_panda_vdac,
         .vusb           = &omap4_panda_vusb,
-        .vaux1          = &omap4_panda_vaux1,
         .vaux2          = &omap4_panda_vaux2,
         .vaux3          = &omap4_panda_vaux3,
+        .clk32kg        = &omap4_panda_clk32kg,
+        .usb            = &omap4_usbphy_data,
 };
 
-static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = {
+/*
+ * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
+ * is connected as I2C slave device, and can be accessed at address 0x50
+ */
+static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
         {
-                I2C_BOARD_INFO("twl6030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = OMAP44XX_IRQ_SYS_1N,
-                .platform_data = &omap4_panda_twldata,
+                I2C_BOARD_INFO("eeprom", 0x50),
         },
 };
+
 static int __init omap4_panda_i2c_init(void)
 {
+        omap4_pmic_init("twl6030", &omap4_panda_twldata);
+        omap_register_i2c_bus(2, 400, NULL, 0);
         /*
-         * Phoenix Audio IC needs I2C1 to
-         * start with 400 KHz or less
+         * Bus 3 is attached to the DVI port where devices like the pico DLP
+         * projector don't work reliably with 400kHz
          */
-        omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo,
-                        ARRAY_SIZE(omap4_panda_i2c_boardinfo));
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        omap_register_i2c_bus(3, 400, NULL, 0);
+        omap_register_i2c_bus(3, 100, panda_i2c_eeprom,
+                                        ARRAY_SIZE(panda_i2c_eeprom));
         omap_register_i2c_bus(4, 400, NULL, 0);
         return 0;
 }
-static void __init omap4_panda_init(void)
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        /* WLAN IRQ - GPIO 53 */
+        OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
+        /* WLAN POWER ENABLE - GPIO 43 */
+        OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* WLAN SDIO: MMC5 CMD */
+        OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC5 CLK */
+        OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC5 DAT[0-3] */
+        OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* gpio 0 - TFP410 PD */
+        OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
+        /* dispc2_data23 */
+        OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data22 */
+        OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data21 */
+        OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data20 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data19 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data18 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data15 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data14 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data13 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data12 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data11 */
+        OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data10 */
+        OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data9 */
+        OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data16 */
+        OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data17 */
+        OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_hsync */
+        OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_pclk */
+        OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_vsync */
+        OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_de */
+        OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data8 */
+        OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data7 */
+        OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data6 */
+        OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data5 */
+        OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data4 */
+        OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data3 */
+        OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data2 */
+        OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data1 */
+        OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* dispc2_data0 */
+        OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
+                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
+                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial3_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
+                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
+                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial4_pads[] __initdata = {
+        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
+                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
+        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
+                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_board_data serial2_data __initdata = {
+        .id             = 1,
+        .pads           = serial2_pads,
+        .pads_cnt       = ARRAY_SIZE(serial2_pads),
+};
+
+static struct omap_board_data serial3_data __initdata = {
+        .id             = 2,
+        .pads           = serial3_pads,
+        .pads_cnt       = ARRAY_SIZE(serial3_pads),
+};
+
+static struct omap_board_data serial4_data __initdata = {
+        .id             = 3,
+        .pads           = serial4_pads,
+        .pads_cnt       = ARRAY_SIZE(serial4_pads),
+};
+
+static inline void board_serial_init(void)
+{
+        struct omap_board_data bdata;
+        bdata.flags     = 0;
+        bdata.pads      = NULL;
+        bdata.pads_cnt  = 0;
+        bdata.id        = 0;
+        /* pass dummy data for UART1 */
+        omap_serial_init_port(&bdata);
+
+        omap_serial_init_port(&serial2_data);
+        omap_serial_init_port(&serial3_data);
+        omap_serial_init_port(&serial4_data);
+}
+#else
+#define board_mux       NULL
+
+static inline void board_serial_init(void)
+{
+        omap_serial_init();
+}
+#endif
+
+/* Display DVI */
+#define PANDA_DVI_TFP410_POWER_DOWN_GPIO        0
+
+static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev)
+{
+        gpio_set_value(dssdev->reset_gpio, 1);
+        return 0;
+}
+
+static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev)
+{
+        gpio_set_value(dssdev->reset_gpio, 0);
+}
+
+/* Using generic display panel */
+static struct panel_generic_dpi_data omap4_dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = omap4_panda_enable_dvi,
+        .platform_disable       = omap4_panda_disable_dvi,
+};
+
+struct omap_dss_device omap4_panda_dvi_device = {
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .name                   = "dvi",
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &omap4_dvi_panel,
+        .phy.dpi.data_lines     = 24,
+        .reset_gpio             = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
+        .channel                = OMAP_DSS_CHANNEL_LCD2,
+};
+
+int __init omap4_panda_dvi_init(void)
+{
+        int r;
+
+        /* Requesting TFP410 DVI GPIO and disabling it, at bootup */
+        r = gpio_request_one(omap4_panda_dvi_device.reset_gpio,
+                                GPIOF_OUT_INIT_LOW, "DVI PD");
+        if (r)
+                pr_err("Failed to get DVI powerdown GPIO\n");
+
+        return r;
+}
+
+
+static void omap4_panda_hdmi_mux_init(void)
+{
+        /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+        omap_mux_init_signal("hdmi_hpd",
+                        OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_signal("hdmi_cec",
+                        OMAP_PIN_INPUT_PULLUP);
+        /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+        omap_mux_init_signal("hdmi_ddc_scl",
+                        OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_signal("hdmi_ddc_sda",
+                        OMAP_PIN_INPUT_PULLUP);
+}
+
+static struct gpio panda_hdmi_gpios[] = {
+        { HDMI_GPIO_HPD,        GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd"   },
+        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
+};
+
+static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
 {
         int status;
 
+        status = gpio_request_array(panda_hdmi_gpios,
+                                    ARRAY_SIZE(panda_hdmi_gpios));
+        if (status)
+                pr_err("Cannot request HDMI GPIOs\n");
+
+        return status;
+}
+
+static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev)
+{
+        gpio_free(HDMI_GPIO_LS_OE);
+        gpio_free(HDMI_GPIO_HPD);
+}
+
+static struct omap_dss_device  omap4_panda_hdmi_device = {
+        .name = "hdmi",
+        .driver_name = "hdmi_panel",
+        .type = OMAP_DISPLAY_TYPE_HDMI,
+        .platform_enable = omap4_panda_panel_enable_hdmi,
+        .platform_disable = omap4_panda_panel_disable_hdmi,
+        .channel = OMAP_DSS_CHANNEL_DIGIT,
+};
+
+static struct omap_dss_device *omap4_panda_dss_devices[] = {
+        &omap4_panda_dvi_device,
+        &omap4_panda_hdmi_device,
+};
+
+static struct omap_dss_board_info omap4_panda_dss_data = {
+        .num_devices    = ARRAY_SIZE(omap4_panda_dss_devices),
+        .devices        = omap4_panda_dss_devices,
+        .default_device = &omap4_panda_dvi_device,
+};
+
+void omap4_panda_display_init(void)
+{
+        int r;
+
+        r = omap4_panda_dvi_init();
+        if (r)
+                pr_err("error initializing panda DVI\n");
+
+        omap4_panda_hdmi_mux_init();
+        omap_display_init(&omap4_panda_dss_data);
+}
+
+static void __init omap4_panda_init(void)
+{
+        int package = OMAP_PACKAGE_CBS;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                package = OMAP_PACKAGE_CBL;
+        omap4_mux_init(board_mux, NULL, package);
+
+        if (wl12xx_set_platform_data(&omap_panda_wlan_data))
+                pr_err("error setting wl12xx data\n");
+
         omap4_panda_i2c_init();
-        omap_serial_init();
+        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
+        platform_device_register(&omap_vwlan_device);
+        board_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
-        /* OMAP4 Panda uses internal transceiver so register nop transceiver */
-        usb_nop_xceiv_register();
-        /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
-        if (!cpu_is_omap44xx())
-                usb_musb_init(&musb_board_data);
+        omap4_ehci_init();
+        usb_musb_init(&musb_board_data);
+        omap4_panda_display_init();
 }
 
 static void __init omap4_panda_map_io(void)
@@ -294,11 +710,11 @@ static void __init omap4_panda_map_io(void)
 
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         /* Maintainer: David Anders - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
         .map_io         = omap4_panda_map_io,
-        .init_irq       = omap4_panda_init_irq,
+        .init_early     = omap4_panda_init_early,
+        .init_irq       = gic_init_irq,
         .init_machine   = omap4_panda_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4c4843618350..175e1ab2b04d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -24,14 +24,18 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/spi/spi.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -40,15 +44,19 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <mach/gpio.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
 #include <plat/nand.h>
+#include <plat/mcspi.h>
+#include <plat/mux.h>
 #include <plat/usb.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
@@ -57,8 +65,6 @@
 #define OVERO_GPIO_USBH_CPEN    168
 #define OVERO_GPIO_USBH_NRESET  183
 
-#define NAND_BLOCK_SIZE SZ_128K
-
 #define OVERO_SMSC911X_CS      5
 #define OVERO_SMSC911X_GPIO    176
 #define OVERO_SMSC911X2_CS     4
@@ -67,56 +73,38 @@
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 
-#include <plat/mcspi.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
+/* fixed regulator for ads7846 */
+static struct regulator_consumer_supply ads7846_supply =
+        REGULATOR_SUPPLY("vcc", "spi1.0");
 
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
+static struct regulator_init_data vads7846_regulator = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &ads7846_supply,
 };
 
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OVERO_GPIO_PENDOWN);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
+static struct fixed_voltage_config vads7846 = {
+        .supply_name            = "vads7846",
+        .microvolts             = 3300000, /* 3.3V */
+        .gpio                   = -EINVAL,
+        .startup_delay          = 0,
+        .init_data              = &vads7846_regulator,
 };
 
-static struct spi_board_info overo_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN),
-                .platform_data          = &ads7846_config,
-        }
+static struct platform_device vads7846_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &vads7846,
+        },
 };
 
 static void __init overo_ads7846_init(void)
 {
-        if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) &&
-            (gpio_direction_input(OVERO_GPIO_PENDOWN) == 0)) {
-                gpio_export(OVERO_GPIO_PENDOWN, 0);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n");
-                return;
-        }
-
-        spi_register_board_info(overo_spi_board_info,
-                        ARRAY_SIZE(overo_spi_board_info));
+        omap_ads7846_init(1, OVERO_GPIO_PENDOWN, 0, NULL);
+        platform_device_register(&vads7846_device);
 }
 
 #else
@@ -126,112 +114,164 @@ static inline void __init overo_ads7846_init(void) { return; }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
+#include <plat/gpmc-smsc911x.h>
 
-static struct resource overo_smsc911x_resources[] = {
-        {
-                .name   = "smsc911x-memory",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .id             = 0,
+        .cs             = OVERO_SMSC911X_CS,
+        .gpio_irq       = OVERO_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT,
 };
 
-static struct resource overo_smsc911x2_resources[] = {
-        {
-                .name   = "smsc911x2-memory",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
+static struct omap_smsc911x_platform_data smsc911x2_cfg = {
+        .id             = 1,
+        .cs             = OVERO_SMSC911X2_CS,
+        .gpio_irq       = OVERO_SMSC911X2_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT,
 };
 
-static struct smsc911x_platform_config overo_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT ,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
+static void __init overo_init_smsc911x(void)
+{
+        gpmc_smsc911x_init(&smsc911x_cfg);
+        gpmc_smsc911x_init(&smsc911x2_cfg);
+}
 
-static struct platform_device overo_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(overo_smsc911x_resources),
-        .resource       = overo_smsc911x_resources,
-        .dev            = {
-                .platform_data = &overo_smsc911x_config,
-        },
-};
+#else
+static inline void __init overo_init_smsc911x(void) { return; }
+#endif
 
-static struct platform_device overo_smsc911x2_device = {
-        .name           = "smsc911x",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(overo_smsc911x2_resources),
-        .resource       = overo_smsc911x2_resources,
-        .dev            = {
-                .platform_data = &overo_smsc911x_config,
-        },
-};
+/* DSS */
+static int lcd_enabled;
+static int dvi_enabled;
+
+#define OVERO_GPIO_LCD_EN 144
+#define OVERO_GPIO_LCD_BL 145
 
-static struct platform_device *smsc911x_devices[] = {
-        &overo_smsc911x_device,
-        &overo_smsc911x2_device,
+static struct gpio overo_dss_gpios[] __initdata = {
+        { OVERO_GPIO_LCD_EN, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_EN" },
+        { OVERO_GPIO_LCD_BL, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_BL" },
 };
 
-static inline void __init overo_init_smsc911x(void)
+static void __init overo_display_init(void)
 {
-        unsigned long cs_mem_base, cs_mem_base2;
-
-        /* set up first smsc911x chip */
-
-        if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n");
+        if (gpio_request_array(overo_dss_gpios, ARRAY_SIZE(overo_dss_gpios))) {
+                printk(KERN_ERR "could not obtain DSS control GPIOs\n");
                 return;
         }
 
-        overo_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        overo_smsc911x_resources[0].end   = cs_mem_base + 0xff;
+        gpio_export(OVERO_GPIO_LCD_EN, 0);
+        gpio_export(OVERO_GPIO_LCD_BL, 0);
+}
 
-        if ((gpio_request(OVERO_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
-            (gpio_direction_input(OVERO_SMSC911X_GPIO) == 0)) {
-                gpio_export(OVERO_SMSC911X_GPIO, 0);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for SMSC911X IRQ\n");
-                return;
+static int overo_panel_enable_dvi(struct omap_dss_device *dssdev)
+{
+        if (lcd_enabled) {
+                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
+                return -EINVAL;
         }
+        dvi_enabled = 1;
 
-        overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO);
-        overo_smsc911x_resources[1].end   = 0;
+        return 0;
+}
 
-        /* set up second smsc911x chip */
+static void overo_panel_disable_dvi(struct omap_dss_device *dssdev)
+{
+        dvi_enabled = 0;
+}
 
-        if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) {
-                printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n");
-                return;
-        }
+static struct panel_generic_dpi_data dvi_panel = {
+        .name                   = "generic",
+        .platform_enable        = overo_panel_enable_dvi,
+        .platform_disable       = overo_panel_disable_dvi,
+};
 
-        overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0;
-        overo_smsc911x2_resources[0].end   = cs_mem_base2 + 0xff;
+static struct omap_dss_device overo_dvi_device = {
+        .name                   = "dvi",
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &dvi_panel,
+        .phy.dpi.data_lines     = 24,
+};
 
-        if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) &&
-            (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) {
-                gpio_export(OVERO_SMSC911X2_GPIO, 0);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n");
-                return;
+static struct omap_dss_device overo_tv_device = {
+        .name = "tv",
+        .driver_name = "venc",
+        .type = OMAP_DISPLAY_TYPE_VENC,
+        .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+};
+
+static int overo_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+        if (dvi_enabled) {
+                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
+                return -EINVAL;
         }
 
-        overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO);
-        overo_smsc911x2_resources[1].end   = 0;
+        gpio_set_value(OVERO_GPIO_LCD_EN, 1);
+        gpio_set_value(OVERO_GPIO_LCD_BL, 1);
+        lcd_enabled = 1;
+        return 0;
+}
 
-        platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices));
+static void overo_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+        gpio_set_value(OVERO_GPIO_LCD_EN, 0);
+        gpio_set_value(OVERO_GPIO_LCD_BL, 0);
+        lcd_enabled = 0;
 }
 
-#else
-static inline void __init overo_init_smsc911x(void) { return; }
+static struct panel_generic_dpi_data lcd43_panel = {
+        .name                   = "samsung_lte430wq_f0c",
+        .platform_enable        = overo_panel_enable_lcd,
+        .platform_disable       = overo_panel_disable_lcd,
+};
+
+static struct omap_dss_device overo_lcd43_device = {
+        .name                   = "lcd43",
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .driver_name            = "generic_dpi_panel",
+        .data                   = &lcd43_panel,
+        .phy.dpi.data_lines     = 24,
+};
+
+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \
+        defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE)
+static struct omap_dss_device overo_lcd35_device = {
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .name                   = "lcd35",
+        .driver_name            = "lgphilips_lb035q02_panel",
+        .phy.dpi.data_lines     = 24,
+        .platform_enable        = overo_panel_enable_lcd,
+        .platform_disable       = overo_panel_disable_lcd,
+};
 #endif
 
+static struct omap_dss_device *overo_dss_devices[] = {
+        &overo_dvi_device,
+        &overo_tv_device,
+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \
+        defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE)
+        &overo_lcd35_device,
+#endif
+        &overo_lcd43_device,
+};
+
+static struct omap_dss_board_info overo_dss_data = {
+        .num_devices    = ARRAY_SIZE(overo_dss_devices),
+        .devices        = overo_dss_devices,
+        .default_device = &overo_dvi_device,
+};
+
+static struct regulator_consumer_supply overo_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
+
+static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
+
 static struct mtd_partition overo_nand_partitions[] = {
         {
                 .name           = "xloader",
@@ -261,55 +301,16 @@ static struct mtd_partition overo_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data overo_nand_data = {
-        .parts = overo_nand_partitions,
-        .nr_parts = ARRAY_SIZE(overo_nand_partitions),
-        .dma_channel = -1,      /* disable DMA in OMAP NAND driver */
-};
-
-static void __init overo_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                overo_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&overo_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .transceiver    = true,
@@ -322,6 +323,93 @@ static struct regulator_consumer_supply overo_vmmc1_supply = {
         .supply                 = "vmmc",
 };
 
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "overo:red:gpio21",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 21,
+                .active_low             = true,
+        },
+        {
+                .name                   = "overo:blue:gpio22",
+                .default_trigger        = "none",
+                .gpio                   = 22,
+                .active_low             = true,
+        },
+        {
+                .name                   = "overo:blue:COM",
+                .default_trigger        = "mmc0",
+                .gpio                   = -EINVAL,      /* gets replaced */
+                .active_low             = true,
+        },
+};
+
+static struct gpio_led_platform_data gpio_leds_pdata = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device gpio_leds_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_leds_pdata,
+        },
+};
+
+static void __init overo_init_led(void)
+{
+        platform_device_register(&gpio_leds_device);
+}
+
+#else
+static inline void __init overo_init_led(void) { return; }
+#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button gpio_buttons[] = {
+        {
+                .code                   = BTN_0,
+                .gpio                   = 23,
+                .desc                   = "button0",
+                .wakeup                 = 1,
+        },
+        {
+                .code                   = BTN_1,
+                .gpio                   = 14,
+                .desc                   = "button1",
+                .wakeup                 = 1,
+        },
+};
+
+static struct gpio_keys_platform_data gpio_keys_pdata = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+
+static struct platform_device gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_keys_pdata,
+        },
+};
+
+static void __init overo_init_keys(void)
+{
+        platform_device_register(&gpio_keys_device);
+}
+
+#else
+static inline void __init overo_init_keys(void) { return; }
+#endif
+
 static int overo_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -329,6 +417,11 @@ static int overo_twl_gpio_setup(struct device *dev,
 
         overo_vmmc1_supply.dev = mmc[0].dev;
 
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+#endif
+
         return 0;
 }
 
@@ -336,6 +429,7 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
         .setup          = overo_twl_gpio_setup,
 };
 
@@ -357,17 +451,42 @@ static struct regulator_init_data overo_vmmc1 = {
         .consumer_supplies      = &overo_vmmc1_supply,
 };
 
-static struct twl4030_codec_audio_data overo_audio_data = {
-        .audio_mclk = 26000000,
+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+static struct regulator_init_data overo_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &overo_vdda_dac_supply,
 };
 
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data overo_vpll2 = {
+        .constraints = {
+                .name                   = "VDVI",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(overo_vdds_dsi_supply),
+        .consumer_supplies      = overo_vdds_dsi_supply,
+};
+
+static struct twl4030_codec_audio_data overo_audio_data;
+
 static struct twl4030_codec_data overo_codec_data = {
         .audio_mclk = 26000000,
         .audio = &overo_audio_data,
 };
 
-/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */
-
 static struct twl4030_platform_data overo_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -375,58 +494,50 @@ static struct twl4030_platform_data overo_twldata = {
         .usb            = &overo_usb_data,
         .codec          = &overo_codec_data,
         .vmmc1          = &overo_vmmc1,
-};
-
-static struct i2c_board_info __initdata overo_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65950", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &overo_twldata,
-        },
+        .vdac           = &overo_vdac,
+        .vpll2          = &overo_vpll2,
 };
 
 static int __init overo_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, overo_i2c_boardinfo,
-                        ARRAY_SIZE(overo_i2c_boardinfo));
+        omap3_pmic_init("tps65950", &overo_twldata);
         /* i2c2 pins are used for gpio */
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
 }
 
-static struct platform_device overo_lcd_device = {
-        .name           = "overo_lcd",
-        .id             = -1,
-};
-
-static struct omap_lcd_config overo_lcd_config __initdata = {
-        .ctrl_name      = "internal",
-};
-
-static struct omap_board_config_kernel overo_config[] __initdata = {
-        { OMAP_TAG_LCD,         &overo_lcd_config },
+static struct spi_board_info overo_spi_board_info[] __initdata = {
+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \
+        defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE)
+        {
+                .modalias               = "lgphilips_lb035q02_panel-spi",
+                .bus_num                = 1,
+                .chip_select            = 1,
+                .max_speed_hz           = 500000,
+                .mode                   = SPI_MODE_3,
+        },
+#endif
 };
 
-static void __init overo_init_irq(void)
+static int __init overo_spi_init(void)
 {
-        omap_board_config = overo_config;
-        omap_board_config_size = ARRAY_SIZE(overo_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
+        overo_ads7846_init();
+        spi_register_board_info(overo_spi_board_info,
+                        ARRAY_SIZE(overo_spi_board_info));
+        return 0;
 }
 
-static struct platform_device *overo_devices[] __initdata = {
-        &overo_lcd_device,
-};
-
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+static void __init overo_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
+}
 
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
         .phy_reset  = true,
         .reset_gpio_port[0]  = -EINVAL,
         .reset_gpio_port[1]  = OVERO_GPIO_USBH_NRESET,
@@ -437,35 +548,39 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
+static struct gpio overo_bt_gpios[] __initdata = {
+        { OVERO_GPIO_BT_XGATE,  GPIOF_OUT_INIT_LOW,     "lcd enable"    },
+        { OVERO_GPIO_BT_NRESET, GPIOF_OUT_INIT_HIGH,    "lcd bl enable" },
 };
 
 static void __init overo_init(void)
 {
+        int ret;
+
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         overo_i2c_init();
-        platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
+        omap_display_init(&overo_dss_data);
         omap_serial_init();
-        overo_flash_init();
-        usb_musb_init(&musb_board_data);
-        usb_ehci_init(&ehci_pdata);
+        omap_nand_flash_init(0, overo_nand_partitions,
+                             ARRAY_SIZE(overo_nand_partitions));
+        usb_musb_init(NULL);
+        usbhs_init(&usbhs_bdata);
+        overo_spi_init();
         overo_ads7846_init();
         overo_init_smsc911x();
+        overo_display_init();
+        overo_init_led();
+        overo_init_keys();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
         omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
-        if ((gpio_request(OVERO_GPIO_W2W_NRESET,
-                          "OVERO_GPIO_W2W_NRESET") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
+        ret = gpio_request_one(OVERO_GPIO_W2W_NRESET, GPIOF_OUT_INIT_HIGH,
+                               "OVERO_GPIO_W2W_NRESET");
+        if (ret == 0) {
                 gpio_export(OVERO_GPIO_W2W_NRESET, 0);
                 gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
                 udelay(10);
@@ -475,25 +590,20 @@ static void __init overo_init(void)
                                         "OVERO_GPIO_W2W_NRESET\n");
         }
 
-        if ((gpio_request(OVERO_GPIO_BT_XGATE, "OVERO_GPIO_BT_XGATE") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_BT_XGATE, 0) == 0))
+        ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
+        if (ret) {
+                pr_err("%s: could not obtain BT gpios\n", __func__);
+        } else {
                 gpio_export(OVERO_GPIO_BT_XGATE, 0);
-        else
-                printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_XGATE\n");
-
-        if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) {
                 gpio_export(OVERO_GPIO_BT_NRESET, 0);
                 gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
                 mdelay(6);
                 gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for "
-                                        "OVERO_GPIO_BT_NRESET\n");
         }
 
-        if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0))
+        ret = gpio_request_one(OVERO_GPIO_USBH_CPEN, GPIOF_OUT_INIT_HIGH,
+                               "OVERO_GPIO_USBH_CPEN");
+        if (ret == 0)
                 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
         else
                 printk(KERN_ERR "could not obtain gpio for "
@@ -501,12 +611,11 @@ static void __init overo_init(void)
 }
 
 MACHINE_START(OVERO, "Gumstix Overo")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = overo_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = overo_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = overo_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
new file mode 100644
index 000000000000..42d10b12da3c
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -0,0 +1,169 @@
+/*
+ * Board support file for Nokia RM-680.
+ *
+ * Copyright (C) 2010 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/i2c/twl.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/i2c.h>
+#include <plat/mmc.h>
+#include <plat/usb.h>
+#include <plat/gpmc.h>
+#include <plat/common.h>
+#include <plat/onenand.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "sdram-nokia.h"
+#include "common-board-devices.h"
+
+static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
+
+/* Fixed regulator for internal eMMC */
+static struct regulator_init_data rm680_vemmc = {
+        .constraints =  {
+                .name                   = "rm680_vemmc",
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS
+                                        | REGULATOR_CHANGE_MODE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(rm680_vemmc_consumers),
+        .consumer_supplies              = rm680_vemmc_consumers,
+};
+
+static struct fixed_voltage_config rm680_vemmc_config = {
+        .supply_name            = "VEMMC",
+        .microvolts             = 2900000,
+        .gpio                   = 157,
+        .startup_delay          = 150,
+        .enable_high            = 1,
+        .init_data              = &rm680_vemmc,
+};
+
+static struct platform_device rm680_vemmc_device = {
+        .name                   = "reg-fixed-voltage",
+        .dev                    = {
+                .platform_data  = &rm680_vemmc_config,
+        },
+};
+
+static struct platform_device *rm680_peripherals_devices[] __initdata = {
+        &rm680_vemmc_device,
+};
+
+/* TWL */
+static struct twl4030_gpio_platform_data rm680_gpio_data = {
+        .gpio_base              = OMAP_MAX_GPIO_LINES,
+        .irq_base               = TWL4030_GPIO_IRQ_BASE,
+        .irq_end                = TWL4030_GPIO_IRQ_END,
+        .pullups                = BIT(0),
+        .pulldowns              = BIT(1) | BIT(2) | BIT(8) | BIT(15),
+};
+
+static struct twl4030_usb_data rm680_usb_data = {
+        .usb_mode               = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_platform_data rm680_twl_data = {
+        .irq_base               = TWL4030_IRQ_BASE,
+        .irq_end                = TWL4030_IRQ_END,
+        .gpio                   = &rm680_gpio_data,
+        .usb                    = &rm680_usb_data,
+        /* add rest of the children here */
+};
+
+static void __init rm680_i2c_init(void)
+{
+        omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        omap_register_i2c_bus(3, 400, NULL, 0);
+}
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+static struct omap_onenand_platform_data board_onenand_data[] = {
+        {
+                .gpio_irq       = 65,
+                .flags          = ONENAND_SYNC_READWRITE,
+        }
+};
+#endif
+
+/* eMMC */
+static struct omap2_hsmmc_info mmc[] __initdata = {
+        {
+                .name           = "internal",
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        { /* Terminator */ }
+};
+
+static void __init rm680_peripherals_init(void)
+{
+        platform_add_devices(rm680_peripherals_devices,
+                                ARRAY_SIZE(rm680_peripherals_devices));
+        rm680_i2c_init();
+        gpmc_onenand_init(board_onenand_data);
+        omap2_hsmmc_init(mmc);
+}
+
+static void __init rm680_init_early(void)
+{
+        struct omap_sdrc_params *sdrc_params;
+
+        omap2_init_common_infrastructure();
+        sdrc_params = nokia_get_sdram_timings();
+        omap2_init_common_devices(sdrc_params, sdrc_params);
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#endif
+
+static void __init rm680_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+        usb_musb_init(NULL);
+        rm680_peripherals_init();
+}
+
+static void __init rm680_map_io(void)
+{
+        omap2_set_globals_3xxx();
+        omap34xx_map_common_io();
+}
+
+MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
+        .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
+        .map_io         = rm680_map_io,
+        .init_early     = rm680_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = rm680_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a5eb87425fc..88bd6f7705f0 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -14,7 +14,7 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/wl12xx.h>
+#include <linux/wl12xx.h>
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/clk.h>
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
+#include <linux/power/isp1704_charger.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
@@ -32,19 +33,28 @@
 #include <plat/onenand.h>
 #include <plat/gpmc-smc91x.h>
 
+#include <mach/board-rx51.h>
+
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
+#include <media/radio-si4713.h>
+#include <media/si4713.h>
 
 #include <../drivers/staging/iio/light/tsl2563.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define SYSTEM_REV_B_USES_VAUX3 0x1699
 #define SYSTEM_REV_S_USES_VAUX3 0x8
 
 #define RX51_WL1251_POWER_GPIO          87
 #define RX51_WL1251_IRQ_GPIO            42
+#define RX51_FMTX_RESET_GPIO            163
+#define RX51_FMTX_IRQ                   53
+
+#define RX51_USB_TRANSCEIVER_RST_GPIO   67
 
 /* list all spi devices here */
 enum {
@@ -104,6 +114,30 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
         },
 };
 
+static void rx51_charger_set_power(bool on)
+{
+        gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
+}
+
+static struct isp1704_charger_data rx51_charger_data = {
+        .set_power      = rx51_charger_set_power,
+};
+
+static struct platform_device rx51_charger_device = {
+        .name   = "isp1704_charger",
+        .dev    = {
+                .platform_data = &rx51_charger_data,
+        },
+};
+
+static void __init rx51_charger_init(void)
+{
+        WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
+                GPIOF_OUT_INIT_LOW, "isp1704_reset"));
+
+        platform_device_register(&rx51_charger_device);
+}
+
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 
 #define RX51_GPIO_CAMERA_LENS_COVER     110
@@ -184,7 +218,7 @@ static void __init rx51_add_gpio_keys(void)
 }
 #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         /*
          * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
          * connected to the ground" matrix state.
@@ -286,6 +320,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
+static struct omap_mux_partition *partition;
+
 /*
  * Current flows to eMMC when eMMC is off and the data lines are pulled up,
  * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
@@ -293,16 +329,16 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
 static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
 {
         if (power_on)
-                omap_mux_write_array(rx51_mmc2_on_mux);
+                omap_mux_write_array(partition, rx51_mmc2_on_mux);
         else
-                omap_mux_write_array(rx51_mmc2_off_mux);
+                omap_mux_write_array(partition, rx51_mmc2_off_mux);
 }
 
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "external",
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .cover_only     = true,
                 .gpio_cd        = 160,
                 .gpio_wp        = -EINVAL,
@@ -311,7 +347,8 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "internal",
                 .mmc            = 2,
-                .wires          = 8, /* See also rx51_mmc2_remux */
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                                                /* See also rx51_mmc2_remux */
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
@@ -322,41 +359,44 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
 };
 
 static struct regulator_consumer_supply rx51_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 static struct regulator_consumer_supply rx51_vaux3_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
 
 static struct regulator_consumer_supply rx51_vsim_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
 
 static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
         /* tlv320aic3x analog supplies */
         REGULATOR_SUPPLY("AVDD", "2-0018"),
         REGULATOR_SUPPLY("DRVDD", "2-0018"),
+        REGULATOR_SUPPLY("AVDD", "2-0019"),
+        REGULATOR_SUPPLY("DRVDD", "2-0019"),
         /* tpa6130a2 */
         REGULATOR_SUPPLY("Vdd", "2-0060"),
         /* Keep vmmc as last item. It is not iterated for newer boards */
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
 };
 
 static struct regulator_consumer_supply rx51_vio_supplies[] = {
         /* tlv320aic3x digital supplies */
         REGULATOR_SUPPLY("IOVDD", "2-0018"),
         REGULATOR_SUPPLY("DVDD", "2-0018"),
+        REGULATOR_SUPPLY("IOVDD", "2-0019"),
+        REGULATOR_SUPPLY("DVDD", "2-0019"),
+        /* Si4713 IO supply */
+        REGULATOR_SUPPLY("vio", "2-0063"),
 };
 
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-extern struct platform_device rx51_display_device;
-#endif
-
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-        {
-                .supply = "vdds_sdi",
-                .dev    = &rx51_display_device.dev,
-        },
-#endif
+        REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+        /* Si4713 supply */
+        REGULATOR_SUPPLY("vdd", "2-0063"),
+};
+
+static struct regulator_consumer_supply rx51_vdac_supply[] = {
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
 };
 
 static struct regulator_init_data rx51_vaux1 = {
@@ -448,6 +488,7 @@ static struct regulator_init_data rx51_vmmc2 = {
                 .name                   = "V28_A",
                 .min_uV                 = 2800000,
                 .max_uV                 = 3000000,
+                .always_on              = true, /* due VIO leak to AIC34 VDDs */
                 .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
@@ -476,14 +517,17 @@ static struct regulator_init_data rx51_vsim = {
 
 static struct regulator_init_data rx51_vdac = {
         .constraints = {
+                .name                   = "VDAC",
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
+                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = rx51_vdac_supply,
 };
 
 static struct regulator_init_data rx51_vio = {
@@ -500,13 +544,46 @@ static struct regulator_init_data rx51_vio = {
         .consumer_supplies      = rx51_vio_supplies,
 };
 
+static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
+        .gpio_reset     = RX51_FMTX_RESET_GPIO,
+};
+
+static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
+        I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
+        .platform_data  = &rx51_si4713_i2c_data,
+};
+
+static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
+        .i2c_bus        = 2,
+        .subdev_board_info = &rx51_si4713_board_info,
+};
+
+static struct platform_device rx51_si4713_dev = {
+        .name   = "radio-si4713",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &rx51_si4713_data,
+        },
+};
+
+static __init void rx51_init_si4713(void)
+{
+        int err;
+
+        err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
+        if (err) {
+                printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
+                return;
+        }
+        rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
+        platform_device_register(&rx51_si4713_dev);
+}
+
 static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 {
         /* FIXME this gpio setup is just a placeholder for now */
-        gpio_request(gpio + 6, "backlight_pwm");
-        gpio_direction_output(gpio + 6, 0);
-        gpio_request(gpio + 7, "speaker_en");
-        gpio_direction_output(gpio + 7, 1);
+        gpio_request_one(gpio + 6, GPIOF_OUT_INIT_LOW, "backlight_pwm");
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "speaker_en");
 
         return 0;
 }
@@ -676,7 +753,7 @@ static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
         { .resource = RES_RESET, .devgroup = -1,
           .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
         },
-        { .resource = RES_Main_Ref, .devgroup = -1,
+        { .resource = RES_MAIN_REF, .devgroup = -1,
           .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
         },
         { 0, 0},
@@ -688,7 +765,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
         .resource_config = twl4030_rconfig,
 };
 
+struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
+        .coexist        = 0,
+};
 
+struct twl4030_codec_data rx51_codec_data __initdata = {
+        .audio_mclk     = 26000000,
+        .vibra          = &rx51_vibra_data,
+};
 
 static struct twl4030_platform_data rx51_twldata __initdata = {
         .irq_base               = TWL4030_IRQ_BASE,
@@ -700,6 +784,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
         .madc                   = &rx51_madc_data,
         .usb                    = &rx51_usb_data,
         .power                  = &rx51_t2scripts_data,
+        .codec                  = &rx51_codec_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
@@ -710,22 +795,24 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
         .vio                    = &rx51_vio,
 };
 
-static struct aic3x_pdata rx51_aic3x_data __initdata = {
-        .gpio_reset             = 60,
-};
-
-static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = {
+static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
         .id                     = TPA6130A2,
         .power_gpio             = 98,
 };
 
-static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
-        {
-                I2C_BOARD_INFO("twl5030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &rx51_twldata,
-        },
+/* Audio setup data */
+static struct aic3x_setup_data rx51_aic34_setup = {
+        .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
+        .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
+};
+
+static struct aic3x_pdata rx51_aic3x_data = {
+        .setup = &rx51_aic34_setup,
+        .gpio_reset = 60,
+};
+
+static struct aic3x_pdata rx51_aic3x_data2 = {
+        .gpio_reset = 60,
 };
 
 static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
@@ -733,6 +820,10 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
                 .platform_data = &rx51_aic3x_data,
         },
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x19),
+                .platform_data = &rx51_aic3x_data2,
+        },
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
         {
                 I2C_BOARD_INFO("tsl2563", 0x29),
@@ -756,8 +847,7 @@ static int __init rx51_i2c_init(void)
                 rx51_twldata.vaux3 = &rx51_vaux3_cam;
         }
         rx51_twldata.vmmc2 = &rx51_vmmc2;
-        omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
-                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
+        omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
         omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                               ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -801,25 +891,15 @@ static struct mtd_partition onenand_partitions[] = {
         },
 };
 
-static struct omap_onenand_platform_data board_onenand_data = {
-        .cs             = 0,
-        .gpio_irq       = 65,
-        .parts          = onenand_partitions,
-        .nr_parts       = ARRAY_SIZE(onenand_partitions),
-        .flags          = ONENAND_SYNC_READWRITE,
+static struct omap_onenand_platform_data board_onenand_data[] = {
+        {
+                .cs             = 0,
+                .gpio_irq       = 65,
+                .parts          = onenand_partitions,
+                .nr_parts       = ARRAY_SIZE(onenand_partitions),
+                .flags          = ONENAND_SYNC_READWRITE,
+        }
 };
-
-static void __init board_onenand_init(void)
-{
-        gpmc_onenand_init(&board_onenand_data);
-}
-
-#else
-
-static inline void board_onenand_init(void)
-{
-}
-
 #endif
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@@ -854,26 +934,20 @@ static void rx51_wl1251_set_power(bool enable)
         gpio_set_value(RX51_WL1251_POWER_GPIO, enable);
 }
 
+static struct gpio rx51_wl1251_gpios[] __initdata = {
+        { RX51_WL1251_POWER_GPIO, GPIOF_OUT_INIT_LOW,   "wl1251 power"  },
+        { RX51_WL1251_IRQ_GPIO,   GPIOF_IN,             "wl1251 irq"    },
+};
+
 static void __init rx51_init_wl1251(void)
 {
         int irq, ret;
 
-        ret = gpio_request(RX51_WL1251_POWER_GPIO, "wl1251 power");
+        ret = gpio_request_array(rx51_wl1251_gpios,
+                                 ARRAY_SIZE(rx51_wl1251_gpios));
         if (ret < 0)
                 goto error;
 
-        ret = gpio_direction_output(RX51_WL1251_POWER_GPIO, 0);
-        if (ret < 0)
-                goto err_power;
-
-        ret = gpio_request(RX51_WL1251_IRQ_GPIO, "wl1251 irq");
-        if (ret < 0)
-                goto err_power;
-
-        ret = gpio_direction_input(RX51_WL1251_IRQ_GPIO);
-        if (ret < 0)
-                goto err_irq;
-
         irq = gpio_to_irq(RX51_WL1251_IRQ_GPIO);
         if (irq < 0)
                 goto err_irq;
@@ -885,10 +959,7 @@ static void __init rx51_init_wl1251(void)
 
 err_irq:
         gpio_free(RX51_WL1251_IRQ_GPIO);
-
-err_power:
         gpio_free(RX51_WL1251_POWER_GPIO);
-
 error:
         printk(KERN_ERR "wl1251 board initialisation failed\n");
         wl1251_pdata.set_power = NULL;
@@ -902,12 +973,18 @@ error:
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
-        board_onenand_init();
+        gpmc_onenand_init(board_onenand_data);
         board_smc91x_init();
         rx51_add_gpio_keys();
         rx51_init_wl1251();
+        rx51_init_si4713();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
-        omap2_hsmmc_init(mmc);
+
+        partition = omap_mux_get("core");
+        if (partition)
+                omap2_hsmmc_init(mmc);
+
+        rx51_charger_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 5a1005ba9815..2c1289bd5e6a 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -14,12 +14,13 @@
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/mm.h>
-
 #include <asm/mach-types.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/vram.h>
 #include <plat/mcspi.h>
 
+#include <mach/board-rx51.h>
+
 #include "mux.h"
 
 #define RX51_LCD_RESET_GPIO     90
@@ -47,8 +48,16 @@ static struct omap_dss_device rx51_lcd_device = {
         .platform_disable       = rx51_lcd_disable,
 };
 
+static struct omap_dss_device  rx51_tv_device = {
+        .name                   = "tv",
+        .type                   = OMAP_DISPLAY_TYPE_VENC,
+        .driver_name            = "venc",
+        .phy.venc.type          = OMAP_DSS_VENC_TYPE_COMPOSITE,
+};
+
 static struct omap_dss_device *rx51_dss_devices[] = {
         &rx51_lcd_device,
+        &rx51_tv_device,
 };
 
 static struct omap_dss_board_info rx51_dss_board_info = {
@@ -57,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
         .default_device = &rx51_lcd_device,
 };
 
-struct platform_device rx51_display_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &rx51_dss_board_info,
-        },
-};
-
-static struct platform_device *rx51_video_devices[] __initdata = {
-        &rx51_display_device,
-};
-
 static int __init rx51_video_init(void)
 {
         if (!machine_is_nokia_rx51())
@@ -79,15 +76,13 @@ static int __init rx51_video_init(void)
                 return 0;
         }
 
-        if (gpio_request(RX51_LCD_RESET_GPIO, "LCD ACX565AKM reset")) {
+        if (gpio_request_one(RX51_LCD_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
+                             "LCD ACX565AKM reset")) {
                 pr_err("%s failed to get LCD Reset GPIO\n", __func__);
                 return 0;
         }
 
-        gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
-
-        platform_add_devices(rx51_video_devices,
-                                ARRAY_SIZE(rx51_video_devices));
+        omap_display_init(&rx51_dss_board_info);
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index a58e8cb1a7fc..fec4cac8fa0a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -32,10 +32,10 @@
 
 #include "mux.h"
 #include "pm.h"
+#include "sdram-nokia.h"
 
 #define RX51_GPIO_SLEEP_IND 162
 
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
 extern void rx51_video_mem_init(void);
 
 static struct gpio_led gpio_leds[] = {
@@ -58,21 +58,25 @@ static struct platform_device leds_gpio = {
         },
 };
 
+/*
+ * cpuidle C-states definition override from the default values.
+ * The 'exit_latency' field is the sum of sleep and wake-up latencies.
+ */
 static struct cpuidle_params rx51_cpuidle_params[] = {
         /* C1 */
-        {1, 110, 162, 5},
+        {110 + 162, 5 , 1},
         /* C2 */
-        {1, 106, 180, 309},
+        {106 + 180, 309, 1},
         /* C3 */
-        {0, 107, 410, 46057},
+        {107 + 410, 46057, 0},
         /* C4 */
-        {0, 121, 3374, 46057},
+        {121 + 3374, 46057, 0},
         /* C5 */
-        {1, 855, 1146, 46057},
+        {855 + 1146, 46057, 1},
         /* C6 */
-        {0, 7580, 4134, 484329},
+        {7580 + 4134, 484329, 0},
         /* C7 */
-        {1, 7505, 15274, 484329},
+        {7505 + 15274, 484329, 1},
 };
 
 static struct omap_lcd_config rx51_lcd_config = {
@@ -98,17 +102,13 @@ static struct omap_board_config_kernel rx51_config[] = {
         { OMAP_TAG_LCD,         &rx51_lcd_config },
 };
 
-static void __init rx51_init_irq(void)
+static void __init rx51_init_early(void)
 {
         struct omap_sdrc_params *sdrc_params;
 
-        omap_board_config = rx51_config;
-        omap_board_config_size = ARRAY_SIZE(rx51_config);
-        omap3_pm_init_cpuidle(rx51_cpuidle_params);
-        sdrc_params = rx51_get_sdram_timings();
-        omap2_init_common_hw(sdrc_params, sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
+        omap2_init_common_infrastructure();
+        sdrc_params = nokia_get_sdram_timings();
+        omap2_init_common_devices(sdrc_params, sdrc_params);
 }
 
 extern void __init rx51_peripherals_init(void);
@@ -117,8 +117,6 @@ extern void __init rx51_peripherals_init(void);
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
@@ -130,6 +128,9 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init rx51_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = rx51_config;
+        omap_board_config_size = ARRAY_SIZE(rx51_config);
+        omap3_pm_init_cpuidle(rx51_cpuidle_params);
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         rx51_peripherals_init();
@@ -144,18 +145,22 @@ static void __init rx51_init(void)
 static void __init rx51_map_io(void)
 {
         omap2_set_globals_3xxx();
-        rx51_video_mem_init();
         omap34xx_map_common_io();
 }
 
+static void __init rx51_reserve(void)
+{
+        rx51_video_mem_init();
+        omap_reserve();
+}
+
 MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
+        .reserve        = rx51_reserve,
         .map_io         = rx51_map_io,
-        .reserve        = omap_reserve,
-        .init_irq       = rx51_init_irq,
+        .init_early     = rx51_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = rx51_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
new file mode 100644
index 000000000000..09fa7bfff8d6
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -0,0 +1,62 @@
+/*
+ * Code for TI8168 EVM.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/irqs.h>
+#include <plat/board.h>
+#include <plat/common.h>
+
+static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+};
+
+static void __init ti8168_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
+static void __init ti8168_evm_init_irq(void)
+{
+        omap_init_irq();
+}
+
+static void __init ti8168_evm_init(void)
+{
+        omap_serial_init();
+        omap_board_config = ti8168_evm_config;
+        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+}
+
+static void __init ti8168_evm_map_io(void)
+{
+        omap2_set_globals_ti816x();
+        omapti816x_map_common_io();
+}
+
+MACHINE_START(TI8168EVM, "ti8168evm")
+        /* Maintainer: Texas Instruments */
+        .boot_params    = 0x80000100,
+        .map_io         = ti8168_evm_map_io,
+        .init_early     = ti8168_init_early,
+        .init_irq       = ti8168_evm_init_irq,
+        .timer          = &omap_timer,
+        .init_machine   = ti8168_evm_init,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 1d7f827b0408..6402e781c458 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -15,6 +15,9 @@
 #include <linux/interrupt.h>
 
 #include <plat/gpmc.h>
+#include <plat/gpmc-smsc911x.h>
+
+#include <mach/board-zoom.h>
 
 #define ZOOM_SMSC911X_CS        7
 #define ZOOM_SMSC911X_GPIO      158
@@ -24,60 +27,16 @@
 #define DEBUG_BASE              0x08000000
 #define ZOOM_ETHR_START DEBUG_BASE
 
-static struct resource zoom_smsc911x_resources[] = {
-        [0] = {
-                .start  = ZOOM_ETHR_START,
-                .end    = ZOOM_ETHR_START + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct smsc911x_platform_config zoom_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+static struct omap_smsc911x_platform_data zoom_smsc911x_cfg = {
+        .cs             = ZOOM_SMSC911X_CS,
+        .gpio_irq       = ZOOM_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
         .flags          = SMSC911X_USE_32BIT,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device zoom_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(zoom_smsc911x_resources),
-        .resource       = zoom_smsc911x_resources,
-        .dev            = {
-                .platform_data = &zoom_smsc911x_config,
-        },
 };
 
 static inline void __init zoom_init_smsc911x(void)
 {
-        int eth_cs;
-        unsigned long cs_mem_base;
-        int eth_gpio = 0;
-
-        eth_cs = ZOOM_SMSC911X_CS;
-
-        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
-                return;
-        }
-
-        zoom_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        zoom_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-
-        eth_gpio = ZOOM_SMSC911X_GPIO;
-
-        zoom_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
-
-        if (gpio_request(eth_gpio, "smsc911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                                eth_gpio);
-                return;
-        }
-        gpio_direction_input(eth_gpio);
+        gpmc_smsc911x_init(&zoom_smsc911x_cfg);
 }
 
 static struct plat_serial8250_port serial_platform_data[] = {
@@ -118,12 +77,9 @@ static inline void __init zoom_init_quaduart(void)
 
         quart_gpio = ZOOM_QUADUART_GPIO;
 
-        if (gpio_request(quart_gpio, "TL16CP754C GPIO") < 0) {
+        if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
                 printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
                                                                 quart_gpio);
-                return;
-        }
-        gpio_direction_input(quart_gpio);
 }
 
 static inline int omap_zoom_debugboard_detect(void)
@@ -133,12 +89,12 @@ static inline int omap_zoom_debugboard_detect(void)
 
         debug_board_detect = ZOOM_SMSC911X_GPIO;
 
-        if (gpio_request(debug_board_detect, "Zoom debug board detect") < 0) {
+        if (gpio_request_one(debug_board_detect, GPIOF_IN,
+                             "Zoom debug board detect") < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
                 "board detect\n", debug_board_detect);
                 return 0;
         }
-        gpio_direction_input(debug_board_detect);
 
         if (!gpio_get_value(debug_board_detect)) {
                 ret = 0;
@@ -148,7 +104,6 @@ static inline int omap_zoom_debugboard_detect(void)
 }
 
 static struct platform_device *zoom_devices[] __initdata = {
-        &zoom_smsc911x_device,
         &zoom_debugboard_serial_device,
 };
 
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
new file mode 100644
index 000000000000..d4683ba5f721
--- /dev/null
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Inc.
+ *
+ * Modified from mach-omap2/board-zoom-peripherals.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c/twl.h>
+#include <linux/spi/spi.h>
+#include <plat/mcspi.h>
+#include <video/omapdss.h>
+
+#define LCD_PANEL_RESET_GPIO_PROD       96
+#define LCD_PANEL_RESET_GPIO_PILOT      55
+#define LCD_PANEL_QVGA_GPIO             56
+
+static struct gpio zoom_lcd_gpios[] __initdata = {
+        { -EINVAL,              GPIOF_OUT_INIT_HIGH, "lcd reset" },
+        { LCD_PANEL_QVGA_GPIO,  GPIOF_OUT_INIT_HIGH, "lcd qvga"  },
+};
+
+static void __init zoom_lcd_panel_init(void)
+{
+        zoom_lcd_gpios[0].gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
+                        LCD_PANEL_RESET_GPIO_PROD :
+                        LCD_PANEL_RESET_GPIO_PILOT;
+
+        if (gpio_request_array(zoom_lcd_gpios, ARRAY_SIZE(zoom_lcd_gpios)))
+                pr_err("%s: Failed to get LCD GPIOs.\n", __func__);
+}
+
+static int zoom_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+        return 0;
+}
+
+static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+}
+
+/*
+ * PWMA/B register offsets (TWL4030_MODULE_PWMA)
+ */
+#define TWL_INTBR_PMBR1 0xD
+#define TWL_INTBR_GPBR1 0xC
+#define TWL_LED_PWMON   0x0
+#define TWL_LED_PWMOFF  0x1
+
+static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
+{
+        unsigned char c;
+        u8 mux_pwm, enb_pwm;
+
+        if (level > 100)
+                return -1;
+
+        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &mux_pwm, TWL_INTBR_PMBR1);
+        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &enb_pwm, TWL_INTBR_GPBR1);
+
+        if (level == 0) {
+                /* disable pwm1 output and clock */
+                enb_pwm = enb_pwm & 0xF5;
+                /* change pwm1 pin to gpio pin */
+                mux_pwm = mux_pwm & 0xCF;
+                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
+                                        enb_pwm, TWL_INTBR_GPBR1);
+                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
+                                        mux_pwm, TWL_INTBR_PMBR1);
+                return 0;
+        }
+
+        if (!((enb_pwm & 0xA) && (mux_pwm & 0x30))) {
+                /* change gpio pin to pwm1 pin */
+                mux_pwm = mux_pwm | 0x30;
+                /* enable pwm1 output and clock*/
+                enb_pwm = enb_pwm | 0x0A;
+                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
+                                        mux_pwm, TWL_INTBR_PMBR1);
+                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
+                                        enb_pwm, TWL_INTBR_GPBR1);
+        }
+
+        c = ((50 * (100 - level)) / 100) + 1;
+        twl_i2c_write_u8(TWL4030_MODULE_PWM1, 0x7F, TWL_LED_PWMOFF);
+        twl_i2c_write_u8(TWL4030_MODULE_PWM1, c, TWL_LED_PWMON);
+
+        return 0;
+}
+
+static struct omap_dss_device zoom_lcd_device = {
+        .name                   = "lcd",
+        .driver_name            = "NEC_8048_panel",
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .phy.dpi.data_lines     = 24,
+        .platform_enable        = zoom_panel_enable_lcd,
+        .platform_disable       = zoom_panel_disable_lcd,
+        .max_backlight_level    = 100,
+        .set_backlight          = zoom_set_bl_intensity,
+};
+
+static struct omap_dss_device *zoom_dss_devices[] = {
+        &zoom_lcd_device,
+};
+
+static struct omap_dss_board_info zoom_dss_data = {
+        .num_devices            = ARRAY_SIZE(zoom_dss_devices),
+        .devices                = zoom_dss_devices,
+        .default_device         = &zoom_lcd_device,
+};
+
+static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
+        .turbo_mode             = 1,
+        .single_channel = 1,  /* 0: slave, 1: master */
+};
+
+static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
+        [0] = {
+                .modalias               = "nec_8048_spi",
+                .bus_num                = 1,
+                .chip_select            = 2,
+                .max_speed_hz           = 375000,
+                .controller_data        = &dss_lcd_mcspi_config,
+        },
+};
+
+void __init zoom_display_init(void)
+{
+        omap_display_init(&zoom_dss_data);
+        spi_register_board_info(nec_8048_spi_board_info,
+                                ARRAY_SIZE(nec_8048_spi_board_info));
+        zoom_lcd_panel_init();
+}
+
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 6b3984964cc5..118c6f53c5eb 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -16,6 +16,9 @@
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/wl12xx.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -24,11 +27,19 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 
+#include <mach/board-zoom.h>
+
 #include "mux.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
+
+#define OMAP_ZOOM_WLAN_PMENA_GPIO       (101)
+#define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
+
+#define LCD_PANEL_ENABLE_GPIO           (7 + OMAP_MAX_GPIO_LINES)
 
 /* Zoom2 has Qwerty keyboard*/
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_E),
         KEY(0, 1, KEY_R),
         KEY(0, 2, KEY_T),
@@ -106,6 +117,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
         .supply         = "vmmc",
 };
 
+static struct regulator_consumer_supply zoom_vmmc3_supply = {
+        .supply         = "vmmc",
+        .dev_name       = "omap_hsmmc.2",
+};
+
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data zoom_vmmc1 = {
         .constraints = {
@@ -151,29 +167,105 @@ static struct regulator_init_data zoom_vsim = {
         .consumer_supplies      = &zoom_vsim_supply,
 };
 
-static struct omap2_hsmmc_info mmc[] __initdata = {
+static struct regulator_init_data zoom_vmmc3 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies = &zoom_vmmc3_supply,
+};
+
+static struct fixed_voltage_config zoom_vwlan = {
+        .supply_name            = "vwl1271",
+        .microvolts             = 1800000, /* 1.8V */
+        .gpio                   = OMAP_ZOOM_WLAN_PMENA_GPIO,
+        .startup_delay          = 70000, /* 70msec */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &zoom_vmmc3,
+};
+
+static struct platform_device omap_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &zoom_vwlan,
+        },
+};
+
+static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
+        .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
+        /* ZOOM ref clock is 26 MHz */
+        .board_ref_clock = 1,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
         {
                 .name           = "external",
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_wp        = -EINVAL,
                 .power_saving   = true,
         },
         {
                 .name           = "internal",
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
                 .power_saving   = true,
         },
+        {
+                .name           = "wl1271",
+                .mmc            = 3,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .nonremovable   = true,
+        },
         {}      /* Terminator */
 };
 
+static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
+
+static struct regulator_consumer_supply zoom_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
+
+static struct regulator_init_data zoom_vpll2 = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(zoom_vpll2_supplies),
+        .consumer_supplies              = zoom_vpll2_supplies,
+};
+
+static struct regulator_init_data zoom_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies          = 1,
+        .consumer_supplies              = &zoom_vdda_dac_supply,
+};
+
 static int zoom_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int ret;
+
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
@@ -185,9 +277,20 @@ static int zoom_twl_gpio_setup(struct device *dev,
         zoom_vsim_supply.dev = mmc[0].dev;
         zoom_vmmc2_supply.dev = mmc[1].dev;
 
-        return 0;
+        ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
+                               "lcd enable");
+        if (ret)
+                pr_err("Failed to get LCD_PANEL_ENABLE_GPIO (gpio%d).\n",
+                                LCD_PANEL_ENABLE_GPIO);
+
+        return ret;
 }
 
+/* EXTMUTE callback function */
+static void zoom2_set_hs_extmute(int mute)
+{
+        gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
+}
 
 static int zoom_batt_table[] = {
 /* 0 C*/
@@ -220,9 +323,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = {
         .irq_line       = 1,
 };
 
-static struct twl4030_codec_audio_data zoom_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data zoom_audio_data;
 
 static struct twl4030_codec_data zoom_codec_data = {
         .audio_mclk = 26000000,
@@ -243,33 +344,23 @@ static struct twl4030_platform_data zoom_twldata = {
         .vmmc1          = &zoom_vmmc1,
         .vmmc2          = &zoom_vmmc2,
         .vsim           = &zoom_vsim,
-
-};
-
-static struct i2c_board_info __initdata zoom_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl5030", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &zoom_twldata,
-        },
+        .vpll2          = &zoom_vpll2,
+        .vdac           = &zoom_vdac,
 };
 
 static int __init omap_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2400, zoom_i2c_boardinfo,
-                        ARRAY_SIZE(zoom_i2c_boardinfo));
+        if (machine_is_omap_zoom2()) {
+                zoom_audio_data.ramp_delay_value = 3;   /* 161 ms */
+                zoom_audio_data.hs_extmute = 1;
+                zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
+        }
+        omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
 }
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void enable_board_wakeup_source(void)
 {
         /* T2 interrupt line (keypad) */
@@ -279,7 +370,12 @@ static void enable_board_wakeup_source(void)
 
 void __init zoom_peripherals_init(void)
 {
+        if (wl12xx_set_platform_data(&omap_zoom_wlan_data))
+                pr_err("error setting wl12xx data\n");
+
         omap_i2c_init();
-        usb_musb_init(&musb_board_data);
+        platform_device_register(&omap_vwlan_device);
+        usb_musb_init(NULL);
         enable_board_wakeup_source();
+        omap_serial_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom.c
index 6ca0b8341615..4b133d75c935 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -1,6 +1,9 @@
 /*
- * Copyright (C) 2009 Texas Instruments Inc.
+ * Copyright (C) 2009-2010 Texas Instruments Inc.
+ * Mikkel Christensen <mlc@ti.com>
+ * Felipe Balbi <balbi@ti.com>
  *
+ * Modified from mach-omap2/board-ldp.c
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,21 +15,54 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/i2c/twl.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board-zoom.h>
-
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/usb.h>
 
+#include <mach/board-zoom.h>
+
+#include "board-flash.h"
 #include "mux.h"
+#include "sdram-micron-mt46h32m32lf-6.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
-static struct omap_board_config_kernel zoom_config[] __initdata = {
+#define ZOOM3_EHCI_RESET_GPIO           64
+
+static void __init omap_zoom_init_early(void)
+{
+        omap2_init_common_infrastructure();
+        if (machine_is_omap_zoom2())
+                omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                          mt46h32m32lf6_sdrc_params);
+        else if (machine_is_omap_zoom3())
+                omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+                                          h8mbx00u0mer0em_sdrc_params);
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        /* WLAN IRQ - GPIO 162 */
+        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* WLAN POWER ENABLE - GPIO 101 */
+        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* WLAN SDIO: MMC3 CMD */
+        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC3 CLK */
+        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC3 DAT[0-3] */
+        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+#endif
 
 static struct mtd_partition zoom_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
@@ -69,66 +105,49 @@ static struct mtd_partition zoom_nand_partitions[] = {
         },
 };
 
-static void __init omap_zoom_init_irq(void)
-{
-        omap_board_config = zoom_config;
-        omap_board_config_size = ARRAY_SIZE(zoom_config);
-        omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
-                        h8mbx00u0mer0em_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* WLAN IRQ - GPIO 162 */
-        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN POWER ENABLE - GPIO 101 */
-        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* WLAN SDIO: MMC3 CMD */
-        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 CLK */
-        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 DAT[0-3] */
-        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
-#endif
-
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0]           = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[1]           = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[2]           = EHCI_HCD_OMAP_MODE_UNKNOWN,
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+        .port_mode[0]           = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1]           = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2]           = OMAP_USBHS_PORT_MODE_UNUSED,
         .phy_reset              = true,
         .reset_gpio_port[0]     = -EINVAL,
-        .reset_gpio_port[1]     = 64,
+        .reset_gpio_port[1]     = ZOOM3_EHCI_RESET_GPIO,
         .reset_gpio_port[2]     = -EINVAL,
 };
 
 static void __init omap_zoom_init(void)
 {
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        zoom_peripherals_init();
-        board_nand_init(zoom_nand_partitions,
-                         ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
-        zoom_debugboard_init();
+        if (machine_is_omap_zoom2()) {
+                omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        } else if (machine_is_omap_zoom3()) {
+                omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+                omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+                usbhs_init(&usbhs_bdata);
+        }
 
-        omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
-        usb_ehci_init(&ehci_pdata);
+        board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
+                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+        zoom_debugboard_init();
+        zoom_peripherals_init();
+        zoom_display_init();
 }
 
-MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
-        .phys_io        = ZOOM_UART_BASE,
-        .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
+MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
         .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
+        .init_early     = omap_zoom_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = omap_zoom_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
+        .boot_params    = 0x80000100,
         .reserve        = omap_reserve,
-        .init_irq       = omap_zoom_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_zoom_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_zoom_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
deleted file mode 100644
index 3ad9ecf7f5e2..000000000000
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Inc.
- * Mikkel Christensen <mlc@ti.com>
- *
- * Modified from mach-omap2/board-ldp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <plat/common.h>
-#include <plat/board.h>
-
-#include <mach/board-zoom.h>
-
-#include "mux.h"
-#include "sdram-micron-mt46h32m32lf-6.h"
-
-static void __init omap_zoom2_init_irq(void)
-{
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                                 mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
-/* REVISIT: These audio entries can be removed once MFD code is merged */
-#if 0
-
-static struct twl4030_madc_platform_data zoom2_madc_data = {
-        .irq_line       = 1,
-};
-
-static struct twl4030_codec_audio_data zoom2_audio_data = {
-        .audio_mclk = 26000000,
-};
-
-static struct twl4030_codec_data zoom2_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &zoom2_audio_data,
-};
-
-static struct twl4030_platform_data zoom2_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
-        /* platform_data for children goes here */
-        .bci            = &zoom2_bci_data,
-        .madc           = &zoom2_madc_data,
-        .usb            = &zoom2_usb_data,
-        .gpio           = &zoom2_gpio_data,
-        .keypad         = &zoom2_kp_twl4030_data,
-        .codec          = &zoom2_codec_data,
-        .vmmc1          = &zoom2_vmmc1,
-        .vmmc2          = &zoom2_vmmc2,
-        .vsim           = &zoom2_vsim,
-
-};
-
-#endif
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* WLAN IRQ - GPIO 162 */
-        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN POWER ENABLE - GPIO 101 */
-        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* WLAN SDIO: MMC3 CMD */
-        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 CLK */
-        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 DAT[0-3] */
-        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
-#endif
-
-static struct mtd_partition zoom_nand_partitions[] = {
-        /* All the partition sizes are listed in terms of NAND block size */
-        {
-                .name           = "X-Loader-NAND",
-                .offset         = 0,
-                .size           = 4 * (64 * 2048),      /* 512KB, 0x80000 */
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
-                .size           = 10 * (64 * 2048),     /* 1.25MB, 0x140000 */
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "Boot Env-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
-                .size           = 2 * (64 * 2048),      /* 256KB, 0x40000 */
-        },
-        {
-                .name           = "Kernel-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x0200000*/
-                .size           = 240 * (64 * 2048),    /* 30M, 0x1E00000 */
-        },
-        {
-                .name           = "system",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2000000 */
-                .size           = 3328 * (64 * 2048),   /* 416M, 0x1A000000 */
-        },
-        {
-                .name           = "userdata",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1C000000*/
-                .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
-        },
-        {
-                .name           = "cache",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1E000000*/
-                .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
-        },
-};
-
-static void __init omap_zoom2_init(void)
-{
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        zoom_peripherals_init();
-        board_nand_init(zoom_nand_partitions,
-                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
-        zoom_debugboard_init();
-}
-
-MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
-        .phys_io        = ZOOM_UART_BASE,
-        .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
-        .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
-        .reserve        = omap_reserve,
-        .init_irq       = omap_zoom2_init_irq,
-        .init_machine   = omap_zoom2_init,
-        .timer          = &omap_timer,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 66e01acfd585..b19a1f7234ae 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -26,7 +26,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
 
         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
         if ((cval & apll_mask) == apll_mask)
                 return 0;   /* apll already enabled */
 
         cval &= ~apll_mask;
         cval |= apll_mask;
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
         omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
                              OMAP24XX_CM_IDLEST_VAL, clk->name);
@@ -78,14 +78,34 @@ static int omap2_clk_apll54_enable(struct clk *clk)
         return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
 }
 
+static void _apll96_allow_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll96_auto_low_power_stop();
+}
+
+static void _apll96_deny_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll96_disable_autoidle();
+}
+
+static void _apll54_allow_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll54_auto_low_power_stop();
+}
+
+static void _apll54_deny_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll54_disable_autoidle();
+}
+
 /* Stop APLL */
 static void omap2_clk_apll_disable(struct clk *clk)
 {
         u32 cval;
 
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 }
 
 /* Public data */
@@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
 const struct clkops clkops_apll96 = {
         .enable         = omap2_clk_apll96_enable,
         .disable        = omap2_clk_apll_disable,
+        .allow_idle     = _apll96_allow_idle,
+        .deny_idle      = _apll96_deny_idle,
 };
 
 const struct clkops clkops_apll54 = {
         .enable         = omap2_clk_apll54_enable,
         .disable        = omap2_clk_apll_disable,
+        .allow_idle     = _apll54_allow_idle,
+        .deny_idle      = _apll54_deny_idle,
 };
 
 /* Public functions */
@@ -106,7 +130,7 @@ u32 omap2xxx_get_apll_clkin(void)
 {
         u32 aplls, srate = 0;
 
-        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
new file mode 100644
index 000000000000..1502a7bc20bb
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -0,0 +1,63 @@
+/*
+ * OMAP2-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+
+/* Private functions */
+
+/**
+ * _allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control.  The DPLL will enter low-power
+ * stop when its downstream clocks are gated.  No return value.
+ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
+ * instead.  Add some mechanism to optionally enter this mode.
+ */
+static void _allow_idle(struct clk *clk)
+{
+        if (!clk || !clk->dpll_data)
+                return;
+
+        omap2xxx_cm_set_dpll_auto_low_power_stop();
+}
+
+/**
+ * _deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control.  No return value.
+ */
+static void _deny_idle(struct clk *clk)
+{
+        if (!clk || !clk->dpll_data)
+                return;
+
+        omap2xxx_cm_set_dpll_disable_autoidle();
+}
+
+
+/* Public data */
+
+const struct clkops clkops_omap2xxx_dpll_ops = {
+        .allow_idle     = _allow_idle,
+        .deny_idle      = _deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 019048434f13..4ae439222085 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -32,7 +32,7 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
 
         core_clk = omap2_get_dpll_rate(clk);
 
-        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         v &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if (v == CORE_CLK_SRC_32K)
@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
-        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
         const struct dpll_data *dd;
 
         cur_rate = omap2xxx_clk_get_core_rate(dclk);
-        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if ((rate == (cur_rate / 2)) && (mult == 2)) {
@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
                                            dd->div1_mask);
                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
                 if (rate > low) {
                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 2167be84a5bc..c3460928b5e0 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -27,9 +27,16 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 
+/*
+ * XXX This does not actually enable the osc_ck, since the osc_ck must
+ * be running for this function to be called.  Instead, this function
+ * is used to disable an autoidle mode on the osc_ck.  The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
 static int omap2_enable_osc_ck(struct clk *clk)
 {
         u32 pcc;
@@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
         return 0;
 }
 
+/*
+ * XXX This does not actually disable the osc_ck, since doing so would
+ * immediately halt the system.  Instead, this function is used to
+ * enable an autoidle mode on the osc_ck.  The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
 static void omap2_disable_osc_ck(struct clk *clk)
 {
         u32 pcc;
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index 822b5a79f457..8693cfdac49a 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -26,7 +26,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 
 void __iomem *prcm_clksrc_ctrl;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index aef62918aaf0..39f9d5a58d0c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -40,7 +40,7 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 const struct prcm_config *curr_prcm_set;
@@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
                         done_rate = CORE_CLK_SRC_DPLL;
 
                 /* MPU divider */
-                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+                omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 
                 /* dsp + iva1 div(2420), iva2.1(2430) */
-                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 
-                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+                omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 
                 /* Major subsystem dividers */
-                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
                                  CM_CLKSEL1);
 
                 if (cpu_is_omap2430())
-                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                        omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 
                 /* x2 to enter omap2xxx_sdrc_init_params() */
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index b2b1e37bb6bb..d6e34dd9e7e7 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   0, 0, 0, 0);
+        clk->rate = rate;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index a781cd6795a4..e25364de028a 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
                                 u32 *field_val)
 {
         const struct clksel *clks;
-        const struct clksel_rate *clkr, *max_clkr;
+        const struct clksel_rate *clkr, *max_clkr = NULL;
         u8 max_div = 0;
 
         clks = _get_clksel_by_parent(clk, src_clk);
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 6ce512e902c6..bcffee001bfa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -24,7 +24,6 @@
 #include <plat/clock.h>
 
 #include "clock.h"
-#include "cm.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
@@ -78,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
         dd = clk->dpll_data;
 
         /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / (n + 1);
+        fint = clk->parent->rate / n;
         if (fint < DPLL_FINT_BAND1_MIN) {
 
                 pr_debug("rejecting n=%d due to Fint failure, "
@@ -179,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
         if (!dd)
                 return;
 
-        /* Return bypass rate if DPLL is bypassed */
         v = __raw_readl(dd->control_reg);
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
-        /* Reparent in case the dpll is in bypass */
+        /* Reparent the struct clk in case the dpll is in bypass */
         if (cpu_is_omap24xx()) {
                 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP2XXX_EN_DPLL_FRBYPASS)
@@ -261,50 +259,22 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 /* DPLL rate rounding code */
 
 /**
- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
- * @clk: struct clk * of the DPLL
- * @tolerance: maximum rate error tolerance
- *
- * Set the maximum DPLL rate error tolerance for the rate rounding
- * algorithm.  The rate tolerance is an attempt to balance DPLL power
- * saving (the least divider value "n") vs. rate fidelity (the least
- * difference between the desired DPLL target rate and the rounded
- * rate out of the algorithm).  So, increasing the tolerance is likely
- * to decrease DPLL power consumption and increase DPLL rate error.
- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
- * DPLL; or 0 upon success.
- */
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
-{
-        if (!clk || !clk->dpll_data)
-                return -EINVAL;
-
-        clk->dpll_data->rate_tolerance = tolerance;
-
-        return 0;
-}
-
-/**
  * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
  * @clk: struct clk * for a DPLL
  * @target_rate: desired DPLL clock rate
  *
- * Given a DPLL, a desired target rate, and a rate tolerance, round
- * the target rate to a possible, programmable rate for this DPLL.
- * Rate tolerance is assumed to be set by the caller before this
- * function is called.  Attempts to select the minimum possible n
- * within the tolerance to reduce power consumption.  Stores the
- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
- * will not need to call this (expensive) function again.  Returns ~0
- * if the target rate cannot be rounded, either because the rate is
- * too low or because the rate tolerance is set too tightly; or the
- * rounded rate upon success.
+ * Given a DPLL and a desired target rate, round the target rate to a
+ * possible, programmable rate for this DPLL.  Attempts to select the
+ * minimum possible n.  Stores the computed (m, n) in the DPLL's
+ * dpll_data structure so set_rate() will not need to call this
+ * (expensive) function again.  Returns ~0 if the target rate cannot
+ * be rounded, or the rounded rate upon success.
  */
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 {
-        int m, n, r, e, scaled_max_m;
-        unsigned long scaled_rt_rp, new_rate;
-        int min_e = -1, min_e_m = -1, min_e_n = -1;
+        int m, n, r, scaled_max_m;
+        unsigned long scaled_rt_rp;
+        unsigned long new_rate = 0;
         struct dpll_data *dd;
 
         if (!clk || !clk->dpll_data)
@@ -312,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 
         dd = clk->dpll_data;
 
-        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
-                 "%ld\n", clk->name, target_rate);
+        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
+                 clk->name, target_rate);
 
         scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
         scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
@@ -348,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                 if (r == DPLL_MULT_UNDERFLOW)
                         continue;
 
-                e = target_rate - new_rate;
-                pr_debug("clock: n = %d: m = %d: rate error is %d "
-                         "(new_rate = %ld)\n", n, m, e, new_rate);
-
-                if (min_e == -1 ||
-                    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
-                        min_e = e;
-                        min_e_m = m;
-                        min_e_n = n;
-
-                        pr_debug("clock: found new least error %d\n", min_e);
+                pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
+                         clk->name, m, n, new_rate);
 
-                        /* We found good settings -- bail out now */
-                        if (min_e <= dd->rate_tolerance)
-                                break;
+                if (target_rate == new_rate) {
+                        dd->last_rounded_m = m;
+                        dd->last_rounded_n = n;
+                        dd->last_rounded_rate = target_rate;
+                        break;
                 }
         }
 
-        if (min_e < 0) {
-                pr_debug("clock: error: target rate or tolerance too low\n");
+        if (target_rate != new_rate) {
+                pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
+                         target_rate);
                 return ~0;
         }
 
-        dd->last_rounded_m = min_e_m;
-        dd->last_rounded_n = min_e_n;
-        dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
-                                                       min_e_m,  min_e_n);
-
-        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
-                 min_e, min_e_m, min_e_n);
-        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
-                 dd->last_rounded_rate, target_rate);
-
-        return dd->last_rounded_rate;
+        return target_rate;
 }
 
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
new file mode 100644
index 000000000000..3d43fba2542f
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -0,0 +1,82 @@
+/*
+ * OMAP2/3 interface clock control
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/prcm.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+
+/* Private functions */
+
+/* XXX */
+void omap2_clkt_iclk_allow_idle(struct clk *clk)
+{
+        u32 v, r;
+
+        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+
+        v = __raw_readl((__force void __iomem *)r);
+        v |= (1 << clk->enable_bit);
+        __raw_writel(v, (__force void __iomem *)r);
+}
+
+/* XXX */
+void omap2_clkt_iclk_deny_idle(struct clk *clk)
+{
+        u32 v, r;
+
+        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+
+        v = __raw_readl((__force void __iomem *)r);
+        v &= ~(1 << clk->enable_bit);
+        __raw_writel(v, (__force void __iomem *)r);
+}
+
+/* Public data */
+
+const struct clkops clkops_omap2_iclk_dflt_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_iclk_dflt = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_iclk_idle_only = {
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_mdmclk_dflt_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 605f531783a8..180299e4a838 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,16 +22,16 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <trace/events/power.h>
 
+#include <asm/cpu.h>
 #include <plat/clock.h>
-#include <plat/clockdomain.h>
+#include "clockdomain.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
 
 #include "clock.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
@@ -263,10 +263,13 @@ void omap2_clk_disable(struct clk *clk)
 
         pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
-        clk->ops->disable(clk);
+        if (clk->ops && clk->ops->disable) {
+                trace_clock_disable(clk->name, 0, smp_processor_id());
+                clk->ops->disable(clk);
+        }
 
         if (clk->clkdm)
-                omap2_clkdm_clk_disable(clk->clkdm, clk);
+                clkdm_clk_disable(clk->clkdm, clk);
 
         if (clk->parent)
                 omap2_clk_disable(clk->parent);
@@ -306,7 +309,7 @@ int omap2_clk_enable(struct clk *clk)
         }
 
         if (clk->clkdm) {
-                ret = omap2_clkdm_clk_enable(clk->clkdm, clk);
+                ret = clkdm_clk_enable(clk->clkdm, clk);
                 if (ret) {
                         WARN(1, "clock: %s: could not enable clockdomain %s: "
                              "%d\n", clk->name, clk->clkdm->name, ret);
@@ -314,17 +317,21 @@ int omap2_clk_enable(struct clk *clk)
                 }
         }
 
-        ret = clk->ops->enable(clk);
-        if (ret) {
-                WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
-                goto oce_err3;
+        if (clk->ops && clk->ops->enable) {
+                trace_clock_enable(clk->name, 1, smp_processor_id());
+                ret = clk->ops->enable(clk);
+                if (ret) {
+                        WARN(1, "clock: %s: could not enable: %d\n",
+                             clk->name, ret);
+                        goto oce_err3;
+                }
         }
 
         return 0;
 
 oce_err3:
         if (clk->clkdm)
-                omap2_clkdm_clk_disable(clk->clkdm, clk);
+                clkdm_clk_disable(clk->clkdm, clk);
 oce_err2:
         if (clk->parent)
                 omap2_clk_disable(clk->parent);
@@ -351,8 +358,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
         /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
-        if (clk->set_rate)
+        if (clk->set_rate) {
+                trace_clock_set_rate(clk->name, rate, smp_processor_id());
                 ret = clk->set_rate(clk, rate);
+        }
 
         return ret;
 }
@@ -375,10 +384,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 const struct clkops clkops_omap3_noncore_dpll_ops = {
         .enable         = omap3_noncore_dpll_enable,
         .disable        = omap3_noncore_dpll_disable,
+        .allow_idle     = omap3_dpll_allow_idle,
+        .deny_idle      = omap3_dpll_deny_idle,
 };
 
-#endif
+const struct clkops clkops_omap3_core_dpll_ops = {
+        .allow_idle     = omap3_dpll_allow_idle,
+        .deny_idle      = omap3_dpll_deny_idle,
+};
 
+#endif
 
 /*
  * OMAP2+ clock reset and init functions
@@ -395,7 +410,7 @@ void omap2_clk_disable_unused(struct clk *clk)
         if ((regval32 & (1 << clk->enable_bit)) == v)
                 return;
 
-        printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
+        pr_debug("Disabling unused clock \"%s\"\n", clk->name);
         if (cpu_is_omap34xx()) {
                 omap2_clk_enable(clk);
                 omap2_clk_disable(clk);
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a535c7a2a62a..e10ff2b54844 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mach-omap2/clock.h
  *
  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2009 Nokia Corporation
+ *  Copyright (C) 2004-2011 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -18,9 +18,6 @@
 
 #include <plat/clock.h>
 
-/* The maximum error between a target DPLL rate and the rounded rate in Hz */
-#define DEFAULT_DPLL_RATE_TOLERANCE     50000
-
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
 #define CORE_CLK_SRC_32K                0x0
 #define CORE_CLK_SRC_DPLL               0x1
@@ -49,14 +46,12 @@
 
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE             0x1
-#define DPLL_NO_DCO_SEL         0x2
 
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
 unsigned long omap3_dpll_recalc(struct clk *clk);
 unsigned long omap3_clkoutx2_recalc(struct clk *clk);
@@ -66,6 +61,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 int omap3_noncore_dpll_enable(struct clk *clk);
 void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
@@ -84,6 +82,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
 
+/* clkt_iclk.c public functions */
+extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
+extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
+
 u32 omap2_get_dpll_rate(struct clk *clk);
 void omap2_init_dpll_parent(struct clk *clk);
 
@@ -137,6 +139,7 @@ extern struct clk *vclk, *sclk;
 extern const struct clksel_rate gpt_32k_rates[];
 extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
+extern const struct clksel_rate dsp_ick_rates[];
 
 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
 extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
@@ -146,6 +149,13 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 #define omap2_clk_exit_cpufreq_table    0
 #endif
 
+extern const struct clkops clkops_omap2_iclk_dflt_wait;
+extern const struct clkops clkops_omap2_iclk_dflt;
+extern const struct clkops clkops_omap2_iclk_idle_only;
+extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
+extern const struct clkops clkops_omap2xxx_dpll_ops;
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
+extern const struct clkops clkops_omap3_core_dpll_ops;
+extern const struct clkops clkops_omap4_dpllmx_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 37d65d62ed8f..2926d028b6e9 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1,12 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap2/clock2420_data.c
+ * OMAP2420 clock data
  *
- *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2010 Nokia Corporation
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
  *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -22,29 +22,27 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
 
 /*
  * 2420 clock tree.
  *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
  *
  *      Several sources are given initial rates which may be wrong, this will
  *      be fixed up in the init func.
  *
  *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
+ *      noteworthy that most peripherals have dependencies on multiple clock
  *      domains. Many get their interface clocks from the L4 domain, but get
  *      functional clocks from fixed sources or other core domain derived
  *      clocks.
@@ -54,7 +52,7 @@
 static struct clk func_32k_ck = {
         .name           = "func_32k_ck",
         .ops            = &clkops_null,
-        .rate           = 32000,
+        .rate           = 32768,
         .clkdm_name     = "wkup_clkdm",
 };
 
@@ -89,6 +87,12 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
         .clkdm_name     = "wkup_clkdm",
 };
 
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
 /*
  * Analog domain root source clocks
  */
@@ -109,7 +113,6 @@ static struct dpll_data dpll_dd = {
         .max_multiplier         = 1023,
         .min_divider            = 1,
         .max_divider            = 16,
-        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 /*
@@ -118,7 +121,7 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2xxx_dpll_ops,
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
         .clkdm_name     = "wkup_clkdm",
@@ -448,36 +451,22 @@ static struct clk dsp_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DSP interface clock */
-static const struct clksel_rate dsp_irate_ick_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-
-static const struct clksel dsp_irate_ick_clksel[] = {
-        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
         { .parent = NULL }
 };
 
-/* This clock does not exist as such in the TRM. */
-static struct clk dsp_irate_ick = {
-        .name           = "dsp_irate_ick",
-        .ops            = &clkops_null,
-        .parent         = &dsp_fck,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
-        .clksel         = dsp_irate_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* 2420 only */
 static struct clk dsp_ick = {
         .name           = "dsp_ick",     /* apparently ipi and isp */
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dsp_irate_ick,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &dsp_fck,
+        .clkdm_name     = "dsp_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 /*
@@ -572,7 +561,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
         .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -654,7 +643,7 @@ static struct clk ssi_ssr_sst_fck = {
  */
 static struct clk ssi_l4_ick = {
         .name           = "ssi_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -709,6 +698,7 @@ static struct clk gfx_2d_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk gfx_ick = {
         .name           = "gfx_ick",            /* From l3 */
         .ops            = &clkops_omap2_dflt_wait,
@@ -756,7 +746,7 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
         .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,       /* really both l3 and l4 */
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -805,7 +795,7 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
         .clksel         = dss2_fck_clksel,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
@@ -818,6 +808,14 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
         .recalc         = &followparent_recalc,
 };
 
+static struct clk wu_l4_ick = {
+        .name           = "wu_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /*
  * CORE power domain ICLK & FCLK defines.
  * Many of the these can have more than one possible parent. Entries
@@ -838,9 +836,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -864,7 +862,7 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -888,7 +886,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -912,7 +910,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -936,7 +934,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -960,7 +958,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -984,8 +982,9 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1007,7 +1006,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1031,7 +1030,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1055,7 +1054,7 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1079,7 +1078,7 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1103,7 +1102,7 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1127,7 +1126,7 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1135,19 +1134,39 @@ static struct clk mcbsp1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1159,15 +1178,19 @@ static struct clk mcbsp2_fck = {
         .name           = "mcbsp2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1187,7 +1210,7 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1207,7 +1230,7 @@ static struct clk mcspi2_fck = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1227,7 +1250,7 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1247,7 +1270,7 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1267,9 +1290,9 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
         .name           = "gpios_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1287,9 +1310,9 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
         .name           = "mpu_wdt_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1307,10 +1330,10 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
         .name           = "sync_32k_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1318,9 +1341,9 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1328,10 +1351,10 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1339,7 +1362,7 @@ static struct clk omapctrl_ick = {
 
 static struct clk cam_ick = {
         .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1364,7 +1387,7 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1374,7 +1397,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
         .name           = "wdt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1394,7 +1417,7 @@ static struct clk wdt4_fck = {
 
 static struct clk wdt3_ick = {
         .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1414,7 +1437,7 @@ static struct clk wdt3_fck = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1434,7 +1457,7 @@ static struct clk mspro_fck = {
 
 static struct clk mmc_ick = {
         .name           = "mmc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1454,7 +1477,7 @@ static struct clk mmc_fck = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1474,7 +1497,7 @@ static struct clk fac_fck = {
 
 static struct clk eac_ick = {
         .name           = "eac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1494,7 +1517,7 @@ static struct clk eac_fck = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1514,7 +1537,7 @@ static struct clk hdq_fck = {
 
 static struct clk i2c2_ick = {
         .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1534,7 +1557,7 @@ static struct clk i2c2_fck = {
 
 static struct clk i2c1_ick = {
         .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1552,12 +1575,18 @@ static struct clk i2c1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk gpmc_fck = {
         .name           = "gpmc_fck",
-        .ops            = &clkops_null, /* RMK: missing? */
+        .ops            = &clkops_omap2_iclk_idle_only,
         .parent         = &core_l3_ck,
         .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
@@ -1569,17 +1598,38 @@ static struct clk sdma_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk sdma_ick = {
         .name           = "sdma_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk vlynq_ick = {
         .name           = "vlynq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1628,7 +1678,7 @@ static struct clk vlynq_fck = {
 
 static struct clk des_ick = {
         .name           = "des_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1638,7 +1688,7 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
         .name           = "sha_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1648,7 +1698,7 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1658,7 +1708,7 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
         .name           = "aes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1668,7 +1718,7 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1721,6 +1771,9 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
@@ -1728,6 +1781,8 @@ static struct omap_clk omap2420_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
@@ -1741,7 +1796,6 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
         /* dsp domain clocks */
         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
-        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_242X),
         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
@@ -1750,10 +1804,10 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
         /* DSS domain clocks */
-        CLK("omapdss",  "ick",          &dss_ick,       CK_242X),
-        CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_242X),
-        CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_242X),
-        CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_242X),
+        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK("omapdss_dss",      "fck",          &dss1_fck,      CK_242X),
+        CLK("omapdss_dss",      "sys_clk",      &dss2_fck,      CK_242X),
+        CLK("omapdss_dss",      "tv_clk",       &dss_54m_fck,   CK_242X),
         /* L3 domain clocks */
         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
@@ -1761,6 +1815,7 @@ static struct omap_clk omap2420_clks[] = {
         /* L4 domain clocks */
         CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
         /* virtual meta-group clock */
         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
         /* general l4 interface ck, multi-parent functional clk */
@@ -1826,22 +1881,23 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_242X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_242X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_242X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_242X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_242X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
-        CLK("musb_hdrc",        "fck",  &osc_ck,        CK_242X),
+        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
 };
 
 /*
@@ -1877,6 +1933,9 @@ int __init omap2420_clk_init(void)
                 omap2_init_clk_clkdm(c->lk.clk);
         }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         /* Check the MPU rate set by bootloader */
         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index 44d0cccc51a9..d87bc9cb2a36 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -25,7 +25,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 /**
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index b33118fb6a87..0c79d39e3021 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1,12 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap2/clock2430_data.c
+ * OMAP2430 clock data
  *
- *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2010 Nokia Corporation
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
  *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -22,29 +22,27 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
 
 /*
  * 2430 clock tree.
  *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
  *
  *      Several sources are given initial rates which may be wrong, this will
  *      be fixed up in the init func.
  *
  *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
+ *      noteworthy that most peripherals have dependencies on multiple clock
  *      domains. Many get their interface clocks from the L4 domain, but get
  *      functional clocks from fixed sources or other core domain derived
  *      clocks.
@@ -54,7 +52,7 @@
 static struct clk func_32k_ck = {
         .name           = "func_32k_ck",
         .ops            = &clkops_null,
-        .rate           = 32000,
+        .rate           = 32768,
         .clkdm_name     = "wkup_clkdm",
 };
 
@@ -89,6 +87,12 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
         .clkdm_name     = "wkup_clkdm",
 };
 
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
 /*
  * Analog domain root source clocks
  */
@@ -109,7 +113,6 @@ static struct dpll_data dpll_dd = {
         .max_multiplier         = 1023,
         .min_divider            = 1,
         .max_divider            = 16,
-        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 /*
@@ -118,7 +121,7 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2xxx_dpll_ops,
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
         .clkdm_name     = "wkup_clkdm",
@@ -427,37 +430,23 @@ static struct clk dsp_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DSP interface clock */
-static const struct clksel_rate dsp_irate_ick_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_243X },
-        { .div = 0 },
-};
-
-static const struct clksel dsp_irate_ick_clksel[] = {
-        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
         { .parent = NULL }
 };
 
-/* This clock does not exist as such in the TRM. */
-static struct clk dsp_irate_ick = {
-        .name           = "dsp_irate_ick",
-        .ops            = &clkops_null,
-        .parent         = &dsp_fck,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
-        .clksel         = dsp_irate_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
 static struct clk iva2_1_ick = {
         .name           = "iva2_1_ick",
         .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dsp_irate_ick,
+        .parent         = &dsp_fck,
+        .clkdm_name     = "dsp_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 /*
@@ -518,7 +507,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
         .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -599,7 +588,7 @@ static struct clk ssi_ssr_sst_fck = {
  */
 static struct clk ssi_l4_ick = {
         .name           = "ssi_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -654,6 +643,7 @@ static struct clk gfx_2d_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk gfx_ick = {
         .name           = "gfx_ick",            /* From l3 */
         .ops            = &clkops_omap2_dflt_wait,
@@ -686,7 +676,7 @@ static const struct clksel mdm_ick_clksel[] = {
 
 static struct clk mdm_ick = {           /* used both as a ick and fck */
         .name           = "mdm_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_ck,
         .clkdm_name     = "mdm_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -699,7 +689,7 @@ static struct clk mdm_ick = {		/* used both as a ick and fck */
 
 static struct clk mdm_osc_ck = {
         .name           = "mdm_osc_ck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_mdmclk_dflt_wait,
         .parent         = &osc_ck,
         .clkdm_name     = "mdm_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -744,7 +734,7 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
         .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,       /* really both l3 and l4 */
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -793,7 +783,7 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
         .clksel         = dss2_fck_clksel,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
@@ -806,6 +796,14 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
         .recalc         = &followparent_recalc,
 };
 
+static struct clk wu_l4_ick = {
+        .name           = "wu_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /*
  * CORE power domain ICLK & FCLK defines.
  * Many of the these can have more than one possible parent. Entries
@@ -826,9 +824,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -852,7 +850,7 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -876,7 +874,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -900,7 +898,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -924,7 +922,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -948,7 +946,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -972,8 +970,9 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
         .recalc         = &followparent_recalc,
@@ -995,7 +994,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1019,7 +1018,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1043,7 +1042,7 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1067,7 +1066,7 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1091,7 +1090,7 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1115,7 +1114,7 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1123,19 +1122,39 @@ static struct clk mcbsp1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1147,15 +1166,19 @@ static struct clk mcbsp2_fck = {
         .name           = "mcbsp2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp3_ick = {
         .name           = "mcbsp3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1167,15 +1190,19 @@ static struct clk mcbsp3_fck = {
         .name           = "mcbsp3_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp4_ick = {
         .name           = "mcbsp4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1187,15 +1214,19 @@ static struct clk mcbsp4_fck = {
         .name           = "mcbsp4_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp5_ick = {
         .name           = "mcbsp5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1207,15 +1238,19 @@ static struct clk mcbsp5_fck = {
         .name           = "mcbsp5_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1235,7 +1270,7 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1255,7 +1290,7 @@ static struct clk mcspi2_fck = {
 
 static struct clk mcspi3_ick = {
         .name           = "mcspi3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1275,7 +1310,7 @@ static struct clk mcspi3_fck = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1295,7 +1330,7 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1315,7 +1350,7 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1335,9 +1370,9 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
         .name           = "gpios_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1355,9 +1390,9 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
         .name           = "mpu_wdt_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1375,10 +1410,10 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
         .name           = "sync_32k_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1386,9 +1421,9 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1396,10 +1431,10 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1407,9 +1442,9 @@ static struct clk omapctrl_ick = {
 
 static struct clk icr_ick = {
         .name           = "icr_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1417,7 +1452,7 @@ static struct clk icr_ick = {
 
 static struct clk cam_ick = {
         .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1442,7 +1477,7 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1452,7 +1487,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
         .name           = "wdt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1472,7 +1507,7 @@ static struct clk wdt4_fck = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1492,7 +1527,7 @@ static struct clk mspro_fck = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1512,7 +1547,7 @@ static struct clk fac_fck = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1536,7 +1571,7 @@ static struct clk hdq_fck = {
  */
 static struct clk i2c2_ick = {
         .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1560,7 +1595,7 @@ static struct clk i2chs2_fck = {
  */
 static struct clk i2c1_ick = {
         .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1578,12 +1613,18 @@ static struct clk i2chs1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk gpmc_fck = {
         .name           = "gpmc_fck",
-        .ops            = &clkops_null, /* RMK: missing? */
+        .ops            = &clkops_omap2_iclk_idle_only,
         .parent         = &core_l3_ck,
         .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
@@ -1595,20 +1636,26 @@ static struct clk sdma_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk sdma_ick = {
         .name           = "sdma_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sdrc_ick = {
         .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
+        .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1616,7 +1663,7 @@ static struct clk sdrc_ick = {
 
 static struct clk des_ick = {
         .name           = "des_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1626,7 +1673,7 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
         .name           = "sha_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1636,7 +1683,7 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1646,7 +1693,7 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
         .name           = "aes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1656,7 +1703,7 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1676,7 +1723,7 @@ static struct clk usb_fck = {
 
 static struct clk usbhs_ick = {
         .name           = "usbhs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1686,7 +1733,7 @@ static struct clk usbhs_ick = {
 
 static struct clk mmchs1_ick = {
         .name           = "mmchs1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1698,7 +1745,7 @@ static struct clk mmchs1_fck = {
         .name           = "mmchs1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l3_clkdm",
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1706,7 +1753,7 @@ static struct clk mmchs1_fck = {
 
 static struct clk mmchs2_ick = {
         .name           = "mmchs2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1718,6 +1765,7 @@ static struct clk mmchs2_fck = {
         .name           = "mmchs2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1725,7 +1773,7 @@ static struct clk mmchs2_fck = {
 
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1745,7 +1793,7 @@ static struct clk gpio5_fck = {
 
 static struct clk mdm_intc_ick = {
         .name           = "mdm_intc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1808,6 +1856,12 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
@@ -1815,6 +1869,11 @@ static struct omap_clk omap2430_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
@@ -1826,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
         /* dsp domain clocks */
         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
-        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X),
         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
         /* GFX domain clocks */
         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
@@ -1836,10 +1894,10 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
         /* DSS domain clocks */
-        CLK("omapdss",  "ick",          &dss_ick,       CK_243X),
-        CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X),
-        CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X),
-        CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X),
+        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK("omapdss_dss",      "fck",          &dss1_fck,      CK_243X),
+        CLK("omapdss_dss",      "sys_clk",      &dss2_fck,      CK_243X),
+        CLK("omapdss_dss",      "tv_clk",       &dss_54m_fck,   CK_243X),
         /* L3 domain clocks */
         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
@@ -1847,6 +1905,7 @@ static struct omap_clk omap2430_clks[] = {
         /* L4 domain clocks */
         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
         /* virtual meta-group clock */
         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
         /* general l4 interface ck, multi-parent functional clk */
@@ -1915,10 +1974,10 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X),
-        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X),
-        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK("omap_i2c.1", "fck",        &i2chs1_fck,    CK_243X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK("omap_i2c.2", "fck",        &i2chs2_fck,    CK_243X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
@@ -1926,19 +1985,19 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
-        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
-        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
-        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
-        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
-        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
+        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK("omap_hsmmc.0", "fck",      &mmchs1_fck,    CK_243X),
+        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK("omap_hsmmc.1", "fck",      &mmchs2_fck,    CK_243X),
         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
-        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
+        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
 };
 
 /*
@@ -1974,6 +2033,9 @@ int __init omap2430_clk_init(void)
                 omap2_init_clk_clkdm(c->lk.clk);
         }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         /* Check the MPU rate set by bootloader */
         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 6a658b890c17..cb6df8ca9e4a 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -20,16 +20,16 @@ u32 omap2xxx_get_apll_clkin(void);
 u32 omap2xxx_get_sysclkdiv(void);
 void omap2xxx_clk_prepare_for_reboot(void);
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 int omap2420_clk_init(void);
 #else
-#define omap2420_clk_init()     0
+#define omap2420_clk_init()     do { } while(0)
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 int omap2430_clk_init(void);
 #else
-#define omap2430_clk_init()     0
+#define omap2430_clk_init()     do { } while(0)
 #endif
 
 extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6febd5f11e85..1fc96b9ee330 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley
  * Jouni Högander
@@ -25,7 +25,7 @@
 
 #include "clock.h"
 #include "clock34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /**
@@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
         .find_companion = omap2_clk_dflt_find_companion,
 };
 
+const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
 /**
  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  * @clk: struct clk * being enabled
@@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
         .find_companion = omap2_clk_dflt_find_companion,
 };
 
+const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
 /**
  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  * @clk: struct clk * being enabled
@@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
         .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
         .find_companion = omap2_clk_dflt_find_companion,
 };
+
+const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 628e8de57680..084ba71b2b31 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2,14 +2,17 @@
  * OMAP34xx clock function prototypes and macros
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 
 extern const struct clkops clkops_omap3430es2_ssi_wait;
+extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
 extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
+extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
+extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index b496a9305e1c..2e97d08f0e56 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -2,7 +2,7 @@
  * OMAP3517/3505-specific clock framework functions
  *
  * Copyright (C) 2010 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Nokia Corporation
  *
  * Ranjith Lohithakshan
  * Paul Walmsley
@@ -25,7 +25,7 @@
 
 #include "clock.h"
 #include "clock3517.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
@@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
         .disable        = omap2_dflt_clk_disable,
         .find_idlest    = am35xx_clk_ipss_find_idlest,
         .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
 };
 
 
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index a447c4d2c28a..952c3e01c9eb 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -25,9 +25,9 @@
 
 #include "clock.h"
 #include "clock3xxx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
         clk_enable(dpll5_clk);
 
-        /* Enable autoidle to allow it to enter low power bypass */
-        omap3_dpll_allow_idle(dpll5_clk);
-
         /* Program dpll5_m2_clk divider for no division */
         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
         clk_enable(dpll5_m2_clk);
@@ -94,7 +91,7 @@ static int __init omap3xxx_clk_arch_init(void)
 
         ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
         if (!ret)
-                omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck");
+                omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
 
         return ret;
 }
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index dfdce2d82779..75b119bd9cda 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2,7 +2,7 @@
  * OMAP3 clock data
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
  * With many device clock fixes by Kevin Hilman and Jouni Högander
@@ -20,7 +20,6 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/control.h>
 #include <plat/clkdev_omap.h>
 
 #include "clock.h"
@@ -29,10 +28,11 @@
 #include "clock36xx.h"
 #include "clock3517.h"
 
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
+#include "control.h"
 
 /*
  * clocks
@@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = {
 };
 
 static const struct clksel_rate osc_sys_16_8m_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
         { .div = 0 }
 };
 
@@ -291,12 +291,11 @@ static struct dpll_data dpll1_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll1_ck = {
         .name           = "dpll1_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll1_dd,
         .round_rate     = &omap2_dpll_round_rate,
@@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll2_ck = {
@@ -424,12 +422,11 @@ static struct dpll_data dpll3_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll3_ck = {
         .name           = "dpll3_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap3_core_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll3_dd,
         .round_rate     = &omap2_dpll_round_rate,
@@ -452,35 +449,35 @@ static struct clk dpll3_x2_ck = {
 static const struct clksel_rate div31_dpll3_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
         { .div = 0 },
 };
 
@@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct dpll_data dpll4_dd_3630 __initdata = {
@@ -602,10 +598,11 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
+        .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
         .flags          = DPLL_J_TYPE
 };
 
@@ -937,7 +934,6 @@ static struct dpll_data dpll5_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll5_ck = {
@@ -1203,7 +1199,10 @@ static const struct clksel gfx_l3_clksel[] = {
         { .parent = NULL }
 };
 
-/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
+/*
+ * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
+ * This interface clock does not have a CM_AUTOIDLE bit
+ */
 static struct clk gfx_l3_ck = {
         .name           = "gfx_l3_ck",
         .ops            = &clkops_omap2_dflt_wait,
@@ -1302,6 +1301,7 @@ static struct clk sgx_fck = {
         .round_rate     = &omap2_clksel_round_rate
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk sgx_ick = {
         .name           = "sgx_ick",
         .ops            = &clkops_omap2_dflt_wait,
@@ -1326,7 +1326,7 @@ static struct clk d2d_26m_fck = {
 
 static struct clk modem_fck = {
         .name           = "modem_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_mdmclk_dflt_wait,
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
@@ -1336,7 +1336,7 @@ static struct clk modem_fck = {
 
 static struct clk sad2d_ick = {
         .name           = "sad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
@@ -1346,7 +1346,7 @@ static struct clk sad2d_ick = {
 
 static struct clk mad2d_ick = {
         .name           = "mad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
@@ -1558,6 +1558,7 @@ static struct clk mcspi4_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk mcspi3_fck = {
@@ -1567,6 +1568,7 @@ static struct clk mcspi3_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk mcspi2_fck = {
@@ -1576,6 +1578,7 @@ static struct clk mcspi2_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk mcspi1_fck = {
@@ -1585,6 +1588,7 @@ static struct clk mcspi1_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk uart2_fck = {
@@ -1712,7 +1716,7 @@ static struct clk core_l3_ick = {
 
 static struct clk hsotgusb_ick_3430es1 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1722,7 +1726,7 @@ static struct clk hsotgusb_ick_3430es1 = {
 
 static struct clk hsotgusb_ick_3430es2 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap3430es2_hsotgusb_wait,
+        .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1730,6 +1734,7 @@ static struct clk hsotgusb_ick_3430es2 = {
         .recalc         = &followparent_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk sdrc_ick = {
         .name           = "sdrc_ick",
         .ops            = &clkops_omap2_dflt_wait,
@@ -1761,7 +1766,7 @@ static struct clk security_l3_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
@@ -1780,7 +1785,7 @@ static struct clk core_l4_ick = {
 
 static struct clk usbtll_ick = {
         .name           = "usbtll_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1790,7 +1795,7 @@ static struct clk usbtll_ick = {
 
 static struct clk mmchs3_ick = {
         .name           = "mmchs3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1801,7 +1806,7 @@ static struct clk mmchs3_ick = {
 /* Intersystem Communication Registers - chassis mode only */
 static struct clk icr_ick = {
         .name           = "icr_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
@@ -1811,7 +1816,7 @@ static struct clk icr_ick = {
 
 static struct clk aes2_ick = {
         .name           = "aes2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
@@ -1821,7 +1826,7 @@ static struct clk aes2_ick = {
 
 static struct clk sha12_ick = {
         .name           = "sha12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
@@ -1831,7 +1836,7 @@ static struct clk sha12_ick = {
 
 static struct clk des2_ick = {
         .name           = "des2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
@@ -1841,7 +1846,7 @@ static struct clk des2_ick = {
 
 static struct clk mmchs2_ick = {
         .name           = "mmchs2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
@@ -1851,7 +1856,7 @@ static struct clk mmchs2_ick = {
 
 static struct clk mmchs1_ick = {
         .name           = "mmchs1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
@@ -1861,7 +1866,7 @@ static struct clk mmchs1_ick = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
@@ -1871,7 +1876,7 @@ static struct clk mspro_ick = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
@@ -1881,7 +1886,7 @@ static struct clk hdq_ick = {
 
 static struct clk mcspi4_ick = {
         .name           = "mcspi4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1891,7 +1896,7 @@ static struct clk mcspi4_ick = {
 
 static struct clk mcspi3_ick = {
         .name           = "mcspi3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1901,7 +1906,7 @@ static struct clk mcspi3_ick = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1911,7 +1916,7 @@ static struct clk mcspi2_ick = {
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1921,7 +1926,7 @@ static struct clk mcspi1_ick = {
 
 static struct clk i2c3_ick = {
         .name           = "i2c3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
@@ -1931,7 +1936,7 @@ static struct clk i2c3_ick = {
 
 static struct clk i2c2_ick = {
         .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
@@ -1941,7 +1946,7 @@ static struct clk i2c2_ick = {
 
 static struct clk i2c1_ick = {
         .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
@@ -1951,7 +1956,7 @@ static struct clk i2c1_ick = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
@@ -1961,7 +1966,7 @@ static struct clk uart2_ick = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
@@ -1971,7 +1976,7 @@ static struct clk uart1_ick = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
@@ -1981,7 +1986,7 @@ static struct clk gpt11_ick = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
@@ -1991,7 +1996,7 @@ static struct clk gpt10_ick = {
 
 static struct clk mcbsp5_ick = {
         .name           = "mcbsp5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2001,7 +2006,7 @@ static struct clk mcbsp5_ick = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2011,7 +2016,7 @@ static struct clk mcbsp1_ick = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
@@ -2021,7 +2026,7 @@ static struct clk fac_ick = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -2031,7 +2036,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -2051,7 +2056,7 @@ static struct clk ssi_l4_ick = {
 
 static struct clk ssi_ick_3430es1 = {
         .name           = "ssi_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &ssi_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
@@ -2061,7 +2066,7 @@ static struct clk ssi_ick_3430es1 = {
 
 static struct clk ssi_ick_3430es2 = {
         .name           = "ssi_ick",
-        .ops            = &clkops_omap3430es2_ssi_wait,
+        .ops            = &clkops_omap3430es2_iclk_ssi_wait,
         .parent         = &ssi_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
@@ -2079,7 +2084,7 @@ static const struct clksel usb_l4_clksel[] = {
 
 static struct clk usb_l4_ick = {
         .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2101,7 +2106,7 @@ static struct clk security_l4_ick2 = {
 
 static struct clk aes1_ick = {
         .name           = "aes1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
@@ -2110,7 +2115,7 @@ static struct clk aes1_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
@@ -2119,7 +2124,7 @@ static struct clk rng_ick = {
 
 static struct clk sha11_ick = {
         .name           = "sha11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
@@ -2128,7 +2133,7 @@ static struct clk sha11_ick = {
 
 static struct clk des1_ick = {
         .name           = "des1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
@@ -2189,7 +2194,7 @@ static struct clk dss2_alwon_fck = {
 static struct clk dss_ick_3430es1 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2200,7 +2205,7 @@ static struct clk dss_ick_3430es1 = {
 static struct clk dss_ick_3430es2 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2223,7 +2228,7 @@ static struct clk cam_mclk = {
 static struct clk cam_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
@@ -2266,7 +2271,7 @@ static struct clk usbhost_48m_fck = {
 static struct clk usbhost_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "usbhost_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
@@ -2366,7 +2371,7 @@ static struct clk wkup_l4_ick = {
 /* Never specifically named in the TRM, so we have to infer a likely name */
 static struct clk usim_ick = {
         .name           = "usim_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2376,7 +2381,7 @@ static struct clk usim_ick = {
 
 static struct clk wdt2_ick = {
         .name           = "wdt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
@@ -2386,7 +2391,7 @@ static struct clk wdt2_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
@@ -2396,7 +2401,7 @@ static struct clk wdt1_ick = {
 
 static struct clk gpio1_ick = {
         .name           = "gpio1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
@@ -2406,7 +2411,7 @@ static struct clk gpio1_ick = {
 
 static struct clk omap_32ksync_ick = {
         .name           = "omap_32ksync_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2417,7 +2422,7 @@ static struct clk omap_32ksync_ick = {
 /* XXX This clock no longer exists in 3430 TRM rev F */
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
@@ -2427,7 +2432,7 @@ static struct clk gpt12_ick = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
@@ -2465,6 +2470,16 @@ static struct clk uart3_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_fck = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt2_fck = {
         .name           = "gpt2_fck",
         .ops            = &clkops_omap2_dflt_wait,
@@ -2647,7 +2662,7 @@ static struct clk per_l4_ick = {
 
 static struct clk gpio6_ick = {
         .name           = "gpio6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
@@ -2657,7 +2672,7 @@ static struct clk gpio6_ick = {
 
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
@@ -2667,7 +2682,7 @@ static struct clk gpio5_ick = {
 
 static struct clk gpio4_ick = {
         .name           = "gpio4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
@@ -2677,7 +2692,7 @@ static struct clk gpio4_ick = {
 
 static struct clk gpio3_ick = {
         .name           = "gpio3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
@@ -2687,7 +2702,7 @@ static struct clk gpio3_ick = {
 
 static struct clk gpio2_ick = {
         .name           = "gpio2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
@@ -2697,7 +2712,7 @@ static struct clk gpio2_ick = {
 
 static struct clk wdt3_ick = {
         .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
@@ -2707,7 +2722,7 @@ static struct clk wdt3_ick = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
@@ -2715,9 +2730,19 @@ static struct clk uart3_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_ick = {
+        .name           = "uart4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
@@ -2727,7 +2752,7 @@ static struct clk gpt9_ick = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
@@ -2737,7 +2762,7 @@ static struct clk gpt8_ick = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
@@ -2747,7 +2772,7 @@ static struct clk gpt7_ick = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
@@ -2757,7 +2782,7 @@ static struct clk gpt6_ick = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
@@ -2767,7 +2792,7 @@ static struct clk gpt5_ick = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
@@ -2777,7 +2802,7 @@ static struct clk gpt4_ick = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
@@ -2787,7 +2812,7 @@ static struct clk gpt3_ick = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
@@ -2797,7 +2822,7 @@ static struct clk gpt2_ick = {
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2807,7 +2832,7 @@ static struct clk mcbsp2_ick = {
 
 static struct clk mcbsp3_ick = {
         .name           = "mcbsp3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2817,7 +2842,7 @@ static struct clk mcbsp3_ick = {
 
 static struct clk mcbsp4_ick = {
         .name           = "mcbsp4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
@@ -3024,6 +3049,7 @@ static struct clk sr1_fck = {
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
@@ -3034,6 +3060,7 @@ static struct clk sr2_fck = {
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
@@ -3158,7 +3185,7 @@ static struct clk vpfe_fck = {
  */
 static struct clk uart4_ick_am35xx = {
         .name           = "uart4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = AM35XX_EN_UART4_SHIFT,
@@ -3181,20 +3208,25 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
@@ -3223,8 +3255,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
@@ -3232,8 +3264,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
@@ -3242,25 +3274,28 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2 | CK_3517),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2 | CK_3517),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
-        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
-        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
-        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_3XXX),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_3XXX),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_3XXX),
+        CLK("omap_hsmmc.2",     "fck",  &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap_hsmmc.1",     "fck",  &mmchs2_fck,    CK_3XXX),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
+        CLK("omap_hsmmc.0",     "fck",  &mmchs1_fck,    CK_3XXX),
+        CLK("omap_i2c.3", "fck",        &i2c3_fck,      CK_3XXX),
+        CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_3XXX),
+        CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_3XXX),
         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
@@ -3274,34 +3309,35 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2 | CK_AM35XX),
-        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
-        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
-        CLK("omap-sham",        "ick",  &sha12_ick,     CK_343X),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
-        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
-        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
+        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
+        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
+        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
+        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
-        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_3XXX),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_3XXX),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
@@ -3309,46 +3345,62 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
-        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_3XXX),
-        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_3XXX),
-        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_3XXX),
-        CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
+        CLK("omapdss_dss",      "fck",          &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK("omapdss_dss",      "fck",          &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omapdss_dss",      "tv_clk",       &dss_tv_fck,    CK_3XXX),
+        CLK("omapdss_dss",      "video_clk",    &dss_96m_fck,   CK_3XXX),
+        CLK("omapdss_dss",      "sys_clk",      &dss2_alwon_fck, CK_3XXX),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3372,6 +3424,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
@@ -3392,9 +3445,9 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
@@ -3405,8 +3458,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK("musb_hdrc",        "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK("musb_hdrc",        "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
+        CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
+        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
 };
@@ -3415,38 +3468,40 @@ static struct omap_clk omap3xxx_clks[] = {
 int __init omap3xxx_clk_init(void)
 {
         struct omap_clk *c;
-        u32 cpu_clkflg = CK_3XXX;
+        u32 cpu_clkflg = 0;
 
         if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
-                cpu_clkflg |= CK_3517;
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3517;
         } else if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
-                cpu_clkflg |= CK_3505;
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3505;
+        } else if (cpu_is_omap3630()) {
+                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
+                cpu_clkflg = CK_36XX;
+        } else if (cpu_is_ti816x()) {
+                cpu_mask = RATE_IN_TI816X;
+                cpu_clkflg = CK_TI816X;
         } else if (cpu_is_omap34xx()) {
-                cpu_mask = RATE_IN_3XXX;
-                cpu_clkflg |= CK_343X;
-
-                /*
-                 * Update this if there are further clock changes between ES2
-                 * and production parts
-                 */
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
-                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
-                        cpu_clkflg |= CK_3430ES1;
+                        cpu_mask = RATE_IN_3430ES1;
+                        cpu_clkflg = CK_3430ES1;
                 } else {
-                        cpu_mask |= RATE_IN_3430ES2PLUS;
-                        cpu_clkflg |= CK_3430ES2;
+                        /*
+                         * Assume that anything that we haven't matched yet
+                         * has 3430ES2-type clocks.
+                         */
+                        cpu_mask = RATE_IN_3430ES2PLUS;
+                        cpu_clkflg = CK_3430ES2PLUS;
                 }
+        } else {
+                WARN(1, "clock: could not identify OMAP3 variant\n");
         }
 
         if (omap3_has_192mhz_clk())
                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
 
         if (cpu_is_omap3630()) {
-                cpu_mask |= RATE_IN_36XX;
-                cpu_clkflg |= CK_36XX;
-
                 /*
                  * XXX This type of dynamic rewriting of the clock tree is
                  * deprecated and should be revised soon.
@@ -3491,12 +3546,14 @@ int __init omap3xxx_clk_init(void)
                         omap2_init_clk_clkdm(c->lk.clk);
                 }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+        pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
 
         /*
          * Only enable those clocks we will need, let the drivers
@@ -3505,9 +3562,10 @@ int __init omap3xxx_clk_init(void)
         clk_enable_init_clocks();
 
         /*
-         * Lock DPLL5 and put it in autoidle.
+         * Lock DPLL5 -- here only until other device init code can
+         * handle this
          */
-        if (omap_rev() >= OMAP3430_REV_ES2_0)
+        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
                 omap3_clk_lock_dpll5();
 
         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index e10db7a90cb2..8c965671b4d4 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -17,21 +17,30 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
  */
 
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
-
-#include <plat/control.h>
 #include <plat/clkdev_omap.h>
 
 #include "clock.h"
 #include "clock44xx.h"
-#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
 #include "cm-regbits-44xx.h"
-#include "prm.h"
+#include "prm44xx.h"
 #include "prm-regbits-44xx.h"
+#include "control.h"
+#include "scrm44xx.h"
+
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL                      0
+#define OMAP4430_MODULEMODE_SWCTRL                      1
 
 /* Root clocks */
 
@@ -44,7 +53,9 @@ static struct clk extalt_clkin_ck = {
 static struct clk pad_clks_ck = {
         .name           = "pad_clks_ck",
         .rate           = 12000000,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
 };
 
 static struct clk pad_slimbus_core_clks_ck = {
@@ -62,7 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
 static struct clk slimbus_clk = {
         .name           = "slimbus_clk",
         .rate           = 12000000,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
 };
 
 static struct clk sys_32k_ck = {
@@ -175,21 +188,27 @@ static struct clk sys_clkin_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+static struct clk tie_low_clock_ck = {
+        .name           = "tie_low_clock_ck",
+        .rate           = 0,
+        .ops            = &clkops_null,
+};
+
 static struct clk utmi_phy_clkout_ck = {
         .name           = "utmi_phy_clkout_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
 static struct clk xclk60mhsp1_ck = {
         .name           = "xclk60mhsp1_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
 static struct clk xclk60mhsp2_ck = {
         .name           = "xclk60mhsp2_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
@@ -201,39 +220,23 @@ static struct clk xclk60motg_ck = {
 
 /* Module clocks and DPLL outputs */
 
-static const struct clksel_rate div2_1to2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel dpll_sys_ref_clk_div[] = {
-        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_sys_ref_clk = {
-        .name           = "dpll_sys_ref_clk",
+static struct clk abe_dpll_bypass_clk_mux_ck = {
+        .name           = "abe_dpll_bypass_clk_mux_ck",
         .parent         = &sys_clkin_ck,
-        .clksel         = dpll_sys_ref_clk_div,
-        .clksel_reg     = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
         .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
-static const struct clksel abe_dpll_refclk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk abe_dpll_refclk_mux_ck = {
         .name           = "abe_dpll_refclk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
-        .clksel         = abe_dpll_refclk_mux_sel,
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
@@ -244,7 +247,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
 /* DPLL_ABE */
 static struct dpll_data dpll_abe_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
-        .clk_bypass     = &sys_clkin_ck,
+        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
         .clk_ref        = &abe_dpll_refclk_mux_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -272,18 +275,73 @@ static struct clk dpll_abe_ck = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
+static struct clk dpll_abe_x2_ck = {
+        .name           = "dpll_abe_x2_ck",
+        .parent         = &dpll_abe_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap3_clkoutx2_recalc,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel dpll_abe_m2x2_div[] = {
+        { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
 static struct clk dpll_abe_m2x2_ck = {
         .name           = "dpll_abe_m2x2_ck",
-        .parent         = &dpll_abe_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .parent         = &dpll_abe_x2_ck,
+        .clksel         = dpll_abe_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
 static struct clk abe_24m_fclk = {
         .name           = "abe_24m_fclk",
         .parent         = &dpll_abe_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 8,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel_rate div3_1to4_rates[] = {
@@ -310,6 +368,12 @@ static struct clk abe_clk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
+static const struct clksel_rate div2_1to2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
 static const struct clksel aess_fclk_div[] = {
         { .parent = &abe_clk, .rates = div2_1to2_rates },
         { .parent = NULL },
@@ -327,67 +391,27 @@ static struct clk aess_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel_rate div31_1to31_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
-        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
-        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
-        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
-        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
-        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
-        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
-        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
-        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
-        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
-        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
-        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
-        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
-        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
-        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
-        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
-        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
-        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
-        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
-        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
-        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
-        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
-        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
-        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
-        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
-        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
-        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel dpll_abe_m3_div[] = {
-        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-static struct clk dpll_abe_m3_ck = {
-        .name           = "dpll_abe_m3_ck",
-        .parent         = &dpll_abe_ck,
-        .clksel         = dpll_abe_m3_div,
+static struct clk dpll_abe_m3x2_ck = {
+        .name           = "dpll_abe_m3x2_ck",
+        .parent         = &dpll_abe_x2_ck,
+        .clksel         = dpll_abe_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
-        { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk core_hsd_byp_clk_mux_ck = {
         .name           = "core_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .clksel         = core_hsd_byp_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
@@ -400,7 +424,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_core_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
@@ -418,25 +442,33 @@ static struct dpll_data dpll_core_dd = {
 
 static struct clk dpll_core_ck = {
         .name           = "dpll_core_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_core_dd,
         .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap3_core_dpll_ops,
         .recalc         = &omap3_dpll_recalc,
 };
 
-static const struct clksel dpll_core_m6_div[] = {
-        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+static struct clk dpll_core_x2_ck = {
+        .name           = "dpll_core_x2_ck",
+        .parent         = &dpll_core_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_core_m6x2_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_core_m6_ck = {
-        .name           = "dpll_core_m6_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m6x2_ck = {
+        .name           = "dpll_core_m6x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -444,7 +476,7 @@ static struct clk dpll_core_m6_ck = {
 
 static const struct clksel dbgclk_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
@@ -455,13 +487,18 @@ static struct clk dbgclk_mux_ck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel dpll_core_m2_div[] = {
+        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
 static struct clk dpll_core_m2_ck = {
         .name           = "dpll_core_m2_ck",
         .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+        .clksel         = dpll_core_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -471,29 +508,30 @@ static struct clk ddrphy_ck = {
         .name           = "ddrphy_ck",
         .parent         = &dpll_core_m2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
-static struct clk dpll_core_m5_ck = {
-        .name           = "dpll_core_m5_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m5x2_ck = {
+        .name           = "dpll_core_m5x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
 static const struct clksel div_core_div[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+        { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
         { .parent = NULL },
 };
 
 static struct clk div_core_ck = {
         .name           = "div_core_ck",
-        .parent         = &dpll_core_m5_ck,
+        .parent         = &dpll_core_m5x2_ck,
         .clksel         = div_core_div,
         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
@@ -512,13 +550,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
 };
 
 static const struct clksel div_iva_hs_clk_div[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+        { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
         { .parent = NULL },
 };
 
 static struct clk div_iva_hs_clk = {
         .name           = "div_iva_hs_clk",
-        .parent         = &dpll_core_m5_ck,
+        .parent         = &dpll_core_m5x2_ck,
         .clksel         = div_iva_hs_clk_div,
         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
@@ -530,7 +568,7 @@ static struct clk div_iva_hs_clk = {
 
 static struct clk div_mpu_hs_clk = {
         .name           = "div_mpu_hs_clk",
-        .parent         = &dpll_core_m5_ck,
+        .parent         = &dpll_core_m5x2_ck,
         .clksel         = div_iva_hs_clk_div,
         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
@@ -540,13 +578,13 @@ static struct clk div_mpu_hs_clk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_core_m4_ck = {
-        .name           = "dpll_core_m4_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m4x2_ck = {
+        .name           = "dpll_core_m4x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -554,65 +592,77 @@ static struct clk dpll_core_m4_ck = {
 
 static struct clk dll_clk_div_ck = {
         .name           = "dll_clk_div_ck",
-        .parent         = &dpll_core_m4_ck,
+        .parent         = &dpll_core_m4x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static const struct clksel dpll_abe_m2_div[] = {
+        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
 };
 
 static struct clk dpll_abe_m2_ck = {
         .name           = "dpll_abe_m2_ck",
         .parent         = &dpll_abe_ck,
-        .clksel         = dpll_abe_m3_div,
+        .clksel         = dpll_abe_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_core_m3_ck = {
-        .name           = "dpll_core_m3_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m3x2_ck = {
+        .name           = "dpll_core_m3x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_core_m7_ck = {
-        .name           = "dpll_core_m7_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m7x2_ck = {
+        .name           = "dpll_core_m7x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk iva_hsd_byp_clk_mux_ck = {
         .name           = "iva_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
+        .clksel         = iva_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 /* DPLL_IVA */
 static struct dpll_data dpll_iva_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
@@ -630,7 +680,7 @@ static struct dpll_data dpll_iva_dd = {
 
 static struct clk dpll_iva_ck = {
         .name           = "dpll_iva_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_iva_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -639,30 +689,38 @@ static struct clk dpll_iva_ck = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
-static const struct clksel dpll_iva_m4_div[] = {
-        { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
+static struct clk dpll_iva_x2_ck = {
+        .name           = "dpll_iva_x2_ck",
+        .parent         = &dpll_iva_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_iva_m4x2_div[] = {
+        { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_iva_m4_ck = {
-        .name           = "dpll_iva_m4_ck",
-        .parent         = &dpll_iva_ck,
-        .clksel         = dpll_iva_m4_div,
+static struct clk dpll_iva_m4x2_ck = {
+        .name           = "dpll_iva_m4x2_ck",
+        .parent         = &dpll_iva_x2_ck,
+        .clksel         = dpll_iva_m4x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_iva_m5_ck = {
-        .name           = "dpll_iva_m5_ck",
-        .parent         = &dpll_iva_ck,
-        .clksel         = dpll_iva_m4_div,
+static struct clk dpll_iva_m5x2_ck = {
+        .name           = "dpll_iva_m5x2_ck",
+        .parent         = &dpll_iva_x2_ck,
+        .clksel         = dpll_iva_m4x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -672,7 +730,7 @@ static struct clk dpll_iva_m5_ck = {
 static struct dpll_data dpll_mpu_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
         .clk_bypass     = &div_mpu_hs_clk,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
@@ -690,7 +748,7 @@ static struct dpll_data dpll_mpu_dd = {
 
 static struct clk dpll_mpu_ck = {
         .name           = "dpll_mpu_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_mpu_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -710,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
         .clksel         = dpll_mpu_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -718,20 +776,21 @@ static struct clk dpll_mpu_m2_ck = {
 
 static struct clk per_hs_clk_div_ck = {
         .name           = "per_hs_clk_div_ck",
-        .parent         = &dpll_abe_m3_ck,
+        .parent         = &dpll_abe_m3x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk per_hsd_byp_clk_mux_ck = {
         .name           = "per_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .clksel         = per_hsd_byp_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
@@ -744,7 +803,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_per_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
@@ -762,7 +821,7 @@ static struct dpll_data dpll_per_dd = {
 
 static struct clk dpll_per_ck = {
         .name           = "dpll_per_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_per_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -782,74 +841,95 @@ static struct clk dpll_per_m2_ck = {
         .clksel         = dpll_per_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_per_x2_ck = {
+        .name           = "dpll_per_x2_ck",
+        .parent         = &dpll_per_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap3_clkoutx2_recalc,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+};
+
+static const struct clksel dpll_per_m2x2_div[] = {
+        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
 static struct clk dpll_per_m2x2_ck = {
         .name           = "dpll_per_m2x2_ck",
-        .parent         = &dpll_per_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m3_ck = {
-        .name           = "dpll_per_m3_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m3x2_ck = {
+        .name           = "dpll_per_m3x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m4_ck = {
-        .name           = "dpll_per_m4_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m4x2_ck = {
+        .name           = "dpll_per_m4x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m5_ck = {
-        .name           = "dpll_per_m5_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m5x2_ck = {
+        .name           = "dpll_per_m5x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m6_ck = {
-        .name           = "dpll_per_m6_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m6x2_ck = {
+        .name           = "dpll_per_m6x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m7_ck = {
-        .name           = "dpll_per_m7_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m7x2_ck = {
+        .name           = "dpll_per_m7x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -858,8 +938,8 @@ static struct clk dpll_per_m7_ck = {
 /* DPLL_UNIPRO */
 static struct dpll_data dpll_unipro_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
-        .clk_bypass     = &dpll_sys_ref_clk,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
@@ -869,6 +949,7 @@ static struct dpll_data dpll_unipro_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
         .max_divider    = OMAP4430_MAX_DPLL_DIV,
         .min_divider    = 1,
@@ -877,7 +958,7 @@ static struct dpll_data dpll_unipro_dd = {
 
 static struct clk dpll_unipro_ck = {
         .name           = "dpll_unipro_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_unipro_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -886,18 +967,26 @@ static struct clk dpll_unipro_ck = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
+static struct clk dpll_unipro_x2_ck = {
+        .name           = "dpll_unipro_x2_ck",
+        .parent         = &dpll_unipro_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
 static const struct clksel dpll_unipro_m2x2_div[] = {
-        { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
+        { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
 };
 
 static struct clk dpll_unipro_m2x2_ck = {
         .name           = "dpll_unipro_m2x2_ck",
-        .parent         = &dpll_unipro_ck,
+        .parent         = &dpll_unipro_x2_ck,
         .clksel         = dpll_unipro_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -905,16 +994,18 @@ static struct clk dpll_unipro_m2x2_ck = {
 
 static struct clk usb_hs_clk_div_ck = {
         .name           = "usb_hs_clk_div_ck",
-        .parent         = &dpll_abe_m3_ck,
+        .parent         = &dpll_abe_m3x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 3,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /* DPLL_USB */
 static struct dpll_data dpll_usb_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
         .clk_bypass     = &usb_hs_clk_div_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .flags          = DPLL_J_TYPE,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
@@ -927,13 +1018,12 @@ static struct dpll_data dpll_usb_dd = {
         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
         .max_divider    = OMAP4430_MAX_DPLL_DIV,
         .min_divider    = 1,
-        .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL
 };
 
 
 static struct clk dpll_usb_ck = {
         .name           = "dpll_usb_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_usb_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -945,7 +1035,8 @@ static struct clk dpll_usb_ck = {
 static struct clk dpll_usb_clkdcoldo_ck = {
         .name           = "dpll_usb_clkdcoldo_ck",
         .parent         = &dpll_usb_ck,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
         .recalc         = &followparent_recalc,
 };
 
@@ -960,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
         .clksel         = dpll_usb_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -968,7 +1059,7 @@ static struct clk dpll_usb_m2_ck = {
 
 static const struct clksel ducati_clk_mux_sel[] = {
         { .parent = &div_core_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
@@ -987,21 +1078,24 @@ static struct clk func_12m_fclk = {
         .name           = "func_12m_fclk",
         .parent         = &dpll_per_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 16,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static struct clk func_24m_clk = {
         .name           = "func_24m_clk",
         .parent         = &dpll_per_m2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static struct clk func_24mc_fclk = {
         .name           = "func_24mc_fclk",
         .parent         = &dpll_per_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 8,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel_rate div2_4to8_rates[] = {
@@ -1031,7 +1125,8 @@ static struct clk func_48mc_fclk = {
         .name           = "func_48mc_fclk",
         .parent         = &dpll_per_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel_rate div2_2to4_rates[] = {
@@ -1041,13 +1136,13 @@ static const struct clksel_rate div2_2to4_rates[] = {
 };
 
 static const struct clksel func_64m_fclk_div[] = {
-        { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
+        { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
         { .parent = NULL },
 };
 
 static struct clk func_64m_fclk = {
         .name           = "func_64m_fclk",
-        .parent         = &dpll_per_m4_ck,
+        .parent         = &dpll_per_m4x2_ck,
         .clksel         = func_64m_fclk_div,
         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
@@ -1148,7 +1243,8 @@ static struct clk lp_clk_div_ck = {
         .name           = "lp_clk_div_ck",
         .parent         = &dpll_abe_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 16,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1216,13 +1312,14 @@ static struct clk per_abe_24m_fclk = {
         .name           = "per_abe_24m_fclk",
         .parent         = &dpll_abe_m2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel pmd_stm_clock_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
+        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
+        { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
         { .parent = NULL },
 };
 
@@ -1240,10 +1337,15 @@ static struct clk pmd_trace_clk_mux_ck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel syc_clk_div_div[] = {
+        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
 static struct clk syc_clk_div_ck = {
         .name           = "syc_clk_div_ck",
         .parent         = &sys_clkin_ck,
-        .clksel         = dpll_sys_ref_clk_div,
+        .clksel         = syc_clk_div_div,
         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
         .ops            = &clkops_null,
@@ -1284,13 +1386,13 @@ static struct clk aess_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk cust_efuse_fck = {
-        .name           = "cust_efuse_fck",
+static struct clk bandgap_fclk = {
+        .name           = "bandgap_fclk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_cefuse_clkdm",
-        .parent         = &sys_clkin_ck,
+        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -1344,6 +1446,56 @@ static struct clk dmic_fck = {
         .clkdm_name     = "abe_clkdm",
 };
 
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "tesla_clkdm",
+        .parent         = &dpll_iva_m4x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_sys_clk = {
+        .name           = "dss_sys_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &syc_clk_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_tv_clk = {
+        .name           = "dss_tv_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &extalt_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_dss_clk = {
+        .name           = "dss_dss_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &dpll_per_m5x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_48mhz_clk = {
+        .name           = "dss_48mhz_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_fck = {
         .name           = "dss_fck",
         .ops            = &clkops_omap2_dflt,
@@ -1354,18 +1506,18 @@ static struct clk dss_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ducati_ick = {
-        .name           = "ducati_ick",
+static struct clk efuse_ctrl_cust_fck = {
+        .name           = "efuse_ctrl_cust_fck",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "ducati_clkdm",
-        .parent         = &ducati_clk_mux_ck,
+        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk emif1_ick = {
-        .name           = "emif1_ick",
+static struct clk emif1_fck = {
+        .name           = "emif1_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1375,8 +1527,8 @@ static struct clk emif1_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk emif2_ick = {
-        .name           = "emif2_ick",
+static struct clk emif2_fck = {
+        .name           = "emif2_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1387,14 +1539,14 @@ static struct clk emif2_ick = {
 };
 
 static const struct clksel fdif_fclk_div[] = {
-        { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
+        { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
 };
 
 /* Merged fdif_fclk into fdif */
 static struct clk fdif_fck = {
         .name           = "fdif_fck",
-        .parent         = &dpll_per_m4_ck,
+        .parent         = &dpll_per_m4x2_ck,
         .clksel         = fdif_fclk_div,
         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
@@ -1407,42 +1559,24 @@ static struct clk fdif_fck = {
         .clkdm_name     = "iss_clkdm",
 };
 
-static const struct clksel per_sgx_fclk_div[] = {
-        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-
-static struct clk per_sgx_fclk = {
-        .name           = "per_sgx_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .clksel         = per_sgx_fclk_div,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PER_192M_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
-static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
-        { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
+static struct clk fpka_fck = {
+        .name           = "fpka_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
-/* Merged sgx_clk_mux into gfx */
-static struct clk gfx_fck = {
-        .name           = "gfx_fck",
-        .parent         = &dpll_core_m7_ck,
-        .clksel         = sgx_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
+static struct clk gpio1_dbclk = {
+        .name           = "gpio1_dbclk",
         .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_gfx_clkdm",
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio1_ick = {
@@ -1455,6 +1589,16 @@ static struct clk gpio1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio2_dbclk = {
+        .name           = "gpio2_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio2_ick = {
         .name           = "gpio2_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1465,6 +1609,16 @@ static struct clk gpio2_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio3_dbclk = {
+        .name           = "gpio3_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio3_ick = {
         .name           = "gpio3_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1475,6 +1629,16 @@ static struct clk gpio3_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio4_dbclk = {
+        .name           = "gpio4_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio4_ick = {
         .name           = "gpio4_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1485,6 +1649,16 @@ static struct clk gpio4_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio5_dbclk = {
+        .name           = "gpio5_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1495,6 +1669,16 @@ static struct clk gpio5_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio6_dbclk = {
+        .name           = "gpio6_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio6_ick = {
         .name           = "gpio6_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1515,214 +1699,25 @@ static struct clk gpmc_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static const struct clksel dmt1_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-/*
- * Merged dmt1_clk_mux into gptimer1
- * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
- */
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-};
-
-/*
- * Merged cm2_dm10_mux into gptimer10
- * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
- */
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm11_mux into gptimer11
- * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
- */
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm2_mux into gptimer2
- * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
- */
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm3_mux into gptimer3
- * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
- */
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm4_mux into gptimer4
- * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
- */
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-static const struct clksel timer5_sync_mux_sel[] = {
-        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-/*
- * Merged timer5_sync_mux into gptimer5
- * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
- */
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer6_sync_mux into gptimer6
- * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
- */
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer7_sync_mux into gptimer7
- * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
- */
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer8_sync_mux into gptimer8
- * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
- */
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged cm2_dm9_mux into gptimer9
- * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
- */
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
+/* Merged sgx_clk_mux into gpu */
+static struct clk gpu_fck = {
+        .name           = "gpu_fck",
+        .parent         = &dpll_core_m7x2_ck,
+        .clksel         = sgx_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
         .ops            = &clkops_omap2_dflt,
         .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
+        .clkdm_name     = "l3_gfx_clkdm",
 };
 
 static struct clk hdq1w_fck = {
@@ -1735,11 +1730,16 @@ static struct clk hdq1w_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel hsi_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
 /* Merged hsi_fclk into hsi */
-static struct clk hsi_ick = {
-        .name           = "hsi_ick",
+static struct clk hsi_fck = {
+        .name           = "hsi_fck",
         .parent         = &dpll_per_m2x2_ck,
-        .clksel         = per_sgx_fclk_div,
+        .clksel         = hsi_fclk_div,
         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
         .ops            = &clkops_omap2_dflt,
@@ -1791,6 +1791,26 @@ static struct clk i2c4_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk ipu_fck = {
+        .name           = "ipu_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ducati_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk iss_ctrlclk = {
+        .name           = "iss_ctrlclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk iss_fck = {
         .name           = "iss_fck",
         .ops            = &clkops_omap2_dflt,
@@ -1801,18 +1821,18 @@ static struct clk iss_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ivahd_ick = {
-        .name           = "ivahd_ick",
+static struct clk iva_fck = {
+        .name           = "iva_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "ivahd_clkdm",
-        .parent         = &dpll_iva_m5_ck,
+        .parent         = &dpll_iva_m5x2_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk keyboard_fck = {
-        .name           = "keyboard_fck",
+static struct clk kbd_fck = {
+        .name           = "kbd_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -1821,22 +1841,24 @@ static struct clk keyboard_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk l3_instr_interconnect_ick = {
-        .name           = "l3_instr_interconnect_ick",
+static struct clk l3_instr_ick = {
+        .name           = "l3_instr_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l3_instr_clkdm",
+        .flags          = ENABLE_ON_INIT,
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk l3_interconnect_3_ick = {
-        .name           = "l3_interconnect_3_ick",
+static struct clk l3_main_3_ick = {
+        .name           = "l3_main_3_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l3_instr_clkdm",
+        .flags          = ENABLE_ON_INIT,
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -2005,6 +2027,16 @@ static struct clk mcbsp4_fck = {
         .clkdm_name     = "l4_per_clkdm",
 };
 
+static struct clk mcpdm_fck = {
+        .name           = "mcpdm_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk mcspi1_fck = {
         .name           = "mcspi1_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2105,33 +2137,34 @@ static struct clk mmc5_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ocp_wp1_ick = {
-        .name           = "ocp_wp1_ick",
+static struct clk ocp2scp_usb_phy_phy_48m = {
+        .name           = "ocp2scp_usb_phy_phy_48m",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
-        .parent         = &l3_div_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk pdm_fck = {
-        .name           = "pdm_fck",
+static struct clk ocp2scp_usb_phy_ick = {
+        .name           = "ocp2scp_usb_phy_ick",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &pad_clks_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk pkaeip29_fck = {
-        .name           = "pkaeip29_fck",
+static struct clk ocp_wp_noc_ick = {
+        .name           = "ocp_wp_noc_ick",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l4_div_ck,
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .flags          = ENABLE_ON_INIT,
+        .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -2145,8 +2178,8 @@ static struct clk rng_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sha2md51_fck = {
-        .name           = "sha2md51_fck",
+static struct clk sha2md5_fck = {
+        .name           = "sha2md5_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2155,13 +2188,53 @@ static struct clk sha2md51_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sl2_ick = {
-        .name           = "sl2_ick",
+static struct clk sl2if_ick = {
+        .name           = "sl2if_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "ivahd_clkdm",
-        .parent         = &dpll_iva_m5_ck,
+        .parent         = &dpll_iva_m5x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_1 = {
+        .name           = "slimbus1_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &func_24m_clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_0 = {
+        .name           = "slimbus1_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_2 = {
+        .name           = "slimbus1_fclk_2",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_slimbus_clk = {
+        .name           = "slimbus1_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &slimbus_clk,
         .recalc         = &followparent_recalc,
 };
 
@@ -2175,6 +2248,36 @@ static struct clk slimbus1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk slimbus2_fclk_1 = {
+        .name           = "slimbus2_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &per_abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_fclk_0 = {
+        .name           = "slimbus2_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_24mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_slimbus_clk = {
+        .name           = "slimbus2_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &pad_slimbus_core_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk slimbus2_fck = {
         .name           = "slimbus2_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2185,8 +2288,8 @@ static struct clk slimbus2_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_core_fck = {
-        .name           = "sr_core_fck",
+static struct clk smartreflex_core_fck = {
+        .name           = "smartreflex_core_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2195,8 +2298,8 @@ static struct clk sr_core_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_iva_fck = {
-        .name           = "sr_iva_fck",
+static struct clk smartreflex_iva_fck = {
+        .name           = "smartreflex_iva_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2205,8 +2308,8 @@ static struct clk sr_iva_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_mpu_fck = {
-        .name           = "sr_mpu_fck",
+static struct clk smartreflex_mpu_fck = {
+        .name           = "smartreflex_mpu_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2215,14 +2318,175 @@ static struct clk sr_mpu_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk tesla_ick = {
-        .name           = "tesla_ick",
+/* Merged dmt1_clk_mux into timer1 */
+static struct clk timer1_fck = {
+        .name           = "timer1_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "tesla_clkdm",
-        .parent         = &dpll_iva_m4_ck,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* Merged cm2_dm10_mux into timer10 */
+static struct clk timer10_fck = {
+        .name           = "timer10_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm11_mux into timer11 */
+static struct clk timer11_fck = {
+        .name           = "timer11_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm2_mux into timer2 */
+static struct clk timer2_fck = {
+        .name           = "timer2_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm3_mux into timer3 */
+static struct clk timer3_fck = {
+        .name           = "timer3_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm4_mux into timer4 */
+static struct clk timer4_fck = {
+        .name           = "timer4_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged timer5_sync_mux into timer5 */
+static struct clk timer5_fck = {
+        .name           = "timer5_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer6_sync_mux into timer6 */
+static struct clk timer6_fck = {
+        .name           = "timer6_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer7_sync_mux into timer7 */
+static struct clk timer7_fck = {
+        .name           = "timer7_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer8_sync_mux into timer8 */
+static struct clk timer8_fck = {
+        .name           = "timer8_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged cm2_dm9_mux into timer9 */
+static struct clk timer9_fck = {
+        .name           = "timer9_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
 };
 
 static struct clk uart1_fck = {
@@ -2265,38 +2529,169 @@ static struct clk uart4_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk unipro1_fck = {
-        .name           = "unipro1_fck",
+static struct clk usb_host_fs_fck = {
+        .name           = "usb_host_fs_fck",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_96m_fclk,
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel utmi_p1_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p1_gfclk = {
+        .name           = "utmi_p1_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p1_clk = {
+        .name           = "usb_host_hs_utmi_p1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &utmi_p1_gfclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_fck = {
-        .name           = "usb_host_fck",
+static const struct clksel utmi_p2_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p2_gfclk = {
+        .name           = "utmi_p2_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p2_clk = {
+        .name           = "usb_host_hs_utmi_p2_clk",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &utmi_p2_gfclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p3_clk = {
+        .name           = "usb_host_hs_utmi_p3_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
         .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_fs_fck = {
-        .name           = "usb_host_fs_fck",
+static struct clk usb_host_hs_hsic480m_p1_clk = {
+        .name           = "usb_host_hs_hsic480m_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+        .name           = "usb_host_hs_hsic60m_p1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+        .name           = "usb_host_hs_hsic60m_p2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_hsic480m_p2_clk = {
+        .name           = "usb_host_hs_hsic480m_p2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_func48mclk = {
+        .name           = "usb_host_hs_func48mclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
         .parent         = &func_48mc_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_otg_ick = {
-        .name           = "usb_otg_ick",
+static struct clk usb_host_hs_fck = {
+        .name           = "usb_host_hs_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel otg_60m_gfclk_sel[] = {
+        { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
+        { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk otg_60m_gfclk = {
+        .name           = "otg_60m_gfclk",
+        .parent         = &utmi_phy_clkout_ck,
+        .clksel         = otg_60m_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_otg_hs_xclk = {
+        .name           = "usb_otg_hs_xclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &otg_60m_gfclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_otg_hs_ick = {
+        .name           = "usb_otg_hs_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -2305,38 +2700,101 @@ static struct clk usb_otg_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_tll_ick = {
-        .name           = "usb_tll_ick",
+static struct clk usb_phy_cm_clk32k = {
+        .name           = "usb_phy_cm_clk32k",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_usb_ch2_clk = {
+        .name           = "usb_tll_hs_usb_ch2_clk",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usbphyocp2scp_ick = {
-        .name           = "usbphyocp2scp_ick",
+static struct clk usb_tll_hs_usb_ch0_clk = {
+        .name           = "usb_tll_hs_usb_ch0_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_usb_ch1_clk = {
+        .name           = "usb_tll_hs_usb_ch1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_ick = {
+        .name           = "usb_tll_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l3_init_clkdm",
         .parent         = &l4_div_ck,
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate div2_14to18_rates[] = {
+        { .div = 14, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel usim_fclk_div[] = {
+        { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
+        { .parent = NULL },
+};
+
+static struct clk usim_ck = {
+        .name           = "usim_ck",
+        .parent         = &dpll_per_m4x2_ck,
+        .clksel         = usim_fclk_div,
+        .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk usim_fclk = {
+        .name           = "usim_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &usim_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk usim_fck = {
         .name           = "usim_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l4_wkup_clkdm",
         .parent         = &sys_32k_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk wdt2_fck = {
-        .name           = "wdt2_fck",
+static struct clk wd_timer2_fck = {
+        .name           = "wd_timer2_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2345,8 +2803,8 @@ static struct clk wdt2_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
+static struct clk wd_timer3_fck = {
+        .name           = "wd_timer3_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2356,23 +2814,6 @@ static struct clk wdt3_fck = {
 };
 
 /* Remaining optional clocks */
-static const struct clksel otg_60m_gfclk_sel[] = {
-        { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
-        { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk otg_60m_gfclk_ck = {
-        .name           = "otg_60m_gfclk_ck",
-        .parent         = &utmi_phy_clkout_ck,
-        .clksel         = otg_60m_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-
 static const struct clksel stm_clk_div_div[] = {
         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
@@ -2407,60 +2848,165 @@ static struct clk trace_clk_div_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel_rate div2_14to18_rates[] = {
-        { .div = 14, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 18, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
+/* SCRM aux clk nodes */
+
+static const struct clksel auxclk_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
 };
 
-static const struct clksel usim_fclk_div[] = {
-        { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
+static struct clk auxclk0_ck = {
+        .name           = "auxclk0_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK0,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk1_ck = {
+        .name           = "auxclk1_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK1,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk2_ck = {
+        .name           = "auxclk2_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK2,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static struct clk auxclk3_ck = {
+        .name           = "auxclk3_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK3,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk4_ck = {
+        .name           = "auxclk4_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK4,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk5_ck = {
+        .name           = "auxclk5_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK5,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static const struct clksel auxclkreq_sel[] = {
+        { .parent = &auxclk0_ck, .rates = div_1_0_rates },
+        { .parent = &auxclk1_ck, .rates = div_1_1_rates },
+        { .parent = &auxclk2_ck, .rates = div_1_2_rates },
+        { .parent = &auxclk3_ck, .rates = div_1_3_rates },
+        { .parent = &auxclk4_ck, .rates = div_1_4_rates },
+        { .parent = &auxclk5_ck, .rates = div_1_5_rates },
         { .parent = NULL },
 };
 
-static struct clk usim_fclk = {
-        .name           = "usim_fclk",
-        .parent         = &dpll_per_m4_ck,
-        .clksel         = usim_fclk_div,
-        .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
+static struct clk auxclkreq0_ck = {
+        .name           = "auxclkreq0_ck",
+        .parent         = &auxclk0_ck,
+        .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
         .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel utmi_p1_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
+static struct clk auxclkreq1_ck = {
+        .name           = "auxclkreq1_ck",
+        .parent         = &auxclk1_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
 };
 
-static struct clk utmi_p1_gfclk_ck = {
-        .name           = "utmi_p1_gfclk_ck",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p1_gfclk_sel,
+static struct clk auxclkreq2_ck = {
+        .name           = "auxclkreq2_ck",
+        .parent         = &auxclk2_ck,
         .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
         .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
         .recalc         = &omap2_clksel_recalc,
 };
 
-static const struct clksel utmi_p2_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
+static struct clk auxclkreq3_ck = {
+        .name           = "auxclkreq3_ck",
+        .parent         = &auxclk3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
 };
 
-static struct clk utmi_p2_gfclk_ck = {
-        .name           = "utmi_p2_gfclk_ck",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p2_gfclk_sel,
+static struct clk auxclkreq4_ck = {
+        .name           = "auxclkreq4_ck",
+        .parent         = &auxclk4_ck,
         .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
         .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq5_ck = {
+        .name           = "auxclkreq5_ck",
+        .parent         = &auxclk5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -2483,50 +3029,56 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
-        CLK(NULL,       "dpll_sys_ref_clk",             &dpll_sys_ref_clk,      CK_443X),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
+        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
-        CLK(NULL,       "dpll_abe_m3_ck",               &dpll_abe_m3_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
-        CLK(NULL,       "dpll_core_m6_ck",              &dpll_core_m6_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m5_ck",              &dpll_core_m5_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
-        CLK(NULL,       "dpll_core_m4_ck",              &dpll_core_m4_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_core_m3_ck",              &dpll_core_m3_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_m7_ck",              &dpll_core_m7_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
-        CLK(NULL,       "dpll_iva_m4_ck",               &dpll_iva_m4_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_m5_ck",               &dpll_iva_m5_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m3_ck",               &dpll_per_m3_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m4_ck",               &dpll_per_m4_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m5_ck",               &dpll_per_m5_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m6_ck",               &dpll_per_m6_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m7_ck",               &dpll_per_m7_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
+        CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
@@ -2557,46 +3109,48 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
-        CLK(NULL,       "cust_efuse_fck",               &cust_efuse_fck,        CK_443X),
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
-        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
-        CLK(NULL,       "ducati_ick",                   &ducati_ick,    CK_443X),
-        CLK(NULL,       "emif1_ick",                    &emif1_ick,     CK_443X),
-        CLK(NULL,       "emif2_ick",                    &emif2_ick,     CK_443X),
+        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
+        CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
+        CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
+        CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
+        CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
+        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
+        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
+        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "per_sgx_fclk",                 &per_sgx_fclk,  CK_443X),
-        CLK(NULL,       "gfx_fck",                      &gfx_fck,       CK_443X),
+        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
+        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
+        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
+        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
+        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
+        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
+        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
-        CLK(NULL,       "gpt1_fck",                     &gpt1_fck,      CK_443X),
-        CLK(NULL,       "gpt10_fck",                    &gpt10_fck,     CK_443X),
-        CLK(NULL,       "gpt11_fck",                    &gpt11_fck,     CK_443X),
-        CLK(NULL,       "gpt2_fck",                     &gpt2_fck,      CK_443X),
-        CLK(NULL,       "gpt3_fck",                     &gpt3_fck,      CK_443X),
-        CLK(NULL,       "gpt4_fck",                     &gpt4_fck,      CK_443X),
-        CLK(NULL,       "gpt5_fck",                     &gpt5_fck,      CK_443X),
-        CLK(NULL,       "gpt6_fck",                     &gpt6_fck,      CK_443X),
-        CLK(NULL,       "gpt7_fck",                     &gpt7_fck,      CK_443X),
-        CLK(NULL,       "gpt8_fck",                     &gpt8_fck,      CK_443X),
-        CLK(NULL,       "gpt9_fck",                     &gpt9_fck,      CK_443X),
+        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
-        CLK(NULL,       "hsi_ick",                      &hsi_ick,       CK_443X),
-        CLK("i2c_omap.1",       "fck",                          &i2c1_fck,      CK_443X),
-        CLK("i2c_omap.2",       "fck",                          &i2c2_fck,      CK_443X),
-        CLK("i2c_omap.3",       "fck",                          &i2c3_fck,      CK_443X),
-        CLK("i2c_omap.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
+        CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
+        CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
+        CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
+        CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
-        CLK(NULL,       "ivahd_ick",                    &ivahd_ick,     CK_443X),
-        CLK(NULL,       "keyboard_fck",                 &keyboard_fck,  CK_443X),
-        CLK(NULL,       "l3_instr_interconnect_ick",    &l3_instr_interconnect_ick,     CK_443X),
-        CLK(NULL,       "l3_interconnect_3_ick",        &l3_interconnect_3_ick, CK_443X),
+        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
+        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
+        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
+        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
@@ -2607,52 +3161,82 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
-        CLK("mmci-omap-hs.0",   "fck",                          &mmc1_fck,      CK_443X),
-        CLK("mmci-omap-hs.1",   "fck",                          &mmc2_fck,      CK_443X),
-        CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
-        CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
-        CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
-        CLK(NULL,       "ocp_wp1_ick",                  &ocp_wp1_ick,   CK_443X),
-        CLK(NULL,       "pdm_fck",                      &pdm_fck,       CK_443X),
-        CLK(NULL,       "pkaeip29_fck",                 &pkaeip29_fck,  CK_443X),
+        CLK("omap_hsmmc.0",     "fck",                          &mmc1_fck,      CK_443X),
+        CLK("omap_hsmmc.1",     "fck",                          &mmc2_fck,      CK_443X),
+        CLK("omap_hsmmc.2",     "fck",                          &mmc3_fck,      CK_443X),
+        CLK("omap_hsmmc.3",     "fck",                          &mmc4_fck,      CK_443X),
+        CLK("omap_hsmmc.4",     "fck",                          &mmc5_fck,      CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
+        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
-        CLK(NULL,       "sha2md51_fck",                 &sha2md51_fck,  CK_443X),
-        CLK(NULL,       "sl2_ick",                      &sl2_ick,       CK_443X),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
+        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
-        CLK(NULL,       "sr_core_fck",                  &sr_core_fck,   CK_443X),
-        CLK(NULL,       "sr_iva_fck",                   &sr_iva_fck,    CK_443X),
-        CLK(NULL,       "sr_mpu_fck",                   &sr_mpu_fck,    CK_443X),
-        CLK(NULL,       "tesla_ick",                    &tesla_ick,     CK_443X),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
+        CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
+        CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
+        CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
+        CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
+        CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
+        CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
+        CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
+        CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
+        CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
+        CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
+        CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK(NULL,       "unipro1_fck",                  &unipro1_fck,   CK_443X),
-        CLK(NULL,       "usb_host_fck",                 &usb_host_fck,  CK_443X),
         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK("musb_hdrc",        "ick",                          &usb_otg_ick,   CK_443X),
-        CLK(NULL,       "usb_tll_ick",                  &usb_tll_ick,   CK_443X),
-        CLK(NULL,       "usbphyocp2scp_ick",            &usbphyocp2scp_ick,     CK_443X),
+        CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
+        CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
+        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK("omap_wdt", "fck",                          &wdt2_fck,      CK_443X),
-        CLK(NULL,       "wdt3_fck",                     &wdt3_fck,      CK_443X),
-        CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
+        CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
+        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
-        CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
-        CLK(NULL,       "gpio1_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio2_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio3_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio4_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio5_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio6_dbck",                   &dummy_ck,      CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
@@ -2665,28 +3249,40 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
-        CLK("i2c_omap.1",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("i2c_omap.2",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("i2c_omap.3",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("i2c_omap.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.0",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.1",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.2",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.3",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.4",   "ick",          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
@@ -2713,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
                         omap2_init_clk_clkdm(c->lk.clk);
                 }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         recalculate_root_clocks();
 
         /*
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index 1cf8131205fa..6424d46be14a 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -37,3 +37,9 @@ const struct clksel_rate gfx_l3_rates[] = {
         { .div = 0 }
 };
 
+const struct clksel_rate dsp_ick_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X },
+        { .div = 0 },
+};
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 5d80cb897489..6cb6c03293df 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -13,7 +13,6 @@
  */
 #undef DEBUG
 
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/list.h>
@@ -27,14 +26,8 @@
 
 #include <linux/bitops.h>
 
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "cm.h"
-
 #include <plat/clock.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
-#include <plat/prcm.h>
+#include "clockdomain.h"
 
 /* clkdm_list contains all registered struct clockdomains */
 static LIST_HEAD(clkdm_list);
@@ -42,6 +35,7 @@ static LIST_HEAD(clkdm_list);
 /* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
 static struct clkdm_autodep *autodeps;
 
+static struct clkdm_ops *arch_clkdm;
 
 /* Private functions */
 
@@ -141,6 +135,9 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
  * clockdomain is in hardware-supervised mode.  Meant to be called
  * once at clockdomain layer initialization, since these should remain
  * fixed for a particular architecture.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
  */
 static void _autodep_lookup(struct clkdm_autodep *autodep)
 {
@@ -168,12 +165,15 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
  * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
  * in hardware-supervised mode.  Meant to be called from clock framework
  * when a clock inside clockdomain 'clkdm' is enabled.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
  */
-static void _clkdm_add_autodeps(struct clockdomain *clkdm)
+void _clkdm_add_autodeps(struct clockdomain *clkdm)
 {
         struct clkdm_autodep *autodep;
 
-        if (!autodeps)
+        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
                 return;
 
         for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -199,12 +199,15 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
  * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
  * in hardware-supervised mode.  Meant to be called from clock framework
  * when a clock inside clockdomain 'clkdm' is disabled.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
  */
-static void _clkdm_del_autodeps(struct clockdomain *clkdm)
+void _clkdm_del_autodeps(struct clockdomain *clkdm)
 {
         struct clkdm_autodep *autodep;
 
-        if (!autodeps)
+        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
                 return;
 
         for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -223,138 +226,39 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
         }
 }
 
-/*
- * _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
- * @clkdm: struct clockdomain *
- * @enable: int 0 to disable, 1 to enable
- *
- * Internal helper for actually switching the bit that controls hwsup
- * idle transitions for clkdm.
- */
-static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
-{
-        u32 bits, v;
-
-        if (cpu_is_omap24xx()) {
-                if (enable)
-                        bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
-                else
-                        bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
-        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                if (enable)
-                        bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
-                else
-                        bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
-        } else {
-                BUG();
-        }
-
-        bits = bits << __ffs(clkdm->clktrctrl_mask);
-
-        v = __raw_readl(clkdm->clkstctrl_reg);
-        v &= ~(clkdm->clktrctrl_mask);
-        v |= bits;
-        __raw_writel(v, clkdm->clkstctrl_reg);
-
-}
-
 /**
- * _init_wkdep_usecount - initialize wkdep usecounts to match hardware
- * @clkdm: clockdomain to initialize wkdep usecounts
+ * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
+ * @clkdm: clockdomain that we are resolving dependencies for
+ * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
  *
- * Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
- * If a wakeup dependency is present in the hardware, the usecount will be
- * set to 1; otherwise, it will be set to 0.  Software should clear all
- * software wakeup dependencies prior to calling this function if it wishes
- * to ensure that all usecounts start at 0.  No return value.
+ * Iterates through @clkdm_deps, looking up the struct clockdomain named by
+ * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
+ * No return value.
  */
-static void _init_wkdep_usecount(struct clockdomain *clkdm)
+static void _resolve_clkdm_deps(struct clockdomain *clkdm,
+                                struct clkdm_dep *clkdm_deps)
 {
-        u32 v;
         struct clkdm_dep *cd;
 
-        if (!clkdm->wkdep_srcs)
-                return;
-
-        for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
+        for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
                 if (!omap_chip_is(cd->omap_chip))
                         continue;
-
-                if (!cd->clkdm && cd->clkdm_name)
-                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-
-                if (!cd->clkdm) {
-                        WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
-                             "found\n", clkdm->name, cd->clkdm_name);
+                if (cd->clkdm)
                         continue;
-                }
-
-                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
-                                            PM_WKDEP,
-                                            (1 << cd->clkdm->dep_bit));
+                cd->clkdm = _clkdm_lookup(cd->clkdm_name);
 
-                if (v)
-                        pr_debug("clockdomain: %s: wakeup dependency already "
-                                 "set to wake up when %s wakes\n",
-                                 clkdm->name, cd->clkdm->name);
-
-                atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
+                WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
+                     clkdm->name, cd->clkdm_name);
         }
 }
 
-/**
- * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
- * @clkdm: clockdomain to initialize sleepdep usecounts
- *
- * Initialize the sleep dependency usecount variables for clockdomain @clkdm.
- * If a sleep dependency is present in the hardware, the usecount will be
- * set to 1; otherwise, it will be set to 0.  Software should clear all
- * software sleep dependencies prior to calling this function if it wishes
- * to ensure that all usecounts start at 0.  No return value.
- */
-static void _init_sleepdep_usecount(struct clockdomain *clkdm)
-{
-        u32 v;
-        struct clkdm_dep *cd;
-
-        if (!cpu_is_omap34xx())
-                return;
-
-        if (!clkdm->sleepdep_srcs)
-                return;
-
-        for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                if (!cd->clkdm && cd->clkdm_name)
-                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-
-                if (!cd->clkdm) {
-                        WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
-                             "not found\n", clkdm->name, cd->clkdm_name);
-                        continue;
-                }
-
-                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
-                                            OMAP3430_CM_SLEEPDEP,
-                                            (1 << cd->clkdm->dep_bit));
-
-                if (v)
-                        pr_debug("clockdomain: %s: sleep dependency already "
-                                 "set to prevent from idling until %s "
-                                 "idles\n", clkdm->name, cd->clkdm->name);
-
-                atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
-        }
-};
-
 /* Public functions */
 
 /**
  * clkdm_init - set up the clockdomain layer
  * @clkdms: optional pointer to an array of clockdomains to register
  * @init_autodeps: optional pointer to an array of autodeps to register
+ * @custom_funcs: func pointers for arch specific implementations
  *
  * Set up internal state.  If a pointer to an array of clockdomains
  * @clkdms was supplied, loop through the list of clockdomains,
@@ -363,12 +267,18 @@ static void _init_sleepdep_usecount(struct clockdomain *clkdm)
  * @init_autodeps was provided, register those.  No return value.
  */
 void clkdm_init(struct clockdomain **clkdms,
-                struct clkdm_autodep *init_autodeps)
+                struct clkdm_autodep *init_autodeps,
+                struct clkdm_ops *custom_funcs)
 {
         struct clockdomain **c = NULL;
         struct clockdomain *clkdm;
         struct clkdm_autodep *autodep = NULL;
 
+        if (!custom_funcs)
+                WARN(1, "No custom clkdm functions registered\n");
+        else
+                arch_clkdm = custom_funcs;
+
         if (clkdms)
                 for (c = clkdms; *c; c++)
                         _clkdm_register(*c);
@@ -379,12 +289,20 @@ void clkdm_init(struct clockdomain **clkdms,
                         _autodep_lookup(autodep);
 
         /*
-         * Ensure that the *dep_usecount registers reflect the current
-         * state of the PRCM.
+         * Put all clockdomains into software-supervised mode; PM code
+         * should later enable hardware-supervised mode as appropriate
          */
         list_for_each_entry(clkdm, &clkdm_list, node) {
-                _init_wkdep_usecount(clkdm);
-                _init_sleepdep_usecount(clkdm);
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        clkdm_wakeup(clkdm);
+                else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+                        clkdm_deny_idle(clkdm);
+
+                _resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
+                clkdm_clear_all_wkdeps(clkdm);
+
+                _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
+                clkdm_clear_all_sleepdeps(clkdm);
         }
 }
 
@@ -480,26 +398,32 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
 int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
         struct clkdm_dep *cd;
+        int ret = 0;
 
         if (!clkdm1 || !clkdm2)
                 return -EINVAL;
 
         cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
-        if (IS_ERR(cd)) {
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+
+        if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
+                ret = -EINVAL;
+
+        if (ret) {
                 pr_debug("clockdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
-                return PTR_ERR(cd);
+                return ret;
         }
 
         if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
                 pr_debug("clockdomain: hardware will wake up %s when %s wakes "
                          "up\n", clkdm1->name, clkdm2->name);
 
-                prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
-                                     clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+                ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
         }
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -515,26 +439,32 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
         struct clkdm_dep *cd;
+        int ret = 0;
 
         if (!clkdm1 || !clkdm2)
                 return -EINVAL;
 
         cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
-        if (IS_ERR(cd)) {
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+
+        if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
+                ret = -EINVAL;
+
+        if (ret) {
                 pr_debug("clockdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
-                return PTR_ERR(cd);
+                return ret;
         }
 
         if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
                 pr_debug("clockdomain: hardware will no longer wake up %s "
                          "after %s wakes up\n", clkdm1->name, clkdm2->name);
 
-                prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
-                                       clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+                ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
         }
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -554,20 +484,26 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
         struct clkdm_dep *cd;
+        int ret = 0;
 
         if (!clkdm1 || !clkdm2)
                 return -EINVAL;
 
         cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
-        if (IS_ERR(cd)) {
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+
+        if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
+                ret = -EINVAL;
+
+        if (ret) {
                 pr_debug("clockdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
-                return PTR_ERR(cd);
+                return ret;
         }
 
         /* XXX It's faster to return the atomic wkdep_usecount */
-        return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
-                                       (1 << clkdm2->dep_bit));
+        return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
 }
 
 /**
@@ -582,24 +518,13 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
  */
 int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 {
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-
         if (!clkdm)
                 return -EINVAL;
 
-        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                /* PRM accesses are slow, so minimize them */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
-        }
-
-        prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
+                return -EINVAL;
 
-        return 0;
+        return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
 }
 
 /**
@@ -617,31 +542,33 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
         struct clkdm_dep *cd;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
+        int ret = 0;
 
         if (!clkdm1 || !clkdm2)
                 return -EINVAL;
 
         cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
-        if (IS_ERR(cd)) {
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+
+        if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
+                ret = -EINVAL;
+
+        if (ret) {
                 pr_debug("clockdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", clkdm1->name,
                          clkdm2->name);
-                return PTR_ERR(cd);
+                return ret;
         }
 
         if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
                 pr_debug("clockdomain: will prevent %s from sleeping if %s "
                          "is active\n", clkdm1->name, clkdm2->name);
 
-                cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
-                                    clkdm1->pwrdm.ptr->prcm_offs,
-                                    OMAP3430_CM_SLEEPDEP);
+                ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
         }
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -659,19 +586,23 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
         struct clkdm_dep *cd;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
+        int ret = 0;
 
         if (!clkdm1 || !clkdm2)
                 return -EINVAL;
 
         cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
-        if (IS_ERR(cd)) {
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+
+        if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
+                ret = -EINVAL;
+
+        if (ret) {
                 pr_debug("clockdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", clkdm1->name,
                          clkdm2->name);
-                return PTR_ERR(cd);
+                return ret;
         }
 
         if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
@@ -679,12 +610,10 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                          "sleeping if %s is active\n", clkdm1->name,
                          clkdm2->name);
 
-                cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
-                                      clkdm1->pwrdm.ptr->prcm_offs,
-                                      OMAP3430_CM_SLEEPDEP);
+                ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
         }
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -706,25 +635,27 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
         struct clkdm_dep *cd;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
+        int ret = 0;
 
         if (!clkdm1 || !clkdm2)
                 return -EINVAL;
 
         cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
-        if (IS_ERR(cd)) {
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+
+        if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
+                ret = -EINVAL;
+
+        if (ret) {
                 pr_debug("clockdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", clkdm1->name,
                          clkdm2->name);
-                return PTR_ERR(cd);
+                return ret;
         }
 
         /* XXX It's faster to return the atomic sleepdep_usecount */
-        return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                                       OMAP3430_CM_SLEEPDEP,
-                                       (1 << clkdm2->dep_bit));
+        return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
 }
 
 /**
@@ -739,54 +670,17 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
  */
 int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
 {
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
-
         if (!clkdm)
                 return -EINVAL;
 
-        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                /* PRM accesses are slow, so minimize them */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->sleepdep_usecount, 0);
-        }
-
-        prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
-                               OMAP3430_CM_SLEEPDEP);
-
-        return 0;
-}
-
-/**
- * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
- * @clkdm: struct clkdm * of a clockdomain
- *
- * Return the clockdomain @clkdm current state transition mode from the
- * corresponding domain CM_CLKSTCTRL register.  Returns -EINVAL if @clkdm
- * is NULL or the current mode upon success.
- */
-static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
-{
-        u32 v;
-
-        if (!clkdm)
+        if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
                 return -EINVAL;
 
-        v = __raw_readl(clkdm->clkstctrl_reg);
-        v &= clkdm->clktrctrl_mask;
-        v >>= __ffs(clkdm->clktrctrl_mask);
-
-        return v;
+        return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
 }
 
 /**
- * omap2_clkdm_sleep - force clockdomain sleep transition
+ * clkdm_sleep - force clockdomain sleep transition
  * @clkdm: struct clockdomain *
  *
  * Instruct the CM to force a sleep transition on the specified
@@ -794,7 +688,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
  * clockdomain does not support software-initiated sleep; 0 upon
  * success.
  */
-int omap2_clkdm_sleep(struct clockdomain *clkdm)
+int clkdm_sleep(struct clockdomain *clkdm)
 {
         if (!clkdm)
                 return -EINVAL;
@@ -805,32 +699,16 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
                 return -EINVAL;
         }
 
-        pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
-
-        if (cpu_is_omap24xx()) {
-
-                cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
-                            clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
-
-        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-
-                u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
-                         __ffs(clkdm->clktrctrl_mask));
-
-                u32 v = __raw_readl(clkdm->clkstctrl_reg);
-                v &= ~(clkdm->clktrctrl_mask);
-                v |= bits;
-                __raw_writel(v, clkdm->clkstctrl_reg);
+        if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
+                return -EINVAL;
 
-        } else {
-                BUG();
-        };
+        pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
 
-        return 0;
+        return arch_clkdm->clkdm_sleep(clkdm);
 }
 
 /**
- * omap2_clkdm_wakeup - force clockdomain wakeup transition
+ * clkdm_wakeup - force clockdomain wakeup transition
  * @clkdm: struct clockdomain *
  *
  * Instruct the CM to force a wakeup transition on the specified
@@ -838,7 +716,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
  * clockdomain does not support software-controlled wakeup; 0 upon
  * success.
  */
-int omap2_clkdm_wakeup(struct clockdomain *clkdm)
+int clkdm_wakeup(struct clockdomain *clkdm)
 {
         if (!clkdm)
                 return -EINVAL;
@@ -849,32 +727,16 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
                 return -EINVAL;
         }
 
-        pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
-
-        if (cpu_is_omap24xx()) {
-
-                cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
-                              clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
-
-        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-
-                u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
-                         __ffs(clkdm->clktrctrl_mask));
-
-                u32 v = __raw_readl(clkdm->clkstctrl_reg);
-                v &= ~(clkdm->clktrctrl_mask);
-                v |= bits;
-                __raw_writel(v, clkdm->clkstctrl_reg);
+        if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
+                return -EINVAL;
 
-        } else {
-                BUG();
-        };
+        pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
 
-        return 0;
+        return arch_clkdm->clkdm_wakeup(clkdm);
 }
 
 /**
- * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
+ * clkdm_allow_idle - enable hwsup idle transitions for clkdm
  * @clkdm: struct clockdomain *
  *
  * Allow the hardware to automatically switch the clockdomain @clkdm into
@@ -883,7 +745,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
  * framework, wkdep/sleepdep autodependencies are added; this is so
  * device drivers can read and write to the device.  No return value.
  */
-void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
+void clkdm_allow_idle(struct clockdomain *clkdm)
 {
         if (!clkdm)
                 return;
@@ -894,28 +756,18 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
                 return;
         }
 
+        if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
+                return;
+
         pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
                  clkdm->name);
 
-        /*
-         * XXX This should be removed once TI adds wakeup/sleep
-         * dependency code and data for OMAP4.
-         */
-        if (cpu_is_omap44xx()) {
-                WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency "
-                          "support is not yet implemented\n");
-        } else {
-                if (atomic_read(&clkdm->usecount) > 0)
-                        _clkdm_add_autodeps(clkdm);
-        }
-
-        _omap2_clkdm_set_hwsup(clkdm, 1);
-
+        arch_clkdm->clkdm_allow_idle(clkdm);
         pwrdm_clkdm_state_switch(clkdm);
 }
 
 /**
- * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
+ * clkdm_deny_idle - disable hwsup idle transitions for clkdm
  * @clkdm: struct clockdomain *
  *
  * Prevent the hardware from automatically switching the clockdomain
@@ -923,7 +775,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
  * downstream clocks enabled in the clock framework, wkdep/sleepdep
  * autodependencies are removed.  No return value.
  */
-void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
+void clkdm_deny_idle(struct clockdomain *clkdm)
 {
         if (!clkdm)
                 return;
@@ -934,29 +786,20 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
                 return;
         }
 
+        if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
+                return;
+
         pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
                  clkdm->name);
 
-        _omap2_clkdm_set_hwsup(clkdm, 0);
-
-        /*
-         * XXX This should be removed once TI adds wakeup/sleep
-         * dependency code and data for OMAP4.
-         */
-        if (cpu_is_omap44xx()) {
-                WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency "
-                          "support is not yet implemented\n");
-        } else {
-                if (atomic_read(&clkdm->usecount) > 0)
-                        _clkdm_del_autodeps(clkdm);
-        }
+        arch_clkdm->clkdm_deny_idle(clkdm);
 }
 
 
 /* Clockdomain-to-clock framework interface code */
 
 /**
- * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
+ * clkdm_clk_enable - add an enabled downstream clock to this clkdm
  * @clkdm: struct clockdomain *
  * @clk: struct clk * of the enabled downstream clock
  *
@@ -969,10 +812,8 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
  * by on-chip processors.  Returns -EINVAL if passed null pointers;
  * returns 0 upon success or if the clockdomain is in hwsup idle mode.
  */
-int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 {
-        int v;
-
         /*
          * XXX Rewrite this code to maintain a list of enabled
          * downstream clocks for debugging purposes?
@@ -981,6 +822,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
         if (!clkdm || !clk)
                 return -EINVAL;
 
+        if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
+                return -EINVAL;
+
         if (atomic_inc_return(&clkdm->usecount) > 1)
                 return 0;
 
@@ -989,21 +833,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
         pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
                  clk->name);
 
-        if (!clkdm->clkstctrl_reg)
-                return 0;
-
-        v = omap2_clkdm_clktrctrl_read(clkdm);
-
-        if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
-            (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
-                /* Disable HW transitions when we are changing deps */
-                _omap2_clkdm_set_hwsup(clkdm, 0);
-                _clkdm_add_autodeps(clkdm);
-                _omap2_clkdm_set_hwsup(clkdm, 1);
-        } else {
-                omap2_clkdm_wakeup(clkdm);
-        }
-
+        arch_clkdm->clkdm_clk_enable(clkdm);
         pwrdm_wait_transition(clkdm->pwrdm.ptr);
         pwrdm_clkdm_state_switch(clkdm);
 
@@ -1011,7 +841,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 }
 
 /**
- * omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
+ * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
  * @clkdm: struct clockdomain *
  * @clk: struct clk * of the disabled downstream clock
  *
@@ -1024,10 +854,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  * is enabled; or returns 0 upon success or if the clockdomain is in
  * hwsup idle mode.
  */
-int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-        int v;
-
         /*
          * XXX Rewrite this code to maintain a list of enabled
          * downstream clocks for debugging purposes?
@@ -1036,6 +864,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
         if (!clkdm || !clk)
                 return -EINVAL;
 
+        if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+                return -EINVAL;
+
 #ifdef DEBUG
         if (atomic_read(&clkdm->usecount) == 0) {
                 WARN_ON(1); /* underflow */
@@ -1051,21 +882,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
         pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
                  clk->name);
 
-        if (!clkdm->clkstctrl_reg)
-                return 0;
-
-        v = omap2_clkdm_clktrctrl_read(clkdm);
-
-        if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
-            (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
-                /* Disable HW transitions when we are changing deps */
-                _omap2_clkdm_set_hwsup(clkdm, 0);
-                _clkdm_del_autodeps(clkdm);
-                _omap2_clkdm_set_hwsup(clkdm, 1);
-        } else {
-                omap2_clkdm_sleep(clkdm);
-        }
-
+        arch_clkdm->clkdm_clk_disable(clkdm);
         pwrdm_clkdm_state_switch(clkdm);
 
         return 0;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
new file mode 100644
index 000000000000..5823584d9cd7
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -0,0 +1,197 @@
+/*
+ * arch/arm/plat-omap/include/mach/clockdomain.h
+ *
+ * OMAP2/3 clockdomain framework functions
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
+
+#include <linux/init.h>
+
+#include "powerdomain.h"
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/*
+ * Clockdomain flags
+ *
+ * XXX Document CLKDM_CAN_* flags
+ *
+ * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
+ *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
+ */
+#define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
+#define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
+#define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
+#define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
+#define CLKDM_NO_AUTODEPS                       (1 << 4)
+
+#define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
+#define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
+#define CLKDM_CAN_HWSUP_SWSUP   (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
+
+/**
+ * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
+ * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
+ * @omap_chip: OMAP chip types that this autodep is valid on
+ *
+ * A clockdomain that should have wkdeps and sleepdeps added when a
+ * clockdomain should stay active in hwsup mode; and conversely,
+ * removed when the clockdomain should be allowed to go inactive in
+ * hwsup mode.
+ *
+ * Autodeps are deprecated and should be removed after
+ * omap_hwmod-based fine-grained module idle control is added.
+ */
+struct clkdm_autodep {
+        union {
+                const char *name;
+                struct clockdomain *ptr;
+        } clkdm;
+        const struct omap_chip_id omap_chip;
+};
+
+/**
+ * struct clkdm_dep - encode dependencies between clockdomains
+ * @clkdm_name: clockdomain name
+ * @clkdm: pointer to the struct clockdomain of @clkdm_name
+ * @omap_chip: OMAP chip types that this dependency is valid on
+ * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
+ * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
+ *
+ * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
+ * should not be pre-initialized.
+ *
+ * XXX Should also include hardware (fixed) dependencies.
+ */
+struct clkdm_dep {
+        const char *clkdm_name;
+        struct clockdomain *clkdm;
+        atomic_t wkdep_usecount;
+        atomic_t sleepdep_usecount;
+        const struct omap_chip_id omap_chip;
+};
+
+/**
+ * struct clockdomain - OMAP clockdomain
+ * @name: clockdomain name
+ * @pwrdm: powerdomain containing this clockdomain
+ * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ * @flags: Clockdomain capability flags
+ * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
+ * @cm_inst: (OMAP4 only) CM instance register offset
+ * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
+ * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
+ * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
+ * @omap_chip: OMAP chip types that this clockdomain is valid on
+ * @usecount: Usecount tracking
+ * @node: list_head to link all clockdomains together
+ *
+ * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
+ * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance
+ *     definitions (OMAP4 only)
+ * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance
+ *     definitions (OMAP4 only)
+ */
+struct clockdomain {
+        const char *name;
+        union {
+                const char *name;
+                struct powerdomain *ptr;
+        } pwrdm;
+        const u16 clktrctrl_mask;
+        const u8 flags;
+        const u8 dep_bit;
+        const u8 prcm_partition;
+        const s16 cm_inst;
+        const u16 clkdm_offs;
+        struct clkdm_dep *wkdep_srcs;
+        struct clkdm_dep *sleepdep_srcs;
+        const struct omap_chip_id omap_chip;
+        atomic_t usecount;
+        struct list_head node;
+};
+
+/**
+ * struct clkdm_ops - Arch specific function implementations
+ * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
+ * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
+ * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
+ * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
+ * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
+ * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
+ * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
+ * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
+ * @clkdm_sleep: Force a clockdomain to sleep
+ * @clkdm_wakeup: Force a clockdomain to wakeup
+ * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
+ * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
+ * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
+ * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
+ */
+struct clkdm_ops {
+        int     (*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+        int     (*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+        int     (*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+        int     (*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
+        int     (*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+        int     (*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+        int     (*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+        int     (*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
+        int     (*clkdm_sleep)(struct clockdomain *clkdm);
+        int     (*clkdm_wakeup)(struct clockdomain *clkdm);
+        void    (*clkdm_allow_idle)(struct clockdomain *clkdm);
+        void    (*clkdm_deny_idle)(struct clockdomain *clkdm);
+        int     (*clkdm_clk_enable)(struct clockdomain *clkdm);
+        int     (*clkdm_clk_disable)(struct clockdomain *clkdm);
+};
+
+void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
+                        struct clkdm_ops *custom_funcs);
+struct clockdomain *clkdm_lookup(const char *name);
+
+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+                        void *user);
+struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
+
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
+void clkdm_allow_idle(struct clockdomain *clkdm);
+void clkdm_deny_idle(struct clockdomain *clkdm);
+
+int clkdm_wakeup(struct clockdomain *clkdm);
+int clkdm_sleep(struct clockdomain *clkdm);
+
+int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+
+extern void __init omap2xxx_clockdomains_init(void);
+extern void __init omap3xxx_clockdomains_init(void);
+extern void __init omap44xx_clockdomains_init(void);
+extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
+extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
+
+extern struct clkdm_ops omap2_clkdm_operations;
+extern struct clkdm_ops omap3_clkdm_operations;
+extern struct clkdm_ops omap4_clkdm_operations;
+
+#endif
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
new file mode 100644
index 000000000000..48d0db7e6069
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -0,0 +1,274 @@
+/*
+ * OMAP2 and OMAP3 clockdomain control
+ *
+ * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <plat/prcm.h>
+#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-24xx.h"
+#include "clockdomain.h"
+
+static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+                                                struct clockdomain *clkdm2)
+{
+        omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+
+static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+
+static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                PM_WKDEP, (1 << clkdm2->dep_bit));
+}
+
+static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                 PM_WKDEP);
+        return 0;
+}
+
+static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
+
+static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
+
+static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
+}
+
+static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->sleepdep_usecount, 0);
+        }
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
+
+static int omap2_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                clkdm->pwrdm.ptr->prcm_offs,
+                                OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                clkdm->pwrdm.ptr->prcm_offs,
+                                OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+
+static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+
+        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+}
+
+static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
+
+static void _enable_hwsup(struct clockdomain *clkdm)
+{
+        if (cpu_is_omap24xx())
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        else if (cpu_is_omap34xx())
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+}
+
+static void _disable_hwsup(struct clockdomain *clkdm)
+{
+        if (cpu_is_omap24xx())
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+        else if (cpu_is_omap34xx())
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+}
+
+
+static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_add_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                clkdm_wakeup(clkdm);
+        }
+
+        return 0;
+}
+
+static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_del_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                clkdm_sleep(clkdm);
+        }
+
+        return 0;
+}
+
+static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+
+static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+
+static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+
+        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+}
+
+static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
+
+struct clkdm_ops omap2_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_sleep            = omap2_clkdm_sleep,
+        .clkdm_wakeup           = omap2_clkdm_wakeup,
+        .clkdm_allow_idle       = omap2_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap2_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
+};
+
+struct clkdm_ops omap3_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_add_sleepdep     = omap3_clkdm_add_sleepdep,
+        .clkdm_del_sleepdep     = omap3_clkdm_del_sleepdep,
+        .clkdm_read_sleepdep    = omap3_clkdm_read_sleepdep,
+        .clkdm_clear_all_sleepdeps      = omap3_clkdm_clear_all_sleepdeps,
+        .clkdm_sleep            = omap3_clkdm_sleep,
+        .clkdm_wakeup           = omap3_clkdm_wakeup,
+        .clkdm_allow_idle       = omap3_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap3_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
new file mode 100644
index 000000000000..a1a4ecd26544
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -0,0 +1,137 @@
+/*
+ * OMAP4 clockdomain control
+ *
+ * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include "clockdomain.h"
+#include "cminst44xx.h"
+#include "cm44xx.h"
+
+static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
+                                        clkdm1->prcm_partition,
+                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                        OMAP4_CM_STATICDEP);
+        return 0;
+}
+
+static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
+                                        clkdm1->prcm_partition,
+                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                        OMAP4_CM_STATICDEP);
+        return 0;
+}
+
+static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
+                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                        OMAP4_CM_STATICDEP,
+                                        (1 << clkdm2->dep_bit));
+}
+
+static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+
+        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs +
+                                        OMAP4_CM_STATICDEP);
+        return 0;
+}
+
+static int omap4_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+
+        if (!hwsup)
+                clkdm_wakeup(clkdm);
+
+        return 0;
+}
+
+static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+
+        if (!hwsup)
+                clkdm_sleep(clkdm);
+
+        return 0;
+}
+
+struct clkdm_ops omap4_clkdm_operations = {
+        .clkdm_add_wkdep        = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_wkdep        = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_wkdep       = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_add_sleepdep     = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_sleepdep     = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_sleepdep    = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_sleepdeps      = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_sleep            = omap4_clkdm_sleep,
+        .clkdm_wakeup           = omap4_clkdm_wakeup,
+        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 8fc19ff2cd89..13bde95b6790 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2008-2009 Texas Instruments, Inc.
  * Copyright (C) 2008-2010 Nokia Corporation
  *
- * Written by Paul Walmsley and Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This file contains clockdomains and clockdomain wakeup/sleep
  * dependencies for the OMAP2/3 chips.  Some notes:
@@ -32,12 +32,17 @@
  *    from the Power domain framework
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
+#include <linux/kernel.h>
+#include <linux/io.h>
 
-#include <plat/clockdomain.h>
-#include "cm.h"
-#include "prm.h"
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
 
 /*
  * Clockdomain dependencies for wkdeps/sleepdeps
@@ -165,12 +170,11 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
         { NULL },
 };
 
-#endif
-
+#endif /* CONFIG_ARCH_OMAP2 */
 
 /* 2430-specific possible wakeup dependencies */
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 
 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
 static struct clkdm_dep mdm_2430_wkdeps[] = {
@@ -193,7 +197,7 @@ static struct clkdm_dep mdm_2430_wkdeps[] = {
         { NULL },
 };
 
-#endif /* CONFIG_ARCH_OMAP2430 */
+#endif /* CONFIG_SOC_OMAP2430 */
 
 
 /* OMAP3-specific possible dependencies */
@@ -425,8 +429,6 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
  * sys_clkout/sys_clkout2.
  */
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
 /* This is an implicit clockdomain - it is never defined as such in TRM */
 static struct clockdomain wkup_clkdm = {
         .name           = "wkup_clkdm",
@@ -447,19 +449,16 @@ static struct clockdomain cm_clkdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
-#endif
-
 /*
  * 2420-only clockdomains
  */
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 
 static struct clockdomain mpu_2420_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = mpu_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -469,8 +468,6 @@ static struct clockdomain iva1_2420_clkdm = {
         .name           = "iva1_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
         .wkdep_srcs     = dsp_24xx_wkdeps,
         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
@@ -481,8 +478,6 @@ static struct clockdomain dsp_2420_clkdm = {
         .name           = "dsp_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
@@ -491,7 +486,6 @@ static struct clockdomain gfx_2420_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -501,7 +495,6 @@ static struct clockdomain core_l3_2420_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -511,7 +504,6 @@ static struct clockdomain core_l4_2420_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -521,26 +513,23 @@ static struct clockdomain dss_2420_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-#endif   /* CONFIG_ARCH_OMAP2420 */
+#endif   /* CONFIG_SOC_OMAP2420 */
 
 
 /*
  * 2430-only clockdomains
  */
 
-#if defined(CONFIG_ARCH_OMAP2430)
+#if defined(CONFIG_SOC_OMAP2430)
 
 static struct clockdomain mpu_2430_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = mpu_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -551,8 +540,6 @@ static struct clockdomain mdm_clkdm = {
         .name           = "mdm_clkdm",
         .pwrdm          = { .name = "mdm_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
         .wkdep_srcs     = mdm_2430_wkdeps,
         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
@@ -563,8 +550,6 @@ static struct clockdomain dsp_2430_clkdm = {
         .name           = "dsp_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
         .wkdep_srcs     = dsp_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
@@ -575,7 +560,6 @@ static struct clockdomain gfx_2430_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -590,7 +574,6 @@ static struct clockdomain core_l3_2430_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
@@ -606,7 +589,6 @@ static struct clockdomain core_l4_2430_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
@@ -617,12 +599,11 @@ static struct clockdomain dss_2430_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-#endif    /* CONFIG_ARCH_OMAP2430 */
+#endif    /* CONFIG_SOC_OMAP2430 */
 
 
 /*
@@ -635,7 +616,6 @@ static struct clockdomain mpu_3xxx_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_MPU_SHIFT,
         .wkdep_srcs     = mpu_3xxx_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
@@ -646,8 +626,6 @@ static struct clockdomain neon_clkdm = {
         .name           = "neon_clkdm",
         .pwrdm          = { .name = "neon_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = neon_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -657,8 +635,6 @@ static struct clockdomain iva2_clkdm = {
         .name           = "iva2_clkdm",
         .pwrdm          = { .name = "iva2_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
         .wkdep_srcs     = iva2_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
@@ -669,7 +645,6 @@ static struct clockdomain gfx_3430es1_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .sleepdep_srcs  = gfx_sgx_sleepdeps,
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
@@ -680,8 +655,6 @@ static struct clockdomain sgx_clkdm = {
         .name           = "sgx_clkdm",
         .pwrdm          = { .name = "sgx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .sleepdep_srcs  = gfx_sgx_sleepdeps,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
@@ -699,7 +672,6 @@ static struct clockdomain d2d_clkdm = {
         .name           = "d2d_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -713,7 +685,6 @@ static struct clockdomain core_l3_3xxx_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -728,7 +699,6 @@ static struct clockdomain core_l4_3xxx_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -739,8 +709,6 @@ static struct clockdomain dss_3xxx_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "dss_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
         .wkdep_srcs     = dss_wkdeps,
         .sleepdep_srcs  = dss_sleepdeps,
@@ -752,8 +720,6 @@ static struct clockdomain cam_clkdm = {
         .name           = "cam_clkdm",
         .pwrdm          = { .name = "cam_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = cam_wkdeps,
         .sleepdep_srcs  = cam_sleepdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
@@ -764,8 +730,6 @@ static struct clockdomain usbhost_clkdm = {
         .name           = "usbhost_clkdm",
         .pwrdm          = { .name = "usbhost_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = usbhost_wkdeps,
         .sleepdep_srcs  = usbhost_sleepdeps,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
@@ -776,8 +740,6 @@ static struct clockdomain per_clkdm = {
         .name           = "per_clkdm",
         .pwrdm          = { .name = "per_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_PER_SHIFT,
         .wkdep_srcs     = per_wkdeps,
         .sleepdep_srcs  = per_sleepdeps,
@@ -793,8 +755,6 @@ static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
         .pwrdm          = { .name = "emu_pwrdm" },
         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -831,8 +791,6 @@ static struct clockdomain dpll5_clkdm = {
 
 #endif   /* CONFIG_ARCH_OMAP3 */
 
-#include "clockdomains44xx.h"
-
 /*
  * Clockdomain hwsup dependencies (OMAP3 only)
  */
@@ -851,19 +809,12 @@ static struct clkdm_autodep clkdm_autodeps[] = {
         }
 };
 
-/*
- * List of clockdomain pointers per platform
- */
-
-static struct clockdomain *clockdomains_omap[] = {
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+static struct clockdomain *clockdomains_omap2[] __initdata = {
         &wkup_clkdm,
         &cm_clkdm,
         &prm_clkdm,
-#endif
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
         &mpu_2420_clkdm,
         &iva1_2420_clkdm,
         &dsp_2420_clkdm,
@@ -873,7 +824,7 @@ static struct clockdomain *clockdomains_omap[] = {
         &dss_2420_clkdm,
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
         &mpu_2430_clkdm,
         &mdm_clkdm,
         &dsp_2430_clkdm,
@@ -903,35 +854,15 @@ static struct clockdomain *clockdomains_omap[] = {
         &dpll4_clkdm,
         &dpll5_clkdm,
 #endif
-
-#ifdef CONFIG_ARCH_OMAP4
-        &l4_cefuse_44xx_clkdm,
-        &l4_cfg_44xx_clkdm,
-        &tesla_44xx_clkdm,
-        &l3_gfx_44xx_clkdm,
-        &ivahd_44xx_clkdm,
-        &l4_secure_44xx_clkdm,
-        &l4_per_44xx_clkdm,
-        &abe_44xx_clkdm,
-        &l3_instr_44xx_clkdm,
-        &l3_init_44xx_clkdm,
-        &mpuss_44xx_clkdm,
-        &mpu0_44xx_clkdm,
-        &mpu1_44xx_clkdm,
-        &l3_emif_44xx_clkdm,
-        &l4_ao_44xx_clkdm,
-        &ducati_44xx_clkdm,
-        &l3_2_44xx_clkdm,
-        &l3_1_44xx_clkdm,
-        &l3_d2d_44xx_clkdm,
-        &iss_44xx_clkdm,
-        &l3_dss_44xx_clkdm,
-        &l4_wkup_44xx_clkdm,
-        &emu_sys_44xx_clkdm,
-        &l3_dma_44xx_clkdm,
-#endif
-
         NULL,
 };
 
-#endif
+void __init omap2xxx_clockdomains_init(void)
+{
+        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
+}
+
+void __init omap3xxx_clockdomains_init(void)
+{
+        clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
+}
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h
deleted file mode 100644
index 7e5ba0f67925..000000000000
--- a/arch/arm/mach-omap2/clockdomains44xx.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * OMAP4 Clock domains framework
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
- *
- * Abhijit Pagare (abhijitpagare@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*
- * To-Do List
- * -> Populate the Sleep/Wakeup dependencies for the domains
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
-
-#include <plat/clockdomain.h>
-
-#if defined(CONFIG_ARCH_OMAP4)
-
-static struct clockdomain l4_cefuse_44xx_clkdm = {
-        .name             = "l4_cefuse_clkdm",
-        .pwrdm            = { .name = "cefuse_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CEFUSE_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l4_cfg_44xx_clkdm = {
-        .name             = "l4_cfg_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L4CFG_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain tesla_44xx_clkdm = {
-        .name             = "tesla_clkdm",
-        .pwrdm            = { .name = "tesla_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_TESLA_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_gfx_44xx_clkdm = {
-        .name             = "l3_gfx_clkdm",
-        .pwrdm            = { .name = "gfx_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_GFX_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain ivahd_44xx_clkdm = {
-        .name             = "ivahd_clkdm",
-        .pwrdm            = { .name = "ivahd_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_IVAHD_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l4_secure_44xx_clkdm = {
-        .name             = "l4_secure_clkdm",
-        .pwrdm            = { .name = "l4per_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L4SEC_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l4_per_44xx_clkdm = {
-        .name             = "l4_per_clkdm",
-        .pwrdm            = { .name = "l4per_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L4PER_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain abe_44xx_clkdm = {
-        .name             = "abe_clkdm",
-        .pwrdm            = { .name = "abe_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM1_ABE_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_instr_44xx_clkdm = {
-        .name             = "l3_instr_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3INSTR_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_init_44xx_clkdm = {
-        .name             = "l3_init_clkdm",
-        .pwrdm            = { .name = "l3init_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3INIT_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain mpuss_44xx_clkdm = {
-        .name             = "mpuss_clkdm",
-        .pwrdm            = { .name = "mpu_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_MPU_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain mpu0_44xx_clkdm = {
-        .name             = "mpu0_clkdm",
-        .pwrdm            = { .name = "cpu0_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CPU0_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain mpu1_44xx_clkdm = {
-        .name             = "mpu1_clkdm",
-        .pwrdm            = { .name = "cpu1_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CPU1_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_emif_44xx_clkdm = {
-        .name             = "l3_emif_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_MEMIF_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l4_ao_44xx_clkdm = {
-        .name             = "l4_ao_clkdm",
-        .pwrdm            = { .name = "always_on_core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_ALWON_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain ducati_44xx_clkdm = {
-        .name             = "ducati_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_DUCATI_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_2_44xx_clkdm = {
-        .name             = "l3_2_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3_2_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_1_44xx_clkdm = {
-        .name             = "l3_1_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3_1_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_d2d_44xx_clkdm = {
-        .name             = "l3_d2d_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_D2D_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain iss_44xx_clkdm = {
-        .name             = "iss_clkdm",
-        .pwrdm            = { .name = "cam_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CAM_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_dss_44xx_clkdm = {
-        .name             = "l3_dss_clkdm",
-        .pwrdm            = { .name = "dss_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_DSS_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l4_wkup_44xx_clkdm = {
-        .name             = "l4_wkup_clkdm",
-        .pwrdm            = { .name = "wkup_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_WKUP_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain emu_sys_44xx_clkdm = {
-        .name             = "emu_sys_clkdm",
-        .pwrdm            = { .name = "emu_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_EMU_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-static struct clockdomain l3_dma_44xx_clkdm = {
-        .name             = "l3_dma_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_SDMA_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
new file mode 100644
index 000000000000..a607ec196e8b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -0,0 +1,689 @@
+/*
+ * OMAP4 Clock domains framework
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+
+#include "cm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu44xx.h"
+
+/* Static Dependencies for OMAP4 Clock Domains */
+
+static struct clkdm_dep ducati_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "abe_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_2_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_dss_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_gfx_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_init_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_cfg_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_secure_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_wkup_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "tesla_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep iss_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "abe_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_2_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_init_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_cfg_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "abe_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ducati_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_dss_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_init_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_cfg_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_secure_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_wkup_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_2_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "abe_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_cfg_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_secure_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_wkup_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "abe_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ducati_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_2_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_dss_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_gfx_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_init_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_cfg_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_secure_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_wkup_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "tesla_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clkdm_dep tesla_wkup_sleep_deps[] = {
+        {
+                .clkdm_name      = "abe_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "ivahd_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_1_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_2_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_emif_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l3_init_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_cfg_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_per_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        {
+                .clkdm_name      = "l4_wkup_clkdm",
+                .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+        },
+        { NULL },
+};
+
+static struct clockdomain l4_cefuse_44xx_clkdm = {
+        .name             = "l4_cefuse_clkdm",
+        .pwrdm            = { .name = "cefuse_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CEFUSE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_cfg_44xx_clkdm = {
+        .name             = "l4_cfg_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
+        .dep_bit          = OMAP4430_L4CFG_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain tesla_44xx_clkdm = {
+        .name             = "tesla_clkdm",
+        .pwrdm            = { .name = "tesla_pwrdm" },
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_TESLA_INST,
+        .clkdm_offs       = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
+        .dep_bit          = OMAP4430_TESLA_STATDEP_SHIFT,
+        .wkdep_srcs       = tesla_wkup_sleep_deps,
+        .sleepdep_srcs    = tesla_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_gfx_44xx_clkdm = {
+        .name             = "l3_gfx_clkdm",
+        .pwrdm            = { .name = "gfx_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_GFX_INST,
+        .clkdm_offs       = OMAP4430_CM2_GFX_GFX_CDOFFS,
+        .dep_bit          = OMAP4430_GFX_STATDEP_SHIFT,
+        .wkdep_srcs       = l3_gfx_wkup_sleep_deps,
+        .sleepdep_srcs    = l3_gfx_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain ivahd_44xx_clkdm = {
+        .name             = "ivahd_clkdm",
+        .pwrdm            = { .name = "ivahd_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_IVAHD_INST,
+        .clkdm_offs       = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
+        .dep_bit          = OMAP4430_IVAHD_STATDEP_SHIFT,
+        .wkdep_srcs       = ivahd_wkup_sleep_deps,
+        .sleepdep_srcs    = ivahd_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_secure_44xx_clkdm = {
+        .name             = "l4_secure_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_L4PER_INST,
+        .clkdm_offs       = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
+        .dep_bit          = OMAP4430_L4SEC_STATDEP_SHIFT,
+        .wkdep_srcs       = l4_secure_wkup_sleep_deps,
+        .sleepdep_srcs    = l4_secure_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_per_44xx_clkdm = {
+        .name             = "l4_per_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_L4PER_INST,
+        .clkdm_offs       = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
+        .dep_bit          = OMAP4430_L4PER_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain abe_44xx_clkdm = {
+        .name             = "abe_clkdm",
+        .pwrdm            = { .name = "abe_pwrdm" },
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_ABE_INST,
+        .clkdm_offs       = OMAP4430_CM1_ABE_ABE_CDOFFS,
+        .dep_bit          = OMAP4430_ABE_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_instr_44xx_clkdm = {
+        .name             = "l3_instr_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_init_44xx_clkdm = {
+        .name             = "l3_init_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_L3INIT_INST,
+        .clkdm_offs       = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
+        .dep_bit          = OMAP4430_L3INIT_STATDEP_SHIFT,
+        .wkdep_srcs       = l3_init_wkup_sleep_deps,
+        .sleepdep_srcs    = l3_init_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpuss_44xx_clkdm = {
+        .name             = "mpuss_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_MPU_INST,
+        .clkdm_offs       = OMAP4430_CM1_MPU_MPU_CDOFFS,
+        .wkdep_srcs       = mpuss_wkup_sleep_deps,
+        .sleepdep_srcs    = mpuss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpu0_44xx_clkdm = {
+        .name             = "mpu0_clkdm",
+        .pwrdm            = { .name = "cpu0_pwrdm" },
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
+        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpu1_44xx_clkdm = {
+        .name             = "mpu1_clkdm",
+        .pwrdm            = { .name = "cpu1_pwrdm" },
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
+        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_emif_44xx_clkdm = {
+        .name             = "l3_emif_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
+        .dep_bit          = OMAP4430_MEMIF_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_ao_44xx_clkdm = {
+        .name             = "l4_ao_clkdm",
+        .pwrdm            = { .name = "always_on_core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_ALWAYS_ON_INST,
+        .clkdm_offs       = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain ducati_44xx_clkdm = {
+        .name             = "ducati_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
+        .dep_bit          = OMAP4430_DUCATI_STATDEP_SHIFT,
+        .wkdep_srcs       = ducati_wkup_sleep_deps,
+        .sleepdep_srcs    = ducati_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_2_44xx_clkdm = {
+        .name             = "l3_2_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L3_2_CDOFFS,
+        .dep_bit          = OMAP4430_L3_2_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_1_44xx_clkdm = {
+        .name             = "l3_1_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L3_1_CDOFFS,
+        .dep_bit          = OMAP4430_L3_1_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_d2d_44xx_clkdm = {
+        .name             = "l3_d2d_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_D2D_CDOFFS,
+        .wkdep_srcs       = l3_d2d_wkup_sleep_deps,
+        .sleepdep_srcs    = l3_d2d_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain iss_44xx_clkdm = {
+        .name             = "iss_clkdm",
+        .pwrdm            = { .name = "cam_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CAM_INST,
+        .clkdm_offs       = OMAP4430_CM2_CAM_CAM_CDOFFS,
+        .wkdep_srcs       = iss_wkup_sleep_deps,
+        .sleepdep_srcs    = iss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_dss_44xx_clkdm = {
+        .name             = "l3_dss_clkdm",
+        .pwrdm            = { .name = "dss_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_DSS_INST,
+        .clkdm_offs       = OMAP4430_CM2_DSS_DSS_CDOFFS,
+        .dep_bit          = OMAP4430_DSS_STATDEP_SHIFT,
+        .wkdep_srcs       = l3_dss_wkup_sleep_deps,
+        .sleepdep_srcs    = l3_dss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_wkup_44xx_clkdm = {
+        .name             = "l4_wkup_clkdm",
+        .pwrdm            = { .name = "wkup_pwrdm" },
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
+        .cm_inst          = OMAP4430_PRM_WKUP_CM_INST,
+        .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
+        .dep_bit          = OMAP4430_L4WKUP_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain emu_sys_44xx_clkdm = {
+        .name             = "emu_sys_clkdm",
+        .pwrdm            = { .name = "emu_pwrdm" },
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
+        .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
+        .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_dma_44xx_clkdm = {
+        .name             = "l3_dma_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_SDMA_CDOFFS,
+        .wkdep_srcs       = l3_dma_wkup_sleep_deps,
+        .sleepdep_srcs    = l3_dma_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain *clockdomains_omap44xx[] __initdata = {
+        &l4_cefuse_44xx_clkdm,
+        &l4_cfg_44xx_clkdm,
+        &tesla_44xx_clkdm,
+        &l3_gfx_44xx_clkdm,
+        &ivahd_44xx_clkdm,
+        &l4_secure_44xx_clkdm,
+        &l4_per_44xx_clkdm,
+        &abe_44xx_clkdm,
+        &l3_instr_44xx_clkdm,
+        &l3_init_44xx_clkdm,
+        &mpuss_44xx_clkdm,
+        &mpu0_44xx_clkdm,
+        &mpu1_44xx_clkdm,
+        &l3_emif_44xx_clkdm,
+        &l4_ao_44xx_clkdm,
+        &ducati_44xx_clkdm,
+        &l3_2_44xx_clkdm,
+        &l3_1_44xx_clkdm,
+        &l3_d2d_44xx_clkdm,
+        &iss_44xx_clkdm,
+        &l3_dss_44xx_clkdm,
+        &l4_wkup_44xx_clkdm,
+        &emu_sys_44xx_clkdm,
+        &l3_dma_44xx_clkdm,
+        NULL,
+};
+
+void __init omap44xx_clockdomains_init(void)
+{
+        clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index da51cc3ed7eb..686290437568 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -14,8 +14,6 @@
  * published by the Free Software Foundation.
  */
 
-#include "cm.h"
-
 /* Bits shared between registers */
 
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
@@ -126,8 +124,12 @@
 #define OMAP24XX_ST_HDQ_MASK                            (1 << 23)
 #define OMAP2420_ST_I2C2_SHIFT                          20
 #define OMAP2420_ST_I2C2_MASK                           (1 << 20)
+#define OMAP2430_ST_I2CHS1_SHIFT                        19
+#define OMAP2430_ST_I2CHS1_MASK                         (1 << 19)
 #define OMAP2420_ST_I2C1_SHIFT                          19
 #define OMAP2420_ST_I2C1_MASK                           (1 << 19)
+#define OMAP2430_ST_I2CHS2_SHIFT                        20
+#define OMAP2430_ST_I2CHS2_MASK                         (1 << 20)
 #define OMAP24XX_ST_MCBSP2_SHIFT                        16
 #define OMAP24XX_ST_MCBSP2_MASK                         (1 << 16)
 #define OMAP24XX_ST_MCBSP1_SHIFT                        15
@@ -208,8 +210,11 @@
 #define OMAP24XX_AUTO_USB_MASK                          (1 << 0)
 
 /* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC_SHIFT                        2
 #define OMAP24XX_AUTO_SDRC_MASK                         (1 << 2)
+#define OMAP24XX_AUTO_GPMC_SHIFT                        1
 #define OMAP24XX_AUTO_GPMC_MASK                         (1 << 1)
+#define OMAP24XX_AUTO_SDMA_SHIFT                        0
 #define OMAP24XX_AUTO_SDMA_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE4_CORE */
@@ -432,4 +437,9 @@
 #define OMAP2430_AUTOSTATE_MDM_SHIFT                    0
 #define OMAP2430_AUTOSTATE_MDM_MASK                     (1 << 0)
 
+/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
+#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
+#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
+
+
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index fe82b79d5f3b..b91275908f33 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -14,8 +14,6 @@
  * published by the Free Software Foundation.
  */
 
-#include "cm.h"
-
 /* Bits shared between registers */
 
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
@@ -649,6 +647,8 @@
 #define OMAP3430_ST_MCBSP2_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_PER */
+#define OMAP3630_AUTO_UART4_MASK                        (1 << 18)
+#define OMAP3630_AUTO_UART4_SHIFT                       18
 #define OMAP3430_AUTO_GPIO6_MASK                        (1 << 17)
 #define OMAP3430_AUTO_GPIO6_SHIFT                       17
 #define OMAP3430_AUTO_GPIO5_MASK                        (1 << 16)
@@ -798,4 +798,15 @@
 #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT           0
 #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK            (1 << 0)
 
+/*
+ *
+ */
+
+/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
+
+
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index ac8458e43252..9d47a05b17b4 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx Clock Management register bits
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -22,456 +22,459 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 
-#include "cm.h"
-
-
-/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+/*
+ * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
+ * CM_TESLA_DYNAMICDEP
+ */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
-#define OMAP4430_ABE_DYNDEP_MASK                                BITFIELD(3, 3)
+#define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
-#define OMAP4430_ABE_STATDEP_MASK                               BITFIELD(3, 3)
+#define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
-#define OMAP4430_ALWONCORE_DYNDEP_MASK                          BITFIELD(16, 16)
+#define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
-#define OMAP4430_ALWONCORE_STATDEP_MASK                         BITFIELD(16, 16)
+#define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 
 /*
- * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB,
- * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+ * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
+ * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
+ * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
-#define OMAP4430_AUTO_DPLL_MODE_MASK                            BITFIELD(0, 2)
+#define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
-#define OMAP4430_CEFUSE_DYNDEP_MASK                             BITFIELD(17, 17)
+#define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
-#define OMAP4430_CEFUSE_STATDEP_MASK                            BITFIELD(17, 17)
+#define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
-#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    BITFIELD(14, 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   BITFIELD(8, 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK                BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                BITFIELD(15, 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            BITFIELD(20, 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 BITFIELD(26, 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            BITFIELD(21, 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 BITFIELD(27, 27)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               31
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK                BITFIELD(31, 31)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             BITFIELD(28, 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             BITFIELD(29, 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                BITFIELD(16, 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             BITFIELD(17, 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             BITFIELD(18, 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             BITFIELD(19, 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        14
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK         BITFIELD(14, 14)
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                BITFIELD(16, 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 BITFIELD(17, 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 BITFIELD(18, 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 BITFIELD(19, 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             BITFIELD(25, 25)
-
-/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             10
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK              BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              BITFIELD(20, 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              BITFIELD(21, 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              BITFIELD(22, 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 BITFIELD(24, 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
-#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 BITFIELD(22, 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 BITFIELD(23, 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 BITFIELD(24, 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               BITFIELD(15, 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 BITFIELD(30, 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               BITFIELD(25, 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 
 /*
- * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
+ * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL,
- * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL
+ * CM_WKUP_TIMER1_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SHIFT                                   24
-#define OMAP4430_CLKSEL_MASK                                    BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 
 /*
  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
- * CM_CLKSEL_USB_60MHZ
+ * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
-#define OMAP4430_CLKSEL_0_0_MASK                                BITFIELD(0, 0)
+#define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
-#define OMAP4430_CLKSEL_0_1_MASK                                BITFIELD(0, 1)
+#define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
-#define OMAP4430_CLKSEL_24_25_MASK                              BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
-#define OMAP4430_CLKSEL_60M_MASK                                BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
-#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
-#define OMAP4430_CLKSEL_CORE_MASK                               BITFIELD(0, 0)
+#define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
-/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+/*
+ * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+ * CM_SHADOW_FREQ_CONFIG2
+ */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
-#define OMAP4430_CLKSEL_CORE_1_1_MASK                           BITFIELD(1, 1)
+#define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
-#define OMAP4430_CLKSEL_DIV_MASK                                BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
-#define OMAP4430_CLKSEL_FCLK_MASK                               BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    BITFIELD(25, 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 
 /*
  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
@@ -479,836 +482,869 @@
  * CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       BITFIELD(26, 27)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
-#define OMAP4430_CLKSEL_L3_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
-/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+/*
+ * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+ * CM_SHADOW_FREQ_CONFIG2
+ */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
-#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          BITFIELD(2, 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
-#define OMAP4430_CLKSEL_L4_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
-#define OMAP4430_CLKSEL_OPP_MASK                                BITFIELD(0, 1)
-
-/* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_PER_192M_SHIFT                          25
-#define OMAP4430_CLKSEL_PER_192M_MASK                           BITFIELD(25, 26)
+#define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
-#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        BITFIELD(27, 29)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      BITFIELD(24, 26)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
-#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 
 /*
  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
-#define OMAP4430_CLKSEL_SOURCE_MASK                             BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
-#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
-#define OMAP4430_CLKSEL_UTMI_P1_MASK                            BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
-#define OMAP4430_CLKSEL_UTMI_P2_MASK                            BITFIELD(25, 25)
+#define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
 /*
- * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL,
- * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
- * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL,
- * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE,
- * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE,
- * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL,
- * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
- * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
+ * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
+ * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
+ * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
+ * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
+ * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
+ * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
+ * CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
-#define OMAP4430_CLKTRCTRL_MASK                                 BITFIELD(0, 1)
+#define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
-#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         BITFIELD(0, 6)
+#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
-#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        BITFIELD(8, 18)
+#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
-#define OMAP4430_D2D_DYNDEP_MASK                                BITFIELD(18, 18)
+#define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
-#define OMAP4430_D2D_STATDEP_MASK                               BITFIELD(18, 18)
+#define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 
 /*
- * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
- * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,
- * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
- * CM_SSC_DELTAMSTEP_DPLL_MPU
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
+ * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
+ * CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
-#define OMAP4430_DELTAMSTEP_MASK                                BITFIELD(0, 19)
+#define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             2
-#define OMAP4430_DLL_OVERRIDE_MASK                              BITFIELD(2, 2)
+#define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 2)
 
 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
-#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          BITFIELD(0, 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DLL_RESET_SHIFT                                3
-#define OMAP4430_DLL_RESET_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
-#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           BITFIELD(23, 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
+/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     BITFIELD(20, 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        BITFIELD(0, 4)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   BITFIELD(5, 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   BITFIELD(10, 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
-#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           BITFIELD(0, 4)
+#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       BITFIELD(0, 6)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      BITFIELD(5, 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               BITFIELD(7, 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
- * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
-#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         BITFIELD(8, 10)
+#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
-#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          BITFIELD(11, 15)
+#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
+/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
-#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          BITFIELD(3, 7)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 1
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK                  BITFIELD(1, 1)
+#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
-#define OMAP4430_DPLL_DIV_MASK                                  BITFIELD(0, 6)
+#define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
-#define OMAP4430_DPLL_DIV_0_7_MASK                              BITFIELD(0, 7)
+#define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
-#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        BITFIELD(8, 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    BITFIELD(3, 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
-#define OMAP4430_DPLL_EN_MASK                                   BITFIELD(0, 2)
+#define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
-#define OMAP4430_DPLL_LPMODE_EN_MASK                            BITFIELD(10, 10)
+#define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
-#define OMAP4430_DPLL_MULT_MASK                                 BITFIELD(8, 18)
+#define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
-#define OMAP4430_DPLL_MULT_USB_MASK                             BITFIELD(8, 19)
+#define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
-#define OMAP4430_DPLL_REGM4XEN_MASK                             BITFIELD(11, 11)
+#define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
-#define OMAP4430_DPLL_SD_DIV_MASK                               BITFIELD(24, 31)
+#define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
-#define OMAP4430_DPLL_SSC_ACK_MASK                              BITFIELD(13, 13)
+#define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       BITFIELD(14, 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
-#define OMAP4430_DPLL_SSC_EN_MASK                               BITFIELD(12, 12)
+#define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
-#define OMAP4430_DSS_DYNDEP_MASK                                BITFIELD(8, 8)
+#define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE
  */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
-#define OMAP4430_DSS_STATDEP_MASK                               BITFIELD(8, 8)
+#define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
-#define OMAP4430_DUCATI_DYNDEP_MASK                             BITFIELD(0, 0)
+#define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
-/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
+/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
-#define OMAP4430_DUCATI_STATDEP_MASK                            BITFIELD(0, 0)
+#define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
-#define OMAP4430_FREQ_UPDATE_MASK                               BITFIELD(0, 0)
+#define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
-#define OMAP4430_GFX_DYNDEP_MASK                                BITFIELD(10, 10)
+#define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
-#define OMAP4430_GFX_STATDEP_MASK                               BITFIELD(10, 10)
+#define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
+/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
-#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          BITFIELD(0, 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    BITFIELD(12, 12)
-
-/*
- * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
- * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
- * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
- * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
- * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
- * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
- * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
- * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
+
+/*
+ * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
- * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
- * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
- * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
- * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
- * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
- * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_IDLEST_SHIFT                                   16
-#define OMAP4430_IDLEST_MASK                                    BITFIELD(16, 17)
+#define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
-/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+/*
+ * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
-#define OMAP4430_ISS_DYNDEP_MASK                                BITFIELD(9, 9)
+#define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
-#define OMAP4430_ISS_STATDEP_MASK                               BITFIELD(9, 9)
+#define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
-#define OMAP4430_IVAHD_DYNDEP_MASK                              BITFIELD(2, 2)
+#define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
-#define OMAP4430_IVAHD_STATDEP_MASK                             BITFIELD(2, 2)
+#define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
-#define OMAP4430_L3INIT_DYNDEP_MASK                             BITFIELD(7, 7)
+#define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
-#define OMAP4430_L3INIT_STATDEP_MASK                            BITFIELD(7, 7)
+#define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
- * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
-#define OMAP4430_L3_1_DYNDEP_MASK                               BITFIELD(5, 5)
+#define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
-#define OMAP4430_L3_1_STATDEP_MASK                              BITFIELD(5, 5)
+#define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
- * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP,
- * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
+ * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
+ * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
+ * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
-#define OMAP4430_L3_2_DYNDEP_MASK                               BITFIELD(6, 6)
+#define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
-#define OMAP4430_L3_2_STATDEP_MASK                              BITFIELD(6, 6)
+#define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
-/* Used by CM_L3_1_DYNAMICDEP */
+/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
-#define OMAP4430_L4CFG_DYNDEP_MASK                              BITFIELD(12, 12)
+#define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
-#define OMAP4430_L4CFG_STATDEP_MASK                             BITFIELD(12, 12)
+#define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
-#define OMAP4430_L4PER_DYNDEP_MASK                              BITFIELD(13, 13)
+#define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
-#define OMAP4430_L4PER_STATDEP_MASK                             BITFIELD(13, 13)
+#define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
-#define OMAP4430_L4SEC_DYNDEP_MASK                              BITFIELD(14, 14)
+#define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
-#define OMAP4430_L4SEC_STATDEP_MASK                             BITFIELD(14, 14)
+#define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
-#define OMAP4430_L4WKUP_DYNDEP_MASK                             BITFIELD(15, 15)
+#define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
-#define OMAP4430_L4WKUP_STATDEP_MASK                            BITFIELD(15, 15)
+#define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
- * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_MPU_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
-#define OMAP4430_MEMIF_DYNDEP_MASK                              BITFIELD(4, 4)
+#define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
-#define OMAP4430_MEMIF_STATDEP_MASK                             BITFIELD(4, 4)
+#define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
- * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
- * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
-#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       BITFIELD(8, 10)
+#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
- * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
- * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
-#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       BITFIELD(0, 6)
-
-/*
- * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
- * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
- * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
- * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
- * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
- * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
- * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
- * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
+
+/*
+ * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
- * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
- * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
- * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
- * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
- * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
- * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_MODULEMODE_SHIFT                               0
-#define OMAP4430_MODULEMODE_MASK                                BITFIELD(0, 1)
+#define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 
-/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         9
-#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          BITFIELD(9, 9)
+/* Used by CM_ALWON_USBPHY_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
- * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
-#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
+
+/* Used by CM_WKUP_USIM_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
-#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
-#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      BITFIELD(15, 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 BITFIELD(13, 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 BITFIELD(14, 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  BITFIELD(12, 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
-#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
-#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
-#define OMAP4430_OPTFCLKEN_XCLK_MASK                            BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 
-/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
-#define OMAP4430_OVERRIDE_ENABLE_MASK                           BITFIELD(19, 19)
+#define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
-#define OMAP4430_PAD_CLKS_GATE_MASK                             BITFIELD(8, 8)
+#define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
-#define OMAP4430_PERF_CURRENT_MASK                              BITFIELD(0, 7)
+#define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 
 /*
  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
@@ -1316,159 +1352,173 @@
  * CM_IVA_DVFS_PERF_TESLA
  */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
-#define OMAP4430_PERF_REQ_MASK                                  BITFIELD(0, 7)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         0
-#define OMAP4430_PER_DPLL_EMU_DIV_MASK                          BITFIELD(0, 6)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        8
-#define OMAP4430_PER_DPLL_EMU_MULT_MASK                         BITFIELD(8, 18)
+#define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
-#define OMAP4430_PHASE1_COMPLETED_MASK                          BITFIELD(0, 0)
+#define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
-#define OMAP4430_PHASE2A_COMPLETED_MASK                         BITFIELD(1, 1)
+#define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
-#define OMAP4430_PHASE2B_COMPLETED_MASK                         BITFIELD(2, 2)
+#define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
-#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          BITFIELD(20, 21)
+#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
-#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        BITFIELD(22, 23)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
-/* Used by CM_DYN_DEP_PRESCAL */
+/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
 #define OMAP4430_PRESCAL_SHIFT                                  0
-#define OMAP4430_PRESCAL_MASK                                   BITFIELD(0, 5)
+#define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
-/* Used by REVISION_CM2, REVISION_CM1 */
-#define OMAP4430_REV_SHIFT                                      0
-#define OMAP4430_REV_MASK                                       BITFIELD(0, 7)
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
 /*
- * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
+ * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
  */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
-#define OMAP4430_SAR_MODE_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
-#define OMAP4430_SCALE_FCLK_MASK                                BITFIELD(0, 0)
+#define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
-#define OMAP4430_SDMA_DYNDEP_MASK                               BITFIELD(11, 11)
+#define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
-#define OMAP4430_SDMA_STATDEP_MASK                              BITFIELD(11, 11)
+#define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
-#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          BITFIELD(10, 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 
 /*
- * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
-#define OMAP4430_STBYST_MASK                                    BITFIELD(18, 18)
+#define OMAP4430_STBYST_MASK                                    (1 << 18)
 
 /*
- * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB,
- * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
-#define OMAP4430_ST_DPLL_CLK_MASK                               BITFIELD(0, 0)
+#define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
- * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
-#define OMAP4430_ST_DPLL_CLKOUT_MASK                            BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
-/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
-#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          BITFIELD(11, 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
+ */
+#define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
-#define OMAP4430_SYS_CLKSEL_MASK                                BITFIELD(0, 2)
+#define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
-#define OMAP4430_TESLA_DYNDEP_MASK                              BITFIELD(1, 1)
+#define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
-#define OMAP4430_TESLA_STATDEP_MASK                             BITFIELD(1, 1)
+#define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
- * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
+ * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
+ * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
-#define OMAP4430_WINDOWSIZE_MASK                                BITFIELD(24, 27)
+#define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
deleted file mode 100644
index 721c3b66740a..000000000000
--- a/arch/arm/mach-omap2/cm.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * OMAP2/3 CM module functions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/atomic.h>
-
-#include <plat/common.h>
-
-#include "cm.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
-
-static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
-};
-
-/**
- * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
- * @prcm_mod: PRCM module offset
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
- * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
- *
- * XXX document
- */
-int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
-{
-        int ena = 0, i = 0;
-        u8 cm_idlest_reg;
-        u32 mask;
-
-        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
-                return -EINVAL;
-
-        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
-
-        mask = 1 << idlest_shift;
-
-        if (cpu_is_omap24xx())
-                ena = mask;
-        else if (cpu_is_omap34xx())
-                ena = 0;
-        else
-                BUG();
-
-        /* XXX should be OMAP2 CM */
-        omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
-                          MAX_MODULE_READY_TIME, i);
-
-        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
-}
-
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index a02ca30423dc..a7bc096bd407 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -1,8 +1,5 @@
-#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
-#define __ARCH_ASM_MACH_OMAP2_CM_H
-
 /*
- * OMAP2/3 Clock Management (CM) register definitions
+ * OMAP2+ Clock Management prototypes
  *
  * Copyright (C) 2007-2009 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
@@ -13,136 +10,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
-#include "prcm-common.h"
-
-#define OMAP2420_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
-#define OMAP2430_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
-#define OMAP34XX_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
-#define OMAP44XX_CM1_REGADDR(module, reg)                               \
-                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
-#define OMAP44XX_CM2_REGADDR(module, reg)                               \
-                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
-
-#include "cm44xx.h"
-
-/*
- * Architecture-specific global CM registers
- * Use cm_{read,write}_reg() with these registers.
- * These registers appear once per CM module.
- */
-
-#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
-
-#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
-#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
-/*
- * Module specific CM registers from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* Common between 24xx and 34xx */
-
-#define CM_FCLKEN                                       0x0000
-#define CM_FCLKEN1                                      CM_FCLKEN
-#define CM_CLKEN                                        CM_FCLKEN
-#define CM_ICLKEN                                       0x0010
-#define CM_ICLKEN1                                      CM_ICLKEN
-#define CM_ICLKEN2                                      0x0014
-#define CM_ICLKEN3                                      0x0018
-#define CM_IDLEST                                       0x0020
-#define CM_IDLEST1                                      CM_IDLEST
-#define CM_IDLEST2                                      0x0024
-#define CM_AUTOIDLE                                     0x0030
-#define CM_AUTOIDLE1                                    CM_AUTOIDLE
-#define CM_AUTOIDLE2                                    0x0034
-#define CM_AUTOIDLE3                                    0x0038
-#define CM_CLKSEL                                       0x0040
-#define CM_CLKSEL1                                      CM_CLKSEL
-#define CM_CLKSEL2                                      0x0044
-#define OMAP2_CM_CLKSTCTRL                              0x0048
-#define OMAP4_CM_CLKSTCTRL                              0x0000
-
-
-/* Architecture-specific registers */
-
-#define OMAP24XX_CM_FCLKEN2                             0x0004
-#define OMAP24XX_CM_ICLKEN4                             0x001c
-#define OMAP24XX_CM_AUTOIDLE4                           0x003c
-
-#define OMAP2430_CM_IDLEST3                             0x0028
-
-#define OMAP3430_CM_CLKEN_PLL                           0x0004
-#define OMAP3430ES2_CM_CLKEN2                           0x0004
-#define OMAP3430ES2_CM_FCLKEN3                          0x0008
-#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
-#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
-#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
-#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
-#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
-#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
-#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
-#define OMAP3430_CM_CLKSTST                             0x004c
-#define OMAP3430ES2_CM_CLKSEL4                          0x004c
-#define OMAP3430ES2_CM_CLKSEL5                          0x0050
-#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
-#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
-
-/* CM2.CEFUSE_CM2 register offsets */
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL                      0
-#define OMAP4430_MODULEMODE_SWCTRL                      1
-
-/* Clock management domain register get/set */
-
-#ifndef __ASSEMBLER__
-
-extern u32 cm_read_mod_reg(s16 module, u16 idx);
-extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
-extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-
-extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
-                                      u8 idlest_shift);
-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
-
-static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return cm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
-#endif
-
-/* CM register bits shared between 24XX and 3430 */
-
-/* CM_CLKSEL_GFX */
-#define OMAP_CLKSEL_GFX_SHIFT                           0
-#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
-
-/* CM_ICLKEN_GFX */
-#define OMAP_EN_GFX_SHIFT                               0
-#define OMAP_EN_GFX_MASK                                (1 << 0)
-
-/* CM_IDLEST_GFX */
-#define OMAP_ST_GFX_MASK                                (1 << 0)
-
-
-/* CM_IDLEST indicator */
-#define OMAP24XX_CM_IDLEST_VAL          0
-#define OMAP34XX_CM_IDLEST_VAL          1
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
 
 /*
  * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
new file mode 100644
index 000000000000..e2d7a56b2ad6
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -0,0 +1,261 @@
+/*
+ * OMAP44xx CM1 instance offset macros
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
+
+/* CM1 base address */
+#define OMAP4430_CM1_BASE               0x4a004000
+
+#define OMAP44XX_CM1_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
+
+/* CM1 instances */
+#define OMAP4430_CM1_OCP_SOCKET_INST    0x0000
+#define OMAP4430_CM1_CKGEN_INST         0x0100
+#define OMAP4430_CM1_MPU_INST           0x0300
+#define OMAP4430_CM1_TESLA_INST         0x0400
+#define OMAP4430_CM1_ABE_INST           0x0500
+#define OMAP4430_CM1_RESTORE_INST       0x0e00
+#define OMAP4430_CM1_INSTR_INST         0x0f00
+
+/* CM1 clockdomain register offsets (from instance start) */
+#define OMAP4430_CM1_ABE_ABE_CDOFFS             0x0000
+#define OMAP4430_CM1_MPU_MPU_CDOFFS             0x0000
+#define OMAP4430_CM1_TESLA_TESLA_CDOFFS         0x0000
+
+/* CM1 */
+
+/* CM1.OCP_SOCKET_CM1 register offsets */
+#define OMAP4_REVISION_CM1_OFFSET                       0x0000
+#define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
+
+/* CM1.CKGEN_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
+#define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
+#define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
+#define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
+#define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
+#define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
+#define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
+#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
+#define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
+#define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
+#define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
+#define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
+#define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
+#define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
+#define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
+#define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET       0x004c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
+#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
+#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
+#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
+#define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
+#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
+#define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
+#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
+#define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
+#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
+#define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
+#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
+#define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET                0x008c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
+#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
+#define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
+#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
+#define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
+#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
+#define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
+#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
+#define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
+#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
+#define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
+#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
+#define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
+#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
+#define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET                0x00cc
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
+#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
+#define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
+#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
+#define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
+#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
+#define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
+#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
+#define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
+#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
+#define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
+#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
+#define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
+#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
+#define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET                0x010c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
+#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
+#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
+#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
+#define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
+#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
+#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
+#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
+#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
+#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
+#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
+#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
+#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
+#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
+#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
+#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
+#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET     0x014c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
+#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
+#define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
+#define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
+#define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
+
+/* CM1.MPU_CM1 register offsets */
+#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
+#define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
+#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
+#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
+
+/* CM1.TESLA_CM1 register offsets */
+#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
+#define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
+#define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
+#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
+#define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
+#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
+#define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
+
+/* CM1.ABE_CM1 register offsets */
+#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
+#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
+#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
+#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
+#define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
+#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
+#define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
+#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
+#define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
+#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
+#define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
+#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
+#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
+#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
+#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
+#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
+#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
+#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
+#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
+#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
+#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
+#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
+#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
+#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
+#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
+#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
+#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
+#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
+#define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
+
+/* CM1.RESTORE_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
+#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
+#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
+#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
+#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
+#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
+#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET       0x0024
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
+#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
+#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
+#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
+#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
+#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
+
+/* Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
new file mode 100644
index 000000000000..aa4745044065
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -0,0 +1,508 @@
+/*
+ * OMAP44xx CM2 instance offset macros
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
+
+/* CM2 base address */
+#define OMAP4430_CM2_BASE               0x4a008000
+
+#define OMAP44XX_CM2_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
+
+/* CM2 instances */
+#define OMAP4430_CM2_OCP_SOCKET_INST    0x0000
+#define OMAP4430_CM2_CKGEN_INST         0x0100
+#define OMAP4430_CM2_ALWAYS_ON_INST     0x0600
+#define OMAP4430_CM2_CORE_INST          0x0700
+#define OMAP4430_CM2_IVAHD_INST         0x0f00
+#define OMAP4430_CM2_CAM_INST           0x1000
+#define OMAP4430_CM2_DSS_INST           0x1100
+#define OMAP4430_CM2_GFX_INST           0x1200
+#define OMAP4430_CM2_L3INIT_INST                0x1300
+#define OMAP4430_CM2_L4PER_INST         0x1400
+#define OMAP4430_CM2_CEFUSE_INST                0x1600
+#define OMAP4430_CM2_RESTORE_INST       0x1e00
+#define OMAP4430_CM2_INSTR_INST         0x1f00
+
+/* CM2 clockdomain register offsets (from instance start) */
+#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS     0x0000
+#define OMAP4430_CM2_CORE_L3_1_CDOFFS           0x0000
+#define OMAP4430_CM2_CORE_L3_2_CDOFFS           0x0100
+#define OMAP4430_CM2_CORE_DUCATI_CDOFFS         0x0200
+#define OMAP4430_CM2_CORE_SDMA_CDOFFS           0x0300
+#define OMAP4430_CM2_CORE_MEMIF_CDOFFS          0x0400
+#define OMAP4430_CM2_CORE_D2D_CDOFFS            0x0500
+#define OMAP4430_CM2_CORE_L4CFG_CDOFFS          0x0600
+#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS        0x0700
+#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS         0x0000
+#define OMAP4430_CM2_CAM_CAM_CDOFFS             0x0000
+#define OMAP4430_CM2_DSS_DSS_CDOFFS             0x0000
+#define OMAP4430_CM2_GFX_GFX_CDOFFS             0x0000
+#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS       0x0000
+#define OMAP4430_CM2_L4PER_L4PER_CDOFFS         0x0000
+#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS         0x0180
+#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS       0x0000
+
+
+/* CM2 */
+
+/* CM2.OCP_SOCKET_CM2 register offsets */
+#define OMAP4_REVISION_CM2_OFFSET                       0x0000
+#define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
+
+/* CM2.CKGEN_CM2 register offsets */
+#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET          0x0000
+#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
+#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET                0x0004
+#define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
+#define OMAP4_CM_SCALE_FCLK_OFFSET                      0x0008
+#define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
+#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET                 0x0010
+#define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
+#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET                 0x0014
+#define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
+#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET                 0x0018
+#define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
+#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET                 0x001c
+#define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
+#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET               0x0024
+#define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
+#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET             0x0028
+#define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
+#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET             0x002c
+#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
+#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET               0x0030
+#define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
+#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET                0x0038
+#define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
+#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET                0x0040
+#define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
+#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET                 0x0044
+#define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
+#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET               0x0048
+#define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
+#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET                 0x004c
+#define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
+#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET                 0x0050
+#define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
+#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET                 0x0054
+#define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
+#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET                 0x0058
+#define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
+#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET                 0x005c
+#define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
+#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET                 0x0060
+#define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
+#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET                 0x0064
+#define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET                0x006c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
+#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
+#define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
+#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
+#define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
+#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET               0x0088
+#define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
+#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET                 0x008c
+#define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
+#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET                 0x0090
+#define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET                0x00ac
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
+#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
+#define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
+#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
+#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
+#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET              0x00c4
+#define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
+#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET            0x00c8
+#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
+#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET              0x00cc
+#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
+#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET              0x00d0
+#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET     0x00ec
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
+
+/* CM2.ALWAYS_ON_CM2 register offsets */
+#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
+#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET           0x0020
+#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
+#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET            0x0028
+#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
+#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET            0x0030
+#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
+#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
+#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
+#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET            0x0040
+#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
+
+/* CM2.CORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
+#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET                 0x0008
+#define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
+#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET               0x0020
+#define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
+#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET                  0x0100
+#define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
+#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET                 0x0108
+#define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
+#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET               0x0120
+#define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
+#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET               0x0128
+#define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
+#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET           0x0130
+#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
+#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET                0x0200
+#define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
+#define OMAP4_CM_DUCATI_STATICDEP_OFFSET                0x0204
+#define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
+#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET               0x0208
+#define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
+#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET           0x0220
+#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
+#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET                  0x0300
+#define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
+#define OMAP4_CM_SDMA_STATICDEP_OFFSET                  0x0304
+#define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
+#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET                 0x0308
+#define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
+#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET               0x0320
+#define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET                 0x0400
+#define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
+#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET               0x0420
+#define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
+#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET           0x0428
+#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
+#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET            0x0430
+#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
+#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET            0x0438
+#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
+#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET               0x0440
+#define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
+#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET           0x0450
+#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
+#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET           0x0458
+#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
+#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET             0x0460
+#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
+#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET                   0x0500
+#define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
+#define OMAP4_CM_D2D_STATICDEP_OFFSET                   0x0504
+#define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
+#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET                  0x0508
+#define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
+#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
+#define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
+#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET          0x0528
+#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
+#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
+#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
+#define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET                0x0608
+#define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
+#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET            0x0620
+#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
+#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET            0x0628
+#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
+#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET           0x0630
+#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
+#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET           0x0638
+#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
+#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET               0x0700
+#define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET            0x0720
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET        0x0728
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET         0x0740
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
+
+/* CM2.IVAHD_CM2 register offsets */
+#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
+#define OMAP4_CM_IVAHD_STATICDEP_OFFSET                 0x0004
+#define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
+#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET                0x0008
+#define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
+#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET             0x0020
+#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
+#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET               0x0028
+#define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
+
+/* CM2.CAM_CM2 register offsets */
+#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
+#define OMAP4_CM_CAM_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
+#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
+#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
+#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET                0x0028
+#define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
+
+/* CM2.DSS_CM2 register offsets */
+#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
+#define OMAP4_CM_DSS_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
+#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
+#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
+#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET               0x0028
+#define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
+
+/* CM2.GFX_CM2 register offsets */
+#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
+#define OMAP4_CM_GFX_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
+#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
+#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
+
+/* CM2.L3INIT_CM2 register offsets */
+#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET                0x0000
+#define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
+#define OMAP4_CM_L3INIT_STATICDEP_OFFSET                0x0004
+#define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
+#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET               0x0008
+#define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
+#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET             0x0028
+#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
+#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET             0x0030
+#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
+#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET              0x0038
+#define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
+#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET          0x0040
+#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET         0x0058
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
+#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET          0x0060
+#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET          0x0068
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
+#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET            0x0078
+#define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
+#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET             0x0080
+#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
+#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET             0x0088
+#define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
+#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET            0x0090
+#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
+#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET           0x0098
+#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
+#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET            0x00a8
+#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
+#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET             0x00c0
+#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
+#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET             0x00c8
+#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
+#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET      0x00d0
+#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
+#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET    0x00e0
+#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
+
+/* CM2.L4PER_CM2 register offsets */
+#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
+#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET                0x0008
+#define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
+#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET               0x0020
+#define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
+#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET         0x0028
+#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
+#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET         0x0030
+#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
+#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET          0x0038
+#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
+#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET          0x0040
+#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
+#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET          0x0048
+#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
+#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET          0x0050
+#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
+#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET               0x0058
+#define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET             0x0060
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET             0x0068
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET             0x0070
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET             0x0078
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET             0x0080
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
+#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET             0x0088
+#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
+#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET             0x0090
+#define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
+#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET             0x0098
+#define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
+#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET              0x00a0
+#define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
+#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET              0x00a8
+#define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
+#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET              0x00b0
+#define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
+#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET              0x00b8
+#define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
+#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET             0x00c0
+#define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
+#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET            0x00d0
+#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
+#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET            0x00d8
+#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
+#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET            0x00e0
+#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
+#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET             0x00e8
+#define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
+#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET            0x00f0
+#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
+#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET            0x00f8
+#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
+#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET            0x0100
+#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
+#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET            0x0108
+#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
+#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET            0x0120
+#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
+#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET            0x0128
+#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
+#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET           0x0130
+#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
+#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET          0x0138
+#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
+#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET             0x0140
+#define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
+#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET             0x0148
+#define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
+#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET             0x0150
+#define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
+#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET             0x0158
+#define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
+#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET            0x0160
+#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
+#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET              0x0168
+#define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
+#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET                 0x0180
+#define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
+#define OMAP4_CM_L4SEC_STATICDEP_OFFSET                 0x0184
+#define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
+#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET                0x0188
+#define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
+#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET              0x01a0
+#define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
+#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET              0x01a8
+#define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
+#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET           0x01b0
+#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
+#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET          0x01b8
+#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
+#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET               0x01c0
+#define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
+#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET          0x01c8
+#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
+#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET         0x01d8
+#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
+
+/* CM2.CEFUSE_CM2 register offsets */
+#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET                0x0000
+#define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
+#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
+#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
+
+/* CM2.RESTORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET          0x0000
+#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
+#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET          0x0004
+#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET         0x0008
+#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET         0x000c
+#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
+#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET         0x0010
+#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
+#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET    0x0018
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET   0x0024
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
+#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET           0x0028
+#define OMAP4430_CM_D2D_STATICDEP_RESTORE               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
+#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET         0x002c
+#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
+#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET         0x0030
+#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
+#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET          0x0034
+#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET        0x0038
+#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
+#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET        0x003c
+#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET     0x0040
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET     0x0044
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET     0x0048
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET     0x004c
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET     0x0050
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET  0x0058
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
+#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET          0x005c
+#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
+
+/* Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
new file mode 100644
index 000000000000..38830d8d4783
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -0,0 +1,557 @@
+/*
+ * OMAP2/3 CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+#define DPLL_AUTOIDLE_DISABLE                           0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
+
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
+#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
+#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
+
+static const u8 cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+};
+
+u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(cm_base + module + idx);
+}
+
+void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, cm_base + module + idx);
+}
+
+/* Read-modify-write a register in a CM module. Caller must lock */
+u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_cm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+
+u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+
+/*
+ *
+ */
+
+static void _write_clktrctrl(u8 c, s16 module, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= ~mask;
+        v |= c << __ffs(mask);
+        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
+}
+
+bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+{
+        u32 v;
+        bool ret = 0;
+
+        BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
+
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        if (cpu_is_omap24xx())
+                ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+        else
+                ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+
+        return ret;
+}
+
+void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+
+void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+
+void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+
+void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+
+void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
+}
+
+void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
+}
+
+/*
+ * DPLL autoidle control
+ */
+
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~OMAP24XX_AUTO_DPLL_MASK;
+        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
+
+/*
+ * APLL autoidle control
+ */
+
+static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~mask;
+        v |= m << __ffs(mask);
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_apll54_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+
+/*
+ *
+ */
+
+/**
+ * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * XXX document
+ */
+int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
+                return -EINVAL;
+
+        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
+
+        mask = 1 << idlest_shift;
+
+        if (cpu_is_omap24xx())
+                ena = mask;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
+                          MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/*
+ * Context save/restore code - OMAP3 only
+ */
+#ifdef CONFIG_ARCH_OMAP3
+struct omap3_cm_regs {
+        u32 iva2_cm_clksel1;
+        u32 iva2_cm_clksel2;
+        u32 cm_sysconfig;
+        u32 sgx_cm_clksel;
+        u32 dss_cm_clksel;
+        u32 cam_cm_clksel;
+        u32 per_cm_clksel;
+        u32 emu_cm_clksel;
+        u32 emu_cm_clkstctrl;
+        u32 pll_cm_autoidle;
+        u32 pll_cm_autoidle2;
+        u32 pll_cm_clksel4;
+        u32 pll_cm_clksel5;
+        u32 pll_cm_clken2;
+        u32 cm_polctrl;
+        u32 iva2_cm_fclken;
+        u32 iva2_cm_clken_pll;
+        u32 core_cm_fclken1;
+        u32 core_cm_fclken3;
+        u32 sgx_cm_fclken;
+        u32 wkup_cm_fclken;
+        u32 dss_cm_fclken;
+        u32 cam_cm_fclken;
+        u32 per_cm_fclken;
+        u32 usbhost_cm_fclken;
+        u32 core_cm_iclken1;
+        u32 core_cm_iclken2;
+        u32 core_cm_iclken3;
+        u32 sgx_cm_iclken;
+        u32 wkup_cm_iclken;
+        u32 dss_cm_iclken;
+        u32 cam_cm_iclken;
+        u32 per_cm_iclken;
+        u32 usbhost_cm_iclken;
+        u32 iva2_cm_autoidle2;
+        u32 mpu_cm_autoidle2;
+        u32 iva2_cm_clkstctrl;
+        u32 mpu_cm_clkstctrl;
+        u32 core_cm_clkstctrl;
+        u32 sgx_cm_clkstctrl;
+        u32 dss_cm_clkstctrl;
+        u32 cam_cm_clkstctrl;
+        u32 per_cm_clkstctrl;
+        u32 neon_cm_clkstctrl;
+        u32 usbhost_cm_clkstctrl;
+        u32 core_cm_autoidle1;
+        u32 core_cm_autoidle2;
+        u32 core_cm_autoidle3;
+        u32 wkup_cm_autoidle;
+        u32 dss_cm_autoidle;
+        u32 cam_cm_autoidle;
+        u32 per_cm_autoidle;
+        u32 usbhost_cm_autoidle;
+        u32 sgx_cm_sleepdep;
+        u32 dss_cm_sleepdep;
+        u32 cam_cm_sleepdep;
+        u32 per_cm_sleepdep;
+        u32 usbhost_cm_sleepdep;
+        u32 cm_clkout_ctrl;
+};
+
+static struct omap3_cm_regs cm_context;
+
+void omap3_cm_save_context(void)
+{
+        cm_context.iva2_cm_clksel1 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
+        cm_context.iva2_cm_clksel2 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
+        cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+        cm_context.sgx_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+        cm_context.dss_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
+        cm_context.cam_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
+        cm_context.per_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
+        cm_context.emu_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
+        cm_context.emu_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
+         * In this case, even though this register has been saved in
+         * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
+         * by ourselves. So, we need to save it anyway.
+         */
+        cm_context.pll_cm_autoidle =
+                omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        cm_context.pll_cm_autoidle2 =
+                omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
+        cm_context.pll_cm_clksel4 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
+        cm_context.pll_cm_clksel5 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
+        cm_context.pll_cm_clken2 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
+        cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
+        cm_context.iva2_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
+        cm_context.iva2_cm_clken_pll =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
+        cm_context.core_cm_fclken1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        cm_context.core_cm_fclken3 =
+                omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+        cm_context.sgx_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
+        cm_context.wkup_cm_fclken =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+        cm_context.dss_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
+        cm_context.cam_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
+        cm_context.per_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
+        cm_context.usbhost_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
+        cm_context.core_cm_iclken1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+        cm_context.core_cm_iclken2 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
+        cm_context.core_cm_iclken3 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+        cm_context.sgx_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
+        cm_context.wkup_cm_iclken =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+        cm_context.dss_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
+        cm_context.cam_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
+        cm_context.per_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
+        cm_context.usbhost_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
+        cm_context.iva2_cm_autoidle2 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+        cm_context.mpu_cm_autoidle2 =
+                omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
+        cm_context.iva2_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.mpu_cm_clkstctrl =
+                omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.core_cm_clkstctrl =
+                omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.sgx_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.dss_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.cam_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.per_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.neon_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.usbhost_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                      OMAP2_CM_CLKSTCTRL);
+        cm_context.core_cm_autoidle1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
+        cm_context.core_cm_autoidle2 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
+        cm_context.core_cm_autoidle3 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
+        cm_context.wkup_cm_autoidle =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
+        cm_context.dss_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
+        cm_context.cam_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
+        cm_context.per_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        cm_context.usbhost_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
+        cm_context.sgx_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+                                      OMAP3430_CM_SLEEPDEP);
+        cm_context.dss_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.cam_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.per_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.usbhost_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                      OMAP3430_CM_SLEEPDEP);
+        cm_context.cm_clkout_ctrl =
+                omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
+                                      OMAP3_CM_CLKOUT_CTRL_OFFSET);
+}
+
+void omap3_cm_restore_context(void)
+{
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
+                               CM_CLKSEL1);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
+                               CM_CLKSEL2);
+        __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
+                               CM_CLKSEL1);
+        omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
+         * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
+         */
+        omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
+                               OMAP3430ES2_CM_CLKSEL4);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
+                               OMAP3430ES2_CM_CLKSEL5);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
+                               OMAP3430ES2_CM_CLKEN2);
+        __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
+                               OMAP3430_CM_CLKEN_PLL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
+                               CM_FCLKEN1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
+                               OMAP3430ES2_CM_FCLKEN3);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
+                               OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
+                               CM_ICLKEN1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
+                               CM_ICLKEN2);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
+                               CM_ICLKEN3);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
+                               OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
+                               OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
+                               CM_AUTOIDLE1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
+                               CM_AUTOIDLE3);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
+                               OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
+                               OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
+                               OMAP3_CM_CLKOUT_CTRL_OFFSET);
+}
+#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
new file mode 100644
index 000000000000..088bbad73db5
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -0,0 +1,155 @@
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
+#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
+
+#include "prcm-common.h"
+
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+
+
+/*
+ * OMAP3-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between OMAP2 and OMAP3 */
+
+#define CM_FCLKEN                                       0x0000
+#define CM_FCLKEN1                                      CM_FCLKEN
+#define CM_CLKEN                                        CM_FCLKEN
+#define CM_ICLKEN                                       0x0010
+#define CM_ICLKEN1                                      CM_ICLKEN
+#define CM_ICLKEN2                                      0x0014
+#define CM_ICLKEN3                                      0x0018
+#define CM_IDLEST                                       0x0020
+#define CM_IDLEST1                                      CM_IDLEST
+#define CM_IDLEST2                                      0x0024
+#define CM_AUTOIDLE                                     0x0030
+#define CM_AUTOIDLE1                                    CM_AUTOIDLE
+#define CM_AUTOIDLE2                                    0x0034
+#define CM_AUTOIDLE3                                    0x0038
+#define CM_CLKSEL                                       0x0040
+#define CM_CLKSEL1                                      CM_CLKSEL
+#define CM_CLKSEL2                                      0x0044
+#define OMAP2_CM_CLKSTCTRL                              0x0048
+
+/* OMAP2-specific register offsets */
+
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+
+#define OMAP2430_CM_IDLEST3                             0x0028
+
+/* OMAP3-specific register offsets */
+
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+
+
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+
+#define OMAP24XX_CM_IDLEST_VAL                          0
+#define OMAP34XX_CM_IDLEST_VAL                          1
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+
+extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
+extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
+extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                      u8 idlest_shift);
+extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+
+extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+
+extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+
+extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
+extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT                           0
+#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT                               0
+#define OMAP_EN_GFX_MASK                                (1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX_MASK                                (1 << 0)
+
+
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+extern void omap3_cm_save_context(void);
+extern void omap3_cm_restore_context(void);
+# endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
new file mode 100644
index 000000000000..e96f53ea01a1
--- /dev/null
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -0,0 +1,52 @@
+/*
+ * OMAP4 CM1, CM2 module low-level functions
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * These functions are intended to be used only by the cminst44xx.c file.
+ * XXX Perhaps we should just move them there and make them static.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm-regbits-44xx.h"
+
+/* CM1 hardware module low-level functions */
+
+/* Read a register in CM1 */
+u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
+}
+
+/* Write into a register in CM1 */
+void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
+}
+
+/* Read a register in CM2 */
+u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
+}
+
+/* Write into a register in CM2 */
+void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
+}
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 336d94889e5b..0b87ec82b41c 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,581 +1,32 @@
 /*
- * OMAP44xx CM1 & CM2 instance offset macros
+ * OMAP4 Clock Management (CM) definitions
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
+ * Written by Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * OMAP4 has two separate CM blocks, CM1 and CM2.  This file contains
+ * macros and function prototypes that are applicable to both.
  */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H
+#define __ARCH_ASM_MACH_OMAP2_CM44XX_H
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
-
-
-/* CM1 */
-
-/* CM1.OCP_SOCKET_CM1 register offsets */
-#define OMAP4_REVISION_CM1_OFFSET                       0x0000
-#define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
-#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
-#define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
-
-/* CM1.CKGEN_CM1 register offsets */
-#define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
-#define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
-#define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
-#define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
-#define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
-#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
-#define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
-#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
-#define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
-#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
-#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
-#define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
-#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
-#define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
-#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
-#define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
-#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
-#define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
-#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
-#define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
-#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
-#define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
-#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
-#define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET        0x004c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
-#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
-#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
-#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
-#define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
-#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
-#define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
-#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
-#define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
-#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
-#define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
-#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
-#define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET         0x008c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
-#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
-#define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
-#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
-#define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
-#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
-#define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
-#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
-#define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
-#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
-#define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
-#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
-#define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
-#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
-#define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET         0x00cc
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
-#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
-#define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
-#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
-#define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
-#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
-#define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
-#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
-#define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
-#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
-#define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
-#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
-#define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
-#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
-#define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET         0x010c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
-#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
-#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
-#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
-#define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
-#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
-#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
-#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
-#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
-#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
-#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
-#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
-#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
-#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
-#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
-#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
-#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET      0x014c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
-#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
-#define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
-#define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
-#define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
-
-/* CM1.MPU_CM1 register offsets */
-#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
-#define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
-#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
-#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
-
-/* CM1.TESLA_CM1 register offsets */
-#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
-#define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
-#define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
-#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
-#define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
-#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
-
-/* CM1.ABE_CM1 register offsets */
-#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
-#define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
-#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
-#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
-#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
-#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
-#define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
-#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
-#define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
-#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
-#define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
-#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
-#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
-#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
-#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
-#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
-#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
-#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
-#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
-#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
-#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
-#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
-#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
-#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
-#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
-#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
-#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
-#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
-#define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
-
-/* CM2 */
-
-/* CM2.OCP_SOCKET_CM2 register offsets */
-#define OMAP4_REVISION_CM2_OFFSET                       0x0000
-#define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
-#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET           0x0040
-#define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
-
-/* CM2.CKGEN_CM2 register offsets */
-#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET          0x0000
-#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET                0x0004
-#define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
-#define OMAP4_CM_SCALE_FCLK_OFFSET                      0x0008
-#define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
-#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET                 0x0010
-#define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
-#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET                 0x0014
-#define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
-#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET                 0x0018
-#define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
-#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET                 0x001c
-#define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
-#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET               0x0024
-#define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
-#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET             0x0028
-#define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
-#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET             0x002c
-#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
-#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET               0x0030
-#define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
-#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET                0x0038
-#define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
-#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET                0x0040
-#define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
-#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET                 0x0044
-#define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
-#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET               0x0048
-#define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
-#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET                 0x004c
-#define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
-#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET                 0x0050
-#define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
-#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET                 0x0054
-#define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
-#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET                 0x0058
-#define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
-#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET                 0x005c
-#define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
-#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET                 0x0060
-#define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
-#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET                 0x0064
-#define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
-#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET           0x0070
-#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
-#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
-#define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
-#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
-#define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
-#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET               0x0088
-#define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
-#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET                 0x008c
-#define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
-#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET                 0x0090
-#define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET         0x00ac
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
-#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
-#define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
-#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
-#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
-#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET              0x00c4
-#define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
-#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET            0x00c8
-#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
-#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET              0x00cc
-#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
-#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET              0x00d0
-#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET      0x00ec
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
-
-/* CM2.ALWAYS_ON_CM2 register offsets */
-#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
-#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET           0x0020
-#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
-#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET            0x0028
-#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
-#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET            0x0030
-#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
-#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
-#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
-
-/* CM2.CORE_CM2 register offsets */
-#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
-#define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
-#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET                 0x0008
-#define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
-#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET               0x0020
-#define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
-#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET                  0x0100
-#define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
-#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET                 0x0108
-#define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
-#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET               0x0120
-#define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
-#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET               0x0128
-#define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
-#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET           0x0130
-#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
-#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET                0x0200
-#define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
-#define OMAP4_CM_DUCATI_STATICDEP_OFFSET                0x0204
-#define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
-#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET               0x0208
-#define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
-#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET           0x0220
-#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
-#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET                  0x0300
-#define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
-#define OMAP4_CM_SDMA_STATICDEP_OFFSET                  0x0304
-#define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
-#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET                 0x0308
-#define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
-#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET               0x0320
-#define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
-#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET                 0x0400
-#define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
-#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET               0x0420
-#define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
-#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET           0x0428
-#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
-#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET            0x0430
-#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
-#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET            0x0438
-#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
-#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET               0x0440
-#define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
-#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET           0x0450
-#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
-#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET           0x0458
-#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
-#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET             0x0460
-#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
-#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET                   0x0500
-#define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
-#define OMAP4_CM_D2D_STATICDEP_OFFSET                   0x0504
-#define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
-#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET                  0x0508
-#define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
-#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
-#define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
-#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET           0x0528
-#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
-#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
-#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
-#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
-#define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
-#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET                0x0608
-#define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
-#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET            0x0620
-#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
-#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET            0x0628
-#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
-#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET           0x0630
-#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
-#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET           0x0638
-#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
-#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET               0x0700
-#define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
-#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET            0x0720
-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
-#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET        0x0728
-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
-#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET         0x0740
-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
-
-/* CM2.IVAHD_CM2 register offsets */
-#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
-#define OMAP4_CM_IVAHD_STATICDEP_OFFSET                 0x0004
-#define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
-#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET                0x0008
-#define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
-#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
-#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
-
-/* CM2.CAM_CM2 register offsets */
-#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
-#define OMAP4_CM_CAM_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
-#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
-#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
-#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET                0x0028
-#define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
 
-/* CM2.DSS_CM2 register offsets */
-#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
-#define OMAP4_CM_DSS_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
-#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
-#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
-#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
+#include "prcm-common.h"
+#include "cm.h"
 
-/* CM2.GFX_CM2 register offsets */
-#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
-#define OMAP4_CM_GFX_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
-#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
-#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
+#define OMAP4_CM_CLKSTCTRL                              0x0000
+#define OMAP4_CM_STATICDEP                              0x0004
 
-/* CM2.L3INIT_CM2 register offsets */
-#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET                0x0000
-#define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
-#define OMAP4_CM_L3INIT_STATICDEP_OFFSET                0x0004
-#define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
-#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET               0x0008
-#define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
-#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET             0x0028
-#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
-#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET             0x0030
-#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
-#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET              0x0038
-#define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
-#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
-#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET         0x0058
-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
-#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET          0x0060
-#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
-#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET          0x0068
-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
-#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET            0x0078
-#define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
-#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET             0x0080
-#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
-#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET             0x0088
-#define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
-#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET            0x0090
-#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
-#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET           0x0098
-#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
-#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET            0x00a8
-#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
-#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET             0x00c0
-#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
-#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET             0x00c8
-#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
-#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET      0x00d0
-#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
-#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET    0x00e0
-#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
+/* Function prototypes */
+# ifndef __ASSEMBLER__
 
-/* CM2.L4PER_CM2 register offsets */
-#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
-#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET                0x0008
-#define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
-#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET               0x0020
-#define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
-#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET         0x0028
-#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
-#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET         0x0030
-#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
-#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET          0x0038
-#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
-#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
-#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET          0x0048
-#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
-#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET          0x0050
-#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
-#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET               0x0058
-#define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
-#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET             0x0060
-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
-#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET             0x0068
-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
-#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET             0x0070
-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
-#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET             0x0078
-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
-#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET             0x0080
-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
-#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET             0x0088
-#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
-#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET             0x0090
-#define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
-#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET             0x0098
-#define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
-#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET              0x00a0
-#define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
-#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET              0x00a8
-#define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
-#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET              0x00b0
-#define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
-#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET              0x00b8
-#define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
-#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET             0x00c0
-#define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
-#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET            0x00d0
-#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
-#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET            0x00d8
-#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
-#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET            0x00e0
-#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
-#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET             0x00e8
-#define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
-#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET            0x00f0
-#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
-#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET            0x00f8
-#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
-#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET            0x0100
-#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
-#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET            0x0108
-#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
-#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET            0x0120
-#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
-#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET            0x0128
-#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
-#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET           0x0130
-#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
-#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET          0x0138
-#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
-#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET             0x0140
-#define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
-#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET             0x0148
-#define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
-#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET             0x0150
-#define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
-#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET             0x0158
-#define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
-#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET            0x0160
-#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
-#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET              0x0168
-#define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
-#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET                 0x0180
-#define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
-#define OMAP4_CM_L4SEC_STATICDEP_OFFSET                 0x0184
-#define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
-#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET                0x0188
-#define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
-#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET              0x01a0
-#define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
-#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET              0x01a8
-#define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
-#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET           0x01b0
-#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
-#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET          0x01b8
-#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
-#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET               0x01c0
-#define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
-#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET          0x01c8
-#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
-#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET         0x01d8
-#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
+extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
 
-/* CM2.CEFUSE_CM2 register offsets */
-#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET                0x0000
-#define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
-#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
-#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
+# endif
 #endif
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
deleted file mode 100644
index b101091e95d6..000000000000
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * OMAP4 CM module functions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/atomic.h>
-
-#include <plat/common.h>
-
-#include "cm.h"
-#include "cm-regbits-44xx.h"
-
-/**
- * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
- * @clkctrl_reg: CLKCTRL module address
- *
- * Wait for the module IDLEST to be functional. If the idle state is in any
- * the non functional state (trans, idle or disabled), module and thus the
- * sysconfig cannot be accessed and will probably lead to an "imprecise
- * external abort"
- *
- * Module idle state:
- *   0x0 func:     Module is fully functional, including OCP
- *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
- *                 abortion
- *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
- *                 using separate functional clock
- *   0x3 disabled: Module is disabled and cannot be accessed
- *
- * TODO: Need to handle module accessible in idle state
- */
-int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
-{
-        int i = 0;
-
-        if (!clkctrl_reg)
-                return 0;
-
-        omap_test_timeout(((__raw_readl(clkctrl_reg) &
-                            OMAP4430_IDLEST_MASK) == 0),
-                          MAX_MODULE_READY_TIME, i);
-
-        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
-}
-
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
new file mode 100644
index 000000000000..a482bfa0a954
--- /dev/null
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -0,0 +1,235 @@
+/*
+ * OMAP4 CM instance functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
+ * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
+ * the PRM hardware module.  What a mess...
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm44xx.h"
+#include "cminst44xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+#include "prcm44xx.h"
+#include "prm44xx.h"
+#include "prcm_mpu44xx.h"
+
+static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
+        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
+        [OMAP4430_CM1_PARTITION]                = OMAP4430_CM1_BASE,
+        [OMAP4430_CM2_PARTITION]                = OMAP4430_CM2_BASE,
+        [OMAP4430_SCRM_PARTITION]               = 0,
+        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
+};
+
+/* Read a register in a CM instance */
+u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_cm_bases[part]);
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+}
+
+/* Write into a register in a CM instance */
+void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_cm_bases[part]);
+        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+}
+
+/* Read-modify-write a register in CM1. Caller must lock */
+u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+                                   s16 idx)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, idx);
+        v &= ~mask;
+        v |= bits;
+        omap4_cminst_write_inst_reg(v, part, inst, idx);
+
+        return v;
+}
+
+u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
+{
+        return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
+}
+
+u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
+{
+        return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
+}
+
+u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/*
+ *
+ */
+
+/**
+ * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
+ * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
+ * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * @c must be the unshifted value for CLKTRCTRL - i.e., this function
+ * will handle the shift itself.
+ */
+static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+        v &= ~OMAP4430_CLKTRCTRL_MASK;
+        v |= c << OMAP4430_CLKTRCTRL_SHIFT;
+        omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+}
+
+/**
+ * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
+ * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
+ * is in hardware-supervised idle mode, or 0 otherwise.
+ */
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+        v &= OMAP4430_CLKTRCTRL_MASK;
+        v >>= OMAP4430_CLKTRCTRL_SHIFT;
+
+        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
+}
+
+/**
+ * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
+ * hardware-supervised idle mode.  No return value.
+ */
+void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
+}
+
+/**
+ * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
+ * software-supervised idle mode, i.e., controlled manually by the
+ * Linux OMAP clockdomain code.  No return value.
+ */
+void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
+}
+
+/**
+ * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
+ * No return value.
+ */
+void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+}
+
+/**
+ * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
+ * waking it up.  No return value.
+ */
+void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
+}
+
+/*
+ *
+ */
+
+/**
+ * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
+ * @clkctrl_reg: CLKCTRL module address
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+ *
+ * Module idle state:
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
+{
+        int i = 0;
+
+        if (!clkctrl_reg)
+                return 0;
+
+        omap_test_timeout((
+                ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
+                 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
+                  OMAP4430_IDLEST_SHIFT) == 0x2)),
+                MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
new file mode 100644
index 000000000000..2b32c181a2ee
--- /dev/null
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -0,0 +1,37 @@
+/*
+ * OMAP4 Clock Management (CM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
+#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
+
+extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+
+/*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+ */
+extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+                                           s16 inst, s16 idx);
+extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
+                                           s16 idx);
+extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
+                                           s16 idx);
+extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
+                                           u32 mask);
+
+extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
+
+#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
new file mode 100644
index 000000000000..94ccf464677b
--- /dev/null
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -0,0 +1,163 @@
+/*
+ * common-board-devices.c
+ *
+ * Copyright (C) 2011 CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c/twl.h>
+
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+
+#include <plat/i2c.h>
+#include <plat/mcspi.h>
+#include <plat/nand.h>
+
+#include "common-board-devices.h"
+
+static struct i2c_board_info __initdata pmic_i2c_board_info = {
+        .addr           = 0x48,
+        .flags          = I2C_CLIENT_WAKE,
+};
+
+void __init omap_pmic_init(int bus, u32 clkrate,
+                           const char *pmic_type, int pmic_irq,
+                           struct twl4030_platform_data *pmic_data)
+{
+        strncpy(pmic_i2c_board_info.type, pmic_type,
+                sizeof(pmic_i2c_board_info.type));
+        pmic_i2c_board_info.irq = pmic_irq;
+        pmic_i2c_board_info.platform_data = pmic_data;
+
+        omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
+}
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
+        defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+
+static struct ads7846_platform_data ads7846_config = {
+        .x_max                  = 0x0fff,
+        .y_max                  = 0x0fff,
+        .x_plate_ohms           = 180,
+        .pressure_max           = 255,
+        .debounce_max           = 10,
+        .debounce_tol           = 3,
+        .debounce_rep           = 1,
+        .gpio_pendown           = -EINVAL,
+        .keep_vref_on           = 1,
+};
+
+static struct spi_board_info ads7846_spi_board_info __initdata = {
+        .modalias               = "ads7846",
+        .bus_num                = -EINVAL,
+        .chip_select            = 0,
+        .max_speed_hz           = 1500000,
+        .controller_data        = &ads7846_mcspi_config,
+        .irq                    = -EINVAL,
+        .platform_data          = &ads7846_config,
+};
+
+void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+                              struct ads7846_platform_data *board_pdata)
+{
+        struct spi_board_info *spi_bi = &ads7846_spi_board_info;
+        int err;
+
+        if (board_pdata && board_pdata->get_pendown_state) {
+                err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
+                if (err) {
+                        pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
+                        return;
+                }
+                gpio_export(gpio_pendown, 0);
+
+                if (gpio_debounce)
+                        gpio_set_debounce(gpio_pendown, gpio_debounce);
+        }
+
+        ads7846_config.gpio_pendown = gpio_pendown;
+
+        spi_bi->bus_num = bus_num;
+        spi_bi->irq     = OMAP_GPIO_IRQ(gpio_pendown);
+
+        if (board_pdata)
+                spi_bi->platform_data = board_pdata;
+
+        spi_register_board_info(&ads7846_spi_board_info, 1);
+}
+#else
+void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+                              struct ads7846_platform_data *board_pdata)
+{
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+static struct omap_nand_platform_data nand_data = {
+        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
+};
+
+void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
+                                 int nr_parts)
+{
+        u8 cs = 0;
+        u8 nandcs = GPMC_CS_NUM + 1;
+
+        /* find out the chip-select on which NAND exists */
+        while (cs < GPMC_CS_NUM) {
+                u32 ret = 0;
+                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+                if ((ret & 0xC00) == 0x800) {
+                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
+                        if (nandcs > GPMC_CS_NUM)
+                                nandcs = cs;
+                }
+                cs++;
+        }
+
+        if (nandcs > GPMC_CS_NUM) {
+                printk(KERN_INFO "NAND: Unable to find configuration "
+                                 "in GPMC\n ");
+                return;
+        }
+
+        if (nandcs < GPMC_CS_NUM) {
+                nand_data.cs = nandcs;
+                nand_data.parts = parts;
+                nand_data.nr_parts = nr_parts;
+                nand_data.options = options;
+
+                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+                if (gpmc_nand_init(&nand_data) < 0)
+                        printk(KERN_ERR "Unable to register NAND device\n");
+        }
+}
+#else
+void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
+                                 int nr_parts)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
new file mode 100644
index 000000000000..679719051df5
--- /dev/null
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -0,0 +1,37 @@
+#ifndef __OMAP_COMMON_BOARD_DEVICES__
+#define __OMAP_COMMON_BOARD_DEVICES__
+
+#define NAND_BLOCK_SIZE SZ_128K
+
+struct twl4030_platform_data;
+struct mtd_partition;
+
+void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+                    struct twl4030_platform_data *pmic_data);
+
+static inline void omap2_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap3_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap4_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
+        omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+}
+
+struct ads7846_platform_data;
+
+void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+                       struct ads7846_platform_data *board_pdata);
+void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
+
+#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
new file mode 100644
index 000000000000..3f20cbb9967b
--- /dev/null
+++ b/arch/arm/mach-omap2/common.c
@@ -0,0 +1,142 @@
+/*
+ * linux/arch/arm/mach-omap2/common.c
+ *
+ * Code common to all OMAP2+ machines.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/mux.h>
+
+#include <plat/clock.h>
+
+#include "sdrc.h"
+#include "control.h"
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
+{
+        omap2_set_globals_tap(omap2_globals);
+        omap2_set_globals_sdrc(omap2_globals);
+        omap2_set_globals_control(omap2_globals);
+        omap2_set_globals_prcm(omap2_globals);
+}
+
+#endif
+
+#if defined(CONFIG_SOC_OMAP2420)
+
+static struct omap_globals omap242x_globals = {
+        .class  = OMAP242X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
+        .sdrc   = OMAP2420_SDRC_BASE,
+        .sms    = OMAP2420_SMS_BASE,
+        .ctrl   = OMAP242X_CTRL_BASE,
+        .prm    = OMAP2420_PRM_BASE,
+        .cm     = OMAP2420_CM_BASE,
+};
+
+void __init omap2_set_globals_242x(void)
+{
+        __omap2_set_globals(&omap242x_globals);
+}
+#endif
+
+#if defined(CONFIG_SOC_OMAP2430)
+
+static struct omap_globals omap243x_globals = {
+        .class  = OMAP243X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
+        .sdrc   = OMAP243X_SDRC_BASE,
+        .sms    = OMAP243X_SMS_BASE,
+        .ctrl   = OMAP243X_CTRL_BASE,
+        .prm    = OMAP2430_PRM_BASE,
+        .cm     = OMAP2430_CM_BASE,
+};
+
+void __init omap2_set_globals_243x(void)
+{
+        __omap2_set_globals(&omap243x_globals);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct omap_globals omap3_globals = {
+        .class  = OMAP343X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
+        .sdrc   = OMAP343X_SDRC_BASE,
+        .sms    = OMAP343X_SMS_BASE,
+        .ctrl   = OMAP343X_CTRL_BASE,
+        .prm    = OMAP3430_PRM_BASE,
+        .cm     = OMAP3430_CM_BASE,
+};
+
+void __init omap2_set_globals_3xxx(void)
+{
+        __omap2_set_globals(&omap3_globals);
+}
+
+void __init omap3_map_io(void)
+{
+        omap2_set_globals_3xxx();
+        omap34xx_map_common_io();
+}
+
+/*
+ * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * TI816X register for checking device ID (it adds 0x204 to tap base while
+ * TI816X DEVICE ID register is at offset 0x600 from control base).
+ */
+#define TI816X_TAP_BASE         (TI816X_CTRL_BASE + \
+                                TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals ti816x_globals = {
+        .class  = OMAP343X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
+        .ctrl   = TI816X_CTRL_BASE,
+        .prm    = TI816X_PRCM_BASE,
+        .cm     = TI816X_PRCM_BASE,
+};
+
+void __init omap2_set_globals_ti816x(void)
+{
+        __omap2_set_globals(&ti816x_globals);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4)
+static struct omap_globals omap4_globals = {
+        .class  = OMAP443X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
+        .ctrl   = OMAP443X_SCM_BASE,
+        .ctrl_pad       = OMAP443X_CTRL_BASE,
+        .prm    = OMAP4430_PRM_BASE,
+        .cm     = OMAP4430_CM_BASE,
+        .cm2    = OMAP4430_CM2_BASE,
+};
+
+void __init omap2_set_globals_443x(void)
+{
+        omap2_set_globals_tap(&omap4_globals);
+        omap2_set_globals_control(&omap4_globals);
+        omap2_set_globals_prcm(&omap4_globals);
+}
+#endif
+
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20eef2306..da53ba3917ca 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -16,15 +16,22 @@
 #include <linux/io.h>
 
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/sdrc.h>
+
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
-#include "cm.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "sdrc.h"
+#include "pm.h"
+#include "control.h"
+
+/* Used by omap3_ctrl_save_padconf() */
+#define START_PADCONF_SAVE              0x2
+#define PADCONF_SAVE_DONE               0x1
 
 static void __iomem *omap2_ctrl_base;
+static void __iomem *omap4_ctrl_pad_base;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 struct omap3_scratchpad {
@@ -131,12 +138,14 @@ struct omap3_control_regs {
         u32 sramldo4;
         u32 sramldo5;
         u32 csi;
+        u32 padconf_sys_nirq;
 };
 
 static struct omap3_control_regs control_context;
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 
 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
+#define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
@@ -145,6 +154,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
                 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
                 WARN_ON(!omap2_ctrl_base);
         }
+
+        /* Static mapping, never released */
+        if (omap2_globals->ctrl_pad) {
+                omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
+                WARN_ON(!omap4_ctrl_pad_base);
+        }
 }
 
 void __iomem *omap_ctrl_base_get(void)
@@ -182,6 +197,54 @@ void omap_ctrl_writel(u32 val, u16 offset)
         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 }
 
+/*
+ * On OMAP4 control pad are not addressable from control
+ * core base. So the common omap_ctrl_read/write APIs breaks
+ * Hence export separate APIs to manage the omap4 pad control
+ * registers. This APIs will work only for OMAP4
+ */
+
+u32 omap4_ctrl_pad_readl(u16 offset)
+{
+        return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+}
+
+void omap4_ctrl_pad_writel(u32 val, u16 offset)
+{
+        __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+}
+
+#ifdef CONFIG_ARCH_OMAP3
+
+/**
+ * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
+ * @bootmode: 8-bit value to pass to some boot code
+ *
+ * Set the bootmode in the scratchpad RAM.  This is used after the
+ * system restarts.  Not sure what actually uses this - it may be the
+ * bootloader, rather than the boot ROM - contrary to the preserved
+ * comment below.  No return value.
+ */
+void omap3_ctrl_write_boot_mode(u8 bootmode)
+{
+        u32 l;
+
+        l = ('B' << 24) | ('M' << 16) | bootmode;
+
+        /*
+         * Reserve the first word in scratchpad for communicating
+         * with the boot ROM. A pointer to a data structure
+         * describing the boot process can be stored there,
+         * cf. OMAP34xx TRM, Initialization / Software Booting
+         * Configuration.
+         *
+         * XXX This should use some omap_ctrl_writel()-type function
+         */
+        __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
+}
+
+#endif
+
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 /*
  * Clears the scratchpad contents in case of cold boot-
@@ -190,31 +253,41 @@ void omap_ctrl_writel(u32 val, u16 offset)
 void omap3_clear_scratchpad_contents(void)
 {
         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
-        u32 *v_addr;
+        void __iomem *v_addr;
         u32 offset = 0;
         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
-        if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
+        if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
             OMAP3430_GLOBAL_COLD_RST_MASK) {
                 for ( ; offset <= max_offset; offset += 0x4)
                         __raw_writel(0x0, (v_addr + offset));
-                prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
-                                     OMAP3430_GR_MOD,
-                                     OMAP3_PRM_RSTST_OFFSET);
+                omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
+                                           OMAP3430_GR_MOD,
+                                           OMAP3_PRM_RSTST_OFFSET);
         }
 }
 
 /* Populate the scratchpad structure with restore structure */
 void omap3_save_scratchpad_contents(void)
 {
-        void * __iomem scratchpad_address;
+        void  __iomem *scratchpad_address;
         u32 arm_context_addr;
         struct omap3_scratchpad scratchpad_contents;
         struct omap3_scratchpad_prcm_block prcm_block_contents;
         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 
-        /* Populate the Scratchpad contents */
+        /*
+         * Populate the Scratchpad contents
+         *
+         * The "get_*restore_pointer" functions are used to provide a
+         * physical restore address where the ROM code jumps while waking
+         * up from MPU OFF/OSWR state.
+         * The restore pointer is stored into the scratchpad.
+         */
         scratchpad_contents.boot_config_ptr = 0x0;
-        if (omap_rev() != OMAP3430_REV_ES3_0 &&
+        if (cpu_is_omap3630())
+                scratchpad_contents.public_restore_ptr =
+                        virt_to_phys(get_omap3630_restore_pointer());
+        else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                         omap_rev() != OMAP3430_REV_ES3_1)
                 scratchpad_contents.public_restore_ptr =
                         virt_to_phys(get_restore_pointer());
@@ -231,32 +304,40 @@ void omap3_save_scratchpad_contents(void)
         scratchpad_contents.sdrc_block_offset = 0x64;
 
         /* Populate the PRCM block contents */
-        prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
-                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
-        prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
-                        OMAP3_PRM_CLKSEL_OFFSET);
+        prcm_block_contents.prm_clksrc_ctrl =
+                omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
+                                       OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+        prcm_block_contents.prm_clksel =
+                omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
+                                       OMAP3_PRM_CLKSEL_OFFSET);
         prcm_block_contents.cm_clksel_core =
-                        cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
+                        omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
         prcm_block_contents.cm_clksel_wkup =
-                        cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+                        omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
         prcm_block_contents.cm_clken_pll =
-                        cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+                        omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
+         * Then,  in anycase, clear these bits to avoid extra latencies.
+         */
         prcm_block_contents.cm_autoidle_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
+                        ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
         prcm_block_contents.cm_clksel1_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
         prcm_block_contents.cm_clksel2_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
         prcm_block_contents.cm_clksel3_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
         prcm_block_contents.cm_clken_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
         prcm_block_contents.cm_autoidle_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
         prcm_block_contents.cm_clksel1_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
         prcm_block_contents.cm_clksel2_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
         prcm_block_contents.prcm_block_size = 0x0;
 
         /* Populate the SDRC block contents */
@@ -389,6 +470,8 @@ void omap3_control_save_context(void)
         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
+        control_context.padconf_sys_nirq =
+                omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
         return;
 }
 
@@ -445,6 +528,43 @@ void omap3_control_restore_context(void)
         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
+        omap_ctrl_writel(control_context.padconf_sys_nirq,
+                         OMAP343X_CONTROL_PADCONF_SYSNIRQ);
         return;
 }
+
+void omap3630_ctrl_disable_rta(void)
+{
+        if (!cpu_is_omap3630())
+                return;
+        omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
+
+/**
+ * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
+ *
+ * Tell the SCM to start saving the padconf registers, then wait for
+ * the process to complete.  Returns 0 unconditionally, although it
+ * should also eventually be able to return -ETIMEDOUT, if the save
+ * does not complete.
+ *
+ * XXX This function is missing a timeout.  What should it be?
+ */
+int omap3_ctrl_save_padconf(void)
+{
+        u32 cpo;
+
+        /* Save the padconf registers */
+        cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
+        cpo |= START_PADCONF_SAVE;
+        omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
+
+        /* wait for the save to complete */
+        while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
+                 & PADCONF_SAVE_DONE))
+                udelay(1);
+
+        return 0;
+}
+
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
new file mode 100644
index 000000000000..a016c8b59e00
--- /dev/null
+++ b/arch/arm/mach-omap2/control.h
@@ -0,0 +1,412 @@
+/*
+ * arch/arm/mach-omap2/control.h
+ *
+ * OMAP2/3/4 System Control Module definitions
+ *
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2010 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
+#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
+
+#include <mach/io.h>
+#include <mach/ctrl_module_core_44xx.h>
+#include <mach/ctrl_module_wkup_44xx.h>
+#include <mach/ctrl_module_pad_core_44xx.h>
+#include <mach/ctrl_module_pad_wkup_44xx.h>
+
+#ifndef __ASSEMBLY__
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#else
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#endif /* __ASSEMBLY__ */
+
+/*
+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ * OMAP24XX and OMAP34XX.
+ */
+
+/* Control submodule offsets */
+
+#define OMAP2_CONTROL_INTERFACE         0x000
+#define OMAP2_CONTROL_PADCONFS          0x030
+#define OMAP2_CONTROL_GENERAL           0x270
+#define OMAP343X_CONTROL_MEM_WKUP       0x600
+#define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
+#define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
+
+/* TI816X spefic control submodules */
+#define TI816X_CONTROL_DEVCONF          0x600
+
+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+
+#define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
+
+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+#define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
+#define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
+#define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
+#define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
+#define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
+#define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
+#define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
+#define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
+#define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
+#define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
+#define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
+#define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
+
+/* 242x-only CONTROL_GENERAL register offsets */
+#define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
+#define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
+
+/* 243x-only CONTROL_GENERAL register offsets */
+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+#define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
+#define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
+#define OMAP243X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x0230)
+
+/* 24xx-only CONTROL_GENERAL register offsets */
+#define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
+#define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
+#define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
+#define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
+#define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
+#define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
+#define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
+#define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
+#define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
+#define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
+
+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
+
+/* 34xx-only CONTROL_GENERAL register offsets */
+#define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
+#define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
+#define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
+#define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
+#define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
+#define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
+#define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
+#define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+#define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
+#define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
+                                        + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
+#define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
+#define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
+#define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
+#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
+#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
+#define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
+#define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
+#define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
+
+/* OMAP3630 only CONTROL_GENERAL register offsets */
+#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
+
+/* OMAP44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50         0x22C
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100        0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO      0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO      0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50         0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100        0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO      0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO      0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50        0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100       0x257
+
+/* AM35XX only CONTROL_GENERAL register offsets */
+#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
+#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
+#define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
+#define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
+#define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
+#define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
+#define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
+
+/* 34xx PADCONF register offsets */
+#define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
+                                                (i)*2)
+#define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
+#define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
+#define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
+#define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
+#define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
+#define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
+#define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
+#define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
+#define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
+#define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
+#define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
+#define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
+#define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
+#define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
+#define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
+#define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
+#define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
+#define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
+
+/* 34xx GENERAL_WKUP regist offsets */
+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
+                                                0x008 + (i))
+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+
+/* 36xx-only RTA - Retention till Access control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL   0x40C
+#define OMAP36XX_RTA_DISABLE            0x0
+
+/* 34xx D2D idle-related pins, handled by PM core */
+#define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
+#define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
+
+/* TI816X CONTROL_DEVCONF register offsets */
+#define TI816X_CONTROL_DEVICE_ID        (TI816X_CONTROL_DEVCONF + 0x000)
+
+/*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+ */
+
+/*
+ * Control module register bit defines - these should eventually go into
+ * their own regbits file.  Some of these will be complicated, depending
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
+ * and the security mode (secure, non-secure, don't care)
+ */
+/* CONTROL_DEVCONF0 bits */
+#define OMAP2_MMCSDIO1ADPCLKISEL        (1 << 24) /* MMC1 loop back clock */
+#define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
+#define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
+#define OMAP2_MCBSP1_FSR_MASK           (1 << 4)
+#define OMAP2_MCBSP1_CLKR_MASK          (1 << 3)
+#define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
+
+/* CONTROL_DEVCONF1 bits */
+#define OMAP243X_MMC1_ACTIVE_OVERWRITE  (1 << 31)
+#define OMAP2_MMCSDIO2ADPCLKISEL        (1 << 6) /* MMC2 loop back clock */
+#define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
+#define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
+#define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
+
+/* CONTROL_STATUS bits */
+#define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
+#define OMAP2_SYSBOOT_5_MASK            (1 << 5)
+#define OMAP2_SYSBOOT_4_MASK            (1 << 4)
+#define OMAP2_SYSBOOT_3_MASK            (1 << 3)
+#define OMAP2_SYSBOOT_2_MASK            (1 << 2)
+#define OMAP2_SYSBOOT_1_MASK            (1 << 1)
+#define OMAP2_SYSBOOT_0_MASK            (1 << 0)
+
+/* CONTROL_PBIAS_LITE bits */
+#define OMAP343X_PBIASLITESUPPLY_HIGH1  (1 << 15)
+#define OMAP343X_PBIASLITEVMODEERROR1   (1 << 11)
+#define OMAP343X_PBIASSPEEDCTRL1        (1 << 10)
+#define OMAP343X_PBIASLITEPWRDNZ1       (1 << 9)
+#define OMAP343X_PBIASLITEVMODE1        (1 << 8)
+#define OMAP343X_PBIASLITESUPPLY_HIGH0  (1 << 7)
+#define OMAP343X_PBIASLITEVMODEERROR0   (1 << 3)
+#define OMAP2_PBIASSPEEDCTRL0           (1 << 2)
+#define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
+#define OMAP2_PBIASLITEVMODE0           (1 << 0)
+
+/* CONTROL_PROG_IO1 bits */
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
+
+/* CONTROL_IVA2_BOOTMOD bits */
+#define OMAP3_IVA2_BOOTMOD_SHIFT        0
+#define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
+#define OMAP3_IVA2_BOOTMOD_IDLE         (0x1 << 0)
+
+/* CONTROL_PADCONF_X bits */
+#define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
+#define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
+
+#define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
+#define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
+#define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+#define OMAP343X_SCRATCHPAD_REGADDR(reg)        OMAP2_L4_IO_ADDRESS(\
+                                                OMAP343X_SCRATCHPAD + reg)
+
+/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
+/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
+#define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
+#define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
+#define AM35XX_CPGMAC_C0_TX_PULSE_CLR   BIT(3)
+#define AM35XX_USBOTGSS_INT_CLR         BIT(4)
+#define AM35XX_VPFE_CCDC_VD0_INT_CLR    BIT(5)
+#define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
+#define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
+
+/*AM35XX CONTROL_IP_SW_RESET bits*/
+#define AM35XX_USBOTGSS_SW_RST          BIT(0)
+#define AM35XX_CPGMACSS_SW_RST          BIT(1)
+#define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
+#define AM35XX_HECC_SW_RST              BIT(3)
+#define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
+
+/*
+ * CONTROL OMAP STATUS register to identify OMAP3 features
+ */
+#define OMAP3_CONTROL_OMAP_STATUS       0x044c
+
+#define OMAP3_SGX_SHIFT                 13
+#define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
+#define         FEAT_SGX_FULL           0
+#define         FEAT_SGX_HALF           1
+#define         FEAT_SGX_NONE           2
+
+#define OMAP3_IVA_SHIFT                 12
+#define OMAP3_IVA_MASK                  (1 << OMAP3_IVA_SHIFT)
+#define         FEAT_IVA                0
+#define         FEAT_IVA_NONE           1
+
+#define OMAP3_L2CACHE_SHIFT             10
+#define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
+#define         FEAT_L2CACHE_NONE       0
+#define         FEAT_L2CACHE_64KB       1
+#define         FEAT_L2CACHE_128KB      2
+#define         FEAT_L2CACHE_256KB      3
+
+#define OMAP3_ISP_SHIFT                 5
+#define OMAP3_ISP_MASK                  (1 << OMAP3_ISP_SHIFT)
+#define         FEAT_ISP                0
+#define         FEAT_ISP_NONE           1
+
+#define OMAP3_NEON_SHIFT                4
+#define OMAP3_NEON_MASK                 (1 << OMAP3_NEON_SHIFT)
+#define         FEAT_NEON               0
+#define         FEAT_NEON_NONE          1
+
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_ARCH_OMAP2PLUS
+extern void __iomem *omap_ctrl_base_get(void);
+extern u8 omap_ctrl_readb(u16 offset);
+extern u16 omap_ctrl_readw(u16 offset);
+extern u32 omap_ctrl_readl(u16 offset);
+extern u32 omap4_ctrl_pad_readl(u16 offset);
+extern void omap_ctrl_writeb(u8 val, u16 offset);
+extern void omap_ctrl_writew(u16 val, u16 offset);
+extern void omap_ctrl_writel(u32 val, u16 offset);
+extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
+
+extern void omap3_save_scratchpad_contents(void);
+extern void omap3_clear_scratchpad_contents(void);
+extern u32 *get_restore_pointer(void);
+extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
+extern u32 omap3_arm_context[128];
+extern void omap3_control_save_context(void);
+extern void omap3_control_restore_context(void);
+extern void omap3_ctrl_write_boot_mode(u8 bootmode);
+extern void omap3630_ctrl_disable_rta(void);
+extern int omap3_ctrl_save_padconf(void);
+#else
+#define omap_ctrl_base_get()            0
+#define omap_ctrl_readb(x)              0
+#define omap_ctrl_readw(x)              0
+#define omap_ctrl_readl(x)              0
+#define omap4_ctrl_pad_readl(x)         0
+#define omap_ctrl_writeb(x, y)          WARN_ON(1)
+#define omap_ctrl_writew(x, y)          WARN_ON(1)
+#define omap_ctrl_writel(x, y)          WARN_ON(1)
+#define omap4_ctrl_pad_writel(x, y)     WARN_ON(1)
+#endif
+#endif  /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
+
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 3d3d035db9af..4bf6e6e8b100 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -27,41 +27,15 @@
 
 #include <plat/prcm.h>
 #include <plat/irqs.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
-#include <plat/control.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 #include <plat/serial.h>
 
 #include "pm.h"
+#include "control.h"
 
 #ifdef CONFIG_CPU_IDLE
 
-#define OMAP3_MAX_STATES 7
-#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
-#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
-#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
-#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
-#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
-#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
-#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
-
-#define OMAP3_STATE_MAX OMAP3_STATE_C7
-
-struct omap3_processor_cx {
-        u8 valid;
-        u8 type;
-        u32 sleep_latency;
-        u32 wakeup_latency;
-        u32 mpu_state;
-        u32 core_state;
-        u32 threshold;
-        u32 flags;
-};
-
-struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
-struct omap3_processor_cx current_cx_state;
-struct powerdomain *mpu_pd, *core_pd;
-
 /*
  * The latencies/thresholds for various C states have
  * to be configured from the respective board files.
@@ -71,39 +45,43 @@ struct powerdomain *mpu_pd, *core_pd;
  */
 static struct cpuidle_params cpuidle_params_table[] = {
         /* C1 */
-        {1, 2, 2, 5},
+        {2 + 2, 5, 1},
         /* C2 */
-        {1, 10, 10, 30},
+        {10 + 10, 30, 1},
         /* C3 */
-        {1, 50, 50, 300},
+        {50 + 50, 300, 1},
         /* C4 */
-        {1, 1500, 1800, 4000},
+        {1500 + 1800, 4000, 1},
         /* C5 */
-        {1, 2500, 7500, 12000},
+        {2500 + 7500, 12000, 1},
         /* C6 */
-        {1, 3000, 8500, 15000},
+        {3000 + 8500, 15000, 1},
         /* C7 */
-        {1, 10000, 30000, 300000},
+        {10000 + 30000, 300000, 1},
 };
+#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
 
-static int omap3_idle_bm_check(void)
-{
-        if (!omap3_can_sleep())
-                return 1;
-        return 0;
-}
+/* Mach specific information to be recorded in the C-state driver_data */
+struct omap3_idle_statedata {
+        u32 mpu_state;
+        u32 core_state;
+        u8 valid;
+};
+struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
+
+struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 
 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
                                 struct clockdomain *clkdm)
 {
-        omap2_clkdm_allow_idle(clkdm);
+        clkdm_allow_idle(clkdm);
         return 0;
 }
 
 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
                                 struct clockdomain *clkdm)
 {
-        omap2_clkdm_deny_idle(clkdm);
+        clkdm_deny_idle(clkdm);
         return 0;
 }
 
@@ -118,12 +96,10 @@ static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
 static int omap3_enter_idle(struct cpuidle_device *dev,
                         struct cpuidle_state *state)
 {
-        struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
+        struct omap3_idle_statedata *cx = cpuidle_get_statedata(state);
         struct timespec ts_preidle, ts_postidle, ts_idle;
         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 
-        current_cx_state = *cx;
-
         /* Used to keep track of the total time in idle */
         getnstimeofday(&ts_preidle);
 
@@ -136,7 +112,8 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
         if (omap_irq_pending() || need_resched())
                 goto return_sleep_time;
 
-        if (cx->type == OMAP3_STATE_C1) {
+        /* Deny idle for C1 */
+        if (state == &dev->states[0]) {
                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
         }
@@ -144,7 +121,8 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
         /* Execute ARM wfi */
         omap_sram_idle();
 
-        if (cx->type == OMAP3_STATE_C1) {
+        /* Re-allow idle for C1 */
+        if (state == &dev->states[0]) {
                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
         }
@@ -160,41 +138,53 @@ return_sleep_time:
 }
 
 /**
- * next_valid_state - Find next valid c-state
+ * next_valid_state - Find next valid C-state
  * @dev: cpuidle device
- * @state: Currently selected c-state
+ * @state: Currently selected C-state
  *
  * If the current state is valid, it is returned back to the caller.
  * Else, this function searches for a lower c-state which is still
- * valid (as defined in omap3_power_states[]).
+ * valid.
+ *
+ * A state is valid if the 'valid' field is enabled and
+ * if it satisfies the enable_off_mode condition.
  */
 static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
-                                                struct cpuidle_state *curr)
+                                              struct cpuidle_state *curr)
 {
         struct cpuidle_state *next = NULL;
-        struct omap3_processor_cx *cx;
+        struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr);
+        u32 mpu_deepest_state = PWRDM_POWER_RET;
+        u32 core_deepest_state = PWRDM_POWER_RET;
 
-        cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
+        if (enable_off_mode) {
+                mpu_deepest_state = PWRDM_POWER_OFF;
+                /*
+                 * Erratum i583: valable for ES rev < Es1.2 on 3630.
+                 * CORE OFF mode is not supported in a stable form, restrict
+                 * instead the CORE state to RET.
+                 */
+                if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+                        core_deepest_state = PWRDM_POWER_OFF;
+        }
 
         /* Check if current state is valid */
-        if (cx->valid) {
+        if ((cx->valid) &&
+            (cx->mpu_state >= mpu_deepest_state) &&
+            (cx->core_state >= core_deepest_state)) {
                 return curr;
         } else {
-                u8 idx = OMAP3_STATE_MAX;
+                int idx = OMAP3_NUM_STATES - 1;
 
-                /*
-                 * Reach the current state starting at highest C-state
-                 */
-                for (; idx >= OMAP3_STATE_C1; idx--) {
+                /* Reach the current state starting at highest C-state */
+                for (; idx >= 0; idx--) {
                         if (&dev->states[idx] == curr) {
                                 next = &dev->states[idx];
                                 break;
                         }
                 }
 
-                /*
-                 * Should never hit this condition.
-                 */
+                /* Should never hit this condition */
                 WARN_ON(next == NULL);
 
                 /*
@@ -202,17 +192,17 @@ static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
                  * Start search from the next (lower) state.
                  */
                 idx--;
-                for (; idx >= OMAP3_STATE_C1; idx--) {
-                        struct omap3_processor_cx *cx;
-
+                for (; idx >= 0; idx--) {
                         cx = cpuidle_get_statedata(&dev->states[idx]);
-                        if (cx->valid) {
+                        if ((cx->valid) &&
+                            (cx->mpu_state >= mpu_deepest_state) &&
+                            (cx->core_state >= core_deepest_state)) {
                                 next = &dev->states[idx];
                                 break;
                         }
                 }
                 /*
-                 * C1 and C2 are always valid.
+                 * C1 is always valid.
                  * So, no need to check for 'next==NULL' outside this loop.
                  */
         }
@@ -225,50 +215,70 @@ static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
  * @dev: cpuidle device
  * @state: The target state to be programmed
  *
- * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
- * function checks for any pending activity and then programs the
- * device to the specified or a safer state.
+ * This function checks for any pending activity and then programs
+ * the device to the specified or a safer state.
  */
 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
                                struct cpuidle_state *state)
 {
-        struct cpuidle_state *new_state = next_valid_state(dev, state);
+        struct cpuidle_state *new_state;
+        u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
+        struct omap3_idle_statedata *cx;
+        int ret;
 
-        if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
-                BUG_ON(!dev->safe_state);
+        if (!omap3_can_sleep()) {
                 new_state = dev->safe_state;
+                goto select_state;
         }
 
-        dev->last_state = new_state;
-        return omap3_enter_idle(dev, new_state);
-}
-
-DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+        /*
+         * Prevent idle completely if CAM is active.
+         * CAM does not have wakeup capability in OMAP3.
+         */
+        cam_state = pwrdm_read_pwrst(cam_pd);
+        if (cam_state == PWRDM_POWER_ON) {
+                new_state = dev->safe_state;
+                goto select_state;
+        }
 
-/**
- * omap3_cpuidle_update_states - Update the cpuidle states.
- *
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
- */
-void omap3_cpuidle_update_states(void)
-{
-        int i;
+        /*
+         * FIXME: we currently manage device-specific idle states
+         *        for PER and CORE in combination with CPU-specific
+         *        idle states.  This is wrong, and device-specific
+         *        idle management needs to be separated out into
+         *        its own code.
+         */
+
+        /*
+         * Prevent PER off if CORE is not in retention or off as this
+         * would disable PER wakeups completely.
+         */
+        cx = cpuidle_get_statedata(state);
+        core_next_state = cx->core_state;
+        per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
+        if ((per_next_state == PWRDM_POWER_OFF) &&
+            (core_next_state > PWRDM_POWER_RET))
+                per_next_state = PWRDM_POWER_RET;
+
+        /* Are we changing PER target state? */
+        if (per_next_state != per_saved_state)
+                pwrdm_set_next_pwrst(per_pd, per_next_state);
+
+        new_state = next_valid_state(dev, state);
+
+select_state:
+        dev->last_state = new_state;
+        ret = omap3_enter_idle(dev, new_state);
 
-        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
-                struct omap3_processor_cx *cx = &omap3_power_states[i];
+        /* Restore original PER state if it was modified */
+        if (per_next_state != per_saved_state)
+                pwrdm_set_next_pwrst(per_pd, per_saved_state);
 
-                if (enable_off_mode) {
-                        cx->valid = 1;
-                } else {
-                        if ((cx->mpu_state == PWRDM_POWER_OFF) ||
-                                (cx->core_state == PWRDM_POWER_OFF))
-                                cx->valid = 0;
-                }
-        }
+        return ret;
 }
 
+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+
 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 {
         int i;
@@ -276,186 +286,109 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
         if (!cpuidle_board_params)
                 return;
 
-        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
-                cpuidle_params_table[i].valid =
-                        cpuidle_board_params[i].valid;
-                cpuidle_params_table[i].sleep_latency =
-                        cpuidle_board_params[i].sleep_latency;
-                cpuidle_params_table[i].wake_latency =
-                        cpuidle_board_params[i].wake_latency;
-                cpuidle_params_table[i].threshold =
-                        cpuidle_board_params[i].threshold;
+        for (i = 0; i < OMAP3_NUM_STATES; i++) {
+                cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
+                cpuidle_params_table[i].exit_latency =
+                        cpuidle_board_params[i].exit_latency;
+                cpuidle_params_table[i].target_residency =
+                        cpuidle_board_params[i].target_residency;
         }
         return;
 }
 
-/* omap3_init_power_states - Initialises the OMAP3 specific C states.
- *
- * Below is the desciption of each C state.
- *      C1 . MPU WFI + Core active
- *      C2 . MPU WFI + Core inactive
- *      C3 . MPU CSWR + Core inactive
- *      C4 . MPU OFF + Core inactive
- *      C5 . MPU CSWR + Core CSWR
- *      C6 . MPU OFF + Core CSWR
- *      C7 . MPU OFF + Core OFF
- */
-void omap_init_power_states(void)
-{
-        /* C1 . MPU WFI + Core active */
-        omap3_power_states[OMAP3_STATE_C1].valid =
-                        cpuidle_params_table[OMAP3_STATE_C1].valid;
-        omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
-        omap3_power_states[OMAP3_STATE_C1].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
-        omap3_power_states[OMAP3_STATE_C1].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C1].threshold;
-        omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
-
-        /* C2 . MPU WFI + Core inactive */
-        omap3_power_states[OMAP3_STATE_C2].valid =
-                        cpuidle_params_table[OMAP3_STATE_C2].valid;
-        omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
-        omap3_power_states[OMAP3_STATE_C2].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
-        omap3_power_states[OMAP3_STATE_C2].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C2].threshold;
-        omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
-
-        /* C3 . MPU CSWR + Core inactive */
-        omap3_power_states[OMAP3_STATE_C3].valid =
-                        cpuidle_params_table[OMAP3_STATE_C3].valid;
-        omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
-        omap3_power_states[OMAP3_STATE_C3].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
-        omap3_power_states[OMAP3_STATE_C3].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C3].threshold;
-        omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-
-        /* C4 . MPU OFF + Core inactive */
-        omap3_power_states[OMAP3_STATE_C4].valid =
-                        cpuidle_params_table[OMAP3_STATE_C4].valid;
-        omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
-        omap3_power_states[OMAP3_STATE_C4].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
-        omap3_power_states[OMAP3_STATE_C4].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C4].threshold;
-        omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-
-        /* C5 . MPU CSWR + Core CSWR*/
-        omap3_power_states[OMAP3_STATE_C5].valid =
-                        cpuidle_params_table[OMAP3_STATE_C5].valid;
-        omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
-        omap3_power_states[OMAP3_STATE_C5].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
-        omap3_power_states[OMAP3_STATE_C5].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C5].threshold;
-        omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-
-        /* C6 . MPU OFF + Core CSWR */
-        omap3_power_states[OMAP3_STATE_C6].valid =
-                        cpuidle_params_table[OMAP3_STATE_C6].valid;
-        omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
-        omap3_power_states[OMAP3_STATE_C6].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
-        omap3_power_states[OMAP3_STATE_C6].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C6].threshold;
-        omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-
-        /* C7 . MPU OFF + Core OFF */
-        omap3_power_states[OMAP3_STATE_C7].valid =
-                        cpuidle_params_table[OMAP3_STATE_C7].valid;
-        omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
-        omap3_power_states[OMAP3_STATE_C7].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
-        omap3_power_states[OMAP3_STATE_C7].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C7].threshold;
-        omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-}
-
 struct cpuidle_driver omap3_idle_driver = {
         .name =         "omap3_idle",
         .owner =        THIS_MODULE,
 };
 
+/* Helper to fill the C-state common data and register the driver_data */
+static inline struct omap3_idle_statedata *_fill_cstate(
+                                        struct cpuidle_device *dev,
+                                        int idx, const char *descr)
+{
+        struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
+        struct cpuidle_state *state = &dev->states[idx];
+
+        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
+        state->target_residency = cpuidle_params_table[idx].target_residency;
+        state->flags            = CPUIDLE_FLAG_TIME_VALID;
+        state->enter            = omap3_enter_idle_bm;
+        cx->valid               = cpuidle_params_table[idx].valid;
+        sprintf(state->name, "C%d", idx + 1);
+        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
+        cpuidle_set_statedata(state, cx);
+
+        return cx;
+}
+
 /**
  * omap3_idle_init - Init routine for OMAP3 idle
  *
- * Registers the OMAP3 specific cpuidle driver with the cpuidle
+ * Registers the OMAP3 specific cpuidle driver to the cpuidle
  * framework with the valid set of states.
  */
 int __init omap3_idle_init(void)
 {
-        int i, count = 0;
-        struct omap3_processor_cx *cx;
-        struct cpuidle_state *state;
         struct cpuidle_device *dev;
+        struct omap3_idle_statedata *cx;
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         core_pd = pwrdm_lookup("core_pwrdm");
+        per_pd = pwrdm_lookup("per_pwrdm");
+        cam_pd = pwrdm_lookup("cam_pwrdm");
 
-        omap_init_power_states();
         cpuidle_register_driver(&omap3_idle_driver);
-
         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 
-        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
-                cx = &omap3_power_states[i];
-                state = &dev->states[count];
-
-                if (!cx->valid)
-                        continue;
-                cpuidle_set_statedata(state, cx);
-                state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
-                state->target_residency = cx->threshold;
-                state->flags = cx->flags;
-                state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
-                        omap3_enter_idle_bm : omap3_enter_idle;
-                if (cx->type == OMAP3_STATE_C1)
-                        dev->safe_state = state;
-                sprintf(state->name, "C%d", count+1);
-                count++;
-        }
+        /* C1 . MPU WFI + Core active */
+        cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
+        (&dev->states[0])->enter = omap3_enter_idle;
+        dev->safe_state = &dev->states[0];
+        cx->valid = 1;  /* C1 is always valid */
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->core_state = PWRDM_POWER_ON;
 
-        if (!count)
-                return -EINVAL;
-        dev->state_count = count;
+        /* C2 . MPU WFI + Core inactive */
+        cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->core_state = PWRDM_POWER_ON;
 
-        omap3_cpuidle_update_states();
+        /* C3 . MPU CSWR + Core inactive */
+        cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->core_state = PWRDM_POWER_ON;
+
+        /* C4 . MPU OFF + Core inactive */
+        cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
+        cx->mpu_state = PWRDM_POWER_OFF;
+        cx->core_state = PWRDM_POWER_ON;
+
+        /* C5 . MPU RET + Core RET */
+        cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->core_state = PWRDM_POWER_RET;
+
+        /* C6 . MPU OFF + Core RET */
+        cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
+        cx->mpu_state = PWRDM_POWER_OFF;
+        cx->core_state = PWRDM_POWER_RET;
+
+        /* C7 . MPU OFF + Core OFF */
+        cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
+        /*
+         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+         * enable OFF mode in a stable form for previous revisions.
+         * We disable C7 state as a result.
+         */
+        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+                cx->valid = 0;
+                pr_warn("%s: core off state C7 disabled due to i583\n",
+                        __func__);
+        }
+        cx->mpu_state = PWRDM_POWER_OFF;
+        cx->core_state = PWRDM_POWER_OFF;
 
+        dev->state_count = OMAP3_NUM_STATES;
         if (cpuidle_register_device(dev)) {
                 printk(KERN_ERR "%s: CPUidle register device failed\n",
                        __func__);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2dbb265bedd4..5b8ca680ed93 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -9,12 +9,13 @@
  * (at your option) any later version.
  */
 
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -22,18 +23,87 @@
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
 
-#include <plat/control.h>
 #include <plat/tc.h>
 #include <plat/board.h>
+#include <plat/mcbsp.h>
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/omap4-keypad.h>
 
 #include "mux.h"
+#include "control.h"
+#include "devices.h"
+
+#define L3_MODULES_MAX_LEN 12
+#define L3_MODULES 3
+
+static int __init omap3_l3_init(void)
+{
+        int l;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        char oh_name[L3_MODULES_MAX_LEN];
+
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!(cpu_is_omap34xx()))
+                return -ENODEV;
+
+        l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+
+        oh = omap_hwmod_lookup(oh_name);
+
+        if (!oh)
+                pr_err("could not look up %s\n", oh_name);
+
+        od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
+                                                           NULL, 0, 0);
+
+        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+
+        return IS_ERR(od) ? PTR_ERR(od) : 0;
+}
+postcore_initcall(omap3_l3_init);
+
+static int __init omap4_l3_init(void)
+{
+        int l, i;
+        struct omap_hwmod *oh[3];
+        struct omap_device *od;
+        char oh_name[L3_MODULES_MAX_LEN];
+
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!(cpu_is_omap44xx()))
+                return -ENODEV;
+
+        for (i = 0; i < L3_MODULES; i++) {
+                l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
+
+                oh[i] = omap_hwmod_lookup(oh_name);
+                if (!(oh[i]))
+                        pr_err("could not look up %s\n", oh_name);
+        }
+
+        od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
+                                                     0, NULL, 0, 0);
+
+        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+
+        return IS_ERR(od) ? PTR_ERR(od) : 0;
+}
+postcore_initcall(omap4_l3_init);
 
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
-static struct resource cam_resources[] = {
+static struct resource omap2cam_resources[] = {
         {
                 .start          = OMAP24XX_CAMERA_BASE,
                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
@@ -45,19 +115,13 @@ static struct resource cam_resources[] = {
         }
 };
 
-static struct platform_device omap_cam_device = {
+static struct platform_device omap2cam_device = {
         .name           = "omap24xxcam",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(cam_resources),
-        .resource       = cam_resources,
+        .num_resources  = ARRAY_SIZE(omap2cam_resources),
+        .resource       = omap2cam_resources,
 };
-
-static inline void omap_init_camera(void)
-{
-        platform_device_register(&omap_cam_device);
-}
-
-#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
+#endif
 
 static struct resource omap3isp_resources[] = {
         {
@@ -66,11 +130,6 @@ static struct resource omap3isp_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = OMAP3430_ISP_CBUFF_BASE,
-                .end            = OMAP3430_ISP_CBUFF_END,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
                 .start          = OMAP3430_ISP_CCP2_BASE,
                 .end            = OMAP3430_ISP_CCP2_END,
                 .flags          = IORESOURCE_MEM,
@@ -106,13 +165,33 @@ static struct resource omap3isp_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = OMAP3430_ISP_CSI2A_BASE,
-                .end            = OMAP3430_ISP_CSI2A_END,
+                .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
+                .end            = OMAP3430_ISP_CSI2A_REGS1_END,
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = OMAP3430_ISP_CSI2PHY_BASE,
-                .end            = OMAP3430_ISP_CSI2PHY_END,
+                .start          = OMAP3430_ISP_CSIPHY2_BASE,
+                .end            = OMAP3430_ISP_CSIPHY2_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
+                .end            = OMAP3630_ISP_CSI2A_REGS2_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
+                .end            = OMAP3630_ISP_CSI2C_REGS1_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3630_ISP_CSIPHY1_BASE,
+                .end            = OMAP3630_ISP_CSIPHY1_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
+                .end            = OMAP3630_ISP_CSI2C_REGS2_END,
                 .flags          = IORESOURCE_MEM,
         },
         {
@@ -128,106 +207,84 @@ static struct platform_device omap3isp_device = {
         .resource       = omap3isp_resources,
 };
 
-static inline void omap_init_camera(void)
+int omap3_init_camera(struct isp_platform_data *pdata)
 {
-        platform_device_register(&omap3isp_device);
+        omap3isp_device.dev.platform_data = pdata;
+        return platform_device_register(&omap3isp_device);
 }
-#else
+
 static inline void omap_init_camera(void)
 {
-}
+#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
+        if (cpu_is_omap24xx())
+                platform_device_register(&omap2cam_device);
 #endif
+}
 
-#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE   0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
+struct omap_device_pm_latency omap_keyboard_latency[] = {
         {
-                .start          = OMAP24XX_MAILBOX_BASE,
-                .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = INT_24XX_MAIL_U0_MPU,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "dsp",
-        },
-        {
-                .start          = INT_24XX_MAIL_U3_MPU,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "iva",
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
 };
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources            NULL
-#define omap2_mbox_resources_sz         0
-#endif
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
-        {
-                .start          = OMAP34XX_MAILBOX_BASE,
-                .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = INT_24XX_MAIL_U0_MPU,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "dsp",
-        },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources            NULL
-#define omap3_mbox_resources_sz         0
-#endif
+int __init omap4_keyboard_init(struct omap4_keypad_platform_data
+                                                *sdp4430_keypad_data)
+{
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        struct omap4_keypad_platform_data *keypad_data;
+        unsigned int id = -1;
+        char *oh_name = "kbd";
+        char *name = "omap4-keypad";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
 
-#ifdef CONFIG_ARCH_OMAP4
+        keypad_data = sdp4430_keypad_data;
 
-#define OMAP4_MBOX_REG_SIZE     0x130
-static struct resource omap4_mbox_resources[] = {
-        {
-                .start          = OMAP44XX_MAILBOX_BASE,
-                .end            = OMAP44XX_MAILBOX_BASE +
-                                        OMAP4_MBOX_REG_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = OMAP44XX_IRQ_MAIL_U0,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "mbox",
-        },
-};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources            NULL
-#define omap4_mbox_resources_sz         0
-#endif
+        od = omap_device_build(name, id, oh, keypad_data,
+                        sizeof(struct omap4_keypad_platform_data),
+                        omap_keyboard_latency,
+                        ARRAY_SIZE(omap_keyboard_latency), 0);
 
-static struct platform_device mbox_device = {
-        .name           = "omap-mailbox",
-        .id             = -1,
+        if (IS_ERR(od)) {
+                WARN(1, "Can't build omap_device for %s:%s.\n",
+                                                name, oh->name);
+                return PTR_ERR(od);
+        }
+
+        return 0;
+}
+
+#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+static struct omap_device_pm_latency mbox_latencies[] = {
+        [0] = {
+                .activate_func = omap_device_enable_hwmods,
+                .deactivate_func = omap_device_idle_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
 };
 
 static inline void omap_init_mbox(void)
 {
-        if (cpu_is_omap24xx()) {
-                mbox_device.resource = omap2_mbox_resources;
-                mbox_device.num_resources = omap2_mbox_resources_sz;
-        } else if (cpu_is_omap34xx()) {
-                mbox_device.resource = omap3_mbox_resources;
-                mbox_device.num_resources = omap3_mbox_resources_sz;
-        } else if (cpu_is_omap44xx()) {
-                mbox_device.resource = omap4_mbox_resources;
-                mbox_device.num_resources = omap4_mbox_resources_sz;
-        } else {
-                pr_err("%s: platform not supported\n", __func__);
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+
+        oh = omap_hwmod_lookup("mailbox");
+        if (!oh) {
+                pr_err("%s: unable to find hwmod\n", __func__);
                 return;
         }
-        platform_device_register(&mbox_device);
+
+        od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
+                                mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
+        WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
+                                                __func__, PTR_ERR(od));
 }
 #else
 static inline void omap_init_mbox(void) { }
@@ -235,167 +292,96 @@ static inline void omap_init_mbox(void) { }
 
 static inline void omap_init_sti(void) {}
 
-#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
-
-#include <plat/mcspi.h>
-
-#define OMAP2_MCSPI1_BASE               0x48098000
-#define OMAP2_MCSPI2_BASE               0x4809a000
-#define OMAP2_MCSPI3_BASE               0x480b8000
-#define OMAP2_MCSPI4_BASE               0x480ba000
-
-#define OMAP4_MCSPI1_BASE               0x48098100
-#define OMAP4_MCSPI2_BASE               0x4809a100
-#define OMAP4_MCSPI3_BASE               0x480b8100
-#define OMAP4_MCSPI4_BASE               0x480ba100
-
-static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
-        .num_cs         = 4,
-};
-
-static struct resource omap2_mcspi1_resources[] = {
-        {
-                .start          = OMAP2_MCSPI1_BASE,
-                .end            = OMAP2_MCSPI1_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap2_mcspi1 = {
-        .name           = "omap2_mcspi",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
-        .resource       = omap2_mcspi1_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi1_config,
-        },
-};
+#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
 
-static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
-        .num_cs         = 2,
+static struct platform_device omap_pcm = {
+        .name   = "omap-pcm-audio",
+        .id     = -1,
 };
 
-static struct resource omap2_mcspi2_resources[] = {
-        {
-                .start          = OMAP2_MCSPI2_BASE,
-                .end            = OMAP2_MCSPI2_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap2_mcspi2 = {
-        .name           = "omap2_mcspi",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
-        .resource       = omap2_mcspi2_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi2_config,
-        },
-};
+/*
+ * OMAP2420 has 2 McBSP ports
+ * OMAP2430 has 5 McBSP ports
+ * OMAP3 has 5 McBSP ports
+ * OMAP4 has 4 McBSP ports
+ */
+OMAP_MCBSP_PLATFORM_DEVICE(1);
+OMAP_MCBSP_PLATFORM_DEVICE(2);
+OMAP_MCBSP_PLATFORM_DEVICE(3);
+OMAP_MCBSP_PLATFORM_DEVICE(4);
+OMAP_MCBSP_PLATFORM_DEVICE(5);
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
-        defined(CONFIG_ARCH_OMAP4)
-static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
-        .num_cs         = 2,
-};
+static void omap_init_audio(void)
+{
+        platform_device_register(&omap_mcbsp1);
+        platform_device_register(&omap_mcbsp2);
+        if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                platform_device_register(&omap_mcbsp3);
+                platform_device_register(&omap_mcbsp4);
+        }
+        if (cpu_is_omap243x() || cpu_is_omap34xx())
+                platform_device_register(&omap_mcbsp5);
 
-static struct resource omap2_mcspi3_resources[] = {
-        {
-        .start          = OMAP2_MCSPI3_BASE,
-        .end            = OMAP2_MCSPI3_BASE + 0xff,
-        .flags          = IORESOURCE_MEM,
-        },
-};
+        platform_device_register(&omap_pcm);
+}
 
-static struct platform_device omap2_mcspi3 = {
-        .name           = "omap2_mcspi",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
-        .resource       = omap2_mcspi3_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi3_config,
-        },
-};
+#else
+static inline void omap_init_audio(void) {}
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
-        .num_cs         = 1,
-};
+#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
-static struct resource omap2_mcspi4_resources[] = {
-        {
-                .start          = OMAP2_MCSPI4_BASE,
-                .end            = OMAP2_MCSPI4_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
+#include <plat/mcspi.h>
 
-static struct platform_device omap2_mcspi4 = {
-        .name           = "omap2_mcspi",
-        .id             = 4,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
-        .resource       = omap2_mcspi4_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi4_config,
+struct omap_device_pm_latency omap_mcspi_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
 };
-#endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static inline void omap4_mcspi_fixup(void)
+static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
-        omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
-        omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
-        omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
-        omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
-        omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
-        omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
-        omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
-        omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
-}
-#else
-static inline void omap4_mcspi_fixup(void)
-{
-}
-#endif
+        struct omap_device *od;
+        char *name = "omap2_mcspi";
+        struct omap2_mcspi_platform_config *pdata;
+        static int spi_num;
+        struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
+
+        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("Memory allocation for McSPI device failed\n");
+                return -ENOMEM;
+        }
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
-        defined(CONFIG_ARCH_OMAP4)
-static inline void omap2_mcspi3_init(void)
-{
-        platform_device_register(&omap2_mcspi3);
-}
-#else
-static inline void omap2_mcspi3_init(void)
-{
-}
-#endif
+        pdata->num_cs = mcspi_attrib->num_chipselect;
+        switch (oh->class->rev) {
+        case OMAP2_MCSPI_REV:
+        case OMAP3_MCSPI_REV:
+                        pdata->regs_offset = 0;
+                        break;
+        case OMAP4_MCSPI_REV:
+                        pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
+                        break;
+        default:
+                        pr_err("Invalid McSPI Revision value\n");
+                        return -EINVAL;
+        }
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static inline void omap2_mcspi4_init(void)
-{
-        platform_device_register(&omap2_mcspi4);
-}
-#else
-static inline void omap2_mcspi4_init(void)
-{
+        spi_num++;
+        od = omap_device_build(name, spi_num, oh, pdata,
+                                sizeof(*pdata), omap_mcspi_latency,
+                                ARRAY_SIZE(omap_mcspi_latency), 0);
+        WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
+                                name, oh->name);
+        kfree(pdata);
+        return 0;
 }
-#endif
 
 static void omap_init_mcspi(void)
 {
-        if (cpu_is_omap44xx())
-                omap4_mcspi_fixup();
-
-        platform_device_register(&omap2_mcspi1);
-        platform_device_register(&omap2_mcspi2);
-
-        if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
-                omap2_mcspi3_init();
-
-        if (cpu_is_omap343x() || cpu_is_omap44xx())
-                omap2_mcspi4_init();
+        omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
 }
 
 #else
@@ -498,115 +484,82 @@ static void omap_init_sham(void)
 static inline void omap_init_sham(void) { }
 #endif
 
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
 
-#define MMCHS_SYSCONFIG                 0x0010
-#define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
-#define MMCHS_SYSSTATUS                 0x0014
-#define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
+#ifdef CONFIG_ARCH_OMAP2
+static struct resource omap2_aes_resources[] = {
+        {
+                .start  = OMAP24XX_SEC_AES_BASE,
+                .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = OMAP24XX_DMA_AES_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = OMAP24XX_DMA_AES_RX,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
+#else
+#define omap2_aes_resources             NULL
+#define omap2_aes_resources_sz          0
+#endif
 
-static struct platform_device dummy_pdev = {
-        .dev = {
-                .bus = &platform_bus_type,
+#ifdef CONFIG_ARCH_OMAP3
+static struct resource omap3_aes_resources[] = {
+        {
+                .start  = OMAP34XX_SEC_AES_BASE,
+                .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
+                .flags  = IORESOURCE_MEM,
         },
+        {
+                .start  = OMAP34XX_DMA_AES2_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = OMAP34XX_DMA_AES2_RX,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
+#else
+#define omap3_aes_resources             NULL
+#define omap3_aes_resources_sz          0
+#endif
+
+static struct platform_device aes_device = {
+        .name           = "omap-aes",
+        .id             = -1,
 };
 
-/**
- * omap_hsmmc_reset() - Full reset of each HS-MMC controller
- *
- * Ensure that each MMC controller is fully reset.  Controllers
- * left in an unknown state (by bootloader) may prevent retention
- * or OFF-mode.  This is especially important in cases where the
- * MMC driver is not enabled, _or_ built as a module.
- *
- * In order for reset to work, interface, functional and debounce
- * clocks must be enabled.  The debounce clock comes from func_32k_clk
- * and is not under SW control, so we only enable i- and f-clocks.
- **/
-static void __init omap_hsmmc_reset(void)
+static void omap_init_aes(void)
 {
-        u32 i, nr_controllers;
-
-        if (cpu_is_omap242x())
+        if (cpu_is_omap24xx()) {
+                aes_device.resource = omap2_aes_resources;
+                aes_device.num_resources = omap2_aes_resources_sz;
+        } else if (cpu_is_omap34xx()) {
+                aes_device.resource = omap3_aes_resources;
+                aes_device.num_resources = omap3_aes_resources_sz;
+        } else {
+                pr_err("%s: platform not supported\n", __func__);
                 return;
-
-        nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
-                (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
-
-        for (i = 0; i < nr_controllers; i++) {
-                u32 v, base = 0;
-                struct clk *iclk, *fclk;
-                struct device *dev = &dummy_pdev.dev;
-
-                switch (i) {
-                case 0:
-                        base = OMAP2_MMC1_BASE;
-                        break;
-                case 1:
-                        base = OMAP2_MMC2_BASE;
-                        break;
-                case 2:
-                        base = OMAP3_MMC3_BASE;
-                        break;
-                case 3:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC4_BASE;
-                        break;
-                case 4:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC5_BASE;
-                        break;
-                }
-
-                if (cpu_is_omap44xx())
-                        base += OMAP4_MMC_REG_OFFSET;
-
-                dummy_pdev.id = i;
-                dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
-                iclk = clk_get(dev, "ick");
-                if (iclk && clk_enable(iclk))
-                        iclk = NULL;
-
-                fclk = clk_get(dev, "fck");
-                if (fclk && clk_enable(fclk))
-                        fclk = NULL;
-
-                if (!iclk || !fclk) {
-                        printk(KERN_WARNING
-                               "%s: Unable to enable clocks for MMC%d, "
-                               "cannot reset.\n",  __func__, i);
-                        break;
-                }
-
-                omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
-                v = omap_readl(base + MMCHS_SYSSTATUS);
-                while (!(omap_readl(base + MMCHS_SYSSTATUS) &
-                         MMCHS_SYSSTATUS_RESETDONE))
-                        cpu_relax();
-
-                if (fclk) {
-                        clk_disable(fclk);
-                        clk_put(fclk);
-                }
-                if (iclk) {
-                        clk_disable(iclk);
-                        clk_put(iclk);
-                }
         }
+        platform_device_register(&aes_device);
 }
+
 #else
-static inline void omap_hsmmc_reset(void) {}
+static inline void omap_init_aes(void) { }
 #endif
 
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
-        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+/*-------------------------------------------------------------------------*/
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
-static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
-                        int controller_nr)
+static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
+                                                        *mmc_controller)
 {
         if ((mmc_controller->slots[0].switch_pin > 0) && \
                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
@@ -617,163 +570,44 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
                                         OMAP_PIN_INPUT_PULLUP);
 
-        if (cpu_is_omap2420() && controller_nr == 0) {
-                omap_mux_init_signal("sdmmc_cmd", 0);
-                omap_mux_init_signal("sdmmc_clki", 0);
-                omap_mux_init_signal("sdmmc_clko", 0);
-                omap_mux_init_signal("sdmmc_dat0", 0);
-                omap_mux_init_signal("sdmmc_dat_dir0", 0);
-                omap_mux_init_signal("sdmmc_cmd_dir", 0);
-                if (mmc_controller->slots[0].wires == 4) {
-                        omap_mux_init_signal("sdmmc_dat1", 0);
-                        omap_mux_init_signal("sdmmc_dat2", 0);
-                        omap_mux_init_signal("sdmmc_dat3", 0);
-                        omap_mux_init_signal("sdmmc_dat_dir1", 0);
-                        omap_mux_init_signal("sdmmc_dat_dir2", 0);
-                        omap_mux_init_signal("sdmmc_dat_dir3", 0);
-                }
-
-                /*
-                 * Use internal loop-back in MMC/SDIO Module Input Clock
-                 * selection
-                 */
-                if (mmc_controller->slots[0].internal_clock) {
-                        u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-                        v |= (1 << 24);
-                        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-                }
+        omap_mux_init_signal("sdmmc_cmd", 0);
+        omap_mux_init_signal("sdmmc_clki", 0);
+        omap_mux_init_signal("sdmmc_clko", 0);
+        omap_mux_init_signal("sdmmc_dat0", 0);
+        omap_mux_init_signal("sdmmc_dat_dir0", 0);
+        omap_mux_init_signal("sdmmc_cmd_dir", 0);
+        if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
+                omap_mux_init_signal("sdmmc_dat1", 0);
+                omap_mux_init_signal("sdmmc_dat2", 0);
+                omap_mux_init_signal("sdmmc_dat3", 0);
+                omap_mux_init_signal("sdmmc_dat_dir1", 0);
+                omap_mux_init_signal("sdmmc_dat_dir2", 0);
+                omap_mux_init_signal("sdmmc_dat_dir3", 0);
         }
 
-        if (cpu_is_omap34xx()) {
-                if (controller_nr == 0) {
-                        omap_mux_init_signal("sdmmc1_clk",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc1_cmd",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc1_dat0",
-                                OMAP_PIN_INPUT_PULLUP);
-                        if (mmc_controller->slots[0].wires == 4 ||
-                                mmc_controller->slots[0].wires == 8) {
-                                omap_mux_init_signal("sdmmc1_dat1",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat2",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat3",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                        if (mmc_controller->slots[0].wires == 8) {
-                                omap_mux_init_signal("sdmmc1_dat4",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat5",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat6",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat7",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                }
-                if (controller_nr == 1) {
-                        /* MMC2 */
-                        omap_mux_init_signal("sdmmc2_clk",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc2_cmd",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc2_dat0",
-                                OMAP_PIN_INPUT_PULLUP);
-
-                        /*
-                         * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
-                         * in the board-*.c files
-                         */
-                        if (mmc_controller->slots[0].wires == 4 ||
-                                mmc_controller->slots[0].wires == 8) {
-                                omap_mux_init_signal("sdmmc2_dat1",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat2",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat3",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                        if (mmc_controller->slots[0].wires == 8) {
-                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                }
-
-                /*
-                 * For MMC3 the pins need to be muxed in the board-*.c files
-                 */
+        /*
+         * Use internal loop-back in MMC/SDIO Module Input Clock
+         * selection
+         */
+        if (mmc_controller->slots[0].internal_clock) {
+                u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+                v |= (1 << 24);
+                omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
         }
 }
 
-void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                        int nr_controllers)
+void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 {
-        int i;
-        char *name;
+        char *name = "mmci-omap";
 
-        for (i = 0; i < nr_controllers; i++) {
-                unsigned long base, size;
-                unsigned int irq = 0;
-
-                if (!mmc_data[i])
-                        continue;
-
-                omap2_mmc_mux(mmc_data[i], i);
+        if (!mmc_data[0]) {
+                pr_err("%s fails: Incomplete platform data\n", __func__);
+                return;
+        }
 
-                switch (i) {
-                case 0:
-                        base = OMAP2_MMC1_BASE;
-                        irq = INT_24XX_MMC_IRQ;
-                        break;
-                case 1:
-                        base = OMAP2_MMC2_BASE;
-                        irq = INT_24XX_MMC2_IRQ;
-                        break;
-                case 2:
-                        if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
-                                return;
-                        base = OMAP3_MMC3_BASE;
-                        irq = INT_34XX_MMC3_IRQ;
-                        break;
-                case 3:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
-                        irq = OMAP44XX_IRQ_MMC4;
-                        break;
-                case 4:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
-                        irq = OMAP44XX_IRQ_MMC5;
-                        break;
-                default:
-                        continue;
-                }
-
-                if (cpu_is_omap2420()) {
-                        size = OMAP2420_MMC_SIZE;
-                        name = "mmci-omap";
-                } else if (cpu_is_omap44xx()) {
-                        if (i < 3) {
-                                base += OMAP4_MMC_REG_OFFSET;
-                                irq += OMAP44XX_IRQ_GIC_START;
-                        }
-                        size = OMAP4_HSMMC_SIZE;
-                        name = "mmci-omap-hs";
-                } else {
-                        size = OMAP3_HSMMC_SIZE;
-                        name = "mmci-omap-hs";
-                }
-                omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
-        };
+        omap242x_mmc_mux(mmc_data[0]);
+        omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
+                                        INT_24XX_MMC_IRQ, mmc_data[0]);
 }
 
 #endif
@@ -781,7 +615,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
 #define OMAP_HDQ_BASE   0x480B2000
 #endif
 static struct resource omap_hdq_resources[] = {
@@ -843,10 +677,11 @@ static inline void omap_init_vout(void) {}
 
 static int __init omap2_init_devices(void)
 {
-        /* please keep these calls, and their implementations above,
+        /*
+         * please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
-        omap_hsmmc_reset();
+        omap_init_audio();
         omap_init_camera();
         omap_init_mbox();
         omap_init_mcspi();
@@ -854,8 +689,45 @@ static int __init omap2_init_devices(void)
         omap_hdq_init();
         omap_init_sti();
         omap_init_sham();
+        omap_init_aes();
         omap_init_vout();
 
         return 0;
 }
 arch_initcall(omap2_init_devices);
+
+#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+static struct omap_device_pm_latency omap_wdt_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static int __init omap_init_wdt(void)
+{
+        int id = -1;
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        char *oh_name = "wd_timer2";
+        char *dev_name = "omap_wdt";
+
+        if (!cpu_class_is_omap2())
+                return 0;
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up wd_timer%d hwmod\n", id);
+                return -EINVAL;
+        }
+
+        od = omap_device_build(dev_name, id, oh, NULL, 0,
+                                omap_wdt_latency,
+                                ARRAY_SIZE(omap_wdt_latency), 0);
+        WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
+                                dev_name, oh->name);
+        return 0;
+}
+subsys_initcall(omap_init_wdt);
+#endif
diff --git a/arch/arm/mach-omap2/devices.h b/arch/arm/mach-omap2/devices.h
new file mode 100644
index 000000000000..f61eb6e5d136
--- /dev/null
+++ b/arch/arm/mach-omap2/devices.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-omap2/devices.h
+ *
+ * OMAP2 platform device setup/initialization
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP_DEVICES_H
+#define __ARCH_ARM_MACH_OMAP_DEVICES_H
+
+struct isp_platform_data;
+
+int omap3_init_camera(struct isp_platform_data *pdata);
+
+#endif
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
new file mode 100644
index 000000000000..543fcb8b518c
--- /dev/null
+++ b/arch/arm/mach-omap2/display.c
@@ -0,0 +1,148 @@
+/*
+ * OMAP2plus display device setup / initialization.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Senthilvadivu Guruswamy
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <video/omapdss.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static struct platform_device omap_display_device = {
+        .name          = "omapdss",
+        .id            = -1,
+        .dev            = {
+                .platform_data = NULL,
+        },
+};
+
+static struct omap_device_pm_latency omap_dss_latency[] = {
+        [0] = {
+                .deactivate_func        = omap_device_idle_hwmods,
+                .activate_func          = omap_device_enable_hwmods,
+                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+/* oh_core is used for getting opt-clocks */
+static struct omap_hwmod        *oh_core;
+
+static bool opt_clock_available(const char *clk_role)
+{
+        int i;
+
+        for (i = 0; i < oh_core->opt_clks_cnt; i++) {
+                if (!strcmp(oh_core->opt_clks[i].role, clk_role))
+                        return true;
+        }
+        return false;
+}
+
+struct omap_dss_hwmod_data {
+        const char *oh_name;
+        const char *dev_name;
+        const int id;
+};
+
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+        { "dss_core", "omapdss_dss", -1 },
+        { "dss_dispc", "omapdss_dispc", -1 },
+        { "dss_rfbi", "omapdss_rfbi", -1 },
+        { "dss_venc", "omapdss_venc", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+        { "dss_core", "omapdss_dss", -1 },
+        { "dss_dispc", "omapdss_dispc", -1 },
+        { "dss_rfbi", "omapdss_rfbi", -1 },
+        { "dss_venc", "omapdss_venc", -1 },
+        { "dss_dsi1", "omapdss_dsi1", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+        { "dss_core", "omapdss_dss", -1 },
+        { "dss_dispc", "omapdss_dispc", -1 },
+        { "dss_rfbi", "omapdss_rfbi", -1 },
+        { "dss_venc", "omapdss_venc", -1 },
+        { "dss_dsi1", "omapdss_dsi1", -1 },
+        { "dss_dsi2", "omapdss_dsi2", -1 },
+        { "dss_hdmi", "omapdss_hdmi", -1 },
+};
+
+int __init omap_display_init(struct omap_dss_board_info *board_data)
+{
+        int r = 0;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        int i, oh_count;
+        struct omap_display_platform_data pdata;
+        const struct omap_dss_hwmod_data *curr_dss_hwmod;
+
+        memset(&pdata, 0, sizeof(pdata));
+
+        if (cpu_is_omap24xx()) {
+                curr_dss_hwmod = omap2_dss_hwmod_data;
+                oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
+        } else if (cpu_is_omap34xx()) {
+                curr_dss_hwmod = omap3_dss_hwmod_data;
+                oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
+        } else {
+                curr_dss_hwmod = omap4_dss_hwmod_data;
+                oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
+        }
+
+        /* opt_clks are always associated with dss hwmod */
+        oh_core = omap_hwmod_lookup("dss_core");
+        if (!oh_core) {
+                pr_err("Could not look up dss_core.\n");
+                return -ENODEV;
+        }
+
+        pdata.board_data = board_data;
+        pdata.board_data->get_last_off_on_transaction_id = NULL;
+        pdata.opt_clock_available = opt_clock_available;
+
+        for (i = 0; i < oh_count; i++) {
+                oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
+                if (!oh) {
+                        pr_err("Could not look up %s\n",
+                                curr_dss_hwmod[i].oh_name);
+                        return -ENODEV;
+                }
+
+                od = omap_device_build(curr_dss_hwmod[i].dev_name,
+                                curr_dss_hwmod[i].id, oh, &pdata,
+                                sizeof(struct omap_display_platform_data),
+                                omap_dss_latency,
+                                ARRAY_SIZE(omap_dss_latency), 0);
+
+                if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
+                                curr_dss_hwmod[i].oh_name))
+                        return -ENODEV;
+        }
+        omap_display_device.dev.platform_data = board_data;
+
+        r = platform_device_register(&omap_display_device);
+        if (r < 0)
+                printk(KERN_ERR "Unable to register OMAP-Display device\n");
+
+        return r;
+}
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
new file mode 100644
index 000000000000..c9ff0e79703d
--- /dev/null
+++ b/arch/arm/mach-omap2/dma.c
@@ -0,0 +1,297 @@
+/*
+ * OMAP2+ DMA driver
+ *
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into platform driver
+ *      - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/dma.h>
+
+#define OMAP2_DMA_STRIDE        0x60
+
+static u32 errata;
+static u8 dma_stride;
+
+static struct omap_dma_dev_attr *d;
+
+static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+
+static u16 reg_map[] = {
+        [REVISION]              = 0x00,
+        [GCR]                   = 0x78,
+        [IRQSTATUS_L0]          = 0x08,
+        [IRQSTATUS_L1]          = 0x0c,
+        [IRQSTATUS_L2]          = 0x10,
+        [IRQSTATUS_L3]          = 0x14,
+        [IRQENABLE_L0]          = 0x18,
+        [IRQENABLE_L1]          = 0x1c,
+        [IRQENABLE_L2]          = 0x20,
+        [IRQENABLE_L3]          = 0x24,
+        [SYSSTATUS]             = 0x28,
+        [OCP_SYSCONFIG]         = 0x2c,
+        [CAPS_0]                = 0x64,
+        [CAPS_2]                = 0x6c,
+        [CAPS_3]                = 0x70,
+        [CAPS_4]                = 0x74,
+
+        /* Common register offsets */
+        [CCR]                   = 0x80,
+        [CLNK_CTRL]             = 0x84,
+        [CICR]                  = 0x88,
+        [CSR]                   = 0x8c,
+        [CSDP]                  = 0x90,
+        [CEN]                   = 0x94,
+        [CFN]                   = 0x98,
+        [CSEI]                  = 0xa4,
+        [CSFI]                  = 0xa8,
+        [CDEI]                  = 0xac,
+        [CDFI]                  = 0xb0,
+        [CSAC]                  = 0xb4,
+        [CDAC]                  = 0xb8,
+
+        /* Channel specific register offsets */
+        [CSSA]                  = 0x9c,
+        [CDSA]                  = 0xa0,
+        [CCEN]                  = 0xbc,
+        [CCFN]                  = 0xc0,
+        [COLOR]                 = 0xc4,
+
+        /* OMAP4 specific registers */
+        [CDP]                   = 0xd0,
+        [CNDP]                  = 0xd4,
+        [CCDN]                  = 0xd8,
+};
+
+static struct omap_device_pm_latency omap2_dma_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static void __iomem *dma_base;
+static inline void dma_write(u32 val, int reg, int lch)
+{
+        u8  stride;
+        u32 offset;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        __raw_writel(val, dma_base + offset);
+}
+
+static inline u32 dma_read(int reg, int lch)
+{
+        u8 stride;
+        u32 offset, val;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        val = __raw_readl(dma_base + offset);
+        return val;
+}
+
+static inline void omap2_disable_irq_lch(int lch)
+{
+        u32 val;
+
+        val = dma_read(IRQENABLE_L0, lch);
+        val &= ~(1 << lch);
+        dma_write(val, IRQENABLE_L0, lch);
+}
+
+static void omap2_clear_dma(int lch)
+{
+        int i = dma_common_ch_start;
+
+        for (; i <= dma_common_ch_end; i += 1)
+                dma_write(0, i, lch);
+}
+
+static void omap2_show_dma_caps(void)
+{
+        u8 revision = dma_read(REVISION, 0) & 0xff;
+        printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
+                                revision >> 4, revision & 0xf);
+        return;
+}
+
+static u32 configure_dma_errata(void)
+{
+
+        /*
+         * Errata applicable for OMAP2430ES1.0 and all omap2420
+         *
+         * I.
+         * Erratum ID: Not Available
+         * Inter Frame DMA buffering issue DMA will wrongly
+         * buffer elements if packing and bursting is enabled. This might
+         * result in data gets stalled in FIFO at the end of the block.
+         * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
+         * guarantee no data will stay in the DMA FIFO in case inter frame
+         * buffering occurs
+         *
+         * II.
+         * Erratum ID: Not Available
+         * DMA may hang when several channels are used in parallel
+         * In the following configuration, DMA channel hanging can occur:
+         * a. Channel i, hardware synchronized, is enabled
+         * b. Another channel (Channel x), software synchronized, is enabled.
+         * c. Channel i is disabled before end of transfer
+         * d. Channel i is reenabled.
+         * e. Steps 1 to 4 are repeated a certain number of times.
+         * f. A third channel (Channel y), software synchronized, is enabled.
+         * Channel x and Channel y may hang immediately after step 'f'.
+         * Workaround:
+         * For any channel used - make sure NextLCH_ID is set to the value j.
+         */
+        if (cpu_is_omap2420() || (cpu_is_omap2430() &&
+                                (omap_type() == OMAP2430_REV_ES1_0))) {
+
+                SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
+                SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
+        }
+
+        /*
+         * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
+         * after a transaction error.
+         * Workaround: SW should explicitely disable the channel.
+         */
+        if (cpu_class_is_omap2())
+                SET_DMA_ERRATA(DMA_ERRATA_i378);
+
+        /*
+         * Erratum ID: i541: sDMA FIFO draining does not finish
+         * If sDMA channel is disabled on the fly, sDMA enters standby even
+         * through FIFO Drain is still in progress
+         * Workaround: Put sDMA in NoStandby more before a logical channel is
+         * disabled, then put it back to SmartStandby right after the channel
+         * finishes FIFO draining.
+         */
+        if (cpu_is_omap34xx())
+                SET_DMA_ERRATA(DMA_ERRATA_i541);
+
+        /*
+         * Erratum ID: i88 : Special programming model needed to disable DMA
+         * before end of block.
+         * Workaround: software must ensure that the DMA is configured in No
+         * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
+         */
+        if (omap_type() == OMAP3430_REV_ES1_0)
+                SET_DMA_ERRATA(DMA_ERRATA_i88);
+
+        /*
+         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        SET_DMA_ERRATA(DMA_ERRATA_3_3);
+
+        /*
+         * Erratum ID: Not Available
+         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+         * after secure sram context save and restore.
+         * Work around: Hence we need to manually clear those IRQs to avoid
+         * spurious interrupts. This affects only secure devices.
+         */
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                SET_DMA_ERRATA(DMA_ROMCODE_BUG);
+
+        return errata;
+}
+
+/* One time initializations */
+static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
+{
+        struct omap_device                      *od;
+        struct omap_system_dma_plat_info        *p;
+        struct resource                         *mem;
+        char                                    *name = "omap_dma_system";
+
+        dma_stride              = OMAP2_DMA_STRIDE;
+        dma_common_ch_start     = CSDP;
+        if (cpu_is_omap3630() || cpu_is_omap4430())
+                dma_common_ch_end = CCDN;
+        else
+                dma_common_ch_end = CCFN;
+
+        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
+        if (!p) {
+                pr_err("%s: Unable to allocate pdata for %s:%s\n",
+                        __func__, name, oh->name);
+                return -ENOMEM;
+        }
+
+        p->dma_attr             = (struct omap_dma_dev_attr *)oh->dev_attr;
+        p->disable_irq_lch      = omap2_disable_irq_lch;
+        p->show_dma_caps        = omap2_show_dma_caps;
+        p->clear_dma            = omap2_clear_dma;
+        p->dma_write            = dma_write;
+        p->dma_read             = dma_read;
+
+        p->clear_lch_regs       = NULL;
+
+        p->errata               = configure_dma_errata();
+
+        od = omap_device_build(name, 0, oh, p, sizeof(*p),
+                        omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
+        kfree(p);
+        if (IS_ERR(od)) {
+                pr_err("%s: Can't build omap_device for %s:%s.\n",
+                        __func__, name, oh->name);
+                return PTR_ERR(od);
+        }
+
+        mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
+                return -EINVAL;
+        }
+        dma_base = ioremap(mem->start, resource_size(mem));
+        if (!dma_base) {
+                dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
+                return -ENOMEM;
+        }
+
+        d = oh->dev_attr;
+        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+                                        (d->lch_count), GFP_KERNEL);
+
+        if (!d->chan) {
+                dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+static int __init omap2_system_dma_init(void)
+{
+        return omap_hwmod_for_each_by_class("dma",
+                        omap2_system_dma_init_dev, NULL);
+}
+arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ed8d330522f1..f77022be783d 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -26,15 +26,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/clkdev.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
-#include <asm/clkdev.h>
 
 #include "clock.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
@@ -225,10 +223,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 }
 
 /**
- * lookup_dco_sddiv -  Set j-type DPLL4 compensation variables
+ * _lookup_dco - Lookup DCO used by j-type DPLL
  * @clk: pointer to a DPLL struct clk
  * @dco: digital control oscillator selector
- * @sd_div: target sigma-delta divider
  * @m: DPLL multiplier to set
  * @n: DPLL divider to set
  *
@@ -237,11 +234,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
  * XXX This code is not needed for 3430/AM35xx; can it be optimized
  * out in non-multi-OMAP builds for those chips?
  */
-static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
-                             u8 n)
+static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
-        unsigned long fint, clkinp, sd; /* watch out for overflow */
-        int mod1, mod2;
+        unsigned long fint, clkinp; /* watch out for overflow */
 
         clkinp = clk->parent->rate;
         fint = (clkinp / n) * m;
@@ -250,6 +245,27 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
                 *dco = 2;
         else
                 *dco = 4;
+}
+
+/**
+ * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
+ * @clk: pointer to a DPLL struct clk
+ * @sd_div: target sigma-delta divider
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ *
+ * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
+ *
+ * XXX This code is not needed for 3430/AM35xx; can it be optimized
+ * out in non-multi-OMAP builds for those chips?
+ */
+static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
+{
+        unsigned long clkinp, sd; /* watch out for overflow */
+        int mod1, mod2;
+
+        clkinp = clk->parent->rate;
+
         /*
          * target sigma-delta to near 250MHz
          * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
@@ -278,6 +294,7 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 {
         struct dpll_data *dd = clk->dpll_data;
+        u8 dco, sd_div;
         u32 v;
 
         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
@@ -300,18 +317,16 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
         v |= m << __ffs(dd->mult_mask);
         v |= (n - 1) << __ffs(dd->div1_mask);
 
-        /*
-         * XXX This code is not needed for 3430/AM35XX; can it be optimized
-         * out in non-multi-OMAP builds for those chips?
-         */
-        if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) {
-                u8 dco, sd_div;
-                lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
-                /* XXX This probably will need revision for OMAP4 */
-                v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
-                        | OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
-                v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK);
-                v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
+        /* Configure dco and sd_div for dplls that have these fields */
+        if (dd->dco_mask) {
+                _lookup_dco(clk, &dco, m, n);
+                v &= ~(dd->dco_mask);
+                v |= dco << __ffs(dd->dco_mask);
+        }
+        if (dd->sddiv_mask) {
+                _lookup_sddiv(clk, &sd_div, m, n);
+                v &= ~(dd->sddiv_mask);
+                v |= sd_div << __ffs(dd->sddiv_mask);
         }
 
         __raw_writel(v, dd->mult_div1_reg);
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
new file mode 100644
index 000000000000..4e4da6160d05
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -0,0 +1,84 @@
+/*
+ * OMAP4-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm-regbits-44xx.h"
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+        u32 v;
+        u32 mask;
+
+        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+                return -EINVAL;
+
+        mask = clk->flags & CLOCK_CLKOUTX2 ?
+                        OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+                        OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+        v = __raw_readl(clk->clksel_reg);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+        u32 v;
+        u32 mask;
+
+        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+                return;
+
+        mask = clk->flags & CLOCK_CLKOUTX2 ?
+                        OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+                        OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+        v = __raw_readl(clk->clksel_reg);
+        /* Clear the bit to allow gatectrl */
+        v &= ~mask;
+        __raw_writel(v, clk->clksel_reg);
+}
+
+void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+{
+        u32 v;
+        u32 mask;
+
+        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+                return;
+
+        mask = clk->flags & CLOCK_CLKOUTX2 ?
+                        OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+                        OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+        v = __raw_readl(clk->clksel_reg);
+        /* Set the bit to deny gatectrl */
+        v |= mask;
+        __raw_writel(v, clk->clksel_reg);
+}
+
+const struct clkops clkops_omap4_dpllmx_ops = {
+        .allow_idle     = omap4_dpllmx_allow_gatectrl,
+        .deny_idle      = omap4_dpllmx_deny_gatectrl,
+};
+
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
new file mode 100644
index 000000000000..911cd2e68d46
--- /dev/null
+++ b/arch/arm/mach-omap2/dsp.c
@@ -0,0 +1,92 @@
+/*
+ * TI's OMAP DSP platform device registration
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * XXX The function pointers to the PRM/CM functions are incorrect and
+ * should be removed.  No device driver should be changing PRM/CM bits
+ * directly; that's a layering violation -- those bits are the responsibility
+ * of the OMAP PM core code.
+ */
+
+#include <linux/platform_device.h>
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
+#ifdef CONFIG_BRIDGE_DVFS
+#include <plat/omap-pm.h>
+#endif
+
+#include <plat/dsp.h>
+
+extern phys_addr_t omap_dsp_get_mempool_base(void);
+
+static struct platform_device *omap_dsp_pdev;
+
+static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
+#ifdef CONFIG_BRIDGE_DVFS
+        .dsp_set_min_opp = omap_pm_dsp_set_min_opp,
+        .dsp_get_opp = omap_pm_dsp_get_opp,
+        .cpu_set_freq = omap_pm_cpu_set_freq,
+        .cpu_get_freq = omap_pm_cpu_get_freq,
+#endif
+        .dsp_prm_read = omap2_prm_read_mod_reg,
+        .dsp_prm_write = omap2_prm_write_mod_reg,
+        .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits,
+        .dsp_cm_read = omap2_cm_read_mod_reg,
+        .dsp_cm_write = omap2_cm_write_mod_reg,
+        .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
+};
+
+static int __init omap_dsp_init(void)
+{
+        struct platform_device *pdev;
+        int err = -ENOMEM;
+        struct omap_dsp_platform_data *pdata = &omap_dsp_pdata;
+
+        pdata->phys_mempool_base = omap_dsp_get_mempool_base();
+
+        if (pdata->phys_mempool_base) {
+                pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
+                pr_info("%s: %x bytes @ %x\n", __func__,
+                        pdata->phys_mempool_size, pdata->phys_mempool_base);
+        }
+
+        pdev = platform_device_alloc("omap-dsp", -1);
+        if (!pdev)
+                goto err_out;
+
+        err = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+        if (err)
+                goto err_out;
+
+        err = platform_device_add(pdev);
+        if (err)
+                goto err_out;
+
+        omap_dsp_pdev = pdev;
+        return 0;
+
+err_out:
+        platform_device_put(pdev);
+        return err;
+}
+module_init(omap_dsp_init);
+
+static void __exit omap_dsp_exit(void)
+{
+        platform_device_unregister(omap_dsp_pdev);
+}
+module_exit(omap_dsp_exit);
+
+MODULE_AUTHOR("Hiroshi DOYU");
+MODULE_DESCRIPTION("TI's OMAP DSP platform device registration");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
new file mode 100644
index 000000000000..9529842ae054
--- /dev/null
+++ b/arch/arm/mach-omap2/gpio.c
@@ -0,0 +1,104 @@
+/*
+ * OMAP2+ specific gpio initialization
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *      Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static struct omap_device_pm_latency omap_gpio_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
+{
+        struct omap_device *od;
+        struct omap_gpio_platform_data *pdata;
+        struct omap_gpio_dev_attr *dev_attr;
+        char *name = "omap_gpio";
+        int id;
+
+        /*
+         * extract the device id from name field available in the
+         * hwmod database and use the same for constructing ids for
+         * gpio devices.
+         * CAUTION: Make sure the name in the hwmod database does
+         * not change. If changed, make corresponding change here
+         * or make use of static variable mechanism to handle this.
+         */
+        sscanf(oh->name, "gpio%d", &id);
+
+        pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("gpio%d: Memory allocation failed\n", id);
+                return -ENOMEM;
+        }
+
+        dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
+        pdata->bank_width = dev_attr->bank_width;
+        pdata->dbck_flag = dev_attr->dbck_flag;
+        pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
+
+        switch (oh->class->rev) {
+        case 0:
+        case 1:
+                pdata->bank_type = METHOD_GPIO_24XX;
+                break;
+        case 2:
+                pdata->bank_type = METHOD_GPIO_44XX;
+                break;
+        default:
+                WARN(1, "Invalid gpio bank_type\n");
+                kfree(pdata);
+                return -EINVAL;
+        }
+
+        od = omap_device_build(name, id - 1, oh, pdata,
+                                sizeof(*pdata), omap_gpio_latency,
+                                ARRAY_SIZE(omap_gpio_latency),
+                                false);
+        kfree(pdata);
+
+        if (IS_ERR(od)) {
+                WARN(1, "Can't build omap_device for %s:%s.\n",
+                                        name, oh->name);
+                return PTR_ERR(od);
+        }
+
+        gpio_bank_count++;
+        return 0;
+}
+
+/*
+ * gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence gpio_init is a postcore_initcall.
+ */
+static int __init omap2_gpio_init(void)
+{
+        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
+                                                NULL);
+}
+postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 722209601927..c1791d08ae56 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach/flash.h>
 
@@ -41,7 +42,7 @@ static int omap2_nand_gpmc_retime(void)
                 return 0;
 
         memset(&t, 0, sizeof(t));
-        t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);
+        t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
         t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
         t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
 
@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
         t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
 
         /* Configure GPMC */
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                                GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize);
+        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
+        else
+                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
         gpmc_cs_configure(gpmc_nand_data->cs,
                         GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 7bb69220adfa..d776ded9830d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-                                int sync_read, int sync_write, int hf)
+                                int sync_read, int sync_write, int hf, int vhf)
 {
         u32 reg;
 
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
                 reg |= ONENAND_SYS_CFG1_HF;
         else
                 reg &= ~ONENAND_SYS_CFG1_HF;
+        if (vhf)
+                reg |= ONENAND_SYS_CFG1_VHF;
+        else
+                reg &= ~ONENAND_SYS_CFG1_VHF;
         writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
+static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
+                                  void __iomem *onenand_base, bool *clk_dep)
+{
+        u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
+        int freq = 0;
+
+        if (cfg->get_freq) {
+                struct onenand_freq_info fi;
+
+                fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
+                fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
+                fi.ver_id = ver;
+                freq = cfg->get_freq(&fi, clk_dep);
+                if (freq)
+                        return freq;
+        }
+
+        switch ((ver >> 4) & 0xf) {
+        case 0:
+                freq = 40;
+                break;
+        case 1:
+                freq = 54;
+                break;
+        case 2:
+                freq = 66;
+                break;
+        case 3:
+                freq = 83;
+                break;
+        case 4:
+                freq = 104;
+                break;
+        default:
+                freq = 54;
+                break;
+        }
+
+        return freq;
+}
+
 static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                                         void __iomem *onenand_base,
-                                        int freq)
+                                        int *freq_ptr)
 {
         struct gpmc_timings t;
         const int t_cer  = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         const int t_wph  = 30;
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-        int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
+        int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
         int err, ticks_cez;
-        int cs = cfg->cs;
+        int cs = cfg->cs, freq = *freq_ptr;
         u32 reg;
+        bool clk_dep = false;
 
         if (cfg->flags & ONENAND_SYNC_READ) {
                 sync_read = 1;
@@ -148,33 +194,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 err = omap2_onenand_set_async_mode(cs, onenand_base);
                 if (err)
                         return err;
-                reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
-                switch ((reg >> 4) & 0xf) {
-                case 0:
-                        freq = 40;
-                        break;
-                case 1:
-                        freq = 54;
-                        break;
-                case 2:
-                        freq = 66;
-                        break;
-                case 3:
-                        freq = 83;
-                        break;
-                case 4:
-                        freq = 104;
-                        break;
-                default:
-                        freq = 54;
-                        break;
-                }
+                freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
                 first_time = 1;
         }
 
         switch (freq) {
+        case 104:
+                min_gpmc_clk_period = 9600; /* 104 MHz */
+                t_ces   = 3;
+                t_avds  = 4;
+                t_avdh  = 2;
+                t_ach   = 3;
+                t_aavdh = 6;
+                t_rdyo  = 6;
+                break;
         case 83:
-                min_gpmc_clk_period = 12; /* 83 MHz */
+                min_gpmc_clk_period = 12000; /* 83 MHz */
                 t_ces   = 5;
                 t_avds  = 4;
                 t_avdh  = 2;
@@ -183,7 +218,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_rdyo  = 9;
                 break;
         case 66:
-                min_gpmc_clk_period = 15; /* 66 MHz */
+                min_gpmc_clk_period = 15000; /* 66 MHz */
                 t_ces   = 6;
                 t_avds  = 5;
                 t_avdh  = 2;
@@ -192,7 +227,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_rdyo  = 11;
                 break;
         default:
-                min_gpmc_clk_period = 18; /* 54 MHz */
+                min_gpmc_clk_period = 18500; /* 54 MHz */
                 t_ces   = 7;
                 t_avds  = 7;
                 t_avdh  = 7;
@@ -208,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         gpmc_clk_ns = gpmc_ticks_to_ns(div);
         if (gpmc_clk_ns < 15) /* >66Mhz */
                 hf = 1;
-        if (hf)
+        if (gpmc_clk_ns < 12) /* >83Mhz */
+                vhf = 1;
+        if (vhf)
+                latency = 8;
+        else if (hf)
                 latency = 6;
         else if (gpmc_clk_ns >= 25) /* 40 MHz*/
                 latency = 3;
         else
                 latency = 4;
 
+        if (clk_dep) {
+                if (gpmc_clk_ns < 12) { /* >83Mhz */
+                        t_ces   = 3;
+                        t_avds  = 4;
+                } else if (gpmc_clk_ns < 15) { /* >66Mhz */
+                        t_ces   = 5;
+                        t_avds  = 4;
+                } else if (gpmc_clk_ns < 25) { /* >40Mhz */
+                        t_ces   = 6;
+                        t_avds  = 5;
+                } else {
+                        t_ces   = 7;
+                        t_avds  = 7;
+                }
+        }
+
         if (first_time)
                 set_onenand_cfg(onenand_base, latency,
-                                        sync_read, sync_write, hf);
+                                        sync_read, sync_write, hf, vhf);
 
         if (div == 1) {
                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -255,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         /* Read */
         t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
         t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
+        /* Force at least 1 clk between AVD High to OE Low */
+        if (t.oe_on <= t.adv_rd_off)
+                t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
         t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
         t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
         t.cs_rd_off = t.oe_off;
@@ -271,8 +329,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t.wr_cycle  = t.rd_cycle;
                 if (cpu_is_omap34xx()) {
                         t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
-                                        gpmc_ns_to_ticks(min_gpmc_clk_period +
-                                        t_rdyo));
+                                        gpmc_ps_to_ticks(min_gpmc_clk_period +
+                                        t_rdyo * 1000));
                         t.wr_access = t.access;
                 }
         } else {
@@ -308,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         if (err)
                 return err;
 
-        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
+        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+
+        *freq_ptr = freq;
 
         return 0;
 }
 
-static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
+static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
         struct device *dev = &gpmc_onenand_device.dev;
 
         /* Set sync timings in GPMC */
         if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
-                        freq) < 0) {
+                        freq_ptr) < 0) {
                 dev_err(dev, "Unable to set synchronous mode\n");
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 877c6f5807b7..ba10c24f3d8d 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -147,25 +147,24 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
                         goto free1;
         }
 
-        if (gpio_request(gpmc_cfg->gpio_irq, "SMC91X irq") < 0)
+        if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "SMC91X irq") < 0)
                 goto free1;
 
-        gpio_direction_input(gpmc_cfg->gpio_irq);
         gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
 
         if (gpmc_cfg->gpio_pwrdwn) {
-                ret = gpio_request(gpmc_cfg->gpio_pwrdwn, "SMC91X powerdown");
+                ret = gpio_request_one(gpmc_cfg->gpio_pwrdwn,
+                                       GPIOF_OUT_INIT_LOW, "SMC91X powerdown");
                 if (ret)
                         goto free2;
-                gpio_direction_output(gpmc_cfg->gpio_pwrdwn, 0);
         }
 
         if (gpmc_cfg->gpio_reset) {
-                ret = gpio_request(gpmc_cfg->gpio_reset, "SMC91X reset");
+                ret = gpio_request_one(gpmc_cfg->gpio_reset,
+                                       GPIOF_OUT_INIT_LOW, "SMC91X reset");
                 if (ret)
                         goto free3;
 
-                gpio_direction_output(gpmc_cfg->gpio_reset, 0);
                 gpio_set_value(gpmc_cfg->gpio_reset, 1);
                 msleep(100);
                 gpio_set_value(gpmc_cfg->gpio_reset, 0);
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
new file mode 100644
index 000000000000..997033129d26
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -0,0 +1,107 @@
+/*
+ * linux/arch/arm/mach-omap2/gpmc-smsc911x.c
+ *
+ * Copyright (C) 2009 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/smsc911x.h>
+
+#include <plat/board.h>
+#include <plat/gpmc.h>
+#include <plat/gpmc-smsc911x.h>
+
+static struct omap_smsc911x_platform_data *gpmc_cfg;
+
+static struct resource gpmc_smsc911x_resources[] = {
+        [0] = {
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+
+static struct smsc911x_platform_config gpmc_smsc911x_config = {
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_16BIT,
+};
+
+/*
+ * Initialize smsc911x device connected to the GPMC. Note that we
+ * assume that pin multiplexing is done in the board-*.c file,
+ * or in the bootloader.
+ */
+void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
+{
+        struct platform_device *pdev;
+        unsigned long cs_mem_base;
+        int ret;
+
+        gpmc_cfg = board_data;
+
+        if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
+                pr_err("Failed to request GPMC mem region\n");
+                return;
+        }
+
+        gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
+        gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
+
+        if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
+                pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
+                goto free1;
+        }
+
+        gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
+
+        if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
+                ret = gpio_request_one(gpmc_cfg->gpio_reset,
+                                       GPIOF_OUT_INIT_HIGH, "smsc911x reset");
+                if (ret) {
+                        pr_err("Failed to request reset GPIO%d\n",
+                               gpmc_cfg->gpio_reset);
+                        goto free2;
+                }
+
+                gpio_set_value(gpmc_cfg->gpio_reset, 0);
+                msleep(100);
+                gpio_set_value(gpmc_cfg->gpio_reset, 1);
+        }
+
+        if (gpmc_cfg->flags)
+                gpmc_smsc911x_config.flags = gpmc_cfg->flags;
+
+        pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
+                 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
+                 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
+        if (!pdev) {
+                pr_err("Unable to register platform device\n");
+                gpio_free(gpmc_cfg->gpio_reset);
+                goto free2;
+        }
+
+        return;
+
+free2:
+        gpio_free(gpmc_cfg->gpio_irq);
+free1:
+        gpmc_cs_free(gpmc_cfg->cs);
+
+        pr_err("Could not initialize smsc911x device\n");
+}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f46933bc9373..130034bf01d5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
  */
 #undef DEBUG
 
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/err.h>
@@ -22,6 +23,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
@@ -58,7 +60,6 @@
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 
-#define PREFETCH_FIFOTHRESHOLD  (0x40 << 8)
 #define CS_NUM_SHIFT            24
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
@@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
 
+static irqreturn_t gpmc_handle_irq(int irq, void *dev);
+
 static void gpmc_write_reg(int idx, u32 val)
 {
         __raw_writel(val, gpmc_base + idx);
@@ -168,6 +171,16 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
+unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+{
+        unsigned long tick_ps;
+
+        /* Calculate in picosecs to yield more exact results */
+        tick_ps = gpmc_get_fclk_period();
+
+        return (time_ps + tick_ps - 1) / tick_ps;
+}
+
 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period() / 1000;
@@ -235,7 +248,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
         int div;
         u32 l;
 
-        l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
+        l = sync_clk + (gpmc_get_fclk_period() - 1);
         div = l / gpmc_get_fclk_period();
         if (div > 4)
                 return -1;
@@ -487,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
         u32 regval = 0;
 
         switch (cmd) {
+        case GPMC_ENABLE_IRQ:
+                gpmc_write_reg(GPMC_IRQENABLE, wval);
+                break;
+
         case GPMC_SET_IRQ_STATUS:
                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
                 break;
@@ -588,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
 /**
  * gpmc_prefetch_enable - configures and starts prefetch transfer
  * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
  * @dma_mode: dma mode enable (1) or disable (0)
  * @u32_count: number of bytes to be transferred
  * @is_write: prefetch read(0) or write post(1) mode
  */
-int gpmc_prefetch_enable(int cs, int dma_mode,
+int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                 unsigned int u32_count, int is_write)
 {
 
-        if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
+        if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
+                pr_err("gpmc: fifo threshold is not supported\n");
+                return -1;
+        } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
                 /* Set the amount of bytes to be prefetched */
                 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 
@@ -604,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
                  * enable the engine. Set which cs is has requested for.
                  */
                 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
-                                        PREFETCH_FIFOTHRESHOLD |
+                                        PREFETCH_FIFOTHRESHOLD(fifo_th) |
                                         ENABLE_PREFETCH |
                                         (dma_mode << DMA_MPU_MODE) |
                                         (0x1 & is_write)));
@@ -668,9 +689,11 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-void __init gpmc_init(void)
+static int __init gpmc_init(void)
 {
-        u32 l;
+        u32 l, irq;
+        int cs, ret = -EINVAL;
+        int gpmc_irq;
         char *ck = NULL;
 
         if (cpu_is_omap24xx()) {
@@ -679,16 +702,19 @@ void __init gpmc_init(void)
                         l = OMAP2420_GPMC_BASE;
                 else
                         l = OMAP34XX_GPMC_BASE;
+                gpmc_irq = INT_34XX_GPMC_IRQ;
         } else if (cpu_is_omap34xx()) {
                 ck = "gpmc_fck";
                 l = OMAP34XX_GPMC_BASE;
+                gpmc_irq = INT_34XX_GPMC_IRQ;
         } else if (cpu_is_omap44xx()) {
                 ck = "gpmc_ck";
                 l = OMAP44XX_GPMC_BASE;
+                gpmc_irq = OMAP44XX_IRQ_GPMC;
         }
 
         if (WARN_ON(!ck))
-                return;
+                return ret;
 
         gpmc_l3_clk = clk_get(NULL, ck);
         if (IS_ERR(gpmc_l3_clk)) {
@@ -713,6 +739,35 @@ void __init gpmc_init(void)
         l |= (0x02 << 3) | (1 << 0);
         gpmc_write_reg(GPMC_SYSCONFIG, l);
         gpmc_mem_init();
+
+        /* initalize the irq_chained */
+        irq = OMAP_GPMC_IRQ_BASE;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                irq_set_chip_and_handler(irq, &dummy_irq_chip,
+                                                handle_simple_irq);
+                set_irq_flags(irq, IRQF_VALID);
+                irq++;
+        }
+
+        ret = request_irq(gpmc_irq,
+                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
+        if (ret)
+                pr_err("gpmc: irq-%d could not claim: err %d\n",
+                                                gpmc_irq, ret);
+        return ret;
+}
+postcore_initcall(gpmc_init);
+
+static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+{
+        u8 cs;
+
+        /* check cs to invoke the irq */
+        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
+        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
+                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+
+        return IRQ_HANDLED;
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index c8f647b6205e..66868c5d5a29 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,11 +14,14 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <mach/hardware.h>
-#include <plat/control.h>
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
+#include <plat/mux.h>
+#include <plat/omap_device.h>
 
+#include "mux.h"
 #include "hsmmc.h"
+#include "control.h"
 
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
@@ -28,10 +31,6 @@ static u16 control_mmc1;
 
 #define HSMMC_NAME_LEN  9
 
-static struct hsmmc_controller {
-        char                            name[HSMMC_NAME_LEN + 1];
-} hsmmc[OMAP34XX_NR_MMC];
-
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 
 static int hsmmc_get_context_loss(struct device *dev)
@@ -135,42 +134,53 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
          *
          * FIXME handle VMMC1A as needed ...
          */
-        reg = omap_ctrl_readl(control_pbias_offset);
-        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
-                                        OMAP4_USBC1_ICUSB_PWRDNZ);
-        omap_ctrl_writel(reg, control_pbias_offset);
+        reg = omap4_ctrl_pad_readl(control_pbias_offset);
+        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                OMAP4_MMC1_PWRDNZ_MASK |
+                OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+        omap4_ctrl_pad_writel(reg, control_pbias_offset);
 }
 
 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
                                  int power_on, int vdd)
 {
         u32 reg;
+        unsigned long timeout;
 
         if (power_on) {
-                reg = omap_ctrl_readl(control_pbias_offset);
-                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
                 if ((1 << vdd) <= MMC_VDD_165_195)
-                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
+                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
                 else
-                        reg |= OMAP4_MMC1_PBIASLITE_VMODE;
-                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
-                                                OMAP4_USBC1_ICUSB_PWRDNZ);
-                omap_ctrl_writel(reg, control_pbias_offset);
-                /* 4 microsec delay for comparator to generate an error*/
-                udelay(4);
-                reg = omap_ctrl_readl(control_pbias_offset);
-                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
+                        reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
+                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                        OMAP4_MMC1_PWRDNZ_MASK |
+                        OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                omap4_ctrl_pad_writel(reg, control_pbias_offset);
+
+                timeout = jiffies + msecs_to_jiffies(5);
+                do {
+                        reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                        if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
+                                break;
+                        usleep_range(100, 200);
+                } while (!time_after(jiffies, timeout));
+
+                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
                         pr_err("Pbias Voltage is not same as LDO\n");
                         /* Caution : On VMODE_ERROR Power Down MMC IO */
-                        reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
-                        omap_ctrl_writel(reg, control_pbias_offset);
+                        reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
+                                OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                        omap4_ctrl_pad_writel(reg, control_pbias_offset);
                 }
         } else {
-                reg = omap_ctrl_readl(control_pbias_offset);
-                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
-                        OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
-                        OMAP4_USBC1_ICUSB_PWRDNZ);
-                omap_ctrl_writel(reg, control_pbias_offset);
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                        OMAP4_MMC1_PWRDNZ_MASK |
+                        OMAP4_MMC1_PBIASLITE_VMODE_MASK |
+                        OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                omap4_ctrl_pad_writel(reg, control_pbias_offset);
         }
 }
 
@@ -200,162 +210,315 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
         return 0;
 }
 
-static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
-
-void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
+                        int controller_nr)
 {
-        struct omap2_hsmmc_info *c;
-        int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
-        int i;
-        u32 reg;
-
-        if (!cpu_is_omap44xx()) {
-                if (cpu_is_omap2430()) {
-                        control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-                } else {
-                        control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
+        if ((mmc_controller->slots[0].switch_pin > 0) && \
+                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
+                                        OMAP_PIN_INPUT_PULLUP);
+        if ((mmc_controller->slots[0].gpio_wp > 0) && \
+                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
+                                        OMAP_PIN_INPUT_PULLUP);
+        if (cpu_is_omap34xx()) {
+                if (controller_nr == 0) {
+                        omap_mux_init_signal("sdmmc1_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+                                omap_mux_init_signal("sdmmc1_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
+                        if (mmc_controller->slots[0].caps &
+                                                MMC_CAP_8_BIT_DATA) {
+                                omap_mux_init_signal("sdmmc1_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
+                }
+                if (controller_nr == 1) {
+                        /* MMC2 */
+                        omap_mux_init_signal("sdmmc2_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
+
+                        /*
+                         * For 8 wire configurations, Lines DAT4, 5, 6 and 7
+                         * need to be muxed in the board-*.c files
+                         */
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+                                omap_mux_init_signal("sdmmc2_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
+                        if (mmc_controller->slots[0].caps &
+                                                        MMC_CAP_8_BIT_DATA) {
+                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
                 }
-        } else {
-                control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
-                control_mmc1 = OMAP44XX_CONTROL_MMC1;
-                reg = omap_ctrl_readl(control_mmc1);
-                reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
-                        OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
-                reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
-                        OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
-                reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
-                        OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
-                        OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
-                omap_ctrl_writel(reg, control_mmc1);
-        }
 
-        for (c = controllers; c->mmc; c++) {
-                struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
-                struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+                /*
+                 * For MMC3 the pins need to be muxed in the board-*.c files
+                 */
+        }
+}
 
-                if (!c->mmc || c->mmc > nr_hsmmc) {
-                        pr_debug("MMC%d: no such controller\n", c->mmc);
-                        continue;
-                }
-                if (mmc) {
-                        pr_debug("MMC%d: already configured\n", c->mmc);
-                        continue;
-                }
+static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
+                                        struct omap_mmc_platform_data *mmc)
+{
+        char *hc_name;
 
-                mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
-                              GFP_KERNEL);
-                if (!mmc) {
-                        pr_err("Cannot allocate memory for mmc device!\n");
-                        goto done;
-                }
+        hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
+        if (!hc_name) {
+                pr_err("Cannot allocate memory for controller slot name\n");
+                kfree(hc_name);
+                return -ENOMEM;
+        }
 
-                if (c->name)
-                        strncpy(hc->name, c->name, HSMMC_NAME_LEN);
-                else
-                        snprintf(hc->name, ARRAY_SIZE(hc->name),
-                                "mmc%islot%i", c->mmc, 1);
-                mmc->slots[0].name = hc->name;
-                mmc->nr_slots = 1;
-                mmc->slots[0].wires = c->wires;
-                mmc->slots[0].internal_clock = !c->ext_clock;
-                mmc->dma_mask = 0xffffffff;
+        if (c->name)
+                strncpy(hc_name, c->name, HSMMC_NAME_LEN);
+        else
+                snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
+                                                                c->mmc, 1);
+        mmc->slots[0].name = hc_name;
+        mmc->nr_slots = 1;
+        mmc->slots[0].caps = c->caps;
+        mmc->slots[0].internal_clock = !c->ext_clock;
+        mmc->dma_mask = 0xffffffff;
+        if (cpu_is_omap44xx())
+                mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
+        else
+                mmc->reg_offset = 0;
 
-                mmc->get_context_loss_count = hsmmc_get_context_loss;
+        mmc->get_context_loss_count = hsmmc_get_context_loss;
 
-                mmc->slots[0].switch_pin = c->gpio_cd;
-                mmc->slots[0].gpio_wp = c->gpio_wp;
+        mmc->slots[0].switch_pin = c->gpio_cd;
+        mmc->slots[0].gpio_wp = c->gpio_wp;
 
-                mmc->slots[0].remux = c->remux;
-                mmc->slots[0].init_card = c->init_card;
+        mmc->slots[0].remux = c->remux;
+        mmc->slots[0].init_card = c->init_card;
 
-                if (c->cover_only)
-                        mmc->slots[0].cover = 1;
+        if (c->cover_only)
+                mmc->slots[0].cover = 1;
 
-                if (c->nonremovable)
-                        mmc->slots[0].nonremovable = 1;
+        if (c->nonremovable)
+                mmc->slots[0].nonremovable = 1;
 
-                if (c->power_saving)
-                        mmc->slots[0].power_saving = 1;
+        if (c->power_saving)
+                mmc->slots[0].power_saving = 1;
 
-                if (c->no_off)
-                        mmc->slots[0].no_off = 1;
+        if (c->no_off)
+                mmc->slots[0].no_off = 1;
 
-                if (c->vcc_aux_disable_is_sleep)
-                        mmc->slots[0].vcc_aux_disable_is_sleep = 1;
+        if (c->no_off_init)
+                mmc->slots[0].no_regulator_off_init = c->no_off_init;
 
-                /* NOTE:  MMC slots should have a Vcc regulator set up.
-                 * This may be from a TWL4030-family chip, another
-                 * controllable regulator, or a fixed supply.
-                 *
-                 * temporary HACK: ocr_mask instead of fixed supply
-                 */
-                mmc->slots[0].ocr_mask = c->ocr_mask;
+        if (c->vcc_aux_disable_is_sleep)
+                mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 
-                if (cpu_is_omap3517() || cpu_is_omap3505())
-                        mmc->slots[0].set_power = nop_mmc_set_power;
-                else
-                        mmc->slots[0].features |= HSMMC_HAS_PBIAS;
-
-                switch (c->mmc) {
-                case 1:
-                        if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
-                                /* on-chip level shifting via PBIAS0/PBIAS1 */
-                                if (cpu_is_omap44xx()) {
-                                        mmc->slots[0].before_set_reg =
+        /*
+         * NOTE:  MMC slots should have a Vcc regulator set up.
+         * This may be from a TWL4030-family chip, another
+         * controllable regulator, or a fixed supply.
+         *
+         * temporary HACK: ocr_mask instead of fixed supply
+         */
+        mmc->slots[0].ocr_mask = c->ocr_mask;
+
+        if (cpu_is_omap3517() || cpu_is_omap3505())
+                mmc->slots[0].set_power = nop_mmc_set_power;
+        else
+                mmc->slots[0].features |= HSMMC_HAS_PBIAS;
+
+        if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+                mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+
+        switch (c->mmc) {
+        case 1:
+                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+                        /* on-chip level shifting via PBIAS0/PBIAS1 */
+                        if (cpu_is_omap44xx()) {
+                                mmc->slots[0].before_set_reg =
                                                 omap4_hsmmc1_before_set_reg;
-                                        mmc->slots[0].after_set_reg =
+                                mmc->slots[0].after_set_reg =
                                                 omap4_hsmmc1_after_set_reg;
-                                } else {
-                                        mmc->slots[0].before_set_reg =
+                        } else {
+                                mmc->slots[0].before_set_reg =
                                                 omap_hsmmc1_before_set_reg;
-                                        mmc->slots[0].after_set_reg =
+                                mmc->slots[0].after_set_reg =
                                                 omap_hsmmc1_after_set_reg;
-                                }
                         }
+                }
 
-                        /* Omap3630 HSMMC1 supports only 4-bit */
-                        if (cpu_is_omap3630() && c->wires > 4) {
-                                c->wires = 4;
-                                mmc->slots[0].wires = c->wires;
-                        }
-                        break;
-                case 2:
-                        if (c->ext_clock)
-                                c->transceiver = 1;
-                        if (c->transceiver && c->wires > 4)
-                                c->wires = 4;
-                        /* FALLTHROUGH */
-                case 3:
-                        if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
-                                /* off-chip level shifting, or none */
-                                mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
-                                mmc->slots[0].after_set_reg = NULL;
-                        }
-                        break;
-                default:
-                        pr_err("MMC%d configuration not supported!\n", c->mmc);
-                        kfree(mmc);
-                        continue;
+                /* OMAP3630 HSMMC1 supports only 4-bit */
+                if (cpu_is_omap3630() &&
+                                (c->caps & MMC_CAP_8_BIT_DATA)) {
+                        c->caps &= ~MMC_CAP_8_BIT_DATA;
+                        c->caps |= MMC_CAP_4_BIT_DATA;
+                        mmc->slots[0].caps = c->caps;
+                }
+                break;
+        case 2:
+                if (c->ext_clock)
+                        c->transceiver = 1;
+                if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
+                        c->caps &= ~MMC_CAP_8_BIT_DATA;
+                        c->caps |= MMC_CAP_4_BIT_DATA;
+                }
+                /* FALLTHROUGH */
+        case 3:
+                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+                        /* off-chip level shifting, or none */
+                        mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
+                        mmc->slots[0].after_set_reg = NULL;
                 }
-                hsmmc_data[c->mmc - 1] = mmc;
+                break;
+        case 4:
+        case 5:
+                mmc->slots[0].before_set_reg = NULL;
+                mmc->slots[0].after_set_reg = NULL;
+                break;
+        default:
+                pr_err("MMC%d configuration not supported!\n", c->mmc);
+                kfree(hc_name);
+                return -ENODEV;
         }
+        return 0;
+}
 
-        omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+static struct omap_device_pm_latency omap_hsmmc_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+        /*
+         * XXX There should also be an entry here to power off/on the
+         * MMC regulators/PBIAS cells, etc.
+         */
+};
 
-        /* pass the device nodes back to board setup code */
-        for (c = controllers; c->mmc; c++) {
-                struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+#define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 
-                if (!c->mmc || c->mmc > nr_hsmmc)
-                        continue;
-                c->dev = mmc->dev;
+void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
+{
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        struct omap_device_pm_latency *ohl;
+        char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
+        struct omap_mmc_platform_data *mmc_data;
+        struct omap_mmc_dev_attr *mmc_dev_attr;
+        char *name;
+        int l;
+        int ohl_cnt = 0;
+
+        mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
+        if (!mmc_data) {
+                pr_err("Cannot allocate memory for mmc device!\n");
+                goto done;
         }
 
+        if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
+                pr_err("%s fails!\n", __func__);
+                goto done;
+        }
+        omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+
+        name = "omap_hsmmc";
+        ohl = omap_hsmmc_latency;
+        ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
+
+        l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
+                     "mmc%d", ctrl_nr);
+        WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
+             "String buffer overflow in MMC%d device setup\n", ctrl_nr);
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                kfree(mmc_data->slots[0].name);
+                goto done;
+        }
+
+        if (oh->dev_attr != NULL) {
+                mmc_dev_attr = oh->dev_attr;
+                mmc_data->controller_flags = mmc_dev_attr->flags;
+        }
+
+        od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
+                sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
+        if (IS_ERR(od)) {
+                WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
+                kfree(mmc_data->slots[0].name);
+                goto done;
+        }
+        /*
+         * return device handle to board setup code
+         * required to populate for regulator framework structure
+         */
+        hsmmcinfo->dev = &od->pdev.dev;
+
 done:
-        for (i = 0; i < nr_hsmmc; i++)
-                kfree(hsmmc_data[i]);
+        kfree(mmc_data);
+}
+
+void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+        u32 reg;
+
+        if (!cpu_is_omap44xx()) {
+                if (cpu_is_omap2430()) {
+                        control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
+                        control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
+                } else {
+                        control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+                        control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
+                }
+        } else {
+                control_pbias_offset =
+                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
+                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
+                reg = omap4_ctrl_pad_readl(control_mmc1);
+                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
+                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
+                reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
+                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
+                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
+                omap4_ctrl_pad_writel(reg, control_mmc1);
+        }
+
+        for (; controllers->mmc; controllers++)
+                omap_init_hsmmc(controllers, controllers->mmc);
+
 }
 
 #endif
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 1fe6f0187177..f757e78d4d4f 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -10,20 +10,22 @@ struct mmc_card;
 
 struct omap2_hsmmc_info {
         u8      mmc;            /* controller 1/2/3 */
-        u8      wires;          /* 1/4/8 wires */
+        u32     caps;           /* 4/8 wires and any additional host
+                                 * capabilities OR'd (ref. linux/mmc/host.h) */
         bool    transceiver;    /* MMC-2 option */
         bool    ext_clock;      /* use external pin for input clock */
         bool    cover_only;     /* No card detect - just cover switch */
         bool    nonremovable;   /* Nonremovable e.g. eMMC */
         bool    power_saving;   /* Try to sleep or power off when possible */
         bool    no_off;         /* power_saving and power is not to go off */
+        bool    no_off_init;    /* no power off when not in MMC sleep state */
         bool    vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
         int     gpio_cd;        /* or -EINVAL */
         int     gpio_wp;        /* or -EINVAL */
         char    *name;          /* or NULL for default */
         struct device *dev;     /* returned: pointer to mmc adapter */
         int     ocr_mask;       /* temporary HACK */
-        /* Remux (pad configuation) when powering on/off */
+        /* Remux (pad configuration) when powering on/off */
         void (*remux)(struct device *dev, int slot, int power_on);
         /* init some special card */
         void (*init_card)(struct mmc_card *card);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
new file mode 100644
index 000000000000..06d4a80660a5
--- /dev/null
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -0,0 +1,63 @@
+/*
+ * OMAP hardware spinlock device initialization
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Contact: Simon Que <sque@ti.com>
+ *          Hari Kanigeri <h-kanigeri2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+struct omap_device_pm_latency omap_spinlock_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        }
+};
+
+int __init hwspinlocks_init(void)
+{
+        int retval = 0;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        const char *oh_name = "spinlock";
+        const char *dev_name = "omap_hwspinlock";
+
+        /*
+         * Hwmod lookup will fail in case our platform doesn't support the
+         * hardware spinlock module, so it is safe to run this initcall
+         * on all omaps
+         */
+        oh = omap_hwmod_lookup(oh_name);
+        if (oh == NULL)
+                return -EINVAL;
+
+        od = omap_device_build(dev_name, 0, oh, NULL, 0,
+                                omap_spinlock_latency,
+                                ARRAY_SIZE(omap_spinlock_latency), false);
+        if (IS_ERR(od)) {
+                pr_err("Can't build omap_device for %s:%s\n", dev_name,
+                                                                oh_name);
+                retval = PTR_ERR(od);
+        }
+
+        return retval;
+}
+/* early board code might need to reserve specific hwspinlock instances */
+postcore_initcall(hwspinlocks_init);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9a879f959509..2537090aa33a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
  * Copyright (C) 2005 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
  *
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-11 Texas Instruments
  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -22,11 +22,12 @@
 #include <asm/cputype.h>
 
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/cpu.h>
 
 #include <mach/id.h>
 
+#include "control.h"
+
 static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 
@@ -60,7 +61,7 @@ int omap_type(void)
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
-                val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
+                val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
         } else {
                 pr_err("Cannot detect omap type!\n");
                 goto out;
@@ -83,6 +84,11 @@ EXPORT_SYMBOL(omap_type);
 #define OMAP_TAP_DIE_ID_2       0x0220
 #define OMAP_TAP_DIE_ID_3       0x0224
 
+#define OMAP_TAP_DIE_ID_44XX_0  0x0200
+#define OMAP_TAP_DIE_ID_44XX_1  0x0208
+#define OMAP_TAP_DIE_ID_44XX_2  0x020c
+#define OMAP_TAP_DIE_ID_44XX_3  0x0210
+
 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
 
 struct omap_id {
@@ -106,6 +112,14 @@ static u16 tap_prod_id;
 
 void omap_get_die_id(struct omap_die_id *odi)
 {
+        if (cpu_is_omap44xx()) {
+                odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
+                odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
+                odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
+                odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
+
+                return;
+        }
         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
@@ -190,12 +204,19 @@ static void __init omap3_check_features(void)
         if (!cpu_is_omap3505() && !cpu_is_omap3517())
                 omap3_features |= OMAP3_HAS_IO_WAKEUP;
 
+        omap3_features |= OMAP3_HAS_SDRC;
+
         /*
          * TODO: Get additional info (where applicable)
          *       e.g. Size of L2 cache.
          */
 }
 
+static void __init ti816x_check_features(void)
+{
+        omap3_features = OMAP3_HAS_NEON;
+}
+
 static void __init omap3_check_revision(void)
 {
         u32 cpuid, idcode;
@@ -286,6 +307,20 @@ static void __init omap3_check_revision(void)
                         omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
                 }
                 break;
+        case 0xb81e:
+                omap_chip.oc = CHIP_IS_TI816X;
+
+                switch (rev) {
+                case 0:
+                        omap_revision = TI8168_REV_ES1_0;
+                        break;
+                case 1:
+                        omap_revision = TI8168_REV_ES1_1;
+                        break;
+                default:
+                        omap_revision =  TI8168_REV_ES1_1;
+                }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default*/
                 omap_revision =  OMAP3630_REV_ES1_2;
@@ -298,7 +333,6 @@ static void __init omap4_check_revision(void)
         u32 idcode;
         u16 hawkeye;
         u8 rev;
-        char *rev_name = "ES1.0";
 
         /*
          * The IC rev detection is done with hawkeye and rev.
@@ -307,16 +341,50 @@ static void __init omap4_check_revision(void)
          */
         idcode = read_tap_reg(OMAP_TAP_IDCODE);
         hawkeye = (idcode >> 12) & 0xffff;
-        rev = (idcode >> 28) & 0xff;
+        rev = (idcode >> 28) & 0xf;
 
-        if ((hawkeye == 0xb852) && (rev == 0x0)) {
-                omap_revision = OMAP4430_REV_ES1_0;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES1;
-                pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
-                return;
+        /*
+         * Few initial ES2.0 samples IDCODE is same as ES1.0
+         * Use ARM register to detect the correct ES version
+         */
+        if (!rev) {
+                idcode = read_cpuid(CPUID_ID);
+                rev = (idcode & 0xf) - 1;
+        }
+
+        switch (hawkeye) {
+        case 0xb852:
+                switch (rev) {
+                case 0:
+                        omap_revision = OMAP4430_REV_ES1_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES1;
+                        break;
+                case 1:
+                default:
+                        omap_revision = OMAP4430_REV_ES2_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                }
+                break;
+        case 0xb95c:
+                switch (rev) {
+                case 3:
+                        omap_revision = OMAP4430_REV_ES2_1;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
+                        break;
+                case 4:
+                default:
+                        omap_revision = OMAP4430_REV_ES2_2;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
+                }
+                break;
+        default:
+                /* Unknown default to latest silicon rev as default */
+                omap_revision = OMAP4430_REV_ES2_2;
+                omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
         }
 
-        pr_err("Unknown OMAP4 CPU id\n");
+        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
+                ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
 #define OMAP3_SHOW_FEATURE(feat)                \
@@ -347,6 +415,8 @@ static void __init omap3_cpuinfo(void)
                         /* Already set in omap3_check_revision() */
                         strcpy(cpu_name, "AM3505");
                 }
+        } else if (cpu_is_ti816x()) {
+                strcpy(cpu_name, "TI816X");
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                 strcpy(cpu_name, "OMAP3430/3530");
@@ -361,30 +431,54 @@ static void __init omap3_cpuinfo(void)
                 strcpy(cpu_name, "OMAP3503");
         }
 
-        switch (rev) {
-        case OMAP_REVBITS_00:
-                strcpy(cpu_rev, "1.0");
-                break;
-        case OMAP_REVBITS_01:
-                strcpy(cpu_rev, "1.1");
-                break;
-        case OMAP_REVBITS_02:
-                strcpy(cpu_rev, "1.2");
-                break;
-        case OMAP_REVBITS_10:
-                strcpy(cpu_rev, "2.0");
-                break;
-        case OMAP_REVBITS_20:
-                strcpy(cpu_rev, "2.1");
-                break;
-        case OMAP_REVBITS_30:
-                strcpy(cpu_rev, "3.0");
-                break;
-        case OMAP_REVBITS_40:
-        /* FALLTHROUGH */
-        default:
-                /* Use the latest known revision as default */
-                strcpy(cpu_rev, "3.1");
+        if (cpu_is_omap3630() || cpu_is_ti816x()) {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        strcpy(cpu_rev, "1.1");
+                        break;
+                case OMAP_REVBITS_02:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "1.2");
+                }
+        } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "1.1");
+                }
+        } else {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        strcpy(cpu_rev, "2.0");
+                        break;
+                case OMAP_REVBITS_02:
+                        strcpy(cpu_rev, "2.1");
+                        break;
+                case OMAP_REVBITS_03:
+                        strcpy(cpu_rev, "3.0");
+                        break;
+                case OMAP_REVBITS_04:
+                        strcpy(cpu_rev, "3.1");
+                        break;
+                case OMAP_REVBITS_05:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "3.1.2");
+                }
         }
 
         /* Print verbose information */
@@ -413,7 +507,13 @@ void __init omap2_check_revision(void)
                 omap24xx_check_revision();
         } else if (cpu_is_omap34xx()) {
                 omap3_check_revision();
-                omap3_check_features();
+
+                /* TI816X doesn't have feature register */
+                if (!cpu_is_ti816x())
+                        omap3_check_features();
+                else
+                        ti816x_check_features();
+
                 omap3_cpuinfo();
                 return;
         } else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h
new file mode 100644
index 000000000000..b76f49e7eed5
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-rx51.h
@@ -0,0 +1,11 @@
+/*
+ * Defines for rx51 boards
+ */
+
+#ifndef _OMAP_BOARD_RX51_H
+#define _OMAP_BOARD_RX51_H
+
+extern void __init rx51_peripherals_init(void);
+extern void __init rx51_video_mem_init(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 3af69d2c3dcd..775fdc3b000b 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,11 +1,12 @@
 /*
  * Defines for zoom boards
  */
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
+#include <video/omapdss.h>
 
 #define ZOOM_NAND_CS    0
 
-extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs);
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
+extern void __init zoom_display_init(void);
+
+#define ZOOM2_HEADSET_EXTMUTE_GPIO      153
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
new file mode 100644
index 000000000000..2f7ac70a20d8
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -0,0 +1,391 @@
+/*
+ * OMAP44xx CTRL_MODULE_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_CORE                                  0x4a002000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_CORE_IP_REVISION                      0x0000
+#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO                        0x0004
+#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG                     0x0010
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0                0x0200
+#define OMAP4_CTRL_MODULE_CORE_ID_CODE                          0x0204
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1                0x0208
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2                0x020c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3                0x0210
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0               0x0214
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1               0x0218
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF                0x021c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP            0x0228
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP                0x0260
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0              0x0264
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
+#define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
+#define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL         0x0324
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL        0x0328
+#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR                      0x032c
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0                0x0330
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1                0x0334
+#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL                 0x033c
+#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL                      0x0340
+#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL                    0x0350
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL             0x0400
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU                   0x0408
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0               0x042c
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1               0x0430
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2               0x0434
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3               0x0438
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0                    0x0440
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1                    0x0444
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2                    0x0448
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL           0x044c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL             0x0450
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL          0x0454
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0             0x0480
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1             0x0484
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2             0x0488
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3             0x048c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4             0x0490
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5             0x0494
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6             0x0498
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7             0x049c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8             0x04a0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9             0x04a4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10            0x04a8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11            0x04ac
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12            0x04b0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13            0x04b4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14            0x04b8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15            0x04bc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16            0x04c0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17            0x04c4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18            0x04c8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19            0x04cc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20            0x04d0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21            0x04d4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22            0x04d8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23            0x04dc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24            0x04e0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25            0x04e4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26            0x04e8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27            0x04ec
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28            0x04f0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29            0x04f4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30            0x04f8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31            0x04fc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                       30
+#define OMAP4_IP_REV_SCHEME_MASK                        (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                         16
+#define OMAP4_IP_REV_FUNC_MASK                          (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                          11
+#define OMAP4_IP_REV_RTL_MASK                           (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                        8
+#define OMAP4_IP_REV_MAJOR_MASK                         (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                       6
+#define OMAP4_IP_REV_CUSTOM_MASK                        (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                        0
+#define OMAP4_IP_REV_MINOR_MASK                         (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                           0
+#define OMAP4_IP_HWINFO_MASK                            (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT               2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                (0x3 << 2)
+
+/* STD_FUSE_DIE_ID_0 */
+#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_0_MASK                    (0xffffffff << 0)
+
+/* ID_CODE */
+#define OMAP4_STD_FUSE_IDCODE_SHIFT                     0
+#define OMAP4_STD_FUSE_IDCODE_MASK                      (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_1 */
+#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_1_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_2 */
+#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_2_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_3 */
+#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_3_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_0 */
+#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_0_MASK                   (0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_1 */
+#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_1_MASK                   (0xffffffff << 0)
+
+/* STD_FUSE_USB_CONF */
+#define OMAP4_USB_PROD_ID_SHIFT                         16
+#define OMAP4_USB_PROD_ID_MASK                          (0xffff << 16)
+#define OMAP4_USB_VENDOR_ID_SHIFT                       0
+#define OMAP4_USB_VENDOR_ID_MASK                        (0xffff << 0)
+
+/* STD_FUSE_OPP_VDD_WKUP */
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT               0
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK                (0xffffffff << 0)
+
+/* STD_FUSE_OPP_BGAP */
+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT                   0
+#define OMAP4_STD_FUSE_OPP_BGAP_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_0 */
+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK                  (0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_1 */
+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK                  (0xffffffff << 0)
+
+/* STATUS */
+#define OMAP4_ATTILA_CONF_SHIFT                         11
+#define OMAP4_ATTILA_CONF_MASK                          (0x3 << 11)
+#define OMAP4_DEVICE_TYPE_SHIFT                         8
+#define OMAP4_DEVICE_TYPE_MASK                          (0x7 << 8)
+#define OMAP4_SYS_BOOT_SHIFT                            0
+#define OMAP4_SYS_BOOT_MASK                             (0xff << 0)
+
+/* DEV_CONF */
+#define OMAP4_DEV_CONF_SHIFT                            1
+#define OMAP4_DEV_CONF_MASK                             (0x7fffffff << 1)
+#define OMAP4_USBPHY_PD_SHIFT                           0
+#define OMAP4_USBPHY_PD_MASK                            (1 << 0)
+
+/* LDOVBB_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK               (0x1f << 0)
+
+/* LDOVBB_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK               (0x1f << 0)
+
+/* LDOSRAM_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+
+/* LDOSRAM_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+
+/* LDOSRAM_CORE_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT        26
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK         (1 << 26)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT         21
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK          (0x1f << 21)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT        16
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK         (0x1f << 16)
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT        10
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK         (1 << 10)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT         5
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK          (0x1f << 5)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT        0
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK         (0x1f << 0)
+
+/* TEMP_SENSOR */
+#define OMAP4_BGAP_TEMPSOFF_SHIFT                       12
+#define OMAP4_BGAP_TEMPSOFF_MASK                        (1 << 12)
+#define OMAP4_BGAP_TSHUT_SHIFT                          11
+#define OMAP4_BGAP_TSHUT_MASK                           (1 << 11)
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT           10
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK            (1 << 10)
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT                9
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK                 (1 << 9)
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT               8
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK                (1 << 8)
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT              0
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK               (0xff << 0)
+
+/* DPLL_NWELL_TRIM_0 */
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT        29
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK         (1 << 29)
+#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT                 24
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK                  (0x1f << 24)
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_PER_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT        11
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK         (1 << 11)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT                 6
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK                  (0x1f << 6)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT        5
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK         (1 << 5)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT                 0
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK                  (0x1f << 0)
+
+/* DPLL_NWELL_TRIM_1 */
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT     29
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK      (1 << 29)
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT              24
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK               (0x1f << 24)
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_USB_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT       11
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK        (1 << 11)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT                6
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK                 (0x1f << 6)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT       5
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK        (1 << 5)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT                0
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK                 (0x1f << 0)
+
+/* USBOTGHS_CONTROL */
+#define OMAP4_DISCHRGVBUS_SHIFT                         8
+#define OMAP4_DISCHRGVBUS_MASK                          (1 << 8)
+#define OMAP4_CHRGVBUS_SHIFT                            7
+#define OMAP4_CHRGVBUS_MASK                             (1 << 7)
+#define OMAP4_DRVVBUS_SHIFT                             6
+#define OMAP4_DRVVBUS_MASK                              (1 << 6)
+#define OMAP4_IDPULLUP_SHIFT                            5
+#define OMAP4_IDPULLUP_MASK                             (1 << 5)
+#define OMAP4_IDDIG_SHIFT                               4
+#define OMAP4_IDDIG_MASK                                (1 << 4)
+#define OMAP4_SESSEND_SHIFT                             3
+#define OMAP4_SESSEND_MASK                              (1 << 3)
+#define OMAP4_VBUSVALID_SHIFT                           2
+#define OMAP4_VBUSVALID_MASK                            (1 << 2)
+#define OMAP4_BVALID_SHIFT                              1
+#define OMAP4_BVALID_MASK                               (1 << 1)
+#define OMAP4_AVALID_SHIFT                              0
+#define OMAP4_AVALID_MASK                               (1 << 0)
+
+/* DSS_CONTROL */
+#define OMAP4_DSS_MUX6_SELECT_SHIFT                     0
+#define OMAP4_DSS_MUX6_SELECT_MASK                      (1 << 0)
+
+/* HWOBS_CONTROL */
+#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT                    3
+#define OMAP4_HWOBS_CLKDIV_SEL_MASK                     (0x1f << 3)
+#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT                 2
+#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK                  (1 << 2)
+#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT                  1
+#define OMAP4_HWOBS_ALL_ONE_MODE_MASK                   (1 << 1)
+#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT                  0
+#define OMAP4_HWOBS_MACRO_ENABLE_MASK                   (1 << 0)
+
+/* DEBOBS_FINAL_MUX_SEL */
+#define OMAP4_SELECT_SHIFT                              0
+#define OMAP4_SELECT_MASK                               (0xffffffff << 0)
+
+/* DEBOBS_MMR_MPU */
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT               0
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK                (0xf << 0)
+
+/* CONF_SDMA_REQ_SEL0 */
+#define OMAP4_MULT_SHIFT                                0
+#define OMAP4_MULT_MASK                                 (0x7f << 0)
+
+/* CONF_CLK_SEL0 */
+#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL0_MASK                   (0x7 << 0)
+
+/* CONF_CLK_SEL1 */
+#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL1_MASK                   (0x7 << 0)
+
+/* CONF_CLK_SEL2 */
+#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL2_MASK                   (0x7 << 0)
+
+/* CONF_DPLL_FREQLOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT         0
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK          (0x7 << 0)
+
+/* CONF_DPLL_TINITZ_SEL */
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT           0
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK            (0x7 << 0)
+
+/* CONF_DPLL_PHASELOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT        0
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK         (0x7 << 0)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_MODE_SHIFT                                0
+#define OMAP4_MODE_MASK                                 (0xf << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
new file mode 100644
index 000000000000..c88420de1151
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -0,0 +1,1409 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE                              0x4a100000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION                  0x0000
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO                    0x0004
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG                 0x0010
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0        0x01d8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1        0x01dc
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2        0x01e0
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3        0x01e4
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4        0x01e8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5        0x01ec
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6        0x01f0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE         0x05a4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0   0x05a8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1   0x05ac
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0   0x05b0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1   0x05b4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0   0x05b8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1   0x05bc
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2   0x05c0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC            0x05c4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS              0x05c8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE            0x0600
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0                0x0604
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX            0x0608
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC                0x060c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY          0x0610
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2                 0x0614
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY               0x0618
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP              0x061c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE          0x0620
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1                0x0624
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1                 0x0628
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI                  0x062c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB                  0x0630
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ                  0x0634
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0          0x0638
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1          0x063c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2          0x0640
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3          0x0644
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0          0x0648
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1          0x064c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2          0x0650
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3          0x0654
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD             0x0658
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C                  0x065c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW        0x0660
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R         0x0664
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0      0x0668
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1              0x0700
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2              0x0704
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3              0x0708
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4              0x070c
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT               31
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK                (1 << 31)
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT               30
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK                (1 << 30)
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT               16
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK                (1 << 16)
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT              11
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK               (1 << 11)
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT              10
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK               (1 << 10)
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT               9
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK                (1 << 9)
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT               8
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK                (1 << 8)
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT               6
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK                (1 << 6)
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT               5
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK                (1 << 5)
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT               4
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK                (1 << 4)
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT               3
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK                (1 << 3)
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT               0
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK                (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_1 */
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT            30
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK             (1 << 30)
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT              25
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK               (1 << 25)
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT              24
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK               (1 << 24)
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT              23
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK               (1 << 23)
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT              22
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK               (1 << 22)
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT              20
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK               (1 << 20)
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT           15
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK            (1 << 15)
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT               13
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK                (1 << 13)
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT               12
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK                (1 << 12)
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT             11
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK              (1 << 11)
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_2 */
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        31
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 31)
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT         30
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 30)
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT          29
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 29)
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT          28
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 28)
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        27
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 27)
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT            25
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK             (1 << 25)
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT            24
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK             (1 << 24)
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT            23
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK             (1 << 23)
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            22
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 22)
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            21
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 21)
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            20
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 20)
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            19
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 19)
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT             18
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 18)
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             17
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 17)
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT         16
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK          (1 << 16)
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT         15
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK          (1 << 15)
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      14
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        13
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 13)
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     12
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 12)
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     11
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 11)
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     10
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     9
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     8
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     7
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     6
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     5
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      4
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      3
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      2
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      1
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT        0
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK         (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_3 */
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT             29
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK              (1 << 29)
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT             28
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 28)
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            27
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 27)
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             25
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 25)
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT                16
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK                 (1 << 16)
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT         6
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK          (1 << 6)
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT          5
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK           (1 << 5)
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        4
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 4)
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        3
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 3)
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT         2
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 2)
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT          1
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 1)
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_4 */
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      29
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        28
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 28)
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     27
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 27)
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     26
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 26)
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     25
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 25)
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     24
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 24)
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     23
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 23)
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     22
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 22)
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     21
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 21)
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     20
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 20)
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      19
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      18
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      17
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      16
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT             13
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 13)
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            12
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 12)
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            11
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 11)
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            9
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 9)
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            8
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 8)
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            7
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 7)
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            6
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 6)
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT          2
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK           (1 << 2)
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT           1
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK            (1 << 1)
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT         0
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK          (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_5 */
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT              31
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK               (1 << 31)
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT              30
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK               (1 << 30)
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT               29
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK                (1 << 29)
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT               28
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK                (1 << 28)
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT               27
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK                (1 << 27)
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT               26
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK                (1 << 26)
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT             3
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 3)
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT             2
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 2)
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT             1
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 1)
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT             0
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_6 */
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT              7
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK               (1 << 7)
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT              6
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK               (1 << 6)
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT              5
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK               (1 << 5)
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT              3
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK               (1 << 3)
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT              1
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK               (1 << 1)
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT              0
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK               (1 << 0)
+
+/* CONTROL_PADCONF_GLOBAL */
+#define OMAP4_FORCE_OFFMODE_EN_SHIFT                            31
+#define OMAP4_FORCE_OFFMODE_EN_MASK                             (1 << 31)
+
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_BANK0_SHIFT                               31
+#define OMAP4_VDDS_DV_BANK0_MASK                                (1 << 31)
+#define OMAP4_VDDS_DV_BANK1_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK1_MASK                                (1 << 30)
+#define OMAP4_VDDS_DV_BANK3_SHIFT                               29
+#define OMAP4_VDDS_DV_BANK3_MASK                                (1 << 29)
+#define OMAP4_VDDS_DV_BANK4_SHIFT                               28
+#define OMAP4_VDDS_DV_BANK4_MASK                                (1 << 28)
+#define OMAP4_VDDS_DV_BANK5_SHIFT                               27
+#define OMAP4_VDDS_DV_BANK5_MASK                                (1 << 27)
+#define OMAP4_VDDS_DV_BANK6_SHIFT                               26
+#define OMAP4_VDDS_DV_BANK6_MASK                                (1 << 26)
+#define OMAP4_VDDS_DV_C2C_SHIFT                                 25
+#define OMAP4_VDDS_DV_C2C_MASK                                  (1 << 25)
+#define OMAP4_VDDS_DV_CAM_SHIFT                                 24
+#define OMAP4_VDDS_DV_CAM_MASK                                  (1 << 24)
+#define OMAP4_VDDS_DV_GPMC_SHIFT                                23
+#define OMAP4_VDDS_DV_GPMC_MASK                                 (1 << 23)
+#define OMAP4_VDDS_DV_SDMMC2_SHIFT                              22
+#define OMAP4_VDDS_DV_SDMMC2_MASK                               (1 << 22)
+
+/* CONTROL_SMART1IO_PADCONF_0 */
+#define OMAP4_ABE_DR0_SC_SHIFT                                  30
+#define OMAP4_ABE_DR0_SC_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_SC_SHIFT                                  28
+#define OMAP4_CAM_DR0_SC_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_SC_SHIFT                                 26
+#define OMAP4_FREF_DR2_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_SC_SHIFT                                 24
+#define OMAP4_FREF_DR3_SC_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_SC_SHIFT                                 22
+#define OMAP4_GPIO_DR8_SC_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_SC_SHIFT                                 20
+#define OMAP4_GPIO_DR9_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_SC_SHIFT                                 18
+#define OMAP4_GPMC_DR2_SC_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_SC_SHIFT                                 16
+#define OMAP4_GPMC_DR3_SC_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_SC_SHIFT                                 14
+#define OMAP4_GPMC_DR6_SC_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_SC_SHIFT                                 12
+#define OMAP4_HDMI_DR0_SC_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_SC_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_SC_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_SC_SHIFT                                8
+#define OMAP4_UART1_DR0_SC_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_SC_SHIFT                                6
+#define OMAP4_UART3_DR0_SC_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_SC_SHIFT                                4
+#define OMAP4_UART3_DR1_SC_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_SC_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_SC_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_SC_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_SC_MASK                                (0x3 << 0)
+
+/* CONTROL_SMART1IO_PADCONF_1 */
+#define OMAP4_ABE_DR0_LB_SHIFT                                  30
+#define OMAP4_ABE_DR0_LB_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_LB_SHIFT                                  28
+#define OMAP4_CAM_DR0_LB_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_LB_SHIFT                                 26
+#define OMAP4_FREF_DR2_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_LB_SHIFT                                 24
+#define OMAP4_FREF_DR3_LB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_LB_SHIFT                                 22
+#define OMAP4_GPIO_DR8_LB_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_LB_SHIFT                                 20
+#define OMAP4_GPIO_DR9_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_LB_SHIFT                                 18
+#define OMAP4_GPMC_DR2_LB_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_LB_SHIFT                                 16
+#define OMAP4_GPMC_DR3_LB_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_LB_SHIFT                                 14
+#define OMAP4_GPMC_DR6_LB_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_LB_SHIFT                                 12
+#define OMAP4_HDMI_DR0_LB_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_LB_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_LB_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_LB_SHIFT                                8
+#define OMAP4_UART1_DR0_LB_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_LB_SHIFT                                6
+#define OMAP4_UART3_DR0_LB_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_LB_SHIFT                                4
+#define OMAP4_UART3_DR1_LB_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_LB_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_LB_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_LB_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_LB_MASK                                (0x3 << 0)
+
+/* CONTROL_SMART2IO_PADCONF_0 */
+#define OMAP4_C2C_DR0_LB_SHIFT                                  31
+#define OMAP4_C2C_DR0_LB_MASK                                   (1 << 31)
+#define OMAP4_DPM_DR1_LB_SHIFT                                  30
+#define OMAP4_DPM_DR1_LB_MASK                                   (1 << 30)
+#define OMAP4_DPM_DR2_LB_SHIFT                                  29
+#define OMAP4_DPM_DR2_LB_MASK                                   (1 << 29)
+#define OMAP4_DPM_DR3_LB_SHIFT                                  28
+#define OMAP4_DPM_DR3_LB_MASK                                   (1 << 28)
+#define OMAP4_GPIO_DR0_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR0_LB_MASK                                  (1 << 27)
+#define OMAP4_GPIO_DR1_LB_SHIFT                                 26
+#define OMAP4_GPIO_DR1_LB_MASK                                  (1 << 26)
+#define OMAP4_GPIO_DR10_LB_SHIFT                                25
+#define OMAP4_GPIO_DR10_LB_MASK                                 (1 << 25)
+#define OMAP4_GPIO_DR2_LB_SHIFT                                 24
+#define OMAP4_GPIO_DR2_LB_MASK                                  (1 << 24)
+#define OMAP4_GPMC_DR0_LB_SHIFT                                 23
+#define OMAP4_GPMC_DR0_LB_MASK                                  (1 << 23)
+#define OMAP4_GPMC_DR1_LB_SHIFT                                 22
+#define OMAP4_GPMC_DR1_LB_MASK                                  (1 << 22)
+#define OMAP4_GPMC_DR4_LB_SHIFT                                 21
+#define OMAP4_GPMC_DR4_LB_MASK                                  (1 << 21)
+#define OMAP4_GPMC_DR5_LB_SHIFT                                 20
+#define OMAP4_GPMC_DR5_LB_MASK                                  (1 << 20)
+#define OMAP4_GPMC_DR7_LB_SHIFT                                 19
+#define OMAP4_GPMC_DR7_LB_MASK                                  (1 << 19)
+#define OMAP4_HSI2_DR0_LB_SHIFT                                 18
+#define OMAP4_HSI2_DR0_LB_MASK                                  (1 << 18)
+#define OMAP4_HSI2_DR1_LB_SHIFT                                 17
+#define OMAP4_HSI2_DR1_LB_MASK                                  (1 << 17)
+#define OMAP4_HSI2_DR2_LB_SHIFT                                 16
+#define OMAP4_HSI2_DR2_LB_MASK                                  (1 << 16)
+#define OMAP4_KPD_DR0_LB_SHIFT                                  15
+#define OMAP4_KPD_DR0_LB_MASK                                   (1 << 15)
+#define OMAP4_KPD_DR1_LB_SHIFT                                  14
+#define OMAP4_KPD_DR1_LB_MASK                                   (1 << 14)
+#define OMAP4_PDM_DR0_LB_SHIFT                                  13
+#define OMAP4_PDM_DR0_LB_MASK                                   (1 << 13)
+#define OMAP4_SDMMC2_DR0_LB_SHIFT                               12
+#define OMAP4_SDMMC2_DR0_LB_MASK                                (1 << 12)
+#define OMAP4_SDMMC3_DR0_LB_SHIFT                               11
+#define OMAP4_SDMMC3_DR0_LB_MASK                                (1 << 11)
+#define OMAP4_SDMMC4_DR0_LB_SHIFT                               10
+#define OMAP4_SDMMC4_DR0_LB_MASK                                (1 << 10)
+#define OMAP4_SDMMC4_DR1_LB_SHIFT                               9
+#define OMAP4_SDMMC4_DR1_LB_MASK                                (1 << 9)
+#define OMAP4_SPI3_DR0_LB_SHIFT                                 8
+#define OMAP4_SPI3_DR0_LB_MASK                                  (1 << 8)
+#define OMAP4_SPI3_DR1_LB_SHIFT                                 7
+#define OMAP4_SPI3_DR1_LB_MASK                                  (1 << 7)
+#define OMAP4_UART3_DR2_LB_SHIFT                                6
+#define OMAP4_UART3_DR2_LB_MASK                                 (1 << 6)
+#define OMAP4_UART3_DR3_LB_SHIFT                                5
+#define OMAP4_UART3_DR3_LB_MASK                                 (1 << 5)
+#define OMAP4_UART3_DR4_LB_SHIFT                                4
+#define OMAP4_UART3_DR4_LB_MASK                                 (1 << 4)
+#define OMAP4_UART3_DR5_LB_SHIFT                                3
+#define OMAP4_UART3_DR5_LB_MASK                                 (1 << 3)
+#define OMAP4_USBA0_DR1_LB_SHIFT                                2
+#define OMAP4_USBA0_DR1_LB_MASK                                 (1 << 2)
+#define OMAP4_USBA_DR2_LB_SHIFT                                 1
+#define OMAP4_USBA_DR2_LB_MASK                                  (1 << 1)
+
+/* CONTROL_SMART2IO_PADCONF_1 */
+#define OMAP4_USBB1_DR0_LB_SHIFT                                31
+#define OMAP4_USBB1_DR0_LB_MASK                                 (1 << 31)
+#define OMAP4_USBB2_DR0_LB_SHIFT                                30
+#define OMAP4_USBB2_DR0_LB_MASK                                 (1 << 30)
+#define OMAP4_USBA0_DR0_LB_SHIFT                                29
+#define OMAP4_USBA0_DR0_LB_MASK                                 (1 << 29)
+
+/* CONTROL_SMART3IO_PADCONF_0 */
+#define OMAP4_DMIC_DR0_MB_SHIFT                                 30
+#define OMAP4_DMIC_DR0_MB_MASK                                  (0x3 << 30)
+#define OMAP4_GPIO_DR3_MB_SHIFT                                 28
+#define OMAP4_GPIO_DR3_MB_MASK                                  (0x3 << 28)
+#define OMAP4_GPIO_DR4_MB_SHIFT                                 26
+#define OMAP4_GPIO_DR4_MB_MASK                                  (0x3 << 26)
+#define OMAP4_GPIO_DR5_MB_SHIFT                                 24
+#define OMAP4_GPIO_DR5_MB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR6_MB_SHIFT                                 22
+#define OMAP4_GPIO_DR6_MB_MASK                                  (0x3 << 22)
+#define OMAP4_HSI_DR1_MB_SHIFT                                  20
+#define OMAP4_HSI_DR1_MB_MASK                                   (0x3 << 20)
+#define OMAP4_HSI_DR2_MB_SHIFT                                  18
+#define OMAP4_HSI_DR2_MB_MASK                                   (0x3 << 18)
+#define OMAP4_HSI_DR3_MB_SHIFT                                  16
+#define OMAP4_HSI_DR3_MB_MASK                                   (0x3 << 16)
+#define OMAP4_MCBSP2_DR0_MB_SHIFT                               14
+#define OMAP4_MCBSP2_DR0_MB_MASK                                (0x3 << 14)
+#define OMAP4_MCSPI4_DR0_MB_SHIFT                               12
+#define OMAP4_MCSPI4_DR0_MB_MASK                                (0x3 << 12)
+#define OMAP4_MCSPI4_DR1_MB_SHIFT                               10
+#define OMAP4_MCSPI4_DR1_MB_MASK                                (0x3 << 10)
+#define OMAP4_SDMMC3_DR0_MB_SHIFT                               8
+#define OMAP4_SDMMC3_DR0_MB_MASK                                (0x3 << 8)
+#define OMAP4_SPI2_DR0_MB_SHIFT                                 0
+#define OMAP4_SPI2_DR0_MB_MASK                                  (0x3 << 0)
+
+/* CONTROL_SMART3IO_PADCONF_1 */
+#define OMAP4_SPI2_DR1_MB_SHIFT                                 30
+#define OMAP4_SPI2_DR1_MB_MASK                                  (0x3 << 30)
+#define OMAP4_SPI2_DR2_MB_SHIFT                                 28
+#define OMAP4_SPI2_DR2_MB_MASK                                  (0x3 << 28)
+#define OMAP4_UART2_DR0_MB_SHIFT                                26
+#define OMAP4_UART2_DR0_MB_MASK                                 (0x3 << 26)
+#define OMAP4_UART2_DR1_MB_SHIFT                                24
+#define OMAP4_UART2_DR1_MB_MASK                                 (0x3 << 24)
+#define OMAP4_UART4_DR0_MB_SHIFT                                22
+#define OMAP4_UART4_DR0_MB_MASK                                 (0x3 << 22)
+#define OMAP4_HSI_DR0_MB_SHIFT                                  20
+#define OMAP4_HSI_DR0_MB_MASK                                   (0x3 << 20)
+
+/* CONTROL_SMART3IO_PADCONF_2 */
+#define OMAP4_DMIC_DR0_LB_SHIFT                                 31
+#define OMAP4_DMIC_DR0_LB_MASK                                  (1 << 31)
+#define OMAP4_GPIO_DR3_LB_SHIFT                                 30
+#define OMAP4_GPIO_DR3_LB_MASK                                  (1 << 30)
+#define OMAP4_GPIO_DR4_LB_SHIFT                                 29
+#define OMAP4_GPIO_DR4_LB_MASK                                  (1 << 29)
+#define OMAP4_GPIO_DR5_LB_SHIFT                                 28
+#define OMAP4_GPIO_DR5_LB_MASK                                  (1 << 28)
+#define OMAP4_GPIO_DR6_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR6_LB_MASK                                  (1 << 27)
+#define OMAP4_HSI_DR1_LB_SHIFT                                  26
+#define OMAP4_HSI_DR1_LB_MASK                                   (1 << 26)
+#define OMAP4_HSI_DR2_LB_SHIFT                                  25
+#define OMAP4_HSI_DR2_LB_MASK                                   (1 << 25)
+#define OMAP4_HSI_DR3_LB_SHIFT                                  24
+#define OMAP4_HSI_DR3_LB_MASK                                   (1 << 24)
+#define OMAP4_MCBSP2_DR0_LB_SHIFT                               23
+#define OMAP4_MCBSP2_DR0_LB_MASK                                (1 << 23)
+#define OMAP4_MCSPI4_DR0_LB_SHIFT                               22
+#define OMAP4_MCSPI4_DR0_LB_MASK                                (1 << 22)
+#define OMAP4_MCSPI4_DR1_LB_SHIFT                               21
+#define OMAP4_MCSPI4_DR1_LB_MASK                                (1 << 21)
+#define OMAP4_SLIMBUS2_DR0_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR0_LB_MASK                              (1 << 18)
+#define OMAP4_SPI2_DR0_LB_SHIFT                                 16
+#define OMAP4_SPI2_DR0_LB_MASK                                  (1 << 16)
+#define OMAP4_SPI2_DR1_LB_SHIFT                                 15
+#define OMAP4_SPI2_DR1_LB_MASK                                  (1 << 15)
+#define OMAP4_SPI2_DR2_LB_SHIFT                                 14
+#define OMAP4_SPI2_DR2_LB_MASK                                  (1 << 14)
+#define OMAP4_UART2_DR0_LB_SHIFT                                13
+#define OMAP4_UART2_DR0_LB_MASK                                 (1 << 13)
+#define OMAP4_UART2_DR1_LB_SHIFT                                12
+#define OMAP4_UART2_DR1_LB_MASK                                 (1 << 12)
+#define OMAP4_UART4_DR0_LB_SHIFT                                11
+#define OMAP4_UART4_DR0_LB_MASK                                 (1 << 11)
+#define OMAP4_HSI_DR0_LB_SHIFT                                  10
+#define OMAP4_HSI_DR0_LB_MASK                                   (1 << 10)
+
+/* CONTROL_USBB_HSIC */
+#define OMAP4_USBB2_DR1_SR_SHIFT                                30
+#define OMAP4_USBB2_DR1_SR_MASK                                 (0x3 << 30)
+#define OMAP4_USBB2_DR1_I_SHIFT                                 27
+#define OMAP4_USBB2_DR1_I_MASK                                  (0x7 << 27)
+#define OMAP4_USBB1_DR1_SR_SHIFT                                25
+#define OMAP4_USBB1_DR1_SR_MASK                                 (0x3 << 25)
+#define OMAP4_USBB1_DR1_I_SHIFT                                 22
+#define OMAP4_USBB1_DR1_I_MASK                                  (0x7 << 22)
+#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT                          20
+#define OMAP4_USBB1_HSIC_DATA_WD_MASK                           (0x3 << 20)
+#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT                        18
+#define OMAP4_USBB1_HSIC_STROBE_WD_MASK                         (0x3 << 18)
+#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT                          16
+#define OMAP4_USBB2_HSIC_DATA_WD_MASK                           (0x3 << 16)
+#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT                        14
+#define OMAP4_USBB2_HSIC_STROBE_WD_MASK                         (0x3 << 14)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           13
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 13)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT                  11
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 11)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         10
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 10)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT                8
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 8)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           7
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 7)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT                  5
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 5)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         4
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 4)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT                2
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 2)
+
+/* CONTROL_SLIMBUS */
+#define OMAP4_SLIMBUS1_DR0_MB_SHIFT                             30
+#define OMAP4_SLIMBUS1_DR0_MB_MASK                              (0x3 << 30)
+#define OMAP4_SLIMBUS1_DR1_MB_SHIFT                             28
+#define OMAP4_SLIMBUS1_DR1_MB_MASK                              (0x3 << 28)
+#define OMAP4_SLIMBUS2_DR0_MB_SHIFT                             26
+#define OMAP4_SLIMBUS2_DR0_MB_MASK                              (0x3 << 26)
+#define OMAP4_SLIMBUS2_DR1_MB_SHIFT                             24
+#define OMAP4_SLIMBUS2_DR1_MB_MASK                              (0x3 << 24)
+#define OMAP4_SLIMBUS2_DR2_MB_SHIFT                             22
+#define OMAP4_SLIMBUS2_DR2_MB_MASK                              (0x3 << 22)
+#define OMAP4_SLIMBUS2_DR3_MB_SHIFT                             20
+#define OMAP4_SLIMBUS2_DR3_MB_MASK                              (0x3 << 20)
+#define OMAP4_SLIMBUS1_DR0_LB_SHIFT                             19
+#define OMAP4_SLIMBUS1_DR0_LB_MASK                              (1 << 19)
+#define OMAP4_SLIMBUS2_DR1_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR1_LB_MASK                              (1 << 18)
+
+/* CONTROL_PBIASLITE */
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT                     31
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK                      (1 << 31)
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT                30
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 30)
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT                  29
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK                   (1 << 29)
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT                       28
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK                        (1 << 28)
+#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT                        27
+#define OMAP4_USIM_PBIASLITE_VMODE_MASK                         (1 << 27)
+#define OMAP4_MMC1_PWRDNZ_SHIFT                                 26
+#define OMAP4_MMC1_PWRDNZ_MASK                                  (1 << 26)
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT                     25
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK                      (1 << 25)
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT                24
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 24)
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT                  23
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK                   (1 << 23)
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT                       22
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK                        (1 << 22)
+#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT                        21
+#define OMAP4_MMC1_PBIASLITE_VMODE_MASK                         (1 << 21)
+#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT                          20
+#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK                           (1 << 20)
+
+/* CONTROL_I2C_0 */
+#define OMAP4_I2C4_SDA_GLFENB_SHIFT                             31
+#define OMAP4_I2C4_SDA_GLFENB_MASK                              (1 << 31)
+#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT                          29
+#define OMAP4_I2C4_SDA_LOAD_BITS_MASK                           (0x3 << 29)
+#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT                         28
+#define OMAP4_I2C4_SDA_PULLUPRESX_MASK                          (1 << 28)
+#define OMAP4_I2C3_SDA_GLFENB_SHIFT                             27
+#define OMAP4_I2C3_SDA_GLFENB_MASK                              (1 << 27)
+#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT                          25
+#define OMAP4_I2C3_SDA_LOAD_BITS_MASK                           (0x3 << 25)
+#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT                         24
+#define OMAP4_I2C3_SDA_PULLUPRESX_MASK                          (1 << 24)
+#define OMAP4_I2C2_SDA_GLFENB_SHIFT                             23
+#define OMAP4_I2C2_SDA_GLFENB_MASK                              (1 << 23)
+#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT                          21
+#define OMAP4_I2C2_SDA_LOAD_BITS_MASK                           (0x3 << 21)
+#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT                         20
+#define OMAP4_I2C2_SDA_PULLUPRESX_MASK                          (1 << 20)
+#define OMAP4_I2C1_SDA_GLFENB_SHIFT                             19
+#define OMAP4_I2C1_SDA_GLFENB_MASK                              (1 << 19)
+#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT                          17
+#define OMAP4_I2C1_SDA_LOAD_BITS_MASK                           (0x3 << 17)
+#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT                         16
+#define OMAP4_I2C1_SDA_PULLUPRESX_MASK                          (1 << 16)
+#define OMAP4_I2C4_SCL_GLFENB_SHIFT                             15
+#define OMAP4_I2C4_SCL_GLFENB_MASK                              (1 << 15)
+#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT                          13
+#define OMAP4_I2C4_SCL_LOAD_BITS_MASK                           (0x3 << 13)
+#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT                         12
+#define OMAP4_I2C4_SCL_PULLUPRESX_MASK                          (1 << 12)
+#define OMAP4_I2C3_SCL_GLFENB_SHIFT                             11
+#define OMAP4_I2C3_SCL_GLFENB_MASK                              (1 << 11)
+#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT                          9
+#define OMAP4_I2C3_SCL_LOAD_BITS_MASK                           (0x3 << 9)
+#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT                         8
+#define OMAP4_I2C3_SCL_PULLUPRESX_MASK                          (1 << 8)
+#define OMAP4_I2C2_SCL_GLFENB_SHIFT                             7
+#define OMAP4_I2C2_SCL_GLFENB_MASK                              (1 << 7)
+#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT                          5
+#define OMAP4_I2C2_SCL_LOAD_BITS_MASK                           (0x3 << 5)
+#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT                         4
+#define OMAP4_I2C2_SCL_PULLUPRESX_MASK                          (1 << 4)
+#define OMAP4_I2C1_SCL_GLFENB_SHIFT                             3
+#define OMAP4_I2C1_SCL_GLFENB_MASK                              (1 << 3)
+#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT                          1
+#define OMAP4_I2C1_SCL_LOAD_BITS_MASK                           (0x3 << 1)
+#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT                         0
+#define OMAP4_I2C1_SCL_PULLUPRESX_MASK                          (1 << 0)
+
+/* CONTROL_CAMERA_RX */
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT                   31
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK                    (1 << 31)
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT                   29
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK                    (0x3 << 29)
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT                   24
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK                    (0x1f << 24)
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT                     22
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK                      (0x3 << 22)
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT                    21
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK                     (1 << 21)
+#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT                      19
+#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK                       (0x3 << 19)
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT                    18
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK                     (1 << 18)
+#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT                      16
+#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK                       (0x3 << 16)
+
+/* CONTROL_AVDAC */
+#define OMAP4_AVDAC_ACEN_SHIFT                                  31
+#define OMAP4_AVDAC_ACEN_MASK                                   (1 << 31)
+#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT                           30
+#define OMAP4_AVDAC_TVOUTBYPASS_MASK                            (1 << 30)
+#define OMAP4_AVDAC_INPUTINV_SHIFT                              29
+#define OMAP4_AVDAC_INPUTINV_MASK                               (1 << 29)
+#define OMAP4_AVDAC_CTL_SHIFT                                   13
+#define OMAP4_AVDAC_CTL_MASK                                    (0xffff << 13)
+#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT                            12
+#define OMAP4_AVDAC_CTL_WR_ACK_MASK                             (1 << 12)
+
+/* CONTROL_HDMI_TX_PHY */
+#define OMAP4_HDMITXPHY_PADORDER_SHIFT                          31
+#define OMAP4_HDMITXPHY_PADORDER_MASK                           (1 << 31)
+#define OMAP4_HDMITXPHY_TXVALID_SHIFT                           30
+#define OMAP4_HDMITXPHY_TXVALID_MASK                            (1 << 30)
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT                       29
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK                        (1 << 29)
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT                      28
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK                       (1 << 28)
+
+/* CONTROL_MMC2 */
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT                       31
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK                        (1 << 31)
+
+/* CONTROL_DSIPHY */
+#define OMAP4_DSI2_LANEENABLE_SHIFT                             29
+#define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
+#define OMAP4_DSI1_LANEENABLE_SHIFT                             24
+#define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
+
+/* CONTROL_MCBSPLP */
+#define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
+#define OMAP4_ALBCTRLRX_FSX_MASK                                (1 << 31)
+#define OMAP4_ALBCTRLRX_CLKX_SHIFT                              30
+#define OMAP4_ALBCTRLRX_CLKX_MASK                               (1 << 30)
+#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT                            29
+#define OMAP4_ABE_MCBSP1_DR_EN_MASK                             (1 << 29)
+
+/* CONTROL_USB2PHYCORE */
+#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT                       31
+#define OMAP4_USB2PHY_AUTORESUME_EN_MASK                        (1 << 31)
+#define OMAP4_USB2PHY_DISCHGDET_SHIFT                           30
+#define OMAP4_USB2PHY_DISCHGDET_MASK                            (1 << 30)
+#define OMAP4_USB2PHY_GPIOMODE_SHIFT                            29
+#define OMAP4_USB2PHY_GPIOMODE_MASK                             (1 << 29)
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT                     28
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK                      (1 << 28)
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT                    27
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK                     (1 << 27)
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT                    26
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK                     (1 << 26)
+#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT                         25
+#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK                          (1 << 25)
+#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT                        24
+#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK                         (1 << 24)
+#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT                      21
+#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK                       (0x7 << 21)
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT                     20
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK                      (1 << 20)
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT                     19
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK                      (1 << 19)
+#define OMAP4_USB2PHY_DATADET_SHIFT                             18
+#define OMAP4_USB2PHY_DATADET_MASK                              (1 << 18)
+#define OMAP4_USB2PHY_SINKONDP_SHIFT                            17
+#define OMAP4_USB2PHY_SINKONDP_MASK                             (1 << 17)
+#define OMAP4_USB2PHY_SRCONDM_SHIFT                             16
+#define OMAP4_USB2PHY_SRCONDM_MASK                              (1 << 16)
+#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT                       15
+#define OMAP4_USB2PHY_RESTARTCHGDET_MASK                        (1 << 15)
+#define OMAP4_USB2PHY_CHGDETDONE_SHIFT                          14
+#define OMAP4_USB2PHY_CHGDETDONE_MASK                           (1 << 14)
+#define OMAP4_USB2PHY_CHGDETECTED_SHIFT                         13
+#define OMAP4_USB2PHY_CHGDETECTED_MASK                          (1 << 13)
+#define OMAP4_USB2PHY_MCPCPUEN_SHIFT                            12
+#define OMAP4_USB2PHY_MCPCPUEN_MASK                             (1 << 12)
+#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT                          11
+#define OMAP4_USB2PHY_MCPCMODEEN_MASK                           (1 << 11)
+#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT                       10
+#define OMAP4_USB2PHY_RESETDONEMCLK_MASK                        (1 << 10)
+#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT                       9
+#define OMAP4_USB2PHY_UTMIRESETDONE_MASK                        (1 << 9)
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT                    8
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK                     (1 << 8)
+#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT                       7
+#define OMAP4_USB2PHY_DATAPOLARITYN_MASK                        (1 << 7)
+#define OMAP4_USBDPLL_FREQLOCK_SHIFT                            6
+#define OMAP4_USBDPLL_FREQLOCK_MASK                             (1 << 6)
+#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT                       5
+#define OMAP4_USB2PHY_RESETDONETCLK_MASK                        (1 << 5)
+
+/* CONTROL_I2C_1 */
+#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT                         31
+#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK                          (1 << 31)
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT                      29
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK                       (0x3 << 29)
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT                     28
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK                      (1 << 28)
+#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT                         27
+#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK                          (1 << 27)
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT                      25
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK                       (0x3 << 25)
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT                     24
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK                      (1 << 24)
+#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT                         23
+#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK                          (1 << 23)
+#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT                          22
+#define OMAP4_HDMI_DDC_SDA_NMODE_MASK                           (1 << 22)
+#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT                         21
+#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK                          (1 << 21)
+#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT                          20
+#define OMAP4_HDMI_DDC_SCL_NMODE_MASK                           (1 << 20)
+
+/* CONTROL_MMC1 */
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT                      31
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK                       (1 << 31)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT                      30
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK                       (1 << 30)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT                      29
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK                       (1 << 29)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT                      28
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK                       (1 << 28)
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT                        27
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK                         (1 << 27)
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT                        26
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK                         (1 << 26)
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT                        25
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK                         (1 << 25)
+#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT                         24
+#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK                          (1 << 24)
+#define OMAP4_USB_FD_CDEN_SHIFT                                 23
+#define OMAP4_USB_FD_CDEN_MASK                                  (1 << 23)
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT                        22
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK                         (1 << 22)
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT                        21
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK                         (1 << 21)
+
+/* CONTROL_HSI */
+#define OMAP4_HSI1_CALLOOP_SEL_SHIFT                            31
+#define OMAP4_HSI1_CALLOOP_SEL_MASK                             (1 << 31)
+#define OMAP4_HSI1_CALMUX_SEL_SHIFT                             30
+#define OMAP4_HSI1_CALMUX_SEL_MASK                              (1 << 30)
+#define OMAP4_HSI2_CALLOOP_SEL_SHIFT                            29
+#define OMAP4_HSI2_CALLOOP_SEL_MASK                             (1 << 29)
+#define OMAP4_HSI2_CALMUX_SEL_SHIFT                             28
+#define OMAP4_HSI2_CALMUX_SEL_MASK                              (1 << 28)
+
+/* CONTROL_USB */
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT           31
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK            (1 << 31)
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT           30
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK            (1 << 30)
+
+/* CONTROL_HDQ */
+#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT                              31
+#define OMAP4_HDQ_SIO_PWRDNZ_MASK                               (1 << 31)
+
+/* CONTROL_LPDDR2IO1_0 */
+#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR1_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO1_1 */
+#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR5_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO1_2 */
+#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO1_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO1_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO1_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO1_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO1_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO1_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR9_WD_MASK                             (0x3 << 9)
+
+/* CONTROL_LPDDR2IO1_3 */
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK                         (1 << 12)
+
+/* CONTROL_LPDDR2IO2_0 */
+#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR1_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO2_1 */
+#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR5_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO2_2 */
+#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO2_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO2_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO2_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO2_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO2_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO2_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR9_WD_MASK                             (0x3 << 9)
+
+/* CONTROL_LPDDR2IO2_3 */
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK                         (1 << 12)
+
+/* CONTROL_BUS_HOLD */
+#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT                            31
+#define OMAP4_ABE_DMIC_DIN3_EN_MASK                             (1 << 31)
+#define OMAP4_MCSPI1_CS3_EN_SHIFT                               30
+#define OMAP4_MCSPI1_CS3_EN_MASK                                (1 << 30)
+
+/* CONTROL_C2C */
+#define OMAP4_MIRROR_MODE_EN_SHIFT                              31
+#define OMAP4_MIRROR_MODE_EN_MASK                               (1 << 31)
+#define OMAP4_C2C_SPARE_SHIFT                                   24
+#define OMAP4_C2C_SPARE_MASK                                    (0x7f << 24)
+
+/* CORE_CONTROL_SPARE_RW */
+#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_CORE_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+
+/* CORE_CONTROL_SPARE_R */
+#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_CORE_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+
+/* CORE_CONTROL_SPARE_R_C0 */
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+
+/* CONTROL_EFUSE_1 */
+#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT                            24
+#define OMAP4_AVDAC_TRIM_BYTE3_MASK                             (0x7f << 24)
+#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT                            16
+#define OMAP4_AVDAC_TRIM_BYTE2_MASK                             (0xff << 16)
+#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT                            8
+#define OMAP4_AVDAC_TRIM_BYTE1_MASK                             (0xff << 8)
+#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT                            0
+#define OMAP4_AVDAC_TRIM_BYTE0_MASK                             (0xff << 0)
+
+/* CONTROL_EFUSE_2 */
+#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT                         31
+#define OMAP4_EFUSE_SMART2TEST_P0_MASK                          (1 << 31)
+#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT                         30
+#define OMAP4_EFUSE_SMART2TEST_P1_MASK                          (1 << 30)
+#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT                         29
+#define OMAP4_EFUSE_SMART2TEST_P2_MASK                          (1 << 29)
+#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT                         28
+#define OMAP4_EFUSE_SMART2TEST_P3_MASK                          (1 << 28)
+#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT                         27
+#define OMAP4_EFUSE_SMART2TEST_N0_MASK                          (1 << 27)
+#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT                         26
+#define OMAP4_EFUSE_SMART2TEST_N1_MASK                          (1 << 26)
+#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT                         25
+#define OMAP4_EFUSE_SMART2TEST_N2_MASK                          (1 << 25)
+#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT                         24
+#define OMAP4_EFUSE_SMART2TEST_N3_MASK                          (1 << 24)
+#define OMAP4_LPDDR2_PTV_N1_SHIFT                               23
+#define OMAP4_LPDDR2_PTV_N1_MASK                                (1 << 23)
+#define OMAP4_LPDDR2_PTV_N2_SHIFT                               22
+#define OMAP4_LPDDR2_PTV_N2_MASK                                (1 << 22)
+#define OMAP4_LPDDR2_PTV_N3_SHIFT                               21
+#define OMAP4_LPDDR2_PTV_N3_MASK                                (1 << 21)
+#define OMAP4_LPDDR2_PTV_N4_SHIFT                               20
+#define OMAP4_LPDDR2_PTV_N4_MASK                                (1 << 20)
+#define OMAP4_LPDDR2_PTV_N5_SHIFT                               19
+#define OMAP4_LPDDR2_PTV_N5_MASK                                (1 << 19)
+#define OMAP4_LPDDR2_PTV_P1_SHIFT                               18
+#define OMAP4_LPDDR2_PTV_P1_MASK                                (1 << 18)
+#define OMAP4_LPDDR2_PTV_P2_SHIFT                               17
+#define OMAP4_LPDDR2_PTV_P2_MASK                                (1 << 17)
+#define OMAP4_LPDDR2_PTV_P3_SHIFT                               16
+#define OMAP4_LPDDR2_PTV_P3_MASK                                (1 << 16)
+#define OMAP4_LPDDR2_PTV_P4_SHIFT                               15
+#define OMAP4_LPDDR2_PTV_P4_MASK                                (1 << 15)
+#define OMAP4_LPDDR2_PTV_P5_SHIFT                               14
+#define OMAP4_LPDDR2_PTV_P5_MASK                                (1 << 14)
+
+/* CONTROL_EFUSE_3 */
+#define OMAP4_STD_FUSE_SPARE_1_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_1_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_2_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_2_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_3_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_3_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_4_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_4_MASK                             (0xff << 0)
+
+/* CONTROL_EFUSE_4 */
+#define OMAP4_STD_FUSE_SPARE_5_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_5_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_6_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_6_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_7_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_7_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_8_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_8_MASK                             (0xff << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
new file mode 100644
index 000000000000..17c9b37042c0
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
@@ -0,0 +1,236 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP                                      0x4a31e000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION                          0x0000
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO                            0x0004
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG                         0x0010
+#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0                0x007c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1       0x05a4
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE                 0x05a8
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR              0x05ac
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO                       0x0600
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2                        0x0604
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG                         0x0608
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS                          0x060c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW                0x0614
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R                 0x0618
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0              0x061c
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT          22
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK           (1 << 22)
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT             19
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK              (1 << 19)
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT    16
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK     (1 << 16)
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT            15
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK             (1 << 15)
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT                13
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK                 (1 << 13)
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT          12
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 12)
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT         7
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK          (1 << 7)
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT                 6
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK                  (1 << 6)
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT                 5
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK                  (1 << 5)
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT            4
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK             (1 << 4)
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT                 3
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK                  (1 << 3)
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT                1
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK                 (1 << 1)
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT                 0
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK                  (1 << 0)
+
+/* CONTROL_SMART1NOPMIO_PADCONF_0 */
+#define OMAP4_FREF_DR0_SC_SHIFT                                 30
+#define OMAP4_FREF_DR0_SC_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_SC_SHIFT                                 28
+#define OMAP4_FREF_DR1_SC_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_SC_SHIFT                                 26
+#define OMAP4_FREF_DR4_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_SC_SHIFT                                 24
+#define OMAP4_FREF_DR5_SC_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_SC_SHIFT                                 22
+#define OMAP4_FREF_DR6_SC_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_SC_SHIFT                                 20
+#define OMAP4_FREF_DR7_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_SC_SHIFT                                 18
+#define OMAP4_GPIO_DR7_SC_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_SC_SHIFT                                  14
+#define OMAP4_DPM_DR0_SC_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_SC_SHIFT                                  12
+#define OMAP4_SIM_DR0_SC_MASK                                   (0x3 << 12)
+
+/* CONTROL_SMART1NOPMIO_PADCONF_1 */
+#define OMAP4_FREF_DR0_LB_SHIFT                                 30
+#define OMAP4_FREF_DR0_LB_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_LB_SHIFT                                 28
+#define OMAP4_FREF_DR1_LB_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_LB_SHIFT                                 26
+#define OMAP4_FREF_DR4_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_LB_SHIFT                                 24
+#define OMAP4_FREF_DR5_LB_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_LB_SHIFT                                 22
+#define OMAP4_FREF_DR6_LB_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_LB_SHIFT                                 20
+#define OMAP4_FREF_DR7_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_LB_SHIFT                                 18
+#define OMAP4_GPIO_DR7_LB_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_LB_SHIFT                                  14
+#define OMAP4_DPM_DR0_LB_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_LB_SHIFT                                  12
+#define OMAP4_SIM_DR0_LB_MASK                                   (0x3 << 12)
+
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_FREF_SHIFT                                31
+#define OMAP4_VDDS_DV_FREF_MASK                                 (1 << 31)
+#define OMAP4_VDDS_DV_BANK2_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK2_MASK                                (1 << 30)
+
+/* CONTROL_XTAL_OSCILLATOR */
+#define OMAP4_OSCILLATOR_BOOST_SHIFT                            31
+#define OMAP4_OSCILLATOR_BOOST_MASK                             (1 << 31)
+#define OMAP4_OSCILLATOR_OS_OUT_SHIFT                           30
+#define OMAP4_OSCILLATOR_OS_OUT_MASK                            (1 << 30)
+
+/* CONTROL_USIMIO */
+#define OMAP4_PAD_USIM_CLK_LOW_SHIFT                            31
+#define OMAP4_PAD_USIM_CLK_LOW_MASK                             (1 << 31)
+#define OMAP4_PAD_USIM_RST_LOW_SHIFT                            29
+#define OMAP4_PAD_USIM_RST_LOW_MASK                             (1 << 29)
+#define OMAP4_USIM_PWRDNZ_SHIFT                                 28
+#define OMAP4_USIM_PWRDNZ_MASK                                  (1 << 28)
+
+/* CONTROL_I2C_2 */
+#define OMAP4_SR_SDA_GLFENB_SHIFT                               31
+#define OMAP4_SR_SDA_GLFENB_MASK                                (1 << 31)
+#define OMAP4_SR_SDA_LOAD_BITS_SHIFT                            29
+#define OMAP4_SR_SDA_LOAD_BITS_MASK                             (0x3 << 29)
+#define OMAP4_SR_SDA_PULLUPRESX_SHIFT                           28
+#define OMAP4_SR_SDA_PULLUPRESX_MASK                            (1 << 28)
+#define OMAP4_SR_SCL_GLFENB_SHIFT                               27
+#define OMAP4_SR_SCL_GLFENB_MASK                                (1 << 27)
+#define OMAP4_SR_SCL_LOAD_BITS_SHIFT                            25
+#define OMAP4_SR_SCL_LOAD_BITS_MASK                             (0x3 << 25)
+#define OMAP4_SR_SCL_PULLUPRESX_SHIFT                           24
+#define OMAP4_SR_SCL_PULLUPRESX_MASK                            (1 << 24)
+
+/* CONTROL_JTAG */
+#define OMAP4_JTAG_NTRST_EN_SHIFT                               31
+#define OMAP4_JTAG_NTRST_EN_MASK                                (1 << 31)
+#define OMAP4_JTAG_TCK_EN_SHIFT                                 30
+#define OMAP4_JTAG_TCK_EN_MASK                                  (1 << 30)
+#define OMAP4_JTAG_RTCK_EN_SHIFT                                29
+#define OMAP4_JTAG_RTCK_EN_MASK                                 (1 << 29)
+#define OMAP4_JTAG_TDI_EN_SHIFT                                 28
+#define OMAP4_JTAG_TDI_EN_MASK                                  (1 << 28)
+#define OMAP4_JTAG_TDO_EN_SHIFT                                 27
+#define OMAP4_JTAG_TDO_EN_MASK                                  (1 << 27)
+
+/* CONTROL_SYS */
+#define OMAP4_SYS_NRESWARM_PIPU_SHIFT                           31
+#define OMAP4_SYS_NRESWARM_PIPU_MASK                            (1 << 31)
+
+/* WKUP_CONTROL_SPARE_RW */
+#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+
+/* WKUP_CONTROL_SPARE_R */
+#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_WKUP_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+
+/* WKUP_CONTROL_SPARE_R_C0 */
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
new file mode 100644
index 000000000000..a0af9baec3f7
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
@@ -0,0 +1,92 @@
+/*
+ * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_WKUP                          0x4a30c000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION              0x0000
+#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO                0x0004
+#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG             0x0010
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0     0x0460
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1     0x0464
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2     0x0468
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3     0x046c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4     0x0470
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5     0x0474
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6     0x0478
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7     0x047c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8     0x0480
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9     0x0484
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10    0x0488
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11    0x048c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12    0x0490
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13    0x0494
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14    0x0498
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15    0x049c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16    0x04a0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17    0x04a4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18    0x04a8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19    0x04ac
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20    0x04b0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21    0x04b4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22    0x04b8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23    0x04bc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24    0x04c0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25    0x04c4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26    0x04c8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27    0x04cc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28    0x04d0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29    0x04d4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30    0x04d8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31    0x04dc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT               30
+#define OMAP4_IP_REV_SCHEME_MASK                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                 16
+#define OMAP4_IP_REV_FUNC_MASK                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                  11
+#define OMAP4_IP_REV_RTL_MASK                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                8
+#define OMAP4_IP_REV_MAJOR_MASK                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT               6
+#define OMAP4_IP_REV_CUSTOM_MASK                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                0
+#define OMAP4_IP_REV_MINOR_MASK                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                   0
+#define OMAP4_IP_HWINFO_MASK                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK        (0x3 << 2)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_WKUP_MODE_SHIFT                   0
+#define OMAP4_WKUP_MODE_MASK                            (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 09331bbbda52..48adfe9fe4f3 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -19,6 +19,9 @@
 
 #define UART_OFFSET(addr)       ((addr) & 0x00ffffff)
 
+#define omap_uart_v2p(x)        ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
+#define omap_uart_p2v(x)        ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
+
                 .pushsection .data
 omap_uart_phys: .word   0
 omap_uart_virt: .word   0
@@ -31,95 +34,106 @@ omap_uart_lsr:	.word	0
                  * the desired UART phys and virt addresses temporarily into
                  * the omap_uart_phys and omap_uart_virt above.
                  */
-                .macro  addruart, rx, tmp
+                .macro  addruart, rp, rv
 
                 /* Use omap_uart_phys/virt if already configured */
-10:             mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =__virt_to_phys(omap_uart_phys)    @ physical base address
-                ldrne   \rx, =omap_uart_virt    @ virtual base address
-                ldr     \rx, [\rx, #0]
-                cmp     \rx, #0                 @ is port configured?
+10:             mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =omap_uart_v2p(omap_uart_phys)     @ MMU disabled
+                ldrne   \rp, =omap_uart_phys    @ MMU enabled
+                add     \rv, \rp, #4            @ omap_uart_virt
+                ldr     \rp, [\rp, #0]
+                ldr     \rv, [\rv, #0]
+                cmp     \rp, #0                 @ is port configured?
+                cmpne   \rv, #0
                 bne     99f                     @ already configured
 
                 /* Check the debug UART configuration set in uncompress.h */
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =OMAP_UART_INFO
-                ldrne   \rx, =__phys_to_virt(OMAP_UART_INFO)
-                ldr     \rx, [\rx, #0]
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =OMAP_UART_INFO    @ MMU not enabled
+                ldrne   \rp, =omap_uart_p2v(OMAP_UART_INFO)     @ MMU enabled
+                ldr     \rp, [\rp, #0]
 
                 /* Select the UART to use based on the UART1 scratchpad value */
-                cmp     \rx, #0                 @ no port configured?
+                cmp     \rp, #0                 @ no port configured?
                 beq     21f                     @ if none, try to use UART1
-                cmp     \rx, #OMAP2UART1        @ OMAP2/3/4UART1
+                cmp     \rp, #OMAP2UART1        @ OMAP2/3/4UART1
                 beq     21f                     @ configure OMAP2/3/4UART1
-                cmp     \rx, #OMAP2UART2        @ OMAP2/3/4UART2
+                cmp     \rp, #OMAP2UART2        @ OMAP2/3/4UART2
                 beq     22f                     @ configure OMAP2/3/4UART2
-                cmp     \rx, #OMAP2UART3        @ only on 24xx
+                cmp     \rp, #OMAP2UART3        @ only on 24xx
                 beq     23f                     @ configure OMAP2UART3
-                cmp     \rx, #OMAP3UART3        @ only on 34xx
+                cmp     \rp, #OMAP3UART3        @ only on 34xx
                 beq     33f                     @ configure OMAP3UART3
-                cmp     \rx, #OMAP4UART3        @ only on 44xx
+                cmp     \rp, #OMAP4UART3        @ only on 44xx
                 beq     43f                     @ configure OMAP4UART3
-                cmp     \rx, #OMAP3UART4        @ only on 36xx
+                cmp     \rp, #OMAP3UART4        @ only on 36xx
                 beq     34f                     @ configure OMAP3UART4
-                cmp     \rx, #OMAP4UART4        @ only on 44xx
+                cmp     \rp, #OMAP4UART4        @ only on 44xx
                 beq     44f                     @ configure OMAP4UART4
-                cmp     \rx, #ZOOM_UART         @ only on zoom2/3
+                cmp     \rp, #TI816XUART1       @ ti816x UART offsets different
+                beq     81f                     @ configure UART1
+                cmp     \rp, #TI816XUART2       @ ti816x UART offsets different
+                beq     82f                     @ configure UART2
+                cmp     \rp, #TI816XUART3       @ ti816x UART offsets different
+                beq     83f                     @ configure UART3
+                cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
 
                 /* Configure the UART offset from the phys/virt base */
-21:             mov     \rx, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
+21:             mov     \rp, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
+                b       98f
+22:             mov     \rp, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
+                b       98f
+23:             mov     \rp, #UART_OFFSET(OMAP2_UART3_BASE)
+                b       98f
+33:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+                add     \rp, \rp, #0x00fb0000
+                add     \rp, \rp, #0x00006000           @ OMAP3_UART3_BASE
                 b       98f
-22:             mov     \rx, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
+34:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+                add     \rp, \rp, #0x00fb0000
+                add     \rp, \rp, #0x00028000           @ OMAP3_UART4_BASE
                 b       98f
-23:             mov     \rx, #UART_OFFSET(OMAP2_UART3_BASE)
+43:             mov     \rp, #UART_OFFSET(OMAP4_UART3_BASE)
                 b       98f
-33:             mov     \rx, #UART_OFFSET(OMAP3_UART1_BASE)
-                add     \rx, \rx, #0x00fb0000
-                add     \rx, \rx, #0x00006000           @ OMAP3_UART3_BASE
+44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                 b       98f
-34:             mov     \rx, #UART_OFFSET(OMAP3_UART1_BASE)
-                add     \rx, \rx, #0x00fb0000
-                add     \rx, \rx, #0x00028000           @ OMAP3_UART4_BASE
+81:             mov     \rp, #UART_OFFSET(TI816X_UART1_BASE)
                 b       98f
-43:             mov     \rx, #UART_OFFSET(OMAP4_UART3_BASE)
+82:             mov     \rp, #UART_OFFSET(TI816X_UART2_BASE)
                 b       98f
-44:             mov     \rx, #UART_OFFSET(OMAP4_UART4_BASE)
+83:             mov     \rp, #UART_OFFSET(TI816X_UART3_BASE)
                 b       98f
-95:             ldr     \rx, =ZOOM_UART_BASE
-                mrc     p15, 0, \tmp, c1, c0
-                tst     \tmp, #1                @ MMU enabled?
-                ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
-                ldrne   \tmp, =omap_uart_phys
-                str     \rx, [\tmp, #0]
-                ldr     \rx, =ZOOM_UART_VIRT
-                ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
-                ldrne   \tmp, =omap_uart_virt
-                str     \rx, [\tmp, #0]
-                mov     \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
-                ldreq   \tmp, =__virt_to_phys(omap_uart_lsr)
-                ldrne   \tmp, =omap_uart_lsr
-                str     \rx, [\tmp, #0]
+95:             ldr     \rp, =ZOOM_UART_BASE
+                mrc     p15, 0, \rv, c1, c0
+                tst     \rv, #1                 @ MMU enabled?
+                ldreq   \rv, =omap_uart_v2p(omap_uart_phys)     @ MMU disabled
+                ldrne   \rv, =omap_uart_phys    @ MMU enabled
+                str     \rp, [\rv, #0]
+                ldr     \rp, =ZOOM_UART_VIRT
+                add     \rv, \rv, #4            @ omap_uart_virt
+                str     \rp, [\rv, #0]
+                mov     \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
+                add     \rv, \rv, #4            @ omap_uart_lsr
+                str     \rp, [\rv, #0]
                 b       10b
 
                 /* Store both phys and virt address for the uart */
-98:             add     \rx, \rx, #0x48000000   @ phys base
-                mrc     p15, 0, \tmp, c1, c0
-                tst     \tmp, #1                @ MMU enabled?
-                ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
-                ldrne   \tmp, =omap_uart_phys
-                str     \rx, [\tmp, #0]
-                sub     \rx, \rx, #0x48000000   @ phys base
-                add     \rx, \rx, #0xfa000000   @ virt base
-                ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
-                ldrne   \tmp, =omap_uart_virt
-                str     \rx, [\tmp, #0]
-                mov     \rx, #(UART_LSR << OMAP_PORT_SHIFT)
-                ldreq   \tmp, =__virt_to_phys(omap_uart_lsr)
-                ldrne   \tmp, =omap_uart_lsr
-                str     \rx, [\tmp, #0]
+98:             add     \rp, \rp, #0x48000000   @ phys base
+                mrc     p15, 0, \rv, c1, c0
+                tst     \rv, #1                 @ MMU enabled?
+                ldreq   \rv, =omap_uart_v2p(omap_uart_phys)     @ MMU disabled
+                ldrne   \rv, =omap_uart_phys    @ MMU enabled
+                str     \rp, [\rv, #0]
+                sub     \rp, \rp, #0x48000000   @ phys base
+                add     \rp, \rp, #0xfa000000   @ virt base
+                add     \rv, \rv, #4            @ omap_uart_virt
+                str     \rp, [\rv, #0]
+                mov     \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+                add     \rv, \rv, #4            @ omap_uart_lsr
+                str     \rp, [\rv, #0]
 
                 b       10b
 99:
@@ -131,9 +145,9 @@ omap_uart_lsr:	.word	0
 
                 .macro  busyuart,rd,rx
 1001:           mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1         @ MMU enabled?
-                ldreq   \rd, =__virt_to_phys(omap_uart_lsr)
-                ldrne   \rd, =omap_uart_lsr
+                tst     \rd, #1                 @ MMU enabled?
+                ldreq   \rd, =omap_uart_v2p(omap_uart_lsr)      @ MMU disabled
+                ldrne   \rd, =omap_uart_lsr     @ MMU enabled
                 ldr     \rd, [\rd, #0]
                 ldrb    \rd, [\rx, \rd]
                 and     \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1fc28a..a48690b90990 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -38,41 +38,13 @@
  */
 
 #ifdef MULTI_OMAP2
-                .pushsection .data
-omap_irq_base:  .word   0
-                .popsection
-
-                /* Configure the interrupt base on the first interrupt */
+                /*
+                 * Configure the interrupt base on the first interrupt.
+                 * See also omap_irq_base_init for setting omap_irq_base.
+                 */
                 .macro  get_irqnr_preamble, base, tmp
-9:
                 ldr     \base, =omap_irq_base   @ irq base address
                 ldr     \base, [\base, #0]      @ irq base value
-                cmp     \base, #0               @ already configured?
-                bne     9997f                   @ nothing to do
-
-                mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
-                and     \tmp, \tmp, #0x000f0000 @ only check architecture
-                cmp     \tmp, #0x00070000       @ is v6?
-                beq     2400f                   @ found v6 so it's omap24xx
-                mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
-                and     \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
-                cmp     \tmp, #0x00000080       @ cortex A-8?
-                beq     3400f                   @ found A-8 so it's omap34xx
-                cmp     \tmp, #0x00000090       @ cortex A-9?
-                beq     4400f                   @ found A-9 so it's omap44xx
-2400:           ldr     \base, =OMAP2_IRQ_BASE
-                ldr     \tmp, =omap_irq_base
-                str     \base, [\tmp, #0]
-                b       9b
-3400:           ldr     \base, =OMAP3_IRQ_BASE
-                ldr     \tmp, =omap_irq_base
-                str     \base, [\tmp, #0]
-                b       9b
-4400:           ldr     \base, =OMAP4_IRQ_BASE
-                ldr     \tmp, =omap_irq_base
-                str     \base, [\tmp, #0]
-                b       9b
-9997:
                 .endm
 
                 /* Check the pending interrupts. Note that base already set */
@@ -89,6 +61,14 @@ omap_irq_base:	.word	0
                 bne     9998f
                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
                 cmp     \irqnr, #0x0
+                bne     9998f
+
+                /*
+                 * ti816x has additional IRQ pending register. Checking this
+                 * register on omap2 & omap3 has no effect (read as 0).
+                 */
+                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+                cmp     \irqnr, #0x0
 9998:
                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
@@ -105,6 +85,35 @@ omap_irq_base:	.word	0
 9999:
                 .endm
 
+#ifdef CONFIG_SMP
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt
+                 * on the controller, since this requires the original irqstat
+                 * value which we won't easily be able to recreate later.
+                 */
+
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                it      cc
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                it      cs
+                cmpcs   \irqnr, \irqnr
+                .endm
+
+                /* As above, this assumes that irqstat and base are preserved */
+
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                itt     eq
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
+#endif  /* CONFIG_SMP */
 
 #else   /* MULTI_OMAP2 */
 
@@ -132,6 +141,11 @@ omap_irq_base:	.word	0
                 bne     9999f
                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
                 cmp     \irqnr, #0x0
+#ifdef CONFIG_SOC_OMAPTI816X
+                bne     9999f
+                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+                cmp     \irqnr, #0x0
+#endif
 9999:
                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
@@ -141,74 +155,16 @@ omap_irq_base:	.word	0
 
 
 #ifdef CONFIG_ARCH_OMAP4
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
 
                 .macro  get_irqnr_preamble, base, tmp
                 ldr     \base, =OMAP4_IRQ_BASE
                 .endm
 
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020.  The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt.
-                 * We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
 #endif
-#endif  /* MULTI_OMAP2 */
 
-#ifdef CONFIG_SMP
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
-#endif  /* CONFIG_SMP */
+#endif  /* MULTI_OMAP2 */
 
                 .macro  irq_prio_table
                 .endm
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 2744dfee1ff4..e4bd87619734 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -17,17 +17,27 @@
  * wfi used in low power code. Directly opcode is used instead
  * of instruction to avoid mulit-omap build break
  */
+#ifdef CONFIG_THUMB2_KERNEL
+#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
 #define do_wfi()                        \
                 __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
+#endif
 
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *l2cache_base;
 #endif
 
-extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *gic_dist_base_addr;
 
 extern void __init gic_init_irq(void);
 extern void omap_smc1(u32 fn, u32 arg);
 
+#ifdef CONFIG_SMP
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
+#endif
 #endif
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
index 9ce9b6e8ad23..866319947760 100644
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x38000000)
+#define VMALLOC_END       0xf8000000UL
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b9ea70bce563..441e79d043a7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,21 +30,19 @@
 
 #include <plat/sram.h>
 #include <plat/sdrc.h>
-#include <plat/gpmc.h>
 #include <plat/serial.h>
 
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
+#include "io.h"
 
 #include <plat/omap-pm.h>
-#include <plat/powerdomain.h>
-#include "powerdomains.h"
-
-#include <plat/clockdomain.h>
-#include "clockdomains.h"
+#include "powerdomain.h"
 
+#include "clockdomain.h"
 #include <plat/omap_hwmod.h>
+#include <plat/multi.h>
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -67,7 +65,7 @@ static struct map_desc omap24xx_io_desc[] __initdata = {
         },
 };
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static struct map_desc omap242x_io_desc[] __initdata = {
         {
                 .virtual        = DSP_MEM_2420_VIRT,
@@ -91,7 +89,7 @@ static struct map_desc omap242x_io_desc[] __initdata = {
 
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static struct map_desc omap243x_io_desc[] __initdata = {
         {
                 .virtual        = L4_WK_243X_VIRT,
@@ -176,6 +174,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 #endif
 };
 #endif
+
+#ifdef CONFIG_SOC_OMAPTI816X
+static struct map_desc omapti816x_io_desc[] __initdata = {
+        {
+                .virtual        = L4_34XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
+                .length         = L4_34XX_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+#endif
+
 #ifdef  CONFIG_ARCH_OMAP4
 static struct map_desc omap44xx_io_desc[] __initdata = {
         {
@@ -242,7 +252,7 @@ static void __init _omap2_map_common_io(void)
         omap_sram_init();
 }
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 void __init omap242x_map_common_io(void)
 {
         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
@@ -251,7 +261,7 @@ void __init omap242x_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 void __init omap243x_map_common_io(void)
 {
         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
@@ -268,6 +278,14 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPTI816X
+void __init omapti816x_map_common_io(void)
+{
+        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+        _omap2_map_common_io();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap44xx_map_common_io(void)
 {
@@ -296,7 +314,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
                 return 0;
 
         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
-        if (!dpll3_m2_ck)
+        if (IS_ERR(dpll3_m2_ck))
                 return -EINVAL;
 
         rate = clk_get_rate(dpll3_m2_ck);
@@ -310,21 +328,79 @@ static int __init _omap2_init_reprogram_sdrc(void)
         return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
-                                 struct omap_sdrc_params *sdrc_cs1)
+static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 {
-        u8 skip_setup_idle = 0;
+        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
+}
 
-        pwrdm_init(powerdomains_omap);
-        clkdm_init(clockdomains_omap, clkdm_autodeps);
-        if (cpu_is_omap242x())
+void __iomem *omap_irq_base;
+
+/*
+ * Initialize asm_irq_base for entry-macro.S
+ */
+static inline void omap_irq_base_init(void)
+{
+        if (cpu_is_omap24xx())
+                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
+        else if (cpu_is_omap34xx())
+                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
+        else if (cpu_is_omap44xx())
+                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
+        else
+                pr_err("Could not initialize omap_irq_base\n");
+}
+
+void __init omap2_init_common_infrastructure(void)
+{
+        u8 postsetup_state;
+
+        if (cpu_is_omap242x()) {
+                omap2xxx_powerdomains_init();
+                omap2xxx_clockdomains_init();
                 omap2420_hwmod_init();
-        else if (cpu_is_omap243x())
+        } else if (cpu_is_omap243x()) {
+                omap2xxx_powerdomains_init();
+                omap2xxx_clockdomains_init();
                 omap2430_hwmod_init();
-        else if (cpu_is_omap34xx())
+        } else if (cpu_is_omap34xx()) {
+                omap3xxx_powerdomains_init();
+                omap3xxx_clockdomains_init();
                 omap3xxx_hwmod_init();
-        /* The OPP tables have to be registered before a clk init */
-        omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
+        } else if (cpu_is_omap44xx()) {
+                omap44xx_powerdomains_init();
+                omap44xx_clockdomains_init();
+                omap44xx_hwmod_init();
+        } else {
+                pr_err("Could not init hwmod data - unknown SoC\n");
+        }
+
+        /* Set the default postsetup state for all hwmods */
+#ifdef CONFIG_PM_RUNTIME
+        postsetup_state = _HWMOD_STATE_IDLE;
+#else
+        postsetup_state = _HWMOD_STATE_ENABLED;
+#endif
+        omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
+
+        /*
+         * Set the default postsetup state for unusual modules (like
+         * MPU WDT).
+         *
+         * The postsetup_state is not actually used until
+         * omap_hwmod_late_init(), so boards that desire full watchdog
+         * coverage of kernel initialization can reprogram the
+         * postsetup_state between the calls to
+         * omap2_init_common_infra() and omap2_init_common_devices().
+         *
+         * XXX ideally we could detect whether the MPU WDT was currently
+         * enabled here and make this conditional
+         */
+        postsetup_state = _HWMOD_STATE_DISABLED;
+        omap_hwmod_for_each_by_class("wd_timer",
+                                     _set_hwmod_postsetup_state,
+                                     &postsetup_state);
+
+        omap_pm_if_early_init();
 
         if (cpu_is_omap2420())
                 omap2420_clk_init();
@@ -335,19 +411,56 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
         else if (cpu_is_omap44xx())
                 omap4xxx_clk_init();
         else
-                pr_err("Could not init clock framework - unknown CPU\n");
-
-        omap_serial_early_init();
-
-#ifndef CONFIG_PM_RUNTIME
-        skip_setup_idle = 1;
-#endif
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())   /* FIXME: OMAP4 */
-                omap_hwmod_late_init(skip_setup_idle);
+                pr_err("Could not init clock framework - unknown SoC\n");
+}
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+                                      struct omap_sdrc_params *sdrc_cs1)
+{
+        if (cpu_is_omap24xx() || omap3_has_sdrc()) {
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
         }
-        gpmc_init();
+
+        omap_irq_base_init();
+}
+
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
 }
+EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
new file mode 100644
index 000000000000..fd230c6cded5
--- /dev/null
+++ b/arch/arm/mach-omap2/io.h
@@ -0,0 +1,7 @@
+
+#ifndef __MACH_OMAP2_IO_H__
+#define __MACH_OMAP2_IO_H__
+
+extern int __init omap_sram_init(void);
+
+#endif /*  __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 14ee686b6492..adb083e41acd 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -145,35 +145,32 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
 
 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 {
-        int i;
         u32 stat, da;
-        const char *err_msg[] = {
-                "tlb miss",
-                "translation fault",
-                "emulation miss",
-                "table walk fault",
-                "multi hit fault",
-        };
+        u32 errs = 0;
 
         stat = iommu_read_reg(obj, MMU_IRQSTATUS);
         stat &= MMU_IRQ_MASK;
-        if (!stat)
+        if (!stat) {
+                *ra = 0;
                 return 0;
+        }
 
         da = iommu_read_reg(obj, MMU_FAULT_AD);
         *ra = da;
 
-        dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
-
-        for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
-                if (stat & (1 << i))
-                        printk("%s ", err_msg[i]);
-        }
-        printk("\n");
-
+        if (stat & MMU_IRQ_TLBMISS)
+                errs |= OMAP_IOMMU_ERR_TLB_MISS;
+        if (stat & MMU_IRQ_TRANSLATIONFAULT)
+                errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
+        if (stat & MMU_IRQ_EMUMISS)
+                errs |= OMAP_IOMMU_ERR_EMU_MISS;
+        if (stat & MMU_IRQ_TABLEWALKFAULT)
+                errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
+        if (stat & MMU_IRQ_MULTIHITFAULT)
+                errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
         iommu_write_reg(obj, stat, MMU_IRQSTATUS);
 
-        return stat;
+        return errs;
 }
 
 static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 26aeef560aa3..3af2b7a1045e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -47,7 +47,6 @@ static struct omap_irq_bank {
 } __attribute__ ((aligned(4))) irq_banks[] = {
         {
                 /* MPU INTC */
-                .base_reg       = 0,
                 .nr_irqs        = 96,
         },
 };
@@ -62,8 +61,6 @@ struct omap3_intc_regs {
         u32 mir[INTCPS_NR_MIR_REGS];
 };
 
-static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
-
 /* INTC bank register get/set */
 
 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@@ -76,81 +73,18 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
         return __raw_readl(bank->base_reg + reg);
 }
 
-static int previous_irq;
-
-/*
- * On 34xx we can get occasional spurious interrupts if the ack from
- * an interrupt handler does not get posted before we unmask. Warn about
- * the interrupt handlers that need to flush posted writes.
- */
-static int omap_check_spurious(unsigned int irq)
-{
-        u32 sir, spurious;
-
-        sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
-        spurious = sir >> 7;
-
-        if (spurious) {
-                printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
-                                        "posted write for irq %i\n",
-                                        irq, sir, previous_irq);
-                return spurious;
-        }
-
-        return 0;
-}
-
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
-static void omap_ack_irq(unsigned int irq)
+static void omap_ack_irq(struct irq_data *d)
 {
         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 }
 
-static void omap_mask_irq(unsigned int irq)
+static void omap_mask_ack_irq(struct irq_data *d)
 {
-        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
-        if (cpu_is_omap34xx()) {
-                int spurious = 0;
-
-                /*
-                 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
-                 * it is the highest irq number?
-                 */
-                if (irq == INT_34XX_GPT12_IRQ)
-                        spurious = omap_check_spurious(irq);
-
-                if (!spurious)
-                        previous_irq = irq;
-        }
-
-        irq &= (IRQ_BITS_PER_REG - 1);
-
-        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
+        irq_gc_mask_disable_reg(d);
+        omap_ack_irq(d);
 }
 
-static void omap_unmask_irq(unsigned int irq)
-{
-        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
-        irq &= (IRQ_BITS_PER_REG - 1);
-
-        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
-}
-
-static void omap_mask_ack_irq(unsigned int irq)
-{
-        omap_mask_irq(irq);
-        omap_ack_irq(irq);
-}
-
-static struct irq_chip omap_irq_chip = {
-        .name   = "INTC",
-        .ack    = omap_mask_ack_irq,
-        .mask   = omap_mask_irq,
-        .unmask = omap_unmask_irq,
-};
-
 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 {
         unsigned long tmp;
@@ -187,11 +121,31 @@ int omap_irq_pending(void)
         return 0;
 }
 
+static __init void
+omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
+                                        handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = omap_mask_ack_irq;
+        ct->chip.irq_mask = irq_gc_mask_disable_reg;
+        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+
+        ct->regs.ack = INTC_CONTROL;
+        ct->regs.enable = INTC_MIR_CLEAR0;
+        ct->regs.disable = INTC_MIR_SET0;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+}
+
 void __init omap_init_irq(void)
 {
         unsigned long nr_of_irqs = 0;
         unsigned int nr_banks = 0;
-        int i;
+        int i, j;
 
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
                 unsigned long base = 0;
@@ -204,6 +158,9 @@ void __init omap_init_irq(void)
 
                 BUG_ON(!base);
 
+                if (cpu_is_ti816x())
+                        bank->nr_irqs = 128;
+
                 /* Static mapping, never released */
                 bank->base_reg = ioremap(base, SZ_4K);
                 if (!bank->base_reg) {
@@ -213,21 +170,20 @@ void __init omap_init_irq(void)
 
                 omap_irq_bank_init_one(bank);
 
+                for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
+                        omap_alloc_gc(bank->base_reg + j, i, 32);
+
                 nr_of_irqs += bank->nr_irqs;
                 nr_banks++;
         }
 
         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
-
-        for (i = 0; i < nr_of_irqs; i++) {
-                set_irq_chip(i, &omap_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
 }
 
 #ifdef CONFIG_ARCH_OMAP3
+static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
+
 void omap_intc_save_context(void)
 {
         int ind = 0, i = 0;
@@ -285,7 +241,10 @@ void omap3_intc_suspend(void)
 
 void omap3_intc_prepare_idle(void)
 {
-        /* Disable autoidle as it can stall interrupt controller */
+        /*
+         * Disable autoidle as it can stall interrupt controller,
+         * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
+         */
         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
 }
 
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 42dbfa46e656..86d564a640bb 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,12 +14,11 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/pm_runtime.h>
 #include <plat/mailbox.h>
 #include <mach/irqs.h>
 
 #define MAILBOX_REVISION                0x000
-#define MAILBOX_SYSCONFIG               0x010
-#define MAILBOX_SYSSTATUS               0x014
 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
 #define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
 #define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
@@ -33,17 +32,6 @@
 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
 
-/* SYSCONFIG: register bit definition */
-#define AUTOIDLE        (1 << 0)
-#define SOFTRESET       (1 << 1)
-#define SMARTIDLE       (2 << 3)
-#define OMAP4_SOFTRESET (1 << 0)
-#define OMAP4_NOIDLE    (1 << 2)
-#define OMAP4_SMARTIDLE (2 << 2)
-
-/* SYSSTATUS: register bit definition */
-#define RESETDONE       (1 << 0)
-
 #define MBOX_REG_SIZE                   0x120
 
 #define OMAP4_MBOX_REG_SIZE             0x130
@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
         unsigned long irqdisable;
 };
 
-static struct clk *mbox_ick_handle;
-
 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
                                   omap_mbox_type_t irq);
 
@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
 static int omap2_mbox_startup(struct omap_mbox *mbox)
 {
         u32 l;
-        unsigned long timeout;
 
-        mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
-        if (IS_ERR(mbox_ick_handle)) {
-                printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
-                        PTR_ERR(mbox_ick_handle));
-                return PTR_ERR(mbox_ick_handle);
-        }
-        clk_enable(mbox_ick_handle);
-
-        if (cpu_is_omap44xx()) {
-                mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
-                timeout = jiffies + msecs_to_jiffies(20);
-                do {
-                        l = mbox_read_reg(MAILBOX_SYSCONFIG);
-                        if (!(l & OMAP4_SOFTRESET))
-                                break;
-                } while (!time_after(jiffies, timeout));
-
-                if (l & OMAP4_SOFTRESET) {
-                        pr_err("Can't take mailbox out of reset\n");
-                        return -ENODEV;
-                }
-        } else {
-                mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
-                timeout = jiffies + msecs_to_jiffies(20);
-                do {
-                        l = mbox_read_reg(MAILBOX_SYSSTATUS);
-                        if (l & RESETDONE)
-                                break;
-                } while (!time_after(jiffies, timeout));
-
-                if (!(l & RESETDONE)) {
-                        pr_err("Can't take mailbox out of reset\n");
-                        return -ENODEV;
-                }
-        }
+        pm_runtime_enable(mbox->dev->parent);
+        pm_runtime_get_sync(mbox->dev->parent);
 
         l = mbox_read_reg(MAILBOX_REVISION);
         pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 
-        if (cpu_is_omap44xx())
-                l = OMAP4_SMARTIDLE;
-        else
-                l = SMARTIDLE | AUTOIDLE;
-        mbox_write_reg(l, MAILBOX_SYSCONFIG);
-
         omap2_mbox_enable_irq(mbox, IRQ_RX);
 
         return 0;
@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
 
 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
 {
-        clk_disable(mbox_ick_handle);
-        clk_put(mbox_ick_handle);
-        mbox_ick_handle = NULL;
+        pm_runtime_put_sync(mbox->dev->parent);
+        pm_runtime_disable(mbox->dev->parent);
 }
 
 /* Mailbox FIFO handle functions */
@@ -181,7 +126,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
         l = mbox_read_reg(p->irqenable);
@@ -192,17 +137,19 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
-        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        l = mbox_read_reg(p->irqdisable);
-        l &= ~bit;
-        mbox_write_reg(l, p->irqdisable);
+        struct omap_mbox2_priv *p = mbox->priv;
+        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+
+        if (!cpu_is_omap44xx())
+                bit = mbox_read_reg(p->irqdisable) & ~bit;
+
+        mbox_write_reg(bit, p->irqdisable);
 }
 
 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
         mbox_write_reg(bit, p->irqstatus);
@@ -214,7 +161,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
         u32 enable = mbox_read_reg(p->irqenable);
         u32 status = mbox_read_reg(p->irqstatus);
@@ -281,7 +228,7 @@ static struct omap_mbox_ops omap2_mbox_ops = {
 
 /* FIXME: the following structs should be filled automatically by the user id */
 
-#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
 /* DSP */
 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
         .tx_fifo = {
@@ -306,11 +253,11 @@ struct omap_mbox mbox_dsp_info = {
 };
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 /* IVA */
 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
         .tx_fifo = {
@@ -334,7 +281,7 @@ static struct omap_mbox mbox_iva_info = {
         .priv   = &omap2_mbox_iva_priv,
 };
 
-struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
+struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)
@@ -394,15 +341,19 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 
         if (false)
                 ;
-#if defined(CONFIG_ARCH_OMAP3430)
-        else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+        else if (cpu_is_omap34xx()) {
                 list = omap3_mboxes;
 
-                list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+                list[0]->irq = platform_get_irq(pdev, 0);
         }
 #endif
-#if defined(CONFIG_ARCH_OMAP2420)
-        else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+        else if (cpu_is_omap2430()) {
+                list = omap2_mboxes;
+
+                list[0]->irq = platform_get_irq(pdev, 0);
+        } else if (cpu_is_omap2420()) {
                 list = omap2_mboxes;
 
                 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
@@ -413,8 +364,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
         else if (cpu_is_omap44xx()) {
                 list = omap4_mboxes;
 
-                list[0]->irq = list[1]->irq =
-                        platform_get_irq_byname(pdev, "mbox");
+                list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
         }
 #endif
         else {
@@ -432,9 +382,8 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
                 iounmap(mbox_base);
                 return ret;
         }
-        return 0;
 
-        return ret;
+        return 0;
 }
 
 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 467aae245781..4a6ef6ab8458 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -22,234 +22,150 @@
 #include <plat/dma.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
+#include <plat/omap_device.h>
+#include <linux/pm_runtime.h>
 
-#include "mux.h"
+#include "control.h"
 
-static void omap2_mcbsp2_mux_setup(void)
+/* McBSP internal signal muxing functions */
+
+void omap2_mcbsp1_mux_clkr_src(u8 mux)
 {
-        omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA);
-        omap_mux_init_gpio(117, OMAP_PULL_ENA);
-        /*
-         * TODO: Need to add MUX settings for OMAP 2430 SDP
-         */
+        u32 v;
+
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        if (mux == CLKR_SRC_CLKR)
+                v &= ~OMAP2_MCBSP1_CLKR_MASK;
+        else if (mux == CLKR_SRC_CLKX)
+                v |= OMAP2_MCBSP1_CLKR_MASK;
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
 
-static void omap2_mcbsp_request(unsigned int id)
+void omap2_mcbsp1_mux_fsr_src(u8 mux)
 {
-        if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
-                omap2_mcbsp2_mux_setup();
+        u32 v;
+
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        if (mux == FSR_SRC_FSR)
+                v &= ~OMAP2_MCBSP1_FSR_MASK;
+        else if (mux == FSR_SRC_FSX)
+                v |= OMAP2_MCBSP1_FSR_MASK;
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
 
-static struct omap_mcbsp_ops omap2_mcbsp_ops = {
-        .request        = omap2_mcbsp_request,
-};
+/* McBSP CLKS source switching function */
 
-#ifdef CONFIG_ARCH_OMAP2420
-static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP24XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP24XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-};
-#define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
-#define OMAP2420_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
-#else
-#define omap2420_mcbsp_pdata            NULL
-#define OMAP2420_MCBSP_PDATA_SZ         0
-#define OMAP2420_MCBSP_REG_NUM          0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2430
-static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP24XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP24XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP2430_MCBSP3_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
-                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP2430_MCBSP4_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
-                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP2430_MCBSP5_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
-                .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-        },
-};
-#define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
-#define OMAP2430_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
-#else
-#define omap2430_mcbsp_pdata            NULL
-#define OMAP2430_MCBSP_PDATA_SZ         0
-#define OMAP2430_MCBSP_REG_NUM          0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP34XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP2_BASE,
-                .phys_base_st   = OMAP34XX_MCBSP2_ST_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-                .buffer_size    = 0x500, /* The FIFO has 1024 + 256 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP3_BASE,
-                .phys_base_st   = OMAP34XX_MCBSP3_ST_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
-                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP4_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
-                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP5_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
-                .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-};
-#define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
-#define OMAP34XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
-#else
-#define omap34xx_mcbsp_pdata            NULL
-#define OMAP34XX_MCBSP_PDATA_SZ         0
-#define OMAP34XX_MCBSP_REG_NUM          0
-#endif
-
-static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP44XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP1,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP44XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP2,
-                .ops            = &omap2_mcbsp_ops,
-        },
-        {
-                .phys_base      = OMAP44XX_MCBSP3_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP3,
-                .ops            = &omap2_mcbsp_ops,
-        },
+int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct clk *fck_src;
+        char *fck_src_name;
+        int r;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
+                return -EINVAL;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
+                fck_src_name = "pad_fck";
+        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+                fck_src_name = "prcm_fck";
+        else
+                return -EINVAL;
+
+        fck_src = clk_get(mcbsp->dev, fck_src_name);
+        if (IS_ERR_OR_NULL(fck_src)) {
+                pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
+                       fck_src_name);
+                return -EINVAL;
+        }
+
+        pm_runtime_put_sync(mcbsp->dev);
+
+        r = clk_set_parent(mcbsp->fclk, fck_src);
+        if (IS_ERR_VALUE(r)) {
+                pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
+                       "clks", fck_src_name);
+                clk_put(fck_src);
+                return -EINVAL;
+        }
+
+        pm_runtime_get_sync(mcbsp->dev);
+
+        clk_put(fck_src);
+
+        return 0;
+}
+EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+
+struct omap_device_pm_latency omap2_mcbsp_latency[] = {
         {
-                .phys_base      = OMAP44XX_MCBSP4_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP4,
-                .ops            = &omap2_mcbsp_ops,
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
 };
-#define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
-#define OMAP44XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
 
-static int __init omap2_mcbsp_init(void)
+static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 {
-        if (cpu_is_omap2420()) {
-                omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
-        } else if (cpu_is_omap2430()) {
-                omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
-        } else if (cpu_is_omap34xx()) {
-                omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
-        } else if (cpu_is_omap44xx()) {
-                omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
+        int id, count = 1;
+        char *name = "omap-mcbsp";
+        struct omap_hwmod *oh_device[2];
+        struct omap_mcbsp_platform_data *pdata = NULL;
+        struct omap_device *od;
+
+        sscanf(oh->name, "mcbsp%d", &id);
+
+        pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("%s: No memory for mcbsp\n", __func__);
+                return -ENOMEM;
+        }
+
+        pdata->mcbsp_config_type = oh->class->rev;
+
+        if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+                if (id == 2)
+                        /* The FIFO has 1024 + 256 locations */
+                        pdata->buffer_size = 0x500;
+                else
+                        /* The FIFO has 128 locations */
+                        pdata->buffer_size = 0x80;
+        }
+
+        oh_device[0] = oh;
+
+        if (oh->dev_attr) {
+                oh_device[1] = omap_hwmod_lookup((
+                (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
+                count++;
         }
+        od = omap_device_build_ss(name, id, oh_device, count, pdata,
+                                sizeof(*pdata), omap2_mcbsp_latency,
+                                ARRAY_SIZE(omap2_mcbsp_latency), false);
+        kfree(pdata);
+        if (IS_ERR(od))  {
+                pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
+                                        name, oh->name);
+                return PTR_ERR(od);
+        }
+        omap_mcbsp_count++;
+        return 0;
+}
+
+static int __init omap2_mcbsp_init(void)
+{
+        omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
                                                                 GFP_KERNEL);
         if (!mcbsp_ptr)
                 return -ENOMEM;
 
-        if (cpu_is_omap2420())
-                omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
-                                                OMAP2420_MCBSP_PDATA_SZ);
-        if (cpu_is_omap2430())
-                omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
-                                                OMAP2430_MCBSP_PDATA_SZ);
-        if (cpu_is_omap34xx())
-                omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
-                                                OMAP34XX_MCBSP_PDATA_SZ);
-        if (cpu_is_omap44xx())
-                omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
-                                                OMAP44XX_MCBSP_PDATA_SZ);
-
         return omap_mcbsp_init();
 }
 arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ab403b2ed26b..c7fb22abc219 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,9 +1,9 @@
 /*
  * linux/arch/arm/mach-omap2/mux.c
  *
- * OMAP2 and OMAP3 pin multiplexing configurations
+ * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
  *
- * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2004 - 2010 Texas Instruments Inc.
  * Copyright (C) 2003 - 2008 Nokia Corporation
  *
  * Written by Tony Lindgren
@@ -23,12 +23,11 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  *
  */
-#include <linux/module.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
 #include <linux/list.h>
+#include <linux/slab.h>
 #include <linux/ctype.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -36,66 +35,82 @@
 
 #include <asm/system.h>
 
-#include <plat/control.h>
+#include <plat/omap_hwmod.h>
 
+#include "control.h"
 #include "mux.h"
 
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ                0x5ca
-#define MUXABLE_GPIO_MODE3              BIT(0)
 
 struct omap_mux_entry {
         struct omap_mux         mux;
         struct list_head        node;
 };
 
-static unsigned long mux_phys;
-static void __iomem *mux_base;
-static u8 omap_mux_flags;
+static LIST_HEAD(mux_partitions);
+static DEFINE_MUTEX(muxmode_mutex);
+
+struct omap_mux_partition *omap_mux_get(const char *name)
+{
+        struct omap_mux_partition *partition;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                if (!strcmp(name, partition->name))
+                        return partition;
+        }
+
+        return NULL;
+}
 
-u16 omap_mux_read(u16 reg)
+u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
 {
-        if (cpu_is_omap24xx())
-                return __raw_readb(mux_base + reg);
+        if (partition->flags & OMAP_MUX_REG_8BIT)
+                return __raw_readb(partition->base + reg);
         else
-                return __raw_readw(mux_base + reg);
+                return __raw_readw(partition->base + reg);
 }
 
-void omap_mux_write(u16 val, u16 reg)
+void omap_mux_write(struct omap_mux_partition *partition, u16 val,
+                           u16 reg)
 {
-        if (cpu_is_omap24xx())
-                __raw_writeb(val, mux_base + reg);
+        if (partition->flags & OMAP_MUX_REG_8BIT)
+                __raw_writeb(val, partition->base + reg);
         else
-                __raw_writew(val, mux_base + reg);
+                __raw_writew(val, partition->base + reg);
 }
 
-void omap_mux_write_array(struct omap_board_mux *board_mux)
+void omap_mux_write_array(struct omap_mux_partition *partition,
+                                 struct omap_board_mux *board_mux)
 {
-        while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
-                omap_mux_write(board_mux->value, board_mux->reg_offset);
+        if (!board_mux)
+                return;
+
+        while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
+                omap_mux_write(partition, board_mux->value,
+                               board_mux->reg_offset);
                 board_mux++;
         }
 }
 
-static LIST_HEAD(muxmodes);
-static DEFINE_MUTEX(muxmode_mutex);
-
 #ifdef CONFIG_OMAP_MUX
 
 static char *omap_mux_options;
 
-int __init omap_mux_init_gpio(int gpio, int val)
+static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
+                                      int gpio, int val)
 {
         struct omap_mux_entry *e;
-        struct omap_mux *gpio_mux;
+        struct omap_mux *gpio_mux = NULL;
         u16 old_mode;
         u16 mux_mode;
         int found = 0;
+        struct list_head *muxmodes = &partition->muxmodes;
 
         if (!gpio)
                 return -EINVAL;
 
-        list_for_each_entry(e, &muxmodes, node) {
+        list_for_each_entry(e, muxmodes, node) {
                 struct omap_mux *m = &e->mux;
                 if (gpio == m->gpio) {
                         gpio_mux = m;
@@ -104,87 +119,312 @@ int __init omap_mux_init_gpio(int gpio, int val)
         }
 
         if (found == 0) {
-                printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+                pr_err("%s: Could not set gpio%i\n", __func__, gpio);
                 return -ENODEV;
         }
 
         if (found > 1) {
-                printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n",
-                                found, gpio);
+                pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
+                        found, gpio);
                 return -EINVAL;
         }
 
-        old_mode = omap_mux_read(gpio_mux->reg_offset);
+        old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
         mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
-        if (omap_mux_flags & MUXABLE_GPIO_MODE3)
+        if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
                 mux_mode |= OMAP_MUX_MODE3;
         else
                 mux_mode |= OMAP_MUX_MODE4;
-        printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
-                        gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
-        omap_mux_write(mux_mode, gpio_mux->reg_offset);
+        pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
+                 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
+        omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
 
         return 0;
 }
 
-int __init omap_mux_init_signal(char *muxname, int val)
+int __init omap_mux_init_gpio(int gpio, int val)
 {
+        struct omap_mux_partition *partition;
+        int ret;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                ret = _omap_mux_init_gpio(partition, gpio, val);
+                if (!ret)
+                        return ret;
+        }
+
+        return -ENODEV;
+}
+
+static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
+                                        const char *muxname,
+                                        struct omap_mux **found_mux)
+{
+        struct omap_mux *mux = NULL;
         struct omap_mux_entry *e;
-        char *m0_name = NULL, *mode_name = NULL;
-        int found = 0;
+        const char *mode_name;
+        int found = 0, found_mode = 0, mode0_len = 0;
+        struct list_head *muxmodes = &partition->muxmodes;
 
         mode_name = strchr(muxname, '.');
         if (mode_name) {
-                *mode_name = '\0';
+                mode0_len = strlen(muxname) - strlen(mode_name);
                 mode_name++;
-                m0_name = muxname;
         } else {
                 mode_name = muxname;
         }
 
-        list_for_each_entry(e, &muxmodes, node) {
-                struct omap_mux *m = &e->mux;
-                char *m0_entry = m->muxnames[0];
+        list_for_each_entry(e, muxmodes, node) {
+                char *m0_entry;
                 int i;
 
-                if (m0_name && strcmp(m0_name, m0_entry))
+                mux = &e->mux;
+                m0_entry = mux->muxnames[0];
+
+                /* First check for full name in mode0.muxmode format */
+                if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
                         continue;
 
+                /* Then check for muxmode only */
                 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
-                        char *mode_cur = m->muxnames[i];
+                        char *mode_cur = mux->muxnames[i];
 
                         if (!mode_cur)
                                 continue;
 
                         if (!strcmp(mode_name, mode_cur)) {
-                                u16 old_mode;
-                                u16 mux_mode;
-
-                                old_mode = omap_mux_read(m->reg_offset);
-                                mux_mode = val | i;
-                                printk(KERN_DEBUG "mux: Setting signal "
-                                        "%s.%s 0x%04x -> 0x%04x\n",
-                                        m0_entry, muxname, old_mode, mux_mode);
-                                omap_mux_write(mux_mode, m->reg_offset);
+                                *found_mux = mux;
                                 found++;
+                                found_mode = i;
                         }
                 }
         }
 
-        if (found == 1)
-                return 0;
+        if (found == 1) {
+                return found_mode;
+        }
 
         if (found > 1) {
-                printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
-                                found, muxname);
+                pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
+                       found, muxname);
                 return -EINVAL;
         }
 
-        printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
+        pr_err("%s: Could not find signal %s\n", __func__, muxname);
+
+        return -ENODEV;
+}
+
+static int __init
+omap_mux_get_by_name(const char *muxname,
+                        struct omap_mux_partition **found_partition,
+                        struct omap_mux **found_mux)
+{
+        struct omap_mux_partition *partition;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                struct omap_mux *mux = NULL;
+                int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
+                if (mux_mode < 0)
+                        continue;
+
+                *found_partition = partition;
+                *found_mux = mux;
+
+                return mux_mode;
+        }
 
         return -ENODEV;
 }
 
+int __init omap_mux_init_signal(const char *muxname, int val)
+{
+        struct omap_mux_partition *partition = NULL;
+        struct omap_mux *mux = NULL;
+        u16 old_mode;
+        int mux_mode;
+
+        mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
+        if (mux_mode < 0)
+                return mux_mode;
+
+        old_mode = omap_mux_read(partition, mux->reg_offset);
+        mux_mode |= val;
+        pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
+                         __func__, muxname, old_mode, mux_mode);
+        omap_mux_write(partition, mux_mode, mux->reg_offset);
+
+        return 0;
+}
+
+struct omap_hwmod_mux_info * __init
+omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+{
+        struct omap_hwmod_mux_info *hmux;
+        int i, nr_pads_dynamic = 0;
+
+        if (!bpads || nr_pads < 1)
+                return NULL;
+
+        hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
+        if (!hmux)
+                goto err1;
+
+        hmux->nr_pads = nr_pads;
+
+        hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
+                                nr_pads, GFP_KERNEL);
+        if (!hmux->pads)
+                goto err2;
+
+        for (i = 0; i < hmux->nr_pads; i++) {
+                struct omap_mux_partition *partition;
+                struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
+                struct omap_mux *mux;
+                int mux_mode;
+
+                mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
+                if (mux_mode < 0)
+                        goto err3;
+                if (!pad->partition)
+                        pad->partition = partition;
+                if (!pad->mux)
+                        pad->mux = mux;
+
+                pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
+                if (!pad->name) {
+                        int j;
+
+                        for (j = i - 1; j >= 0; j--)
+                                kfree(hmux->pads[j].name);
+                        goto err3;
+                }
+                strcpy(pad->name, bpad->name);
+
+                pad->flags = bpad->flags;
+                pad->enable = bpad->enable;
+                pad->idle = bpad->idle;
+                pad->off = bpad->off;
+
+                if (pad->flags & OMAP_DEVICE_PAD_REMUX)
+                        nr_pads_dynamic++;
+
+                pr_debug("%s: Initialized %s\n", __func__, pad->name);
+        }
+
+        if (!nr_pads_dynamic)
+                return hmux;
+
+        /*
+         * Add pads that need dynamic muxing into a separate list
+         */
+
+        hmux->nr_pads_dynamic = nr_pads_dynamic;
+        hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
+                                        nr_pads_dynamic, GFP_KERNEL);
+        if (!hmux->pads_dynamic) {
+                pr_err("%s: Could not allocate dynamic pads\n", __func__);
+                return hmux;
+        }
+
+        nr_pads_dynamic = 0;
+        for (i = 0; i < hmux->nr_pads; i++) {
+                struct omap_device_pad *pad = &hmux->pads[i];
+
+                if (pad->flags & OMAP_DEVICE_PAD_REMUX) {
+                        pr_debug("%s: pad %s tagged dynamic\n",
+                                        __func__, pad->name);
+                        hmux->pads_dynamic[nr_pads_dynamic] = pad;
+                        nr_pads_dynamic++;
+                }
+        }
+
+        return hmux;
+
+err3:
+        kfree(hmux->pads);
+err2:
+        kfree(hmux);
+err1:
+        pr_err("%s: Could not allocate device mux entry\n", __func__);
+
+        return NULL;
+}
+
+/* Assumes the calling function takes care of locking */
+void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+{
+        int i;
+
+        /* Runtime idling of dynamic pads */
+        if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
+                for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+                        struct omap_device_pad *pad = hmux->pads_dynamic[i];
+                        int val = -EINVAL;
+
+                        val = pad->idle;
+                        omap_mux_write(pad->partition, val,
+                                        pad->mux->reg_offset);
+                }
+
+                return;
+        }
+
+        /* Runtime enabling of dynamic pads */
+        if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
+                                        && hmux->enabled) {
+                for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+                        struct omap_device_pad *pad = hmux->pads_dynamic[i];
+                        int val = -EINVAL;
+
+                        val = pad->enable;
+                        omap_mux_write(pad->partition, val,
+                                        pad->mux->reg_offset);
+                }
+
+                return;
+        }
+
+        /* Enabling or disabling of all pads */
+        for (i = 0; i < hmux->nr_pads; i++) {
+                struct omap_device_pad *pad = &hmux->pads[i];
+                int flags, val = -EINVAL;
+
+                flags = pad->flags;
+
+                switch (state) {
+                case _HWMOD_STATE_ENABLED:
+                        val = pad->enable;
+                        pr_debug("%s: Enabling %s %x\n", __func__,
+                                        pad->name, val);
+                        break;
+                case _HWMOD_STATE_DISABLED:
+                        /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
+                        if (flags & OMAP_DEVICE_PAD_REMUX)
+                                val = pad->off;
+                        else
+                                val = OMAP_MUX_MODE7;
+                        pr_debug("%s: Disabling %s %x\n", __func__,
+                                        pad->name, val);
+                        break;
+                default:
+                        /* Nothing to be done */
+                        break;
+                };
+
+                if (val >= 0) {
+                        omap_mux_write(pad->partition, val,
+                                        pad->mux->reg_offset);
+                        pad->flags = flags;
+                }
+        }
+
+        if (state == _HWMOD_STATE_ENABLED)
+                hmux->enabled = true;
+        else
+                hmux->enabled = false;
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 #define OMAP_MUX_MAX_NR_FLAGS   10
@@ -249,13 +489,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val)
         } while (i-- > 0);
 }
 
-#define OMAP_MUX_DEFNAME_LEN    16
+#define OMAP_MUX_DEFNAME_LEN    32
 
 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
 {
+        struct omap_mux_partition *partition = s->private;
         struct omap_mux_entry *e;
+        u8 omap_gen = omap_rev() >> 28;
 
-        list_for_each_entry(e, &muxmodes, node) {
+        list_for_each_entry(e, &partition->muxmodes, node) {
                 struct omap_mux *m = &e->mux;
                 char m0_def[OMAP_MUX_DEFNAME_LEN];
                 char *m0_name = m->muxnames[0];
@@ -273,11 +515,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
                         }
                         m0_def[i] = toupper(m0_name[i]);
                 }
-                val = omap_mux_read(m->reg_offset);
+                val = omap_mux_read(partition, m->reg_offset);
                 mode = val & OMAP_MUX_MODE7;
-
-                seq_printf(s, "OMAP%i_MUX(%s, ",
-                                        cpu_is_omap34xx() ? 3 : 0, m0_def);
+                if (mode != 0)
+                        seq_printf(s, "/* %s */\n", m->muxnames[mode]);
+
+                /*
+                 * XXX: Might be revisited to support differences across
+                 * same OMAP generation.
+                 */
+                seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
                 omap_mux_decode(s, val);
                 seq_printf(s, "),\n");
         }
@@ -287,7 +534,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
 
 static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
 {
-        return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
+        return single_open(file, omap_mux_dbg_board_show, inode->i_private);
 }
 
 static const struct file_operations omap_mux_dbg_board_fops = {
@@ -297,19 +544,43 @@ static const struct file_operations omap_mux_dbg_board_fops = {
         .release        = single_release,
 };
 
+static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
+{
+        struct omap_mux_partition *partition;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                struct list_head *muxmodes = &partition->muxmodes;
+                struct omap_mux_entry *e;
+
+                list_for_each_entry(e, muxmodes, node) {
+                        struct omap_mux *m = &e->mux;
+
+                        if (m == mux)
+                                return partition;
+                }
+        }
+
+        return NULL;
+}
+
 static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
 {
         struct omap_mux *m = s->private;
+        struct omap_mux_partition *partition;
         const char *none = "NA";
         u16 val;
         int mode;
 
-        val = omap_mux_read(m->reg_offset);
+        partition = omap_mux_get_partition(m);
+        if (!partition)
+                return 0;
+
+        val = omap_mux_read(partition, m->reg_offset);
         mode = val & OMAP_MUX_MODE7;
 
-        seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
+        seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
                         m->muxnames[0], m->muxnames[mode],
-                        mux_phys + m->reg_offset, m->reg_offset, val,
+                        partition->phys + m->reg_offset, m->reg_offset, val,
                         m->balls[0] ? m->balls[0] : none,
                         m->balls[1] ? m->balls[1] : none);
         seq_printf(s, "mode: ");
@@ -331,14 +602,15 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
 #define OMAP_MUX_MAX_ARG_CHAR  7
 
 static ssize_t omap_mux_dbg_signal_write(struct file *file,
-                                                const char __user *user_buf,
-                                                size_t count, loff_t *ppos)
+                                         const char __user *user_buf,
+                                         size_t count, loff_t *ppos)
 {
         char buf[OMAP_MUX_MAX_ARG_CHAR];
         struct seq_file *seqf;
         struct omap_mux *m;
         unsigned long val;
         int buf_size, ret;
+        struct omap_mux_partition *partition;
 
         if (count > OMAP_MUX_MAX_ARG_CHAR)
                 return -EINVAL;
@@ -359,7 +631,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
         seqf = file->private_data;
         m = seqf->private;
 
-        omap_mux_write((u16)val, m->reg_offset);
+        partition = omap_mux_get_partition(m);
+        if (!partition)
+                return -ENODEV;
+
+        omap_mux_write(partition, (u16)val, m->reg_offset);
         *ppos += count;
 
         return count;
@@ -380,22 +656,38 @@ static const struct file_operations omap_mux_dbg_signal_fops = {
 
 static struct dentry *mux_dbg_dir;
 
-static void __init omap_mux_dbg_init(void)
+static void __init omap_mux_dbg_create_entry(
+                                struct omap_mux_partition *partition,
+                                struct dentry *mux_dbg_dir)
 {
         struct omap_mux_entry *e;
 
+        list_for_each_entry(e, &partition->muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+
+                (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
+                                          m, &omap_mux_dbg_signal_fops);
+        }
+}
+
+static void __init omap_mux_dbg_init(void)
+{
+        struct omap_mux_partition *partition;
+        static struct dentry *mux_dbg_board_dir;
+
         mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
         if (!mux_dbg_dir)
                 return;
 
-        (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
-                                        NULL, &omap_mux_dbg_board_fops);
-
-        list_for_each_entry(e, &muxmodes, node) {
-                struct omap_mux *m = &e->mux;
+        mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
+        if (!mux_dbg_board_dir)
+                return;
 
-                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
-                                        m, &omap_mux_dbg_signal_fops);
+        list_for_each_entry(partition, &mux_partitions, node) {
+                omap_mux_dbg_create_entry(partition, mux_dbg_dir);
+                (void)debugfs_create_file(partition->name, S_IRUGO,
+                                          mux_dbg_board_dir, partition,
+                                          &omap_mux_dbg_board_fops);
         }
 }
 
@@ -422,23 +714,25 @@ static void __init omap_mux_free_names(struct omap_mux *m)
 /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
 static int __init omap_mux_late_init(void)
 {
-        struct omap_mux_entry *e, *tmp;
+        struct omap_mux_partition *partition;
 
-        list_for_each_entry_safe(e, tmp, &muxmodes, node) {
-                struct omap_mux *m = &e->mux;
-                u16 mode = omap_mux_read(m->reg_offset);
+        list_for_each_entry(partition, &mux_partitions, node) {
+                struct omap_mux_entry *e, *tmp;
+                list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
+                        struct omap_mux *m = &e->mux;
+                        u16 mode = omap_mux_read(partition, m->reg_offset);
 
-                if (OMAP_MODE_GPIO(mode))
-                        continue;
+                        if (OMAP_MODE_GPIO(mode))
+                                continue;
 
 #ifndef CONFIG_DEBUG_FS
-                mutex_lock(&muxmode_mutex);
-                list_del(&e->node);
-                mutex_unlock(&muxmode_mutex);
-                omap_mux_free_names(m);
-                kfree(m);
+                        mutex_lock(&muxmode_mutex);
+                        list_del(&e->node);
+                        mutex_unlock(&muxmode_mutex);
+                        omap_mux_free_names(m);
+                        kfree(m);
 #endif
-
+                }
         }
 
         omap_mux_dbg_init();
@@ -463,8 +757,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p,
                         s++;
                 }
                 if (!found)
-                        printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
-                                        p->reg_offset);
+                        pr_err("%s: Unknown entry offset 0x%x\n", __func__,
+                               p->reg_offset);
                 p++;
         }
 }
@@ -488,8 +782,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b,
                         s++;
                 }
                 if (!found)
-                        printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
-                                        b->reg_offset);
+                        pr_err("%s: Unknown ball offset 0x%x\n", __func__,
+                               b->reg_offset);
                 b++;
         }
 }
@@ -555,7 +849,7 @@ static void __init omap_mux_set_cmdline_signals(void)
 }
 
 static int __init omap_mux_copy_names(struct omap_mux *src,
-                                        struct omap_mux *dst)
+                                      struct omap_mux *dst)
 {
         int i;
 
@@ -593,51 +887,63 @@ free:
 
 #endif  /* CONFIG_OMAP_MUX */
 
-static u16 omap_mux_get_by_gpio(int gpio)
+static struct omap_mux *omap_mux_get_by_gpio(
+                                struct omap_mux_partition *partition,
+                                int gpio)
 {
         struct omap_mux_entry *e;
-        u16 offset = OMAP_MUX_TERMINATOR;
+        struct omap_mux *ret = NULL;
 
-        list_for_each_entry(e, &muxmodes, node) {
+        list_for_each_entry(e, &partition->muxmodes, node) {
                 struct omap_mux *m = &e->mux;
                 if (m->gpio == gpio) {
-                        offset = m->reg_offset;
+                        ret = m;
                         break;
                 }
         }
 
-        return offset;
+        return ret;
 }
 
 /* Needed for dynamic muxing of GPIO pins for off-idle */
 u16 omap_mux_get_gpio(int gpio)
 {
-        u16 offset;
+        struct omap_mux_partition *partition;
+        struct omap_mux *m = NULL;
 
-        offset = omap_mux_get_by_gpio(gpio);
-        if (offset == OMAP_MUX_TERMINATOR) {
-                printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
-                return offset;
+        list_for_each_entry(partition, &mux_partitions, node) {
+                m = omap_mux_get_by_gpio(partition, gpio);
+                if (m)
+                        return omap_mux_read(partition, m->reg_offset);
         }
 
-        return omap_mux_read(offset);
+        if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+                pr_err("%s: Could not get gpio%i\n", __func__, gpio);
+
+        return OMAP_MUX_TERMINATOR;
 }
 
 /* Needed for dynamic muxing of GPIO pins for off-idle */
 void omap_mux_set_gpio(u16 val, int gpio)
 {
-        u16 offset;
+        struct omap_mux_partition *partition;
+        struct omap_mux *m = NULL;
 
-        offset = omap_mux_get_by_gpio(gpio);
-        if (offset == OMAP_MUX_TERMINATOR) {
-                printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
-                return;
+        list_for_each_entry(partition, &mux_partitions, node) {
+                m = omap_mux_get_by_gpio(partition, gpio);
+                if (m) {
+                        omap_mux_write(partition, val, m->reg_offset);
+                        return;
+                }
         }
 
-        omap_mux_write(val, offset);
+        if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+                pr_err("%s: Could not set gpio%i\n", __func__, gpio);
 }
 
-static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
+static struct omap_mux * __init omap_mux_list_add(
+                                        struct omap_mux_partition *partition,
+                                        struct omap_mux *src)
 {
         struct omap_mux_entry *entry;
         struct omap_mux *m;
@@ -647,7 +953,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
                 return NULL;
 
         m = &entry->mux;
-        memcpy(m, src, sizeof(struct omap_mux_entry));
+        entry->mux = *src;
 
 #ifdef CONFIG_OMAP_MUX
         if (omap_mux_copy_names(src, m)) {
@@ -657,7 +963,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
 #endif
 
         mutex_lock(&muxmode_mutex);
-        list_add_tail(&entry->node, &muxmodes);
+        list_add_tail(&entry->node, &partition->muxmodes);
         mutex_unlock(&muxmode_mutex);
 
         return m;
@@ -668,7 +974,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
  * the GPIO to mux offset mapping that is needed for dynamic muxing
  * of GPIO pins for off-idle.
  */
-static void __init omap_mux_init_list(struct omap_mux *superset)
+static void __init omap_mux_init_list(struct omap_mux_partition *partition,
+                                      struct omap_mux *superset)
 {
         while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
                 struct omap_mux *entry;
@@ -680,15 +987,16 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
                 }
 #else
                 /* Skip pins that are not muxed as GPIO by bootloader */
-                if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
+                if (!OMAP_MODE_GPIO(omap_mux_read(partition,
+                                    superset->reg_offset))) {
                         superset++;
                         continue;
                 }
 #endif
 
-                entry = omap_mux_list_add(superset);
+                entry = omap_mux_list_add(partition, superset);
                 if (!entry) {
-                        printk(KERN_ERR "mux: Could not add entry\n");
+                        pr_err("%s: Could not add entry\n", __func__);
                         return;
                 }
                 superset++;
@@ -707,10 +1015,11 @@ static void omap_mux_init_package(struct omap_mux *superset,
                 omap_mux_package_init_balls(package_balls, superset);
 }
 
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+                                  struct omap_board_mux *board_mux)
 {
         omap_mux_set_cmdline_signals();
-        omap_mux_write_array(board_mux);
+        omap_mux_write_array(partition, board_mux);
 }
 
 #else
@@ -721,34 +1030,50 @@ static void omap_mux_init_package(struct omap_mux *superset,
 {
 }
 
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+                                  struct omap_board_mux *board_mux)
 {
 }
 
 #endif
 
-int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
-                                struct omap_mux *superset,
-                                struct omap_mux *package_subset,
-                                struct omap_board_mux *board_mux,
-                                struct omap_ball *package_balls)
-{
-        if (mux_base)
-                return -EBUSY;
+static u32 mux_partitions_cnt;
 
-        mux_phys = mux_pbase;
-        mux_base = ioremap(mux_pbase, mux_size);
-        if (!mux_base) {
-                printk(KERN_ERR "mux: Could not ioremap\n");
+int __init omap_mux_init(const char *name, u32 flags,
+                         u32 mux_pbase, u32 mux_size,
+                         struct omap_mux *superset,
+                         struct omap_mux *package_subset,
+                         struct omap_board_mux *board_mux,
+                         struct omap_ball *package_balls)
+{
+        struct omap_mux_partition *partition;
+
+        partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
+        if (!partition)
+                return -ENOMEM;
+
+        partition->name = name;
+        partition->flags = flags;
+        partition->size = mux_size;
+        partition->phys = mux_pbase;
+        partition->base = ioremap(mux_pbase, mux_size);
+        if (!partition->base) {
+                pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
+                        __func__, partition->phys);
+                kfree(partition);
                 return -ENODEV;
         }
 
-        if (cpu_is_omap24xx())
-                omap_mux_flags = MUXABLE_GPIO_MODE3;
+        INIT_LIST_HEAD(&partition->muxmodes);
+
+        list_add_tail(&partition->node, &mux_partitions);
+        mux_partitions_cnt++;
+        pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
+                mux_partitions_cnt, partition->name, partition->flags);
 
         omap_mux_init_package(superset, package_subset, package_balls);
-        omap_mux_init_list(superset);
-        omap_mux_init_signals(board_mux);
+        omap_mux_init_list(partition, superset);
+        omap_mux_init_signals(partition, board_mux);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a8e040c2c7e9..2132308ad1e4 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2009 Nokia
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-2010 Texas Instruments
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -10,6 +10,7 @@
 #include "mux2420.h"
 #include "mux2430.h"
 #include "mux34xx.h"
+#include "mux44xx.h"
 
 #define OMAP_MUX_TERMINATOR     0xffff
 
@@ -37,6 +38,9 @@
 #define OMAP_OFF_PULL_UP                (1 << 13)
 #define OMAP_WAKEUP_EN                  (1 << 14)
 
+/* 44xx specific mux bit defines */
+#define OMAP_WAKEUP_EVENT               (1 << 15)
+
 /* Active pin states */
 #define OMAP_PIN_OUTPUT                 0
 #define OMAP_PIN_INPUT                  OMAP_INPUT_EN
@@ -56,8 +60,10 @@
 
 #define OMAP_MODE_GPIO(x)       (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
 
-/* Flags for omap_mux_init */
+/* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK               0xffff
+#define OMAP_PACKAGE_CBS                8               /* 547-pin 0.40 0.40 */
+#define OMAP_PACKAGE_CBL                7               /* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBP                6               /* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CUS                5               /* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB                4               /* 515-pin 0.40 0.50 */
@@ -66,14 +72,61 @@
 #define OMAP_PACKAGE_ZAF                1               /* 2420 447-pin SIP */
 
 
-#define OMAP_MUX_NR_MODES       8                       /* Available modes */
-#define OMAP_MUX_NR_SIDES       2                       /* Bottom & top */
+#define OMAP_MUX_NR_MODES               8               /* Available modes */
+#define OMAP_MUX_NR_SIDES               2               /* Bottom & top */
+
+/*
+ * omap_mux_init flags definition:
+ *
+ * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
+ * The default value is 16 bits.
+ * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
+ * The default is mode4.
+ */
+#define OMAP_MUX_REG_8BIT               (1 << 0)
+#define OMAP_MUX_GPIO_IN_MODE3          (1 << 1)
+
+/**
+ * struct omap_board_data - board specific device data
+ * @id: instance id
+ * @flags: additional flags for platform init code
+ * @pads: array of device specific pads
+ * @pads_cnt: ARRAY_SIZE() of pads
+ */
+struct omap_board_data {
+        int                     id;
+        u32                     flags;
+        struct omap_device_pad  *pads;
+        int                     pads_cnt;
+};
+
+/**
+ * struct mux_partition - contain partition related information
+ * @name: name of the current partition
+ * @flags: flags specific to this partition
+ * @phys: physical address
+ * @size: partition size
+ * @base: virtual address after ioremap
+ * @muxmodes: list of nodes that belong to a partition
+ * @node: list node for the partitions linked list
+ */
+struct omap_mux_partition {
+        const char              *name;
+        u32                     flags;
+        u32                     phys;
+        u32                     size;
+        void __iomem            *base;
+        struct list_head        muxmodes;
+        struct list_head        node;
+};
 
 /**
  * struct omap_mux - data for omap mux register offset and it's value
  * @reg_offset: mux register offset from the mux base
  * @gpio:       GPIO number
  * @muxnames:   available signal modes for a ball
+ * @balls:      available balls on the package
+ * @partition:  mux partition
  */
 struct omap_mux {
         u16     reg_offset;
@@ -106,6 +159,39 @@ struct omap_board_mux {
         u16     value;
 };
 
+#define OMAP_DEVICE_PAD_REMUX           BIT(1)  /* Dynamically remux a pad,
+                                                   needs enable, idle and off
+                                                   values */
+#define OMAP_DEVICE_PAD_WAKEUP          BIT(0)  /* Pad is wake-up capable */
+
+/**
+ * struct omap_device_pad - device specific pad configuration
+ * @name:               signal name
+ * @flags:              pad specific runtime flags
+ * @enable:             runtime value for a pad
+ * @idle:               idle value for a pad
+ * @off:                off value for a pad, defaults to safe mode
+ * @partition:          mux partition
+ * @mux:                mux register
+ */
+struct omap_device_pad {
+        char                            *name;
+        u8                              flags;
+        u16                             enable;
+        u16                             idle;
+        u16                             off;
+        struct omap_mux_partition       *partition;
+        struct omap_mux                 *mux;
+};
+
+struct omap_hwmod_mux_info;
+
+#define OMAP_MUX_STATIC(signal, mode)                                   \
+{                                                                       \
+        .name   = (signal),                                             \
+        .enable = (mode),                                               \
+}
+
 #if defined(CONFIG_OMAP_MUX)
 
 /**
@@ -120,7 +206,24 @@ int omap_mux_init_gpio(int gpio, int val);
  * @muxname:            Mux name in mode0_name.signal_name format
  * @val:                Options for the mux register value
  */
-int omap_mux_init_signal(char *muxname, int val);
+int omap_mux_init_signal(const char *muxname, int val);
+
+/**
+ * omap_hwmod_mux_init - initialize hwmod specific mux data
+ * @bpads:              Board specific device signal names
+ * @nr_pads:            Number of signal names for the device
+ */
+extern struct omap_hwmod_mux_info *
+omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
+
+/**
+ * omap_hwmod_mux - omap hwmod specific pin muxing
+ * @hmux:               Pads for a hwmod
+ * @state:              Desired _HWMOD_STATE
+ *
+ * Called only from omap_hwmod.c, do not use.
+ */
+void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
 
 #else
 
@@ -133,6 +236,18 @@ static inline int omap_mux_init_signal(char *muxname, int val)
         return 0;
 }
 
+static inline struct omap_hwmod_mux_info *
+omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+{
+        return NULL;
+}
+
+static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+{
+}
+
+static struct omap_board_mux *board_mux __initdata __maybe_unused;
+
 #endif
 
 /**
@@ -151,28 +266,39 @@ u16 omap_mux_get_gpio(int gpio);
 void omap_mux_set_gpio(u16 val, int gpio);
 
 /**
+ * omap_mux_get() - get a mux partition by name
+ * @name:               Name of the mux partition
+ *
+ */
+struct omap_mux_partition *omap_mux_get(const char *name);
+
+/**
  * omap_mux_read() - read mux register
+ * @partition:          Mux partition
  * @mux_offset:         Offset of the mux register
  *
  */
-u16 omap_mux_read(u16 mux_offset);
+u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
 
 /**
  * omap_mux_write() - write mux register
+ * @partition:          Mux partition
  * @val:                New mux register value
  * @mux_offset:         Offset of the mux register
  *
  * This should be only needed for dynamic remuxing of non-gpio signals.
  */
-void omap_mux_write(u16 val, u16 mux_offset);
+void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
 
 /**
  * omap_mux_write_array() - write an array of mux registers
+ * @partition:          Mux partition
  * @board_mux:          Array of mux registers terminated by MAP_MUX_TERMINATOR
  *
  * This should be only needed for dynamic remuxing of non-gpio signals.
  */
-void omap_mux_write_array(struct omap_board_mux *board_mux);
+void omap_mux_write_array(struct omap_mux_partition *p,
+                          struct omap_board_mux *board_mux);
 
 /**
  * omap2420_mux_init() - initialize mux system with board specific set
@@ -196,10 +322,21 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
 int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
 
 /**
+ * omap4_mux_init() - initialize mux system with board specific set
+ * @board_subset:       Board specific mux table
+ * @board_wkup_subset:  Board specific mux table for wakeup instance
+ * @flags:              OMAP package type used for the board
+ */
+int omap4_mux_init(struct omap_board_mux *board_subset,
+        struct omap_board_mux *board_wkup_subset, int flags);
+
+/**
  * omap_mux_init - private mux init function, do not call
  */
-int omap_mux_init(u32 mux_pbase, u32 mux_size,
-                                struct omap_mux *superset,
-                                struct omap_mux *package_subset,
-                                struct omap_board_mux *board_mux,
-                                struct omap_ball *package_balls);
+int omap_mux_init(const char *name, u32 flags,
+                  u32 mux_pbase, u32 mux_size,
+                  struct omap_mux *superset,
+                  struct omap_mux *package_subset,
+                  struct omap_board_mux *board_mux,
+                  struct omap_ball *package_balls);
+
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
index fdb04a7eb8aa..cf6de0971c6c 100644
--- a/arch/arm/mach-omap2/mux2420.c
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = {
  * Balls for 447-pin POP package
  */
 #ifdef CONFIG_DEBUG_FS
-struct omap_ball __initdata omap2420_pop_ball[] = {
+static struct omap_ball __initdata omap2420_pop_ball[] = {
         _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
         _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
         _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
@@ -678,11 +678,13 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
         case OMAP_PACKAGE_ZAF:
                 /* REVISIT: Please add data */
         default:
-                pr_warning("mux: No ball data available for omap2420 package\n");
+                pr_warning("%s: No ball data available for omap2420 package\n",
+                                __func__);
         }
 
-        return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
+        return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+                             OMAP2420_CONTROL_PADCONF_MUX_PBASE,
                              OMAP2420_CONTROL_PADCONF_MUX_SIZE,
-                                omap2420_muxmodes, NULL, board_subset,
-                                package_balls);
+                             omap2420_muxmodes, NULL, board_subset,
+                             package_balls);
 }
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
index 7dcaaa8af32a..4185f92553db 100644
--- a/arch/arm/mach-omap2/mux2430.c
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = {
  * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
  */
 #ifdef CONFIG_DEBUG_FS
-struct omap_ball __initdata omap2430_pop_ball[] = {
+static struct omap_ball __initdata omap2430_pop_ball[] = {
         _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
         _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
         _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
@@ -781,11 +781,13 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
                 package_balls = omap2430_pop_ball;
                 break;
         default:
-                pr_warning("mux: No ball data available for omap2420 package\n");
+                pr_warning("%s: No ball data available for omap2420 package\n",
+                                __func__);
         }
 
-        return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE,
+        return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+                             OMAP2430_CONTROL_PADCONF_MUX_PBASE,
                              OMAP2430_CONTROL_PADCONF_MUX_SIZE,
-                                omap2430_muxmodes, NULL, board_subset,
-                                package_balls);
+                             omap2430_muxmodes, NULL, board_subset,
+                             package_balls);
 }
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
index adbea0d03e08..9fd93149ebd9 100644
--- a/arch/arm/mach-omap2/mux2430.h
+++ b/arch/arm/mach-omap2/mux2430.h
@@ -22,7 +22,7 @@
  * absolute addresses.  The name in the macro is the mode-0 name of
  * the pin.  NOTE: These registers are 8-bits wide.
  *
- * Note that these defines use SDMMC instead of MMC for compability
+ * Note that these defines use SDMMC instead of MMC for compatibility
  * with signal names used in 3630.
  */
 #define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET                0x000
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index f64d7eea3451..17f80e4ab162 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -703,7 +703,7 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
  * Signals different on CBC package compared to the superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
-struct omap_mux __initdata omap3_cbc_subset[] = {
+static struct omap_mux __initdata omap3_cbc_subset[] = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -721,7 +721,7 @@ struct omap_mux __initdata omap3_cbc_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)        \
                 && defined(CONFIG_OMAP_PACKAGE_CBC)
-struct omap_ball __initdata omap3_cbc_ball[] = {
+static struct omap_ball __initdata omap3_cbc_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
@@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = {
  * Signals different on CUS package compared to superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
-struct omap_mux __initdata omap3_cus_subset[] = {
+static struct omap_mux __initdata omap3_cus_subset[] = {
         _OMAP3_MUXENTRY(CAM_D10, 109,
                 "cam_d10", NULL, NULL, NULL,
                 "gpio_109", NULL, NULL, "safe_mode"),
@@ -1077,7 +1077,7 @@ struct omap_mux __initdata omap3_cus_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined(CONFIG_OMAP_PACKAGE_CUS)
-struct omap_ball __initdata omap3_cus_ball[] = {
+static struct omap_ball __initdata omap3_cus_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
@@ -1269,7 +1269,7 @@ struct omap_ball __initdata omap3_cus_ball[] = {
  * Signals different on CBB package comapared to superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
-struct omap_mux __initdata omap3_cbb_subset[] = {
+static struct omap_mux __initdata omap3_cbb_subset[] = {
         _OMAP3_MUXENTRY(CAM_D10, 109,
                 "cam_d10", NULL, NULL, NULL,
                 "gpio_109", NULL, NULL, "safe_mode"),
@@ -1390,7 +1390,7 @@ struct omap_mux __initdata omap3_cbb_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined(CONFIG_OMAP_PACKAGE_CBB)
-struct omap_ball __initdata omap3_cbb_ball[] = {
+static struct omap_ball __initdata omap3_cbb_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
@@ -1600,7 +1600,7 @@ struct omap_ball __initdata omap3_cbb_ball[] = {
  * Signals different on 36XX CBP package comapared to 34XX CBC package
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
-struct omap_mux __initdata omap36xx_cbp_subset[] = {
+static struct omap_mux __initdata omap36xx_cbp_subset[] = {
         _OMAP3_MUXENTRY(CAM_D0, 99,
                 "cam_d0", NULL, "csi2_dx2", NULL,
                 "gpio_99", NULL, NULL, "safe_mode"),
@@ -1818,7 +1818,7 @@ struct omap_mux __initdata omap36xx_cbp_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined (CONFIG_OMAP_PACKAGE_CBP)
-struct omap_ball __initdata omap36xx_cbp_ball[] = {
+static struct omap_ball __initdata omap36xx_cbp_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
@@ -2049,12 +2049,13 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
                 package_balls = omap36xx_cbp_ball;
                 break;
         default:
-                printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
+                pr_err("%s Unknown omap package, mux disabled\n", __func__);
                 return -EINVAL;
         }
 
-        return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
+        return omap_mux_init("core", 0,
+                             OMAP3_CONTROL_PADCONF_MUX_PBASE,
                              OMAP3_CONTROL_PADCONF_MUX_SIZE,
-                                omap3_muxmodes, package_subset, board_subset,
-                                package_balls);
+                             omap3_muxmodes, package_subset, board_subset,
+                             package_balls);
 }
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
new file mode 100644
index 000000000000..f5a74daab2ff
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -0,0 +1,1356 @@
+/*
+ * OMAP44xx ES1.0 pin mux definition
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
+}
+
+#else
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+}
+
+#endif
+
+#define _OMAP4_BALLENTRY(M0, bb, bt)                            \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .balls          = { bb, bt },                                   \
+}
+
+/*
+ * Superset of all mux modes for omap4 ES1.0
+ */
+static struct omap_mux __initdata omap4_core_muxmodes[] = {
+        _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+                        "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+                        "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+                        "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+                        "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+                        "gpio_32", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+                        "gpio_33", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+                        "gpio_34", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+                        "gpio_35", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+                        "gpio_36", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+                        "gpio_37", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+                        "gpio_38", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+                        "gpio_39", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+                        "gpio_40", "venc_656_data0", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+                        "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+                        "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+                        "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+                        "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+                        "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+                        "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+                        "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
+                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+                        "gpio_49", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+                        "sys_ndmareq0", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+                        "gpio_51", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
+                        "gpio_52", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+                        "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+                        "sys_ndmareq1", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+                        "sys_ndmareq2", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+                        "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+                        "gpio_59", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+                        "gpio_60", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+                        "gpio_61", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+                        "gpio_62", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
+                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
+                        "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
+                        "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
+                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
+                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+                        "gpio_65", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+                        "gpio_66", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+                        "gpio_83", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+                        "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+                        NULL, "hw_dbg20", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+                        "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+                        "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+                        "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+                        "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+                        "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+                        "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+                        "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+                        "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+                        "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+                        "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+                        "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+                        "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+                        "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+                        "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+                        "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+                        "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+                        "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+                        "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+                        "gpio_96", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+                        NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+                        "gpio_98", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+                        "gpio_99", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+                        "gpio_100", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+                        "gpio_101", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+                        "gpio_102", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+                        "gpio_103", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+                        "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+                        "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+                        "gpio_106", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+                        "gpio_107", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+                        "gpio_108", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+                        "gpio_109", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+                        "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+                        "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+                        "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+                        "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+                        "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+                        "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+                        "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+                        "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+                        "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+                        "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+                        "gpio_119", "usbb2_mm_txse0", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+                        "gpio_120", "usbb2_mm_txdat", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+                        NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+                        "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+                        "gpio_123", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+                        "gpio_124", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+                        "gpio_125", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+                        "gpio_126", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+                        "gpio_127", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+                        "gpio_128", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+                        "gpio_129", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+                        "gpio_135", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+                        "gpio_136", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+                        "gpio_138", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+                        "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+                        "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+                        NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+                        "gpio_142", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+                        "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+                        "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+                        "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+                        "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+                        "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+                        "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+                        "gpio_149", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+                        "gpio_150", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
+                        "gpio_151", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
+                        "gpio_152", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
+                        "gpio_153", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
+                        "gpio_154", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
+                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
+                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+                        "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+                        "hsi2_cawake", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+                        "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+                        "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+                        "hsi2_acready", "dispc2_data21", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+                        "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+                        "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+                        "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+                        "hsi2_caready", "dispc2_data15", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+                        "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+                        "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+                        "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+                        "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+                        "gpio_169", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+                        NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
+                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
+                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
+                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
+                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
+                        "gpio_0", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
+                        "gpio_1", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
+                        "gpi_175", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
+                        "gpi_176", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
+                        "gpi_177", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
+                        "gpi_178", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
+                        "gpi_2", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
+                        "gpi_3", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
+                        "uart2_rx", "gpio_179", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
+                        "uart2_tx", "gpio_180", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+                        "gpio_181", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+                        "gpio_182", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+                        NULL, "hw_dbg0", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+                        NULL, "hw_dbg1", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+                        "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
+                        "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+                        "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
+                        "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+                        "hw_dbg5", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+                        "dispc2_data17", "hw_dbg6", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+                        "dispc2_hsync", "hw_dbg7", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+                        "hw_dbg8", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
+                        "dispc2_vsync", "hw_dbg9", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+                        "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+                        "hw_dbg11", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+                        "hw_dbg12", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+                        "hw_dbg13", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+                        "hw_dbg14", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+                        "hw_dbg15", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+                        "hw_dbg16", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+                        "hw_dbg17", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+                        "hw_dbg18", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+                        "hw_dbg19", "reserved"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL package
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ *                                0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBL)
+static struct omap_ball __initdata omap4_core_cbl_ball[] = {
+        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
+        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbl_ball  NULL
+#endif
+
+/*
+ * Signals different on ES2.0 compared to superset
+ */
+static struct omap_mux __initdata omap4_es2_core_subset[] = {
+        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+                        "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+                        "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+                        "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+                        "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+                        "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+                        "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+                        "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+                        "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+                        "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
+                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
+                        "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+                        "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+                        "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
+                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
+                        "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
+                        "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
+                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
+                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+                        "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+                        "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+                        "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+                        "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+                        "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+                        "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+                        "abe_mcasp_axr", "gpio_121", NULL,
+                        "dmtimer11_pwm_evt", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+                        "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+                        "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+                        "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+                        "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+                        "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+                        "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+                        "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
+                        "kpd_col6", "gpio_151", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
+                        "kpd_col7", "gpio_152", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
+                        "kpd_row6", "gpio_153", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
+                        "kpd_row7", "gpio_154", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
+                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
+                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+                        "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+                        "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+                        "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+                        "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+                        "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+                        "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+                        "hsi2_caready", "dispc2_data15", "rfbi_data15",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+                        "mcspi3_somi", "dispc2_data14", "rfbi_data14",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+                        "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+                        "mcspi3_simo", "dispc2_data12", "rfbi_data12",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+                        "mcspi3_clk", "dispc2_data11", "rfbi_data11",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
+                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
+                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
+                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
+                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
+                        "gpio_175", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
+                        "gpio_176", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
+                        "gpio_177", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
+                        "gpio_178", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
+                        "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
+                        "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+                        "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+                        "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+                        "hw_dbg5", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+                        "dispc2_data17", "hw_dbg6", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+                        "dispc2_hsync", "hw_dbg7", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+                        "hw_dbg8", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
+                        "dispc2_vsync", "hw_dbg9", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+                        "hw_dbg11", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+                        "hw_dbg12", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+                        "hw_dbg13", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+                        "hw_dbg14", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+                        "hw_dbg15", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+                        "hw_dbg16", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+                        "hw_dbg17", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+                        "hw_dbg18", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+                        "hw_dbg19", "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBS package
+ * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ *                                0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBS)
+static struct omap_ball __initdata omap4_core_cbs_ball[] = {
+        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
+        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+        _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
+        _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
+        _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
+        _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
+        _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
+        _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbs_ball  NULL
+#endif
+
+/*
+ * Superset of all mux modes for omap4
+ */
+static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
+        _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
+                        "c2c_wakereqin", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
+                        "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
+                        "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
+                        "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
+                        "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
+                        NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
+                        "gpio_wk8", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
+                        NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
+                        NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
+                        "gpio_wk9", "c2c_wakereqout", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
+                        "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
+                        NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
+                        NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL & CBS package - wakeup partition
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ *                                0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBL)
+static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
+        _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
+        _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
+        _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
+        _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
+        _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
+        _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
+        _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
+        _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
+        _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
+        _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
+        _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
+        _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
+        _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
+        _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
+        _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
+        _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
+        _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
+        _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
+        _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
+        _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_wkup_cbl_cbs_ball  NULL
+#endif
+
+int __init omap4_mux_init(struct omap_board_mux *board_subset,
+        struct omap_board_mux *board_wkup_subset, int flags)
+{
+        struct omap_ball *package_balls_core;
+        struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
+        struct omap_mux *core_muxmodes;
+        struct omap_mux *core_subset = NULL;
+        int ret;
+
+        switch (flags & OMAP_PACKAGE_MASK) {
+        case OMAP_PACKAGE_CBL:
+                pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
+                package_balls_core = omap4_core_cbl_ball;
+                core_muxmodes = omap4_core_muxmodes;
+                break;
+        case OMAP_PACKAGE_CBS:
+                pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
+                package_balls_core = omap4_core_cbs_ball;
+                core_muxmodes = omap4_core_muxmodes;
+                core_subset = omap4_es2_core_subset;
+                break;
+        default:
+                pr_err("%s: Unknown omap package, mux disabled\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = omap_mux_init("core",
+                            OMAP_MUX_GPIO_IN_MODE3,
+                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
+                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
+                            core_muxmodes, core_subset, board_subset,
+                            package_balls_core);
+        if (ret)
+                return ret;
+
+        ret = omap_mux_init("wkup",
+                            OMAP_MUX_GPIO_IN_MODE3,
+                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
+                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
+                            omap4_wkup_muxmodes, NULL, board_wkup_subset,
+                            package_balls_wkup);
+
+        return ret;
+}
+
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
new file mode 100644
index 000000000000..c635026cd7e9
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -0,0 +1,298 @@
+/*
+ * OMAP44xx MUX registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+
+#define OMAP4_MUX(M0, mux_value)                                        \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .value          = (mux_value),                                  \
+}
+
+/* ctrl_module_pad_core base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE                    0x4a100000
+
+/* ctrl_module_pad_core registers offset */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET                   0x0040
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET                   0x0042
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET                   0x0044
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET                   0x0046
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET                   0x0048
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET                   0x004a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET                   0x004c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET                   0x004e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET                   0x0050
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET                   0x0052
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET                  0x0054
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET                  0x0056
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET                  0x0058
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET                  0x005a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET                  0x005c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET                  0x005e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET                   0x0060
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET                   0x0062
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET                   0x0064
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET                   0x0066
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET                   0x0068
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET                   0x006a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET                   0x006c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET                   0x006e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET                   0x0070
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET                   0x0072
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET                  0x0074
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET                  0x0076
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET                  0x0078
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET                  0x007a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET                   0x007c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET                   0x007e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET              0x0080
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET                   0x0082
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET                   0x0084
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET              0x0086
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET                  0x0088
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET                 0x008a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET                 0x008c
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET                 0x008e
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET                 0x0090
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET                 0x0092
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET                 0x0094
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET                 0x0096
+#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET                   0x0098
+#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET                   0x009a
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET               0x009c
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET               0x009e
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET                  0x00a0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET                  0x00a2
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET                  0x00a4
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET                  0x00a6
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET                  0x00a8
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET                  0x00aa
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET                  0x00ac
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET                  0x00ae
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET                  0x00b0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET                  0x00b2
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET                  0x00b4
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET                  0x00b6
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET                  0x00b8
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET                  0x00ba
+#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET                0x00bc
+#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET                 0x00be
+#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET            0x00c0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET          0x00c2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET          0x00c4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET          0x00c6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET          0x00c8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET         0x00ca
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET         0x00cc
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET         0x00ce
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET         0x00d0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET         0x00d2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET         0x00d4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET         0x00d6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET         0x00d8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET            0x00da
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET          0x00dc
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET             0x00de
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET             0x00e0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET                 0x00e2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET                 0x00e4
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET                0x00e6
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET                0x00e8
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET                0x00ea
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET                0x00ec
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET                0x00ee
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET                0x00f0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET                0x00f2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET                0x00f4
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET            0x00f6
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET              0x00f8
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET              0x00fa
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET             0x00fc
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET            0x00fe
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET              0x0100
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET              0x0102
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET             0x0104
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET            0x0106
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET            0x0108
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET              0x010a
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET             0x010c
+#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET                   0x010e
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET              0x0110
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET              0x0112
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET              0x0114
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET              0x0116
+#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET                  0x0118
+#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET                  0x011a
+#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET                   0x011c
+#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET                   0x011e
+#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET                    0x0120
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET                   0x0122
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET                   0x0124
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET                   0x0126
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET                   0x0128
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET                   0x012a
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET                   0x012c
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET                   0x012e
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET                   0x0130
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET                 0x0132
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET                0x0134
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET                0x0136
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET                 0x0138
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET                 0x013a
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET                 0x013c
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET                 0x013e
+#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET             0x0140
+#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET               0x0142
+#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET              0x0144
+#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET              0x0146
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET                 0x0148
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET                 0x014a
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET                0x014c
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET                0x014e
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET                0x0150
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET                0x0152
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET                 0x0154
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET                0x0156
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET                0x0158
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET                 0x015a
+#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET                   0x015c
+#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET                   0x015e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET          0x0160
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET          0x0162
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET          0x0164
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET          0x0166
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET         0x0168
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET         0x016a
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET         0x016c
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET         0x016e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET         0x0170
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET         0x0172
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET         0x0174
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET         0x0176
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET            0x0178
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET          0x017a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET                 0x017c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET                 0x017e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET                 0x0180
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET                 0x0182
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET                 0x0184
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET                 0x0186
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET                 0x0188
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET                 0x018a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET                 0x018c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET                 0x018e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET                 0x0190
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET                 0x0192
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET               0x0194
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET               0x0196
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET               0x0198
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET              0x019a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET              0x019c
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET                  0x019e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET                  0x01a0
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET                  0x01a2
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET                  0x01a4
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET                  0x01a6
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET                  0x01a8
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET                  0x01aa
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET                  0x01ac
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET                   0x01ae
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET                   0x01b0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET                   0x01b2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET                   0x01b4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET                   0x01b6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET                   0x01b8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET                   0x01ba
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET                   0x01bc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET                   0x01be
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET                   0x01c0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET                  0x01c2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET                  0x01c4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET                  0x01c6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET                  0x01c8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET                  0x01ca
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET                  0x01cc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET                  0x01ce
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET                  0x01d0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET                  0x01d2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET                  0x01d4
+
+/* ES2.0 only */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET                 0x008e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET                  0x0090
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET                  0x0092
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET                  0x0094
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET                  0x0096
+
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET                   0x017c
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET                   0x017e
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET                   0x0180
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET                   0x0182
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET                   0x0184
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET                   0x0186
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET                   0x0188
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET                   0x018a
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET                   0x018c
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET                   0x018e
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET                   0x0190
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET                   0x0192
+
+
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE                     \
+                (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET         \
+                 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
+
+/* ctrl_module_pad_wkup base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE                    0x4a31e000
+
+/* ctrl_module_pad_wkup registers offset */
+#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET                     0x0040
+#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET                    0x0042
+#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET                  0x0044
+#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET                     0x0046
+#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET                0x0048
+#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET                     0x004a
+#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET                     0x004c
+#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET               0x004e
+#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET             0x0050
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET             0x0052
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET              0x0054
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET              0x0056
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET              0x0058
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET              0x005a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET              0x005c
+#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET                    0x005e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET              0x0060
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET               0x0062
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET                0x0064
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET        0x0066
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET                  0x0068
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET                  0x006a
+#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET                 0x006c
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET                   0x006e
+#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET                  0x0070
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET              0x0072
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET                   0x0074
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET                   0x0076
+
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE                     \
+                (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET          \
+                 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
+
+#endif
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 6ae937a06cc1..4ee6aeca885a 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -45,5 +45,5 @@ hold:	ldr	r12,=0x103
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
-END(omap_secondary_startup)
+ENDPROC(omap_secondary_startup)
 
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 6cee456ca542..4976b9393e49 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,16 +17,13 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 #include <mach/omap4-common.h>
 
-static DECLARE_COMPLETION(cpu_killed);
-
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -35,15 +32,6 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                pr_crit("platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-        pr_notice("CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
         flush_cache_all();
         dsb();
 
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index f5a1aad1a5c0..3fc5dc7233da 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -33,9 +33,11 @@ static struct iommu_device omap3_devices[] = {
                         .name = "isp",
                         .nr_tlb_entries = 8,
                         .clk_name = "cam_ick",
+                        .da_start = 0x0,
+                        .da_end = 0xFFFFF000,
                 },
         },
-#if defined(CONFIG_MPU_BRIDGE_IOMMU)
+#if defined(CONFIG_OMAP_IOMMU_IVA2)
         {
                 .base = 0x5d000000,
                 .irq = 28,
@@ -43,6 +45,8 @@ static struct iommu_device omap3_devices[] = {
                         .name = "iva2",
                         .nr_tlb_entries = 32,
                         .clk_name = "iva2_ck",
+                        .da_start = 0x11000000,
+                        .da_end = 0xFFFFF000,
                 },
         },
 #endif
@@ -64,6 +68,8 @@ static struct iommu_device omap4_devices[] = {
                         .name = "ducati",
                         .nr_tlb_entries = 32,
                         .clk_name = "ducati_ick",
+                        .da_start = 0x0,
+                        .da_end = 0xFFFFF000,
                 },
         },
 #if defined(CONFIG_MPU_TESLA_IOMMU)
@@ -74,6 +80,8 @@ static struct iommu_device omap4_devices[] = {
                         .name = "tesla",
                         .nr_tlb_entries = 32,
                         .clk_name = "tesla_ick",
+                        .da_start = 0x0,
+                        .da_end = 0xFFFFF000,
                 },
         },
 #endif
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e18e3c..ecfe93c4b585 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,7 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -29,28 +29,16 @@
 /* SCU base address */
 static void __iomem *scu_base;
 
-/*
- * Use SCU config register to count number of cores
- */
-static inline unsigned int get_core_count(void)
-{
-        if (scu_base)
-                return scu_get_core_count(scu_base);
-        return 1;
-}
-
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * If any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
 
         /*
          * Synchronise with the boot thread.
@@ -76,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         omap_modify_auxcoreboot0(0x200, 0xfffffdff);
         flush_cache_all();
         smp_wmb();
-        smp_cross_call(cpumask_of(cpu));
+        gic_raise_softirq(cpumask_of(cpu), 1);
 
         /*
          * Now the secondary core is starting up let it run its
@@ -118,25 +106,9 @@ void __init smp_init_cpus(void)
         scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
         BUG_ON(!scu_base);
 
-        ncores = get_core_count();
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
-        unsigned int ncores = get_core_count();
-        unsigned int cpu = smp_processor_id();
-        int i;
+        ncores = scu_get_core_count(scu_base);
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "OMAP4: strange core count of 0? Default to 1\n");
-                ncores = 1;
-        }
-
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "OMAP4: no. of cores (%d) greater than configured "
@@ -144,13 +116,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                        ncores, NR_CPUS);
                 ncores = NR_CPUS;
         }
-        smp_store_cpu_info(cpu);
 
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+
+        set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
 
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -159,18 +134,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                /*
-                 * Initialise the SCU and wake up the secondary core using
-                 * wakeup_secondary().
-                 */
-                scu_enable(scu_base);
-                wakeup_secondary();
-        }
+        /*
+         * Initialise the SCU and wake up the secondary core using
+         * wakeup_secondary().
+         */
+        scu_enable(scu_base);
+        wakeup_secondary();
 }
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13dc9794dcc2..9ef8c29dd817 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -26,26 +26,42 @@
 void __iomem *l2cache_base;
 #endif
 
-void __iomem *gic_cpu_base_addr;
 void __iomem *gic_dist_base_addr;
 
 
 void __init gic_init_irq(void)
 {
+        void __iomem *gic_cpu_base;
+
         /* Static mapping, never released */
         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
         BUG_ON(!gic_dist_base_addr);
-        gic_dist_init(0, gic_dist_base_addr, 29);
 
         /* Static mapping, never released */
-        gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
-        BUG_ON(!gic_cpu_base_addr);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+        BUG_ON(!gic_cpu_base);
+
+        gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
 }
 
 #ifdef CONFIG_CACHE_L2X0
+
+static void omap4_l2x0_disable(void)
+{
+        /* Disable PL310 L2 Cache controller */
+        omap_smc1(0x102, 0x0);
+}
+
+static void omap4_l2x0_set_debug(unsigned long val)
+{
+        /* Program PL310 L2 Cache controller debug register */
+        omap_smc1(0x100, val);
+}
+
 static int __init omap_l2_cache_init(void)
 {
+        u32 aux_ctrl = 0;
+
         /*
          * To avoid code running on other OMAPs in
          * multi-omap builds
@@ -57,14 +73,39 @@ static int __init omap_l2_cache_init(void)
         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
         BUG_ON(!l2cache_base);
 
+        /*
+         * 16-way associativity, parity disabled
+         * Way size - 32KB (es1.0)
+         * Way size - 64KB (es2.0 +)
+         */
+        aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
+                        (0x1 << 25) |
+                        (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
+                        (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
+
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
+        } else {
+                aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
+        }
+        if (omap_rev() != OMAP4430_REV_ES1_0)
+                omap_smc1(0x109, aux_ctrl);
+
         /* Enable PL310 L2 Cache controller */
         omap_smc1(0x102, 0x1);
 
+        l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+
         /*
-         * 32KB way size, 16-way associativity,
-         * parity disabled
-         */
-        l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+         * Override default outer_cache.disable with a OMAP4
+         * specific one
+        */
+        outer_cache.disable = omap4_l2x0_disable;
+        outer_cache.set_debug = omap4_l2x0_set_debug;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index 1980dc31a1a2..e69d37d95204 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -29,7 +29,7 @@ ENTRY(omap_smc1)
         dsb
         smc     #0
         ldmfd   sp!, {r2-r12, pc}
-END(omap_smc1)
+ENDPROC(omap_smc1)
 
 ENTRY(omap_modify_auxcoreboot0)
         stmfd   sp!, {r1-r12, lr}
@@ -37,7 +37,7 @@ ENTRY(omap_modify_auxcoreboot0)
         dsb
         smc     #0
         ldmfd   sp!, {r1-r12, pc}
-END(omap_modify_auxcoreboot0)
+ENDPROC(omap_modify_auxcoreboot0)
 
 ENTRY(omap_auxcoreboot_addr)
         stmfd   sp!, {r2-r12, lr}
@@ -45,7 +45,7 @@ ENTRY(omap_auxcoreboot_addr)
         dsb
         smc     #0
         ldmfd   sp!, {r2-r12, pc}
-END(omap_auxcoreboot_addr)
+ENDPROC(omap_auxcoreboot_addr)
 
 ENTRY(omap_read_auxcoreboot0)
         stmfd   sp!, {r2-r12, lr}
@@ -54,4 +54,4 @@ ENTRY(omap_read_auxcoreboot0)
         smc     #0
         mov     r0, r0, lsr #9
         ldmfd   sp!, {r2-r12, pc}
-END(omap_read_auxcoreboot0)
+ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cb911d7d1a3c..293fa6cd50e1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod implementation for OMAP2/3/4
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Paul Walmsley, Benoît Cousson, Kevin Hilman
  *
@@ -13,10 +13,102 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * This code manages "OMAP modules" (on-chip devices) and their
- * integration with Linux device driver and bus code.
- *
- * References:
+ * Introduction
+ * ------------
+ * One way to view an OMAP SoC is as a collection of largely unrelated
+ * IP blocks connected by interconnects.  The IP blocks include
+ * devices such as ARM processors, audio serial interfaces, UARTs,
+ * etc.  Some of these devices, like the DSP, are created by TI;
+ * others, like the SGX, largely originate from external vendors.  In
+ * TI's documentation, on-chip devices are referred to as "OMAP
+ * modules."  Some of these IP blocks are identical across several
+ * OMAP versions.  Others are revised frequently.
+ *
+ * These OMAP modules are tied together by various interconnects.
+ * Most of the address and data flow between modules is via OCP-based
+ * interconnects such as the L3 and L4 buses; but there are other
+ * interconnects that distribute the hardware clock tree, handle idle
+ * and reset signaling, supply power, and connect the modules to
+ * various pads or balls on the OMAP package.
+ *
+ * OMAP hwmod provides a consistent way to describe the on-chip
+ * hardware blocks and their integration into the rest of the chip.
+ * This description can be automatically generated from the TI
+ * hardware database.  OMAP hwmod provides a standard, consistent API
+ * to reset, enable, idle, and disable these hardware blocks.  And
+ * hwmod provides a way for other core code, such as the Linux device
+ * code or the OMAP power management and address space mapping code,
+ * to query the hardware database.
+ *
+ * Using hwmod
+ * -----------
+ * Drivers won't call hwmod functions directly.  That is done by the
+ * omap_device code, and in rare occasions, by custom integration code
+ * in arch/arm/ *omap*.  The omap_device code includes functions to
+ * build a struct platform_device using omap_hwmod data, and that is
+ * currently how hwmod data is communicated to drivers and to the
+ * Linux driver model.  Most drivers will call omap_hwmod functions only
+ * indirectly, via pm_runtime*() functions.
+ *
+ * From a layering perspective, here is where the OMAP hwmod code
+ * fits into the kernel software stack:
+ *
+ *            +-------------------------------+
+ *            |      Device driver code       |
+ *            |      (e.g., drivers/)         |
+ *            +-------------------------------+
+ *            |      Linux driver model       |
+ *            |     (platform_device /        |
+ *            |  platform_driver data/code)   |
+ *            +-------------------------------+
+ *            | OMAP core-driver integration  |
+ *            |(arch/arm/mach-omap2/devices.c)|
+ *            +-------------------------------+
+ *            |      omap_device code         |
+ *            | (../plat-omap/omap_device.c)  |
+ *            +-------------------------------+
+ *   ---->    |    omap_hwmod code/data       |    <-----
+ *            | (../mach-omap2/omap_hwmod*)   |
+ *            +-------------------------------+
+ *            | OMAP clock/PRCM/register fns  |
+ *            | (__raw_{read,write}l, clk*)   |
+ *            +-------------------------------+
+ *
+ * Device drivers should not contain any OMAP-specific code or data in
+ * them.  They should only contain code to operate the IP block that
+ * the driver is responsible for.  This is because these IP blocks can
+ * also appear in other SoCs, either from TI (such as DaVinci) or from
+ * other manufacturers; and drivers should be reusable across other
+ * platforms.
+ *
+ * The OMAP hwmod code also will attempt to reset and idle all on-chip
+ * devices upon boot.  The goal here is for the kernel to be
+ * completely self-reliant and independent from bootloaders.  This is
+ * to ensure a repeatable configuration, both to ensure consistent
+ * runtime behavior, and to make it easier for others to reproduce
+ * bugs.
+ *
+ * OMAP module activity states
+ * ---------------------------
+ * The hwmod code considers modules to be in one of several activity
+ * states.  IP blocks start out in an UNKNOWN state, then once they
+ * are registered via the hwmod code, proceed to the REGISTERED state.
+ * Once their clock names are resolved to clock pointers, the module
+ * enters the CLKS_INITED state; and finally, once the module has been
+ * reset and the integration registers programmed, the INITIALIZED state
+ * is entered.  The hwmod code will then place the module into either
+ * the IDLE state to save power, or in the case of a critical system
+ * module, the ENABLED state.
+ *
+ * OMAP core integration code can then call omap_hwmod*() functions
+ * directly to move the module between the IDLE, ENABLED, and DISABLED
+ * states, as needed.  This is done during both the PM idle loop, and
+ * in the OMAP core integration code's implementation of the PM runtime
+ * functions.
+ *
+ * References
+ * ----------
+ * This is a partial list.
  * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
  * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
  * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
@@ -24,7 +116,6 @@
  * - Open Core Protocol Specification 2.2
  *
  * To do:
- * - pin mux handling
  * - handle IO mapping
  * - bus throughput & module latency measurement code
  *
@@ -43,18 +134,24 @@
 #include <linux/err.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
+#include <linux/spinlock.h>
 
 #include <plat/common.h>
 #include <plat/cpu.h>
-#include <plat/clockdomain.h>
-#include <plat/powerdomain.h>
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
+#include <plat/prcm.h>
 
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm44xx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "mux.h"
 
-/* Maximum microseconds to wait for OMAP module to reset */
-#define MAX_MODULE_RESET_WAIT           10000
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
 
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
@@ -62,14 +159,9 @@
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 
-static DEFINE_MUTEX(omap_hwmod_mutex);
-
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
-/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
-static u8 inited;
-
 
 /* Private functions */
 
@@ -90,7 +182,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
 
         /* XXX ensure module interface clock is up */
 
-        oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
+        oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
 
         if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
                 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
@@ -115,10 +207,9 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
 
         /* XXX ensure module interface clock is up */
 
-        if (oh->_sysc_cache != v) {
-                oh->_sysc_cache = v;
-                omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs);
-        }
+        /* Module might have lost context, always update cache and register */
+        oh->_sysc_cache = v;
+        omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
 }
 
 /**
@@ -279,7 +370,7 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
         }
 
         autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
-        autoidle_mask = (0x3 << autoidle_shift);
+        autoidle_mask = (0x1 << autoidle_shift);
 
         *v &= ~autoidle_mask;
         *v |= autoidle << autoidle_shift;
@@ -294,12 +385,13 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
  * Allow the hardware module @oh to send wakeups.  Returns -EINVAL
  * upon error or 0 upon success.
  */
-static int _enable_wakeup(struct omap_hwmod *oh)
+static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
 {
-        u32 v, wakeup_mask;
+        u32 wakeup_mask;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+            !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
                 return -EINVAL;
 
         if (!oh->class->sysc->sysc_fields) {
@@ -309,9 +401,10 @@ static int _enable_wakeup(struct omap_hwmod *oh)
 
         wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
 
-        v = oh->_sysc_cache;
-        v |= wakeup_mask;
-        _write_sysconfig(v, oh);
+        *v |= wakeup_mask;
+
+        if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+                _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
@@ -327,12 +420,13 @@ static int _enable_wakeup(struct omap_hwmod *oh)
  * Prevent the hardware module @oh to send wakeups.  Returns -EINVAL
  * upon error or 0 upon success.
  */
-static int _disable_wakeup(struct omap_hwmod *oh)
+static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 {
-        u32 v, wakeup_mask;
+        u32 wakeup_mask;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+            !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
                 return -EINVAL;
 
         if (!oh->class->sysc->sysc_fields) {
@@ -342,9 +436,10 @@ static int _disable_wakeup(struct omap_hwmod *oh)
 
         wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
 
-        v = oh->_sysc_cache;
-        v &= ~wakeup_mask;
-        _write_sysconfig(v, oh);
+        *v &= ~wakeup_mask;
+
+        if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+                _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
@@ -362,14 +457,18 @@ static int _disable_wakeup(struct omap_hwmod *oh)
  * will be accessed by a particular initiator (e.g., if a module will
  * be accessed by the IVA, there should be a sleepdep between the IVA
  * initiator and the module).  Only applies to modules in smart-idle
- * mode.  Returns -EINVAL upon error or passes along
- * clkdm_add_sleepdep() value upon success.
+ * mode.  If the clockdomain is marked as not needing autodeps, return
+ * 0 without doing anything.  Otherwise, returns -EINVAL upon error or
+ * passes along clkdm_add_sleepdep() value upon success.
  */
 static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
         if (!oh->_clk)
                 return -EINVAL;
 
+        if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+                return 0;
+
         return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
 }
 
@@ -382,14 +481,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
  * be accessed by a particular initiator (e.g., if a module will not
  * be accessed by the IVA, there should be no sleepdep between the IVA
  * initiator and the module).  Only applies to modules in smart-idle
- * mode.  Returns -EINVAL upon error or passes along
- * clkdm_del_sleepdep() value upon success.
+ * mode.  If the clockdomain is marked as not needing autodeps, return
+ * 0 without doing anything.  Returns -EINVAL upon error or passes
+ * along clkdm_del_sleepdep() value upon success.
  */
 static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
         if (!oh->_clk)
                 return -EINVAL;
 
+        if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+                return 0;
+
         return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
 }
 
@@ -544,6 +647,36 @@ static int _disable_clocks(struct omap_hwmod *oh)
         return 0;
 }
 
+static void _enable_optional_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int i;
+
+        pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk) {
+                        pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
+                                 oc->_clk->name);
+                        clk_enable(oc->_clk);
+                }
+}
+
+static void _disable_optional_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int i;
+
+        pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk) {
+                        pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
+                                 oc->_clk->name);
+                        clk_disable(oc->_clk);
+                }
+}
+
 /**
  * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
  * @oh: struct omap_hwmod *
@@ -551,7 +684,7 @@ static int _disable_clocks(struct omap_hwmod *oh)
  * Returns the array index of the OCP slave port that the MPU
  * addresses the device on, or -EINVAL upon error or not found.
  */
-static int _find_mpu_port_index(struct omap_hwmod *oh)
+static int __init _find_mpu_port_index(struct omap_hwmod *oh)
 {
         int i;
         int found = 0;
@@ -585,7 +718,7 @@ static int _find_mpu_port_index(struct omap_hwmod *oh)
  * Return the virtual address of the base of the register target of
  * device @oh, or NULL on error.
  */
-static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 {
         struct omap_hwmod_ocp_if *os;
         struct omap_hwmod_addr_space *mem;
@@ -622,7 +755,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 }
 
 /**
- * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG
+ * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * If module is marked as SWSUP_SIDLE, force the module out of slave
@@ -630,7 +763,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
  * as SWSUP_MSUSPEND, force the module out of master standby;
  * otherwise, configure it for smart-standby.  No return value.
  */
-static void _sysc_enable(struct omap_hwmod *oh)
+static void _enable_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
@@ -653,14 +786,6 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
-        if (sf & SYSC_HAS_AUTOIDLE) {
-                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
-                        0 : 1;
-                _set_module_autoidle(oh, idlemode, &v);
-        }
-
-        /* XXX OCP ENAWAKEUP bit? */
-
         /*
          * XXX The clock framework should handle this, by
          * calling into this code.  But this must wait until the
@@ -670,11 +795,26 @@ static void _sysc_enable(struct omap_hwmod *oh)
             (sf & SYSC_HAS_CLOCKACTIVITY))
                 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
+        /* If slave is in SMARTIDLE, also enable wakeup */
+        if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+                _enable_wakeup(oh, &v);
+
         _write_sysconfig(v, oh);
+
+        /*
+         * Set the autoidle bit only after setting the smartidle bit
+         * Setting this will not have any impact on the other modules.
+         */
+        if (sf & SYSC_HAS_AUTOIDLE) {
+                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
+                        0 : 1;
+                _set_module_autoidle(oh, idlemode, &v);
+                _write_sysconfig(v, oh);
+        }
 }
 
 /**
- * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG
+ * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * If module is marked as SWSUP_SIDLE, force the module into slave
@@ -682,7 +822,7 @@ static void _sysc_enable(struct omap_hwmod *oh)
  * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
  * configure it for smart-standby.  No return value.
  */
-static void _sysc_idle(struct omap_hwmod *oh)
+static void _idle_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
@@ -705,17 +845,21 @@ static void _sysc_idle(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
+        /* If slave is in SMARTIDLE, also enable wakeup */
+        if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+                _enable_wakeup(oh, &v);
+
         _write_sysconfig(v, oh);
 }
 
 /**
- * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG
+ * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * Force the module into slave idle and master suspend. No return
  * value.
  */
-static void _sysc_shutdown(struct omap_hwmod *oh)
+static void _shutdown_sysc(struct omap_hwmod *oh)
 {
         u32 v;
         u8 sf;
@@ -743,7 +887,6 @@ static void _sysc_shutdown(struct omap_hwmod *oh)
  * @name: find an omap_hwmod by name
  *
  * Return a pointer to an omap_hwmod by name, or NULL if not found.
- * Caller must hold omap_hwmod_mutex.
  */
 static struct omap_hwmod *_lookup(const char *name)
 {
@@ -766,18 +909,16 @@ static struct omap_hwmod *_lookup(const char *name)
  * @oh: struct omap_hwmod *
  * @data: not used; pass NULL
  *
- * Called by omap_hwmod_late_init() (after omap2_clk_init()).
- * Resolves all clock names embedded in the hwmod.  Must be called
- * with omap_hwmod_mutex held.  Returns -EINVAL if the omap_hwmod
- * has not yet been registered or if the clocks have already been
- * initialized, 0 on success, or a non-zero error on failure.
+ * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
+ * Resolves all clock names embedded in the hwmod.  Returns 0 on
+ * success, or a negative error code on failure.
  */
 static int _init_clocks(struct omap_hwmod *oh, void *data)
 {
         int ret = 0;
 
-        if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED))
-                return -EINVAL;
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
+                return 0;
 
         pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
 
@@ -788,7 +929,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
         if (!ret)
                 oh->_state = _HWMOD_STATE_CLKS_INITED;
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -834,68 +975,252 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
- * _reset - reset an omap_hwmod
+ * _lookup_hardreset - fill register bit info for this hwmod/reset line
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line in the context of this hwmod
+ * @ohri: struct omap_hwmod_rst_info * that this function will fill in
+ *
+ * Return the bit position of the reset line that match the
+ * input name. Return -ENOENT if not found.
+ */
+static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+                            struct omap_hwmod_rst_info *ohri)
+{
+        int i;
+
+        for (i = 0; i < oh->rst_lines_cnt; i++) {
+                const char *rst_line = oh->rst_lines[i].name;
+                if (!strcmp(rst_line, name)) {
+                        ohri->rst_shift = oh->rst_lines[i].rst_shift;
+                        ohri->st_shift = oh->rst_lines[i].st_shift;
+                        pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
+                                 oh->name, __func__, rst_line, ohri->rst_shift,
+                                 ohri->st_shift);
+
+                        return 0;
+                }
+        }
+
+        return -ENOENT;
+}
+
+/**
+ * _assert_hardreset - assert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to lookup and assert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.
+ */
+static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        struct omap_hwmod_rst_info ohri;
+        u8 ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        ret = _lookup_hardreset(oh, name, &ohri);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+                                                  ohri.rst_shift);
+        else if (cpu_is_omap44xx())
+                return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
+                                                  ohri.rst_shift);
+        else
+                return -EINVAL;
+}
+
+/**
+ * _deassert_hardreset - deassert the HW reset line of submodules contained
+ * in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and deassert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.
+ */
+static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        struct omap_hwmod_rst_info ohri;
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        ret = _lookup_hardreset(oh, name, &ohri);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+                                                   ohri.rst_shift,
+                                                   ohri.st_shift);
+        } else if (cpu_is_omap44xx()) {
+                if (ohri.st_shift)
+                        pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+                               oh->name, name);
+                ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
+                                                   ohri.rst_shift);
+        } else {
+                return -EINVAL;
+        }
+
+        if (ret == -EBUSY)
+                pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+
+        return ret;
+}
+
+/**
+ * _read_hardreset - read the HW reset line state of submodules
+ * contained in the hwmod module
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and read
+ *
+ * Return the state of the reset line.
+ */
+static int _read_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        struct omap_hwmod_rst_info ohri;
+        u8 ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        ret = _lookup_hardreset(oh, name, &ohri);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+                                                       ohri.st_shift);
+        } else if (cpu_is_omap44xx()) {
+                return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
+                                                       ohri.rst_shift);
+        } else {
+                return -EINVAL;
+        }
+}
+
+/**
+ * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
  * @oh: struct omap_hwmod *
  *
  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
- * enabled for this to work.  Must be called with omap_hwmod_mutex
- * held.  Returns -EINVAL if the hwmod cannot be reset this way or if
- * the hwmod is in the wrong state, -ETIMEDOUT if the module did not
- * reset in time, or 0 upon success.
+ * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
+ * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * the module did not reset in time, or 0 upon success.
+ *
+ * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
+ * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
+ * use the SYSCONFIG softreset bit to provide the status.
+ *
+ * Note that some IP like McBSP do have reset control but don't have
+ * reset status.
  */
-static int _reset(struct omap_hwmod *oh)
+static int _ocp_softreset(struct omap_hwmod *oh)
 {
-        u32 r, v;
+        u32 v;
         int c = 0;
+        int ret = 0;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) ||
-            (oh->class->sysc->sysc_flags & SYSS_MISSING))
+            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
                 return -EINVAL;
 
         /* clocks must be on for this operation */
         if (oh->_state != _HWMOD_STATE_ENABLED) {
-                WARN(1, "omap_hwmod: %s: reset can only be entered from "
-                     "enabled state\n", oh->name);
+                pr_warning("omap_hwmod: %s: reset can only be entered from "
+                           "enabled state\n", oh->name);
                 return -EINVAL;
         }
 
-        pr_debug("omap_hwmod: %s: resetting\n", oh->name);
+        /* For some modules, all optionnal clocks need to be enabled as well */
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _enable_optional_clocks(oh);
+
+        pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
 
         v = oh->_sysc_cache;
-        r = _set_softreset(oh, &v);
-        if (r)
-                return r;
+        ret = _set_softreset(oh, &v);
+        if (ret)
+                goto dis_opt_clks;
         _write_sysconfig(v, oh);
 
-        omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) &
-                           SYSS_RESETDONE_MASK),
-                          MAX_MODULE_RESET_WAIT, c);
-
-        if (c == MAX_MODULE_RESET_WAIT)
-                WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
-                     oh->name, MAX_MODULE_RESET_WAIT);
+        if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
+                omap_test_timeout((omap_hwmod_read(oh,
+                                                    oh->class->sysc->syss_offs)
+                                   & SYSS_RESETDONE_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+        else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
+                omap_test_timeout(!(omap_hwmod_read(oh,
+                                                     oh->class->sysc->sysc_offs)
+                                   & SYSC_TYPE2_SOFTRESET_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
+                           oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
-                pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c);
+                pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
 
         /*
          * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
          * _wait_target_ready() or _reset()
          */
 
-        return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0;
+        ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+
+dis_opt_clks:
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _disable_optional_clocks(oh);
+
+        return ret;
 }
 
 /**
- * _omap_hwmod_enable - enable an omap_hwmod
+ * _reset - reset an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Resets an omap_hwmod @oh.  The default software reset mechanism for
+ * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
+ * bit.  However, some hwmods cannot be reset via this method: some
+ * are not targets and therefore have no OCP header registers to
+ * access; others (like the IVA) have idiosyncratic reset sequences.
+ * So for these relatively rare cases, custom reset code can be
+ * supplied in the struct omap_hwmod_class .reset function pointer.
+ * Passes along the return value from either _reset() or the custom
+ * reset function - these must return -EINVAL if the hwmod cannot be
+ * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * the module did not reset in time, or 0 upon success.
+ */
+static int _reset(struct omap_hwmod *oh)
+{
+        int ret;
+
+        pr_debug("omap_hwmod: %s: resetting\n", oh->name);
+
+        ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
+
+        return ret;
+}
+
+/**
+ * _enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
- * register target.  Must be called with omap_hwmod_mutex held.
- * Returns -EINVAL if the hwmod is in the wrong state or passes along
- * the return value of _wait_target_ready().
+ * register target.  Returns -EINVAL if the hwmod is in the wrong
+ * state or passes along the return value of _wait_target_ready().
  */
-int _omap_hwmod_enable(struct omap_hwmod *oh)
+static int _enable(struct omap_hwmod *oh)
 {
         int r;
 
@@ -909,7 +1234,20 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
-        /* XXX mux balls */
+        /*
+         * If an IP contains only one HW reset line, then de-assert it in order
+         * to allow to enable the clocks. Otherwise the PRCM will return
+         * Intransition status, and the init will failed.
+         */
+        if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+             oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+                _deassert_hardreset(oh, oh->rst_lines[0].name);
+
+        /* Mux pins for device runtime if populated */
+        if (oh->mux && (!oh->mux->enabled ||
+                        ((oh->_state == _HWMOD_STATE_IDLE) &&
+                         oh->mux->pads_dynamic)))
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
 
         _add_initiator_dep(oh, mpu_oh);
         _enable_clocks(oh);
@@ -922,9 +1260,10 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
                 if (oh->class->sysc) {
                         if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
                                 _update_sysc_cache(oh);
-                        _sysc_enable(oh);
+                        _enable_sysc(oh);
                 }
         } else {
+                _disable_clocks(oh);
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
                          oh->name, r);
         }
@@ -940,7 +1279,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
  * no further work.  Returns -EINVAL if the hwmod is in the wrong
  * state or returns 0.
  */
-int _omap_hwmod_idle(struct omap_hwmod *oh)
+static int _idle(struct omap_hwmod *oh)
 {
         if (oh->_state != _HWMOD_STATE_ENABLED) {
                 WARN(1, "omap_hwmod: %s: idle state can only be entered from "
@@ -951,16 +1290,56 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
         pr_debug("omap_hwmod: %s: idling\n", oh->name);
 
         if (oh->class->sysc)
-                _sysc_idle(oh);
+                _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
         _disable_clocks(oh);
 
+        /* Mux pins for device idle if populated */
+        if (oh->mux && oh->mux->pads_dynamic)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+
         oh->_state = _HWMOD_STATE_IDLE;
 
         return 0;
 }
 
 /**
+ * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
+ * @oh: struct omap_hwmod *
+ * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ *
+ * Sets the IP block's OCP autoidle bit in hardware, and updates our
+ * local copy. Intended to be used by drivers that require
+ * direct manipulation of the AUTOIDLE bits.
+ * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
+ * along the return value from _set_module_autoidle().
+ *
+ * Any users of this function should be scrutinized carefully.
+ */
+int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
+{
+        u32 v;
+        int retval = 0;
+        unsigned long flags;
+
+        if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+
+        v = oh->_sysc_cache;
+
+        retval = _set_module_autoidle(oh, autoidle, &v);
+
+        if (!retval)
+                _write_sysconfig(v, oh);
+
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return retval;
+}
+
+/**
  * _shutdown - shutdown an omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -971,6 +1350,9 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
  */
 static int _shutdown(struct omap_hwmod *oh)
 {
+        int ret;
+        u8 prev_state;
+
         if (oh->_state != _HWMOD_STATE_IDLE &&
             oh->_state != _HWMOD_STATE_ENABLED) {
                 WARN(1, "omap_hwmod: %s: disabled state can only be entered "
@@ -980,14 +1362,39 @@ static int _shutdown(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
 
+        if (oh->class->pre_shutdown) {
+                prev_state = oh->_state;
+                if (oh->_state == _HWMOD_STATE_IDLE)
+                        _enable(oh);
+                ret = oh->class->pre_shutdown(oh);
+                if (ret) {
+                        if (prev_state == _HWMOD_STATE_IDLE)
+                                _idle(oh);
+                        return ret;
+                }
+        }
+
         if (oh->class->sysc)
-                _sysc_shutdown(oh);
-        _del_initiator_dep(oh, mpu_oh);
-        /* XXX what about the other system initiators here? DMA, tesla, d2d */
-        _disable_clocks(oh);
+                _shutdown_sysc(oh);
+
+        /*
+         * If an IP contains only one HW reset line, then assert it
+         * before disabling the clocks and shutting down the IP.
+         */
+        if (oh->rst_lines_cnt == 1)
+                _assert_hardreset(oh, oh->rst_lines[0].name);
+
+        /* clocks and deps are already disabled in idle */
+        if (oh->_state == _HWMOD_STATE_ENABLED) {
+                _del_initiator_dep(oh, mpu_oh);
+                /* XXX what about the other system initiators here? dma, dsp */
+                _disable_clocks(oh);
+        }
         /* XXX Should this code also force-disable the optional clocks? */
 
-        /* XXX mux any associated balls to safe mode */
+        /* Mux pins to safe mode or use populated off mode values */
+        if (oh->mux)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
 
         oh->_state = _HWMOD_STATE_DISABLED;
 
@@ -997,24 +1404,17 @@ static int _shutdown(struct omap_hwmod *oh)
 /**
  * _setup - do initial configuration of omap_hwmod
  * @oh: struct omap_hwmod *
- * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Must be called with omap_hwmod_mutex held.
- * @skip_setup_idle is intended to be used on a system that will not
- * call omap_hwmod_enable() to enable devices (e.g., a system without
- * PM runtime).  Returns -EINVAL if the hwmod is in the wrong state or
- * returns 0.
+ * OCP_SYSCONFIG register.  Returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {
         int i, r;
-        u8 skip_setup_idle;
-
-        if (!oh || !data)
-                return -EINVAL;
+        u8 postsetup_state;
 
-        skip_setup_idle = *(u8 *)data;
+        if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+                return 0;
 
         /* Set iclk autoidle mode */
         if (oh->slaves_cnt > 0) {
@@ -1036,7 +1436,17 @@ static int _setup(struct omap_hwmod *oh, void *data)
 
         oh->_state = _HWMOD_STATE_INITIALIZED;
 
-        r = _omap_hwmod_enable(oh);
+        /*
+         * In the case of hwmod with hardreset that should not be
+         * de-assert at boot time, we have to keep the module
+         * initialized, because we cannot enable it properly with the
+         * reset asserted. Exit without warning because that behavior is
+         * expected.
+         */
+        if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
+                return 0;
+
+        r = _enable(oh);
         if (r) {
                 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
                            oh->name, oh->_state);
@@ -1044,37 +1454,111 @@ static int _setup(struct omap_hwmod *oh, void *data)
         }
 
         if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+                _reset(oh);
+
                 /*
-                 * XXX Do the OCP_SYSCONFIG bits need to be
-                 * reprogrammed after a reset?  If not, then this can
-                 * be removed.  If they do, then probably the
-                 * _omap_hwmod_enable() function should be split to avoid the
-                 * rewrite of the OCP_SYSCONFIG register.
+                 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
+                 * The _enable() function should be split to
+                 * avoid the rewrite of the OCP_SYSCONFIG register.
                  */
                 if (oh->class->sysc) {
                         _update_sysc_cache(oh);
-                        _sysc_enable(oh);
+                        _enable_sysc(oh);
                 }
         }
 
-        if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle)
-                _omap_hwmod_idle(oh);
+        postsetup_state = oh->_postsetup_state;
+        if (postsetup_state == _HWMOD_STATE_UNKNOWN)
+                postsetup_state = _HWMOD_STATE_ENABLED;
+
+        /*
+         * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
+         * it should be set by the core code as a runtime flag during startup
+         */
+        if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
+            (postsetup_state == _HWMOD_STATE_IDLE))
+                postsetup_state = _HWMOD_STATE_ENABLED;
+
+        if (postsetup_state == _HWMOD_STATE_IDLE)
+                _idle(oh);
+        else if (postsetup_state == _HWMOD_STATE_DISABLED)
+                _shutdown(oh);
+        else if (postsetup_state != _HWMOD_STATE_ENABLED)
+                WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
+                     oh->name, postsetup_state);
 
         return 0;
 }
 
+/**
+ * _register - register a struct omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod
+ * already has been registered by the same name; -EINVAL if the
+ * omap_hwmod is in the wrong state, if @oh is NULL, if the
+ * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
+ * name, or if the omap_hwmod's class is missing a name; or 0 upon
+ * success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init.  This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
+ * that the copy process would be relatively complex due to the large number
+ * of substructures.
+ */
+static int __init _register(struct omap_hwmod *oh)
+{
+        int ms_id;
+
+        if (!oh || !oh->name || !oh->class || !oh->class->name ||
+            (oh->_state != _HWMOD_STATE_UNKNOWN))
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: registering\n", oh->name);
+
+        if (_lookup(oh->name))
+                return -EEXIST;
+
+        ms_id = _find_mpu_port_index(oh);
+        if (!IS_ERR_VALUE(ms_id))
+                oh->_mpu_port_index = ms_id;
+        else
+                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+
+        list_add_tail(&oh->node, &omap_hwmod_list);
+
+        spin_lock_init(&oh->_lock);
+
+        oh->_state = _HWMOD_STATE_REGISTERED;
+
+        /*
+         * XXX Rather than doing a strcmp(), this should test a flag
+         * set in the hwmod data, inserted by the autogenerator code.
+         */
+        if (!strcmp(oh->name, MPU_INITIATOR_NAME))
+                mpu_oh = oh;
+
+        return 0;
+}
 
 
 /* Public functions */
 
-u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs)
+u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
 {
-        return __raw_readl(oh->_mpu_rt_va + reg_offs);
+        if (oh->flags & HWMOD_16BIT_REG)
+                return __raw_readw(oh->_mpu_rt_va + reg_offs);
+        else
+                return __raw_readl(oh->_mpu_rt_va + reg_offs);
 }
 
-void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
+void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 {
-        __raw_writel(v, oh->_mpu_rt_va + reg_offs);
+        if (oh->flags & HWMOD_16BIT_REG)
+                __raw_writew(v, oh->_mpu_rt_va + reg_offs);
+        else
+                __raw_writel(v, oh->_mpu_rt_va + reg_offs);
 }
 
 /**
@@ -1110,59 +1594,6 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
 }
 
 /**
- * omap_hwmod_register - register a struct omap_hwmod
- * @oh: struct omap_hwmod *
- *
- * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod
- * already has been registered by the same name; -EINVAL if the
- * omap_hwmod is in the wrong state, if @oh is NULL, if the
- * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
- * name, or if the omap_hwmod's class is missing a name; or 0 upon
- * success.
- *
- * XXX The data should be copied into bootmem, so the original data
- * should be marked __initdata and freed after init.  This would allow
- * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
- * that the copy process would be relatively complex due to the large number
- * of substructures.
- */
-int omap_hwmod_register(struct omap_hwmod *oh)
-{
-        int ret, ms_id;
-
-        if (!oh || !oh->name || !oh->class || !oh->class->name ||
-            (oh->_state != _HWMOD_STATE_UNKNOWN))
-                return -EINVAL;
-
-        mutex_lock(&omap_hwmod_mutex);
-
-        pr_debug("omap_hwmod: %s: registering\n", oh->name);
-
-        if (_lookup(oh->name)) {
-                ret = -EEXIST;
-                goto ohr_unlock;
-        }
-
-        ms_id = _find_mpu_port_index(oh);
-        if (!IS_ERR_VALUE(ms_id)) {
-                oh->_mpu_port_index = ms_id;
-                oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-        } else {
-                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
-        }
-
-        list_add_tail(&oh->node, &omap_hwmod_list);
-
-        oh->_state = _HWMOD_STATE_REGISTERED;
-
-        ret = 0;
-
-ohr_unlock:
-        mutex_unlock(&omap_hwmod_mutex);
-        return ret;
-}
-
-/**
  * omap_hwmod_lookup - look up a registered omap_hwmod by name
  * @name: name of the omap_hwmod to look up
  *
@@ -1176,9 +1607,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name)
         if (!name)
                 return NULL;
 
-        mutex_lock(&omap_hwmod_mutex);
         oh = _lookup(name);
-        mutex_unlock(&omap_hwmod_mutex);
 
         return oh;
 }
@@ -1199,149 +1628,186 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                         void *data)
 {
         struct omap_hwmod *temp_oh;
-        int ret;
+        int ret = 0;
 
         if (!fn)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
         list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
                 ret = (*fn)(temp_oh, data);
                 if (ret)
                         break;
         }
-        mutex_unlock(&omap_hwmod_mutex);
 
         return ret;
 }
 
-
 /**
- * omap_hwmod_init - init omap_hwmod code and register hwmods
+ * omap_hwmod_register - register an array of hwmods
  * @ohs: pointer to an array of omap_hwmods to register
  *
  * Intended to be called early in boot before the clock framework is
  * initialized.  If @ohs is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip.  Returns -EINVAL if
- * omap_hwmod_init() has already been called or 0 otherwise.
+ * listed in @ohs that are valid for this chip.  Returns 0.
  */
-int omap_hwmod_init(struct omap_hwmod **ohs)
+int __init omap_hwmod_register(struct omap_hwmod **ohs)
 {
-        struct omap_hwmod *oh;
-        int r;
+        int r, i;
 
-        if (inited)
-                return -EINVAL;
+        if (!ohs)
+                return 0;
 
-        inited = 1;
+        i = 0;
+        do {
+                if (!omap_chip_is(ohs[i]->omap_chip))
+                        continue;
 
-        if (!ohs)
+                r = _register(ohs[i]);
+                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
+                     r);
+        } while (ohs[++i]);
+
+        return 0;
+}
+
+/*
+ * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ *
+ * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
+ * Assumes the caller takes care of locking if needed.
+ */
+static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+{
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
                 return 0;
 
-        oh = *ohs;
-        while (oh) {
-                if (omap_chip_is(oh->omap_chip)) {
-                        r = omap_hwmod_register(oh);
-                        WARN(r, "omap_hwmod: %s: omap_hwmod_register returned "
-                             "%d\n", oh->name, r);
-                }
-                oh = *++ohs;
-        }
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+        if (!oh->_mpu_rt_va)
+                pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
+                                __func__, oh->name);
 
         return 0;
 }
 
 /**
- * omap_hwmod_late_init - do some post-clock framework initialization
- * @skip_setup_idle: if 1, do not idle hwmods in _setup()
+ * omap_hwmod_setup_one - set up a single hwmod
+ * @oh_name: const char * name of the already-registered hwmod to set up
  *
- * Must be called after omap2_clk_init().  Resolves the struct clk names
- * to struct clk pointers for each registered omap_hwmod.  Also calls
- * _setup() on each hwmod.  Returns 0.
+ * Must be called after omap2_clk_init().  Resolves the struct clk
+ * names to struct clk pointers for each registered omap_hwmod.  Also
+ * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
+ * success.
  */
-int omap_hwmod_late_init(u8 skip_setup_idle)
+int __init omap_hwmod_setup_one(const char *oh_name)
 {
+        struct omap_hwmod *oh;
         int r;
 
-        /* XXX check return value */
-        r = omap_hwmod_for_each(_init_clocks, NULL);
-        WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
+        pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
 
-        mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
-        WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
-             MPU_INITIATOR_NAME);
+        if (!mpu_oh) {
+                pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
+                       oh_name, MPU_INITIATOR_NAME);
+                return -EINVAL;
+        }
 
-        if (skip_setup_idle)
-                pr_debug("omap_hwmod: will leave hwmods enabled during setup\n");
+        oh = _lookup(oh_name);
+        if (!oh) {
+                WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
+                return -EINVAL;
+        }
 
-        omap_hwmod_for_each(_setup, &skip_setup_idle);
+        if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
+
+        r = _populate_mpu_rt_base(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
+                return -EINVAL;
+        }
+
+        r = _init_clocks(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
+                return -EINVAL;
+        }
+
+        _setup(oh, NULL);
 
         return 0;
 }
 
 /**
- * omap_hwmod_unregister - unregister an omap_hwmod
- * @oh: struct omap_hwmod *
+ * omap_hwmod_setup - do some post-clock framework initialization
  *
- * Unregisters a previously-registered omap_hwmod @oh.  There's probably
- * no use case for this, so it is likely to be removed in a later version.
- *
- * XXX Free all of the bootmem-allocated structures here when that is
- * implemented.  Make it clear that core code is the only code that is
- * expected to unregister modules.
+ * Must be called after omap2_clk_init().  Resolves the struct clk names
+ * to struct clk pointers for each registered omap_hwmod.  Also calls
+ * _setup() on each hwmod.  Returns 0 upon success.
  */
-int omap_hwmod_unregister(struct omap_hwmod *oh)
+static int __init omap_hwmod_setup_all(void)
 {
-        if (!oh)
+        int r;
+
+        if (!mpu_oh) {
+                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+                       __func__, MPU_INITIATOR_NAME);
                 return -EINVAL;
+        }
+
+        r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
 
-        pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
+        r = omap_hwmod_for_each(_init_clocks, NULL);
+        WARN(IS_ERR_VALUE(r),
+             "omap_hwmod: %s: _init_clocks failed\n", __func__);
 
-        mutex_lock(&omap_hwmod_mutex);
-        iounmap(oh->_mpu_rt_va);
-        list_del(&oh->node);
-        mutex_unlock(&omap_hwmod_mutex);
+        omap_hwmod_for_each(_setup, NULL);
 
         return 0;
 }
+core_initcall(omap_hwmod_setup_all);
 
 /**
  * omap_hwmod_enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Enable an omap_hwomd @oh.  Intended to be called by omap_device_enable().
+ * Enable an omap_hwmod @oh.  Intended to be called by omap_device_enable().
  * Returns -EINVAL on error or passes along the return value from _enable().
  */
 int omap_hwmod_enable(struct omap_hwmod *oh)
 {
         int r;
+        unsigned long flags;
 
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
-        r = _omap_hwmod_enable(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        r = _enable(oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return r;
 }
 
-
 /**
  * omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Idle an omap_hwomd @oh.  Intended to be called by omap_device_idle().
+ * Idle an omap_hwmod @oh.  Intended to be called by omap_device_idle().
  * Returns -EINVAL on error or passes along the return value from _idle().
  */
 int omap_hwmod_idle(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
-        _omap_hwmod_idle(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        _idle(oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1350,18 +1816,20 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
  * omap_hwmod_shutdown - shutdown an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Shutdown an omap_hwomd @oh.  Intended to be called by
+ * Shutdown an omap_hwmod @oh.  Intended to be called by
  * omap_device_shutdown().  Returns -EINVAL on error or passes along
  * the return value from _shutdown().
  */
 int omap_hwmod_shutdown(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         _shutdown(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1374,9 +1842,11 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
  */
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&omap_hwmod_mutex);
+        unsigned long flags;
+
+        spin_lock_irqsave(&oh->_lock, flags);
         _enable_clocks(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1389,9 +1859,11 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
  */
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&omap_hwmod_mutex);
+        unsigned long flags;
+
+        spin_lock_irqsave(&oh->_lock, flags);
         _disable_clocks(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1421,7 +1893,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
          * Forces posted writes to complete on the OCP thread handling
          * register writes
          */
-        omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
+        omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
 }
 
 /**
@@ -1430,20 +1902,19 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
  *
  * Under some conditions, a driver may wish to reset the entire device.
  * Called from omap_device code.  Returns -EINVAL on error or passes along
- * the return value from _reset()/_enable().
+ * the return value from _reset().
  */
 int omap_hwmod_reset(struct omap_hwmod *oh)
 {
         int r;
+        unsigned long flags;
 
-        if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED))
+        if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         r = _reset(oh);
-        if (!r)
-                r = _omap_hwmod_enable(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return r;
 }
@@ -1468,7 +1939,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
         int ret, i;
 
-        ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt;
+        ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
 
         for (i = 0; i < oh->slaves_cnt; i++)
                 ret += oh->slaves[i]->addr_cnt;
@@ -1501,10 +1972,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 r++;
         }
 
-        for (i = 0; i < oh->sdma_chs_cnt; i++) {
-                (res + r)->name = (oh->sdma_chs + i)->name;
-                (res + r)->start = (oh->sdma_chs + i)->dma_ch;
-                (res + r)->end = (oh->sdma_chs + i)->dma_ch;
+        for (i = 0; i < oh->sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
                 (res + r)->flags = IORESOURCE_DMA;
                 r++;
         }
@@ -1515,6 +1986,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 os = oh->slaves[i];
 
                 for (j = 0; j < os->addr_cnt; j++) {
+                        (res + r)->name = (os->addr + j)->name;
                         (res + r)->start = (os->addr + j)->pa_start;
                         (res + r)->end = (os->addr + j)->pa_end;
                         (res + r)->flags = IORESOURCE_MEM;
@@ -1640,13 +2112,18 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
  */
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+        u32 v;
+
         if (!oh->class->sysc ||
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
-        _enable_wakeup(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        v = oh->_sysc_cache;
+        _enable_wakeup(oh, &v);
+        _write_sysconfig(v, oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1665,26 +2142,111 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
  */
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+        u32 v;
+
         if (!oh->class->sysc ||
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
-        _disable_wakeup(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        v = oh->_sysc_cache;
+        _disable_wakeup(oh, &v);
+        _write_sysconfig(v, oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
 
 /**
+ * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to lookup and assert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ * yet supported on this OMAP; otherwise, passes along the return value
+ * from _assert_hardreset().
+ */
+int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+        unsigned long flags;
+
+        if (!oh)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+        ret = _assert_hardreset(oh, name);
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and deassert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ * yet supported on this OMAP; otherwise, passes along the return value
+ * from _deassert_hardreset().
+ */
+int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+        unsigned long flags;
+
+        if (!oh)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+        ret = _deassert_hardreset(oh, name);
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_read_hardreset - read the HW reset line state of submodules
+ * contained in the hwmod module
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and read
+ *
+ * Return the current state of the hwmod @oh's reset line named @name:
+ * returns -EINVAL upon parameter error or if this operation
+ * is unsupported on the current OMAP; otherwise, passes along the return
+ * value from _read_hardreset().
+ */
+int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+        unsigned long flags;
+
+        if (!oh)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+        ret = _read_hardreset(oh, name);
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return ret;
+}
+
+
+/**
  * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
  * @classname: struct omap_hwmod_class name to search for
  * @fn: callback function pointer to call for each hwmod in class @classname
  * @user: arbitrary context data to pass to the callback function
  *
- * For each omap_hwmod of class @classname, call @fn.  Takes
- * omap_hwmod_mutex to prevent the hwmod list from changing during the
- * iteration.  If the callback function returns something other than
+ * For each omap_hwmod of class @classname, call @fn.
+ * If the callback function returns something other than
  * zero, the iterator is terminated, and the callback function's return
  * value is passed back to the caller.  Returns 0 upon success, -EINVAL
  * if @classname or @fn are NULL, or passes back the error code from @fn.
@@ -1703,8 +2265,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
         pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
                  __func__, classname);
 
-        mutex_lock(&omap_hwmod_mutex);
-
         list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
                 if (!strcmp(temp_oh->class->name, classname)) {
                         pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
@@ -1715,8 +2275,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
                 }
         }
 
-        mutex_unlock(&omap_hwmod_mutex);
-
         if (ret)
                 pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
                          __func__, ret);
@@ -1724,3 +2282,90 @@ int omap_hwmod_for_each_by_class(const char *classname,
         return ret;
 }
 
+/**
+ * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
+ * @oh: struct omap_hwmod *
+ * @state: state that _setup() should leave the hwmod in
+ *
+ * Sets the hwmod state that @oh will enter at the end of _setup()
+ * (called by omap_hwmod_setup_*()).  Only valid to call between
+ * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
+ * 0 upon success or -EINVAL if there is a problem with the arguments
+ * or if the hwmod is in the wrong state.
+ */
+int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
+{
+        int ret;
+        unsigned long flags;
+
+        if (!oh)
+                return -EINVAL;
+
+        if (state != _HWMOD_STATE_DISABLED &&
+            state != _HWMOD_STATE_ENABLED &&
+            state != _HWMOD_STATE_IDLE)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+
+        if (oh->_state != _HWMOD_STATE_REGISTERED) {
+                ret = -EINVAL;
+                goto ohsps_unlock;
+        }
+
+        oh->_postsetup_state = state;
+        ret = 0;
+
+ohsps_unlock:
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_get_context_loss_count - get lost context count
+ * @oh: struct omap_hwmod *
+ *
+ * Query the powerdomain of of @oh to get the context loss
+ * count for this device.
+ *
+ * Returns the context loss count of the powerdomain assocated with @oh
+ * upon success, or zero if no powerdomain exists for @oh.
+ */
+u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
+{
+        struct powerdomain *pwrdm;
+        int ret = 0;
+
+        pwrdm = omap_hwmod_get_pwrdm(oh);
+        if (pwrdm)
+                ret = pwrdm_get_context_loss_count(pwrdm);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
+ * @oh: struct omap_hwmod *
+ *
+ * Prevent the hwmod @oh from being reset during the setup process.
+ * Intended for use by board-*.c files on boards with devices that
+ * cannot tolerate being reset.  Must be called before the hwmod has
+ * been set up.  Returns 0 upon success or negative error code upon
+ * failure.
+ */
+int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_state != _HWMOD_STATE_REGISTERED) {
+                pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
+                        oh->name);
+                return -EINVAL;
+        }
+
+        oh->flags |= HWMOD_INIT_NO_RESET;
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e8bc04..c4d0ae87d62a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,10 +15,19 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
+#include <plat/mcspi.h>
+#include <plat/dmtimer.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
 
+#include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
+#include "wd_timer.h"
 
 /*
  * OMAP2420 hardware module integration data
@@ -33,6 +42,18 @@ static struct omap_hwmod omap2420_mpu_hwmod;
 static struct omap_hwmod omap2420_iva_hwmod;
 static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
+static struct omap_hwmod omap2420_dss_core_hwmod;
+static struct omap_hwmod omap2420_dss_dispc_hwmod;
+static struct omap_hwmod omap2420_dss_rfbi_hwmod;
+static struct omap_hwmod omap2420_dss_venc_hwmod;
+static struct omap_hwmod omap2420_wd_timer2_hwmod;
+static struct omap_hwmod omap2420_gpio1_hwmod;
+static struct omap_hwmod omap2420_gpio2_hwmod;
+static struct omap_hwmod omap2420_gpio3_hwmod;
+static struct omap_hwmod omap2420_gpio4_hwmod;
+static struct omap_hwmod omap2420_dma_system_hwmod;
+static struct omap_hwmod omap2420_mcspi1_hwmod;
+static struct omap_hwmod omap2420_mcspi2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -53,6 +74,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
         &omap2420_mpu__l3_main,
 };
 
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
+        .master         = &omap2420_dss_core_hwmod,
+        .slave          = &omap2420_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Master interfaces on the L3 interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
         &omap2420_l3_main__l4_core,
@@ -71,6 +105,49 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
+static struct omap_hwmod omap2420_uart1_hwmod;
+static struct omap_hwmod omap2420_uart2_hwmod;
+static struct omap_hwmod omap2420_uart3_hwmod;
+static struct omap_hwmod omap2420_i2c1_hwmod;
+static struct omap_hwmod omap2420_i2c2_hwmod;
+static struct omap_hwmod omap2420_mcbsp1_hwmod;
+static struct omap_hwmod omap2420_mcbsp2_hwmod;
+
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480980ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcspi1_hwmod,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2420_mcspi1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcspi1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcspi2_hwmod,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2420_mcspi2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcspi2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -79,6 +156,99 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2420_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2420_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2420_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN                128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2420_i2c1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_i2c1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2420_i2c2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_i2c2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
         &omap2420_l3_main__l4_core,
@@ -87,6 +257,11 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
         &omap2420_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
+        &omap2420_l4_core__i2c1,
+        &omap2420_l4_core__i2c2
 };
 
 /* L4 CORE */
@@ -165,18 +340,1862 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap2420_timer_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2420_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48028000,
+                .pa_end         = 0x48028000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2420_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+        &omap2420_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2420_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2420_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2420_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2420_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+        &omap2420_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2420_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2420_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2420_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2420_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
+        &omap2420_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2420_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2420_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2420_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2420_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+        &omap2420_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2420_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2420_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2420_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2420_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+        &omap2420_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2420_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2420_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+
+/* timer6 */
+static struct omap_hwmod omap2420_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2420_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
+        &omap2420_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2420_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2420_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2420_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2420_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
+        &omap2420_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2420_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2420_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2420_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2420_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+        &omap2420_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2420_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2420_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2420_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2420_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
+        &omap2420_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2420_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2420_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2420_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2420_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+        &omap2420_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2420_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2420_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2420_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2420_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+        &omap2420_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2420_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2420_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2420_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2420_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
+        &omap2420_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2420_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2420_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48022000,
+                .pa_end         = 0x4802207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2420_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap2420_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
+        &omap2420_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap2420_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2420_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+        .slaves         = omap2420_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+        &omap2_l4_core__uart1,
+};
+
+static struct omap_hwmod omap2420_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+        &omap2_l4_core__uart2,
+};
+
+static struct omap_hwmod omap2420_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+        &omap2_l4_core__uart3,
+};
+
+static struct omap_hwmod omap2420_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_dss_hwmod_class = {
+        .name = "dss",
+        .sysc = &omap2420_dss_sysc,
+};
+
+static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
+        &omap2420_dss__l3,
+};
+
+static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x480503FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2420_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
+        &omap2420_l4_core__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "tv_clk", .clk = "dss_54m_fck" },
+        { .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+static struct omap_hwmod omap2420_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2420_dss_hwmod_class,
+        .main_clk       = "dss1_fck", /* instead of dss_fck */
+        .sdma_reqs      = omap2420_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap2420_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
+        .masters        = omap2420_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
+        .name = "dispc",
+        .sysc = &omap2420_dispc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
+        { .irq = 25 },
+};
+
+static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x480507FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2420_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_dispc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
+        &omap2420_l4_core__dss_dispc,
+};
+
+static struct omap_hwmod omap2420_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap2420_dispc_hwmod_class,
+        .mpu_irqs       = omap2420_dispc_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dispc_irqs),
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
+        .name = "rfbi",
+        .sysc = &omap2420_rfbi_sysc,
+};
+
+static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050BFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2420_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
+        &omap2420_l4_core__dss_rfbi,
+};
+
+static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2420_rfbi_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2420_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap2420_venc_hwmod_class = {
+        .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050FFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_venc_hwmod,
+        .clk            = "dss_54m_fck",
+        .addr           = omap2420_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_venc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
+        &omap2420_l4_core__dss_venc,
+};
+
+static struct omap_hwmod omap2420_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap2420_venc_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2420_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+        &omap2420_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
+        .sdma_reqs      = i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .main_clk       = "i2c1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_16BIT_REG,
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+        &omap2420_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
+        .sdma_reqs      = i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .main_clk       = "i2c2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_16BIT_REG,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
+        {
+                .pa_start       = 0x48018000,
+                .pa_end         = 0x480181ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio1_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
+        {
+                .pa_start       = 0x4801a000,
+                .pa_end         = 0x4801a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio2_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
+        {
+                .pa_start       = 0x4801c000,
+                .pa_end         = 0x4801c1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio3_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
+        {
+                .pa_start       = 0x4801e000,
+                .pa_end         = 0x4801e1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio4_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = false,
+};
+
+static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap242x_gpio_sysc,
+        .rev = 0,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+        &omap2420_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap2420_gpio1_hwmod = {
+        .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap242x_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
+        &omap2420_l4_wkup__gpio2,
+};
+
+static struct omap_hwmod omap2420_gpio2_hwmod = {
+        .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap242x_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
+        &omap2420_l4_wkup__gpio3,
+};
+
+static struct omap_hwmod omap2420_gpio3_hwmod = {
+        .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap242x_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
+        &omap2420_l4_wkup__gpio4,
+};
+
+static struct omap_hwmod omap2420_gpio4_hwmod = {
+        .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap242x_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* system dma */
+static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap2420_dma_sysc,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                                IS_CSSA_32 | IS_CDSA_32,
+        .lch_count = 32,
+};
+
+static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+
+static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x48056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
+        .master         = &omap2420_dma_system_hwmod,
+        .slave          = &omap2420_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
+        &omap2420_dma_system__l3,
+};
+
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2420_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
+        &omap2420_l4_core__dma_system,
+};
+
+static struct omap_hwmod omap2420_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2420_dma_hwmod_class,
+        .mpu_irqs       = omap2420_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
+        .main_clk       = "core_l3_ck",
+        .slaves         = omap2420_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
+        .masters        = omap2420_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap2420_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2420_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+        { .name = "dsp", .irq = 26 },
+        { .name = "iva", .irq = 34 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mailbox_hwmod,
+        .addr           = omap2420_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+        &omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap2420_mailbox_hwmod_class,
+        .mpu_irqs       = omap2420_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mcspi_class = {
+        .name = "mcspi",
+        .sysc = &omap2420_mcspi_sysc,
+        .rev = OMAP2_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
+        { .irq = 65 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
+        &omap2420_l4_core__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap2420_mcspi1_hwmod = {
+        .name           = "mcspi1_hwmod",
+        .mpu_irqs       = omap2420_mcspi1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
+        .sdma_reqs      = omap2420_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
+        .class          = &omap2420_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
+        { .irq = 66 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
+        &omap2420_l4_core__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap2420_mcspi2_hwmod = {
+        .name           = "mcspi2_hwmod",
+        .mpu_irqs       = omap2420_mcspi2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
+        .sdma_reqs      = omap2420_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
+        .class          = &omap2420_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+        { .name = "tx", .irq = 59 },
+        { .name = "rx", .irq = 60 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2420_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
+        &omap2420_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap2420_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2420_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp1_irqs),
+        .sdma_reqs      = omap2420_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+        { .name = "tx", .irq = 62 },
+        { .name = "rx", .irq = 63 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480760ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2420_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
+        &omap2420_l4_core__mcbsp2,
+};
+
+static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap2420_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2420_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp2_irqs),
+        .sdma_reqs      = omap2420_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_l3_main_hwmod,
         &omap2420_l4_core_hwmod,
         &omap2420_l4_wkup_hwmod,
         &omap2420_mpu_hwmod,
         &omap2420_iva_hwmod,
+
+        &omap2420_timer1_hwmod,
+        &omap2420_timer2_hwmod,
+        &omap2420_timer3_hwmod,
+        &omap2420_timer4_hwmod,
+        &omap2420_timer5_hwmod,
+        &omap2420_timer6_hwmod,
+        &omap2420_timer7_hwmod,
+        &omap2420_timer8_hwmod,
+        &omap2420_timer9_hwmod,
+        &omap2420_timer10_hwmod,
+        &omap2420_timer11_hwmod,
+        &omap2420_timer12_hwmod,
+
+        &omap2420_wd_timer2_hwmod,
+        &omap2420_uart1_hwmod,
+        &omap2420_uart2_hwmod,
+        &omap2420_uart3_hwmod,
+        /* dss class */
+        &omap2420_dss_core_hwmod,
+        &omap2420_dss_dispc_hwmod,
+        &omap2420_dss_rfbi_hwmod,
+        &omap2420_dss_venc_hwmod,
+        /* i2c class */
+        &omap2420_i2c1_hwmod,
+        &omap2420_i2c2_hwmod,
+
+        /* gpio class */
+        &omap2420_gpio1_hwmod,
+        &omap2420_gpio2_hwmod,
+        &omap2420_gpio3_hwmod,
+        &omap2420_gpio4_hwmod,
+
+        /* dma_system class*/
+        &omap2420_dma_system_hwmod,
+
+        /* mailbox class */
+        &omap2420_mailbox_hwmod,
+
+        /* mcbsp class */
+        &omap2420_mcbsp1_hwmod,
+        &omap2420_mcbsp2_hwmod,
+
+        /* mcspi class */
+        &omap2420_mcspi1_hwmod,
+        &omap2420_mcspi2_hwmod,
         NULL,
 };
 
 int __init omap2420_hwmod_init(void)
 {
-        return omap_hwmod_init(omap2420_hwmods);
+        return omap_hwmod_register(omap2420_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628ed287..9682dd519f8d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,10 +15,20 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
+#include <plat/mcbsp.h>
+#include <plat/mcspi.h>
+#include <plat/dmtimer.h>
+#include <plat/mmc.h>
+#include <plat/l3_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "wd_timer.h"
 
 /*
  * OMAP2430 hardware module integration data
@@ -33,6 +43,27 @@ static struct omap_hwmod omap2430_mpu_hwmod;
 static struct omap_hwmod omap2430_iva_hwmod;
 static struct omap_hwmod omap2430_l3_main_hwmod;
 static struct omap_hwmod omap2430_l4_core_hwmod;
+static struct omap_hwmod omap2430_dss_core_hwmod;
+static struct omap_hwmod omap2430_dss_dispc_hwmod;
+static struct omap_hwmod omap2430_dss_rfbi_hwmod;
+static struct omap_hwmod omap2430_dss_venc_hwmod;
+static struct omap_hwmod omap2430_wd_timer2_hwmod;
+static struct omap_hwmod omap2430_gpio1_hwmod;
+static struct omap_hwmod omap2430_gpio2_hwmod;
+static struct omap_hwmod omap2430_gpio3_hwmod;
+static struct omap_hwmod omap2430_gpio4_hwmod;
+static struct omap_hwmod omap2430_gpio5_hwmod;
+static struct omap_hwmod omap2430_dma_system_hwmod;
+static struct omap_hwmod omap2430_mcbsp1_hwmod;
+static struct omap_hwmod omap2430_mcbsp2_hwmod;
+static struct omap_hwmod omap2430_mcbsp3_hwmod;
+static struct omap_hwmod omap2430_mcbsp4_hwmod;
+static struct omap_hwmod omap2430_mcbsp5_hwmod;
+static struct omap_hwmod omap2430_mcspi1_hwmod;
+static struct omap_hwmod omap2430_mcspi2_hwmod;
+static struct omap_hwmod omap2430_mcspi3_hwmod;
+static struct omap_hwmod omap2430_mmc1_hwmod;
+static struct omap_hwmod omap2430_mmc2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -53,6 +84,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
         &omap2430_mpu__l3_main,
 };
 
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
+        .master         = &omap2430_dss_core_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Master interfaces on the L3 interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
         &omap2430_l3_main__l4_core,
@@ -71,6 +115,60 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_uart1_hwmod;
+static struct omap_hwmod omap2430_uart2_hwmod;
+static struct omap_hwmod omap2430_uart3_hwmod;
+static struct omap_hwmod omap2430_i2c1_hwmod;
+static struct omap_hwmod omap2430_i2c2_hwmod;
+
+static struct omap_hwmod omap2430_usbhsotg_hwmod;
+
+/* l3_core -> usbhsotg  interface */
+static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
+        .master         = &omap2430_usbhsotg_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU,
+};
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN                128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2430_i2c1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2430_i2c2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -79,6 +177,125 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2430_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2430_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2430_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+* usbhsotg interface data
+*/
+static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP243X_HS_BASE,
+                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/*  l4_core ->usbhsotg  interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_usbhsotg_hwmod,
+        .clk            = "usb_l4_ick",
+        .addr           = omap2430_usbhsotg_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
+        &omap2430_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
+        &omap2430_l4_core__usbhsotg,
+};
+
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mmc1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b41ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mmc2_hwmod,
+        .addr           = omap2430_mmc2_addr_space,
+        .clk            = "mmchs2_ick",
+        .addr_cnt       = ARRAY_SIZE(omap2430_mmc2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
         &omap2430_l3_main__l4_core,
@@ -87,6 +304,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
         &omap2430_l4_core__l4_wkup,
+        &omap2430_l4_core__mmc1,
+        &omap2430_l4_core__mmc2,
 };
 
 /* L4 CORE */
@@ -104,12 +323,69 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
 /* Slave interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
         &omap2430_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
 };
 
 /* Master interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 };
 
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480980ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcspi1_hwmod,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2430_mcspi1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcspi2_hwmod,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2430_mcspi2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b80ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcspi3_hwmod,
+        .clk            = "mcspi3_ick",
+        .addr           = omap2430_mcspi3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* L4 WKUP */
 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
         .name           = "l4_wkup",
@@ -165,18 +441,2301 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap2430_timer_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2430_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+        {
+                .pa_start       = 0x49018000,
+                .pa_end         = 0x49018000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2430_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+        &omap2430_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2430_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2430_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2430_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2430_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+        &omap2430_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2430_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2430_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2430_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2430_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
+        &omap2430_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2430_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2430_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2430_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2430_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
+        &omap2430_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2430_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2430_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2430_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2430_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
+        &omap2430_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2430_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2430_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap2430_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2430_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
+        &omap2430_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2430_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2430_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2430_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2430_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
+        &omap2430_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2430_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2430_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2430_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2430_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
+        &omap2430_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2430_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2430_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2430_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2430_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
+        &omap2430_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2430_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2430_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2430_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2430_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
+        &omap2430_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2430_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2430_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2430_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2430_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
+        &omap2430_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2430_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2430_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2430_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2430_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
+        &omap2430_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2430_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2430_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49016000,
+                .pa_end         = 0x4901607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2430_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap2430_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
+        &omap2430_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap2430_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2430_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+        .slaves         = omap2430_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+        &omap2_l4_core__uart1,
+};
+
+static struct omap_hwmod omap2430_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+        &omap2_l4_core__uart2,
+};
+
+static struct omap_hwmod omap2430_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+        &omap2_l4_core__uart3,
+};
+
+static struct omap_hwmod omap2430_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_dss_hwmod_class = {
+        .name = "dss",
+        .sysc = &omap2430_dss_sysc,
+};
+
+static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
+        &omap2430_dss__l3,
+};
+
+static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x480503FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2430_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
+        &omap2430_l4_core__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "tv_clk", .clk = "dss_54m_fck" },
+        { .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+static struct omap_hwmod omap2430_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2430_dss_hwmod_class,
+        .main_clk       = "dss1_fck", /* instead of dss_fck */
+        .sdma_reqs      = omap2430_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap2430_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
+        .masters        = omap2430_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
+        .name = "dispc",
+        .sysc = &omap2430_dispc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
+        { .irq = 25 },
+};
+
+static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x480507FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2430_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
+        &omap2430_l4_core__dss_dispc,
+};
+
+static struct omap_hwmod omap2430_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap2430_dispc_hwmod_class,
+        .mpu_irqs       = omap2430_dispc_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dispc_irqs),
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
+        .name = "rfbi",
+        .sysc = &omap2430_rfbi_sysc,
+};
+
+static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050BFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2430_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
+        &omap2430_l4_core__dss_rfbi,
+};
+
+static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2430_rfbi_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2430_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap2430_venc_hwmod_class = {
+        .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050FFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_venc_hwmod,
+        .clk            = "dss_54m_fck",
+        .addr           = omap2430_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
+        &omap2430_l4_core__dss_venc,
+};
+
+static struct omap_hwmod omap2430_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap2430_venc_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2430_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .fifo_depth     = 8, /* bytes */
+};
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+        &omap2430_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2430_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
+        .sdma_reqs      = i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .main_clk       = "i2chs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        /*
+                         * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
+                         * I2CHS IP's do not follow the usual pattern.
+                         * prcm_reg_id alone cannot be used to program
+                         * the iclk and fclk. Needs to be handled using
+                         * additional flags when clk handling is moved
+                         * to hwmod framework.
+                         */
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+        &omap2430_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2430_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
+        .sdma_reqs      = i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .main_clk       = "i2chs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+        {
+                .pa_start       = 0x4900C000,
+                .pa_end         = 0x4900C1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio1_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+        {
+                .pa_start       = 0x4900E000,
+                .pa_end         = 0x4900E1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio2_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+        {
+                .pa_start       = 0x49010000,
+                .pa_end         = 0x490101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio3_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+        {
+                .pa_start       = 0x49012000,
+                .pa_end         = 0x490121ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio4_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> gpio5 */
+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+        {
+                .pa_start       = 0x480B6000,
+                .pa_end         = 0x480B61ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_gpio5_hwmod,
+        .clk            = "gpio5_ick",
+        .addr           = omap2430_gpio5_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = false,
+};
+
+static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap243x_gpio_sysc,
+        .rev = 0,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+        &omap2430_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap2430_gpio1_hwmod = {
+        .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap243x_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
+        &omap2430_l4_wkup__gpio2,
+};
+
+static struct omap_hwmod omap2430_gpio2_hwmod = {
+        .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap243x_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
+        &omap2430_l4_wkup__gpio3,
+};
+
+static struct omap_hwmod omap2430_gpio3_hwmod = {
+        .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap243x_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
+        &omap2430_l4_wkup__gpio4,
+};
+
+static struct omap_hwmod omap2430_gpio4_hwmod = {
+        .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap243x_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
+        { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
+        &omap2430_l4_core__gpio5,
+};
+
+static struct omap_hwmod omap2430_gpio5_hwmod = {
+        .name           = "gpio5",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap243x_gpio5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
+        .main_clk       = "gpio5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP2430_EN_GPIO5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* dma_system */
+static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap2430_dma_sysc,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+
+static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+
+static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x48056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+        .master         = &omap2430_dma_system_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
+        &omap2430_dma_system__l3,
+};
+
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2430_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
+        &omap2430_l4_core__dma_system,
+};
+
+static struct omap_hwmod omap2430_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2430_dma_hwmod_class,
+        .mpu_irqs       = omap2430_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
+        .main_clk       = "core_l3_ck",
+        .slaves         = omap2430_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
+        .masters        = omap2430_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+        { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mailbox_hwmod,
+        .addr           = omap2430_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
+        &omap2430_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2430_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap2430_mailbox_hwmod_class,
+        .mpu_irqs       = omap2430_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mcspi_class = {
+        .name = "mcspi",
+        .sysc = &omap2430_mcspi_sysc,
+        .rev = OMAP2_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
+        { .irq = 65 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
+        &omap2430_l4_core__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap2430_mcspi1_hwmod = {
+        .name           = "mcspi1_hwmod",
+        .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
+        .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
+        .class          = &omap2430_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
+        { .irq = 66 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
+        &omap2430_l4_core__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap2430_mcspi2_hwmod = {
+        .name           = "mcspi2_hwmod",
+        .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
+        .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
+        .class          = &omap2430_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
+        { .irq = 91 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
+        { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
+        { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
+        { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
+        &omap2430_l4_core__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap2430_mcspi3_hwmod = {
+        .name           = "mcspi3_hwmod",
+        .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
+        .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
+        .main_clk       = "mcspi3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcspi3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
+        .class          = &omap2430_mcspi_class,
+        .dev_attr       = &omap_mcspi3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * usbhsotg
+ */
+static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
+        .rev_offs       = 0x0400,
+        .sysc_offs      = 0x0404,
+        .syss_offs      = 0x0408,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class usbotg_class = {
+        .name = "usbotg",
+        .sysc = &omap2430_usbhsotg_sysc,
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
+
+        { .name = "mc", .irq = 92 },
+        { .name = "dma", .irq = 93 },
+};
+
+static struct omap_hwmod omap2430_usbhsotg_hwmod = {
+        .name           = "usb_otg_hs",
+        .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
+        .main_clk       = "usbhs_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_USBHS_MASK,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
+                },
+        },
+        .masters        = omap2430_usbhsotg_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
+        .slaves         = omap2430_usbhsotg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
+        .class          = &usbotg_class,
+        /*
+         * Erratum ID: i479  idle_req / idle_ack mechanism potentially
+         * broken when autoidle is enabled
+         * workaround is to disable the autoidle bit at module level.
+         */
+        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+                                | HWMOD_SWSUP_MSTANDBY,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
+        .rev_offs       = 0x007C,
+        .sysc_offs      = 0x008C,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+        .sysc = &omap2430_mcbsp_sysc,
+        .rev  = MCBSP_CONFIG_TYPE2,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+        { .name = "tx",         .irq = 59 },
+        { .name = "rx",         .irq = 60 },
+        { .name = "ovr",        .irq = 61 },
+        { .name = "common",     .irq = 64 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2430_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
+        &omap2430_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
+        .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+        { .name = "tx",         .irq = 62 },
+        { .name = "rx",         .irq = 63 },
+        { .name = "common",     .irq = 16 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480760ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2430_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
+        &omap2430_l4_core__mcbsp2,
+};
+
+static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
+        .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+        { .name = "tx",         .irq = 89 },
+        { .name = "rx",         .irq = 90 },
+        { .name = "common",     .irq = 17 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
+        { .name = "rx", .dma_req = 18 },
+        { .name = "tx", .dma_req = 17 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808C000,
+                .pa_end         = 0x4808C0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap2430_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
+        &omap2430_l4_core__mcbsp3,
+};
+
+static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
+        .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
+        { .name = "tx",         .irq = 54 },
+        { .name = "rx",         .irq = 55 },
+        { .name = "common",     .irq = 18 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
+        { .name = "rx", .dma_req = 20 },
+        { .name = "tx", .dma_req = 19 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808E000,
+                .pa_end         = 0x4808E0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap2430_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
+        &omap2430_l4_core__mcbsp4,
+};
+
+static struct omap_hwmod omap2430_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
+        .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
+        { .name = "tx",         .irq = 81 },
+        { .name = "rx",         .irq = 82 },
+        { .name = "common",     .irq = 19 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
+        { .name = "rx", .dma_req = 22 },
+        { .name = "tx", .dma_req = 21 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap2430_mcbsp5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp5 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
+        &omap2430_l4_core__mcbsp5,
+};
+
+static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+        .name           = "mcbsp5",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
+        .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
+        .main_clk       = "mcbsp5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* MMC/SD/SDIO common */
+
+static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mmc_class = {
+        .name = "mmc",
+        .sysc = &omap2430_mmc_sysc,
+};
+
+/* MMC/SD/SDIO1 */
+
+static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
+        { .irq = 83 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
+        { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
+};
+
+static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
+        { .role = "dbck", .clk = "mmchsdb1_fck" },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
+        &omap2430_l4_core__mmc1,
+};
+
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap2430_mmc1_hwmod = {
+        .name           = "mmc1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2430_mmc1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
+        .sdma_reqs      = omap2430_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
+        .opt_clks       = omap2430_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_dev_attr,
+        .slaves         = omap2430_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
+        .class          = &omap2430_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* MMC/SD/SDIO2 */
+
+static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
+        { .irq = 86 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
+        { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
+};
+
+static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
+        { .role = "dbck", .clk = "mmchsdb2_fck" },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
+        &omap2430_l4_core__mmc2,
+};
+
+static struct omap_hwmod omap2430_mmc2_hwmod = {
+        .name           = "mmc2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2430_mmc2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
+        .sdma_reqs      = omap2430_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
+        .opt_clks       = omap2430_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
+        .class          = &omap2430_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
         &omap2430_l4_core_hwmod,
         &omap2430_l4_wkup_hwmod,
         &omap2430_mpu_hwmod,
         &omap2430_iva_hwmod,
+
+        &omap2430_timer1_hwmod,
+        &omap2430_timer2_hwmod,
+        &omap2430_timer3_hwmod,
+        &omap2430_timer4_hwmod,
+        &omap2430_timer5_hwmod,
+        &omap2430_timer6_hwmod,
+        &omap2430_timer7_hwmod,
+        &omap2430_timer8_hwmod,
+        &omap2430_timer9_hwmod,
+        &omap2430_timer10_hwmod,
+        &omap2430_timer11_hwmod,
+        &omap2430_timer12_hwmod,
+
+        &omap2430_wd_timer2_hwmod,
+        &omap2430_uart1_hwmod,
+        &omap2430_uart2_hwmod,
+        &omap2430_uart3_hwmod,
+        /* dss class */
+        &omap2430_dss_core_hwmod,
+        &omap2430_dss_dispc_hwmod,
+        &omap2430_dss_rfbi_hwmod,
+        &omap2430_dss_venc_hwmod,
+        /* i2c class */
+        &omap2430_i2c1_hwmod,
+        &omap2430_i2c2_hwmod,
+        &omap2430_mmc1_hwmod,
+        &omap2430_mmc2_hwmod,
+
+        /* gpio class */
+        &omap2430_gpio1_hwmod,
+        &omap2430_gpio2_hwmod,
+        &omap2430_gpio3_hwmod,
+        &omap2430_gpio4_hwmod,
+        &omap2430_gpio5_hwmod,
+
+        /* dma_system class*/
+        &omap2430_dma_system_hwmod,
+
+        /* mcbsp class */
+        &omap2430_mcbsp1_hwmod,
+        &omap2430_mcbsp2_hwmod,
+        &omap2430_mcbsp3_hwmod,
+        &omap2430_mcbsp4_hwmod,
+        &omap2430_mcbsp5_hwmod,
+
+        /* mailbox class */
+        &omap2430_mailbox_hwmod,
+
+        /* mcspi class */
+        &omap2430_mcspi1_hwmod,
+        &omap2430_mcspi2_hwmod,
+        &omap2430_mcspi3_hwmod,
+
+        /* usbotg class*/
+        &omap2430_usbhsotg_hwmod,
+
         NULL,
 };
 
 int __init omap2430_hwmod_init(void)
 {
-        return omap_hwmod_init(omap2430_hwmods);
+        return omap_hwmod_register(omap2430_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58ba5e3..909a84de6682 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,10 +17,22 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
+#include <plat/l3_3xxx.h>
+#include <plat/l4_3xxx.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
+#include <plat/mmc.h>
+#include <plat/mcbsp.h>
+#include <plat/mcspi.h>
+#include <plat/dmtimer.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-34xx.h"
+#include "cm-regbits-34xx.h"
+#include "wd_timer.h"
+#include <mach/am35xx.h>
 
 /*
  * OMAP3xxx hardware module integration data
@@ -36,6 +48,42 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
 static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
+static struct omap_hwmod omap3430es1_dss_core_hwmod;
+static struct omap_hwmod omap3xxx_dss_core_hwmod;
+static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
+static struct omap_hwmod omap3xxx_dss_venc_hwmod;
+static struct omap_hwmod omap3xxx_i2c1_hwmod;
+static struct omap_hwmod omap3xxx_i2c2_hwmod;
+static struct omap_hwmod omap3xxx_i2c3_hwmod;
+static struct omap_hwmod omap3xxx_gpio1_hwmod;
+static struct omap_hwmod omap3xxx_gpio2_hwmod;
+static struct omap_hwmod omap3xxx_gpio3_hwmod;
+static struct omap_hwmod omap3xxx_gpio4_hwmod;
+static struct omap_hwmod omap3xxx_gpio5_hwmod;
+static struct omap_hwmod omap3xxx_gpio6_hwmod;
+static struct omap_hwmod omap34xx_sr1_hwmod;
+static struct omap_hwmod omap34xx_sr2_hwmod;
+static struct omap_hwmod omap34xx_mcspi1;
+static struct omap_hwmod omap34xx_mcspi2;
+static struct omap_hwmod omap34xx_mcspi3;
+static struct omap_hwmod omap34xx_mcspi4;
+static struct omap_hwmod omap3xxx_mmc1_hwmod;
+static struct omap_hwmod omap3xxx_mmc2_hwmod;
+static struct omap_hwmod omap3xxx_mmc3_hwmod;
+static struct omap_hwmod am35xx_usbhsotg_hwmod;
+
+static struct omap_hwmod omap3xxx_dma_system_hwmod;
+
+static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -51,10 +99,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L3 taret configuration and error log registers */
+static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
+        { .irq = INT_34XX_L3_DBG_IRQ },
+        { .irq = INT_34XX_L3_APP_IRQ },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
+        {
+                .pa_start       = 0x68000000,
+                .pa_end         = 0x6800ffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
 /* MPU -> L3 interface */
 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
-        .master = &omap3xxx_mpu_hwmod,
-        .slave  = &omap3xxx_l3_main_hwmod,
+        .master   = &omap3xxx_mpu_hwmod,
+        .slave    = &omap3xxx_l3_main_hwmod,
+        .addr     = omap3xxx_l3_main_addrs,
+        .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
         .user   = OCP_USER_MPU,
 };
 
@@ -63,6 +127,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
         &omap3xxx_mpu__l3_main,
 };
 
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
+        .master         = &omap3xxx_dss_core_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Master interfaces on the L3 interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
         &omap3xxx_l3_main__l4_core,
@@ -73,6 +150,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
         .name           = "l3_main",
         .class          = &l3_hwmod_class,
+        .mpu_irqs       = omap3xxx_l3_main_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
         .masters        = omap3xxx_l3_main_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
         .slaves         = omap3xxx_l3_main_slaves,
@@ -82,7 +161,27 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
+static struct omap_hwmod omap3xxx_uart1_hwmod;
+static struct omap_hwmod omap3xxx_uart2_hwmod;
+static struct omap_hwmod omap3xxx_uart3_hwmod;
+static struct omap_hwmod omap3xxx_uart4_hwmod;
+static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
+
+/* l3_core -> usbhsotg interface */
+static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
+        .master         = &omap3xxx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
 
+/* l3_core -> am35xx_usbhsotg interface */
+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
+        .master         = &am35xx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -90,22 +189,313 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap3xxx_mmc1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b41ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap3xxx_mmc2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> MMC3 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc3_hwmod,
+        .clk            = "mmchs3_ick",
+        .addr           = omap3xxx_mmc3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART1_BASE,
+                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap3xxx_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART2_BASE,
+                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap3xxx_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART3_BASE,
+                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap3xxx_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_BASE,
+                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = omap3xxx_uart4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN                128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap3xxx_i2c1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
+                        .l4_prot_group = 7,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap3xxx_i2c2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c3_hwmod,
+        .clk            = "i2c3_ick",
+        .addr           = omap3xxx_i2c3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR1_BASE,
+                .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr1_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
+        .user           = OCP_USER_MPU,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR2_BASE,
+                .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr2_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
+        .user           = OCP_USER_MPU,
+};
+
+/*
+* usbhsotg interface data
+*/
+
+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
+                .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = omap3xxx_usbhsotg_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
+        &omap3xxx_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
+        &omap3xxx_l4_core__usbhsotg,
+};
+
+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
+                .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = am35xx_usbhsotg_addrs,
+        .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
+        &am35xx_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
+        &am35xx_l4_core__usbhsotg,
+};
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
 };
 
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
-        &omap3xxx_l4_core__l4_wkup,
-};
-
 /* L4 CORE */
 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
         .name           = "l4_core",
         .class          = &l4_hwmod_class,
-        .masters        = omap3xxx_l4_core_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
         .slaves         = omap3xxx_l4_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -117,16 +507,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
         &omap3xxx_l3_main__l4_per,
 };
 
-/* Master interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
-};
-
 /* L4 PER */
 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
         .name           = "l4_per",
         .class          = &l4_hwmod_class,
-        .masters        = omap3xxx_l4_per_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
         .slaves         = omap3xxx_l4_per_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -138,16 +522,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
         &omap3xxx_l4_core__l4_wkup,
 };
 
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
-};
-
 /* L4 WKUP */
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
         .name           = "l4_wkup",
         .class          = &l4_hwmod_class,
-        .masters        = omap3xxx_l4_wkup_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
         .slaves         = omap3xxx_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -197,19 +575,3091 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* timer class */
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap3xxx_timer_1ms_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap3xxx_timer_sysc,
+        .rev =  OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap3xxx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48318000,
+                .pa_end         = 0x48318000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap3xxx_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+        &omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap3xxx_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap3xxx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x49032000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap3xxx_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
+        &omap3xxx_l4_per__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap3xxx_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap3xxx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x49034000,
+                .pa_end         = 0x49034000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap3xxx_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
+        &omap3xxx_l4_per__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap3xxx_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap3xxx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x49036000,
+                .pa_end         = 0x49036000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap3xxx_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
+        &omap3xxx_l4_per__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap3xxx_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap3xxx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x49038000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap3xxx_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
+        &omap3xxx_l4_per__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap3xxx_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT5_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap3xxx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4903A000,
+                .pa_end         = 0x4903A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap3xxx_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
+        &omap3xxx_l4_per__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap3xxx_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT6_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap3xxx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4903C000,
+                .pa_end         = 0x4903C000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap3xxx_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
+        &omap3xxx_l4_per__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap3xxx_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT7_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap3xxx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4903E000,
+                .pa_end         = 0x4903E000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap3xxx_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
+        &omap3xxx_l4_per__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap3xxx_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT8_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap3xxx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x49040000,
+                .pa_end         = 0x49040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap3xxx_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
+        &omap3xxx_l4_per__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap3xxx_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT9_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap3xxx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap3xxx_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
+        &omap3xxx_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap3xxx_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap3xxx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap3xxx_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
+        &omap3xxx_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap3xxx_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer12*/
+static struct omap_hwmod omap3xxx_timer12_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
+        { .irq = 95, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap3xxx_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
+        &omap3xxx_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap3xxx_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT12_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48314000,
+                .pa_end         = 0x4831407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_wd_timer2_hwmod,
+        .clk            = "wdt2_ick",
+        .addr           = omap3xxx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap3xxx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
+        &omap3xxx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap3xxx_wd_timer_hwmod_class,
+        .main_clk       = "wdt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_WDT2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        /*
+         * XXX: Use software supervised mode, HW supervised smartidle seems to
+         * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
+         */
+        .flags          = HWMOD_SWSUP_SIDLE,
+};
+
+/* UART common */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+        &omap3_l4_core__uart1,
+};
+
+static struct omap_hwmod omap3xxx_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+        &omap3_l4_core__uart2,
+};
+
+static struct omap_hwmod omap3xxx_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+        &omap3_l4_per__uart3,
+};
+
+static struct omap_hwmod omap3xxx_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART4 */
+
+static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+        { .irq = INT_36XX_UART4_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+        { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+        &omap3_l4_per__uart4,
+};
+
+static struct omap_hwmod omap3xxx_uart4_hwmod = {
+        .name           = "uart4",
+        .mpu_irqs       = uart4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
+        .sdma_reqs      = uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3630_EN_UART4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name = "i2c",
+        .sysc = &i2c_sysc,
+};
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
+        .name = "dss",
+        .sysc = &omap3xxx_dss_sysc,
+};
+
+static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+        { .name = "dsi1", .dma_req = 74 },
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
+        &omap3xxx_dss__l3,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x480503FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3430es1_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
+        &omap3430es1_l4_core__dss,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
+        &omap3xxx_l4_core__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "tv_clk", .clk = "dss_tv_fck" },
+        { .role = "video_clk", .clk = "dss_96m_fck" },
+        { .role = "sys_clk", .clk = "dss2_alwon_fck" },
+};
+
+static struct omap_hwmod omap3430es1_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap3xxx_dss_hwmod_class,
+        .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
+        .sdma_reqs      = omap3xxx_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
+
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap3430es1_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
+        .masters        = omap3xxx_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+static struct omap_hwmod omap3xxx_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap3xxx_dss_hwmod_class,
+        .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
+        .sdma_reqs      = omap3xxx_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
+
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
+                        .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap3xxx_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
+        .masters        = omap3xxx_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
+                                CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
+        .name = "dispc",
+        .sysc = &omap3xxx_dispc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
+        { .irq = 25 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x480507FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
+        &omap3xxx_l4_core__dss_dispc,
+};
+
+static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap3xxx_dispc_hwmod_class,
+        .mpu_irqs       = omap3xxx_dispc_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dispc_irqs),
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'dsi' class
+ * display serial interface controller
+ */
+
+static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
+        .name = "dsi",
+};
+
+static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
+        { .irq = 25 },
+};
+
+/* dss_dsi1 */
+static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x4804FC00,
+                .pa_end         = 0x4804FFFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dsi1_hwmod,
+        .addr           = omap3xxx_dss_dsi1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dsi1 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
+        &omap3xxx_l4_core__dss_dsi1,
+};
+
+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
+        .name           = "dss_dsi1",
+        .class          = &omap3xxx_dsi_hwmod_class,
+        .mpu_irqs       = omap3xxx_dsi1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dsi1_irqs),
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_dsi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
+        .name = "rfbi",
+        .sysc = &omap3xxx_rfbi_sysc,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050BFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
+        &omap3xxx_l4_core__dss_rfbi,
+};
+
+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap3xxx_rfbi_hwmod_class,
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
+        .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050FFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_venc_hwmod,
+        .clk            = "dss_tv_fck",
+        .addr           = omap3xxx_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
+        &omap3xxx_l4_core__dss_venc,
+};
+
+static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap3xxx_venc_hwmod_class,
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+        .fifo_depth     = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+        &omap3_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
+        .sdma_reqs      = i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .main_clk       = "i2c1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_I2C1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+        .fifo_depth     = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+        &omap3_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
+        .sdma_reqs      = i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .main_clk       = "i2c2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_I2C2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C3 */
+
+static struct omap_i2c_dev_attr i2c3_dev_attr = {
+        .fifo_depth     = 64, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+        { .irq = INT_34XX_I2C3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+        { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+        &omap3_l4_core__i2c3,
+};
+
+static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .mpu_irqs       = i2c3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
+        .sdma_reqs      = i2c3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
+        .main_clk       = "i2c3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_I2C3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_i2c3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x48310000,
+                .pa_end         = 0x483101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_gpio1_hwmod,
+        .addr           = omap3xxx_gpio1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x49050000,
+                .pa_end         = 0x490501ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio2_hwmod,
+        .addr           = omap3xxx_gpio2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x49052000,
+                .pa_end         = 0x490521ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio3_hwmod,
+        .addr           = omap3xxx_gpio3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x49054000,
+                .pa_end         = 0x490541ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio4_hwmod,
+        .addr           = omap3xxx_gpio4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x49056000,
+                .pa_end         = 0x490561ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio5_hwmod,
+        .addr           = omap3xxx_gpio5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x49058000,
+                .pa_end         = 0x490581ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio6_hwmod,
+        .addr           = omap3xxx_gpio6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap3xxx_gpio_sysc,
+        .rev = 1,
+};
+
+/* gpio_dev_attr*/
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
+        &omap3xxx_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap3xxx_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
+        .main_clk       = "gpio1_ick",
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
+        &omap3xxx_l4_per__gpio2,
+};
+
+static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap3xxx_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
+        .main_clk       = "gpio2_ick",
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
+        &omap3xxx_l4_per__gpio3,
+};
+
+static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap3xxx_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
+        .main_clk       = "gpio3_ick",
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
+        &omap3xxx_l4_per__gpio4,
+};
+
+static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap3xxx_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
+        .main_clk       = "gpio4_ick",
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
+        { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
+        &omap3xxx_l4_per__gpio5,
+};
+
+static struct omap_hwmod omap3xxx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap3xxx_gpio5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
+        .main_clk       = "gpio5_ick",
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO5_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio6 */
+static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
+        { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
+        &omap3xxx_l4_per__gpio6,
+};
+
+static struct omap_hwmod omap3xxx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap3xxx_gpio6_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
+        .main_clk       = "gpio6_ick",
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO6_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
+        .master         = &omap3xxx_dma_system_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap3xxx_dma_sysc,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x48056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
+        &omap3xxx_dma_system__l3,
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dma_system_hwmod,
+        .clk            = "core_l4_ick",
+        .addr           = omap3xxx_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
+        &omap3xxx_l4_core__dma_system,
+};
+
+static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap3xxx_dma_hwmod_class,
+        .mpu_irqs       = omap3xxx_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
+        .main_clk       = "core_l3_ick",
+        .prcm = {
+                .omap2 = {
+                        .module_offs            = CORE_MOD,
+                        .prcm_reg_id            = 1,
+                        .module_bit             = OMAP3430_ST_SDMA_SHIFT,
+                        .idlest_reg_id          = 1,
+                        .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
+        .masters        = omap3xxx_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+        .clockact       = 0x2,
+};
+
+static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+        .sysc = &omap3xxx_mcbsp_sysc,
+        .rev  = MCBSP_CONFIG_TYPE3,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
+        { .name = "irq", .irq = 16 },
+        { .name = "tx", .irq = 59 },
+        { .name = "rx", .irq = 60 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap3xxx_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
+        &omap3xxx_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
+        { .name = "irq", .irq = 17 },
+        { .name = "tx", .irq = 62 },
+        { .name = "rx", .irq = 63 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
+        &omap3xxx_l4_per__mcbsp2,
+};
+
+static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
+        .sidetone       = "mcbsp2_sidetone",
+};
+
+static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
+        .dev_attr       = &omap34xx_mcbsp2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
+        { .name = "irq", .irq = 22 },
+        { .name = "tx", .irq = 89 },
+        { .name = "rx", .irq = 90 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
+        { .name = "rx", .dma_req = 18 },
+        { .name = "tx", .dma_req = 17 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
+        &omap3xxx_l4_per__mcbsp3,
+};
+
+static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
+        .sidetone       = "mcbsp3_sidetone",
+};
+
+static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
+        .dev_attr       = &omap34xx_mcbsp3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
+        { .name = "irq", .irq = 23 },
+        { .name = "tx", .irq = 54 },
+        { .name = "rx", .irq = 55 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
+        { .name = "rx", .dma_req = 20 },
+        { .name = "tx", .dma_req = 19 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap3xxx_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
+        &omap3xxx_l4_per__mcbsp4,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
+        { .name = "irq", .irq = 27 },
+        { .name = "tx", .irq = 81 },
+        { .name = "rx", .irq = 82 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
+        { .name = "rx", .dma_req = 22 },
+        { .name = "tx", .dma_req = 21 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap3xxx_mcbsp5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp5 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
+        &omap3xxx_l4_core__mcbsp5,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
+        .name           = "mcbsp5",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
+        .main_clk       = "mcbsp5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+/* 'mcbsp sidetone' class */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_AUTOIDLE,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
+        .name = "mcbsp_sidetone",
+        .sysc = &omap3xxx_mcbsp_sidetone_sysc,
+};
+
+/* mcbsp2_sidetone */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
+        { .name = "irq", .irq = 4 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x49028000,
+                .pa_end         = 0x490280ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp2_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_sidetone_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* mcbsp2_sidetone slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
+        &omap3xxx_l4_per__mcbsp2_sidetone,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
+        .name           = "mcbsp2_sidetone",
+        .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp3_sidetone */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
+        { .name = "irq", .irq = 5 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x4902A000,
+                .pa_end         = 0x4902A0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp3_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_sidetone_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* mcbsp3_sidetone slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
+        &omap3xxx_l4_per__mcbsp3_sidetone,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
+        .name           = "mcbsp3_sidetone",
+        .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+
+/* SR common */
+static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+        .clkact_shift   = 20,
+};
+
+static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
+        .sysc_offs      = 0x24,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
+        .clockact       = CLOCKACT_TEST_ICLK,
+        .sysc_fields    = &omap34xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
+        .name = "smartreflex",
+        .sysc = &omap34xx_sr_sysc,
+        .rev  = 1,
+};
+
+static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+        .sidle_shift    = 24,
+        .enwkup_shift   = 26
+};
+
+static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
+        .sysc_offs      = 0x38,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                        SYSC_NO_CACHE),
+        .sysc_fields    = &omap36xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
+        .name = "smartreflex",
+        .sysc = &omap36xx_sr_sysc,
+        .rev  = 2,
+};
+
+/* SR1 */
+static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
+        &omap3_l4_core__sr1,
+};
+
+static struct omap_hwmod omap34xx_sr1_hwmod = {
+        .name           = "sr1_hwmod",
+        .class          = &omap34xx_smartreflex_hwmod_class,
+        .main_clk       = "sr1_fck",
+        .vdd_name       = "mpu",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+                                        CHIP_IS_OMAP3430ES3_0 |
+                                        CHIP_IS_OMAP3430ES3_1),
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+};
+
+static struct omap_hwmod omap36xx_sr1_hwmod = {
+        .name           = "sr1_hwmod",
+        .class          = &omap36xx_smartreflex_hwmod_class,
+        .main_clk       = "sr1_fck",
+        .vdd_name       = "mpu",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
+/* SR2 */
+static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
+        &omap3_l4_core__sr2,
+};
+
+static struct omap_hwmod omap34xx_sr2_hwmod = {
+        .name           = "sr2_hwmod",
+        .class          = &omap34xx_smartreflex_hwmod_class,
+        .main_clk       = "sr2_fck",
+        .vdd_name       = "core",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+                                        CHIP_IS_OMAP3430ES3_0 |
+                                        CHIP_IS_OMAP3430ES3_1),
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+};
+
+static struct omap_hwmod omap36xx_sr2_hwmod = {
+        .name           = "sr2_hwmod",
+        .class          = &omap36xx_smartreflex_hwmod_class,
+        .main_clk       = "sr2_fck",
+        .vdd_name       = "core",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+        { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mailbox_hwmod,
+        .addr           = omap3xxx_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+        &omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap3xxx_mailbox_hwmod_class,
+        .mpu_irqs       = omap3xxx_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480980ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi1,
+        .clk            = "mcspi1_ick",
+        .addr           = omap34xx_mcspi1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi2,
+        .clk            = "mcspi2_ick",
+        .addr           = omap34xx_mcspi2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b80ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi3,
+        .clk            = "mcspi3_ick",
+        .addr           = omap34xx_mcspi3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi4 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi4,
+        .clk            = "mcspi4_ick",
+        .addr           = omap34xx_mcspi4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap34xx_mcspi_class = {
+        .name = "mcspi",
+        .sysc = &omap34xx_mcspi_sysc,
+        .rev = OMAP3_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
+        { .name = "irq", .irq = 65 },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 },
+        { .name = "rx0", .dma_req = 36 },
+        { .name = "tx1", .dma_req = 37 },
+        { .name = "rx1", .dma_req = 38 },
+        { .name = "tx2", .dma_req = 39 },
+        { .name = "rx2", .dma_req = 40 },
+        { .name = "tx3", .dma_req = 41 },
+        { .name = "rx3", .dma_req = 42 },
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
+        &omap34xx_l4_core__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap34xx_mcspi1 = {
+        .name           = "mcspi1",
+        .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
+        { .name = "irq", .irq = 66 },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 },
+        { .name = "rx0", .dma_req = 44 },
+        { .name = "tx1", .dma_req = 45 },
+        { .name = "rx1", .dma_req = 46 },
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
+        &omap34xx_l4_core__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap34xx_mcspi2 = {
+        .name           = "mcspi2",
+        .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
+        { .name = "irq", .irq = 91 }, /* 91 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 15 },
+        { .name = "rx0", .dma_req = 16 },
+        { .name = "tx1", .dma_req = 23 },
+        { .name = "rx1", .dma_req = 24 },
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
+        &omap34xx_l4_core__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap34xx_mcspi3 = {
+        .name           = "mcspi3",
+        .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
+        .main_clk       = "mcspi3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* SPI4 */
+static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
+        { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
+        { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
+        &omap34xx_l4_core__mcspi4,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap34xx_mcspi4 = {
+        .name           = "mcspi4",
+        .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
+        .main_clk       = "mcspi4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi4_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/*
+ * usbhsotg
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
+        .rev_offs       = 0x0400,
+        .sysc_offs      = 0x0404,
+        .syss_offs      = 0x0408,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class usbotg_class = {
+        .name = "usbotg",
+        .sysc = &omap3xxx_usbhsotg_sysc,
+};
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
+
+        { .name = "mc", .irq = 92 },
+        { .name = "dma", .irq = 93 },
+};
+
+static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+        .name           = "usb_otg_hs",
+        .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
+        .main_clk       = "hsotgusb_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
+                        .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
+                },
+        },
+        .masters        = omap3xxx_usbhsotg_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
+        .slaves         = omap3xxx_usbhsotg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
+        .class          = &usbotg_class,
+
+        /*
+         * Erratum ID: i479  idle_req / idle_ack mechanism potentially
+         * broken when autoidle is enabled
+         * workaround is to disable the autoidle bit at module level.
+         */
+        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+                                | HWMOD_SWSUP_MSTANDBY,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+
+        { .name = "mc", .irq = 71 },
+};
+
+static struct omap_hwmod_class am35xx_usbotg_class = {
+        .name = "am35xx_usbotg",
+        .sysc = NULL,
+};
+
+static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+        .name           = "am35x_otg_hs",
+        .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
+        .main_clk       = NULL,
+        .prcm = {
+                .omap2 = {
+                },
+        },
+        .masters        = am35xx_usbhsotg_masters,
+        .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
+        .slaves         = am35xx_usbhsotg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
+        .class          = &am35xx_usbotg_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
+};
+
+/* MMC/SD/SDIO common */
+
+static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap34xx_mmc_class = {
+        .name = "mmc",
+        .sysc = &omap34xx_mmc_sysc,
+};
+
+/* MMC/SD/SDIO1 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
+        { .irq = 83, },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 61, },
+        { .name = "rx", .dma_req = 62, },
+};
+
+static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
+        { .role = "dbck", .clk = "omap_32k_fck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
+        &omap3xxx_l4_core__mmc1,
+};
+
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
+        .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
+        .opt_clks       = omap34xx_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_dev_attr,
+        .slaves         = omap3xxx_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
+        .class          = &omap34xx_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* MMC/SD/SDIO2 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
+        { .irq = INT_24XX_MMC2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 47, },
+        { .name = "rx", .dma_req = 48, },
+};
+
+static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
+        { .role = "dbck", .clk = "omap_32k_fck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
+        &omap3xxx_l4_core__mmc2,
+};
+
+static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
+        .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
+        .opt_clks       = omap34xx_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
+        .class          = &omap34xx_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* MMC/SD/SDIO3 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
+        { .irq = 94, },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 77, },
+        { .name = "rx", .dma_req = 78, },
+};
+
+static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
+        { .role = "dbck", .clk = "omap_32k_fck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
+        &omap3xxx_l4_core__mmc3,
+};
+
+static struct omap_hwmod omap3xxx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
+        .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
+        .opt_clks       = omap34xx_mmc3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
+        .main_clk       = "mmchs3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mmc3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
+        .class          = &omap34xx_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
         &omap3xxx_l4_per_hwmod,
         &omap3xxx_l4_wkup_hwmod,
+        &omap3xxx_mmc1_hwmod,
+        &omap3xxx_mmc2_hwmod,
+        &omap3xxx_mmc3_hwmod,
         &omap3xxx_mpu_hwmod,
         &omap3xxx_iva_hwmod,
+
+        &omap3xxx_timer1_hwmod,
+        &omap3xxx_timer2_hwmod,
+        &omap3xxx_timer3_hwmod,
+        &omap3xxx_timer4_hwmod,
+        &omap3xxx_timer5_hwmod,
+        &omap3xxx_timer6_hwmod,
+        &omap3xxx_timer7_hwmod,
+        &omap3xxx_timer8_hwmod,
+        &omap3xxx_timer9_hwmod,
+        &omap3xxx_timer10_hwmod,
+        &omap3xxx_timer11_hwmod,
+        &omap3xxx_timer12_hwmod,
+
+        &omap3xxx_wd_timer2_hwmod,
+        &omap3xxx_uart1_hwmod,
+        &omap3xxx_uart2_hwmod,
+        &omap3xxx_uart3_hwmod,
+        &omap3xxx_uart4_hwmod,
+        /* dss class */
+        &omap3430es1_dss_core_hwmod,
+        &omap3xxx_dss_core_hwmod,
+        &omap3xxx_dss_dispc_hwmod,
+        &omap3xxx_dss_dsi1_hwmod,
+        &omap3xxx_dss_rfbi_hwmod,
+        &omap3xxx_dss_venc_hwmod,
+
+        /* i2c class */
+        &omap3xxx_i2c1_hwmod,
+        &omap3xxx_i2c2_hwmod,
+        &omap3xxx_i2c3_hwmod,
+        &omap34xx_sr1_hwmod,
+        &omap34xx_sr2_hwmod,
+        &omap36xx_sr1_hwmod,
+        &omap36xx_sr2_hwmod,
+
+
+        /* gpio class */
+        &omap3xxx_gpio1_hwmod,
+        &omap3xxx_gpio2_hwmod,
+        &omap3xxx_gpio3_hwmod,
+        &omap3xxx_gpio4_hwmod,
+        &omap3xxx_gpio5_hwmod,
+        &omap3xxx_gpio6_hwmod,
+
+        /* dma_system class*/
+        &omap3xxx_dma_system_hwmod,
+
+        /* mcbsp class */
+        &omap3xxx_mcbsp1_hwmod,
+        &omap3xxx_mcbsp2_hwmod,
+        &omap3xxx_mcbsp3_hwmod,
+        &omap3xxx_mcbsp4_hwmod,
+        &omap3xxx_mcbsp5_hwmod,
+        &omap3xxx_mcbsp2_sidetone_hwmod,
+        &omap3xxx_mcbsp3_sidetone_hwmod,
+
+        /* mailbox class */
+        &omap3xxx_mailbox_hwmod,
+
+        /* mcspi class */
+        &omap34xx_mcspi1,
+        &omap34xx_mcspi2,
+        &omap34xx_mcspi3,
+        &omap34xx_mcspi4,
+
+        /* usbotg class */
+        &omap3xxx_usbhsotg_hwmod,
+
+        /* usbotg for am35x */
+        &am35xx_usbhsotg_hwmod,
+
         NULL,
 };
 
 int __init omap3xxx_hwmod_init(void)
 {
-        return omap_hwmod_init(omap3xxx_hwmods);
+        return omap_hwmod_register(omap3xxx_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
new file mode 100644
index 000000000000..e1c69ffe0f69
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -0,0 +1,5183 @@
+/*
+ * Hardware modules present on the OMAP44xx chips
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mcspi.h>
+#include <plat/mcbsp.h>
+#include <plat/mmc.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#include "wd_timer.h"
+
+/* Base offset for all OMAP4 interrupts external to MPUSS */
+#define OMAP44XX_IRQ_GIC_START  32
+
+/* Base offset for all OMAP4 dma requests */
+#define OMAP44XX_DMA_REQ_START  1
+
+/* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_aess_hwmod;
+static struct omap_hwmod omap44xx_dma_system_hwmod;
+static struct omap_hwmod omap44xx_dmm_hwmod;
+static struct omap_hwmod omap44xx_dsp_hwmod;
+static struct omap_hwmod omap44xx_dss_hwmod;
+static struct omap_hwmod omap44xx_emif_fw_hwmod;
+static struct omap_hwmod omap44xx_hsi_hwmod;
+static struct omap_hwmod omap44xx_ipu_hwmod;
+static struct omap_hwmod omap44xx_iss_hwmod;
+static struct omap_hwmod omap44xx_iva_hwmod;
+static struct omap_hwmod omap44xx_l3_instr_hwmod;
+static struct omap_hwmod omap44xx_l3_main_1_hwmod;
+static struct omap_hwmod omap44xx_l3_main_2_hwmod;
+static struct omap_hwmod omap44xx_l3_main_3_hwmod;
+static struct omap_hwmod omap44xx_l4_abe_hwmod;
+static struct omap_hwmod omap44xx_l4_cfg_hwmod;
+static struct omap_hwmod omap44xx_l4_per_hwmod;
+static struct omap_hwmod omap44xx_l4_wkup_hwmod;
+static struct omap_hwmod omap44xx_mmc1_hwmod;
+static struct omap_hwmod omap44xx_mmc2_hwmod;
+static struct omap_hwmod omap44xx_mpu_hwmod;
+static struct omap_hwmod omap44xx_mpu_private_hwmod;
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
+
+/*
+ * Interconnects omap_hwmod structures
+ * hwmods that compose the global OMAP interconnect
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
+        .name   = "dmm",
+};
+
+/* dmm interface data */
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
+        {
+                .pa_start       = 0x4e000000,
+                .pa_end         = 0x4e0007ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* mpu -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dmm_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dmm slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
+        &omap44xx_l3_main_1__dmm,
+        &omap44xx_mpu__dmm,
+};
+
+static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod omap44xx_dmm_hwmod = {
+        .name           = "dmm",
+        .class          = &omap44xx_dmm_hwmod_class,
+        .slaves         = omap44xx_dmm_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
+        .mpu_irqs       = omap44xx_dmm_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
+        .name   = "emif_fw",
+};
+
+/* emif_fw interface data */
+/* dmm -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+        .master         = &omap44xx_dmm_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
+        {
+                .pa_start       = 0x4a20c000,
+                .pa_end         = 0x4a20c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_emif_fw_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* emif_fw slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
+        &omap44xx_dmm__emif_fw,
+        &omap44xx_l4_cfg__emif_fw,
+};
+
+static struct omap_hwmod omap44xx_emif_fw_hwmod = {
+        .name           = "emif_fw",
+        .class          = &omap44xx_emif_fw_hwmod_class,
+        .slaves         = omap44xx_emif_fw_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
+        .name   = "l3",
+};
+
+/* l3_instr interface data */
+/* iva -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
+        .master         = &omap44xx_l3_main_3_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_instr slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
+        &omap44xx_iva__l3_instr,
+        &omap44xx_l3_main_3__l3_instr,
+};
+
+static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_instr_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_1 interface data */
+/* dsp -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+        .master         = &omap44xx_dss_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc1 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
+        .master         = &omap44xx_mmc1_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+        .master         = &omap44xx_mmc2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L3 target configuration and error log registers */
+static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
+        { .irq = 9  + OMAP44XX_IRQ_GIC_START },
+        { .irq = 10 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+        {
+                .pa_start       = 0x44000000,
+                .pa_end         = 0x44000fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+        &omap44xx_dsp__l3_main_1,
+        &omap44xx_dss__l3_main_1,
+        &omap44xx_l3_main_2__l3_main_1,
+        &omap44xx_l4_cfg__l3_main_1,
+        &omap44xx_mmc1__l3_main_1,
+        &omap44xx_mmc2__l3_main_1,
+        &omap44xx_mpu__l3_main_1,
+};
+
+static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &omap44xx_l3_hwmod_class,
+        .mpu_irqs       = omap44xx_l3_targ_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_l3_targ_irqs),
+        .slaves         = omap44xx_l3_main_1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_2 interface data */
+/* dma_system -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+        .master         = &omap44xx_dma_system_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* hsi -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
+        .master         = &omap44xx_hsi_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
+        .master         = &omap44xx_ipu_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
+        .master         = &omap44xx_iss_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+        {
+                .pa_start       = 0x44800000,
+                .pa_end         = 0x44801fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_otg_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+        &omap44xx_dma_system__l3_main_2,
+        &omap44xx_hsi__l3_main_2,
+        &omap44xx_ipu__l3_main_2,
+        &omap44xx_iss__l3_main_2,
+        &omap44xx_iva__l3_main_2,
+        &omap44xx_l3_main_1__l3_main_2,
+        &omap44xx_l4_cfg__l3_main_2,
+        &omap44xx_usb_otg_hs__l3_main_2,
+};
+
+static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_3 interface data */
+static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+        {
+                .pa_start       = 0x45000000,
+                .pa_end         = 0x45000fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
+        &omap44xx_l3_main_1__l3_main_3,
+        &omap44xx_l3_main_2__l3_main_3,
+        &omap44xx_l4_cfg__l3_main_3,
+};
+
+static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+        .name           = "l3_main_3",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
+        .name   = "l4",
+};
+
+/* l4_abe interface data */
+/* aess -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
+        .master         = &omap44xx_aess_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
+        &omap44xx_aess__l4_abe,
+        &omap44xx_dsp__l4_abe,
+        &omap44xx_l3_main_1__l4_abe,
+        &omap44xx_mpu__l4_abe,
+};
+
+static struct omap_hwmod omap44xx_l4_abe_hwmod = {
+        .name           = "l4_abe",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_abe_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_cfg interface data */
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_cfg_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
+        &omap44xx_l3_main_1__l4_cfg,
+};
+
+static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_cfg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_per interface data */
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l4_per_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
+        &omap44xx_l3_main_2__l4_per,
+};
+
+static struct omap_hwmod omap44xx_l4_per_hwmod = {
+        .name           = "l4_per",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_per_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_wkup interface data */
+/* l4_cfg -> l4_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l4_wkup_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
+        &omap44xx_l4_cfg__l4_wkup,
+};
+
+static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_wkup_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
+        .name   = "mpu_bus",
+};
+
+/* mpu_private interface data */
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_mpu_private_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu_private slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
+        &omap44xx_mpu__mpu_private,
+};
+
+static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+        .name           = "mpu_private",
+        .class          = &omap44xx_mpu_bus_hwmod_class,
+        .slaves         = omap44xx_mpu_private_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ *   properly adapted to omap_hwmod / omap_device
+ *
+ *  c2c
+ *  c2c_target_fw
+ *  cm_core
+ *  cm_core_aon
+ *  ctrl_module_core
+ *  ctrl_module_pad_core
+ *  ctrl_module_pad_wkup
+ *  ctrl_module_wkup
+ *  debugss
+ *  efuse_ctrl_cust
+ *  efuse_ctrl_std
+ *  elm
+ *  emif1
+ *  emif2
+ *  fdif
+ *  gpmc
+ *  gpu
+ *  hdq1w
+ *  hsi
+ *  ocmc_ram
+ *  ocp2scp_usb_phy
+ *  ocp_wp_noc
+ *  prcm_mpu
+ *  prm
+ *  scrm
+ *  sl2if
+ *  slimbus1
+ *  slimbus2
+ *  usb_host_fs
+ *  usb_host_hs
+ *  usb_phy_cm
+ *  usb_tll_hs
+ *  usim
+ */
+
+/*
+ * 'aess' class
+ * audio engine sub system
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
+        .name   = "aess",
+        .sysc   = &omap44xx_aess_sysc,
+};
+
+/* aess */
+static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
+        { .irq = 99 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
+        { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
+};
+
+/* aess master ports */
+static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
+        &omap44xx_aess__l4_abe,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
+        {
+                .pa_start       = 0x401f1000,
+                .pa_end         = 0x401f13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> aess */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_aess_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
+        {
+                .pa_start       = 0x490f1000,
+                .pa_end         = 0x490f13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> aess (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_aess_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* aess slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
+        &omap44xx_l4_abe__aess,
+        &omap44xx_l4_abe__aess_dma,
+};
+
+static struct omap_hwmod omap44xx_aess_hwmod = {
+        .name           = "aess",
+        .class          = &omap44xx_aess_hwmod_class,
+        .mpu_irqs       = omap44xx_aess_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
+        .sdma_reqs      = omap44xx_aess_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
+        .main_clk       = "aess_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_aess_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
+        .masters        = omap44xx_aess_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'bandgap' class
+ * bangap reference for ldo regulators
+ */
+
+static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
+        .name   = "bandgap",
+};
+
+/* bandgap */
+static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
+        { .role = "fclk", .clk = "bandgap_fclk" },
+};
+
+static struct omap_hwmod omap44xx_bandgap_hwmod = {
+        .name           = "bandgap",
+        .class          = &omap44xx_bandgap_hwmod_class,
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+                },
+        },
+        .opt_clks       = bandgap_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0004,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap44xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod omap44xx_counter_32k_hwmod;
+static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x4a304000,
+                .pa_end         = 0x4a30401f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_counter_32k_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_counter_32k_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* counter_32k slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
+        &omap44xx_l4_wkup__counter_32k,
+};
+
+static struct omap_hwmod omap44xx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap44xx_counter_hwmod_class,
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "sys_32k_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_counter_32k_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap44xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                          IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count      = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
+        &omap44xx_dma_system__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dma_system_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
+        &omap44xx_l4_cfg__dma_system,
+};
+
+static struct omap_hwmod omap44xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &omap44xx_dma_hwmod_class,
+        .mpu_irqs       = omap44xx_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
+        .main_clk       = "l3_div_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
+                },
+        },
+        .dev_attr       = &dma_dev_attr,
+        .slaves         = omap44xx_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
+        .masters        = omap44xx_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dmic' class
+ * digital microphone controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
+        .name   = "dmic",
+        .sysc   = &omap44xx_dmic_sysc,
+};
+
+/* dmic */
+static struct omap_hwmod omap44xx_dmic_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
+        { .irq = 114 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
+        { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
+        {
+                .pa_start       = 0x4012e000,
+                .pa_end         = 0x4012e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
+        {
+                .pa_start       = 0x4902e000,
+                .pa_end         = 0x4902e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> dmic (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* dmic slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
+        &omap44xx_l4_abe__dmic,
+        &omap44xx_l4_abe__dmic_dma,
+};
+
+static struct omap_hwmod omap44xx_dmic_hwmod = {
+        .name           = "dmic",
+        .class          = &omap44xx_dmic_hwmod_class,
+        .mpu_irqs       = omap44xx_dmic_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
+        .sdma_reqs      = omap44xx_dmic_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
+        .main_clk       = "dmic_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dmic_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dsp' class
+ * dsp sub-system
+ */
+
+static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
+        .name   = "dsp",
+};
+
+/* dsp */
+static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
+        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
+        { .name = "dsp", .rst_shift = 0 },
+};
+
+/* dsp -> iva */
+static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+};
+
+/* dsp master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
+        &omap44xx_dsp__l3_main_1,
+        &omap44xx_dsp__l4_abe,
+        &omap44xx_dsp__iva,
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
+        &omap44xx_l4_cfg__dsp,
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
+        .name           = "dsp_c0",
+        .class          = &omap44xx_dsp_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_dsp_c0_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
+        .prcm = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct omap_hwmod omap44xx_dsp_hwmod = {
+        .name           = "dsp",
+        .class          = &omap44xx_dsp_hwmod_class,
+        .mpu_irqs       = omap44xx_dsp_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
+        .rst_lines      = omap44xx_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
+        .main_clk       = "dsp_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+                        .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+                },
+        },
+        .slaves         = omap44xx_dsp_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
+        .masters        = omap44xx_dsp_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
+        .name   = "dss",
+        .sysc   = &omap44xx_dss_sysc,
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
+        &omap44xx_dss__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+        {
+                .pa_start       = 0x58000000,
+                .pa_end         = 0x5800007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x4804007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
+        &omap44xx_l3_main_2__dss,
+        &omap44xx_l4_per__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+        { .role = "tv_clk", .clk = "dss_tv_clk" },
+        { .role = "dss_clk", .clk = "dss_dss_clk" },
+        { .role = "video_clk", .clk = "dss_48mhz_clk" },
+};
+
+static struct omap_hwmod omap44xx_dss_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap44xx_dss_hwmod_class,
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap44xx_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
+        .masters        = omap44xx_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
+        .name   = "dispc",
+        .sysc   = &omap44xx_dispc_sysc,
+};
+
+/* dss_dispc */
+static struct omap_hwmod omap44xx_dss_dispc_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+        { .irq = 25 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
+        { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58001000,
+                .pa_end         = 0x58001fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dispc_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48041000,
+                .pa_end         = 0x48041fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
+        &omap44xx_l3_main_2__dss_dispc,
+        &omap44xx_l4_per__dss_dispc,
+};
+
+static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap44xx_dispc_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_dispc_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
+        .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dsi' class
+ * display serial interface controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
+        .name   = "dsi",
+        .sysc   = &omap44xx_dsi_sysc,
+};
+
+/* dss_dsi1 */
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
+        { .irq = 53 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
+        { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+        {
+                .pa_start       = 0x58004000,
+                .pa_end         = 0x580041ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dsi1_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x480441ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_dsi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
+        &omap44xx_l3_main_2__dss_dsi1,
+        &omap44xx_l4_per__dss_dsi1,
+};
+
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+        .name           = "dss_dsi1",
+        .class          = &omap44xx_dsi_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_dsi1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
+        .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_dsi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* dss_dsi2 */
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
+        { .irq = 84 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
+        { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+        {
+                .pa_start       = 0x58005000,
+                .pa_end         = 0x580051ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dsi2_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+        {
+                .pa_start       = 0x48045000,
+                .pa_end         = 0x480451ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_dsi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
+        &omap44xx_l3_main_2__dss_dsi2,
+        &omap44xx_l4_per__dss_dsi2,
+};
+
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+        .name           = "dss_dsi2",
+        .class          = &omap44xx_dsi_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_dsi2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
+        .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_dsi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
+        .name   = "hdmi",
+        .sysc   = &omap44xx_hdmi_sysc,
+};
+
+/* dss_hdmi */
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
+        { .irq = 101 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
+        { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58006000,
+                .pa_end         = 0x58006fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_hdmi_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_hdmi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_hdmi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
+        &omap44xx_l3_main_2__dss_hdmi,
+        &omap44xx_l4_per__dss_hdmi,
+};
+
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+        .name           = "dss_hdmi",
+        .class          = &omap44xx_hdmi_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_hdmi_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
+        .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_hdmi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
+        .name   = "rfbi",
+        .sysc   = &omap44xx_rfbi_sysc,
+};
+
+/* dss_rfbi */
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
+static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
+        { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58002000,
+                .pa_end         = 0x580020ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_rfbi_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x480420ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
+        &omap44xx_l3_main_2__dss_rfbi,
+        &omap44xx_l4_per__dss_rfbi,
+};
+
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap44xx_rfbi_hwmod_class,
+        .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
+        .name   = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod omap44xx_dss_venc_hwmod;
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58003000,
+                .pa_end         = 0x580030ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_venc_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48043000,
+                .pa_end         = 0x480430ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+        &omap44xx_l3_main_2__dss_venc,
+        &omap44xx_l4_per__dss_venc,
+};
+
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap44xx_venc_hwmod_class,
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
+        .name   = "gpio",
+        .sysc   = &omap44xx_gpio_sysc,
+        .rev    = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod omap44xx_gpio1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
+        { .irq = 29 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4a310000,
+                .pa_end         = 0x4a3101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_gpio1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_gpio1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
+        &omap44xx_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .mpu_irqs       = omap44xx_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
+        .main_clk       = "gpio1_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio2 */
+static struct omap_hwmod omap44xx_gpio2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
+        { .irq = 30 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x48055000,
+                .pa_end         = 0x480551ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
+        &omap44xx_l4_per__gpio2,
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
+        .main_clk       = "gpio2_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio3 */
+static struct omap_hwmod omap44xx_gpio3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
+        { .irq = 31 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x48057000,
+                .pa_end         = 0x480571ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
+        &omap44xx_l4_per__gpio3,
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
+        .main_clk       = "gpio3_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio4 */
+static struct omap_hwmod omap44xx_gpio4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
+        { .irq = 32 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x48059000,
+                .pa_end         = 0x480591ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
+        &omap44xx_l4_per__gpio4,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
+        .main_clk       = "gpio4_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio5 */
+static struct omap_hwmod omap44xx_gpio5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
+        { .irq = 33 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x4805b000,
+                .pa_end         = 0x4805b1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
+        &omap44xx_l4_per__gpio5,
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
+        .main_clk       = "gpio5_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio6 */
+static struct omap_hwmod omap44xx_gpio6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
+        { .irq = 34 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x4805d000,
+                .pa_end         = 0x4805d1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio6_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
+        &omap44xx_l4_per__gpio6,
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio6_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
+        .main_clk       = "gpio6_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'hsi' class
+ * mipi high-speed synchronous serial interface (multichannel and full-duplex
+ * serial if)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
+        .name   = "hsi",
+        .sysc   = &omap44xx_hsi_sysc,
+};
+
+/* hsi */
+static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
+        { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
+        { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
+        { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* hsi master ports */
+static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
+        &omap44xx_hsi__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
+        {
+                .pa_start       = 0x4a058000,
+                .pa_end         = 0x4a05bfff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> hsi */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_hsi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_hsi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* hsi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
+        &omap44xx_l4_cfg__hsi,
+};
+
+static struct omap_hwmod omap44xx_hsi_hwmod = {
+        .name           = "hsi",
+        .class          = &omap44xx_hsi_hwmod_class,
+        .mpu_irqs       = omap44xx_hsi_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
+        .main_clk       = "hsi_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_hsi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
+        .masters        = omap44xx_hsi_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+        .name   = "i2c",
+        .sysc   = &omap44xx_i2c_sysc,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap44xx_i2c1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+        { .irq = 56 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x480700ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+        &omap44xx_l4_per__i2c1,
+};
+
+static struct omap_hwmod omap44xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
+        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
+        .main_clk       = "i2c1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c2 */
+static struct omap_hwmod omap44xx_i2c2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
+        { .irq = 57 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x480720ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+        &omap44xx_l4_per__i2c2,
+};
+
+static struct omap_hwmod omap44xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
+        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
+        .main_clk       = "i2c2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c3 */
+static struct omap_hwmod omap44xx_i2c3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
+        { .irq = 61 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x480600ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+        &omap44xx_l4_per__i2c3,
+};
+
+static struct omap_hwmod omap44xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
+        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
+        .main_clk       = "i2c3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c4 */
+static struct omap_hwmod omap44xx_i2c4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
+        { .irq = 62 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+        {
+                .pa_start       = 0x48350000,
+                .pa_end         = 0x483500ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+        &omap44xx_l4_per__i2c4,
+};
+
+static struct omap_hwmod omap44xx_i2c4_hwmod = {
+        .name           = "i2c4",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
+        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
+        .main_clk       = "i2c4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'ipu' class
+ * imaging processor unit
+ */
+
+static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
+        .name   = "ipu",
+};
+
+/* ipu */
+static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
+        { .irq = 100 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+        { .name = "cpu0", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
+        { .name = "cpu1", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+
+/* ipu master ports */
+static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
+        &omap44xx_ipu__l3_main_2,
+};
+
+/* l3_main_2 -> ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
+        &omap44xx_l3_main_2__ipu,
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
+        .name           = "ipu_c0",
+        .class          = &omap44xx_ipu_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_ipu_c0_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
+        .prcm           = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
+        .name           = "ipu_c1",
+        .class          = &omap44xx_ipu_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_ipu_c1_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
+        .prcm           = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct omap_hwmod omap44xx_ipu_hwmod = {
+        .name           = "ipu",
+        .class          = &omap44xx_ipu_hwmod_class,
+        .mpu_irqs       = omap44xx_ipu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
+        .rst_lines      = omap44xx_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
+        .main_clk       = "ipu_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                },
+        },
+        .slaves         = omap44xx_ipu_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
+        .masters        = omap44xx_ipu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'iss' class
+ * external images sensor pixel data processor
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
+        .name   = "iss",
+        .sysc   = &omap44xx_iss_sysc,
+};
+
+/* iss */
+static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
+        { .irq = 24 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
+        { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
+        { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
+        { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
+        { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
+};
+
+/* iss master ports */
+static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
+        &omap44xx_iss__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
+        {
+                .pa_start       = 0x52000000,
+                .pa_end         = 0x520000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> iss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iss_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iss slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
+        &omap44xx_l3_main_2__iss,
+};
+
+static struct omap_hwmod_opt_clk iss_opt_clks[] = {
+        { .role = "ctrlclk", .clk = "iss_ctrlclk" },
+};
+
+static struct omap_hwmod omap44xx_iss_hwmod = {
+        .name           = "iss",
+        .class          = &omap44xx_iss_hwmod_class,
+        .mpu_irqs       = omap44xx_iss_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
+        .sdma_reqs      = omap44xx_iss_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
+        .main_clk       = "iss_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
+                },
+        },
+        .opt_clks       = iss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
+        .slaves         = omap44xx_iss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
+        .masters        = omap44xx_iss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'iva' class
+ * multi-standard video encoder/decoder hardware accelerator
+ */
+
+static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
+        .name   = "iva",
+};
+
+/* iva */
+static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
+        { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
+        { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
+        { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
+        { .name = "logic", .rst_shift = 2 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
+        { .name = "seq0", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
+        { .name = "seq1", .rst_shift = 1 },
+};
+
+/* iva master ports */
+static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
+        &omap44xx_iva__l3_main_2,
+        &omap44xx_iva__l3_instr,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
+        {
+                .pa_start       = 0x5a000000,
+                .pa_end         = 0x5a07ffff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> iva */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iva_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
+        &omap44xx_dsp__iva,
+        &omap44xx_l3_main_2__iva,
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
+        .name           = "iva_seq0",
+        .class          = &omap44xx_iva_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_iva_seq0_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
+        .prcm = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
+        .name           = "iva_seq1",
+        .class          = &omap44xx_iva_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_iva_seq1_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
+        .prcm = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct omap_hwmod omap44xx_iva_hwmod = {
+        .name           = "iva",
+        .class          = &omap44xx_iva_hwmod_class,
+        .mpu_irqs       = omap44xx_iva_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
+        .rst_lines      = omap44xx_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
+        .main_clk       = "iva_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
+                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                },
+        },
+        .slaves         = omap44xx_iva_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
+        .masters        = omap44xx_iva_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'kbd' class
+ * keyboard controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
+        .name   = "kbd",
+        .sysc   = &omap44xx_kbd_sysc,
+};
+
+/* kbd */
+static struct omap_hwmod omap44xx_kbd_hwmod;
+static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
+        { .irq = 120 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+        {
+                .pa_start       = 0x4a31c000,
+                .pa_end         = 0x4a31c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_kbd_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_kbd_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* kbd slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
+        &omap44xx_l4_wkup__kbd,
+};
+
+static struct omap_hwmod omap44xx_kbd_hwmod = {
+        .name           = "kbd",
+        .class          = &omap44xx_kbd_hwmod_class,
+        .mpu_irqs       = omap44xx_kbd_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
+        .main_clk       = "kbd_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_kbd_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &omap44xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+        { .irq = 26 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x4a0f4000,
+                .pa_end         = 0x4a0f41ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mailbox_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+        &omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap44xx_mailbox_hwmod_class,
+        .mpu_irqs       = omap44xx_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
+        .name   = "mcbsp",
+        .sysc   = &omap44xx_mcbsp_sysc,
+        .rev    = MCBSP_CONFIG_TYPE4,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod omap44xx_mcbsp1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
+        { .irq = 17 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40122000,
+                .pa_end         = 0x401220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
+        &omap44xx_l4_abe__mcbsp1,
+        &omap44xx_l4_abe__mcbsp1_dma,
+};
+
+static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
+        .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod omap44xx_mcbsp2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
+        { .irq = 22 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40124000,
+                .pa_end         = 0x401240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp2 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
+        &omap44xx_l4_abe__mcbsp2,
+        &omap44xx_l4_abe__mcbsp2_dma,
+};
+
+static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
+        .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod omap44xx_mcbsp3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
+        { .irq = 23 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40126000,
+                .pa_end         = 0x401260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
+        &omap44xx_l4_abe__mcbsp3,
+        &omap44xx_l4_abe__mcbsp3_dma,
+};
+
+static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
+        .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod omap44xx_mcbsp4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
+        { .irq = 16 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+        {
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcbsp4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
+        &omap44xx_l4_per__mcbsp4,
+};
+
+static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
+        .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
+        .name   = "mcpdm",
+        .sysc   = &omap44xx_mcpdm_sysc,
+};
+
+/* mcpdm */
+static struct omap_hwmod omap44xx_mcpdm_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
+        { .irq = 112 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
+        { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
+        { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+        {
+                .pa_start       = 0x40132000,
+                .pa_end         = 0x4013207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x4903207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcpdm (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcpdm slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
+        &omap44xx_l4_abe__mcpdm,
+        &omap44xx_l4_abe__mcpdm_dma,
+};
+
+static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+        .name           = "mcpdm",
+        .class          = &omap44xx_mcpdm_hwmod_class,
+        .mpu_irqs       = omap44xx_mcpdm_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
+        .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
+        .main_clk       = "mcpdm_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcpdm_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+        .name   = "mcspi",
+        .sysc   = &omap44xx_mcspi_sysc,
+        .rev    = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+        { .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480981ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+        &omap44xx_l4_per__mcspi1,
+};
+
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
+        .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi1_dev_attr,
+        .slaves         = omap44xx_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+        { .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+        &omap44xx_l4_per__mcspi2,
+};
+
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
+        .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi2_dev_attr,
+        .slaves         = omap44xx_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+        { .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b81ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+        &omap44xx_l4_per__mcspi3,
+};
+
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
+        .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+        .main_clk       = "mcspi3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi3_dev_attr,
+        .slaves         = omap44xx_mcspi3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+        { .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+        &omap44xx_l4_per__mcspi4,
+};
+
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
+        .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+        .main_clk       = "mcspi4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi4_dev_attr,
+        .slaves         = omap44xx_mcspi4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
+        .name   = "mmc",
+        .sysc   = &omap44xx_mmc_sysc,
+};
+
+/* mmc1 */
+
+static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
+        { .irq = 83 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
+};
+
+/* mmc1 master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
+        &omap44xx_mmc1__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
+        &omap44xx_l4_per__mmc1,
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap44xx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
+        .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
+        .main_clk       = "mmc1_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mmc1_dev_attr,
+        .slaves         = omap44xx_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
+        .masters        = omap44xx_mmc1_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
+        { .irq = 86 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
+};
+
+/* mmc2 master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
+        &omap44xx_mmc2__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b43ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
+        &omap44xx_l4_per__mmc2,
+};
+
+static struct omap_hwmod omap44xx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
+        .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
+        .main_clk       = "mmc2_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
+        .masters        = omap44xx_mmc2_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc3 */
+static struct omap_hwmod omap44xx_mmc3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
+        { .irq = 94 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
+        &omap44xx_l4_per__mmc3,
+};
+
+static struct omap_hwmod omap44xx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
+        .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
+        .main_clk       = "mmc3_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc4 */
+static struct omap_hwmod omap44xx_mmc4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
+        { .irq = 96 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+        {
+                .pa_start       = 0x480d1000,
+                .pa_end         = 0x480d13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
+        &omap44xx_l4_per__mmc4,
+};
+
+static struct omap_hwmod omap44xx_mmc4_hwmod = {
+        .name           = "mmc4",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
+        .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
+        .main_clk       = "mmc4_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc5 */
+static struct omap_hwmod omap44xx_mmc5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
+        { .irq = 59 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+        {
+                .pa_start       = 0x480d5000,
+                .pa_end         = 0x480d53ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
+        &omap44xx_l4_per__mmc5,
+};
+
+static struct omap_hwmod omap44xx_mmc5_hwmod = {
+        .name           = "mmc5",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
+        .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
+        .main_clk       = "mmc5_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
+        { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
+        { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* mpu master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
+        &omap44xx_mpu__l3_main_1,
+        &omap44xx_mpu__l4_abe,
+        &omap44xx_mpu__dmm,
+};
+
+static struct omap_hwmod omap44xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &omap44xx_mpu_hwmod_class,
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = omap44xx_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
+                },
+        },
+        .masters        = omap44xx_mpu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+        .sidle_shift    = 24,
+        .enwkup_shift   = 26,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+        .sysc_offs      = 0x0038,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+        .name   = "smartreflex",
+        .sysc   = &omap44xx_smartreflex_sysc,
+        .rev    = 2,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+        { .irq = 19 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+        {
+                .pa_start       = 0x4a0dd000,
+                .pa_end         = 0x4a0dd03f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_core_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_core slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+        &omap44xx_l4_cfg__smartreflex_core,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+        .name           = "smartreflex_core",
+        .class          = &omap44xx_smartreflex_hwmod_class,
+        .mpu_irqs       = omap44xx_smartreflex_core_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+        .main_clk       = "smartreflex_core_fck",
+        .vdd_name       = "core",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_smartreflex_core_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_iva */
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+        { .irq = 102 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+        {
+                .pa_start       = 0x4a0db000,
+                .pa_end         = 0x4a0db03f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_iva_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_iva_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+        &omap44xx_l4_cfg__smartreflex_iva,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+        .name           = "smartreflex_iva",
+        .class          = &omap44xx_smartreflex_hwmod_class,
+        .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+        .main_clk       = "smartreflex_iva_fck",
+        .vdd_name       = "iva",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_smartreflex_iva_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+        { .irq = 18 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+        {
+                .pa_start       = 0x4a0d9000,
+                .pa_end         = 0x4a0d903f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_mpu_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_mpu_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_mpu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
+        &omap44xx_l4_cfg__smartreflex_mpu,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+        .name           = "smartreflex_mpu",
+        .class          = &omap44xx_smartreflex_hwmod_class,
+        .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
+        .main_clk       = "smartreflex_mpu_fck",
+        .vdd_name       = "mpu",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_smartreflex_mpu_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the processes
+ * running on multiple processors
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
+        .name   = "spinlock",
+        .sysc   = &omap44xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod omap44xx_spinlock_hwmod;
+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x4a0f6000,
+                .pa_end         = 0x4a0f6fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_spinlock_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_spinlock_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* spinlock slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
+        &omap44xx_l4_cfg__spinlock,
+};
+
+static struct omap_hwmod omap44xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &omap44xx_spinlock_hwmod_class,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_spinlock_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap44xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap44xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap44xx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x4a318000,
+                .pa_end         = 0x4a31807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_timer1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+        &omap44xx_l4_wkup__timer1,
+};
+
+static struct omap_hwmod omap44xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &omap44xx_timer_1ms_hwmod_class,
+        .mpu_irqs       = omap44xx_timer1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
+        .main_clk       = "timer1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer2 */
+static struct omap_hwmod omap44xx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+        { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48032000,
+                .pa_end         = 0x4803207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+        &omap44xx_l4_per__timer2,
+};
+
+static struct omap_hwmod omap44xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &omap44xx_timer_1ms_hwmod_class,
+        .mpu_irqs       = omap44xx_timer2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
+        .main_clk       = "timer2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer3 */
+static struct omap_hwmod omap44xx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
+        { .irq = 39 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48034000,
+                .pa_end         = 0x4803407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
+        &omap44xx_l4_per__timer3,
+};
+
+static struct omap_hwmod omap44xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
+        .main_clk       = "timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer4 */
+static struct omap_hwmod omap44xx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
+        { .irq = 40 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x48036000,
+                .pa_end         = 0x4803607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
+        &omap44xx_l4_per__timer4,
+};
+
+static struct omap_hwmod omap44xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
+        .main_clk       = "timer4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer5 */
+static struct omap_hwmod omap44xx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
+        { .irq = 41 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x40138000,
+                .pa_end         = 0x4013807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x4903807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
+        &omap44xx_l4_abe__timer5,
+        &omap44xx_l4_abe__timer5_dma,
+};
+
+static struct omap_hwmod omap44xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
+        .main_clk       = "timer5_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer6 */
+static struct omap_hwmod omap44xx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
+        { .irq = 42 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4013a000,
+                .pa_end         = 0x4013a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903a000,
+                .pa_end         = 0x4903a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
+        &omap44xx_l4_abe__timer6,
+        &omap44xx_l4_abe__timer6_dma,
+};
+
+static struct omap_hwmod omap44xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer6_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
+        .main_clk       = "timer6_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer7 */
+static struct omap_hwmod omap44xx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
+        { .irq = 43 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4013c000,
+                .pa_end         = 0x4013c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903c000,
+                .pa_end         = 0x4903c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer7 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
+        &omap44xx_l4_abe__timer7,
+        &omap44xx_l4_abe__timer7_dma,
+};
+
+static struct omap_hwmod omap44xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer7_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
+        .main_clk       = "timer7_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer8 */
+static struct omap_hwmod omap44xx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
+        { .irq = 44 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4013e000,
+                .pa_end         = 0x4013e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903e000,
+                .pa_end         = 0x4903e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer8 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
+        &omap44xx_l4_abe__timer8,
+        &omap44xx_l4_abe__timer8_dma,
+};
+
+static struct omap_hwmod omap44xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer8_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
+        .main_clk       = "timer8_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer9 */
+static struct omap_hwmod omap44xx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
+        { .irq = 45 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x4803e000,
+                .pa_end         = 0x4803e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer9_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
+        &omap44xx_l4_per__timer9,
+};
+
+static struct omap_hwmod omap44xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer9_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
+        .main_clk       = "timer9_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer10 */
+static struct omap_hwmod omap44xx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
+        { .irq = 46 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x4808607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer10_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
+        &omap44xx_l4_per__timer10,
+};
+
+static struct omap_hwmod omap44xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &omap44xx_timer_1ms_hwmod_class,
+        .mpu_irqs       = omap44xx_timer10_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
+        .main_clk       = "timer10_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer11 */
+static struct omap_hwmod omap44xx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
+        { .irq = 47 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x4808807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer11_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
+        &omap44xx_l4_per__timer11,
+};
+
+static struct omap_hwmod omap44xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer11_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
+        .main_clk       = "timer11_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
+        .name   = "uart",
+        .sysc   = &omap44xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap44xx_uart1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
+        { .irq = 72 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+        {
+                .pa_start       = 0x4806a000,
+                .pa_end         = 0x4806a0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
+        &omap44xx_l4_per__uart1,
+};
+
+static struct omap_hwmod omap44xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
+        .sdma_reqs      = omap44xx_uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart2 */
+static struct omap_hwmod omap44xx_uart2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
+        { .irq = 73 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+        {
+                .pa_start       = 0x4806c000,
+                .pa_end         = 0x4806c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
+        &omap44xx_l4_per__uart2,
+};
+
+static struct omap_hwmod omap44xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
+        .sdma_reqs      = omap44xx_uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart3 */
+static struct omap_hwmod omap44xx_uart3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
+        { .irq = 74 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+        {
+                .pa_start       = 0x48020000,
+                .pa_end         = 0x480200ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
+        &omap44xx_l4_per__uart3,
+};
+
+static struct omap_hwmod omap44xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &omap44xx_uart_hwmod_class,
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = omap44xx_uart3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
+        .sdma_reqs      = omap44xx_uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart4 */
+static struct omap_hwmod omap44xx_uart4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
+        { .irq = 70 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+        {
+                .pa_start       = 0x4806e000,
+                .pa_end         = 0x4806e0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
+        &omap44xx_l4_per__uart4,
+};
+
+static struct omap_hwmod omap44xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
+        .sdma_reqs      = omap44xx_uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'usb_otg_hs' class
+ * high-speed on-the-go universal serial bus (usb_otg_hs) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
+        .rev_offs       = 0x0400,
+        .sysc_offs      = 0x0404,
+        .syss_offs      = 0x0408,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
+        .name = "usb_otg_hs",
+        .sysc = &omap44xx_usb_otg_hs_sysc,
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
+        { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
+        { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* usb_otg_hs master ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
+        &omap44xx_usb_otg_hs__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+        {
+                .pa_start       = 0x4a0ab000,
+                .pa_end         = 0x4a0ab003,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> usb_otg_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_otg_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_otg_hs_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
+        &omap44xx_l4_cfg__usb_otg_hs,
+};
+
+static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
+        { .role = "xclk", .clk = "usb_otg_hs_xclk" },
+};
+
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+        .name           = "usb_otg_hs",
+        .class          = &omap44xx_usb_otg_hs_hwmod_class,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
+        .main_clk       = "usb_otg_hs_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_hs_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+        .slaves         = omap44xx_usb_otg_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
+        .masters        = omap44xx_usb_otg_hs_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap44xx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap44xx_wd_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
+        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4a314000,
+                .pa_end         = 0x4a31407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_wd_timer2_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wd_timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
+        &omap44xx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
+        .main_clk       = "wd_timer2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* wd_timer3 */
+static struct omap_hwmod omap44xx_wd_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
+        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+        {
+                .pa_start       = 0x40130000,
+                .pa_end         = 0x4013007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+        {
+                .pa_start       = 0x49030000,
+                .pa_end         = 0x4903007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* wd_timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
+        &omap44xx_l4_abe__wd_timer3,
+        &omap44xx_l4_abe__wd_timer3_dma,
+};
+
+static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+        .name           = "wd_timer3",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
+        .main_clk       = "wd_timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+
+        /* dmm class */
+        &omap44xx_dmm_hwmod,
+
+        /* emif_fw class */
+        &omap44xx_emif_fw_hwmod,
+
+        /* l3 class */
+        &omap44xx_l3_instr_hwmod,
+        &omap44xx_l3_main_1_hwmod,
+        &omap44xx_l3_main_2_hwmod,
+        &omap44xx_l3_main_3_hwmod,
+
+        /* l4 class */
+        &omap44xx_l4_abe_hwmod,
+        &omap44xx_l4_cfg_hwmod,
+        &omap44xx_l4_per_hwmod,
+        &omap44xx_l4_wkup_hwmod,
+
+        /* mpu_bus class */
+        &omap44xx_mpu_private_hwmod,
+
+        /* aess class */
+/*      &omap44xx_aess_hwmod, */
+
+        /* bandgap class */
+        &omap44xx_bandgap_hwmod,
+
+        /* counter class */
+/*      &omap44xx_counter_32k_hwmod, */
+
+        /* dma class */
+        &omap44xx_dma_system_hwmod,
+
+        /* dmic class */
+        &omap44xx_dmic_hwmod,
+
+        /* dsp class */
+        &omap44xx_dsp_hwmod,
+        &omap44xx_dsp_c0_hwmod,
+
+        /* dss class */
+        &omap44xx_dss_hwmod,
+        &omap44xx_dss_dispc_hwmod,
+        &omap44xx_dss_dsi1_hwmod,
+        &omap44xx_dss_dsi2_hwmod,
+        &omap44xx_dss_hdmi_hwmod,
+        &omap44xx_dss_rfbi_hwmod,
+        &omap44xx_dss_venc_hwmod,
+
+        /* gpio class */
+        &omap44xx_gpio1_hwmod,
+        &omap44xx_gpio2_hwmod,
+        &omap44xx_gpio3_hwmod,
+        &omap44xx_gpio4_hwmod,
+        &omap44xx_gpio5_hwmod,
+        &omap44xx_gpio6_hwmod,
+
+        /* hsi class */
+/*      &omap44xx_hsi_hwmod, */
+
+        /* i2c class */
+        &omap44xx_i2c1_hwmod,
+        &omap44xx_i2c2_hwmod,
+        &omap44xx_i2c3_hwmod,
+        &omap44xx_i2c4_hwmod,
+
+        /* ipu class */
+        &omap44xx_ipu_hwmod,
+        &omap44xx_ipu_c0_hwmod,
+        &omap44xx_ipu_c1_hwmod,
+
+        /* iss class */
+/*      &omap44xx_iss_hwmod, */
+
+        /* iva class */
+        &omap44xx_iva_hwmod,
+        &omap44xx_iva_seq0_hwmod,
+        &omap44xx_iva_seq1_hwmod,
+
+        /* kbd class */
+        &omap44xx_kbd_hwmod,
+
+        /* mailbox class */
+        &omap44xx_mailbox_hwmod,
+
+        /* mcbsp class */
+        &omap44xx_mcbsp1_hwmod,
+        &omap44xx_mcbsp2_hwmod,
+        &omap44xx_mcbsp3_hwmod,
+        &omap44xx_mcbsp4_hwmod,
+
+        /* mcpdm class */
+/*      &omap44xx_mcpdm_hwmod, */
+
+        /* mcspi class */
+        &omap44xx_mcspi1_hwmod,
+        &omap44xx_mcspi2_hwmod,
+        &omap44xx_mcspi3_hwmod,
+        &omap44xx_mcspi4_hwmod,
+
+        /* mmc class */
+        &omap44xx_mmc1_hwmod,
+        &omap44xx_mmc2_hwmod,
+        &omap44xx_mmc3_hwmod,
+        &omap44xx_mmc4_hwmod,
+        &omap44xx_mmc5_hwmod,
+
+        /* mpu class */
+        &omap44xx_mpu_hwmod,
+
+        /* smartreflex class */
+        &omap44xx_smartreflex_core_hwmod,
+        &omap44xx_smartreflex_iva_hwmod,
+        &omap44xx_smartreflex_mpu_hwmod,
+
+        /* spinlock class */
+        &omap44xx_spinlock_hwmod,
+
+        /* timer class */
+        &omap44xx_timer1_hwmod,
+        &omap44xx_timer2_hwmod,
+        &omap44xx_timer3_hwmod,
+        &omap44xx_timer4_hwmod,
+        &omap44xx_timer5_hwmod,
+        &omap44xx_timer6_hwmod,
+        &omap44xx_timer7_hwmod,
+        &omap44xx_timer8_hwmod,
+        &omap44xx_timer9_hwmod,
+        &omap44xx_timer10_hwmod,
+        &omap44xx_timer11_hwmod,
+
+        /* uart class */
+        &omap44xx_uart1_hwmod,
+        &omap44xx_uart2_hwmod,
+        &omap44xx_uart3_hwmod,
+        &omap44xx_uart4_hwmod,
+
+        /* usb_otg_hs class */
+        &omap44xx_usb_otg_hs_hwmod,
+
+        /* wd_timer class */
+        &omap44xx_wd_timer2_hwmod,
+        &omap44xx_wd_timer3_hwmod,
+
+        NULL,
+};
+
+int __init omap44xx_hwmod_init(void)
+{
+        return omap_hwmod_register(omap44xx_hwmods);
+}
+
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 000000000000..7b9f1909ddb2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,248 @@
+/*
+  * OMAP4XXX L3 Interconnect error handling driver
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     Sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#include "omap_l3_noc.h"
+
+/*
+ * Interrupt Handler for L3 error detection.
+ *      1) Identify the L3 clockdomain partition to which the error belongs to.
+ *      2) Identify the slave where the error information is logged
+ *      3) Print the logged information.
+ *      4) Add dump stack to provide kernel trace.
+ *
+ * Two Types of errors :
+ *      1) Custom errors in L3 :
+ *              Target like DMM/FW/EMIF generates SRESP=ERR error
+ *      2) Standard L3 error:
+ *              - Unsupported CMD.
+ *                      L3 tries to access target while it is idle
+ *              - OCP disconnect.
+ *              - Address hole error:
+ *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
+ *                      do not have connectivity, the error is logged in
+ *                      their default target which is DMM2.
+ *
+ *      On High Secure devices, firewall errors are possible and those
+ *      can be trapped as well. But the trapping is implemented as part
+ *      secure software and hence need not be implemented here.
+ */
+static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
+{
+
+        struct omap4_l3         *l3 = _l3;
+        int inttype, i, j;
+        int err_src = 0;
+        u32 std_err_main_addr, std_err_main, err_reg;
+        u32 base, slave_addr, clear;
+        char *source_name;
+
+        /* Get the Type of interrupt */
+        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
+
+        for (i = 0; i < L3_MODULES; i++) {
+                /*
+                 * Read the regerr register of the clock domain
+                 * to determine the source
+                 */
+                base = (u32)l3->l3_base[i];
+                err_reg =  readl(base + l3_flagmux[i] + (inttype << 3));
+
+                /* Get the corresponding error and analyse */
+                if (err_reg) {
+                        /* Identify the source from control status register */
+                        for (j = 0; !(err_reg & (1 << j)); j++)
+                                                                        ;
+
+                        err_src = j;
+                        /* Read the stderrlog_main_source from clk domain */
+                        std_err_main_addr = base + *(l3_targ[i] + err_src);
+                        std_err_main = readl(std_err_main_addr);
+
+                        switch (std_err_main & CUSTOM_ERROR) {
+                        case STANDARD_ERROR:
+                                source_name =
+                                l3_targ_stderrlog_main_name[i][err_src];
+
+                                slave_addr = std_err_main_addr +
+                                                L3_SLAVE_ADDRESS_OFFSET;
+                                WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
+                                        source_name, readl(slave_addr));
+                                /* clear the std error log*/
+                                clear = std_err_main | CLEAR_STDERR_LOG;
+                                writel(clear, std_err_main_addr);
+                                break;
+
+                        case CUSTOM_ERROR:
+                                source_name =
+                                l3_targ_stderrlog_main_name[i][err_src];
+
+                                WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
+                                                        source_name);
+                                /* clear the std error log*/
+                                clear = std_err_main | CLEAR_STDERR_LOG;
+                                writel(clear, std_err_main_addr);
+                                break;
+
+                        default:
+                                /* Nothing to be handled here as of now */
+                                break;
+                        }
+                /* Error found so break the for loop */
+                break;
+                }
+        }
+        return IRQ_HANDLED;
+}
+
+static int __init omap4_l3_probe(struct platform_device *pdev)
+{
+        static struct omap4_l3          *l3;
+        struct resource         *res;
+        int                     ret;
+        int                     irq;
+
+        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+        if (!l3)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, l3);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 0\n");
+                ret = -ENODEV;
+                goto err0;
+        }
+
+        l3->l3_base[0] = ioremap(res->start, resource_size(res));
+        if (!l3->l3_base[0]) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err0;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 1\n");
+                ret = -ENODEV;
+                goto err1;
+        }
+
+        l3->l3_base[1] = ioremap(res->start, resource_size(res));
+        if (!l3->l3_base[1]) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 2\n");
+                ret = -ENODEV;
+                goto err2;
+        }
+
+        l3->l3_base[2] = ioremap(res->start, resource_size(res));
+        if (!l3->l3_base[2]) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err2;
+        }
+
+        /*
+         * Setup interrupt Handlers
+         */
+        irq = platform_get_irq(pdev, 0);
+        ret = request_irq(irq,
+                        l3_interrupt_handler,
+                        IRQF_DISABLED, "l3-dbg-irq", l3);
+        if (ret) {
+                pr_crit("L3: request_irq failed to register for 0x%x\n",
+                                         OMAP44XX_IRQ_L3_DBG);
+                goto err3;
+        }
+        l3->debug_irq = irq;
+
+        irq = platform_get_irq(pdev, 1);
+        ret = request_irq(irq,
+                        l3_interrupt_handler,
+                        IRQF_DISABLED, "l3-app-irq", l3);
+        if (ret) {
+                pr_crit("L3: request_irq failed to register for 0x%x\n",
+                                         OMAP44XX_IRQ_L3_APP);
+                goto err4;
+        }
+        l3->app_irq = irq;
+
+        return 0;
+
+err4:
+        free_irq(l3->debug_irq, l3);
+err3:
+        iounmap(l3->l3_base[2]);
+err2:
+        iounmap(l3->l3_base[1]);
+err1:
+        iounmap(l3->l3_base[0]);
+err0:
+        kfree(l3);
+        return ret;
+}
+
+static int __exit omap4_l3_remove(struct platform_device *pdev)
+{
+        struct omap4_l3         *l3 = platform_get_drvdata(pdev);
+
+        free_irq(l3->app_irq, l3);
+        free_irq(l3->debug_irq, l3);
+        iounmap(l3->l3_base[0]);
+        iounmap(l3->l3_base[1]);
+        iounmap(l3->l3_base[2]);
+        kfree(l3);
+
+        return 0;
+}
+
+static struct platform_driver omap4_l3_driver = {
+        .remove         = __exit_p(omap4_l3_remove),
+        .driver         = {
+        .name           = "omap_l3_noc",
+        },
+};
+
+static int __init omap4_l3_init(void)
+{
+        return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
+}
+postcore_initcall_sync(omap4_l3_init);
+
+static void __exit omap4_l3_exit(void)
+{
+        platform_driver_unregister(&omap4_l3_driver);
+}
+module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 000000000000..359b83348aed
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
+ /*
+  * OMAP4XXX L3 Interconnect  error handling driver header
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+
+/*
+ * L3 register offsets
+ */
+#define L3_MODULES                      3
+#define CLEAR_STDERR_LOG                (1 << 31)
+#define CUSTOM_ERROR                    0x2
+#define STANDARD_ERROR                  0x0
+#define INBAND_ERROR                    0x0
+#define EMIF_KERRLOG_OFFSET             0x10
+#define L3_SLAVE_ADDRESS_OFFSET         0x14
+#define LOGICAL_ADDR_ERRORLOG           0x4
+#define L3_APPLICATION_ERROR            0x0
+#define L3_DEBUG_ERROR                  0x1
+
+u32 l3_flagmux[L3_MODULES] = {
+        0x50C,
+        0x100C,
+        0X020C
+};
+
+/*
+ * L3 Target standard Error register offsets
+ */
+u32 l3_targ_stderrlog_main_clk1[] = {
+        0x148, /* DMM1 */
+        0x248, /* DMM2 */
+        0x348, /* ABE */
+        0x448, /* L4CFG */
+        0x648  /* CLK2 PWR DISC */
+};
+
+u32 l3_targ_stderrlog_main_clk2[] = {
+        0x548,          /* CORTEX M3 */
+        0x348,          /* DSS */
+        0x148,          /* GPMC */
+        0x448,          /* ISS */
+        0x748,          /* IVAHD */
+        0xD48,          /* missing in TRM  corresponds to AES1*/
+        0x948,          /* L4 PER0*/
+        0x248,          /* OCMRAM */
+        0x148,          /* missing in TRM corresponds to GPMC sERROR*/
+        0x648,          /* SGX */
+        0x848,          /* SL2 */
+        0x1648,         /* C2C */
+        0x1148,         /* missing in TRM corresponds PWR DISC CLK1*/
+        0xF48,          /* missing in TRM corrsponds to SHA1*/
+        0xE48,          /* missing in TRM corresponds to AES2*/
+        0xC48,          /* L4 PER3 */
+        0xA48,          /* L4 PER1*/
+        0xB48           /* L4 PER2*/
+};
+
+u32 l3_targ_stderrlog_main_clk3[] = {
+        0x0148  /* EMUSS */
+};
+
+char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
+        {
+        "DMM1",
+        "DMM2",
+        "ABE",
+        "L4CFG",
+        "CLK2 PWR DISC",
+        },
+        {
+        "CORTEX M3" ,
+        "DSS ",
+        "GPMC ",
+        "ISS ",
+        "IVAHD ",
+        "AES1",
+        "L4 PER0",
+        "OCMRAM ",
+        "GPMC sERROR",
+        "SGX ",
+        "SL2 ",
+        "C2C ",
+        "PWR DISC CLK1",
+        "SHA1",
+        "AES2",
+        "L4 PER3",
+        "L4 PER1",
+        "L4 PER2",
+        },
+        {
+        "EMUSS",
+        },
+};
+
+u32 *l3_targ[L3_MODULES] = {
+        l3_targ_stderrlog_main_clk1,
+        l3_targ_stderrlog_main_clk2,
+        l3_targ_stderrlog_main_clk3,
+};
+
+struct omap4_l3 {
+        struct device   *dev;
+        struct clk      *ick;
+
+        /* memory base */
+        void __iomem *l3_base[4];
+
+        int             debug_irq;
+        int             app_irq;
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 000000000000..873c0e33b512
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,299 @@
+ /*
+  * OMAP3XXX L3 Interconnect Driver
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Felipe Balbi <balbi@ti.com>
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     Sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include "omap_l3_smx.h"
+
+static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
+{
+        return __raw_readll(base + reg);
+}
+
+static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
+{
+        __raw_writell(value, base + reg);
+}
+
+static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
+{
+        return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
+}
+
+static inline u32 omap3_l3_decode_addr(u64 error_addr)
+{
+        return error_addr & 0xffffffff;
+}
+
+static inline unsigned omap3_l3_decode_cmd(u64 error)
+{
+        return (error & 0x07) >> L3_ERROR_LOG_CMD;
+}
+
+static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
+{
+        return (error & 0xff00) >> L3_ERROR_LOG_INITID;
+}
+
+static inline unsigned omap3_l3_decode_req_info(u64 error)
+{
+        return (error >> 32) & 0xffff;
+}
+
+static char *omap3_l3_code_string(u8 code)
+{
+        switch (code) {
+        case OMAP_L3_CODE_NOERROR:
+                return "No Error";
+        case OMAP_L3_CODE_UNSUP_CMD:
+                return "Unsupported Command";
+        case OMAP_L3_CODE_ADDR_HOLE:
+                return "Address Hole";
+        case OMAP_L3_CODE_PROTECT_VIOLATION:
+                return "Protection Violation";
+        case OMAP_L3_CODE_IN_BAND_ERR:
+                return "In-band Error";
+        case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
+                return "Request Timeout Not Accepted";
+        case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
+                return "Request Timeout, no response";
+        default:
+                return "UNKNOWN error";
+        }
+}
+
+static char *omap3_l3_initiator_string(u8 initid)
+{
+        switch (initid) {
+        case OMAP_L3_LCD:
+                return "LCD";
+        case OMAP_L3_SAD2D:
+                return "SAD2D";
+        case OMAP_L3_IA_MPU_SS_1:
+        case OMAP_L3_IA_MPU_SS_2:
+        case OMAP_L3_IA_MPU_SS_3:
+        case OMAP_L3_IA_MPU_SS_4:
+        case OMAP_L3_IA_MPU_SS_5:
+                return "MPU";
+        case OMAP_L3_IA_IVA_SS_1:
+        case OMAP_L3_IA_IVA_SS_2:
+        case OMAP_L3_IA_IVA_SS_3:
+                return "IVA_SS";
+        case OMAP_L3_IA_IVA_SS_DMA_1:
+        case OMAP_L3_IA_IVA_SS_DMA_2:
+        case OMAP_L3_IA_IVA_SS_DMA_3:
+        case OMAP_L3_IA_IVA_SS_DMA_4:
+        case OMAP_L3_IA_IVA_SS_DMA_5:
+        case OMAP_L3_IA_IVA_SS_DMA_6:
+                return "IVA_SS_DMA";
+        case OMAP_L3_IA_SGX:
+                return "SGX";
+        case OMAP_L3_IA_CAM_1:
+        case OMAP_L3_IA_CAM_2:
+        case OMAP_L3_IA_CAM_3:
+                return "CAM";
+        case OMAP_L3_IA_DAP:
+                return "DAP";
+        case OMAP_L3_SDMA_WR_1:
+        case OMAP_L3_SDMA_WR_2:
+                return "SDMA_WR";
+        case OMAP_L3_SDMA_RD_1:
+        case OMAP_L3_SDMA_RD_2:
+        case OMAP_L3_SDMA_RD_3:
+        case OMAP_L3_SDMA_RD_4:
+                return "SDMA_RD";
+        case OMAP_L3_USBOTG:
+                return "USB_OTG";
+        case OMAP_L3_USBHOST:
+                return "USB_HOST";
+        default:
+                return "UNKNOWN Initiator";
+        }
+}
+
+/**
+ * omap3_l3_block_irq - handles a register block's irq
+ * @l3: struct omap3_l3 *
+ * @base: register block base address
+ * @error: L3_ERROR_LOG register of our block
+ *
+ * Called in hard-irq context. Caller should take care of locking
+ *
+ * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
+ * Analysis Sequence, we are following that sequence here, please
+ * refer to that Figure for more information on the subject.
+ */
+static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
+                                        u64 error, int error_addr)
+{
+        u8                      code = omap3_l3_decode_error_code(error);
+        u8                      initid = omap3_l3_decode_initid(error);
+        u8                      multi = error & L3_ERROR_LOG_MULTI;
+        u32                     address = omap3_l3_decode_addr(error_addr);
+
+        WARN(true, "%s seen by %s %s at address %x\n",
+                                 omap3_l3_code_string(code),
+                          omap3_l3_initiator_string(initid),
+                             multi ? "Multiple Errors" : "",
+                                                   address);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
+{
+        struct omap3_l3         *l3 = _l3;
+        u64                     status, clear;
+        u64                     error;
+        u64                     error_addr;
+        u64                     err_source = 0;
+        void                    __iomem *base;
+        int                     int_type;
+        irqreturn_t             ret = IRQ_NONE;
+
+        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
+        if (!int_type) {
+                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
+                /*
+                 * if we have a timeout error, there's nothing we can
+                 * do besides rebooting the board. So let's BUG on any
+                 * of such errors and handle the others. timeout error
+                 * is severe and not expected to occur.
+                 */
+                BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
+        } else {
+                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
+                /* No timeout error for debug sources */
+        }
+
+        /* identify the error source */
+        for (err_source = 0; !(status & (1 << err_source)); err_source++)
+                                                                        ;
+
+        base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
+        error = omap3_l3_readll(base, L3_ERROR_LOG);
+        if (error) {
+                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
+
+                ret |= omap3_l3_block_irq(l3, error, error_addr);
+        }
+
+        /* Clear the status register */
+        clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
+                L3_AGENT_STATUS_CLEAR_TA;
+        omap3_l3_writell(base, L3_AGENT_STATUS, clear);
+
+        /* clear the error log register */
+        omap3_l3_writell(base, L3_ERROR_LOG, error);
+
+        return ret;
+}
+
+static int __init omap3_l3_probe(struct platform_device *pdev)
+{
+        struct omap3_l3         *l3;
+        struct resource         *res;
+        int                     ret;
+
+        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+        if (!l3)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, l3);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource\n");
+                ret = -ENODEV;
+                goto err0;
+        }
+        l3->rt = ioremap(res->start, resource_size(res));
+        if (!l3->rt) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err0;
+        }
+
+        l3->debug_irq = platform_get_irq(pdev, 0);
+        ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
+                IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                "l3-debug-irq", l3);
+        if (ret) {
+                dev_err(&pdev->dev, "couldn't request debug irq\n");
+                goto err1;
+        }
+
+        l3->app_irq = platform_get_irq(pdev, 1);
+        ret = request_irq(l3->app_irq, omap3_l3_app_irq,
+                IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                "l3-app-irq", l3);
+        if (ret) {
+                dev_err(&pdev->dev, "couldn't request app irq\n");
+                goto err2;
+        }
+
+        return 0;
+
+err2:
+        free_irq(l3->debug_irq, l3);
+err1:
+        iounmap(l3->rt);
+err0:
+        kfree(l3);
+        return ret;
+}
+
+static int __exit omap3_l3_remove(struct platform_device *pdev)
+{
+        struct omap3_l3         *l3 = platform_get_drvdata(pdev);
+
+        free_irq(l3->app_irq, l3);
+        free_irq(l3->debug_irq, l3);
+        iounmap(l3->rt);
+        kfree(l3);
+
+        return 0;
+}
+
+static struct platform_driver omap3_l3_driver = {
+        .remove         = __exit_p(omap3_l3_remove),
+        .driver         = {
+        .name   = "omap_l3_smx",
+        },
+};
+
+static int __init omap3_l3_init(void)
+{
+        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
+}
+postcore_initcall_sync(omap3_l3_init);
+
+static void __exit omap3_l3_exit(void)
+{
+        platform_driver_unregister(&omap3_l3_driver);
+}
+module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 000000000000..ba2ed9a850cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
+ /*
+  * OMAP3XXX L3 Interconnect Driver header
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Felipe Balbi <balbi@ti.com>
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+
+/* Register definitions. All 64-bit wide */
+#define L3_COMPONENT                    0x000
+#define L3_CORE                         0x018
+#define L3_AGENT_CONTROL                0x020
+#define L3_AGENT_STATUS                 0x028
+#define L3_ERROR_LOG                    0x058
+
+#define L3_ERROR_LOG_MULTI              (1 << 31)
+#define L3_ERROR_LOG_SECONDARY          (1 << 30)
+
+#define L3_ERROR_LOG_ADDR               0x060
+
+/* Register definitions for Sideband Interconnect */
+#define L3_SI_CONTROL                   0x020
+#define L3_SI_FLAG_STATUS_0             0x510
+
+const u64 shift = 1;
+
+#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
+#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
+#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
+#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
+#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
+#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
+#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
+#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
+#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
+#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
+#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
+#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
+#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
+#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
+#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
+#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
+#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
+#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
+#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
+#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
+#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
+#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
+#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
+#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
+#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
+#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
+#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
+#define L3_STATUS_0_IVATA_REQ           (shift << 54)
+#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
+#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
+#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
+#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
+#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
+#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
+#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
+
+#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
+                                        | L3_STATUS_0_MPUIA_RSP         \
+                                        | L3_STATUS_0_IVAIA_BRST        \
+                                        | L3_STATUS_0_IVAIA_RSP         \
+                                        | L3_STATUS_0_SGXIA_BRST        \
+                                        | L3_STATUS_0_SGXIA_RSP         \
+                                        | L3_STATUS_0_CAMIA_BRST        \
+                                        | L3_STATUS_0_CAMIA_RSP         \
+                                        | L3_STATUS_0_DISPIA_BRST       \
+                                        | L3_STATUS_0_DISPIA_RSP        \
+                                        | L3_STATUS_0_DMARDIA_BRST      \
+                                        | L3_STATUS_0_DMARDIA_RSP       \
+                                        | L3_STATUS_0_DMAWRIA_BRST      \
+                                        | L3_STATUS_0_DMAWRIA_RSP       \
+                                        | L3_STATUS_0_USBOTGIA_BRST     \
+                                        | L3_STATUS_0_USBOTGIA_RSP      \
+                                        | L3_STATUS_0_USBHOSTIA_BRST    \
+                                        | L3_STATUS_0_SMSTA_REQ         \
+                                        | L3_STATUS_0_GPMCTA_REQ        \
+                                        | L3_STATUS_0_OCMRAMTA_REQ      \
+                                        | L3_STATUS_0_OCMROMTA_REQ      \
+                                        | L3_STATUS_0_IVATA_REQ         \
+                                        | L3_STATUS_0_SGXTA_REQ         \
+                                        | L3_STATUS_0_L4CORETA_REQ      \
+                                        | L3_STATUS_0_L4PERTA_REQ       \
+                                        | L3_STATUS_0_L4EMUTA_REQ       \
+                                        | L3_STATUS_0_MAD2DTA_REQ)
+
+#define L3_SI_FLAG_STATUS_1             0x530
+
+#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
+#define L3_STATUS_1_DAPIA0              (1 << 3)
+#define L3_STATUS_1_DAPIA1              (1 << 4)
+#define L3_STATUS_1_IVAIA               (1 << 6)
+
+#define L3_PM_ERROR_LOG                 0x020
+#define L3_PM_CONTROL                   0x028
+#define L3_PM_ERROR_CLEAR_SINGLE        0x030
+#define L3_PM_ERROR_CLEAR_MULTI         0x038
+#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
+#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
+#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
+#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
+
+/* L3 error log bit fields. Common for IA and TA */
+#define L3_ERROR_LOG_CODE               24
+#define L3_ERROR_LOG_INITID             8
+#define L3_ERROR_LOG_CMD                0
+
+/* L3 agent status bit fields. */
+#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
+#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
+
+#define OMAP34xx_IRQ_L3_APP             10
+#define L3_APPLICATION_ERROR            0x0
+#define L3_DEBUG_ERROR                  0x1
+
+enum omap3_l3_initiator_id {
+        /* LCD has 1 ID */
+        OMAP_L3_LCD             = 29,
+        /* SAD2D has 1 ID */
+        OMAP_L3_SAD2D           = 28,
+        /* MPU has 5 IDs */
+        OMAP_L3_IA_MPU_SS_1     = 27,
+        OMAP_L3_IA_MPU_SS_2     = 26,
+        OMAP_L3_IA_MPU_SS_3     = 25,
+        OMAP_L3_IA_MPU_SS_4     = 24,
+        OMAP_L3_IA_MPU_SS_5     = 23,
+        /* IVA2.2 SS has 3 IDs*/
+        OMAP_L3_IA_IVA_SS_1     = 22,
+        OMAP_L3_IA_IVA_SS_2     = 21,
+        OMAP_L3_IA_IVA_SS_3     = 20,
+        /* IVA 2.2 SS DMA has 6 IDS */
+        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
+        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
+        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
+        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
+        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
+        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
+        /* SGX has 1 ID */
+        OMAP_L3_IA_SGX          = 13,
+        /* CAM has 3 ID */
+        OMAP_L3_IA_CAM_1        = 12,
+        OMAP_L3_IA_CAM_2        = 11,
+        OMAP_L3_IA_CAM_3        = 10,
+        /* DAP has 1 ID */
+        OMAP_L3_IA_DAP          = 9,
+        /* SDMA WR has 2 IDs */
+        OMAP_L3_SDMA_WR_1       = 8,
+        OMAP_L3_SDMA_WR_2       = 7,
+        /* SDMA RD has 4 IDs */
+        OMAP_L3_SDMA_RD_1       = 6,
+        OMAP_L3_SDMA_RD_2       = 5,
+        OMAP_L3_SDMA_RD_3       = 4,
+        OMAP_L3_SDMA_RD_4       = 3,
+        /* HSUSB OTG has 1 ID */
+        OMAP_L3_USBOTG          = 2,
+        /* HSUSB HOST has 1 ID */
+        OMAP_L3_USBHOST         = 1,
+};
+
+enum omap3_l3_code {
+        OMAP_L3_CODE_NOERROR = 0,
+        OMAP_L3_CODE_UNSUP_CMD = 1,
+        OMAP_L3_CODE_ADDR_HOLE = 2,
+        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
+        OMAP_L3_CODE_IN_BAND_ERR = 4,
+        /* codes 5 and 6 are reserved */
+        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
+        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
+        /* codes 9 - 15 are also reserved */
+};
+
+struct omap3_l3 {
+        struct device   *dev;
+        struct clk      *ick;
+
+        /* memory base*/
+        void __iomem    *rt;
+
+        int             debug_irq;
+        int             app_irq;
+
+        /* true when and inband functional error occurs */
+        unsigned        inband:1;
+};
+
+/* offsets for l3 agents in order with the Flag status register */
+unsigned int __iomem omap3_l3_app_bases[] = {
+        /* MPU IA */
+        0x1400,
+        0x1400,
+        0x1400,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        /* IVA 2.2 IA */
+        0x1800,
+        0x1800,
+        0x1800,
+        /* SGX IA */
+        0x1c00,
+        0x1c00,
+        /* RESERVED */
+        0,
+        /* CAMERA IA */
+        0x5800,
+        0x5800,
+        0x5800,
+        /* DISPLAY IA */
+        0x5400,
+        0x5400,
+        /* RESERVED */
+        0,
+        /*SDMA RD IA */
+        0x4c00,
+        0x4c00,
+        /* RESERVED */
+        0,
+        /* SDMA WR IA */
+        0x5000,
+        0x5000,
+        /* RESERVED */
+        0,
+        /* USB OTG IA */
+        0x4400,
+        0x4400,
+        0x4400,
+        /* USB HOST IA */
+        0x4000,
+        0x4000,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        0,
+        /* SAD2D IA */
+        0x3000,
+        0x3000,
+        0x3000,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        /* SMA TA */
+        0x2000,
+        /* GPMC TA */
+        0x2400,
+        /* OCM RAM TA */
+        0x2800,
+        /* OCM ROM TA */
+        0x2C00,
+        /* L4 CORE TA */
+        0x6800,
+        /* L4 PER TA */
+        0x6c00,
+        /* IVA 2.2 TA */
+        0x6000,
+        /* SGX TA */
+        0x6400,
+        /* L4 EMU TA */
+        0x7000,
+        /* GPMC TA */
+        0x2400,
+        /* L4 CORE TA */
+        0x6800,
+        /* L4 PER TA */
+        0x6c00,
+        /* L4 EMU TA */
+        0x7000,
+        /* MAD2D TA */
+        0x3400,
+        /* RESERVED */
+        0,
+        0,
+};
+
+unsigned int __iomem omap3_l3_debug_bases[] = {
+        /* MPU DATA IA */
+        0x1400,
+        /* RESERVED */
+        0,
+        0,
+        /* DAP IA */
+        0x5c00,
+        0x5c00,
+        /* RESERVED */
+        0,
+        /* IVA 2.2 IA */
+        0x1800,
+        /* REST RESERVED */
+};
+
+u32 *omap3_l3_bases[] = {
+        omap3_l3_app_bases,
+        omap3_l3_debug_bases,
+};
+
+/*
+ * REVISIT define __raw_readll/__raw_writell here, but move them to
+ * <asm/io.h> at some point
+ */
+#define __raw_writell(v, a)     (__chk_io_ptr(a), \
+                                *(volatile u64 __force *)(a) = (v))
+#define __raw_readll(a)         (__chk_io_ptr(a), \
+                                *(volatile u64 __force *)(a))
+
+#endif
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
new file mode 100644
index 000000000000..c784c12f98a1
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -0,0 +1,96 @@
+/*
+ * OMAP SoC specific OPP Data helpers
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+
+#include <plat/omap_hwmod.h>
+
+#include "voltage.h"
+
+/*
+ * *BIG FAT WARNING*:
+ * USE the following ONLY in opp data initialization common to an SoC.
+ * DO NOT USE these in board files/pm core etc.
+ */
+
+/**
+ * struct omap_opp_def - OMAP OPP Definition
+ * @hwmod_name: Name of the hwmod for this domain
+ * @freq:       Frequency in hertz corresponding to this OPP
+ * @u_volt:     Nominal voltage in microvolts corresponding to this OPP
+ * @default_available:  True/false - is this OPP available by default
+ *
+ * OMAP SOCs have a standard set of tuples consisting of frequency and voltage
+ * pairs that the device will support per voltage domain. This is called
+ * Operating Points or OPP. The actual definitions of OMAP Operating Points
+ * varies over silicon within the same family of devices. For a specific
+ * domain, you can have a set of {frequency, voltage} pairs and this is denoted
+ * by an array of omap_opp_def. As the kernel boots and more information is
+ * available, a set of these are activated based on the precise nature of
+ * device the kernel boots up on. It is interesting to remember that each IP
+ * which belongs to a voltage domain may define their own set of OPPs on top
+ * of this - but this is handled by the appropriate driver.
+ */
+struct omap_opp_def {
+        char *hwmod_name;
+
+        unsigned long freq;
+        unsigned long u_volt;
+
+        bool default_available;
+};
+
+/*
+ * Initialization wrapper used to define an OPP for OMAP variants.
+ */
+#define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv)      \
+{                                                               \
+        .hwmod_name     = _hwmod_name,                          \
+        .default_available      = _enabled,                     \
+        .freq           = _freq,                                \
+        .u_volt         = _uv,                                  \
+}
+
+/*
+ * Initialization wrapper used to define SmartReflex process data
+ * XXX Is this needed?  Just use C99 initializers in data files?
+ */
+#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain)  \
+{                                                                      \
+        .volt_nominal   = _v_nom,                                      \
+        .sr_efuse_offs  = _efuse_offs,                                 \
+        .sr_errminlimit = _errminlimit,                                \
+        .vp_errgain     = _errgain                                     \
+}
+
+/* Use this to initialize the default table */
+extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+                u32 opp_def_size);
+
+
+extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
+extern struct omap_volt_data omap34xx_vddcore_volt_data[];
+extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
+extern struct omap_volt_data omap36xx_vddcore_volt_data[];
+
+extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
+extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
+extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
+
+#endif          /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
new file mode 100644
index 000000000000..58775e3c8476
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -0,0 +1,262 @@
+/*
+  * This file configures the internal USB PHY in OMAP4430. Used
+  * with TWL6030 transceiver and MUSB on OMAP4430.
+  *
+  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * Author: Hema HK <hemahk@ti.com>
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  *
+  */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/usb.h>
+
+#include <plat/usb.h>
+#include "control.h"
+
+/* OMAP control module register for UTMI PHY */
+#define CONTROL_DEV_CONF                0x300
+#define PHY_PD                          0x1
+
+#define USBOTGHS_CONTROL                0x33c
+#define AVALID                          BIT(0)
+#define BVALID                          BIT(1)
+#define VBUSVALID                       BIT(2)
+#define SESSEND                         BIT(3)
+#define IDDIG                           BIT(4)
+
+static struct clk *phyclk, *clk48m, *clk32k;
+static void __iomem *ctrl_base;
+static int usbotghs_control;
+
+int omap4430_phy_init(struct device *dev)
+{
+        ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
+        if (!ctrl_base) {
+                pr_err("control module ioremap failed\n");
+                return -ENOMEM;
+        }
+        /* Power down the phy */
+        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+
+        if (!dev) {
+                iounmap(ctrl_base);
+                return 0;
+        }
+
+        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
+        if (IS_ERR(phyclk)) {
+                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
+                iounmap(ctrl_base);
+                return PTR_ERR(phyclk);
+        }
+
+        clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
+        if (IS_ERR(clk48m)) {
+                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
+                clk_put(phyclk);
+                iounmap(ctrl_base);
+                return PTR_ERR(clk48m);
+        }
+
+        clk32k = clk_get(dev, "usb_phy_cm_clk32k");
+        if (IS_ERR(clk32k)) {
+                dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
+                clk_put(phyclk);
+                clk_put(clk48m);
+                iounmap(ctrl_base);
+                return PTR_ERR(clk32k);
+        }
+        return 0;
+}
+
+int omap4430_phy_set_clk(struct device *dev, int on)
+{
+        static int state;
+
+        if (on && !state) {
+                /* Enable the phy clocks */
+                clk_enable(phyclk);
+                clk_enable(clk48m);
+                clk_enable(clk32k);
+                state = 1;
+        } else if (state) {
+                /* Disable the phy clocks */
+                clk_disable(phyclk);
+                clk_disable(clk48m);
+                clk_disable(clk32k);
+                state = 0;
+        }
+        return 0;
+}
+
+int omap4430_phy_power(struct device *dev, int ID, int on)
+{
+        if (on) {
+                if (ID)
+                        /* enable VBUS valid, IDDIG groung */
+                        __raw_writel(AVALID | VBUSVALID, ctrl_base +
+                                                        USBOTGHS_CONTROL);
+                else
+                        /*
+                         * Enable VBUS Valid, AValid and IDDIG
+                         * high impedance
+                         */
+                        __raw_writel(IDDIG | AVALID | VBUSVALID,
+                                                ctrl_base + USBOTGHS_CONTROL);
+        } else {
+                /* Enable session END and IDIG to high impedance. */
+                __raw_writel(SESSEND | IDDIG, ctrl_base +
+                                        USBOTGHS_CONTROL);
+        }
+        return 0;
+}
+
+int omap4430_phy_suspend(struct device *dev, int suspend)
+{
+        if (suspend) {
+                /* Disable the clocks */
+                omap4430_phy_set_clk(dev, 0);
+                /* Power down the phy */
+                __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+
+                /* save the context */
+                usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
+        } else {
+                /* Enable the internel phy clcoks */
+                omap4430_phy_set_clk(dev, 1);
+                /* power on the phy */
+                if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
+                        __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+                        mdelay(200);
+                }
+
+                /* restore the context */
+                __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
+        }
+
+        return 0;
+}
+
+int omap4430_phy_exit(struct device *dev)
+{
+        if (ctrl_base)
+                iounmap(ctrl_base);
+        if (phyclk)
+                clk_put(phyclk);
+        if (clk48m)
+                clk_put(clk48m);
+        if (clk32k)
+                clk_put(clk32k);
+
+        return 0;
+}
+
+void am35x_musb_reset(void)
+{
+        u32     regval;
+
+        /* Reset the musb interface */
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+
+        regval |= AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+
+        regval &= ~AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+}
+
+void am35x_musb_phy_power(u8 on)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(100);
+        u32 devconf2;
+
+        if (on) {
+                /*
+                 * Start the on-chip PHY and its PLL.
+                 */
+                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+                devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+                devconf2 |= CONF2_PHY_PLLON;
+
+                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+
+                pr_info(KERN_INFO "Waiting for PHY clock good...\n");
+                while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
+                                & CONF2_PHYCLKGD)) {
+                        cpu_relax();
+
+                        if (time_after(jiffies, timeout)) {
+                                pr_err(KERN_ERR "musb PHY clock good timed out\n");
+                                break;
+                        }
+                }
+        } else {
+                /*
+                 * Power down the on-chip PHY.
+                 */
+                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+                devconf2 &= ~CONF2_PHY_PLLON;
+                devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
+                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+        }
+}
+
+void am35x_musb_clear_irq(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval |= AM35XX_USBOTGSS_INT_CLR;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+void am35x_set_mode(u8 musb_mode)
+{
+        u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        devconf2 &= ~CONF2_OTGMODE;
+        switch (musb_mode) {
+#ifdef  CONFIG_USB_MUSB_HDRC_HCD
+        case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
+                devconf2 |= CONF2_FORCE_HOST;
+                break;
+#endif
+#ifdef  CONFIG_USB_GADGET_MUSB_HDRC
+        case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
+                devconf2 |= CONF2_FORCE_DEVICE;
+                break;
+#endif
+#ifdef  CONFIG_USB_MUSB_OTG
+        case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
+                devconf2 |= CONF2_NO_OVERRIDE;
+                break;
+#endif
+        default:
+                pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
+        }
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+}
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
new file mode 100644
index 000000000000..07d6140baa9d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -0,0 +1,339 @@
+/**
+ * OMAP and TWL PMIC specific intializations.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated.
+ * Thara Gopinath
+ * Copyright (C) 2009 Texas Instruments Incorporated.
+ * Nishanth Menon
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/i2c/twl.h>
+
+#include "voltage.h"
+
+#include "pm.h"
+
+#define OMAP3_SRI2C_SLAVE_ADDR          0x12
+#define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
+#define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
+#define OMAP3_VP_CONFIG_ERROROFFSET     0x00
+#define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
+#define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
+#define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
+
+#define OMAP3430_VP1_VLIMITTO_VDDMIN    0x14
+#define OMAP3430_VP1_VLIMITTO_VDDMAX    0x42
+#define OMAP3430_VP2_VLIMITTO_VDDMIN    0x18
+#define OMAP3430_VP2_VLIMITTO_VDDMAX    0x2c
+
+#define OMAP3630_VP1_VLIMITTO_VDDMIN    0x18
+#define OMAP3630_VP1_VLIMITTO_VDDMAX    0x3c
+#define OMAP3630_VP2_VLIMITTO_VDDMIN    0x18
+#define OMAP3630_VP2_VLIMITTO_VDDMAX    0x30
+
+#define OMAP4_SRI2C_SLAVE_ADDR          0x12
+#define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
+#define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
+#define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
+
+#define OMAP4_VP_CONFIG_ERROROFFSET     0x00
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
+
+#define OMAP4_VP_MPU_VLIMITTO_VDDMIN    0xA
+#define OMAP4_VP_MPU_VLIMITTO_VDDMAX    0x39
+#define OMAP4_VP_IVA_VLIMITTO_VDDMIN    0xA
+#define OMAP4_VP_IVA_VLIMITTO_VDDMAX    0x2D
+#define OMAP4_VP_CORE_VLIMITTO_VDDMIN   0xA
+#define OMAP4_VP_CORE_VLIMITTO_VDDMAX   0x28
+
+static bool is_offset_valid;
+static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool __initdata twl_sr_enable_autoinit;
+
+#define TWL4030_DCDC_GLOBAL_CFG        0x06
+#define REG_SMPS_OFFSET         0xE0
+#define SMARTREFLEX_ENABLE     BIT(3)
+
+static unsigned long twl4030_vsel_to_uv(const u8 vsel)
+{
+        return (((vsel * 125) + 6000)) * 100;
+}
+
+static u8 twl4030_uv_to_vsel(unsigned long uv)
+{
+        return DIV_ROUND_UP(uv - 600000, 12500);
+}
+
+static unsigned long twl6030_vsel_to_uv(const u8 vsel)
+{
+        /*
+         * In TWL6030 depending on the value of SMPS_OFFSET
+         * efuse register the voltage range supported in
+         * standard mode can be either between 0.6V - 1.3V or
+         * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+         * is programmed to all 0's where as starting from
+         * TWL6030 ES1.1 the efuse is programmed to 1
+         */
+        if (!is_offset_valid) {
+                twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+                                REG_SMPS_OFFSET);
+                is_offset_valid = true;
+        }
+
+        /*
+         * There is no specific formula for voltage to vsel
+         * conversion above 1.3V. There are special hardcoded
+         * values for voltages above 1.3V. Currently we are
+         * hardcoding only for 1.35 V which is used for 1GH OPP for
+         * OMAP4430.
+         */
+        if (vsel == 0x3A)
+                return 1350000;
+
+        if (smps_offset & 0x8)
+                return ((((vsel - 1) * 125) + 7000)) * 100;
+        else
+                return ((((vsel - 1) * 125) + 6000)) * 100;
+}
+
+static u8 twl6030_uv_to_vsel(unsigned long uv)
+{
+        /*
+         * In TWL6030 depending on the value of SMPS_OFFSET
+         * efuse register the voltage range supported in
+         * standard mode can be either between 0.6V - 1.3V or
+         * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+         * is programmed to all 0's where as starting from
+         * TWL6030 ES1.1 the efuse is programmed to 1
+         */
+        if (!is_offset_valid) {
+                twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+                                REG_SMPS_OFFSET);
+                is_offset_valid = true;
+        }
+
+        /*
+         * There is no specific formula for voltage to vsel
+         * conversion above 1.3V. There are special hardcoded
+         * values for voltages above 1.3V. Currently we are
+         * hardcoding only for 1.35 V which is used for 1GH OPP for
+         * OMAP4430.
+         */
+        if (uv == 1350000)
+                return 0x3A;
+
+        if (smps_offset & 0x8)
+                return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+        else
+                return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+}
+
+static struct omap_volt_pmic_info omap3_mpu_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1200000,
+        .onlp_volt              = 1000000,
+        .ret_volt               = 975000,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0xfff,
+        .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP3430_VP1_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP3_VDD_MPU_SR_CONTROL_REG,
+        .vsel_to_uv             = twl4030_vsel_to_uv,
+        .uv_to_vsel             = twl4030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap3_core_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1200000,
+        .onlp_volt              = 1000000,
+        .ret_volt               = 975000,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0xfff,
+        .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP3430_VP2_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP3_VDD_CORE_SR_CONTROL_REG,
+        .vsel_to_uv             = twl4030_vsel_to_uv,
+        .uv_to_vsel             = twl4030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_mpu_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1350000,
+        .onlp_volt              = 1350000,
+        .ret_volt               = 837500,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0,
+        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP4_VDD_MPU_SR_VOLT_REG,
+        .vsel_to_uv             = twl6030_vsel_to_uv,
+        .uv_to_vsel             = twl6030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_iva_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1100000,
+        .onlp_volt              = 1100000,
+        .ret_volt               = 837500,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0,
+        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP4_VDD_IVA_SR_VOLT_REG,
+        .vsel_to_uv             = twl6030_vsel_to_uv,
+        .uv_to_vsel             = twl6030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_core_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1100000,
+        .onlp_volt              = 1100000,
+        .ret_volt               = 837500,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0,
+        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP4_VDD_CORE_SR_VOLT_REG,
+        .vsel_to_uv             = twl6030_vsel_to_uv,
+        .uv_to_vsel             = twl6030_uv_to_vsel,
+};
+
+int __init omap4_twl_init(void)
+{
+        struct voltagedomain *voltdm;
+
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        voltdm = omap_voltage_domain_lookup("mpu");
+        omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
+
+        voltdm = omap_voltage_domain_lookup("iva");
+        omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
+
+        voltdm = omap_voltage_domain_lookup("core");
+        omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
+
+        return 0;
+}
+
+int __init omap3_twl_init(void)
+{
+        struct voltagedomain *voltdm;
+
+        if (!cpu_is_omap34xx())
+                return -ENODEV;
+
+        if (cpu_is_omap3630()) {
+                omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
+                omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
+                omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
+                omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
+        }
+
+        /*
+         * The smartreflex bit on twl4030 specifies if the setting of voltage
+         * is done over the I2C_SR path. Since this setting is independent of
+         * the actual usage of smartreflex AVS module, we enable TWL SR bit
+         * by default irrespective of whether smartreflex AVS module is enabled
+         * on the OMAP side or not. This is because without this bit enabled,
+         * the voltage scaling through vp forceupdate/bypass mechanism of
+         * voltage scaling will not function on TWL over I2C_SR.
+         */
+        if (!twl_sr_enable_autoinit)
+                omap3_twl_set_sr_bit(true);
+
+        voltdm = omap_voltage_domain_lookup("mpu");
+        omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
+
+        voltdm = omap_voltage_domain_lookup("core");
+        omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
+
+        return 0;
+}
+
+/**
+ * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
+ * @enable: enable SR mode in twl or not
+ *
+ * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
+ * voltage scaling through OMAP SR works. Else, the smartreflex bit
+ * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
+ * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
+ * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared (enable = false).
+ *
+ * Returns 0 on success, error is returned if I2C read/write fails.
+ */
+int __init omap3_twl_set_sr_bit(bool enable)
+{
+        u8 temp;
+        int ret;
+        if (twl_sr_enable_autoinit)
+                pr_warning("%s: unexpected multiple calls\n", __func__);
+
+        ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
+                                        TWL4030_DCDC_GLOBAL_CFG);
+        if (ret)
+                goto err;
+
+        if (enable)
+                temp |= SMARTREFLEX_ENABLE;
+        else
+                temp &= ~SMARTREFLEX_ENABLE;
+
+        ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+                                TWL4030_DCDC_GLOBAL_CFG);
+        if (!ret) {
+                twl_sr_enable_autoinit = true;
+                return 0;
+        }
+err:
+        pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
+        return ret;
+}
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
new file mode 100644
index 000000000000..ab8b35b780b5
--- /dev/null
+++ b/arch/arm/mach-omap2/opp.c
@@ -0,0 +1,93 @@
+/*
+ * OMAP SoC specific OPP wrapper function
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/opp.h>
+
+#include <plat/omap_device.h>
+
+#include "omap_opp_data.h"
+
+/* Temp variable to allow multiple calls */
+static u8 __initdata omap_table_init;
+
+/**
+ * omap_init_opp_table() - Initialize opp table as per the CPU type
+ * @opp_def:            opp default list for this silicon
+ * @opp_def_size:       number of opp entries for this silicon
+ *
+ * Register the initial OPP table with the OPP library based on the CPU
+ * type. This is meant to be used only by SoC specific registration.
+ */
+int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+                u32 opp_def_size)
+{
+        int i, r;
+
+        if (!opp_def || !opp_def_size) {
+                pr_err("%s: invalid params!\n", __func__);
+                return -EINVAL;
+        }
+
+        /*
+         * Initialize only if not already initialized even if the previous
+         * call failed, because, no reason we'd succeed again.
+         */
+        if (omap_table_init)
+                return -EEXIST;
+        omap_table_init = 1;
+
+        /* Lets now register with OPP library */
+        for (i = 0; i < opp_def_size; i++) {
+                struct omap_hwmod *oh;
+                struct device *dev;
+
+                if (!opp_def->hwmod_name) {
+                        pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
+                                __func__, i);
+                        return -EINVAL;
+                }
+                oh = omap_hwmod_lookup(opp_def->hwmod_name);
+                if (!oh || !oh->od) {
+                        pr_warn("%s: no hwmod or odev for %s, [%d] "
+                                "cannot add OPPs.\n", __func__,
+                                opp_def->hwmod_name, i);
+                        return -EINVAL;
+                }
+                dev = &oh->od->pdev.dev;
+
+                r = opp_add(dev, opp_def->freq, opp_def->u_volt);
+                if (r) {
+                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
+                                "result=%d\n",
+                               __func__, opp_def->freq,
+                               opp_def->hwmod_name, i, r);
+                } else {
+                        if (!opp_def->default_available)
+                                r = opp_disable(dev, opp_def->freq);
+                        if (r)
+                                dev_err(dev, "%s: disable %ld failed for %s "
+                                        "[%d] result=%d\n",
+                                        __func__, opp_def->freq,
+                                        opp_def->hwmod_name, i, r);
+                }
+                opp_def++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 38b730550506..8affc66a92c2 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -418,7 +418,7 @@ struct prcm_config {
 
 extern const struct prcm_config omap2420_rate_table[];
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 extern const struct prcm_config omap2430_rate_table[];
 #else
 #define omap2430_rate_table     NULL
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
new file mode 100644
index 000000000000..d95f3f945d4a
--- /dev/null
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -0,0 +1,172 @@
+/*
+ * OMAP3 OPP table definitions.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010-2011 Nokia Corporation.
+ *      Eduardo Valentin
+ *      Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+
+#include <plat/cpu.h>
+
+#include "control.h"
+#include "omap_opp_data.h"
+#include "pm.h"
+
+/* 34xx */
+
+/* VDD1 */
+
+#define OMAP3430_VDD_MPU_OPP1_UV                975000
+#define OMAP3430_VDD_MPU_OPP2_UV                1075000
+#define OMAP3430_VDD_MPU_OPP3_UV                1200000
+#define OMAP3430_VDD_MPU_OPP4_UV                1270000
+#define OMAP3430_VDD_MPU_OPP5_UV                1350000
+
+struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+/* VDD2 */
+
+#define OMAP3430_VDD_CORE_OPP1_UV               975000
+#define OMAP3430_VDD_CORE_OPP2_UV               1050000
+#define OMAP3430_VDD_CORE_OPP3_UV               1150000
+
+struct omap_volt_data omap34xx_vddcore_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+/* 36xx */
+
+/* VDD1 */
+
+#define OMAP3630_VDD_MPU_OPP50_UV               1012500
+#define OMAP3630_VDD_MPU_OPP100_UV              1200000
+#define OMAP3630_VDD_MPU_OPP120_UV              1325000
+#define OMAP3630_VDD_MPU_OPP1G_UV               1375000
+
+struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+/* VDD2 */
+
+#define OMAP3630_VDD_CORE_OPP50_UV              1000000
+#define OMAP3630_VDD_CORE_OPP100_UV             1200000
+
+struct omap_volt_data omap36xx_vddcore_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+/* OPP data */
+
+static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
+        /* MPU OPP1 */
+        OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
+        /* MPU OPP2 */
+        OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
+        /* MPU OPP3 */
+        OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
+        /* MPU OPP4 */
+        OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
+        /* MPU OPP5 */
+        OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
+
+        /*
+         * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
+         * almost the same than the one at 83MHz thus providing very little
+         * gain for the power point of view. In term of energy it will even
+         * increase the consumption due to the very negative performance
+         * impact that frequency will do to the MPU and the whole system in
+         * general.
+         */
+        OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
+        /* L3 OPP2 */
+        OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
+        /* L3 OPP3 */
+        OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
+
+        /* DSP OPP1 */
+        OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
+        /* DSP OPP2 */
+        OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
+        /* DSP OPP3 */
+        OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
+        /* DSP OPP4 */
+        OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
+        /* DSP OPP5 */
+        OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
+};
+
+static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true,  300000000, OMAP3630_VDD_MPU_OPP50_UV),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true,  600000000, OMAP3630_VDD_MPU_OPP100_UV),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
+        /* MPU OPP4 - OPP-SB */
+        OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
+
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
+        /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+        OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
+
+        /* DSP OPP1 - OPP50 */
+        OPP_INITIALIZER("iva", true,  260000000, OMAP3630_VDD_MPU_OPP50_UV),
+        /* DSP OPP2 - OPP100 */
+        OPP_INITIALIZER("iva", true,  520000000, OMAP3630_VDD_MPU_OPP100_UV),
+        /* DSP OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
+        /* DSP OPP4 - OPP-SB */
+        OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
+};
+
+/**
+ * omap3_opp_init() - initialize omap3 opp table
+ */
+int __init omap3_opp_init(void)
+{
+        int r = -ENODEV;
+
+        if (!cpu_is_omap34xx())
+                return r;
+
+        if (cpu_is_omap3630())
+                r = omap_init_opp_table(omap36xx_opp_def_list,
+                        ARRAY_SIZE(omap36xx_opp_def_list));
+        else
+                r = omap_init_opp_table(omap34xx_opp_def_list,
+                        ARRAY_SIZE(omap34xx_opp_def_list));
+
+        return r;
+}
+device_initcall(omap3_opp_init);
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
new file mode 100644
index 000000000000..2293ba27101b
--- /dev/null
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -0,0 +1,105 @@
+/*
+ * OMAP4 OPP table definitions.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ *      Thara Gopinath
+ * Copyright (C) 2010-2011 Nokia Corporation.
+ *      Eduardo Valentin
+ *      Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+
+#include <plat/cpu.h>
+
+#include "control.h"
+#include "omap_opp_data.h"
+#include "pm.h"
+
+/*
+ * Structures containing OMAP4430 voltage supported and various
+ * voltage dependent data for each VDD.
+ */
+
+#define OMAP4430_VDD_MPU_OPP50_UV               1025000
+#define OMAP4430_VDD_MPU_OPP100_UV              1200000
+#define OMAP4430_VDD_MPU_OPPTURBO_UV            1313000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV            1375000
+
+struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+#define OMAP4430_VDD_IVA_OPP50_UV               1013000
+#define OMAP4430_VDD_IVA_OPP100_UV              1188000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV            1300000
+
+struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+#define OMAP4430_VDD_CORE_OPP50_UV              1025000
+#define OMAP4430_VDD_CORE_OPP100_UV             1200000
+
+struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+
+static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
+        /* MPU OPP4 - OPP-SB */
+        OPP_INITIALIZER("mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
+        /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+        OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
+        /* IVA OPP1 - OPP50 */
+        OPP_INITIALIZER("iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
+        /* IVA OPP2 - OPP100 */
+        OPP_INITIALIZER("iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
+        /* IVA OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
+        /* TODO: add DSP, aess, fdif, gpu */
+};
+
+/**
+ * omap4_opp_init() - initialize omap4 opp table
+ */
+int __init omap4_opp_init(void)
+{
+        int r = -ENODEV;
+
+        if (!cpu_is_omap44xx())
+                return r;
+
+        r = omap_init_opp_table(omap44xx_opp_def_list,
+                        ARRAY_SIZE(omap44xx_opp_def_list));
+
+        return r;
+}
+device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 723b44e252fd..e01da45c0537 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -29,21 +29,27 @@
 
 #include <plat/clock.h>
 #include <plat/board.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
+#include <plat/dmtimer.h>
+#include <plat/omap-pm.h>
 
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "pm.h"
 
 int omap2_pm_debug;
+u32 enable_off_mode;
+u32 sleep_while_idle;
+u32 wakeup_timer_seconds;
+u32 wakeup_timer_milliseconds;
 
 #define DUMP_PRM_MOD_REG(mod, reg)    \
         regs[reg_count].name = #mod "." #reg; \
-        regs[reg_count++].val = prm_read_mod_reg(mod, reg)
+        regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
 #define DUMP_CM_MOD_REG(mod, reg)     \
         regs[reg_count].name = #mod "." #reg; \
-        regs[reg_count++].val = cm_read_mod_reg(mod, reg)
+        regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
 #define DUMP_PRM_REG(reg) \
         regs[reg_count].name = #reg; \
         regs[reg_count++].val = __raw_readl(reg)
@@ -156,17 +162,34 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
                 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 }
 
+void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+{
+        u32 tick_rate, cycles;
+
+        if (!seconds && !milliseconds)
+                return;
+
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+        omap_dm_timer_stop(gptimer_wakeup);
+        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+
+        pr_info("PM: Resume timer in %u.%03u secs"
+                " (%d ticks at %d ticks/sec.)\n",
+                seconds, milliseconds, cycles, tick_rate);
+}
+
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 
 static void pm_dbg_regset_store(u32 *ptr);
 
-struct dentry *pm_dbg_dir;
+static struct dentry *pm_dbg_dir;
 
 static int pm_dbg_init_done;
 
-static int __init pm_dbg_init(void);
+static int pm_dbg_init(void);
 
 enum {
         DEBUG_FILE_COUNTERS = 0,
@@ -306,10 +329,10 @@ static void pm_dbg_regset_store(u32 *ptr)
                 for (j = pm_dbg_reg_modules[i].low;
                         j <= pm_dbg_reg_modules[i].high; j += 4) {
                         if (pm_dbg_reg_modules[i].type == MOD_CM)
-                                val = cm_read_mod_reg(
+                                val = omap2_cm_read_mod_reg(
                                         pm_dbg_reg_modules[i].offset, j);
                         else
-                                val = prm_read_mod_reg(
+                                val = omap2_prm_read_mod_reg(
                                         pm_dbg_reg_modules[i].offset, j);
                         *(ptr++) = val;
                 }
@@ -494,8 +517,10 @@ int pm_dbg_regset_init(int reg_set)
 
 static int pwrdm_suspend_get(void *data, u64 *val)
 {
-        int ret;
-        ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
+        int ret = -EINVAL;
+
+        if (cpu_is_omap34xx())
+                ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
         *val = ret;
 
         if (ret >= 0)
@@ -505,7 +530,10 @@ static int pwrdm_suspend_get(void *data, u64 *val)
 
 static int pwrdm_suspend_set(void *data, u64 val)
 {
-        return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
+        if (cpu_is_omap34xx())
+                return omap3_pm_set_suspend_state(
+                        (struct powerdomain *)data, (int)val);
+        return -EINVAL;
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
@@ -553,15 +581,21 @@ static int option_set(void *data, u64 val)
 
         *option = val;
 
-        if (option == &enable_off_mode)
-                omap3_pm_off_mode_enable(val);
+        if (option == &enable_off_mode) {
+                if (val)
+                        omap_pm_enable_off_mode();
+                else
+                        omap_pm_disable_off_mode();
+                if (cpu_is_omap34xx())
+                        omap3_pm_off_mode_enable(val);
+        }
 
         return 0;
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
 
-static int __init pm_dbg_init(void)
+static int pm_dbg_init(void)
 {
         int i;
         struct dentry *d;
@@ -603,12 +637,15 @@ static int __init pm_dbg_init(void)
 
                 }
 
-        (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
                                    &enable_off_mode, &pm_dbg_option_fops);
-        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
                                    &sleep_while_idle, &pm_dbg_option_fops);
-        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
                                    &wakeup_timer_seconds, &pm_dbg_option_fops);
+        (void) debugfs_create_file("wakeup_timer_milliseconds",
+                        S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
+                        &pm_dbg_option_fops);
         pm_dbg_init_done = 1;
 
         return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 68f9f2e95891..49486f522dca 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -13,16 +13,23 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/opp.h>
 
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 #include <plat/common.h>
 
+#include "voltage.h"
+#include "powerdomain.h"
+#include "clockdomain.h"
+#include "pm.h"
+
 static struct omap_device_pm_latency *pm_lats;
 
 static struct device *mpu_dev;
-static struct device *dsp_dev;
+static struct device *iva_dev;
 static struct device *l3_dev;
+static struct device *dsp_dev;
 
 struct device *omap2_get_mpuss_device(void)
 {
@@ -30,10 +37,10 @@ struct device *omap2_get_mpuss_device(void)
         return mpu_dev;
 }
 
-struct device *omap2_get_dsp_device(void)
+struct device *omap2_get_iva_device(void)
 {
-        WARN_ON_ONCE(!dsp_dev);
-        return dsp_dev;
+        WARN_ON_ONCE(!iva_dev);
+        return iva_dev;
 }
 
 struct device *omap2_get_l3_device(void)
@@ -42,6 +49,13 @@ struct device *omap2_get_l3_device(void)
         return l3_dev;
 }
 
+struct device *omap4_get_dsp_device(void)
+{
+        WARN_ON_ONCE(!dsp_dev);
+        return dsp_dev;
+}
+EXPORT_SYMBOL(omap4_get_dsp_device);
+
 /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
 static int _init_omap_device(char *name, struct device **new_dev)
 {
@@ -69,8 +83,161 @@ static int _init_omap_device(char *name, struct device **new_dev)
 static void omap2_init_processor_devices(void)
 {
         _init_omap_device("mpu", &mpu_dev);
-        _init_omap_device("iva", &dsp_dev);
-        _init_omap_device("l3_main", &l3_dev);
+        if (omap3_has_iva())
+                _init_omap_device("iva", &iva_dev);
+
+        if (cpu_is_omap44xx()) {
+                _init_omap_device("l3_main_1", &l3_dev);
+                _init_omap_device("dsp", &dsp_dev);
+                _init_omap_device("iva", &iva_dev);
+        } else {
+                _init_omap_device("l3_main", &l3_dev);
+        }
+}
+
+/* Types of sleep_switch used in omap_set_pwrdm_state */
+#define FORCEWAKEUP_SWITCH      0
+#define LOWPOWERSTATE_SWITCH    1
+
+/*
+ * This sets pwrdm state (other than mpu & core. Currently only ON &
+ * RET are supported.
+ */
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+{
+        u32 cur_state;
+        int sleep_switch = 0;
+        int ret = 0;
+
+        if (pwrdm == NULL || IS_ERR(pwrdm))
+                return -EINVAL;
+
+        while (!(pwrdm->pwrsts & (1 << state))) {
+                if (state == PWRDM_POWER_OFF)
+                        return ret;
+                state--;
+        }
+
+        cur_state = pwrdm_read_next_pwrst(pwrdm);
+        if (cur_state == state)
+                return ret;
+
+        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
+                if ((pwrdm_read_pwrst(pwrdm) > state) &&
+                        (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+                        sleep_switch = LOWPOWERSTATE_SWITCH;
+                } else {
+                        clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+                        pwrdm_wait_transition(pwrdm);
+                        sleep_switch = FORCEWAKEUP_SWITCH;
+                }
+        }
+
+        ret = pwrdm_set_next_pwrst(pwrdm, state);
+        if (ret) {
+                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
+                       pwrdm->name);
+                goto err;
+        }
+
+        switch (sleep_switch) {
+        case FORCEWAKEUP_SWITCH:
+                if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
+                        clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+                else
+                        clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+                break;
+        case LOWPOWERSTATE_SWITCH:
+                pwrdm_set_lowpwrstchange(pwrdm);
+                break;
+        default:
+                return ret;
+        }
+
+        pwrdm_wait_transition(pwrdm);
+        pwrdm_state_switch(pwrdm);
+err:
+        return ret;
+}
+
+/*
+ * This API is to be called during init to put the various voltage
+ * domains to the voltage as per the opp table. Typically we boot up
+ * at the nominal voltage. So this function finds out the rate of
+ * the clock associated with the voltage domain, finds out the correct
+ * opp entry and puts the voltage domain to the voltage specifies
+ * in the opp entry
+ */
+static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+                                                struct device *dev)
+{
+        struct voltagedomain *voltdm;
+        struct clk *clk;
+        struct opp *opp;
+        unsigned long freq, bootup_volt;
+
+        if (!vdd_name || !clk_name || !dev) {
+                printk(KERN_ERR "%s: Invalid parameters!\n", __func__);
+                goto exit;
+        }
+
+        voltdm = omap_voltage_domain_lookup(vdd_name);
+        if (IS_ERR(voltdm)) {
+                printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
+                        __func__, vdd_name);
+                goto exit;
+        }
+
+        clk =  clk_get(NULL, clk_name);
+        if (IS_ERR(clk)) {
+                printk(KERN_ERR "%s: unable to get clk %s\n",
+                        __func__, clk_name);
+                goto exit;
+        }
+
+        freq = clk->rate;
+        clk_put(clk);
+
+        opp = opp_find_freq_ceil(dev, &freq);
+        if (IS_ERR(opp)) {
+                printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n",
+                        __func__, vdd_name);
+                goto exit;
+        }
+
+        bootup_volt = opp_get_voltage(opp);
+        if (!bootup_volt) {
+                printk(KERN_ERR "%s: unable to find voltage corresponding"
+                        "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+                goto exit;
+        }
+
+        omap_voltage_scale_vdd(voltdm, bootup_volt);
+        return 0;
+
+exit:
+        printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",
+                __func__, vdd_name);
+        return -EINVAL;
+}
+
+static void __init omap3_init_voltages(void)
+{
+        if (!cpu_is_omap34xx())
+                return;
+
+        omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
+        omap2_set_init_voltage("core", "l3_ick", l3_dev);
+}
+
+static void __init omap4_init_voltages(void)
+{
+        if (!cpu_is_omap44xx())
+                return;
+
+        omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
+        omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
+        omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
 }
 
 static int __init omap2_common_pm_init(void)
@@ -80,5 +247,24 @@ static int __init omap2_common_pm_init(void)
 
         return 0;
 }
-device_initcall(omap2_common_pm_init);
+postcore_initcall(omap2_common_pm_init);
 
+static int __init omap2_common_pm_late_init(void)
+{
+        /* Init the OMAP TWL parameters */
+        omap3_twl_init();
+        omap4_twl_init();
+
+        /* Init the voltage layer */
+        omap_voltage_late_init();
+
+        /* Initialize the voltages */
+        omap3_init_voltages();
+        omap4_init_voltages();
+
+        /* Smartreflex device init */
+        omap_devinit_smartreflex();
+
+        return 0;
+}
+late_initcall(omap2_common_pm_late_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 3de6ece23fc8..45bcfce77352 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,23 +11,41 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
-#include <plat/powerdomain.h>
+#include <linux/err.h>
 
-extern u32 enable_off_mode;
-extern u32 sleep_while_idle;
+#include "powerdomain.h"
 
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
-extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 
+#if defined(CONFIG_PM_OPP)
+extern int omap3_opp_init(void);
+extern int omap4_opp_init(void);
+#else
+static inline int omap3_opp_init(void)
+{
+        return -EINVAL;
+}
+static inline int omap4_opp_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
+/*
+ * cpuidle mach specific parameters
+ *
+ * The board code can override the default C-states definition using
+ * omap3_pm_init_cpuidle
+ */
 struct cpuidle_params {
-        u8  valid;
-        u32 sleep_latency;
-        u32 wake_latency;
-        u32 threshold;
+        u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
+        u32 target_residency;
+        u8 valid;               /* validates the C-state */
 };
 
 #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
@@ -48,14 +66,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
 
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
+extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
 extern int omap2_pm_debug;
+extern u32 enable_off_mode;
+extern u32 sleep_while_idle;
 #else
 #define omap2_pm_dump(mode, resume, us)         do {} while (0);
+#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
 #define omap2_pm_debug                          0
-#endif
-
-#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+#define enable_off_mode 0
+#define sleep_while_idle 0
 #endif
 
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@@ -73,13 +93,51 @@ extern void omap24xx_idle_loop_suspend(void);
 extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
                                         void __iomem *sdrc_power);
 extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
-extern void save_secure_ram_context(u32 *addr);
+extern int save_secure_ram_context(u32 *addr);
 extern void omap3_save_scratchpad_contents(void);
 
 extern unsigned int omap24xx_idle_loop_suspend_sz;
-extern unsigned int omap34xx_suspend_sz;
 extern unsigned int save_secure_ram_context_sz;
 extern unsigned int omap24xx_cpu_suspend_sz;
 extern unsigned int omap34xx_cpu_suspend_sz;
 
+#define PM_RTA_ERRATUM_i608             (1 << 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583     (1 << 1)
+
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id)           (pm34xx_errata & (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
+#else
+#define IS_PM34XX_ERRATUM(id)           0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
+#endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
+
+#ifdef CONFIG_OMAP_SMARTREFLEX
+extern int omap_devinit_smartreflex(void);
+extern void omap_enable_smartreflex_on_init(void);
+#else
+static inline int omap_devinit_smartreflex(void)
+{
+        return -EINVAL;
+}
+
+static inline void omap_enable_smartreflex_on_init(void) {}
+#endif
+
+#ifdef CONFIG_TWL4030_CORE
+extern int omap3_twl_init(void);
+extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(bool enable);
+#else
+static inline int omap3_twl_init(void)
+{
+        return -EINVAL;
+}
+static inline int omap4_twl_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 6aeedeacdad8..df3ded6fe194 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -30,6 +30,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
+#include <linux/console.h>
 
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -38,19 +39,32 @@
 #include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/control.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 #include "pm.h"
+#include "control.h"
 
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
+
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
 
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
@@ -65,8 +79,8 @@ static int omap2_fclks_active(void)
 {
         u32 f1, f2;
 
-        f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 
         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
@@ -91,9 +105,9 @@ static void omap2_enter_full_retention(void)
 
         /* Clear old wake-up events */
         /* REVISIT: These write to reserved bits? */
-        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-        prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
         /*
          * Set MPU powerdomain's next power state to RETENTION;
@@ -106,7 +120,7 @@ static void omap2_enter_full_retention(void)
         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 
-        omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
+        omap2_gpio_prepare_for_idle(0);
 
         if (omap2_pm_debug) {
                 omap2_pm_dump(0, 0, 0);
@@ -118,6 +132,11 @@ static void omap2_enter_full_retention(void)
         if (omap_irq_pending())
                 goto no_sleep;
 
+        /* Block console output in case it is on one of the OMAP UARTs */
+        if (!is_suspending())
+                if (!console_trylock())
+                        goto no_sleep;
+
         omap_uart_prepare_idle(0);
         omap_uart_prepare_idle(1);
         omap_uart_prepare_idle(2);
@@ -131,6 +150,9 @@ static void omap2_enter_full_retention(void)
         omap_uart_resume_idle(1);
         omap_uart_resume_idle(0);
 
+        if (!is_suspending())
+                console_unlock();
+
 no_sleep:
         if (omap2_pm_debug) {
                 unsigned long long tmp;
@@ -145,30 +167,30 @@ no_sleep:
         clk_enable(osc_ck);
 
         /* clear CORE wake-up events */
-        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 
         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
+        omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 
         /* MPU domain wake events */
-        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
         if (l & 0x01)
-                prm_write_mod_reg(0x01, OCP_MOD,
+                omap2_prm_write_mod_reg(0x01, OCP_MOD,
                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
         if (l & 0x20)
-                prm_write_mod_reg(0x20, OCP_MOD,
+                omap2_prm_write_mod_reg(0x20, OCP_MOD,
                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 
         /* Mask future PRCM-to-MPU interrupts */
-        prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 }
 
 static int omap2_i2c_active(void)
 {
         u32 l;
 
-        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 }
 
@@ -179,13 +201,13 @@ static int omap2_allow_mpu_retention(void)
         u32 l;
 
         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
-        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
                 return 0;
         /* Check for UART3. */
-        l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
         if (l & OMAP24XX_EN_UART3_MASK)
                 return 0;
         if (sti_console_enabled)
@@ -208,18 +230,18 @@ static void omap2_enter_mpu_retention(void)
          * it is in retention mode. */
         if (omap2_allow_mpu_retention()) {
                 /* REVISIT: These write to reserved bits? */
-                prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-                prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-                prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+                omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
                 /* Try to enter MPU retention */
-                prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+                omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
                                   OMAP_LOGICRETSTATE_MASK,
                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
         } else {
                 /* Block MPU retention */
 
-                prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
+                omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
                                                  OMAP2_PM_PWSTCTRL);
                 only_idle = 1;
         }
@@ -245,6 +267,8 @@ static int omap2_can_sleep(void)
 {
         if (omap2_fclks_active())
                 return 0;
+        if (!omap_uart_can_sleep())
+                return 0;
         if (osc_ck->usecount > 1)
                 return 0;
         if (omap_dma_running())
@@ -275,10 +299,11 @@ out:
         local_irq_enable();
 }
 
-static int omap2_pm_prepare(void)
+#ifdef CONFIG_SUSPEND
+static int omap2_pm_begin(suspend_state_t state)
 {
-        /* We cannot sleep in idle until we have resumed */
         disable_hlt();
+        suspend_state = state;
         return 0;
 }
 
@@ -286,9 +311,9 @@ static int omap2_pm_suspend(void)
 {
         u32 wken_wkup, mir1;
 
-        wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+        wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
-        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         /* Mask GPT1 */
         mir1 = omap_readl(0x480fe0a4);
@@ -298,7 +323,7 @@ static int omap2_pm_suspend(void)
         omap2_enter_full_retention();
 
         omap_writel(mir1, 0x480fe0a4);
-        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         return 0;
 }
@@ -319,29 +344,30 @@ static int omap2_pm_enter(suspend_state_t state)
         return ret;
 }
 
-static void omap2_pm_finish(void)
+static void omap2_pm_end(void)
 {
+        suspend_state = PM_SUSPEND_ON;
         enable_hlt();
 }
 
-static struct platform_suspend_ops omap_pm_ops = {
-        .prepare        = omap2_pm_prepare,
+static const struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap2_pm_begin,
         .enter          = omap2_pm_enter,
-        .finish         = omap2_pm_finish,
+        .end            = omap2_pm_end,
         .valid          = suspend_valid_only_mem,
 };
+#else
+static const struct platform_suspend_ops __initdata omap_pm_ops;
+#endif /* CONFIG_SUSPEND */
 
 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        clkdm_clear_all_wkdeps(clkdm);
-        clkdm_clear_all_sleepdeps(clkdm);
-
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                omap2_clkdm_allow_idle(clkdm);
+                clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                  atomic_read(&clkdm->usecount) == 0)
-                omap2_clkdm_sleep(clkdm);
+                clkdm_sleep(clkdm);
         return 0;
 }
 
@@ -350,8 +376,11 @@ static void __init prcm_setup_regs(void)
         int i, num_mem_banks;
         struct powerdomain *pwrdm;
 
-        /* Enable autoidle */
-        prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
+        /*
+         * Enable autoidle
+         * XXX This should be handled by hwmod code or PRCM init code
+         */
+        omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 
         /*
@@ -376,101 +405,34 @@ static void __init prcm_setup_regs(void)
 
         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-        omap2_clkdm_sleep(dsp_clkdm);
+        clkdm_sleep(dsp_clkdm);
 
         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-        omap2_clkdm_sleep(gfx_clkdm);
+        clkdm_sleep(gfx_clkdm);
 
-        /*
-         * Clear clockdomain wakeup dependencies and enable
-         * hardware-supervised idle for all clkdms
-         */
+        /* Enable hardware-supervised idle for all clkdms */
         clkdm_for_each(clkdms_setup, NULL);
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
-        /* Enable clock autoidle for all domains */
-        cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
-                         OMAP24XX_AUTO_MAILBOXES_MASK |
-                         OMAP24XX_AUTO_WDT4_MASK |
-                         OMAP2420_AUTO_WDT3_MASK |
-                         OMAP24XX_AUTO_MSPRO_MASK |
-                         OMAP2420_AUTO_MMC_MASK |
-                         OMAP24XX_AUTO_FAC_MASK |
-                         OMAP2420_AUTO_EAC_MASK |
-                         OMAP24XX_AUTO_HDQ_MASK |
-                         OMAP24XX_AUTO_UART2_MASK |
-                         OMAP24XX_AUTO_UART1_MASK |
-                         OMAP24XX_AUTO_I2C2_MASK |
-                         OMAP24XX_AUTO_I2C1_MASK |
-                         OMAP24XX_AUTO_MCSPI2_MASK |
-                         OMAP24XX_AUTO_MCSPI1_MASK |
-                         OMAP24XX_AUTO_MCBSP2_MASK |
-                         OMAP24XX_AUTO_MCBSP1_MASK |
-                         OMAP24XX_AUTO_GPT12_MASK |
-                         OMAP24XX_AUTO_GPT11_MASK |
-                         OMAP24XX_AUTO_GPT10_MASK |
-                         OMAP24XX_AUTO_GPT9_MASK |
-                         OMAP24XX_AUTO_GPT8_MASK |
-                         OMAP24XX_AUTO_GPT7_MASK |
-                         OMAP24XX_AUTO_GPT6_MASK |
-                         OMAP24XX_AUTO_GPT5_MASK |
-                         OMAP24XX_AUTO_GPT4_MASK |
-                         OMAP24XX_AUTO_GPT3_MASK |
-                         OMAP24XX_AUTO_GPT2_MASK |
-                         OMAP2420_AUTO_VLYNQ_MASK |
-                         OMAP24XX_AUTO_DSS_MASK,
-                         CORE_MOD, CM_AUTOIDLE1);
-        cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
-                         OMAP24XX_AUTO_SSI_MASK |
-                         OMAP24XX_AUTO_USB_MASK,
-                         CORE_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
-                         OMAP24XX_AUTO_GPMC_MASK |
-                         OMAP24XX_AUTO_SDMA_MASK,
-                         CORE_MOD, CM_AUTOIDLE3);
-        cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
-                         OMAP24XX_AUTO_AES_MASK |
-                         OMAP24XX_AUTO_RNG_MASK |
-                         OMAP24XX_AUTO_SHA_MASK |
-                         OMAP24XX_AUTO_DES_MASK,
-                         CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
-
-        cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
-                         CM_AUTOIDLE);
-
-        /* Put DPLL and both APLLs into autoidle mode */
-        cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
-                         (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
-                         (0x03 << OMAP24XX_AUTO_54M_SHIFT),
-                         PLL_MOD, CM_AUTOIDLE);
-
-        cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
-                         OMAP24XX_AUTO_WDT1_MASK |
-                         OMAP24XX_AUTO_MPU_WDT_MASK |
-                         OMAP24XX_AUTO_GPIOS_MASK |
-                         OMAP24XX_AUTO_32KSYNC_MASK |
-                         OMAP24XX_AUTO_GPT1_MASK,
-                         WKUP_MOD, CM_AUTOIDLE);
-
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
          * stabilisation */
-        prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
-                          OMAP2_PRCM_CLKSSETUP_OFFSET);
+        omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                OMAP2_PRCM_CLKSSETUP_OFFSET);
 
         /* Configure automatic voltage transition */
-        prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
-                          OMAP2_PRCM_VOLTSETUP_OFFSET);
-        prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
-                          (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
-                          OMAP24XX_MEMRETCTRL_MASK |
-                          (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
-                          (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
-                          OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
+        omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                OMAP2_PRCM_VOLTSETUP_OFFSET);
+        omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
+                                (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
+                                OMAP24XX_MEMRETCTRL_MASK |
+                                (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
+                                (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
+                                OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 
         /* Enable wake-up events */
-        prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
-                          WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
+                                WKUP_MOD, PM_WKEN);
 }
 
 static int __init omap2_pm_init(void)
@@ -481,7 +443,7 @@ static int __init omap2_pm_init(void)
                 return -ENODEV;
 
         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
-        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
+        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 
         /* Look up important powerdomains */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7b03426c72a3..c155c9d1c82c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,37 +28,49 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/console.h>
+#include <trace/events/power.h>
 
 #include <plat/sram.h>
-#include <plat/clockdomain.h>
-#include <plat/powerdomain.h>
-#include <plat/control.h>
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
-#include <plat/dmtimer.h>
 
 #include <asm/tlbflush.h>
 
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "pm.h"
 #include "sdrc.h"
+#include "control.h"
+
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
 
 /* Scratchpad offsets */
-#define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
-#define OMAP343X_TABLE_VALUE_OFFSET        0x30
-#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
+#define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
+#define OMAP343X_TABLE_VALUE_OFFSET        0xc0
+#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
-u32 enable_off_mode;
-u32 sleep_while_idle;
-u32 wakeup_timer_seconds;
-u32 wakeup_timer_milliseconds;
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
 
 struct power_state {
         struct powerdomain *pwrdm;
@@ -94,12 +106,12 @@ static void omap3_enable_io_chain(void)
         int timeout = 0;
 
         if (omap_rev() >= OMAP3430_REV_ES3_1) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                                      PM_WKEN);
                 /* Do a readback to assure write has been done */
-                prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+                omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-                while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
+                while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
                          OMAP3430_ST_IO_CHAIN_MASK)) {
                         timeout++;
                         if (timeout > 1000) {
@@ -107,7 +119,7 @@ static void omap3_enable_io_chain(void)
                                        "activation failed.\n");
                                 return;
                         }
-                        prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
+                        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
                                              WKUP_MOD, PM_WKEN);
                 }
         }
@@ -116,26 +128,17 @@ static void omap3_enable_io_chain(void)
 static void omap3_disable_io_chain(void)
 {
         if (omap_rev() >= OMAP3430_REV_ES3_1)
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                                        PM_WKEN);
 }
 
 static void omap3_core_save_context(void)
 {
-        u32 control_padconf_off;
-
-        /* Save the padconf registers */
-        control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
-        control_padconf_off |= START_PADCONF_SAVE;
-        omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
-        /* wait for the save to complete */
-        while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
-                        & PADCONF_SAVE_DONE))
-                udelay(1);
+        omap3_ctrl_save_padconf();
 
         /*
          * Force write last pad into memory, as this can fail in some
-         * cases according to erratas 1.157, 1.185
+         * cases according to errata 1.157, 1.185
          */
         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@@ -166,9 +169,10 @@ static void omap3_core_restore_context(void)
  * once during boot sequence, but this works as we are not using secure
  * services.
  */
-static void omap3_save_secure_ram_context(u32 target_mpu_state)
+static void omap3_save_secure_ram_context(void)
 {
         u32 ret;
+        int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 
         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
                 /*
@@ -179,7 +183,7 @@ static void omap3_save_secure_ram_context(u32 target_mpu_state)
                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
                 ret = _omap_save_secure_sram((u32 *)
                                 __pa(omap3_secure_ram_storage));
-                pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
+                pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
                 /* Following is for error tracking, it should not happen */
                 if (ret) {
                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
@@ -210,27 +214,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
         int c = 0;
 
-        wkst = prm_read_mod_reg(module, wkst_off);
-        wkst &= prm_read_mod_reg(module, grpsel_off);
+        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
         if (wkst) {
-                iclk = cm_read_mod_reg(module, iclk_off);
-                fclk = cm_read_mod_reg(module, fclk_off);
+                iclk = omap2_cm_read_mod_reg(module, iclk_off);
+                fclk = omap2_cm_read_mod_reg(module, fclk_off);
                 while (wkst) {
                         clken = wkst;
-                        cm_set_mod_reg_bits(clken, module, iclk_off);
+                        omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
                         /*
                          * For USBHOST, we don't know whether HOST1 or
                          * HOST2 woke us up, so enable both f-clocks
                          */
                         if (module == OMAP3430ES2_USBHOST_MOD)
                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
-                        cm_set_mod_reg_bits(clken, module, fclk_off);
-                        prm_write_mod_reg(wkst, module, wkst_off);
-                        wkst = prm_read_mod_reg(module, wkst_off);
+                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
+                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
+                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
                         c++;
                 }
-                cm_write_mod_reg(iclk, module, iclk_off);
-                cm_write_mod_reg(fclk, module, fclk_off);
+                omap2_cm_write_mod_reg(iclk, module, iclk_off);
+                omap2_cm_write_mod_reg(fclk, module, fclk_off);
         }
 
         return c;
@@ -273,9 +277,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
         u32 irqenable_mpu, irqstatus_mpu;
         int c = 0;
 
-        irqenable_mpu = prm_read_mod_reg(OCP_MOD,
+        irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+        irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
         irqstatus_mpu &= irqenable_mpu;
 
@@ -296,10 +300,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
                              "no code to handle it (%08x)\n", irqstatus_mpu);
                 }
 
-                prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
+                omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-                irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+                irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
                 irqstatus_mpu &= irqenable_mpu;
 
@@ -308,15 +312,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static void restore_control_register(u32 val)
-{
-        __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
-}
-
 /* Function to restore the table entry that was modified for enabling MMU */
 static void restore_table_entry(void)
 {
-        u32 *scratchpad_address;
+        void __iomem *scratchpad_address;
         u32 previous_value, control_reg_value;
         u32 *address;
 
@@ -334,7 +333,7 @@ static void restore_table_entry(void)
         control_reg_value = __raw_readl(scratchpad_address
                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
         /* This will enable caches and prediction */
-        restore_control_register(control_reg_value);
+        set_cr(control_reg_value);
 }
 
 void omap_sram_idle(void)
@@ -349,9 +348,9 @@ void omap_sram_idle(void)
         int mpu_next_state = PWRDM_POWER_ON;
         int per_next_state = PWRDM_POWER_ON;
         int core_next_state = PWRDM_POWER_ON;
+        int per_going_off;
         int core_prev_state, per_prev_state;
         u32 sdrc_pwr = 0;
-        int per_state_modified = 0;
 
         if (!_omap_sram_idle)
                 return;
@@ -385,37 +384,37 @@ void omap_sram_idle(void)
         /* Enable IO-PAD and IO-CHAIN wakeups */
         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-        if (omap3_has_io_wakeup() && \
-                        (per_next_state < PWRDM_POWER_ON ||
-                        core_next_state < PWRDM_POWER_ON)) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
+        if (omap3_has_io_wakeup() &&
+            (per_next_state < PWRDM_POWER_ON ||
+             core_next_state < PWRDM_POWER_ON)) {
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_enable_io_chain();
         }
 
+        /* Block console output in case it is on one of the OMAP UARTs */
+        if (!is_suspending())
+                if (per_next_state < PWRDM_POWER_ON ||
+                    core_next_state < PWRDM_POWER_ON)
+                        if (!console_trylock())
+                                goto console_still_active;
+
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
+                per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
                 omap_uart_prepare_idle(2);
-                omap2_gpio_prepare_for_idle(per_next_state);
-                if (per_next_state == PWRDM_POWER_OFF) {
-                        if (core_next_state == PWRDM_POWER_ON) {
-                                per_next_state = PWRDM_POWER_RET;
-                                pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
-                                per_state_modified = 1;
-                        } else
+                omap_uart_prepare_idle(3);
+                omap2_gpio_prepare_for_idle(per_going_off);
+                if (per_next_state == PWRDM_POWER_OFF)
                                 omap3_per_save_context();
-                }
         }
 
-        if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
-                omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
-
         /* CORE */
         if (core_next_state < PWRDM_POWER_ON) {
                 omap_uart_prepare_idle(0);
                 omap_uart_prepare_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF) {
                         omap3_core_save_context();
-                        omap3_prcm_save_context();
+                        omap3_cm_save_context();
                 }
         }
 
@@ -424,7 +423,7 @@ void omap_sram_idle(void)
         /*
         * On EMU/HS devices ROM code restores a SRDC value
         * from scratchpad which has automatic self refresh on timeout
-        * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
+        * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
         * Hence store/restore the SDRC_POWER register here.
         */
         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -455,14 +454,14 @@ void omap_sram_idle(void)
                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
                 if (core_prev_state == PWRDM_POWER_OFF) {
                         omap3_core_restore_context();
-                        omap3_prcm_restore_context();
+                        omap3_cm_restore_context();
                         omap3_sram_restore_context();
                         omap2_sms_restore_context();
                 }
                 omap_uart_resume_idle(0);
                 omap_uart_resume_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF)
-                        prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
+                        omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
                                                OMAP3_PRM_VOLTCTRL_OFFSET);
         }
@@ -475,21 +474,25 @@ void omap_sram_idle(void)
                 if (per_prev_state == PWRDM_POWER_OFF)
                         omap3_per_restore_context();
                 omap_uart_resume_idle(2);
-                if (per_state_modified)
-                        pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
+                omap_uart_resume_idle(3);
         }
 
+        if (!is_suspending())
+                console_unlock();
+
+console_still_active:
         /* Disable IO-PAD and IO-CHAIN wakeup */
         if (omap3_has_io_wakeup() &&
             (per_next_state < PWRDM_POWER_ON ||
              core_next_state < PWRDM_POWER_ON)) {
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
+                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                             PM_WKEN);
                 omap3_disable_io_chain();
         }
 
         pwrdm_post_transition();
 
-        omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
+        clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
 int omap3_can_sleep(void)
@@ -501,51 +504,6 @@ int omap3_can_sleep(void)
         return 1;
 }
 
-/* This sets pwrdm state (other than mpu & core. Currently only ON &
- * RET are supported. Function is assuming that clkdm doesn't have
- * hw_sup mode enabled. */
-int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
-{
-        u32 cur_state;
-        int sleep_switch = 0;
-        int ret = 0;
-
-        if (pwrdm == NULL || IS_ERR(pwrdm))
-                return -EINVAL;
-
-        while (!(pwrdm->pwrsts & (1 << state))) {
-                if (state == PWRDM_POWER_OFF)
-                        return ret;
-                state--;
-        }
-
-        cur_state = pwrdm_read_next_pwrst(pwrdm);
-        if (cur_state == state)
-                return ret;
-
-        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
-                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
-                sleep_switch = 1;
-                pwrdm_wait_transition(pwrdm);
-        }
-
-        ret = pwrdm_set_next_pwrst(pwrdm, state);
-        if (ret) {
-                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
-                       pwrdm->name);
-                goto err;
-        }
-
-        if (sleep_switch) {
-                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
-                pwrdm_wait_transition(pwrdm);
-                pwrdm_state_switch(pwrdm);
-        }
-
-err:
-        return ret;
-}
-
 static void omap3_pm_idle(void)
 {
         local_irq_disable();
@@ -557,39 +515,20 @@ static void omap3_pm_idle(void)
         if (omap_irq_pending() || need_resched())
                 goto out;
 
+        trace_power_start(POWER_CSTATE, 1, smp_processor_id());
+        trace_cpu_idle(1, smp_processor_id());
+
         omap_sram_idle();
 
+        trace_power_end(smp_processor_id());
+        trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+
 out:
         local_fiq_enable();
         local_irq_enable();
 }
 
 #ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state;
-
-static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-
-        if (!seconds && !milliseconds)
-                return;
-
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
-
-static int omap3_pm_prepare(void)
-{
-        disable_hlt();
-        return 0;
-}
-
 static int omap3_pm_suspend(void)
 {
         struct power_state *pwrst;
@@ -604,7 +543,7 @@ static int omap3_pm_suspend(void)
                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
         /* Set ones wanted by suspend */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
+                if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
                         goto restore;
                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
                         goto restore;
@@ -625,7 +564,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -652,14 +591,10 @@ static int omap3_pm_enter(suspend_state_t unused)
         return ret;
 }
 
-static void omap3_pm_finish(void)
-{
-        enable_hlt();
-}
-
 /* Hooks to enable / disable UART interrupts during suspend */
 static int omap3_pm_begin(suspend_state_t state)
 {
+        disable_hlt();
         suspend_state = state;
         omap_uart_enable_irqs(0);
         return 0;
@@ -669,15 +604,14 @@ static void omap3_pm_end(void)
 {
         suspend_state = PM_SUSPEND_ON;
         omap_uart_enable_irqs(1);
+        enable_hlt();
         return;
 }
 
-static struct platform_suspend_ops omap_pm_ops = {
+static const struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap3_pm_begin,
         .end            = omap3_pm_end,
-        .prepare        = omap3_pm_prepare,
         .enter          = omap3_pm_enter,
-        .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -696,21 +630,21 @@ static struct platform_suspend_ops omap_pm_ops = {
 static void __init omap3_iva_idle(void)
 {
         /* ensure IVA2 clock is disabled */
-        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* if no clock activity, nothing else to do */
-        if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
+        if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
               OMAP3430_CLKACTIVITY_IVA2_MASK))
                 return;
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
                           OMAP3430_RST2_IVA2_MASK |
                           OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Enable IVA2 clock */
-        cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
+        omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Set IVA2 boot mode to 'idle' */
@@ -718,13 +652,13 @@ static void __init omap3_iva_idle(void)
                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 
         /* Un-reset IVA2 */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Disable IVA2 clock */
-        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
                           OMAP3430_RST2_IVA2_MASK |
                           OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
@@ -748,184 +682,61 @@ static void __init omap3_d2d_idle(void)
         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 
         /* reset modem */
-        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
                           CORE_MOD, OMAP2_RM_RSTCTRL);
-        prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 }
 
 static void __init prcm_setup_regs(void)
 {
-        /* XXX Reset all wkdeps. This should be done when initializing
-         * powerdomains */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
-                prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-        } else
-                prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
-
-        /*
-         * Enable interface clock autoidle for all modules.
-         * Note that in the long run this should be done by clockfw
-         */
-        cm_write_mod_reg(
-                OMAP3430_AUTO_MODEM_MASK |
-                OMAP3430ES2_AUTO_MMC3_MASK |
-                OMAP3430ES2_AUTO_ICR_MASK |
-                OMAP3430_AUTO_AES2_MASK |
-                OMAP3430_AUTO_SHA12_MASK |
-                OMAP3430_AUTO_DES2_MASK |
-                OMAP3430_AUTO_MMC2_MASK |
-                OMAP3430_AUTO_MMC1_MASK |
-                OMAP3430_AUTO_MSPRO_MASK |
-                OMAP3430_AUTO_HDQ_MASK |
-                OMAP3430_AUTO_MCSPI4_MASK |
-                OMAP3430_AUTO_MCSPI3_MASK |
-                OMAP3430_AUTO_MCSPI2_MASK |
-                OMAP3430_AUTO_MCSPI1_MASK |
-                OMAP3430_AUTO_I2C3_MASK |
-                OMAP3430_AUTO_I2C2_MASK |
-                OMAP3430_AUTO_I2C1_MASK |
-                OMAP3430_AUTO_UART2_MASK |
-                OMAP3430_AUTO_UART1_MASK |
-                OMAP3430_AUTO_GPT11_MASK |
-                OMAP3430_AUTO_GPT10_MASK |
-                OMAP3430_AUTO_MCBSP5_MASK |
-                OMAP3430_AUTO_MCBSP1_MASK |
-                OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
-                OMAP3430_AUTO_MAILBOXES_MASK |
-                OMAP3430_AUTO_OMAPCTRL_MASK |
-                OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
-                OMAP3430_AUTO_HSOTGUSB_MASK |
-                OMAP3430_AUTO_SAD2D_MASK |
-                OMAP3430_AUTO_SSI_MASK,
-                CORE_MOD, CM_AUTOIDLE1);
-
-        cm_write_mod_reg(
-                OMAP3430_AUTO_PKA_MASK |
-                OMAP3430_AUTO_AES1_MASK |
-                OMAP3430_AUTO_RNG_MASK |
-                OMAP3430_AUTO_SHA11_MASK |
-                OMAP3430_AUTO_DES1_MASK,
-                CORE_MOD, CM_AUTOIDLE2);
-
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                cm_write_mod_reg(
-                        OMAP3430_AUTO_MAD2D_MASK |
-                        OMAP3430ES2_AUTO_USBTLL_MASK,
-                        CORE_MOD, CM_AUTOIDLE3);
-        }
-
-        cm_write_mod_reg(
-                OMAP3430_AUTO_WDT2_MASK |
-                OMAP3430_AUTO_WDT1_MASK |
-                OMAP3430_AUTO_GPIO1_MASK |
-                OMAP3430_AUTO_32KSYNC_MASK |
-                OMAP3430_AUTO_GPT12_MASK |
-                OMAP3430_AUTO_GPT1_MASK,
-                WKUP_MOD, CM_AUTOIDLE);
-
-        cm_write_mod_reg(
-                OMAP3430_AUTO_DSS_MASK,
-                OMAP3430_DSS_MOD,
-                CM_AUTOIDLE);
-
-        cm_write_mod_reg(
-                OMAP3430_AUTO_CAM_MASK,
-                OMAP3430_CAM_MOD,
-                CM_AUTOIDLE);
-
-        cm_write_mod_reg(
-                OMAP3430_AUTO_GPIO6_MASK |
-                OMAP3430_AUTO_GPIO5_MASK |
-                OMAP3430_AUTO_GPIO4_MASK |
-                OMAP3430_AUTO_GPIO3_MASK |
-                OMAP3430_AUTO_GPIO2_MASK |
-                OMAP3430_AUTO_WDT3_MASK |
-                OMAP3430_AUTO_UART3_MASK |
-                OMAP3430_AUTO_GPT9_MASK |
-                OMAP3430_AUTO_GPT8_MASK |
-                OMAP3430_AUTO_GPT7_MASK |
-                OMAP3430_AUTO_GPT6_MASK |
-                OMAP3430_AUTO_GPT5_MASK |
-                OMAP3430_AUTO_GPT4_MASK |
-                OMAP3430_AUTO_GPT3_MASK |
-                OMAP3430_AUTO_GPT2_MASK |
-                OMAP3430_AUTO_MCBSP4_MASK |
-                OMAP3430_AUTO_MCBSP3_MASK |
-                OMAP3430_AUTO_MCBSP2_MASK,
-                OMAP3430_PER_MOD,
-                CM_AUTOIDLE);
-
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                cm_write_mod_reg(
-                        OMAP3430ES2_AUTO_USBHOST_MASK,
-                        OMAP3430ES2_USBHOST_MOD,
-                        CM_AUTOIDLE);
-        }
+        u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_EN_UART4_MASK : 0;
+        u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_GRPSEL_UART4_MASK : 0;
 
+        /* XXX This should be handled by hwmod code or SCM init code */
         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
         /*
-         * Set all plls to autoidle. This is needed until autoidle is
-         * enabled by clockfw
-         */
-        cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-                         OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-                         MPU_MOD,
-                         CM_AUTOIDLE2);
-        cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-                         (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-                         PLL_MOD,
-                         CM_AUTOIDLE);
-        cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-                         PLL_MOD,
-                         CM_AUTOIDLE2);
-
-        /*
          * Enable control of expternal oscillator through
          * sys_clkreq. In the long run clock framework should
          * take care of this.
          */
-        prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+        omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
                              OMAP3430_GR_MOD,
                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 
         /* setup wakup source */
-        prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
                           WKUP_MOD, PM_WKEN);
         /* No need to write EN_IO, that is always enabled */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
                           OMAP3430_GRPSEL_GPT1_MASK |
                           OMAP3430_GRPSEL_GPT12_MASK,
                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
         /* For some reason IO doesn't generate wakeup event even if
          * it is selected to mpu wakeup goup */
-        prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
+        omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
         /* Enable PM_WKEN to support DSS LPR */
-        prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
+        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
                                 OMAP3430_DSS_MOD, PM_WKEN);
 
         /* Enable wakeups in PER */
-        prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
+        omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
+                          OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
                           OMAP3430_EN_MCBSP4_MASK,
                           OMAP3430_PER_MOD, PM_WKEN);
         /* and allow them to wake up MPU */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
+        omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
+                          OMAP3430_GRPSEL_GPIO2_MASK |
                           OMAP3430_GRPSEL_GPIO3_MASK |
                           OMAP3430_GRPSEL_GPIO4_MASK |
                           OMAP3430_GRPSEL_GPIO5_MASK |
@@ -937,22 +748,22 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
         /* Don't attach IVA interrupts */
-        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+        omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 
         /* Clear any pending 'reset' flags */
-        prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 
         /* Clear any pending PRCM interrupts */
-        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
         omap3_iva_idle();
         omap3_d2d_idle();
@@ -968,13 +779,17 @@ void omap3_pm_off_mode_enable(int enable)
         else
                 state = PWRDM_POWER_RET;
 
-#ifdef CONFIG_CPU_IDLE
-        omap3_cpuidle_update_states();
-#endif
-
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                pwrst->next_state = state;
-                set_pwrdm_state(pwrst->pwrdm, state);
+                if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
+                                pwrst->pwrdm == core_pwrdm &&
+                                state == PWRDM_POWER_OFF) {
+                        pwrst->next_state = PWRDM_POWER_RET;
+                        pr_warn("%s: Core OFF disabled due to errata i583\n",
+                                __func__);
+                } else {
+                        pwrst->next_state = state;
+                }
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
         }
 }
 
@@ -1019,7 +834,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
         if (pwrdm_has_hdwr_sar(pwrdm))
                 pwrdm_enable_hdwr_sar(pwrdm);
 
-        return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 
 /*
@@ -1029,14 +844,11 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        clkdm_clear_all_wkdeps(clkdm);
-        clkdm_clear_all_sleepdeps(clkdm);
-
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                omap2_clkdm_allow_idle(clkdm);
+                clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                  atomic_read(&clkdm->usecount) == 0)
-                omap2_clkdm_sleep(clkdm);
+                clkdm_sleep(clkdm);
         return 0;
 }
 
@@ -1049,6 +861,17 @@ void omap_push_sram_idle(void)
                                 save_secure_ram_context_sz);
 }
 
+static void __init pm_errata_configure(void)
+{
+        if (cpu_is_omap3630()) {
+                pm34xx_errata |= PM_RTA_ERRATUM_i608;
+                /* Enable the l2 cache toggling in sleep logic */
+                enable_omap3630_toggle_l2_on_restore();
+                if (omap_rev() < OMAP3630_REV_ES1_2)
+                        pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
+        }
+}
+
 static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
@@ -1058,7 +881,7 @@ static int __init omap3_pm_init(void)
         if (!cpu_is_omap34xx())
                 return -ENODEV;
 
-        printk(KERN_ERR "Power Management for TI OMAP3.\n");
+        pm_errata_configure();
 
         /* XXX prcm_setup_regs needs to be before enabling hw
          * supervised mode for powerdomains */
@@ -1105,6 +928,14 @@ static int __init omap3_pm_init(void)
         pm_idle = omap3_pm_idle;
         omap3_idle_init();
 
+        /*
+         * RTA is disabled during initialization as per erratum i608
+         * it is safer to disable RTA by the bootloader, but we would like
+         * to be doubly sure here and prevent any mishaps.
+         */
+        if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
+                omap3630_ctrl_disable_rta();
+
         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
                 omap3_secure_ram_storage =
@@ -1117,7 +948,7 @@ static int __init omap3_pm_init(void)
                 local_fiq_disable();
 
                 omap_dma_global_context_save();
-                omap3_save_secure_ram_context(PWRDM_POWER_ON);
+                omap3_save_secure_ram_context();
                 omap_dma_global_context_restore();
 
                 local_irq_enable();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 54544b4fc76b..59a870be8390 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
 #include <mach/omap4-common.h>
 
 struct power_state {
@@ -31,12 +31,6 @@ struct power_state {
 static LIST_HEAD(pwrst_list);
 
 #ifdef CONFIG_SUSPEND
-static int omap4_pm_prepare(void)
-{
-        disable_hlt();
-        return 0;
-}
-
 static int omap4_pm_suspend(void)
 {
         do_wfi();
@@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state)
         return ret;
 }
 
-static void omap4_pm_finish(void)
-{
-        enable_hlt();
-        return;
-}
-
 static int omap4_pm_begin(suspend_state_t state)
 {
+        disable_hlt();
         return 0;
 }
 
 static void omap4_pm_end(void)
 {
+        enable_hlt();
         return;
 }
 
-static struct platform_suspend_ops omap_pm_ops = {
+static const struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap4_pm_begin,
         .end            = omap4_pm_end,
-        .prepare        = omap4_pm_prepare,
         .enter          = omap4_pm_enter,
-        .finish         = omap4_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -117,13 +105,11 @@ static int __init omap4_pm_init(void)
 
         pr_err("Power Management for TI OMAP4.\n");
 
-#ifdef CONFIG_PM
         ret = pwrdm_for_each(pwrdms_setup, NULL);
         if (ret) {
                 pr_err("Failed to setup powerdomains\n");
                 goto err2;
         }
-#endif
 
 #ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
new file mode 100644
index 000000000000..171fccd208c7
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -0,0 +1,110 @@
+/*
+ *  linux/arch/arm/mach-omap2/powerdomain-common.c
+ *  Contains common powerdomain framework functions
+ *
+ *  Copyright (C) 2010 Texas Instruments, Inc.
+ *  Copyright (C) 2010 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include "pm.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+
+/*
+ * OMAP3 and OMAP4 specific register bit initialisations
+ * Notice that the names here are not according to each power
+ * domain but the bit mapping used applies to all of them
+ */
+/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
+#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
+#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
+#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
+#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
+#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
+
+/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
+#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
+#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
+#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
+#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
+#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
+
+/* OMAP3 and OMAP4 Memory Status bits */
+#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
+#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
+#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
+#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
+#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
+
+/* Common Internal functions used across OMAP rev's*/
+u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP_MEM0_ONSTATE_MASK;
+        case 1:
+                return OMAP_MEM1_ONSTATE_MASK;
+        case 2:
+                return OMAP_MEM2_ONSTATE_MASK;
+        case 3:
+                return OMAP_MEM3_ONSTATE_MASK;
+        case 4:
+                return OMAP_MEM4_ONSTATE_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP_MEM0_RETSTATE_MASK;
+        case 1:
+                return OMAP_MEM1_RETSTATE_MASK;
+        case 2:
+                return OMAP_MEM2_RETSTATE_MASK;
+        case 3:
+                return OMAP_MEM3_RETSTATE_MASK;
+        case 4:
+                return OMAP_MEM4_RETSTATE_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP_MEM0_STATEST_MASK;
+        case 1:
+                return OMAP_MEM1_STATEST_MASK;
+        case 2:
+                return OMAP_MEM2_STATEST_MASK;
+        case 3:
+                return OMAP_MEM3_STATEST_MASK;
+        case 4:
+                return OMAP_MEM4_STATEST_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 6527ec30dc17..9af08473bf10 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -2,7 +2,7 @@
  * OMAP powerdomain control
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -15,71 +15,39 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
 #include <linux/list.h>
 #include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
+#include <linux/string.h>
+#include <trace/events/power.h>
 
-#include <asm/atomic.h>
-
-#include "cm.h"
-#include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
-#include "prm-regbits-44xx.h"
+#include "cm2xxx_3xxx.h"
+#include "prcm44xx.h"
+#include "cm44xx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
 
+#include <asm/cpu.h>
 #include <plat/cpu.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 #include <plat/prcm.h>
 
 #include "pm.h"
 
+#define PWRDM_TRACE_STATES_FLAG (1<<31)
+
 enum {
         PWRDM_STATE_NOW = 0,
         PWRDM_STATE_PREV,
 };
 
-/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */
-static u16 pwrstctrl_reg_offs;
-
-/* Variable holding value of the CPU dependent PWRSTST Register Offset */
-static u16 pwrstst_reg_offs;
-
-/* OMAP3 and OMAP4 specific register bit initialisations
- * Notice that the names here are not according to each power
- * domain but the bit mapping used applies to all of them
- */
-
-/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
-#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
-#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
-#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
-#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
-#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
-
-/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
-#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
-#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
-#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
-#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
-#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
-
-/* OMAP3 and OMAP4 Memory Status bits */
-#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
-#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
-#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
-#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
-#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
 
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
 
+static struct pwrdm_ops *arch_pwrdm;
+
 /* Private functions */
 
 static struct powerdomain *_pwrdm_lookup(const char *name)
@@ -110,12 +78,19 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
 {
         int i;
 
-        if (!pwrdm)
+        if (!pwrdm || !pwrdm->name)
                 return -EINVAL;
 
         if (!omap_chip_is(pwrdm->omap_chip))
                 return -EINVAL;
 
+        if (cpu_is_omap44xx() &&
+            pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
+                pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
+                       pwrdm->name);
+                return -EINVAL;
+        }
+
         if (_pwrdm_lookup(pwrdm->name))
                 return -EEXIST;
 
@@ -160,8 +135,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
 static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 {
 
-        int prev;
-        int state;
+        int prev, state, trace_state = 0;
 
         if (pwrdm == NULL)
                 return -EINVAL;
@@ -178,6 +152,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
                         pwrdm->state_counter[prev]++;
                 if (prev == PWRDM_POWER_RET)
                         _update_logic_membank_counters(pwrdm);
+                /*
+                 * If the power domain did not hit the desired state,
+                 * generate a trace event with both the desired and hit states
+                 */
+                if (state != prev) {
+                        trace_state = (PWRDM_TRACE_STATES_FLAG |
+                                       ((state & OMAP_POWERSTATE_MASK) << 8) |
+                                       ((prev & OMAP_POWERSTATE_MASK) << 0));
+                        trace_power_domain_target(pwrdm->name, trace_state,
+                                                  smp_processor_id());
+                }
                 break;
         default:
                 return -EINVAL;
@@ -211,6 +196,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 /**
  * pwrdm_init - set up the powerdomain layer
  * @pwrdm_list: array of struct powerdomain pointers to register
+ * @custom_funcs: func pointers for arch specific implementations
  *
  * Loop through the array of powerdomains @pwrdm_list, registering all
  * that are available on the current CPU. If pwrdm_list is supplied
@@ -218,21 +204,14 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
  * registered.  No return value.  XXX pwrdm_list is not really a
  * "list"; it is an array.  Rename appropriately.
  */
-void pwrdm_init(struct powerdomain **pwrdm_list)
+void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs)
 {
         struct powerdomain **p = NULL;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL;
-                pwrstst_reg_offs = OMAP2_PM_PWSTST;
-        } else if (cpu_is_omap44xx()) {
-                pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL;
-                pwrstst_reg_offs = OMAP4_PM_PWSTST;
-        } else {
-                printk(KERN_ERR "Power Domain struct not supported for " \
-                                                        "this CPU\n");
-                return;
-        }
+        if (!custom_funcs)
+                WARN(1, "powerdomain: No custom pwrdm functions registered\n");
+        else
+                arch_pwrdm = custom_funcs;
 
         if (pwrdm_list) {
                 for (p = pwrdm_list; *p; p++)
@@ -431,6 +410,8 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
  */
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
@@ -440,11 +421,15 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
         pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
                  pwrdm->name, pwrst);
 
-        prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
-                             (pwrst << OMAP_POWERSTATE_SHIFT),
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
+                /* Trace the pwrdm desired target state */
+                trace_power_domain_target(pwrdm->name, pwrst,
+                                          smp_processor_id());
+                /* Program the pwrdm desired target state */
+                ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
+        }
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -457,11 +442,15 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
  */
 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                 pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_next_pwrst)
+                ret = arch_pwrdm->pwrdm_read_next_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -474,11 +463,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                 pwrstst_reg_offs, OMAP_POWERSTATEST_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst)
+                ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -491,11 +484,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
-                                        OMAP3430_LASTPOWERSTATEENTERED_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_pwrst)
+                ret = arch_pwrdm->pwrdm_read_prev_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -511,7 +508,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 {
-        u32 v;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
@@ -522,17 +519,10 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
         pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
                  pwrdm->name, pwrst);
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
-        prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
+                ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -552,7 +542,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
  */
 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
@@ -566,37 +556,10 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         pr_debug("powerdomain: setting next memory powerstate for domain %s "
                  "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_ONSTATE_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_ONSTATE_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_ONSTATE_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_ONSTATE_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_ONSTATE_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
+                ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
 
-        prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
-
-        return 0;
+        return ret;
 }
 
 /**
@@ -617,7 +580,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  */
 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
@@ -631,37 +594,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         pr_debug("powerdomain: setting next memory powerstate for domain %s "
                  "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_RETSTATE_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_RETSTATE_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_RETSTATE_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_RETSTATE_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_RETSTATE_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
-
-        prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                             pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
+                ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -675,11 +611,15 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  */
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs,
-                                       OMAP3430_LOGICSTATEST_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst)
+                ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -692,17 +632,15 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
-                                        OMAP3430_LASTLOGICSTATEENTERED_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst)
+                ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -715,17 +653,15 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs,
-                                       OMAP3430_LOGICSTATEST_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst)
+                ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -740,46 +676,21 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (pwrdm->banks < (bank + 1))
-                return -EEXIST;
+                return ret;
 
         if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
                 bank = 1;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_STATEST_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_STATEST_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_STATEST_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_STATEST_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_STATEST_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_pwrst)
+                ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank);
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                         pwrstst_reg_offs, m);
+        return ret;
 }
 
 /**
@@ -795,43 +706,21 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
  */
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (pwrdm->banks < (bank + 1))
-                return -EEXIST;
+                return ret;
 
         if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
                 bank = 1;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP3430_LASTMEM1STATEENTERED_MASK;
-                break;
-        case 1:
-                m = OMAP3430_LASTMEM2STATEENTERED_MASK;
-                break;
-        case 2:
-                m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
-                break;
-        case 3:
-                m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_mem_pwrst)
+                ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank);
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                        OMAP3430_PM_PREPWSTST, m);
+        return ret;
 }
 
 /**
@@ -846,43 +735,18 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
  */
 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (pwrdm->banks < (bank + 1))
-                return -EEXIST;
+                return ret;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_RETSTATE_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_RETSTATE_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_RETSTATE_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_RETSTATE_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_RETSTATE_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst)
+                ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank);
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                        pwrstctrl_reg_offs, m);
+        return ret;
 }
 
 /**
@@ -896,8 +760,10 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
  */
 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         /*
          * XXX should get the powerdomain's current state here;
@@ -907,9 +773,10 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
         pr_debug("powerdomain: clearing previous power state reg for %s\n",
                  pwrdm->name);
 
-        prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
+                ret = arch_pwrdm->pwrdm_clear_all_prev_pwrst(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -925,19 +792,21 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
-                return -EINVAL;
+                return ret;
 
         pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
                  pwrdm->name);
 
-        prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
+                ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -953,19 +822,21 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
  */
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
-                return -EINVAL;
+                return ret;
 
         pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
                  pwrdm->name);
 
-        prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
+                ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -992,6 +863,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
  */
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
@@ -1001,11 +874,10 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
         pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
                  pwrdm->name);
 
-        prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
-                             (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange)
+                ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -1020,32 +892,15 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
  */
 int pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
-        u32 c = 0;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
 
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-
-        /* XXX Is this udelay() value meaningful? */
-        while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
-                OMAP_INTRANSITION_MASK) &&
-               (c++ < PWRDM_TRANSITION_BAILOUT))
-                        udelay(1);
-
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                printk(KERN_ERR "powerdomain: waited too long for "
-                       "powerdomain %s to complete transition\n", pwrdm->name);
-                return -EAGAIN;
-        }
-
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
+                ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 int pwrdm_state_switch(struct powerdomain *pwrdm)
@@ -1075,3 +930,72 @@ int pwrdm_post_transition(void)
         return 0;
 }
 
+/**
+ * pwrdm_get_context_loss_count - get powerdomain's context loss count
+ * @pwrdm: struct powerdomain * to wait for
+ *
+ * Context loss count is the sum of powerdomain off-mode counter, the
+ * logic off counter and the per-bank memory off counter.  Returns 0
+ * (and WARNs) upon error, otherwise, returns the context loss count.
+ */
+u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
+{
+        int i, count;
+
+        if (!pwrdm) {
+                WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
+                return 0;
+        }
+
+        count = pwrdm->state_counter[PWRDM_POWER_OFF];
+        count += pwrdm->ret_logic_off_counter;
+
+        for (i = 0; i < pwrdm->banks; i++)
+                count += pwrdm->ret_mem_off_counter[i];
+
+        pr_debug("powerdomain: %s: context loss count = %u\n",
+                 pwrdm->name, count);
+
+        return count;
+}
+
+/**
+ * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
+ * @pwrdm: struct powerdomain *
+ *
+ * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
+ * can lose either memory or logic context or if @pwrdm is invalid, or
+ * returns 0 otherwise.  This function is not concerned with how the
+ * powerdomain registers are programmed (i.e., to go off or not); it's
+ * concerned with whether it's ever possible for this powerdomain to
+ * go off while some other part of the chip is active.  This function
+ * assumes that every powerdomain can go to either ON or INACTIVE.
+ */
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
+{
+        int i;
+
+        if (IS_ERR_OR_NULL(pwrdm)) {
+                pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
+                         __func__);
+                return 1;
+        }
+
+        if (pwrdm->pwrsts & PWRSTS_OFF)
+                return 1;
+
+        if (pwrdm->pwrsts & PWRSTS_RET) {
+                if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
+                        return 1;
+
+                for (i = 0; i < pwrdm->banks; i++)
+                        if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
+                                return 1;
+        }
+
+        for (i = 0; i < pwrdm->banks; i++)
+                if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
+                        return 1;
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
new file mode 100644
index 000000000000..d23d979b9c34
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -0,0 +1,230 @@
+/*
+ * OMAP2/3/4 powerdomain control
+ *
+ * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This should be moved to the mach-omap2/ directory at the earliest
+ * opportunity.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+#include <linux/atomic.h>
+
+#include <plat/cpu.h>
+
+/* Powerdomain basic power states */
+#define PWRDM_POWER_OFF         0x0
+#define PWRDM_POWER_RET         0x1
+#define PWRDM_POWER_INACTIVE    0x2
+#define PWRDM_POWER_ON          0x3
+
+#define PWRDM_MAX_PWRSTS        4
+
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_ON               (1 << PWRDM_POWER_ON)
+#define PWRSTS_INACTIVE         (1 << PWRDM_POWER_INACTIVE)
+#define PWRSTS_RET              (1 << PWRDM_POWER_RET)
+#define PWRSTS_OFF              (1 << PWRDM_POWER_OFF)
+
+#define PWRSTS_OFF_ON           (PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_OFF_RET          (PWRSTS_OFF | PWRSTS_RET)
+#define PWRSTS_RET_ON           (PWRSTS_RET | PWRSTS_ON)
+#define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | PWRSTS_ON)
+
+
+/* Powerdomain flags */
+#define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
+#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+                                          * in MEM bank 1 position. This is
+                                          * true for OMAP3430
+                                          */
+#define PWRDM_HAS_LOWPOWERSTATECHANGE   (1 << 2) /*
+                                                  * support to transition from a
+                                                  * sleep state to a lower sleep
+                                                  * state without waking up the
+                                                  * powerdomain
+                                                  */
+
+/*
+ * Number of memory banks that are power-controllable.  On OMAP4430, the
+ * maximum is 5.
+ */
+#define PWRDM_MAX_MEM_BANKS     5
+
+/*
+ * Maximum number of clockdomains that can be associated with a powerdomain.
+ * CORE powerdomain on OMAP4 is the worst case
+ */
+#define PWRDM_MAX_CLKDMS        9
+
+/* XXX A completely arbitrary number. What is reasonable here? */
+#define PWRDM_TRANSITION_BAILOUT 100000
+
+struct clockdomain;
+struct powerdomain;
+
+/**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
+ * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
+ * @pwrsts: Possible powerdomain power states
+ * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ * @flags: Powerdomain flags
+ * @banks: Number of software-controllable memory banks in this powerdomain
+ * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
+ * @state:
+ * @state_counter:
+ * @timer:
+ * @state_timer:
+ *
+ * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
+ */
+struct powerdomain {
+        const char *name;
+        const struct omap_chip_id omap_chip;
+        const s16 prcm_offs;
+        const u8 pwrsts;
+        const u8 pwrsts_logic_ret;
+        const u8 flags;
+        const u8 banks;
+        const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
+        const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
+        const u8 prcm_partition;
+        struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
+        struct list_head node;
+        int state;
+        unsigned state_counter[PWRDM_MAX_PWRSTS];
+        unsigned ret_logic_off_counter;
+        unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
+
+#ifdef CONFIG_PM_DEBUG
+        s64 timer;
+        s64 state_timer[PWRDM_MAX_PWRSTS];
+#endif
+};
+
+/**
+ * struct pwrdm_ops - Arch specific function implementations
+ * @pwrdm_set_next_pwrst: Set the target power state for a pd
+ * @pwrdm_read_next_pwrst: Read the target power state set for a pd
+ * @pwrdm_read_pwrst: Read the current power state of a pd
+ * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
+ * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
+ * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
+ * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
+ * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
+ * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
+ * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
+ * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
+ * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
+ * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
+ * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
+ * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
+ * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
+ * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
+ * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ */
+struct pwrdm_ops {
+        int     (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
+        int     (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
+        int     (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+        int     (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+        int     (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+        int     (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+        int     (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
+        int     (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
+        int     (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
+        int     (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
+        int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+};
+
+void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
+
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+                        void *user);
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+                        void *user);
+
+int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+                         int (*fn)(struct powerdomain *pwrdm,
+                                   struct clockdomain *clkdm));
+
+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+
+int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+
+int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
+int pwrdm_wait_transition(struct powerdomain *pwrdm);
+
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+int pwrdm_pre_transition(void);
+int pwrdm_post_transition(void);
+int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
+u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+
+extern void omap2xxx_powerdomains_init(void);
+extern void omap3xxx_powerdomains_init(void);
+extern void omap44xx_powerdomains_init(void);
+
+extern struct pwrdm_ops omap2_pwrdm_operations;
+extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops omap4_pwrdm_operations;
+
+/* Common Internal functions used across OMAP rev's */
+extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
+extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
+extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
+
+extern struct powerdomain wkup_omap2_pwrdm;
+extern struct powerdomain gfx_omap2_pwrdm;
+
+
+#endif
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
new file mode 100644
index 000000000000..cf600e22bf8e
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -0,0 +1,241 @@
+/*
+ * OMAP2 and OMAP3 powerdomain control
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
+
+
+/* Common functions across OMAP2 and OMAP3 */
+static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP_POWERSTATE_MASK);
+}
+
+static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP_POWERSTATEST_MASK);
+}
+
+static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
+                                             m);
+}
+
+static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL, m);
+}
+
+static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+
+        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
+        omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
+                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+                (c++ < PWRDM_TRANSITION_BAILOUT))
+                        udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                printk(KERN_ERR "powerdomain: waited too long for "
+                        "powerdomain %s to complete transition\n", pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+/* Applicable only for OMAP3. Not supported on OMAP2 */
+static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
+}
+
+static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+
+static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+
+static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
+}
+
+static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP3430_LASTMEM1STATEENTERED_MASK;
+        case 1:
+                return OMAP3430_LASTMEM2STATEENTERED_MASK;
+        case 2:
+                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
+        case 3:
+                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap3_get_mem_bank_lastmemst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                OMAP3430_PM_PREPWSTST, m);
+}
+
+static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        return 0;
+}
+
+static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(0,
+                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+}
+
+static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          0, pwrdm->prcm_offs,
+                                          OMAP2_PM_PWSTCTRL);
+}
+
+struct pwrdm_ops omap2_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+
+struct pwrdm_ops omap3_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
+        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
+        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
new file mode 100644
index 000000000000..a7880af4b3d9
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -0,0 +1,225 @@
+/*
+ * OMAP4 powerdomain control
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include "powerdomain.h"
+#include <plat/prcm.h>
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "prminst44xx.h"
+#include "prm-regbits-44xx.h"
+
+static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+                                        (pwrst << OMAP_POWERSTATE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
+        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
+        return 0;
+}
+
+static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+
+        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                    u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                     u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LOGICSTATEST_MASK;
+        v >>= OMAP4430_LOGICSTATEST_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP4430_LOGICRETSTATE_MASK;
+        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
+                                            pwrdm->prcm_offs,
+                                            OMAP4_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+               (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                printk(KERN_ERR "powerdomain: waited too long for "
+                       "powerdomain %s to complete transition\n", pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+struct pwrdm_ops omap4_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
+        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
+        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 105cbcaefd3b..4210c3399769 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -2,10 +2,9 @@
  * OMAP2/3 common powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Debugging and integration fixes by Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -18,9 +17,6 @@
  *    Clock Domain Framework
  */
 
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
-
 /*
  * This file contains all of the powerdomains that have some element
  * of software control for the OMAP24xx and OMAP34xx chips.
@@ -49,105 +45,36 @@
  * address offset is different between the C55 and C64 DSPs.
  */
 
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
 
 #include "prcm-common.h"
 #include "prm.h"
-#include "cm.h"
-#include "powerdomains24xx.h"
-#include "powerdomains34xx.h"
-#include "powerdomains44xx.h"
 
 /* OMAP2/3-common powerdomains */
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
 /*
  * The GFX powerdomain is not present on 3430ES2, but currently we do not
  * have a macro to filter it out at compile-time.
  */
-static struct powerdomain gfx_omap2_pwrdm = {
+struct powerdomain gfx_omap2_pwrdm = {
         .name             = "gfx_pwrdm",
         .prcm_offs        = GFX_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
                                            CHIP_IS_OMAP3430ES1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
-static struct powerdomain wkup_omap2_pwrdm = {
+struct powerdomain wkup_omap2_pwrdm = {
         .name           = "wkup_pwrdm",
         .prcm_offs      = WKUP_MOD,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+        .pwrsts         = PWRSTS_ON,
 };
-
-#endif
-
-
-/* As powerdomains are added or removed above, this list must also be changed */
-static struct powerdomain *powerdomains_omap[] __initdata = {
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        &wkup_omap2_pwrdm,
-        &gfx_omap2_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-        &dsp_pwrdm,
-        &mpu_24xx_pwrdm,
-        &core_24xx_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2430
-        &mdm_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-        &iva2_pwrdm,
-        &mpu_3xxx_pwrdm,
-        &neon_pwrdm,
-        &core_3xxx_pre_es3_1_pwrdm,
-        &core_3xxx_es3_1_pwrdm,
-        &cam_pwrdm,
-        &dss_pwrdm,
-        &per_pwrdm,
-        &emu_pwrdm,
-        &sgx_pwrdm,
-        &usbhost_pwrdm,
-        &dpll1_pwrdm,
-        &dpll2_pwrdm,
-        &dpll3_pwrdm,
-        &dpll4_pwrdm,
-        &dpll5_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-        &core_44xx_pwrdm,
-        &gfx_44xx_pwrdm,
-        &abe_44xx_pwrdm,
-        &dss_44xx_pwrdm,
-        &tesla_44xx_pwrdm,
-        &wkup_44xx_pwrdm,
-        &cpu0_44xx_pwrdm,
-        &cpu1_44xx_pwrdm,
-        &emu_44xx_pwrdm,
-        &mpu_44xx_pwrdm,
-        &ivahd_44xx_pwrdm,
-        &cam_44xx_pwrdm,
-        &l3init_44xx_pwrdm,
-        &l4per_44xx_pwrdm,
-        &always_on_core_44xx_pwrdm,
-        &cefuse_44xx_pwrdm,
-#endif
-        NULL
-};
-
-
-#endif
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
new file mode 100644
index 000000000000..fa311669d53d
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
@@ -0,0 +1,22 @@
+/*
+ * OMAP2/3 common powerdomains - prototypes
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
+
+#include "powerdomain.h"
+
+extern struct powerdomain gfx_omap2_pwrdm;
+extern struct powerdomain wkup_omap2_pwrdm;
+
+#endif
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 775093add9b6..cc389fb2005d 100644
--- a/arch/arm/mach-omap2/powerdomains24xx.h
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -1,37 +1,28 @@
 /*
- * OMAP24XX powerdomain definitions
+ * OMAP2XXX powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Debugging and integration fixes by Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
+#include <linux/kernel.h>
+#include <linux/init.h>
 
-/*
- * N.B. If powerdomains are added or removed from this file, update
- * the array in mach-omap2/powerdomains.h.
- */
-
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
+#include "powerdomains2xxx_3xxx_data.h"
 
 #include "prcm-common.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm.h"
-#include "cm-regbits-24xx.h"
 
 /* 24XX powerdomains and dependencies */
 
-#ifdef CONFIG_ARCH_OMAP2
-
 /* Powerdomains */
 
 static struct powerdomain dsp_pwrdm = {
@@ -39,13 +30,13 @@ static struct powerdomain dsp_pwrdm = {
         .prcm_offs        = OMAP24XX_DSP_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET,
+                [0] = PWRSTS_RET,
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,
+                [0] = PWRSTS_ON,
         },
 };
 
@@ -57,10 +48,10 @@ static struct powerdomain mpu_24xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET,
+                [0] = PWRSTS_RET,
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,
+                [0] = PWRSTS_ON,
         },
 };
 
@@ -82,15 +73,12 @@ static struct powerdomain core_24xx_pwrdm = {
         },
 };
 
-#endif     /* CONFIG_ARCH_OMAP2 */
-
-
 
 /*
  * 2430-specific powerdomains
  */
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 
 /* XXX 2430 KILLDOMAINWKUP bit?  No current users apparently */
 
@@ -99,17 +87,37 @@ static struct powerdomain mdm_pwrdm = {
         .prcm_offs        = OMAP2430_MDM_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
-#endif     /* CONFIG_ARCH_OMAP2430 */
+#endif     /* CONFIG_SOC_OMAP2430 */
 
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
 
+        &wkup_omap2_pwrdm,
+        &gfx_omap2_pwrdm,
+
+#ifdef CONFIG_ARCH_OMAP2
+        &dsp_pwrdm,
+        &mpu_24xx_pwrdm,
+        &core_24xx_pwrdm,
+#endif
+
+#ifdef CONFIG_SOC_OMAP2430
+        &mdm_pwrdm,
 #endif
+        NULL
+};
+
+void __init omap2xxx_powerdomains_init(void)
+{
+        pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
+}
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index fa904861668b..469a920a74dc 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -2,30 +2,25 @@
  * OMAP3 powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Debugging and integration fixes by Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
+#include <linux/kernel.h>
+#include <linux/init.h>
 
-/*
- * N.B. If powerdomains are added or removed from this file, update
- * the array in mach-omap2/powerdomains.h.
- */
-
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
+#include "powerdomains2xxx_3xxx_data.h"
 
 #include "prcm-common.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
@@ -52,10 +47,10 @@ static struct powerdomain iva2_pwrdm = {
                 [3] = PWRSTS_OFF_RET,
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,
-                [1] = PWRDM_POWER_ON,
+                [0] = PWRSTS_ON,
+                [1] = PWRSTS_ON,
                 [2] = PWRSTS_OFF_ON,
-                [3] = PWRDM_POWER_ON,
+                [3] = PWRSTS_ON,
         },
 };
 
@@ -77,9 +72,13 @@ static struct powerdomain mpu_3xxx_pwrdm = {
 
 /*
  * The USBTLL Save-and-Restore mechanism is broken on
- * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
+ * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
  * needs to be disabled on these chips.
  * Refer: 3430 errata ID i459 and 3630 errata ID i579
+ *
+ * Note: setting the SAR flag could help for errata ID i478
+ *  which applies to 3430 <= ES3.1, but since the SAR feature
+ *  is broken, do not use it.
  */
 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
         .name             = "core_pwrdm",
@@ -108,6 +107,10 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
                                           CHIP_GE_OMAP3630ES1_1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        /*
+         * Setting the SAR flag for errata ID i478 which applies
+         *  to 3430 <= ES3.1
+         */
         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
         .banks            = 2,
         .pwrsts_mem_ret   = {
@@ -125,13 +128,13 @@ static struct powerdomain dss_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_DSS_MOD,
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -146,13 +149,13 @@ static struct powerdomain sgx_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         /* XXX This is accurate for 3430 SGX, but what about GFX? */
         .pwrsts           = PWRSTS_OFF_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -161,13 +164,13 @@ static struct powerdomain cam_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_CAM_MOD,
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -179,10 +182,10 @@ static struct powerdomain per_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -197,7 +200,7 @@ static struct powerdomain neon_pwrdm = {
         .prcm_offs        = OMAP3430_NEON_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
 };
 
 static struct powerdomain usbhost_pwrdm = {
@@ -205,7 +208,7 @@ static struct powerdomain usbhost_pwrdm = {
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         /*
          * REVISIT: Enabling usb host save and restore mechanism seems to
          * leave the usb host domain permanently in ACTIVE mode after
@@ -215,10 +218,10 @@ static struct powerdomain usbhost_pwrdm = {
         /*.flags          = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -252,8 +255,33 @@ static struct powerdomain dpll5_pwrdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
 
-#endif    /* CONFIG_ARCH_OMAP3 */
+        &wkup_omap2_pwrdm,
+        &gfx_omap2_pwrdm,
+        &iva2_pwrdm,
+        &mpu_3xxx_pwrdm,
+        &neon_pwrdm,
+        &core_3xxx_pre_es3_1_pwrdm,
+        &core_3xxx_es3_1_pwrdm,
+        &cam_pwrdm,
+        &dss_pwrdm,
+        &per_pwrdm,
+        &emu_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
+        &dpll1_pwrdm,
+        &dpll2_pwrdm,
+        &dpll3_pwrdm,
+        &dpll4_pwrdm,
+        &dpll5_pwrdm,
+#endif
+        NULL
+};
 
 
-#endif
+void __init omap3xxx_powerdomains_init(void)
+{
+        pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
+}
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx_data.c
index c7219513472a..c4222c7036a5 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -2,7 +2,7 @@
  * OMAP4 Power domains framework
  *
  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Abhijit Pagare (abhijitpagare@ti.com)
  * Benoit Cousson (b-cousson@ti.com)
@@ -19,40 +19,39 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
-#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
+#include <linux/kernel.h>
+#include <linux/init.h>
 
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
 
 #include "prcm-common.h"
-#include "cm.h"
-#include "cm-regbits-44xx.h"
-#include "prm.h"
+#include "prcm44xx.h"
 #include "prm-regbits-44xx.h"
-
-#if defined(CONFIG_ARCH_OMAP4)
+#include "prm44xx.h"
+#include "prcm_mpu44xx.h"
 
 /* core_44xx_pwrdm: CORE power domain */
 static struct powerdomain core_44xx_pwrdm = {
         .name             = "core_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_CORE_MOD,
+        .prcm_offs        = OMAP4430_PRM_CORE_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 5,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* core_nret_bank */
+                [0] = PWRSTS_OFF,       /* core_nret_bank */
                 [1] = PWRSTS_OFF_RET,   /* core_ocmram */
-                [2] = PWRDM_POWER_RET,  /* core_other_bank */
+                [2] = PWRSTS_RET,       /* core_other_bank */
                 [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
                 [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* core_nret_bank */
+                [0] = PWRSTS_ON,        /* core_nret_bank */
                 [1] = PWRSTS_OFF_RET,   /* core_ocmram */
-                [2] = PWRDM_POWER_ON,   /* core_other_bank */
-                [3] = PWRDM_POWER_ON,   /* ducati_l2ram */
-                [4] = PWRDM_POWER_ON,   /* ducati_unicache */
+                [2] = PWRSTS_ON,        /* core_other_bank */
+                [3] = PWRSTS_ON,        /* ducati_l2ram */
+                [4] = PWRSTS_ON,        /* ducati_unicache */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -60,15 +59,16 @@ static struct powerdomain core_44xx_pwrdm = {
 /* gfx_44xx_pwrdm: 3D accelerator power domain */
 static struct powerdomain gfx_44xx_pwrdm = {
         .name             = "gfx_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_GFX_MOD,
+        .prcm_offs        = OMAP4430_PRM_GFX_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* gfx_mem */
+                [0] = PWRSTS_OFF,       /* gfx_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* gfx_mem */
+                [0] = PWRSTS_ON,        /* gfx_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -76,18 +76,19 @@ static struct powerdomain gfx_44xx_pwrdm = {
 /* abe_44xx_pwrdm: Audio back end power domain */
 static struct powerdomain abe_44xx_pwrdm = {
         .name             = "abe_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_ABE_MOD,
+        .prcm_offs        = OMAP4430_PRM_ABE_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_OFF,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 2,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_RET,  /* aessmem */
-                [1] = PWRDM_POWER_OFF,  /* periphmem */
+                [0] = PWRSTS_RET,       /* aessmem */
+                [1] = PWRSTS_OFF,       /* periphmem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* aessmem */
-                [1] = PWRDM_POWER_ON,   /* periphmem */
+                [0] = PWRSTS_ON,        /* aessmem */
+                [1] = PWRSTS_ON,        /* periphmem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -95,16 +96,17 @@ static struct powerdomain abe_44xx_pwrdm = {
 /* dss_44xx_pwrdm: Display subsystem power domain */
 static struct powerdomain dss_44xx_pwrdm = {
         .name             = "dss_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_DSS_MOD,
+        .prcm_offs        = OMAP4430_PRM_DSS_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* dss_mem */
+                [0] = PWRSTS_OFF,       /* dss_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* dss_mem */
+                [0] = PWRSTS_ON,        /* dss_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -112,20 +114,21 @@ static struct powerdomain dss_44xx_pwrdm = {
 /* tesla_44xx_pwrdm: Tesla processor power domain */
 static struct powerdomain tesla_44xx_pwrdm = {
         .name             = "tesla_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_TESLA_MOD,
+        .prcm_offs        = OMAP4430_PRM_TESLA_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 3,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_RET,  /* tesla_edma */
+                [0] = PWRSTS_RET,       /* tesla_edma */
                 [1] = PWRSTS_OFF_RET,   /* tesla_l1 */
                 [2] = PWRSTS_OFF_RET,   /* tesla_l2 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* tesla_edma */
-                [1] = PWRDM_POWER_ON,   /* tesla_l1 */
-                [2] = PWRDM_POWER_ON,   /* tesla_l2 */
+                [0] = PWRSTS_ON,        /* tesla_edma */
+                [1] = PWRSTS_ON,        /* tesla_l1 */
+                [2] = PWRSTS_ON,        /* tesla_l2 */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -133,22 +136,24 @@ static struct powerdomain tesla_44xx_pwrdm = {
 /* wkup_44xx_pwrdm: Wake-up power domain */
 static struct powerdomain wkup_44xx_pwrdm = {
         .name             = "wkup_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_WKUP_MOD,
+        .prcm_offs        = OMAP4430_PRM_WKUP_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* wkup_bank */
+                [0] = PWRSTS_OFF,       /* wkup_bank */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* wkup_bank */
+                [0] = PWRSTS_ON,        /* wkup_bank */
         },
 };
 
 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 static struct powerdomain cpu0_44xx_pwrdm = {
         .name             = "cpu0_pwrdm",
-        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_MOD,
+        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -157,14 +162,15 @@ static struct powerdomain cpu0_44xx_pwrdm = {
                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* cpu0_l1 */
+                [0] = PWRSTS_ON,        /* cpu0_l1 */
         },
 };
 
 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 static struct powerdomain cpu1_44xx_pwrdm = {
         .name             = "cpu1_pwrdm",
-        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_MOD,
+        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -173,29 +179,31 @@ static struct powerdomain cpu1_44xx_pwrdm = {
                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* cpu1_l1 */
+                [0] = PWRSTS_ON,        /* cpu1_l1 */
         },
 };
 
 /* emu_44xx_pwrdm: Emulation power domain */
 static struct powerdomain emu_44xx_pwrdm = {
         .name             = "emu_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_EMU_MOD,
+        .prcm_offs        = OMAP4430_PRM_EMU_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* emu_bank */
+                [0] = PWRSTS_OFF,       /* emu_bank */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* emu_bank */
+                [0] = PWRSTS_ON,        /* emu_bank */
         },
 };
 
 /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 static struct powerdomain mpu_44xx_pwrdm = {
         .name             = "mpu_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_MPU_MOD,
+        .prcm_offs        = OMAP4430_PRM_MPU_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -203,34 +211,35 @@ static struct powerdomain mpu_44xx_pwrdm = {
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
                 [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
-                [2] = PWRDM_POWER_RET,  /* mpu_ram */
+                [2] = PWRSTS_RET,       /* mpu_ram */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* mpu_l1 */
-                [1] = PWRDM_POWER_ON,   /* mpu_l2 */
-                [2] = PWRDM_POWER_ON,   /* mpu_ram */
+                [0] = PWRSTS_ON,        /* mpu_l1 */
+                [1] = PWRSTS_ON,        /* mpu_l2 */
+                [2] = PWRSTS_ON,        /* mpu_ram */
         },
 };
 
 /* ivahd_44xx_pwrdm: IVA-HD power domain */
 static struct powerdomain ivahd_44xx_pwrdm = {
         .name             = "ivahd_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_IVAHD_MOD,
+        .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_OFF,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 4,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* hwa_mem */
+                [0] = PWRSTS_OFF,       /* hwa_mem */
                 [1] = PWRSTS_OFF_RET,   /* sl2_mem */
                 [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
                 [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* hwa_mem */
-                [1] = PWRDM_POWER_ON,   /* sl2_mem */
-                [2] = PWRDM_POWER_ON,   /* tcm1_mem */
-                [3] = PWRDM_POWER_ON,   /* tcm2_mem */
+                [0] = PWRSTS_ON,        /* hwa_mem */
+                [1] = PWRSTS_ON,        /* sl2_mem */
+                [2] = PWRSTS_ON,        /* tcm1_mem */
+                [3] = PWRSTS_ON,        /* tcm2_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -238,15 +247,16 @@ static struct powerdomain ivahd_44xx_pwrdm = {
 /* cam_44xx_pwrdm: Camera subsystem power domain */
 static struct powerdomain cam_44xx_pwrdm = {
         .name             = "cam_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_CAM_MOD,
+        .prcm_offs        = OMAP4430_PRM_CAM_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* cam_mem */
+                [0] = PWRSTS_OFF,       /* cam_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* cam_mem */
+                [0] = PWRSTS_ON,        /* cam_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -254,16 +264,17 @@ static struct powerdomain cam_44xx_pwrdm = {
 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
 static struct powerdomain l3init_44xx_pwrdm = {
         .name             = "l3init_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_L3INIT_MOD,
+        .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* l3init_bank1 */
+                [0] = PWRSTS_OFF,       /* l3init_bank1 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* l3init_bank1 */
+                [0] = PWRSTS_ON,        /* l3init_bank1 */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -271,18 +282,19 @@ static struct powerdomain l3init_44xx_pwrdm = {
 /* l4per_44xx_pwrdm: Target peripherals power domain */
 static struct powerdomain l4per_44xx_pwrdm = {
         .name             = "l4per_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_L4PER_MOD,
+        .prcm_offs        = OMAP4430_PRM_L4PER_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 2,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* nonretained_bank */
-                [1] = PWRDM_POWER_RET,  /* retained_bank */
+                [0] = PWRSTS_OFF,       /* nonretained_bank */
+                [1] = PWRSTS_RET,       /* retained_bank */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* nonretained_bank */
-                [1] = PWRDM_POWER_ON,   /* retained_bank */
+                [0] = PWRSTS_ON,        /* nonretained_bank */
+                [1] = PWRSTS_ON,        /* retained_bank */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -293,7 +305,8 @@ static struct powerdomain l4per_44xx_pwrdm = {
  */
 static struct powerdomain always_on_core_44xx_pwrdm = {
         .name             = "always_on_core_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_MOD,
+        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_ON,
 };
@@ -301,7 +314,8 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
 static struct powerdomain cefuse_44xx_pwrdm = {
         .name             = "cefuse_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_CEFUSE_MOD,
+        .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
 };
@@ -314,6 +328,28 @@ static struct powerdomain cefuse_44xx_pwrdm = {
  * stdefuse
  */
 
-#endif
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap44xx[] __initdata = {
+        &core_44xx_pwrdm,
+        &gfx_44xx_pwrdm,
+        &abe_44xx_pwrdm,
+        &dss_44xx_pwrdm,
+        &tesla_44xx_pwrdm,
+        &wkup_44xx_pwrdm,
+        &cpu0_44xx_pwrdm,
+        &cpu1_44xx_pwrdm,
+        &emu_44xx_pwrdm,
+        &mpu_44xx_pwrdm,
+        &ivahd_44xx_pwrdm,
+        &cam_44xx_pwrdm,
+        &l3init_44xx_pwrdm,
+        &l4per_44xx_pwrdm,
+        &always_on_core_44xx_pwrdm,
+        &cefuse_44xx_pwrdm,
+        NULL
+};
 
-#endif
+void __init omap44xx_powerdomains_init(void)
+{
+        pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
+}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 995b7edbf18d..0363dcb0ef93 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -8,15 +8,12 @@
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
- * OMAP4 defines in this file are automatically generated from the OMAP hardware
- * databases.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-
 /* Module offsets from both CM_BASE & PRM_BASE */
 
 /*
@@ -51,75 +48,6 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
 
-#define BITS(n_bit)     \
-        (((1 << n_bit) - 1) | (1 << n_bit))
-
-#define BITFIELD(l_bit, u_bit)  \
-        (BITS(u_bit) & ~((BITS(l_bit)) >> 1))
-
-/* OMAP44XX specific module offsets */
-
-/* CM1 instances */
-
-#define OMAP4430_CM1_OCP_SOCKET_MOD     0x0000
-#define OMAP4430_CM1_CKGEN_MOD          0x0100
-#define OMAP4430_CM1_MPU_MOD            0x0300
-#define OMAP4430_CM1_TESLA_MOD          0x0400
-#define OMAP4430_CM1_ABE_MOD            0x0500
-#define OMAP4430_CM1_RESTORE_MOD        0x0e00
-#define OMAP4430_CM1_INSTR_MOD          0x0f00
-
-/* CM2 instances */
-
-#define OMAP4430_CM2_OCP_SOCKET_MOD     0x0000
-#define OMAP4430_CM2_CKGEN_MOD          0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD      0x0600
-#define OMAP4430_CM2_CORE_MOD           0x0700
-#define OMAP4430_CM2_IVAHD_MOD          0x0f00
-#define OMAP4430_CM2_CAM_MOD            0x1000
-#define OMAP4430_CM2_DSS_MOD            0x1100
-#define OMAP4430_CM2_GFX_MOD            0x1200
-#define OMAP4430_CM2_L3INIT_MOD         0x1300
-#define OMAP4430_CM2_L4PER_MOD          0x1400
-#define OMAP4430_CM2_CEFUSE_MOD         0x1600
-#define OMAP4430_CM2_RESTORE_MOD        0x1e00
-#define OMAP4430_CM2_INSTR_MOD          0x1f00
-
-/* PRM instances */
-
-#define OMAP4430_PRM_OCP_SOCKET_MOD     0x0000
-#define OMAP4430_PRM_CKGEN_MOD          0x0100
-#define OMAP4430_PRM_MPU_MOD            0x0300
-#define OMAP4430_PRM_TESLA_MOD          0x0400
-#define OMAP4430_PRM_ABE_MOD            0x0500
-#define OMAP4430_PRM_ALWAYS_ON_MOD      0x0600
-#define OMAP4430_PRM_CORE_MOD           0x0700
-#define OMAP4430_PRM_IVAHD_MOD          0x0f00
-#define OMAP4430_PRM_CAM_MOD            0x1000
-#define OMAP4430_PRM_DSS_MOD            0x1100
-#define OMAP4430_PRM_GFX_MOD            0x1200
-#define OMAP4430_PRM_L3INIT_MOD         0x1300
-#define OMAP4430_PRM_L4PER_MOD          0x1400
-#define OMAP4430_PRM_CEFUSE_MOD         0x1600
-#define OMAP4430_PRM_WKUP_MOD           0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD        0x1800
-#define OMAP4430_PRM_EMU_MOD            0x1900
-#define OMAP4430_PRM_EMU_CM_MOD         0x1a00
-#define OMAP4430_PRM_DEVICE_MOD         0x1b00
-#define OMAP4430_PRM_INSTR_MOD          0x1f00
-
-/* SCRM instances */
-
-#define OMAP4430_SCRM_SCRM_MOD  0x0000
-
-/* PRCM_MPU instances */
-
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD   0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD        0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD              0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD              0x0800
-
-
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
@@ -193,6 +121,10 @@
 #define OMAP24XX_ST_MCSPI2_MASK                         (1 << 18)
 #define OMAP24XX_ST_MCSPI1_SHIFT                        17
 #define OMAP24XX_ST_MCSPI1_MASK                         (1 << 17)
+#define OMAP24XX_ST_MCBSP2_SHIFT                        16
+#define OMAP24XX_ST_MCBSP2_MASK                         (1 << 16)
+#define OMAP24XX_ST_MCBSP1_SHIFT                        15
+#define OMAP24XX_ST_MCBSP1_MASK                         (1 << 15)
 #define OMAP24XX_ST_GPT12_SHIFT                         14
 #define OMAP24XX_ST_GPT12_MASK                          (1 << 14)
 #define OMAP24XX_ST_GPT11_SHIFT                         13
@@ -243,13 +175,14 @@
 #define OMAP24XX_EN_GPT1_MASK                           (1 << 0)
 
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT                         (1 << 2)
-#define OMAP24XX_ST_GPIOS_MASK                          2
-#define OMAP24XX_ST_GPT1_SHIFT                          (1 << 0)
-#define OMAP24XX_ST_GPT1_MASK                           0
+#define OMAP24XX_ST_GPIOS_SHIFT                         2
+#define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
+#define OMAP24XX_ST_GPT1_SHIFT                          0
+#define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 
 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT                           (1 << 0)
+#define OMAP2430_ST_MDM_SHIFT                           0
+#define OMAP2430_ST_MDM_MASK                            (1 << 0)
 
 
 /* 3430 register bits shared between CM & PRM registers */
@@ -262,6 +195,8 @@
 #define OMAP3430_AUTOIDLE_MASK                          (1 << 0)
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC3_MASK                           (1 << 30)
+#define OMAP3430_EN_MMC3_SHIFT                          30
 #define OMAP3430_EN_MMC2_MASK                           (1 << 25)
 #define OMAP3430_EN_MMC2_SHIFT                          25
 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
@@ -302,6 +237,8 @@
 #define OMAP3430_EN_HSOTGUSB_SHIFT                      4
 
 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC3_SHIFT                          30
+#define OMAP3430_ST_MMC3_MASK                           (1 << 30)
 #define OMAP3430_ST_MMC2_SHIFT                          25
 #define OMAP3430_ST_MMC2_MASK                           (1 << 25)
 #define OMAP3430_ST_MMC1_SHIFT                          24
@@ -382,6 +319,9 @@
 #define OMAP3430_EN_MPU_SHIFT                           1
 
 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+
+#define OMAP3630_EN_UART4_MASK                          (1 << 18)
+#define OMAP3630_EN_UART4_SHIFT                         18
 #define OMAP3430_EN_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_EN_GPIO6_SHIFT                         17
 #define OMAP3430_EN_GPIO5_MASK                          (1 << 16)
@@ -422,6 +362,8 @@
 #define OMAP3430_EN_MCBSP2_SHIFT                        0
 
 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3630_ST_UART4_SHIFT                         18
+#define OMAP3630_ST_UART4_MASK                          (1 << 18)
 #define OMAP3430_ST_GPIO6_SHIFT                         17
 #define OMAP3430_ST_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_ST_GPIO5_SHIFT                         16
@@ -455,5 +397,18 @@
 #define OMAP3430_EN_CORE_SHIFT                          0
 #define OMAP3430_EN_CORE_MASK                           (1 << 0)
 
+
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+
+# ifndef __ASSEMBLER__
+extern void __iomem *prm_base;
+extern void __iomem *cm_base;
+extern void __iomem *cm2_base;
+# endif
+
 #endif
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c20137497c92..6be14389e4f3 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,123 +17,48 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/module.h>
+
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
 
+#include <mach/system.h>
 #include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
-#include <plat/control.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
-#include "prm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "prminst44xx.h"
 #include "prm-regbits-24xx.h"
+#include "prm-regbits-44xx.h"
+#include "control.h"
 
-static void __iomem *prm_base;
-static void __iomem *cm_base;
-static void __iomem *cm2_base;
+void __iomem *prm_base;
+void __iomem *cm_base;
+void __iomem *cm2_base;
 
 #define MAX_MODULE_ENABLE_WAIT          100000
 
-struct omap3_prcm_regs {
-        u32 control_padconf_sys_nirq;
-        u32 iva2_cm_clksel1;
-        u32 iva2_cm_clksel2;
-        u32 cm_sysconfig;
-        u32 sgx_cm_clksel;
-        u32 dss_cm_clksel;
-        u32 cam_cm_clksel;
-        u32 per_cm_clksel;
-        u32 emu_cm_clksel;
-        u32 emu_cm_clkstctrl;
-        u32 pll_cm_autoidle2;
-        u32 pll_cm_clksel4;
-        u32 pll_cm_clksel5;
-        u32 pll_cm_clken2;
-        u32 cm_polctrl;
-        u32 iva2_cm_fclken;
-        u32 iva2_cm_clken_pll;
-        u32 core_cm_fclken1;
-        u32 core_cm_fclken3;
-        u32 sgx_cm_fclken;
-        u32 wkup_cm_fclken;
-        u32 dss_cm_fclken;
-        u32 cam_cm_fclken;
-        u32 per_cm_fclken;
-        u32 usbhost_cm_fclken;
-        u32 core_cm_iclken1;
-        u32 core_cm_iclken2;
-        u32 core_cm_iclken3;
-        u32 sgx_cm_iclken;
-        u32 wkup_cm_iclken;
-        u32 dss_cm_iclken;
-        u32 cam_cm_iclken;
-        u32 per_cm_iclken;
-        u32 usbhost_cm_iclken;
-        u32 iva2_cm_autiidle2;
-        u32 mpu_cm_autoidle2;
-        u32 iva2_cm_clkstctrl;
-        u32 mpu_cm_clkstctrl;
-        u32 core_cm_clkstctrl;
-        u32 sgx_cm_clkstctrl;
-        u32 dss_cm_clkstctrl;
-        u32 cam_cm_clkstctrl;
-        u32 per_cm_clkstctrl;
-        u32 neon_cm_clkstctrl;
-        u32 usbhost_cm_clkstctrl;
-        u32 core_cm_autoidle1;
-        u32 core_cm_autoidle2;
-        u32 core_cm_autoidle3;
-        u32 wkup_cm_autoidle;
-        u32 dss_cm_autoidle;
-        u32 cam_cm_autoidle;
-        u32 per_cm_autoidle;
-        u32 usbhost_cm_autoidle;
-        u32 sgx_cm_sleepdep;
-        u32 dss_cm_sleepdep;
-        u32 cam_cm_sleepdep;
-        u32 per_cm_sleepdep;
-        u32 usbhost_cm_sleepdep;
-        u32 cm_clkout_ctrl;
-        u32 prm_clkout_ctrl;
-        u32 sgx_pm_wkdep;
-        u32 dss_pm_wkdep;
-        u32 cam_pm_wkdep;
-        u32 per_pm_wkdep;
-        u32 neon_pm_wkdep;
-        u32 usbhost_pm_wkdep;
-        u32 core_pm_mpugrpsel1;
-        u32 iva2_pm_ivagrpsel1;
-        u32 core_pm_mpugrpsel3;
-        u32 core_pm_ivagrpsel3;
-        u32 wkup_pm_mpugrpsel;
-        u32 wkup_pm_ivagrpsel;
-        u32 per_pm_mpugrpsel;
-        u32 per_pm_ivagrpsel;
-        u32 wkup_pm_wken;
-};
-
-struct omap3_prcm_regs prcm_context;
-
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
         if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
         if (cpu_is_omap44xx())
-                return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
+                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 
         return 0;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
 /* Resets clock rates and reboots the system. Only called from system.h */
-void omap_prcm_arch_reset(char mode, const char *cmd)
+static void omap_prcm_arch_reset(char mode, const char *cmd)
 {
         s16 prcm_offs = 0;
 
@@ -142,103 +67,49 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
 
                 prcm_offs = WKUP_MOD;
         } else if (cpu_is_omap34xx()) {
-                u32 l;
-
                 prcm_offs = OMAP3430_GR_MOD;
-                l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0);
-                /* Reserve the first word in scratchpad for communicating
-                 * with the boot ROM. A pointer to a data structure
-                 * describing the boot process can be stored there,
-                 * cf. OMAP34xx TRM, Initialization / Software Booting
-                 * Configuration. */
-                omap_writel(l, OMAP343X_SCRATCHPAD + 4);
-        } else if (cpu_is_omap44xx())
-                prcm_offs = OMAP4430_PRM_DEVICE_MOD;
-        else
+                omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
+        } else if (cpu_is_omap44xx()) {
+                omap4_prm_global_warm_sw_reset(); /* never returns */
+        } else {
                 WARN_ON(1);
+        }
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                                                 OMAP2_RM_RSTCTRL);
-        if (cpu_is_omap44xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                                                 OMAP4_RM_RSTCTRL);
-}
-
-static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
-{
-        BUG_ON(!base);
-        return __raw_readl(base + module + reg);
-}
-
-static inline void __omap_prcm_write(u32 value, void __iomem *base,
-                                                s16 module, u16 reg)
-{
-        BUG_ON(!base);
-        __raw_writel(value, base + module + reg);
-}
-
-/* Read a register in a PRM module */
-u32 prm_read_mod_reg(s16 module, u16 idx)
-{
-        return __omap_prcm_read(prm_base, module, idx);
-}
-
-/* Write into a register in a PRM module */
-void prm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __omap_prcm_write(val, prm_base, module, idx);
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-
-        v = prm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        prm_write_mod_reg(v, module, idx);
-
-        return v;
-}
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        u32 v;
-
-        v = prm_read_mod_reg(domain, idx);
-        v &= mask;
-        v >>= __ffs(mask);
-
-        return v;
-}
-
-/* Read a register in a CM module */
-u32 cm_read_mod_reg(s16 module, u16 idx)
-{
-        return __omap_prcm_read(cm_base, module, idx);
-}
-
-/* Write into a register in a CM module */
-void cm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __omap_prcm_write(val, cm_base, module, idx);
+        /*
+         * As per Errata i520, in some cases, user will not be able to
+         * access DDR memory after warm-reset.
+         * This situation occurs while the warm-reset happens during a read
+         * access to DDR memory. In that particular condition, DDR memory
+         * does not respond to a corrupted read command due to the warm
+         * reset occurrence but SDRC is waiting for read completion.
+         * SDRC is not sensitive to the warm reset, but the interconnect is
+         * reset on the fly, thus causing a misalignment between SDRC logic,
+         * interconnect logic and DDR memory state.
+         * WORKAROUND:
+         * Steps to perform before a Warm reset is trigged:
+         * 1. enable self-refresh on idle request
+         * 2. put SDRC in idle
+         * 3. wait until SDRC goes to idle
+         * 4. generate SW reset (Global SW reset)
+         *
+         * Steps to be performed after warm reset occurs (in bootloader):
+         * if HW warm reset is the source, apply below steps before any
+         * accesses to SDRAM:
+         * 1. Reset SMS and SDRC and wait till reset is complete
+         * 2. Re-initialize SMS, SDRC and memory
+         *
+         * NOTE: Above work around is required only if arch reset is implemented
+         * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
+         * the WA since it resets SDRC as well as part of cold reset.
+         */
+
+        /* XXX should be moved to some OMAP2/3 specific code */
+        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
+                                   OMAP2_RM_RSTCTRL);
+        omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
 }
 
-/* Read-modify-write a register in a CM module. Caller must lock */
-u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-
-        v = cm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        cm_write_mod_reg(v, module, idx);
-
-        return v;
-}
+void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
 
 /**
  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
@@ -249,6 +120,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  *
  * Returns 1 if the module indicated readiness in time, or 0 if it
  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ *
+ * XXX This function is deprecated.  It should be removed once the
+ * hwmod conversion is complete.
  */
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                                 const char *name)
@@ -291,303 +165,3 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
                 WARN_ON(!cm2_base);
         }
 }
-
-#ifdef CONFIG_ARCH_OMAP3
-void omap3_prcm_save_context(void)
-{
-        prcm_context.control_padconf_sys_nirq =
-                         omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
-        prcm_context.iva2_cm_clksel1 =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
-        prcm_context.iva2_cm_clksel2 =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
-        prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
-        prcm_context.sgx_cm_clksel =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
-        prcm_context.dss_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
-        prcm_context.cam_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
-        prcm_context.per_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
-        prcm_context.emu_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
-        prcm_context.emu_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.pll_cm_autoidle2 =
-                         cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
-        prcm_context.pll_cm_clksel4 =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
-        prcm_context.pll_cm_clksel5 =
-                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
-        prcm_context.pll_cm_clken2 =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
-        prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
-        prcm_context.iva2_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
-        prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
-                        OMAP3430_CM_CLKEN_PLL);
-        prcm_context.core_cm_fclken1 =
-                         cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        prcm_context.core_cm_fclken3 =
-                         cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-        prcm_context.sgx_cm_fclken =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
-        prcm_context.wkup_cm_fclken =
-                         cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
-        prcm_context.dss_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
-        prcm_context.cam_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
-        prcm_context.per_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
-        prcm_context.usbhost_cm_fclken =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
-        prcm_context.core_cm_iclken1 =
-                         cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
-        prcm_context.core_cm_iclken2 =
-                         cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
-        prcm_context.core_cm_iclken3 =
-                         cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
-        prcm_context.sgx_cm_iclken =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
-        prcm_context.wkup_cm_iclken =
-                         cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
-        prcm_context.dss_cm_iclken =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
-        prcm_context.cam_cm_iclken =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
-        prcm_context.per_cm_iclken =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
-        prcm_context.usbhost_cm_iclken =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
-        prcm_context.iva2_cm_autiidle2 =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-        prcm_context.mpu_cm_autoidle2 =
-                         cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
-        prcm_context.iva2_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.mpu_cm_clkstctrl =
-                         cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.core_cm_clkstctrl =
-                         cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.sgx_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
-                                                OMAP2_CM_CLKSTCTRL);
-        prcm_context.dss_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.cam_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.per_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.neon_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.usbhost_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
-                                                OMAP2_CM_CLKSTCTRL);
-        prcm_context.core_cm_autoidle1 =
-                         cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
-        prcm_context.core_cm_autoidle2 =
-                         cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
-        prcm_context.core_cm_autoidle3 =
-                         cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
-        prcm_context.wkup_cm_autoidle =
-                         cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
-        prcm_context.dss_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
-        prcm_context.cam_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
-        prcm_context.per_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
-        prcm_context.usbhost_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
-        prcm_context.sgx_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.dss_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.cam_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.per_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.usbhost_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
-                 OMAP3_CM_CLKOUT_CTRL_OFFSET);
-        prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
-                OMAP3_PRM_CLKOUT_CTRL_OFFSET);
-        prcm_context.sgx_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
-        prcm_context.dss_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
-        prcm_context.cam_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
-        prcm_context.per_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
-        prcm_context.neon_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
-        prcm_context.usbhost_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-        prcm_context.core_pm_mpugrpsel1 =
-                 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
-        prcm_context.iva2_pm_ivagrpsel1 =
-                 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
-        prcm_context.core_pm_mpugrpsel3 =
-                 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
-        prcm_context.core_pm_ivagrpsel3 =
-                 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        prcm_context.wkup_pm_mpugrpsel =
-                 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
-        prcm_context.wkup_pm_ivagrpsel =
-                 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        prcm_context.per_pm_mpugrpsel =
-                 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
-        prcm_context.per_pm_ivagrpsel =
-                 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
-        prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-        return;
-}
-
-void omap3_prcm_restore_context(void)
-{
-        omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
-                                         OMAP343X_CONTROL_PADCONF_SYSNIRQ);
-        cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
-                                         CM_CLKSEL1);
-        cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
-                                         CM_CLKSEL2);
-        __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
-        cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
-                                         CM_CLKSEL1);
-        cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
-                                         OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
-                                         CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
-                                        OMAP3430ES2_CM_CLKSEL4);
-        cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
-                                         OMAP3430ES2_CM_CLKSEL5);
-        cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
-                                        OMAP3430ES2_CM_CLKEN2);
-        __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
-        cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
-                                        OMAP3430_CM_CLKEN_PLL);
-        cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
-        cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
-                                         OMAP3430ES2_CM_FCLKEN3);
-        cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
-                                         OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
-        cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
-        cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
-        cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
-                                        OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
-                                        CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
-                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
-                                        CM_AUTOIDLE1);
-        cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
-                                        CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
-                                        CM_AUTOIDLE3);
-        cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
-                                        CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
-                                        CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
-                                        CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
-                                        OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
-                                OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
-                                        OMAP3_CM_CLKOUT_CTRL_OFFSET);
-        prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
-                                        OMAP3_PRM_CLKOUT_CTRL_OFFSET);
-        prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
-                                        OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-        prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
-                                        OMAP3430_PM_MPUGRPSEL1);
-        prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
-                                        OMAP3430_PM_IVAGRPSEL1);
-        prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
-                                        OMAP3430ES2_PM_MPUGRPSEL3);
-        prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
-                                        OMAP3430ES2_PM_IVAGRPSEL3);
-        prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
-                                        OMAP3430_PM_MPUGRPSEL);
-        prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
-                                        OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
-                                        OMAP3430_PM_MPUGRPSEL);
-        prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
-                                         OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
-        return;
-}
-#endif
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
new file mode 100644
index 000000000000..7334ffb9d2c1
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -0,0 +1,42 @@
+/*
+ * OMAP4 PRCM definitions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains macros and functions that are common to all of
+ * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
+ * PRCM_MPU, SCRM
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
+
+/*
+ * OMAP4 PRCM partition IDs
+ *
+ * The numbers and order are arbitrary, but 0 is reserved for the
+ * 'invalid' partition in case someone forgets to add a
+ * .prcm_partition field.
+ */
+#define OMAP4430_INVALID_PRCM_PARTITION         0
+#define OMAP4430_PRM_PARTITION                  1
+#define OMAP4430_CM1_PARTITION                  2
+#define OMAP4430_CM2_PARTITION                  3
+#define OMAP4430_SCRM_PARTITION                 4
+#define OMAP4430_PRCM_MPU_PARTITION             5
+
+/*
+ * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
+ * IDs, plus one
+ */
+#define OMAP4_MAX_PRCM_PARTITIONS               6
+
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
new file mode 100644
index 000000000000..171fe171a749
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -0,0 +1,45 @@
+/*
+ * OMAP4 PRCM_MPU module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "prcm_mpu44xx.h"
+#include "cm-regbits-44xx.h"
+
+/* PRCM_MPU low-level functions */
+
+u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+}
+
+void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+}
+
+u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+{
+        u32 v;
+
+        v = omap4_prcm_mpu_read_inst_reg(inst, reg);
+        v &= ~mask;
+        v |= bits;
+        omap4_prcm_mpu_write_inst_reg(v, inst, reg);
+
+        return v;
+}
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
new file mode 100644
index 000000000000..d22d1b43bccd
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -0,0 +1,104 @@
+/*
+ * OMAP44xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+
+#define OMAP4430_PRCM_MPU_BASE                  0x48243000
+
+#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
+
+/* PRCM_MPU instances */
+
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST       0x0200
+#define OMAP4430_PRCM_MPU_CPU0_INST             0x0400
+#define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS      0x0018
+#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS      0x0018
+
+
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+
+/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
+#define OMAP4_REVISION_PRCM_OFFSET                      0x0000
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
+
+/* PRCM_MPU.DEVICE_PRM register offsets */
+#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
+#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
+#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
+
+/* PRCM_MPU.CPU0 register offsets */
+#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
+#define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
+#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
+#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
+#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
+#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
+#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
+#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
+#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
+#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
+#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
+#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
+#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
+
+/* PRCM_MPU.CPU1 register offsets */
+#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
+#define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
+#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
+#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
+#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
+#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
+#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
+#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
+#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
+#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
+#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
+#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
+#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
+
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+                                            s16 idx);
+# endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 0b188ffa710e..6ac966103f34 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -14,7 +14,7 @@
  * published by the Free Software Foundation.
  */
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 
 /* Bits shared between registers */
 
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 7fd6023edf96..64c087af6a8b 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -1,6 +1,3 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-
 /*
  * OMAP3430 Power/Reset Management register bits
  *
@@ -13,8 +10,11 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 
 /* Shared register bits */
 
@@ -101,8 +101,11 @@
 #define OMAP3430_GRPSEL_MCSPI3_MASK                     (1 << 20)
 #define OMAP3430_GRPSEL_MCSPI2_MASK                     (1 << 19)
 #define OMAP3430_GRPSEL_MCSPI1_MASK                     (1 << 18)
+#define OMAP3430_GRPSEL_I2C3_SHIFT                      17
 #define OMAP3430_GRPSEL_I2C3_MASK                       (1 << 17)
+#define OMAP3430_GRPSEL_I2C2_SHIFT                      16
 #define OMAP3430_GRPSEL_I2C2_MASK                       (1 << 16)
+#define OMAP3430_GRPSEL_I2C1_SHIFT                      15
 #define OMAP3430_GRPSEL_I2C1_MASK                       (1 << 15)
 #define OMAP3430_GRPSEL_UART2_MASK                      (1 << 14)
 #define OMAP3430_GRPSEL_UART1_MASK                      (1 << 13)
@@ -122,6 +125,7 @@
 #define OMAP3430_MEMRETSTATE_MASK                       (1 << 8)
 
 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3630_GRPSEL_UART4_MASK                      (1 << 18)
 #define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
 #define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
 #define OMAP3430_GRPSEL_GPIO4_MASK                      (1 << 15)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 597be4a2b9ff..6d2776f6fc08 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx Power Management register bits
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -22,595 +22,617 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
 
-#include "prm.h"
-
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                1
-#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 (1 << 1)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              2
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               BITFIELD(2, 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               (1 << 2)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   BITFIELD(31, 31)
+#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   (1 << 31)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   BITFIELD(31, 31)
+#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   (1 << 31)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   BITFIELD(7, 7)
+#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   (1 << 7)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   BITFIELD(7, 7)
+#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   (1 << 7)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   2
-#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    BITFIELD(2, 2)
+#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    (1 << 2)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   1
-#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    BITFIELD(1, 1)
+#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    (1 << 1)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_AESSMEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_AESSMEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_AESSMEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_AESSMEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_ABE_PWRSTST */
 #define OMAP4430_AESSMEM_STATEST_SHIFT                                  4
-#define OMAP4430_AESSMEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_AESSMEM_STATEST_MASK                                   (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_AIPOFF_SHIFT                                           8
-#define OMAP4430_AIPOFF_MASK                                            BITFIELD(8, 8)
+#define OMAP4430_AIPOFF_MASK                                            (1 << 8)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             0
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              BITFIELD(0, 1)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              (0x3 << 0)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              4
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               BITFIELD(4, 5)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               (0x3 << 4)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              2
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               BITFIELD(2, 3)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               (0x3 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_RA_ERR_SHIFT                                      25
+#define OMAP4430_BYPS_RA_ERR_MASK                                       (1 << 25)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_SA_ERR_SHIFT                                      24
+#define OMAP4430_BYPS_SA_ERR_MASK                                       (1 << 24)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT                                 26
+#define OMAP4430_BYPS_TIMEOUT_ERR_MASK                                  (1 << 26)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_C2C_RST_SHIFT                                          10
+#define OMAP4430_C2C_RST_MASK                                           (1 << 10)
 
 /* Used by PM_CAM_PWRSTCTRL */
 #define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_CAM_PWRSTST */
 #define OMAP4430_CAM_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_CAM_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_CAM_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PRM_CLKREQCTRL */
 #define OMAP4430_CLKREQ_COND_SHIFT                                      0
-#define OMAP4430_CLKREQ_COND_MASK                                       BITFIELD(0, 2)
+#define OMAP4430_CLKREQ_COND_MASK                                       (0x7 << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 0
-#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  (0xff << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  8
-#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   (0xff << 8)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  16
-#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   (0xff << 16)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   4
-#define OMAP4430_CMD_VDD_CORE_L_MASK                                    BITFIELD(4, 4)
+#define OMAP4430_CMD_VDD_CORE_L_MASK                                    (1 << 4)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    12
-#define OMAP4430_CMD_VDD_IVA_L_MASK                                     BITFIELD(12, 12)
+#define OMAP4430_CMD_VDD_IVA_L_MASK                                     (1 << 12)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    17
-#define OMAP4430_CMD_VDD_MPU_L_MASK                                     BITFIELD(17, 17)
+#define OMAP4430_CMD_VDD_MPU_L_MASK                                     (1 << 17)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              18
-#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               BITFIELD(18, 19)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               (0x3 << 18)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             9
-#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              BITFIELD(9, 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              (1 << 9)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              6
-#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               BITFIELD(6, 7)
+#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               (0x3 << 6)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          16
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           BITFIELD(16, 17)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           (0x3 << 16)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         8
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          BITFIELD(8, 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          (1 << 8)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          4
-#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           BITFIELD(4, 5)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_CUSTOM_SHIFT                                           6
+#define OMAP4430_CUSTOM_MASK                                            (0x3 << 6)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_DATA_SHIFT                                             16
-#define OMAP4430_DATA_MASK                                              BITFIELD(16, 23)
+#define OMAP4430_DATA_MASK                                              (0xff << 16)
 
 /* Used by PRM_DEVICE_OFF_CTRL */
 #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                0
-#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 (1 << 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_DFILTEREN_SHIFT                                        6
-#define OMAP4430_DFILTEREN_MASK                                         BITFIELD(6, 6)
+#define OMAP4430_DFILTEREN_MASK                                         (1 << 6)
 
-/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT                               0
+#define OMAP4430_DISABLE_RTA_EXPORT_MASK                                (1 << 0)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 (1 << 4)
 
-/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                BITFIELD(0, 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                (1 << 0)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                BITFIELD(0, 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                (1 << 0)
 
 /* Used by PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              BITFIELD(6, 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              (1 << 6)
 
 /* Used by PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              BITFIELD(6, 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              (1 << 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 (1 << 2)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 (1 << 2)
 
 /* Used by PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 (1 << 1)
 
 /* Used by PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 (1 << 1)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 (1 << 3)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 (1 << 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              BITFIELD(7, 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              (1 << 7)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              BITFIELD(7, 7)
-
-/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                5
-#define OMAP4430_DPLL_USB_RECAL_EN_MASK                                 BITFIELD(5, 5)
-
-/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                5
-#define OMAP4430_DPLL_USB_RECAL_ST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              (1 << 7)
 
 /* Used by PM_DSS_PWRSTCTRL */
 #define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_DSS_PWRSTCTRL */
 #define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_DSS_PWRSTST */
 #define OMAP4430_DSS_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_DSS_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_DSS_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             20
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              BITFIELD(20, 21)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              (0x3 << 20)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            10
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             BITFIELD(10, 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             (1 << 10)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             8
-#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              BITFIELD(8, 9)
+#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              (0x3 << 8)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          22
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           BITFIELD(22, 23)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           (0x3 << 22)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         11
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          BITFIELD(11, 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          (1 << 11)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          10
-#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           BITFIELD(10, 11)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           (0x3 << 10)
 
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_EMULATION_RST_SHIFT                                    0
-#define OMAP4430_EMULATION_RST_MASK                                     BITFIELD(0, 0)
+#define OMAP4430_EMULATION_RST_MASK                                     (1 << 0)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_EMULATION_RST1ST_SHIFT                                 3
-#define OMAP4430_EMULATION_RST1ST_MASK                                  BITFIELD(3, 3)
+#define OMAP4430_EMULATION_RST1ST_MASK                                  (1 << 3)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_EMULATION_RST2ST_SHIFT                                 4
-#define OMAP4430_EMULATION_RST2ST_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_EMULATION_RST2ST_MASK                                  (1 << 4)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            3
-#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             BITFIELD(3, 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             (1 << 3)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            4
-#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             BITFIELD(4, 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             (1 << 4)
 
 /* Used by PM_EMU_PWRSTCTRL */
 #define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 16
-#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  BITFIELD(16, 17)
+#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  (0x3 << 16)
 
 /* Used by PM_EMU_PWRSTST */
 #define OMAP4430_EMU_BANK_STATEST_SHIFT                                 4
-#define OMAP4430_EMU_BANK_STATEST_MASK                                  BITFIELD(4, 5)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
- */
-#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                0
-#define OMAP4430_ENABLE_RTA_EXPORT_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_EMU_BANK_STATEST_MASK                                  (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC1_SHIFT                                          3
-#define OMAP4430_ENFUNC1_MASK                                           BITFIELD(3, 3)
+#define OMAP4430_ENFUNC1_EXPORT_SHIFT                                   3
+#define OMAP4430_ENFUNC1_EXPORT_MASK                                    (1 << 3)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC3_SHIFT                                          5
-#define OMAP4430_ENFUNC3_MASK                                           BITFIELD(5, 5)
+#define OMAP4430_ENFUNC3_EXPORT_SHIFT                                   5
+#define OMAP4430_ENFUNC3_EXPORT_MASK                                    (1 << 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ENFUNC4_SHIFT                                          6
-#define OMAP4430_ENFUNC4_MASK                                           BITFIELD(6, 6)
+#define OMAP4430_ENFUNC4_MASK                                           (1 << 6)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ENFUNC5_SHIFT                                          7
-#define OMAP4430_ENFUNC5_MASK                                           BITFIELD(7, 7)
+#define OMAP4430_ENFUNC5_MASK                                           (1 << 7)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_ERRORGAIN_SHIFT                                        16
-#define OMAP4430_ERRORGAIN_MASK                                         BITFIELD(16, 23)
+#define OMAP4430_ERRORGAIN_MASK                                         (0xff << 16)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_ERROROFFSET_SHIFT                                      24
-#define OMAP4430_ERROROFFSET_MASK                                       BITFIELD(24, 31)
+#define OMAP4430_ERROROFFSET_MASK                                       (0xff << 24)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                5
-#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 (1 << 5)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_FORCEUPDATE_SHIFT                                      1
-#define OMAP4430_FORCEUPDATE_MASK                                       BITFIELD(1, 1)
+#define OMAP4430_FORCEUPDATE_MASK                                       (1 << 1)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 #define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  8
-#define OMAP4430_FORCEUPDATEWAIT_MASK                                   BITFIELD(8, 31)
+#define OMAP4430_FORCEUPDATEWAIT_MASK                                   (0xffffff << 8)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
 #define OMAP4430_FORCEWKUP_EN_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_EN_MASK                                      BITFIELD(10, 10)
+#define OMAP4430_FORCEWKUP_EN_MASK                                      (1 << 10)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_FORCEWKUP_ST_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_ST_MASK                                      BITFIELD(10, 10)
+#define OMAP4430_FORCEWKUP_ST_MASK                                      (1 << 10)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_FUNC_SHIFT                                             16
+#define OMAP4430_FUNC_MASK                                              (0xfff << 16)
 
 /* Used by PM_GFX_PWRSTCTRL */
 #define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_GFX_PWRSTST */
 #define OMAP4430_GFX_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_GFX_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_GFX_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  0
-#define OMAP4430_GLOBAL_COLD_RST_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_GLOBAL_COLD_RST_MASK                                   (1 << 0)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               1
-#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                BITFIELD(1, 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_GLOBAL_WUEN_SHIFT                                      16
-#define OMAP4430_GLOBAL_WUEN_MASK                                       BITFIELD(16, 16)
+#define OMAP4430_GLOBAL_WUEN_MASK                                       (1 << 16)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_HSMCODE_SHIFT                                          0
-#define OMAP4430_HSMCODE_MASK                                           BITFIELD(0, 2)
+#define OMAP4430_HSMCODE_MASK                                           (0x7 << 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_HSMODEEN_SHIFT                                         3
-#define OMAP4430_HSMODEEN_MASK                                          BITFIELD(3, 3)
+#define OMAP4430_HSMODEEN_MASK                                          (1 << 3)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLH_SHIFT                                           16
-#define OMAP4430_HSSCLH_MASK                                            BITFIELD(16, 23)
+#define OMAP4430_HSSCLH_MASK                                            (0xff << 16)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLL_SHIFT                                           24
-#define OMAP4430_HSSCLL_MASK                                            BITFIELD(24, 31)
+#define OMAP4430_HSSCLL_MASK                                            (0xff << 24)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_HWA_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_HWA_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_HWA_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               1
-#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                BITFIELD(1, 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                (1 << 1)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                5
-#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 (1 << 5)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                6
-#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 BITFIELD(6, 6)
+#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 (1 << 6)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           5
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            BITFIELD(5, 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            (1 << 5)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           6
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            BITFIELD(6, 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            (1 << 6)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_ICEPICK_RST_SHIFT                                      9
-#define OMAP4430_ICEPICK_RST_MASK                                       BITFIELD(9, 9)
+#define OMAP4430_ICEPICK_RST_MASK                                       (1 << 9)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_INITVDD_SHIFT                                          2
-#define OMAP4430_INITVDD_MASK                                           BITFIELD(2, 2)
+#define OMAP4430_INITVDD_MASK                                           (1 << 2)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_INITVOLTAGE_SHIFT                                      8
-#define OMAP4430_INITVOLTAGE_MASK                                       BITFIELD(8, 15)
+#define OMAP4430_INITVOLTAGE_MASK                                       (0xff << 8)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_INTRANSITION_SHIFT                                     20
-#define OMAP4430_INTRANSITION_MASK                                      BITFIELD(20, 20)
+#define OMAP4430_INTRANSITION_MASK                                      (1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_IO_EN_SHIFT                                            9
-#define OMAP4430_IO_EN_MASK                                             BITFIELD(9, 9)
+#define OMAP4430_IO_EN_MASK                                             (1 << 9)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_IO_ON_STATUS_SHIFT                                     5
-#define OMAP4430_IO_ON_STATUS_MASK                                      BITFIELD(5, 5)
+#define OMAP4430_IO_ON_STATUS_MASK                                      (1 << 5)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_IO_ST_SHIFT                                            9
-#define OMAP4430_IO_ST_MASK                                             BITFIELD(9, 9)
+#define OMAP4430_IO_ST_MASK                                             (1 << 9)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  0
-#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   (1 << 0)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOCLK_STATUS_SHIFT                                    1
-#define OMAP4430_ISOCLK_STATUS_MASK                                     BITFIELD(1, 1)
+#define OMAP4430_ISOCLK_STATUS_MASK                                     (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOOVR_EXTEND_SHIFT                                    4
-#define OMAP4430_ISOOVR_EXTEND_MASK                                     BITFIELD(4, 4)
+#define OMAP4430_ISOOVR_EXTEND_MASK                                     (1 << 4)
 
 /* Used by PRM_IO_COUNT */
 #define OMAP4430_ISO_2_ON_TIME_SHIFT                                    0
-#define OMAP4430_ISO_2_ON_TIME_MASK                                     BITFIELD(0, 7)
+#define OMAP4430_ISO_2_ON_TIME_MASK                                     (0xff << 0)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
 #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             16
-#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              BITFIELD(16, 17)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              (0x3 << 16)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
 #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            8
-#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             BITFIELD(8, 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             (1 << 8)
 
 /* Used by PM_L3INIT_PWRSTST */
 #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             4
-#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              BITFIELD(4, 5)
+#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              (0x3 << 4)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ */
+#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT                            24
+#define OMAP4430_LASTPOWERSTATEENTERED_MASK                             (0x3 << 24)
 
 /*
- * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
- * PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_LOGICRETSTATE_SHIFT                                    2
-#define OMAP4430_LOGICRETSTATE_MASK                                     BITFIELD(2, 2)
+#define OMAP4430_LOGICRETSTATE_MASK                                     (1 << 2)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_LOGICSTATEST_SHIFT                                     2
-#define OMAP4430_LOGICSTATEST_MASK                                      BITFIELD(2, 2)
+#define OMAP4430_LOGICSTATEST_MASK                                      (1 << 2)
 
 /*
- * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT,
- * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT,
- * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT,
- * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT,
- * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT,
- * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
- * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT,
- * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT,
- * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT,
- * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT,
- * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
- * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
- * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
- * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
  * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
  * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
  * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
- * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT,
- * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT,
- * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT,
- * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT,
- * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT,
- * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT,
- * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT,
- * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
- * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
- * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT,
- * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
- * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
- * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
- * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT,
- * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
- * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
+ * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
+ * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
+ * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
+ * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
+ * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
+ * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
+ * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
+ * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
+ * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
+ * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
+ * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
+ * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
+ * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
+ * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
+ * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
+ * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
+ * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
+ * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
+ * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
+ * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
+ * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
+ * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
+ * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
  */
 #define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  0
-#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   (1 << 0)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
+ * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
+ * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
  * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
- * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT,
- * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
- * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT,
- * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT,
- * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT,
- * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT,
- * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT,
- * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT,
- * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
- * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT,
- * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
- * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
+ * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
+ * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
+ * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
  */
 #define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  1
-#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   BITFIELD(1, 1)
+#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   (1 << 1)
 
 /* Used by RM_ABE_AESS_CONTEXT */
 #define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   (1 << 8)
 
 /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
 #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           8
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            (1 << 8)
 
 /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       9
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        (1 << 9)
 
 /* Used by RM_L3_2_OCMC_RAM_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              8
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               (1 << 8)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
  * RM_SDMA_SDMA_CONTEXT
  */
 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          8
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           (1 << 8)
 
 /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
 #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             9
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              (1 << 9)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          8
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           (1 << 8)
 
 /* Used by RM_EMU_DEBUGSS_CONTEXT */
 #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 8
-#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  (1 << 8)
 
 /* Used by RM_GFX_GFX_CONTEXT */
 #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   (1 << 10)
 
 /*
  * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
@@ -620,19 +642,19 @@
  * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
  */
 #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             8
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              (1 << 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   8
-#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    (1 << 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   9
-#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    (1 << 9)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   (1 << 10)
 
 /*
  * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
@@ -640,14 +662,14 @@
  * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
  */
 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         8
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          (1 << 8)
 
 /*
  * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
  * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
  */
 #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                8
-#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 (1 << 8)
 
 /*
  * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
@@ -655,245 +677,237 @@
  * RM_L4SEC_CRYPTODMA_CONTEXT
  */
 #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            8
-#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             (1 << 8)
 
 /* Used by RM_IVAHD_SL2_CONTEXT */
 #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  (1 << 9)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               10
-#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                (1 << 10)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  (1 << 8)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  (1 << 9)
 
 /* Used by RM_WKUP_SARRAM_CONTEXT */
 #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                8
-#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 (1 << 8)
 
 /*
- * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
- * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
+ * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              4
-#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               BITFIELD(4, 4)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_MEMORYCHANGE_SHIFT                                     3
-#define OMAP4430_MEMORYCHANGE_MASK                                      BITFIELD(3, 3)
+#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               (1 << 4)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_READY_SHIFT                                      1
-#define OMAP4430_MODEM_READY_MASK                                       BITFIELD(1, 1)
+#define OMAP4430_MODEM_READY_MASK                                       (1 << 1)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               9
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                BITFIELD(9, 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                (1 << 9)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   16
-#define OMAP4430_MODEM_SLEEP_ST_MASK                                    BITFIELD(16, 16)
+#define OMAP4430_MODEM_SLEEP_ST_MASK                                    (1 << 16)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   8
-#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    (1 << 8)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   16
-#define OMAP4430_MPU_L1_ONSTATE_MASK                                    BITFIELD(16, 17)
+#define OMAP4430_MPU_L1_ONSTATE_MASK                                    (0x3 << 16)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  8
-#define OMAP4430_MPU_L1_RETSTATE_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_MPU_L1_RETSTATE_MASK                                   (1 << 8)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_L1_STATEST_SHIFT                                   4
-#define OMAP4430_MPU_L1_STATEST_MASK                                    BITFIELD(4, 5)
+#define OMAP4430_MPU_L1_STATEST_MASK                                    (0x3 << 4)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   18
-#define OMAP4430_MPU_L2_ONSTATE_MASK                                    BITFIELD(18, 19)
+#define OMAP4430_MPU_L2_ONSTATE_MASK                                    (0x3 << 18)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  9
-#define OMAP4430_MPU_L2_RETSTATE_MASK                                   BITFIELD(9, 9)
+#define OMAP4430_MPU_L2_RETSTATE_MASK                                   (1 << 9)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_L2_STATEST_SHIFT                                   6
-#define OMAP4430_MPU_L2_STATEST_MASK                                    BITFIELD(6, 7)
+#define OMAP4430_MPU_L2_STATEST_MASK                                    (0x3 << 6)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  20
-#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   BITFIELD(20, 21)
+#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   (0x3 << 20)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 10
-#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  BITFIELD(10, 10)
+#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  (1 << 10)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_RAM_STATEST_SHIFT                                  8
-#define OMAP4430_MPU_RAM_STATEST_MASK                                   BITFIELD(8, 9)
+#define OMAP4430_MPU_RAM_STATEST_MASK                                   (0x3 << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            2
-#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             BITFIELD(2, 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             (1 << 2)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_MPU_WDT_RST_SHIFT                                      3
-#define OMAP4430_MPU_WDT_RST_MASK                                       BITFIELD(3, 3)
+#define OMAP4430_MPU_WDT_RST_MASK                                       (1 << 3)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         18
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          BITFIELD(18, 19)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          (0x3 << 18)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        9
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         BITFIELD(9, 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         (1 << 9)
 
 /* Used by PM_L4PER_PWRSTST */
 #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         6
-#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          BITFIELD(6, 7)
+#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          (0x3 << 6)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            24
-#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             BITFIELD(24, 25)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             (0x3 << 24)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           12
-#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            BITFIELD(12, 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            (1 << 12)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            12
-#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             BITFIELD(12, 13)
+#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             (0x3 << 12)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_OFF_SHIFT                                              0
-#define OMAP4430_OFF_MASK                                               BITFIELD(0, 7)
-
-/* Used by PRM_LDO_BANDGAP_CTRL */
-#define OMAP4430_OFF_ENABLE_SHIFT                                       0
-#define OMAP4430_OFF_ENABLE_MASK                                        BITFIELD(0, 0)
+#define OMAP4430_OFF_MASK                                               (0xff << 0)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_ON_SHIFT                                               24
-#define OMAP4430_ON_MASK                                                BITFIELD(24, 31)
+#define OMAP4430_ON_MASK                                                (0xff << 24)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_ONLP_SHIFT                                             16
-#define OMAP4430_ONLP_MASK                                              BITFIELD(16, 23)
+#define OMAP4430_ONLP_MASK                                              (0xff << 16)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_OPP_CHANGE_SHIFT                                       2
-#define OMAP4430_OPP_CHANGE_MASK                                        BITFIELD(2, 2)
+#define OMAP4430_OPP_CHANGE_MASK                                        (1 << 2)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_OPP_SEL_SHIFT                                          0
-#define OMAP4430_OPP_SEL_MASK                                           BITFIELD(0, 1)
+#define OMAP4430_OPP_SEL_MASK                                           (0x3 << 0)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 0
-#define OMAP4430_PCHARGECNT_VALUE_MASK                                  BITFIELD(0, 5)
+#define OMAP4430_PCHARGECNT_VALUE_MASK                                  (0x3f << 0)
 
 /* Used by PRM_PSCON_COUNT */
 #define OMAP4430_PCHARGE_TIME_SHIFT                                     0
-#define OMAP4430_PCHARGE_TIME_MASK                                      BITFIELD(0, 7)
+#define OMAP4430_PCHARGE_TIME_MASK                                      (0xff << 0)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                20
-#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 BITFIELD(20, 21)
+#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 (0x3 << 20)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               10
-#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                BITFIELD(10, 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                (1 << 10)
 
 /* Used by PM_ABE_PWRSTST */
 #define OMAP4430_PERIPHMEM_STATEST_SHIFT                                8
-#define OMAP4430_PERIPHMEM_STATEST_MASK                                 BITFIELD(8, 9)
+#define OMAP4430_PERIPHMEM_STATEST_MASK                                 (0x3 << 8)
 
 /* Used by PRM_PHASE1_CNDP */
 #define OMAP4430_PHASE1_CNDP_SHIFT                                      0
-#define OMAP4430_PHASE1_CNDP_MASK                                       BITFIELD(0, 31)
+#define OMAP4430_PHASE1_CNDP_MASK                                       (0xffffffff << 0)
 
 /* Used by PRM_PHASE2A_CNDP */
 #define OMAP4430_PHASE2A_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2A_CNDP_MASK                                      BITFIELD(0, 31)
+#define OMAP4430_PHASE2A_CNDP_MASK                                      (0xffffffff << 0)
 
 /* Used by PRM_PHASE2B_CNDP */
 #define OMAP4430_PHASE2B_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2B_CNDP_MASK                                      BITFIELD(0, 31)
+#define OMAP4430_PHASE2B_CNDP_MASK                                      (0xffffffff << 0)
 
 /* Used by PRM_PSCON_COUNT */
 #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            8
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             BITFIELD(8, 15)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             (0xff << 8)
 
 /*
- * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL,
- * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL,
- * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_POWERSTATE_SHIFT                                       0
-#define OMAP4430_POWERSTATE_MASK                                        BITFIELD(0, 1)
+#define OMAP4430_POWERSTATE_MASK                                        (0x3 << 0)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_POWERSTATEST_SHIFT                                     0
-#define OMAP4430_POWERSTATEST_MASK                                      BITFIELD(0, 1)
+#define OMAP4430_POWERSTATEST_MASK                                      (0x3 << 0)
 
 /* Used by PRM_PWRREQCTRL */
 #define OMAP4430_PWRREQ_COND_SHIFT                                      0
-#define OMAP4430_PWRREQ_COND_MASK                                       BITFIELD(0, 1)
+#define OMAP4430_PWRREQ_COND_MASK                                       (0x3 << 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 3
-#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  BITFIELD(3, 3)
+#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  (1 << 3)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  11
-#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   BITFIELD(11, 11)
+#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   (1 << 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  20
-#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   BITFIELD(20, 20)
+#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   (1 << 20)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   2
-#define OMAP4430_RAC_VDD_CORE_L_MASK                                    BITFIELD(2, 2)
+#define OMAP4430_RAC_VDD_CORE_L_MASK                                    (1 << 2)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    10
-#define OMAP4430_RAC_VDD_IVA_L_MASK                                     BITFIELD(10, 10)
+#define OMAP4430_RAC_VDD_IVA_L_MASK                                     (1 << 10)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    19
-#define OMAP4430_RAC_VDD_MPU_L_MASK                                     BITFIELD(19, 19)
+#define OMAP4430_RAC_VDD_MPU_L_MASK                                     (1 << 19)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -901,7 +915,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  16
-#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   BITFIELD(16, 21)
+#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   (0x3f << 16)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -909,7 +923,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                24
-#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 BITFIELD(24, 25)
+#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 (0x3 << 24)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -917,7 +931,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_UP_COUNT_SHIFT                                    0
-#define OMAP4430_RAMP_UP_COUNT_MASK                                     BITFIELD(0, 5)
+#define OMAP4430_RAMP_UP_COUNT_MASK                                     (0x3f << 0)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -925,1281 +939,1381 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  8
-#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   BITFIELD(8, 9)
+#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   (0x3 << 8)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   1
-#define OMAP4430_RAV_VDD_CORE_L_MASK                                    BITFIELD(1, 1)
+#define OMAP4430_RAV_VDD_CORE_L_MASK                                    (1 << 1)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    9
-#define OMAP4430_RAV_VDD_IVA_L_MASK                                     BITFIELD(9, 9)
+#define OMAP4430_RAV_VDD_IVA_L_MASK                                     (1 << 9)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    18
-#define OMAP4430_RAV_VDD_MPU_L_MASK                                     BITFIELD(18, 18)
+#define OMAP4430_RAV_VDD_MPU_L_MASK                                     (1 << 18)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_REGADDR_SHIFT                                          8
-#define OMAP4430_REGADDR_MASK                                           BITFIELD(8, 15)
+#define OMAP4430_REGADDR_MASK                                           (0xff << 8)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_RET_SHIFT                                              8
-#define OMAP4430_RET_MASK                                               BITFIELD(8, 15)
+#define OMAP4430_RET_MASK                                               (0xff << 8)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            16
-#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             BITFIELD(16, 17)
+#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             (0x3 << 16)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           8
-#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            BITFIELD(8, 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            (1 << 8)
 
 /* Used by PM_L4PER_PWRSTST */
 #define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            4
-#define OMAP4430_RETAINED_BANK_STATEST_MASK                             BITFIELD(4, 5)
+#define OMAP4430_RETAINED_BANK_STATEST_MASK                             (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_RETMODE_ENABLE_SHIFT                                   0
-#define OMAP4430_RETMODE_ENABLE_MASK                                    BITFIELD(0, 0)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_REV_SHIFT                                              0
-#define OMAP4430_REV_MASK                                               BITFIELD(0, 7)
+#define OMAP4430_RETMODE_ENABLE_MASK                                    (1 << 0)
 
-/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 #define OMAP4430_RST1_SHIFT                                             0
-#define OMAP4430_RST1_MASK                                              BITFIELD(0, 0)
+#define OMAP4430_RST1_MASK                                              (1 << 0)
 
-/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 #define OMAP4430_RST1ST_SHIFT                                           0
-#define OMAP4430_RST1ST_MASK                                            BITFIELD(0, 0)
+#define OMAP4430_RST1ST_MASK                                            (1 << 0)
 
-/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 #define OMAP4430_RST2_SHIFT                                             1
-#define OMAP4430_RST2_MASK                                              BITFIELD(1, 1)
+#define OMAP4430_RST2_MASK                                              (1 << 1)
 
-/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 #define OMAP4430_RST2ST_SHIFT                                           1
-#define OMAP4430_RST2ST_MASK                                            BITFIELD(1, 1)
+#define OMAP4430_RST2ST_MASK                                            (1 << 1)
 
 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
 #define OMAP4430_RST3_SHIFT                                             2
-#define OMAP4430_RST3_MASK                                              BITFIELD(2, 2)
+#define OMAP4430_RST3_MASK                                              (1 << 2)
 
 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
 #define OMAP4430_RST3ST_SHIFT                                           2
-#define OMAP4430_RST3ST_MASK                                            BITFIELD(2, 2)
+#define OMAP4430_RST3ST_MASK                                            (1 << 2)
 
 /* Used by PRM_RSTTIME */
 #define OMAP4430_RSTTIME1_SHIFT                                         0
-#define OMAP4430_RSTTIME1_MASK                                          BITFIELD(0, 9)
+#define OMAP4430_RSTTIME1_MASK                                          (0x3ff << 0)
 
 /* Used by PRM_RSTTIME */
 #define OMAP4430_RSTTIME2_SHIFT                                         10
-#define OMAP4430_RSTTIME2_MASK                                          BITFIELD(10, 14)
+#define OMAP4430_RSTTIME2_MASK                                          (0x1f << 10)
 
 /* Used by PRM_RSTCTRL */
 #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               1
-#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                BITFIELD(1, 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                (1 << 1)
 
 /* Used by PRM_RSTCTRL */
 #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               0
-#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                BITFIELD(0, 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                (1 << 0)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_R_RTL_SHIFT                                            11
+#define OMAP4430_R_RTL_MASK                                             (0x1f << 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_CORE_L_SHIFT                                    0
-#define OMAP4430_SA_VDD_CORE_L_MASK                                     BITFIELD(0, 0)
+#define OMAP4430_SA_VDD_CORE_L_MASK                                     (1 << 0)
 
 /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                0
-#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 BITFIELD(0, 6)
+#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 (0x7f << 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_IVA_L_SHIFT                                     8
-#define OMAP4430_SA_VDD_IVA_L_MASK                                      BITFIELD(8, 8)
+#define OMAP4430_SA_VDD_IVA_L_MASK                                      (1 << 8)
 
 /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      8
-#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(8, 14)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 8)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_MPU_L_SHIFT                                     16
-#define OMAP4430_SA_VDD_MPU_L_MASK                                      BITFIELD(16, 16)
+#define OMAP4430_SA_VDD_MPU_L_MASK                                      (1 << 16)
 
 /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      16
-#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(16, 22)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 16)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_SCHEME_SHIFT                                           30
+#define OMAP4430_SCHEME_MASK                                            (0x3 << 30)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLH_SHIFT                                             0
-#define OMAP4430_SCLH_MASK                                              BITFIELD(0, 7)
+#define OMAP4430_SCLH_MASK                                              (0xff << 0)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLL_SHIFT                                             8
-#define OMAP4430_SCLL_MASK                                              BITFIELD(8, 15)
+#define OMAP4430_SCLL_MASK                                              (0xff << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_SECURE_WDT_RST_SHIFT                                   4
-#define OMAP4430_SECURE_WDT_RST_MASK                                    BITFIELD(4, 4)
+#define OMAP4430_SECURE_WDT_RST_MASK                                    (1 << 4)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  18
-#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   BITFIELD(18, 19)
+#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   (0x3 << 18)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 9
-#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  (1 << 9)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_SL2_MEM_STATEST_SHIFT                                  6
-#define OMAP4430_SL2_MEM_STATEST_MASK                                   BITFIELD(6, 7)
+#define OMAP4430_SL2_MEM_STATEST_MASK                                   (0x3 << 6)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_SLAVEADDR_SHIFT                                        0
-#define OMAP4430_SLAVEADDR_MASK                                         BITFIELD(0, 6)
+#define OMAP4430_SLAVEADDR_MASK                                         (0x7f << 0)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    3
-#define OMAP4430_SLEEP_RBB_SEL_MASK                                     BITFIELD(3, 3)
+#define OMAP4430_SLEEP_RBB_SEL_MASK                                     (1 << 3)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_SLPCNT_VALUE_SHIFT                                     16
-#define OMAP4430_SLPCNT_VALUE_MASK                                      BITFIELD(16, 23)
+#define OMAP4430_SLPCNT_VALUE_MASK                                      (0xff << 16)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   BITFIELD(8, 23)
+#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   (0xffff << 8)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   BITFIELD(8, 23)
+#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   (0xffff << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT                                 1
+#define OMAP4430_SMPS_RA_ERR_CORE_MASK                                  (1 << 1)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT                                  9
+#define OMAP4430_SMPS_RA_ERR_IVA_MASK                                   (1 << 9)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT                                  17
+#define OMAP4430_SMPS_RA_ERR_MPU_MASK                                   (1 << 17)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT                                 0
+#define OMAP4430_SMPS_SA_ERR_CORE_MASK                                  (1 << 0)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT                                  8
+#define OMAP4430_SMPS_SA_ERR_IVA_MASK                                   (1 << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT                                  16
+#define OMAP4430_SMPS_SA_ERR_MPU_MASK                                   (1 << 16)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT                            2
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK                             (1 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT                             10
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK                              (1 << 10)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT                             18
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK                              (1 << 18)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SR2EN_SHIFT                                            0
-#define OMAP4430_SR2EN_MASK                                             BITFIELD(0, 0)
+#define OMAP4430_SR2EN_MASK                                             (1 << 0)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_SR2_IN_TRANSITION_SHIFT                                6
-#define OMAP4430_SR2_IN_TRANSITION_MASK                                 BITFIELD(6, 6)
+#define OMAP4430_SR2_IN_TRANSITION_MASK                                 (1 << 6)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_SR2_STATUS_SHIFT                                       3
-#define OMAP4430_SR2_STATUS_MASK                                        BITFIELD(3, 4)
+#define OMAP4430_SR2_STATUS_MASK                                        (0x3 << 3)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  8
-#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   (0xff << 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_SRAMLDO_STATUS_SHIFT                                   8
-#define OMAP4430_SRAMLDO_STATUS_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_SRAMLDO_STATUS_MASK                                    (1 << 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               9
-#define OMAP4430_SRAM_IN_TRANSITION_MASK                                BITFIELD(9, 9)
+#define OMAP4430_SRAM_IN_TRANSITION_MASK                                (1 << 9)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_SRMODEEN_SHIFT                                         4
-#define OMAP4430_SRMODEEN_MASK                                          BITFIELD(4, 4)
+#define OMAP4430_SRMODEEN_MASK                                          (1 << 4)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
 #define OMAP4430_STABLE_COUNT_SHIFT                                     0
-#define OMAP4430_STABLE_COUNT_MASK                                      BITFIELD(0, 5)
+#define OMAP4430_STABLE_COUNT_MASK                                      (0x3f << 0)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
 #define OMAP4430_STABLE_PRESCAL_SHIFT                                   8
-#define OMAP4430_STABLE_PRESCAL_MASK                                    BITFIELD(8, 9)
+#define OMAP4430_STABLE_PRESCAL_MASK                                    (0x3 << 8)
+
+/* Used by PRM_LDO_BANDGAP_SETUP */
+#define OMAP4430_STARTUP_COUNT_SHIFT                                    0
+#define OMAP4430_STARTUP_COUNT_MASK                                     (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP4430_STARTUP_COUNT_24_31_SHIFT                              24
+#define OMAP4430_STARTUP_COUNT_24_31_MASK                               (0xff << 24)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 20
-#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  BITFIELD(20, 21)
+#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  (0x3 << 20)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                10
-#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 BITFIELD(10, 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 (1 << 10)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 8
-#define OMAP4430_TCM1_MEM_STATEST_MASK                                  BITFIELD(8, 9)
+#define OMAP4430_TCM1_MEM_STATEST_MASK                                  (0x3 << 8)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 22
-#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  BITFIELD(22, 23)
+#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  (0x3 << 22)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                11
-#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 BITFIELD(11, 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 (1 << 11)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 10
-#define OMAP4430_TCM2_MEM_STATEST_MASK                                  BITFIELD(10, 11)
+#define OMAP4430_TCM2_MEM_STATEST_MASK                                  (0x3 << 10)
 
 /* Used by RM_TESLA_RSTST */
 #define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                2
-#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 (1 << 2)
 
 /* Used by RM_TESLA_RSTST */
 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          3
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           BITFIELD(3, 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           (1 << 3)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               20
-#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                BITFIELD(20, 21)
+#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                (0x3 << 20)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              10
-#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               BITFIELD(10, 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               (1 << 10)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               8
-#define OMAP4430_TESLA_EDMA_STATEST_MASK                                BITFIELD(8, 9)
+#define OMAP4430_TESLA_EDMA_STATEST_MASK                                (0x3 << 8)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 16
-#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  BITFIELD(16, 17)
+#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  (0x3 << 16)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                8
-#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 (1 << 8)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_L1_STATEST_SHIFT                                 4
-#define OMAP4430_TESLA_L1_STATEST_MASK                                  BITFIELD(4, 5)
+#define OMAP4430_TESLA_L1_STATEST_MASK                                  (0x3 << 4)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 18
-#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  BITFIELD(18, 19)
+#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  (0x3 << 18)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                9
-#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 BITFIELD(9, 9)
+#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 (1 << 9)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_L2_STATEST_SHIFT                                 6
-#define OMAP4430_TESLA_L2_STATEST_MASK                                  BITFIELD(6, 7)
+#define OMAP4430_TESLA_L2_STATEST_MASK                                  (0x3 << 6)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_TIMEOUT_SHIFT                                          0
-#define OMAP4430_TIMEOUT_MASK                                           BITFIELD(0, 15)
+#define OMAP4430_TIMEOUT_MASK                                           (0xffff << 0)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_TIMEOUTEN_SHIFT                                        3
-#define OMAP4430_TIMEOUTEN_MASK                                         BITFIELD(3, 3)
+#define OMAP4430_TIMEOUTEN_MASK                                         (1 << 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_TRANSITION_EN_SHIFT                                    8
-#define OMAP4430_TRANSITION_EN_MASK                                     BITFIELD(8, 8)
+#define OMAP4430_TRANSITION_EN_MASK                                     (1 << 8)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_TRANSITION_ST_SHIFT                                    8
-#define OMAP4430_TRANSITION_ST_MASK                                     BITFIELD(8, 8)
+#define OMAP4430_TRANSITION_ST_MASK                                     (1 << 8)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_VALID_SHIFT                                            24
-#define OMAP4430_VALID_MASK                                             BITFIELD(24, 24)
+#define OMAP4430_VALID_MASK                                             (1 << 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_EN_MASK                                   BITFIELD(14, 14)
+#define OMAP4430_VC_BYPASSACK_EN_MASK                                   (1 << 14)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_ST_MASK                                   BITFIELD(14, 14)
+#define OMAP4430_VC_BYPASSACK_ST_MASK                                   (1 << 14)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_CORE_VPACK_EN_SHIFT                                 22
+#define OMAP4430_VC_CORE_VPACK_EN_MASK                                  (1 << 22)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_CORE_VPACK_ST_SHIFT                                 22
+#define OMAP4430_VC_CORE_VPACK_ST_MASK                                  (1 << 22)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   BITFIELD(30, 30)
+#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   (1 << 30)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   BITFIELD(30, 30)
+#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   (1 << 30)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   BITFIELD(6, 6)
+#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   (1 << 6)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   BITFIELD(6, 6)
+#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   (1 << 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_RAERR_EN_SHIFT                                      12
-#define OMAP4430_VC_RAERR_EN_MASK                                       BITFIELD(12, 12)
+#define OMAP4430_VC_RAERR_EN_MASK                                       (1 << 12)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_RAERR_ST_SHIFT                                      12
-#define OMAP4430_VC_RAERR_ST_MASK                                       BITFIELD(12, 12)
+#define OMAP4430_VC_RAERR_ST_MASK                                       (1 << 12)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_SAERR_EN_SHIFT                                      11
-#define OMAP4430_VC_SAERR_EN_MASK                                       BITFIELD(11, 11)
+#define OMAP4430_VC_SAERR_EN_MASK                                       (1 << 11)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_SAERR_ST_SHIFT                                      11
-#define OMAP4430_VC_SAERR_ST_MASK                                       BITFIELD(11, 11)
+#define OMAP4430_VC_SAERR_ST_MASK                                       (1 << 11)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_TOERR_EN_SHIFT                                      13
-#define OMAP4430_VC_TOERR_EN_MASK                                       BITFIELD(13, 13)
+#define OMAP4430_VC_TOERR_EN_MASK                                       (1 << 13)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_TOERR_ST_SHIFT                                      13
-#define OMAP4430_VC_TOERR_ST_MASK                                       BITFIELD(13, 13)
+#define OMAP4430_VC_TOERR_ST_MASK                                       (1 << 13)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMAX_SHIFT                                           24
-#define OMAP4430_VDDMAX_MASK                                            BITFIELD(24, 31)
+#define OMAP4430_VDDMAX_MASK                                            (0xff << 24)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMIN_SHIFT                                           16
-#define OMAP4430_VDDMIN_MASK                                            BITFIELD(16, 23)
+#define OMAP4430_VDDMIN_MASK                                            (0xff << 16)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             12
-#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              BITFIELD(12, 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              (1 << 12)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            8
-#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             BITFIELD(8, 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             (1 << 8)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              14
-#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               BITFIELD(14, 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               (1 << 14)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 9
-#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  (1 << 9)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             7
-#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              BITFIELD(7, 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              (1 << 7)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              13
-#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               BITFIELD(13, 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               (1 << 13)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 8
-#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  (1 << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             6
-#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              BITFIELD(6, 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              (1 << 6)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT                                 4
+#define OMAP4430_VFSM_RA_ERR_CORE_MASK                                  (1 << 4)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT                                  12
+#define OMAP4430_VFSM_RA_ERR_IVA_MASK                                   (1 << 12)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT                                  20
+#define OMAP4430_VFSM_RA_ERR_MPU_MASK                                   (1 << 20)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT                                 3
+#define OMAP4430_VFSM_SA_ERR_CORE_MASK                                  (1 << 3)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT                                  11
+#define OMAP4430_VFSM_SA_ERR_IVA_MASK                                   (1 << 11)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT                                  19
+#define OMAP4430_VFSM_SA_ERR_MPU_MASK                                   (1 << 19)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT                            5
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK                             (1 << 5)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT                             13
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK                              (1 << 13)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT                             21
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK                              (1 << 21)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 0
-#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  (0xff << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  8
-#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   (0xff << 8)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  16
-#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   (0xff << 16)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_VPENABLE_SHIFT                                         0
-#define OMAP4430_VPENABLE_MASK                                          BITFIELD(0, 0)
+#define OMAP4430_VPENABLE_MASK                                          (1 << 0)
 
 /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
 #define OMAP4430_VPINIDLE_SHIFT                                         0
-#define OMAP4430_VPINIDLE_MASK                                          BITFIELD(0, 0)
+#define OMAP4430_VPINIDLE_MASK                                          (1 << 0)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 #define OMAP4430_VPVOLTAGE_SHIFT                                        0
-#define OMAP4430_VPVOLTAGE_MASK                                         BITFIELD(0, 7)
+#define OMAP4430_VPVOLTAGE_MASK                                         (0xff << 0)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                BITFIELD(20, 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                (1 << 20)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                BITFIELD(20, 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                (1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 BITFIELD(18, 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 (1 << 18)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 BITFIELD(18, 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 (1 << 18)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 BITFIELD(17, 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 (1 << 17)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 BITFIELD(17, 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 (1 << 17)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              BITFIELD(19, 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              (1 << 19)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              BITFIELD(19, 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              (1 << 19)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          BITFIELD(16, 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          (1 << 16)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          BITFIELD(16, 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          (1 << 16)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              BITFIELD(21, 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              (1 << 21)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              BITFIELD(21, 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              (1 << 21)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 BITFIELD(28, 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 (1 << 28)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 BITFIELD(28, 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 (1 << 28)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  BITFIELD(26, 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  (1 << 26)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  BITFIELD(26, 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  (1 << 26)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  BITFIELD(25, 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  (1 << 25)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  BITFIELD(25, 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  (1 << 25)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               BITFIELD(27, 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               (1 << 27)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               BITFIELD(27, 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               (1 << 27)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           BITFIELD(24, 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           (1 << 24)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           BITFIELD(24, 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           (1 << 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               BITFIELD(29, 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               (1 << 29)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               BITFIELD(29, 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               (1 << 29)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  BITFIELD(2, 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  (1 << 2)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  BITFIELD(2, 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  (1 << 2)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  BITFIELD(1, 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  (1 << 1)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  BITFIELD(1, 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  (1 << 1)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               BITFIELD(3, 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               (1 << 3)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               BITFIELD(3, 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               (1 << 3)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           BITFIELD(0, 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           (1 << 0)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           BITFIELD(0, 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           (1 << 0)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               BITFIELD(5, 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               (1 << 5)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               BITFIELD(5, 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               (1 << 5)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  8
-#define OMAP4430_VSETUPCNT_VALUE_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_VSETUPCNT_VALUE_MASK                                   (0xff << 8)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_VSTEPMAX_SHIFT                                         0
-#define OMAP4430_VSTEPMAX_MASK                                          BITFIELD(0, 7)
+#define OMAP4430_VSTEPMAX_MASK                                          (0xff << 0)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_VSTEPMIN_SHIFT                                         0
-#define OMAP4430_VSTEPMIN_MASK                                          BITFIELD(0, 7)
+#define OMAP4430_VSTEPMIN_MASK                                          (0xff << 0)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_WAKE_MODEM_SHIFT                                       0
-#define OMAP4430_WAKE_MODEM_MASK                                        BITFIELD(0, 0)
+#define OMAP4430_WAKE_MODEM_MASK                                        (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              (1 << 1)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               (1 << 2)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           6
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            (1 << 6)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           2
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            (1 << 2)
 
 /* Used by PM_L4PER_DMTIMER10_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         1
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER2_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              5
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               BITFIELD(5, 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               (1 << 5)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 4
-#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  (1 << 4)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                7
-#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 (1 << 7)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               6
-#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                (1 << 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              9
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               BITFIELD(9, 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               (1 << 9)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 8
-#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  (1 << 8)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                11
-#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 BITFIELD(11, 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 (1 << 11)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               10
-#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                BITFIELD(10, 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                (1 << 10)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         (1 << 1)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         (1 << 1)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             19
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              BITFIELD(19, 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              (1 << 19)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           13
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            BITFIELD(13, 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            (1 << 13)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              12
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               BITFIELD(12, 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               (1 << 12)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            14
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             BITFIELD(14, 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             (1 << 14)
 
 /* Used by PM_L4PER_HECC1_WKDEP */
 #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_HECC2_WKDEP */
 #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             (1 << 6)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_WKUP_KEYBOARD_WKDEP */
 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              (1 << 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
 #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
 #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             7
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              (1 << 7)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             (1 << 6)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               (1 << 0)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            2
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             (1 << 2)
 
 /* Used by PM_WKUP_RTC_WKDEP */
 #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  0
-#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   (1 << 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
 #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
 #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         (1 << 7)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        (1 << 6)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          (1 << 0)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        (1 << 2)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         (1 << 7)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        (1 << 6)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          (1 << 0)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        (1 << 2)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
 #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               (1 << 0)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
 #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ALWON_SR_MPU_WKDEP */
 #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                (1 << 0)
 
 /* Used by PM_WKUP_TIMER12_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               (1 << 0)
 
 /* Used by PM_WKUP_TIMER1_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_UART1_WKDEP */
 #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART1_WKDEP */
 #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART2_WKDEP */
 #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART2_WKDEP */
 #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              (1 << 1)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               (1 << 2)
 
 /* Used by PM_L4PER_UART4_WKDEP */
 #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART4_WKDEP */
 #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       1
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        (1 << 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          0
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           (1 << 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
 #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
 #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               (1 << 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
 #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
 #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
 #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
 #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_ABE_WDT3_WKDEP */
 #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         8
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          BITFIELD(8, 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          (1 << 8)
 
 /* Used by PM_L3INIT_XHPI_WKDEP */
 #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_CTRL_SHIFT                                       8
-#define OMAP4430_WUCLK_CTRL_MASK                                        BITFIELD(8, 8)
+#define OMAP4430_WUCLK_CTRL_MASK                                        (1 << 8)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_STATUS_SHIFT                                     9
-#define OMAP4430_WUCLK_STATUS_MASK                                      BITFIELD(9, 9)
+#define OMAP4430_WUCLK_STATUS_MASK                                      (1 << 9)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_X_MAJOR_SHIFT                                          8
+#define OMAP4430_X_MAJOR_MASK                                           (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_Y_MINOR_SHIFT                                          0
+#define OMAP4430_Y_MINOR_MASK                                           (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 588873b9303a..39d562169d18 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -1,312 +1,20 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_H
-
 /*
- * OMAP2/3 Power/Reset Management (PRM) register definitions
+ * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
  *
  * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2010 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
 
 #include "prcm-common.h"
 
-#define OMAP2420_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
-#define OMAP2430_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
-#define OMAP34XX_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
-#define OMAP44XX_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
-#define OMAP44XX_PRCM_MPU_REGADDR(module, reg)                          \
-                OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
-
-#include "prm44xx.h"
-
-/*
- * Architecture-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
- * IRQSTATUS and IRQENABLE bits.)
- *
- */
-
-#define OMAP2_PRCM_REVISION_OFFSET      0x0000
-#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
-#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
-#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
-#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
-#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
-#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
-#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
-#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
-#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
-#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
-#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP3_PRM_REVISION_OFFSET       0x0004
-#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
-#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
-#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
-
-#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
-#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
-#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
-
-
-#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
-#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
-#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
-#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
-#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
-#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
-#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
-#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
-#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
-#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
-#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
-#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
-#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
-#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
-#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
-#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
-#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
-#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
-#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
-#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
-#define OMAP3_PRM_RSTST_OFFSET  0x0058
-#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
-#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
-#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
-#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
-#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
-#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
-#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
-#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
-#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
-#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
-#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
-#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
-#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
-#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
-#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
-#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
-#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
-#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
-#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
-#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
-#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
-#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
-#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
-#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
-#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
-#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
-#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
-#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
-#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
-#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
-#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
-#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
-#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
-#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
-#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
-#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
-#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
-#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
-#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
-#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
-
-#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
-#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
-#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
-/*
- * Module specific PRM registers from PRM_BASE + domain offset
- *
- * Use prm_{read,write}_mod_reg() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
- * and IRQENABLE bits.)
- *
- */
-
-/* Registers appearing on both 24xx and 34xx */
-
-#define OMAP2_RM_RSTCTRL                                0x0050
-#define OMAP2_RM_RSTTIME                                0x0054
-#define OMAP2_RM_RSTST                                  0x0058
-#define OMAP2_PM_PWSTCTRL                               0x00e0
-#define OMAP2_PM_PWSTST                                 0x00e4
-
-#define PM_WKEN                                         0x00a0
-#define PM_WKEN1                                        PM_WKEN
-#define PM_WKST                                         0x00b0
-#define PM_WKST1                                        PM_WKST
-#define PM_WKDEP                                        0x00c8
-#define PM_EVGENCTRL                                    0x00d4
-#define PM_EVGENONTIM                                   0x00d8
-#define PM_EVGENOFFTIM                                  0x00dc
-
-/* Omap2 specific registers */
-#define OMAP24XX_PM_WKEN2                               0x00a4
-#define OMAP24XX_PM_WKST2                               0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
-
-/* Omap3 specific registers */
-#define OMAP3430ES2_PM_WKEN3                            0x00f0
-#define OMAP3430ES2_PM_WKST3                            0x00b8
-
-#define OMAP3430_PM_MPUGRPSEL                           0x00a4
-#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
-#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
-
-#define OMAP3430_PM_IVAGRPSEL                           0x00a8
-#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
-#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
-
-#define OMAP3430_PM_PREPWSTST                           0x00e8
-
-#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
-#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
-
-/* Omap4 specific registers */
-#define OMAP4_RM_RSTCTRL                                0x0000
-#define OMAP4_RM_RSTTIME                                0x0004
-#define OMAP4_RM_RSTST                                  0x0008
-#define OMAP4_PM_PWSTCTRL                               0x0000
-#define OMAP4_PM_PWSTST                                 0x0004
-
-
-#ifndef __ASSEMBLER__
-
-/* Power/reset management domain register get/set */
-extern u32 prm_read_mod_reg(s16 module, u16 idx);
-extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
-extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-
-/* Read-modify-write bits in a PRM register (by domain) */
-static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return prm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
-#endif
-
-/*
- * Bits common to specific registers
- *
- * The 3430 register and bit names are generally used,
- * since they tend to make more sense
- */
-
-/* PM_EVGENONTIM_MPU */
-/* Named PM_EVEGENONTIM_MPU on the 24XX */
-#define OMAP_ONTIMEVAL_SHIFT                            0
-#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
-
-/* PM_EVGENOFFTIM_MPU */
-/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
-#define OMAP_OFFTIMEVAL_SHIFT                           0
-#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
-
-/* PRM_CLKSETUP and PRCM_VOLTSETUP */
-/* Named PRCM_CLKSSETUP on the 24XX */
-#define OMAP_SETUP_TIME_SHIFT                           0
-#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
-
-/* PRM_CLKSRC_CTRL */
-/* Named PRCM_CLKSRC_CTRL on the 24XX */
-#define OMAP_SYSCLKDIV_SHIFT                            6
-#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
-#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
-#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
-#define OMAP_SYSCLKSEL_SHIFT                            0
-#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
-
-/* PM_EVGENCTRL_MPU */
-#define OMAP_OFFLOADMODE_SHIFT                          3
-#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
-#define OMAP_ONLOADMODE_SHIFT                           1
-#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
-#define OMAP_ENABLE_MASK                                (1 << 0)
-
-/* PRM_RSTTIME */
-/* Named RM_RSTTIME_WKUP on the 24xx */
-#define OMAP_RSTTIME2_SHIFT                             8
-#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
-#define OMAP_RSTTIME1_SHIFT                             0
-#define OMAP_RSTTIME1_MASK                              (0xff << 0)
-
-/* PRM_RSTCTRL */
-/* Named RM_RSTCTRL_WKUP on the 24xx */
-/* 2420 calls RST_DPLL3 'RST_DPLL' */
-#define OMAP_RST_DPLL3_MASK                             (1 << 2)
-#define OMAP_RST_GS_MASK                                (1 << 1)
-
-
-/*
- * Bits common to module-shared registers
- *
- * Not all registers of a particular type support all of these bits -
- * check TRM if you are unsure
- */
-
 /*
  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
  *
@@ -332,59 +40,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 #define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
 
 /*
- * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
- *       called 'COREWKUP_RST'
- *
- * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
- *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
- */
-#define OMAP_COREDOMAINWKUP_RST_MASK                    (1 << 3)
-
-/*
- * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
- *
- * 2430: RM_RSTST_MDM
- *
- * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- */
-#define OMAP_DOMAINWKUP_RST_MASK                        (1 << 2)
-
-/*
- * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
- *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
- *
- * 2430: RM_RSTST_MDM
- *
- * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- */
-#define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
-#define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
-
-/*
- * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
- *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
- *
- * 2430: PM_WKDEP_MDM
- *
- * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
- *       PM_WKDEP_PER
- */
-#define OMAP_EN_WKUP_SHIFT                              4
-#define OMAP_EN_WKUP_MASK                               (1 << 4)
-
-/*
- * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *       PM_PWSTCTRL_DSP
- *
- * 2430: PM_PWSTCTRL_MDM
- *
- * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
- *       PM_PWSTCTRL_NEON
- */
-#define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
-
-/*
  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
  *
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
new file mode 100644
index 000000000000..051213fbc346
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -0,0 +1,158 @@
+/*
+ * OMAP2/3 PRM module functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
+
+u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(prm_base + module + idx);
+}
+
+void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, prm_base + module + idx);
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_prm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(domain, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+
+
+/**
+ * omap2_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL if called while running on a non-OMAP2/3 chip.
+ */
+int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
+                                       (1 << shift));
+}
+
+/**
+ * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+        u32 mask;
+
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        mask = 1 << shift;
+        omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
+
+        return 0;
+}
+
+/**
+ * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @rst_shift: register bit shift corresponding to the reset line to deassert
+ * @st_shift: register bit shift for the status of the deasserted submodule
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
+{
+        u32 rst, st;
+        int c;
+
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        rst = 1 << rst_shift;
+        st = 1 << st_shift;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
+        /* de-assert the reset control line */
+        omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
+        /* wait the status to be set */
+        omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
+                                                  st),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
new file mode 100644
index 000000000000..a1fc62a39dbb
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -0,0 +1,429 @@
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+
+
+/*
+ * OMAP2-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ *
+ */
+
+#define OMAP2_PRCM_REVISION_OFFSET      0x0000
+#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
+#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
+#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
+#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
+#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
+#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
+#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
+#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
+#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
+#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
+#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
+#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
+
+/*
+ * OMAP3-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ */
+
+#define OMAP3_PRM_REVISION_OFFSET       0x0004
+#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
+#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
+#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
+#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
+#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3_PRM_RSTST_OFFSET  0x0058
+#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
+#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
+#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
+#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
+#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
+#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
+#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
+#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
+#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
+#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
+#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific PRM register offsets from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ */
+
+/* Register offsets appearing on both OMAP2 and OMAP3 */
+
+#define OMAP2_RM_RSTCTRL                                0x0050
+#define OMAP2_RM_RSTTIME                                0x0054
+#define OMAP2_RM_RSTST                                  0x0058
+#define OMAP2_PM_PWSTCTRL                               0x00e0
+#define OMAP2_PM_PWSTST                                 0x00e4
+
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+
+/* OMAP2xxx specific register offsets */
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+/* OMAP3 specific register offsets */
+#define OMAP3430ES2_PM_WKEN3                            0x00f0
+#define OMAP3430ES2_PM_WKST3                            0x00b8
+
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
+
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
+
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+
+
+#ifndef __ASSEMBLER__
+/*
+ * Stub omap2xxx/omap3xxx functions so that common files
+ * continue to build when custom builds are used
+ */
+#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) ||       \
+                                        defined(CONFIG_ARCH_OMAP3))
+static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+}
+static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
+                s16 module, s16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
+                                                u8 st_shift)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+                "not suppose to be used on omap4\n");
+        return 0;
+}
+#else
+/* Power/reset management domain register get/set */
+extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
+extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+
+/* These omap2_ PRM functions apply to both OMAP2 and 3 */
+extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+
+#endif  /* CONFIG_ARCH_OMAP4 */
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT                            0
+#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT                           0
+#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT                           0
+#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT                            6
+#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
+#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT                            0
+#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT                          3
+#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT                           1
+#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
+#define OMAP_ENABLE_MASK                                (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT                             8
+#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT                             0
+#define OMAP_RSTTIME1_MASK                              (0xff << 0)
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3_MASK                             (1 << 2)
+#define OMAP_RST_GS_MASK                                (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *       called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST_MASK                    (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST_MASK                        (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
+#define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *       PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP_SHIFT                              4
+#define OMAP_EN_WKUP_MASK                               (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
+
+
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+
+
+#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
new file mode 100644
index 000000000000..a2a04bfa9628
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -0,0 +1,195 @@
+/*
+ * OMAP4 PRM module functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET                4
+
+/* PRM low-level functions */
+
+/* Read a register in a CM/PRM instance in the PRM module */
+u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
+}
+
+/* Write into a register in a CM/PRM instance in the PRM module */
+void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+{
+        u32 v;
+
+        v = omap4_prm_read_inst_reg(inst, reg);
+        v &= ~mask;
+        v |= bits;
+        omap4_prm_write_inst_reg(v, inst, reg);
+
+        return v;
+}
+
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+/* XXX deprecated */
+u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+/* XXX deprecated */
+u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= ~mask;
+        v |= bits;
+        __raw_writel(v, reg);
+
+        return v;
+}
+
+u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+{
+        return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
+}
+
+u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+{
+        return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
+}
+
+/**
+ * omap4_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
+{
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
+}
+
+/**
+ * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+{
+        u32 mask;
+
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        mask = 1 << shift;
+        omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
+
+        return 0;
+}
+
+/**
+ * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+{
+        u32 mask;
+        void __iomem *rstst_reg;
+        int c;
+
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
+
+        mask = 1 << shift;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
+        /* de-assert the reset control line */
+        omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
+        /* wait the status to be set */
+        omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
+void omap4_prm_global_warm_sw_reset(void)
+{
+        u32 v;
+
+        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_RM_RSTCTRL);
+        v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
+        omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_RM_RSTCTRL);
+
+        /* OCP barrier */
+        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_RM_RSTCTRL);
+}
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index fe8ef26431e5..67a0d3feb3f6 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -17,734 +17,762 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
+#include "prcm-common.h"
+#include "prm.h"
+
+#define OMAP4430_PRM_BASE               0x4a306000
+
+#define OMAP44XX_PRM_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define OMAP4430_PRM_OCP_SOCKET_INST    0x0000
+#define OMAP4430_PRM_CKGEN_INST         0x0100
+#define OMAP4430_PRM_MPU_INST           0x0300
+#define OMAP4430_PRM_TESLA_INST         0x0400
+#define OMAP4430_PRM_ABE_INST           0x0500
+#define OMAP4430_PRM_ALWAYS_ON_INST     0x0600
+#define OMAP4430_PRM_CORE_INST          0x0700
+#define OMAP4430_PRM_IVAHD_INST         0x0f00
+#define OMAP4430_PRM_CAM_INST           0x1000
+#define OMAP4430_PRM_DSS_INST           0x1100
+#define OMAP4430_PRM_GFX_INST           0x1200
+#define OMAP4430_PRM_L3INIT_INST                0x1300
+#define OMAP4430_PRM_L4PER_INST         0x1400
+#define OMAP4430_PRM_CEFUSE_INST                0x1600
+#define OMAP4430_PRM_WKUP_INST          0x1700
+#define OMAP4430_PRM_WKUP_CM_INST       0x1800
+#define OMAP4430_PRM_EMU_INST           0x1900
+#define OMAP4430_PRM_EMU_CM_INST                0x1a00
+#define OMAP4430_PRM_DEVICE_INST                0x1b00
+#define OMAP4430_PRM_INSTR_INST         0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP4430_PRM_MPU_MPU_CDOFFS             0x0000
+#define OMAP4430_PRM_TESLA_TESLA_CDOFFS         0x0000
+#define OMAP4430_PRM_ABE_ABE_CDOFFS             0x0000
+#define OMAP4430_PRM_CORE_CORE_CDOFFS           0x0000
+#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS         0x0000
+#define OMAP4430_PRM_CAM_CAM_CDOFFS             0x0000
+#define OMAP4430_PRM_DSS_DSS_CDOFFS             0x0000
+#define OMAP4430_PRM_GFX_GFX_CDOFFS             0x0000
+#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS       0x0000
+#define OMAP4430_PRM_L4PER_L4PER_CDOFFS         0x0000
+#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS       0x0000
+#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS        0x0000
+#define OMAP4430_PRM_EMU_EMU_CDOFFS             0x0000
+#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS          0x0000
+
+/* OMAP4 specific register offsets */
+#define OMAP4_RM_RSTCTRL                                0x0000
+#define OMAP4_RM_RSTTIME                                0x0004
+#define OMAP4_RM_RSTST                                  0x0008
+#define OMAP4_PM_PWSTCTRL                               0x0000
+#define OMAP4_PM_PWSTST                                 0x0004
+
 
 /* PRM */
 
 /* PRM.OCP_SOCKET_PRM register offsets */
 #define OMAP4_REVISION_PRM_OFFSET                       0x0000
-#define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET                  0x0010
-#define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
+#define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET                0x0014
-#define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
+#define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET                  0x0018
-#define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
+#define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
 #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET                0x001c
-#define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
+#define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
 #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET               0x0020
-#define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
+#define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
 #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET               0x0028
-#define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
+#define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
 #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET                0x0030
-#define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
+#define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
 #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET                0x0038
-#define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
-#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
+#define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
+#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_PRM_PROFILING_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
 
 /* PRM.CKGEN_PRM register offsets */
 #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET              0x0000
-#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET             0x0004
-#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
+#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
 #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET                  0x0008
-#define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
 #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET              0x000c
-#define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
+#define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
 #define OMAP4_CM_SYS_CLKSEL_OFFSET                      0x0010
-#define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
+#define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
 
 /* PRM.MPU_PRM register offsets */
 #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
+#define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
 #define OMAP4_PM_MPU_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
+#define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
 #define OMAP4_RM_MPU_RSTST_OFFSET                       0x0014
-#define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
+#define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
+#define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
 
 /* PRM.TESLA_PRM register offsets */
 #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET                 0x0000
-#define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
+#define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
 #define OMAP4_PM_TESLA_PWRSTST_OFFSET                   0x0004
-#define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
+#define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
 #define OMAP4_RM_TESLA_RSTCTRL_OFFSET                   0x0010
-#define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
+#define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
 #define OMAP4_RM_TESLA_RSTST_OFFSET                     0x0014
-#define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
+#define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
 #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
+#define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
 
 /* PRM.ABE_PRM register offsets */
 #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
+#define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
 #define OMAP4_PM_ABE_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
+#define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
 #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET                0x002c
-#define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
+#define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
 #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET                   0x0030
-#define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
+#define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
 #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET                 0x0034
-#define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
+#define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
 #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET                  0x0038
-#define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
+#define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
 #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET                0x003c
-#define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
+#define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
 #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET                 0x0040
-#define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
+#define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
 #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET               0x0044
-#define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
+#define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
 #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET                0x0048
-#define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
+#define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
 #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET              0x004c
-#define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
+#define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
 #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET                0x0050
-#define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
+#define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
 #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET              0x0054
-#define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
+#define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
 #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET                0x0058
-#define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
+#define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
 #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET              0x005c
-#define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
+#define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
 #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET               0x0060
-#define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
+#define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
 #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET             0x0064
-#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
+#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
 #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET                0x0068
-#define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
+#define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
 #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET              0x006c
-#define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
+#define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
 #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET                0x0070
-#define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
+#define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
 #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET              0x0074
-#define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
+#define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
 #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET                0x0078
-#define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
+#define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
 #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET              0x007c
-#define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
+#define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
 #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET                0x0080
-#define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
+#define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
 #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET              0x0084
-#define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
+#define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
 #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET                  0x0088
-#define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
+#define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
 #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET                0x008c
-#define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
+#define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
 
 /* PRM.ALWAYS_ON_PRM register offsets */
 #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET           0x0024
-#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
+#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
 #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET              0x0028
-#define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
 #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET            0x002c
-#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
+#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
 #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET              0x0030
-#define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
 #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET            0x0034
-#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
+#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
 #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET             0x0038
-#define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
 #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET           0x003c
-#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
+#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
 
 /* PRM.CORE_PRM register offsets */
 #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
+#define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
 #define OMAP4_PM_CORE_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
+#define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
 #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET               0x0024
-#define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
+#define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
 #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET               0x0124
-#define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
+#define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
 #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET               0x012c
-#define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
+#define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
 #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET           0x0134
-#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
+#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
 #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET                  0x0210
-#define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
+#define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
 #define OMAP4_RM_DUCATI_RSTST_OFFSET                    0x0214
-#define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
+#define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
 #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET           0x0224
-#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
+#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
 #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET               0x0324
-#define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
+#define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
 #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET               0x0424
-#define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
+#define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
 #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET           0x042c
-#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
+#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
 #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET            0x0434
-#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
+#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
 #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET            0x043c
-#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
+#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
 #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET               0x0444
-#define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
+#define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
 #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET           0x0454
-#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
+#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
 #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET           0x045c
-#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
+#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
 #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET             0x0464
-#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
+#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
 #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET               0x0524
-#define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
-#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET           0x052c
-#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
+#define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
+#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET          0x052c
+#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
 #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET            0x0534
-#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
+#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
 #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET            0x0624
-#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
+#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
 #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET            0x062c
-#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
+#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
 #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET           0x0634
-#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
+#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
 #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET           0x063c
-#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
+#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
 #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET            0x0724
-#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
+#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
 #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET        0x072c
-#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
+#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
 #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET         0x0744
-#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
+#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
 
 /* PRM.IVAHD_PRM register offsets */
 #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET                 0x0000
-#define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
+#define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
 #define OMAP4_PM_IVAHD_PWRSTST_OFFSET                   0x0004
-#define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
+#define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
 #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET                   0x0010
-#define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
+#define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
 #define OMAP4_RM_IVAHD_RSTST_OFFSET                     0x0014
-#define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
+#define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
 #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
+#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
 #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET               0x002c
-#define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
+#define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
 
 /* PRM.CAM_PRM register offsets */
 #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
+#define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
 #define OMAP4_PM_CAM_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
+#define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
 #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
+#define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
 #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET                0x002c
-#define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
+#define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
 
 /* PRM.DSS_PRM register offsets */
 #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
+#define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
 #define OMAP4_PM_DSS_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
+#define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
 #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET                   0x0020
-#define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
+#define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
 #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
+#define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
 #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET               0x002c
-#define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
+#define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
 
 /* PRM.GFX_PRM register offsets */
 #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
+#define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
 #define OMAP4_PM_GFX_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
+#define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
 #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
+#define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
 
 /* PRM.L3INIT_PRM register offsets */
 #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET                0x0000
-#define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
+#define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
 #define OMAP4_PM_L3INIT_PWRSTST_OFFSET                  0x0004
-#define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
+#define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
 #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET               0x0028
-#define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
+#define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
 #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET             0x002c
-#define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
+#define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
 #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET               0x0030
-#define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
+#define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
 #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET             0x0034
-#define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
+#define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
 #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET                0x0038
-#define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
+#define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
 #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET              0x003c
-#define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
+#define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
 #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET            0x0040
-#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
+#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
 #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET          0x0044
-#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
+#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
 #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET           0x0058
-#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
+#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
 #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET         0x005c
-#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
+#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
 #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET            0x0060
-#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
+#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
 #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET          0x0064
-#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
+#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
 #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET            0x0068
-#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
+#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
 #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET          0x006c
-#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
+#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
 #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET            0x007c
-#define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
+#define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
 #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET             0x0084
-#define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
+#define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
 #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET               0x0088
-#define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
+#define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
 #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET             0x008c
-#define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
+#define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
 #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET            0x0094
-#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
+#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
 #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET             0x0098
-#define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
+#define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
 #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET           0x009c
-#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
+#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
 #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET            0x00ac
-#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
+#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
 #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET               0x00c0
-#define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
+#define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
 #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET             0x00c4
-#define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
+#define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
 #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET               0x00c8
-#define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
+#define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
 #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET             0x00cc
-#define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
+#define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
 #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET        0x00d0
-#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
+#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
 #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET      0x00d4
-#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
+#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
 #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET    0x00e4
-#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
+#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
 
 /* PRM.L4PER_PRM register offsets */
 #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET                 0x0000
-#define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
+#define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
 #define OMAP4_PM_L4PER_PWRSTST_OFFSET                   0x0004
-#define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
+#define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
 #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET               0x0024
-#define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
+#define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
 #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET           0x0028
-#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
+#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
 #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET         0x002c
-#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
+#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
 #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET           0x0030
-#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
+#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
 #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET         0x0034
-#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
+#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
 #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET            0x0038
-#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
+#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
 #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET          0x003c
-#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
+#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
 #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET            0x0040
-#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
+#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
 #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET          0x0044
-#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
+#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
 #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET            0x0048
-#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
+#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
 #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET          0x004c
-#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
+#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
 #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET            0x0050
-#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
+#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
 #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET          0x0054
-#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
+#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
 #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET               0x005c
-#define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
+#define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
 #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET               0x0060
-#define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
+#define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
 #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET             0x0064
-#define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
+#define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
 #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET               0x0068
-#define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
+#define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
 #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET             0x006c
-#define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
+#define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
 #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET               0x0070
-#define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
+#define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
 #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET             0x0074
-#define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
+#define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
 #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET               0x0078
-#define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
+#define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
 #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET             0x007c
-#define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
+#define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
 #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET               0x0080
-#define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
+#define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
 #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET             0x0084
-#define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
+#define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
 #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET             0x008c
-#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
+#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
 #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET               0x0090
-#define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
+#define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
 #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET             0x0094
-#define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
+#define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
 #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET               0x0098
-#define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
+#define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
 #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET             0x009c
-#define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
+#define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
 #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET                0x00a0
-#define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
+#define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
 #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET              0x00a4
-#define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
+#define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
 #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET                0x00a8
-#define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
+#define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
 #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET              0x00ac
-#define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
+#define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
 #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET                0x00b0
-#define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
+#define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
 #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET              0x00b4
-#define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
+#define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
 #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET                0x00b8
-#define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
+#define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
 #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET              0x00bc
-#define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
+#define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
 #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET            0x00c0
-#define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
+#define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
 #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET              0x00d0
-#define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
+#define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
 #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET            0x00d4
-#define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
+#define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
 #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET              0x00d8
-#define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
+#define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
 #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET            0x00dc
-#define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
+#define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
 #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET              0x00e0
-#define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
+#define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
 #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET            0x00e4
-#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
+#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
 #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET             0x00ec
-#define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
+#define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
 #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET              0x00f0
-#define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
+#define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
 #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET            0x00f4
-#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
+#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
 #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET              0x00f8
-#define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
+#define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
 #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET            0x00fc
-#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
+#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
 #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET              0x0100
-#define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
+#define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
 #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET            0x0104
-#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
+#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
 #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET              0x0108
-#define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
+#define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
 #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET            0x010c
-#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
+#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
 #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET              0x0120
-#define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
+#define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
 #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET            0x0124
-#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
+#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
 #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET              0x0128
-#define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
+#define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
 #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET            0x012c
-#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
+#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
 #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET           0x0134
-#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
+#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
 #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET            0x0138
-#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
+#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
 #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET          0x013c
-#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
+#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
 #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET               0x0140
-#define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
+#define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
 #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET             0x0144
-#define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
+#define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
 #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET               0x0148
-#define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
+#define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
 #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET             0x014c
-#define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
+#define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
 #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET               0x0150
-#define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
+#define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
 #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET             0x0154
-#define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
+#define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
 #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET               0x0158
-#define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
+#define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
 #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET             0x015c
-#define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
+#define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
 #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET              0x0160
-#define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
+#define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
 #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET            0x0164
-#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
+#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
 #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET                0x0168
-#define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
+#define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
 #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET              0x016c
-#define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
+#define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
 #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET              0x01a4
-#define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
+#define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
 #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET              0x01ac
-#define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
+#define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
 #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET           0x01b4
-#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
+#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
 #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET          0x01bc
-#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
+#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
 #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET               0x01c4
-#define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
+#define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
 #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET          0x01cc
-#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
+#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
 #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET         0x01dc
-#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
+#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
 
 /* PRM.CEFUSE_PRM register offsets */
 #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET                0x0000
-#define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
+#define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
 #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET                  0x0004
-#define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
+#define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
 #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET           0x0024
-#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
+#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
 
 /* PRM.WKUP_PRM register offsets */
 #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
+#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
 #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET               0x002c
-#define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
+#define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
 #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET                 0x0030
-#define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
+#define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
 #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET               0x0034
-#define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
+#define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
 #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET                0x0038
-#define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
+#define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
 #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET              0x003c
-#define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
+#define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
 #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET               0x0040
-#define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
+#define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
 #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET             0x0044
-#define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
+#define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
 #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET              0x0048
-#define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
+#define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
 #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET            0x004c
-#define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
+#define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
 #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET          0x0054
-#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
+#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
 #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET                 0x0058
-#define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
+#define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
 #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET               0x005c
-#define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
+#define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
 #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET             0x0064
-#define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
+#define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
 #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET             0x0078
-#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
+#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
 #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET           0x007c
-#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
+#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
 #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET                  0x0080
-#define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
+#define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
 #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET                0x0084
-#define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
+#define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
 
 /* PRM.WKUP_CM register offsets */
 #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET                  0x0000
-#define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
+#define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
 #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
+#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
 #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
+#define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
 #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET               0x0030
-#define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
+#define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
 #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET              0x0038
-#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
+#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
 #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET             0x0040
-#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
+#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
 #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET            0x0048
-#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
+#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
 #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET          0x0050
-#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
+#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
 #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET               0x0058
-#define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
+#define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
 #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET             0x0060
-#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
+#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
 #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET           0x0078
-#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
+#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
 #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET                0x0080
-#define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
+#define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
 #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET            0x0088
-#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
+#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
 
 /* PRM.EMU_PRM register offsets */
 #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
+#define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
 #define OMAP4_PM_EMU_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
+#define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
 #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
+#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
 
 /* PRM.EMU_CM register offsets */
 #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
+#define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
 #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
+#define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
 #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
+#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
 
 /* PRM.DEVICE_PRM register offsets */
 #define OMAP4_PRM_RSTCTRL_OFFSET                        0x0000
-#define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
+#define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
 #define OMAP4_PRM_RSTST_OFFSET                          0x0004
-#define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
+#define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
 #define OMAP4_PRM_RSTTIME_OFFSET                        0x0008
-#define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
+#define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
 #define OMAP4_PRM_CLKREQCTRL_OFFSET                     0x000c
-#define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
+#define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
 #define OMAP4_PRM_VOLTCTRL_OFFSET                       0x0010
-#define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
+#define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
 #define OMAP4_PRM_PWRREQCTRL_OFFSET                     0x0014
-#define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
+#define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
 #define OMAP4_PRM_PSCON_COUNT_OFFSET                    0x0018
-#define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
+#define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
 #define OMAP4_PRM_IO_COUNT_OFFSET                       0x001c
-#define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
+#define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
 #define OMAP4_PRM_IO_PMCTRL_OFFSET                      0x0020
-#define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
+#define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
 #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET            0x0024
-#define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
+#define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET             0x0028
-#define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
+#define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET              0x002c
-#define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
+#define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET              0x0030
-#define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
+#define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET       0x0034
-#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
+#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET        0x0038
-#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
+#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET        0x003c
-#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
+#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET                 0x0040
-#define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
+#define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET                 0x0044
-#define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
+#define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET               0x0048
-#define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
+#define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET                0x004c
-#define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
+#define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET               0x0050
-#define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
+#define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET               0x0054
-#define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
+#define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET                  0x0058
-#define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
+#define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET                  0x005c
-#define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
+#define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET                0x0060
-#define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
+#define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET                 0x0064
-#define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
+#define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET                0x0068
-#define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
+#define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET                0x006c
-#define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
+#define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET                  0x0070
-#define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
+#define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET                  0x0074
-#define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
+#define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET                0x0078
-#define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
+#define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET                 0x007c
-#define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
+#define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET                0x0080
-#define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
+#define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET                0x0084
-#define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
+#define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
 #define OMAP4_PRM_VC_SMPS_SA_OFFSET                     0x0088
-#define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
+#define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET             0x008c
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET             0x0090
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET          0x0094
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET           0x0098
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET           0x009c
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET                  0x00a0
-#define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
+#define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET                 0x00a4
-#define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
-#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET                0x00a8
-#define OMAP4430_PRM_VC_CFG_I2C_MODE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
+#define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
+#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET               0x00a8
+#define OMAP4430_PRM_VC_CFG_I2C_INSTE                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET                 0x00ac
-#define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
+#define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
 #define OMAP4_PRM_SRAM_COUNT_OFFSET                     0x00b0
-#define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
+#define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
 #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET                0x00b4
-#define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
+#define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
 #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET            0x00b8
-#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
+#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
 #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET             0x00bc
-#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
+#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
 #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET             0x00c0
-#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
+#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
 #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET              0x00c4
-#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
+#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
 #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET             0x00c8
-#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
+#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
 #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET              0x00cc
-#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
+#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
 #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET              0x00d0
-#define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
+#define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
 #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET               0x00d4
-#define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
+#define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
 #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET              0x00d8
-#define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
+#define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
 #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET               0x00dc
-#define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
-#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET               0x00e0
-#define OMAP4430_PRM_LDO_BANDGAP_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
+#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET              0x00e0
+#define OMAP4430_PRM_LDO_BANDGAP_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
 #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET                0x00e4
-#define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
+#define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
 #define OMAP4_PRM_PHASE1_CNDP_OFFSET                    0x00e8
-#define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
+#define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
 #define OMAP4_PRM_PHASE2A_CNDP_OFFSET                   0x00ec
-#define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
+#define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
 #define OMAP4_PRM_PHASE2B_CNDP_OFFSET                   0x00f0
-#define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
-#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET                  0x00f4
-#define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
+#define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
+#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET                 0x00f4
+#define OMAP4430_PRM_INSTEM_IF_CTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
+#define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
+#define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
-/*
- * PRCM_MPU
- *
- * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
- * point of view the PRCM_MPU is a single entity. It shares the same
- * programming model as the global PRCM and thus can be assimilate as two new
- * MOD inside the PRCM
- */
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
+extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
+
+extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
+extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+
+extern void omap4_prm_global_warm_sw_reset(void);
+
+# endif
 
-/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
-#define OMAP4_REVISION_PRCM_OFFSET                      0x0000
-#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
-
-/* PRCM_MPU.DEVICE_PRM register offsets */
-#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
-#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
-
-/* PRCM_MPU.CPU0 register offsets */
-#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
-#define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
-#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
-#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
-#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
-#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
-#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
-
-/* PRCM_MPU.CPU1 register offsets */
-#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
-#define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
-#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
-#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
-#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
-#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
-#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
 #endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
new file mode 100644
index 000000000000..a30324297278
--- /dev/null
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -0,0 +1,66 @@
+/*
+ * OMAP4 PRM instance functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "prm44xx.h"
+#include "prminst44xx.h"
+#include "prm-regbits-44xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu44xx.h"
+
+static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
+        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
+        [OMAP4430_CM1_PARTITION]                = 0,
+        [OMAP4430_CM2_PARTITION]                = 0,
+        [OMAP4430_SCRM_PARTITION]               = 0,
+        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
+};
+
+/* Read a register in a PRM instance */
+u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_prm_bases[part]);
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
+                                               idx));
+}
+
+/* Write into a register in a PRM instance */
+void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_prm_bases[part]);
+        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+                                   s16 idx)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(part, inst, idx);
+        v &= ~mask;
+        v |= bits;
+        omap4_prminst_write_inst_reg(v, part, inst, idx);
+
+        return v;
+}
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
new file mode 100644
index 000000000000..02dd66ddda8b
--- /dev/null
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -0,0 +1,25 @@
+/*
+ * OMAP4 Power/Reset Management (PRM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+
+/*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+ */
+extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+                                           s16 inst, s16 idx);
+
+extern void omap4_prm_global_warm_sw_reset(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
new file mode 100644
index 000000000000..701bf2d32949
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm44xx.h
@@ -0,0 +1,175 @@
+/*
+ * OMAP44xx SCRM registers and bitfields
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+
+#define OMAP4_SCRM_BASE                         0x4a30a000
+
+#define OMAP44XX_SCRM_REGADDR(reg)      \
+                OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
+
+/* Registers offset */
+#define OMAP4_SCRM_REVISION_SCRM_OFFSET         0x0000
+#define OMAP4_SCRM_REVISION_SCRM                OMAP44XX_SCRM_REGADDR(0x0000)
+#define OMAP4_SCRM_CLKSETUPTIME_OFFSET          0x0100
+#define OMAP4_SCRM_CLKSETUPTIME                 OMAP44XX_SCRM_REGADDR(0x0100)
+#define OMAP4_SCRM_PMICSETUPTIME_OFFSET         0x0104
+#define OMAP4_SCRM_PMICSETUPTIME                OMAP44XX_SCRM_REGADDR(0x0104)
+#define OMAP4_SCRM_ALTCLKSRC_OFFSET             0x0110
+#define OMAP4_SCRM_ALTCLKSRC                    OMAP44XX_SCRM_REGADDR(0x0110)
+#define OMAP4_SCRM_MODEMCLKM_OFFSET             0x0118
+#define OMAP4_SCRM_MODEMCLKM                    OMAP44XX_SCRM_REGADDR(0x0118)
+#define OMAP4_SCRM_D2DCLKM_OFFSET               0x011c
+#define OMAP4_SCRM_D2DCLKM                      OMAP44XX_SCRM_REGADDR(0x011c)
+#define OMAP4_SCRM_EXTCLKREQ_OFFSET             0x0200
+#define OMAP4_SCRM_EXTCLKREQ                    OMAP44XX_SCRM_REGADDR(0x0200)
+#define OMAP4_SCRM_ACCCLKREQ_OFFSET             0x0204
+#define OMAP4_SCRM_ACCCLKREQ                    OMAP44XX_SCRM_REGADDR(0x0204)
+#define OMAP4_SCRM_PWRREQ_OFFSET                0x0208
+#define OMAP4_SCRM_PWRREQ                       OMAP44XX_SCRM_REGADDR(0x0208)
+#define OMAP4_SCRM_AUXCLKREQ0_OFFSET            0x0210
+#define OMAP4_SCRM_AUXCLKREQ0                   OMAP44XX_SCRM_REGADDR(0x0210)
+#define OMAP4_SCRM_AUXCLKREQ1_OFFSET            0x0214
+#define OMAP4_SCRM_AUXCLKREQ1                   OMAP44XX_SCRM_REGADDR(0x0214)
+#define OMAP4_SCRM_AUXCLKREQ2_OFFSET            0x0218
+#define OMAP4_SCRM_AUXCLKREQ2                   OMAP44XX_SCRM_REGADDR(0x0218)
+#define OMAP4_SCRM_AUXCLKREQ3_OFFSET            0x021c
+#define OMAP4_SCRM_AUXCLKREQ3                   OMAP44XX_SCRM_REGADDR(0x021c)
+#define OMAP4_SCRM_AUXCLKREQ4_OFFSET            0x0220
+#define OMAP4_SCRM_AUXCLKREQ4                   OMAP44XX_SCRM_REGADDR(0x0220)
+#define OMAP4_SCRM_AUXCLKREQ5_OFFSET            0x0224
+#define OMAP4_SCRM_AUXCLKREQ5                   OMAP44XX_SCRM_REGADDR(0x0224)
+#define OMAP4_SCRM_D2DCLKREQ_OFFSET             0x0234
+#define OMAP4_SCRM_D2DCLKREQ                    OMAP44XX_SCRM_REGADDR(0x0234)
+#define OMAP4_SCRM_AUXCLK0_OFFSET               0x0310
+#define OMAP4_SCRM_AUXCLK0                      OMAP44XX_SCRM_REGADDR(0x0310)
+#define OMAP4_SCRM_AUXCLK1_OFFSET               0x0314
+#define OMAP4_SCRM_AUXCLK1                      OMAP44XX_SCRM_REGADDR(0x0314)
+#define OMAP4_SCRM_AUXCLK2_OFFSET               0x0318
+#define OMAP4_SCRM_AUXCLK2                      OMAP44XX_SCRM_REGADDR(0x0318)
+#define OMAP4_SCRM_AUXCLK3_OFFSET               0x031c
+#define OMAP4_SCRM_AUXCLK3                      OMAP44XX_SCRM_REGADDR(0x031c)
+#define OMAP4_SCRM_AUXCLK4_OFFSET               0x0320
+#define OMAP4_SCRM_AUXCLK4                      OMAP44XX_SCRM_REGADDR(0x0320)
+#define OMAP4_SCRM_AUXCLK5_OFFSET               0x0324
+#define OMAP4_SCRM_AUXCLK5                      OMAP44XX_SCRM_REGADDR(0x0324)
+#define OMAP4_SCRM_RSTTIME_OFFSET               0x0400
+#define OMAP4_SCRM_RSTTIME                      OMAP44XX_SCRM_REGADDR(0x0400)
+#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET          0x0418
+#define OMAP4_SCRM_MODEMRSTCTRL                 OMAP44XX_SCRM_REGADDR(0x0418)
+#define OMAP4_SCRM_D2DRSTCTRL_OFFSET            0x041c
+#define OMAP4_SCRM_D2DRSTCTRL                   OMAP44XX_SCRM_REGADDR(0x041c)
+#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET       0x0420
+#define OMAP4_SCRM_EXTPWRONRSTCTRL              OMAP44XX_SCRM_REGADDR(0x0420)
+#define OMAP4_SCRM_EXTWARMRSTST_OFFSET          0x0510
+#define OMAP4_SCRM_EXTWARMRSTST                 OMAP44XX_SCRM_REGADDR(0x0510)
+#define OMAP4_SCRM_APEWARMRSTST_OFFSET          0x0514
+#define OMAP4_SCRM_APEWARMRSTST                 OMAP44XX_SCRM_REGADDR(0x0514)
+#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET        0x0518
+#define OMAP4_SCRM_MODEMWARMRSTST               OMAP44XX_SCRM_REGADDR(0x0518)
+#define OMAP4_SCRM_D2DWARMRSTST_OFFSET          0x051c
+#define OMAP4_SCRM_D2DWARMRSTST                 OMAP44XX_SCRM_REGADDR(0x051c)
+
+/* Registers shifts and masks */
+
+/* REVISION_SCRM */
+#define OMAP4_REV_SHIFT                         0
+#define OMAP4_REV_MASK                          (0xff << 0)
+
+/* CLKSETUPTIME */
+#define OMAP4_DOWNTIME_SHIFT                    16
+#define OMAP4_DOWNTIME_MASK                     (0x3f << 16)
+#define OMAP4_SETUPTIME_SHIFT                   0
+#define OMAP4_SETUPTIME_MASK                    (0xfff << 0)
+
+/* PMICSETUPTIME */
+#define OMAP4_WAKEUPTIME_SHIFT                  16
+#define OMAP4_WAKEUPTIME_MASK                   (0x3f << 16)
+#define OMAP4_SLEEPTIME_SHIFT                   0
+#define OMAP4_SLEEPTIME_MASK                    (0x3f << 0)
+
+/* ALTCLKSRC */
+#define OMAP4_ENABLE_EXT_SHIFT                  3
+#define OMAP4_ENABLE_EXT_MASK                   (1 << 3)
+#define OMAP4_ENABLE_INT_SHIFT                  2
+#define OMAP4_ENABLE_INT_MASK                   (1 << 2)
+#define OMAP4_ALTCLKSRC_MODE_SHIFT              0
+#define OMAP4_ALTCLKSRC_MODE_MASK               (0x3 << 0)
+
+/* MODEMCLKM */
+#define OMAP4_CLK_32KHZ_SHIFT                   0
+#define OMAP4_CLK_32KHZ_MASK                    (1 << 0)
+
+/* D2DCLKM */
+#define OMAP4_SYSCLK_SHIFT                      1
+#define OMAP4_SYSCLK_MASK                       (1 << 1)
+
+/* EXTCLKREQ */
+#define OMAP4_POLARITY_SHIFT                    0
+#define OMAP4_POLARITY_MASK                     (1 << 0)
+
+/* AUXCLKREQ0 */
+#define OMAP4_MAPPING_SHIFT                     2
+#define OMAP4_MAPPING_MASK                      (0x7 << 2)
+#define OMAP4_ACCURACY_SHIFT                    1
+#define OMAP4_ACCURACY_MASK                     (1 << 1)
+
+/* AUXCLK0 */
+#define OMAP4_CLKDIV_SHIFT                      16
+#define OMAP4_CLKDIV_MASK                       (0xf << 16)
+#define OMAP4_DISABLECLK_SHIFT                  9
+#define OMAP4_DISABLECLK_MASK                   (1 << 9)
+#define OMAP4_ENABLE_SHIFT                      8
+#define OMAP4_ENABLE_MASK                       (1 << 8)
+#define OMAP4_SRCSELECT_SHIFT                   1
+#define OMAP4_SRCSELECT_MASK                    (0x3 << 1)
+
+/* RSTTIME */
+#define OMAP4_RSTTIME_SHIFT                     0
+#define OMAP4_RSTTIME_MASK                      (0xf << 0)
+
+/* MODEMRSTCTRL */
+#define OMAP4_WARMRST_SHIFT                     1
+#define OMAP4_WARMRST_MASK                      (1 << 1)
+#define OMAP4_COLDRST_SHIFT                     0
+#define OMAP4_COLDRST_MASK                      (1 << 0)
+
+/* EXTPWRONRSTCTRL */
+#define OMAP4_PWRONRST_SHIFT                    1
+#define OMAP4_PWRONRST_MASK                     (1 << 1)
+#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT      0
+#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK       (1 << 0)
+
+/* EXTWARMRSTST */
+#define OMAP4_EXTWARMRSTST_SHIFT                0
+#define OMAP4_EXTWARMRSTST_MASK                 (1 << 0)
+
+/* APEWARMRSTST */
+#define OMAP4_APEWARMRSTST_SHIFT                1
+#define OMAP4_APEWARMRSTST_MASK                 (1 << 1)
+
+/* MODEMWARMRSTST */
+#define OMAP4_MODEMWARMRSTST_SHIFT              2
+#define OMAP4_MODEMWARMRSTST_MASK               (1 << 2)
+
+/* D2DWARMRSTST */
+#define OMAP4_D2DWARMRSTST_SHIFT                3
+#define OMAP4_D2DWARMRSTST_MASK                 (1 << 3)
+
+#endif
diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/sdram-nokia.c
index f392844195d2..14caa228bc0d 100644
--- a/arch/arm/mach-omap2/board-rx51-sdram.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -1,7 +1,7 @@
 /*
- * SDRC register values for RX51
+ * SDRC register values for Nokia boards
  *
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008, 2010 Nokia Corporation
  *
  * Lauri Leukkunen <lauri.leukkunen@nokia.com>
  *
@@ -22,6 +22,7 @@
 #include <plat/clock.h>
 #include <plat/sdrc.h>
 
+#include "sdram-nokia.h"
 
 /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
 struct sdram_timings {
@@ -43,9 +44,28 @@ struct sdram_timings {
         u32 tWTR;
 };
 
-struct omap_sdrc_params rx51_sdrc_params[4];
+static const struct sdram_timings nokia_97dot6mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30725,
+                .tDPL = 15362,
+                .tRRD = 10241,
+                .tRCD = 20483,
+                .tRP = 15362,
+                .tRAS = 40967,
+                .tRC = 56330,
+                .tRFC = 138266,
+                .tXSR = 204839,
+
+                .tREF = 7798,
+
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2,
+        },
+};
 
-static const struct sdram_timings rx51_timings[] = {
+static const struct sdram_timings nokia_166mhz_timings[] = {
         {
                 .casl = 3,
                 .tDAL = 33000,
@@ -66,6 +86,38 @@ static const struct sdram_timings rx51_timings[] = {
         },
 };
 
+static const struct sdram_timings nokia_195dot2mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30725,
+                .tDPL = 15362,
+                .tRRD = 10241,
+                .tRCD = 20483,
+                .tRP = 15362,
+                .tRAS = 40967,
+                .tRC = 56330,
+                .tRFC = 138266,
+                .tXSR = 204839,
+
+                .tREF = 7752,
+
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2,
+        },
+};
+
+static const struct {
+        long rate;
+        struct sdram_timings const *data;
+} nokia_timings[] = {
+        { 83000000, nokia_166mhz_timings },
+        { 97600000, nokia_97dot6mhz_timings },
+        { 166000000, nokia_166mhz_timings },
+        { 195200000, nokia_195dot2mhz_timings },
+};
+static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
+
 static unsigned long sdrc_get_fclk_period(long rate)
 {
         /* In picoseconds */
@@ -110,12 +162,12 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
 #ifdef DEBUG
 #define SDRC_SET_ONE(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval((reg), (st), (end), \
-                        rx51_timings->field, (rate), #field) < 0) \
+                        memory_timings->field, (rate), #field) < 0) \
                 err = -1;
 #else
 #define SDRC_SET_ONE(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval((reg), (st), (end), \
-                        rx51_timings->field) < 0) \
+                        memory_timings->field) < 0) \
                 err = -1;
 #endif
 
@@ -148,18 +200,19 @@ static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
 #ifdef DEBUG
 #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval_ps((reg), (st), (end), \
-                        rx51_timings->field, \
+                        memory_timings->field, \
                         (rate), #field) < 0) \
                 err = -1;
 
 #else
 #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval_ps((reg), (st), (end), \
-                        rx51_timings->field, (rate)) < 0) \
+                        memory_timings->field, (rate)) < 0) \
                 err = -1;
 #endif
 
-static int sdrc_timings(int id, long rate)
+static int sdrc_timings(int id, long rate,
+                        const struct sdram_timings *memory_timings)
 {
         u32 ticks_per_ms;
         u32 rfr, l;
@@ -184,7 +237,7 @@ static int sdrc_timings(int id, long rate)
         SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
 
         ticks_per_ms = l3_rate;
-        rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000;
+        rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
         if (rfr > 65535 + 50)
                 rfr = 65535;
         else
@@ -197,25 +250,30 @@ static int sdrc_timings(int id, long rate)
         l = rfr << 8;
         rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
 
-        rx51_sdrc_params[id].rate = rate;
-        rx51_sdrc_params[id].actim_ctrla = actim_ctrla;
-        rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb;
-        rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl;
-        rx51_sdrc_params[id].mr = 0x32;
+        nokia_sdrc_params[id].rate = rate;
+        nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
+        nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
+        nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
+        nokia_sdrc_params[id].mr = 0x32;
 
-        rx51_sdrc_params[id + 1].rate = 0;
+        nokia_sdrc_params[id + 1].rate = 0;
 
         return err;
 }
 
-struct omap_sdrc_params *rx51_get_sdram_timings(void)
+struct omap_sdrc_params *nokia_get_sdram_timings(void)
 {
-        int err;
+        int err = 0;
+        int i;
 
-        err = sdrc_timings(0, 41500000);
-        err |= sdrc_timings(1, 83000000);
-        err |= sdrc_timings(2, 166000000);
+        for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
+                err |= sdrc_timings(i, nokia_timings[i].rate,
+                                       nokia_timings[i].data);
+                if (err)
+                        pr_err("%s: error with rate %ld: %d\n", __func__,
+                               nokia_timings[i].rate, err);
+        }
 
-        return &rx51_sdrc_params[0];
+        return err ? NULL : nokia_sdrc_params;
 }
 
diff --git a/arch/arm/mach-omap2/sdram-nokia.h b/arch/arm/mach-omap2/sdram-nokia.h
new file mode 100644
index 000000000000..ee63da5f8df0
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-nokia.h
@@ -0,0 +1,12 @@
+/*
+ * SDRC register values for Nokia boards
+ *
+ * Copyright (C) 2010 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+struct omap_sdrc_params *nokia_get_sdram_timings(void);
+
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 4c65f5628b39..da6f3a63b5d5 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -27,8 +27,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 
-#include "prm.h"
-
 #include <plat/sdrc.h>
 #include "sdrc.h"
 
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 68f57bb67fc5..b3f83799e6cf 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
  */
 #define SDRC_MPURATE_LOOPS              96
 
-
 #endif
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 0f4d27aef44d..ccdb010f169d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -28,7 +28,7 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "clock.h"
 #include <plat/sdrc.h>
 #include "sdrc.h"
@@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
         m_type = omap2xxx_sdrc_get_type();
 
         local_irq_save(flags);
+        /*
+         * XXX These calls should be abstracted out through a
+         * prm2xxx.c function
+         */
         if (cpu_is_omap2420())
                 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
         else
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 566e991ede81..1ac361b7b8cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,20 +19,33 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/serial_8250.h>
+#include <linux/pm_runtime.h>
+#include <linux/console.h>
+
+#ifdef CONFIG_SERIAL_OMAP
+#include <plat/omap-serial.h>
+#endif
 
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/clock.h>
-#include <plat/control.h>
+#include <plat/dma.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "pm.h"
+#include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
+#include "control.h"
+#include "mux.h"
 
 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
@@ -48,6 +61,8 @@
  */
 #define DEFAULT_TIMEOUT 0
 
+#define MAX_UART_HWMOD_NAME_LEN         16
+
 struct omap_uart_state {
         int num;
         int can_sleep;
@@ -58,14 +73,21 @@ struct omap_uart_state {
         void __iomem *wk_en;
         u32 wk_mask;
         u32 padconf;
+        u32 dma_enabled;
 
         struct clk *ick;
         struct clk *fck;
         int clocked;
 
-        struct plat_serial8250_port *p;
+        int irq;
+        int regshift;
+        int irqflags;
+        void __iomem *membase;
+        resource_size_t mapbase;
+
         struct list_head node;
-        struct platform_device pdev;
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
 
         u32 errata;
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
@@ -83,75 +105,42 @@ struct omap_uart_state {
 };
 
 static LIST_HEAD(uart_list);
+static u8 num_uarts;
 
-static struct plat_serial8250_port serial_platform_data0[] = {
-        {
-                .irq            = 72,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+static int uart_idle_hwmod(struct omap_device *od)
+{
+        omap_hwmod_idle(od->hwmods[0]);
 
-static struct plat_serial8250_port serial_platform_data1[] = {
-        {
-                .irq            = 73,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+        return 0;
+}
 
-static struct plat_serial8250_port serial_platform_data2[] = {
-        {
-                .irq            = 74,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+static int uart_enable_hwmod(struct omap_device *od)
+{
+        omap_hwmod_enable(od->hwmods[0]);
 
-static struct plat_serial8250_port serial_platform_data3[] = {
+        return 0;
+}
+
+static struct omap_device_pm_latency omap_uart_latency[] = {
         {
-                .irq            = 70,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
+                .deactivate_func = uart_idle_hwmod,
+                .activate_func   = uart_enable_hwmod,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
 };
 
-void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
-{
-        serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
-        serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
-        serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
-        serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
-}
-
 static inline unsigned int __serial_read_reg(struct uart_port *up,
-                                           int offset)
+                                             int offset)
 {
         offset <<= up->regshift;
         return (unsigned int)__raw_readb(up->membase + offset);
 }
 
-static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
+static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
                                            int offset)
 {
-        offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
+        offset <<= uart->regshift;
+        return (unsigned int)__raw_readb(uart->membase + offset);
 }
 
 static inline void __serial_write_reg(struct uart_port *up, int offset,
@@ -161,11 +150,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset,
         __raw_writeb(value, up->membase + offset);
 }
 
-static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
+static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
                                     int value)
 {
-        offset <<= p->regshift;
-        __raw_writeb(value, p->membase + offset);
+        offset <<= uart->regshift;
+        __raw_writeb(value, uart->membase + offset);
 }
 
 /*
@@ -173,14 +162,12 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
  * properly. Note that the TX watermark initialization may not be needed
  * once the 8250.c watermark handling code is merged.
  */
+
 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
-        struct plat_serial8250_port *p = uart->p;
-
-        serial_write_reg(p, UART_OMAP_MDR1, 0x07);
-        serial_write_reg(p, UART_OMAP_SCR, 0x08);
-        serial_write_reg(p, UART_OMAP_MDR1, 0x00);
-        serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
+        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+        serial_write_reg(uart, UART_OMAP_SCR, 0x08);
+        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 }
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
@@ -197,24 +184,23 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
                 u8 fcr_val)
 {
-        struct plat_serial8250_port *p = uart->p;
         u8 timeout = 255;
 
-        serial_write_reg(p, UART_OMAP_MDR1, mdr1_val);
+        serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
         udelay(2);
-        serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
+        serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
                         UART_FCR_CLEAR_RCVR);
         /*
          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
          * TX_FIFO_E bit is 1.
          */
-        while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) &
+        while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
                                 (UART_LSR_THRE | UART_LSR_DR))) {
                 timeout--;
                 if (!timeout) {
                         /* Should *never* happen. we warn and carry on */
-                        dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n",
-                                serial_read_reg(p, UART_LSR));
+                        dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
+                        serial_read_reg(uart, UART_LSR));
                         break;
                 }
                 udelay(1);
@@ -224,23 +210,22 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 static void omap_uart_save_context(struct omap_uart_state *uart)
 {
         u16 lcr = 0;
-        struct plat_serial8250_port *p = uart->p;
 
         if (!enable_off_mode)
                 return;
 
-        lcr = serial_read_reg(p, UART_LCR);
-        serial_write_reg(p, UART_LCR, 0xBF);
-        uart->dll = serial_read_reg(p, UART_DLL);
-        uart->dlh = serial_read_reg(p, UART_DLM);
-        serial_write_reg(p, UART_LCR, lcr);
-        uart->ier = serial_read_reg(p, UART_IER);
-        uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
-        uart->scr = serial_read_reg(p, UART_OMAP_SCR);
-        uart->wer = serial_read_reg(p, UART_OMAP_WER);
-        serial_write_reg(p, UART_LCR, 0x80);
-        uart->mcr = serial_read_reg(p, UART_MCR);
-        serial_write_reg(p, UART_LCR, lcr);
+        lcr = serial_read_reg(uart, UART_LCR);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+        uart->dll = serial_read_reg(uart, UART_DLL);
+        uart->dlh = serial_read_reg(uart, UART_DLM);
+        serial_write_reg(uart, UART_LCR, lcr);
+        uart->ier = serial_read_reg(uart, UART_IER);
+        uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
+        uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
+        uart->wer = serial_read_reg(uart, UART_OMAP_WER);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
+        uart->mcr = serial_read_reg(uart, UART_MCR);
+        serial_write_reg(uart, UART_LCR, lcr);
 
         uart->context_valid = 1;
 }
@@ -248,7 +233,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
 static void omap_uart_restore_context(struct omap_uart_state *uart)
 {
         u16 efr = 0;
-        struct plat_serial8250_port *p = uart->p;
 
         if (!enable_off_mode)
                 return;
@@ -259,31 +243,35 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
         uart->context_valid = 0;
 
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
+                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
         else
-                serial_write_reg(p, UART_OMAP_MDR1, 0x7);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        efr = serial_read_reg(p, UART_EFR);
-        serial_write_reg(p, UART_EFR, UART_EFR_ECB);
-        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(p, UART_IER, 0x0);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        serial_write_reg(p, UART_DLL, uart->dll);
-        serial_write_reg(p, UART_DLM, uart->dlh);
-        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(p, UART_IER, uart->ier);
-        serial_write_reg(p, UART_LCR, 0x80);
-        serial_write_reg(p, UART_MCR, uart->mcr);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        serial_write_reg(p, UART_EFR, efr);
-        serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
-        serial_write_reg(p, UART_OMAP_SCR, uart->scr);
-        serial_write_reg(p, UART_OMAP_WER, uart->wer);
-        serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
+                serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+        efr = serial_read_reg(uart, UART_EFR);
+        serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
+        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(uart, UART_IER, 0x0);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+        serial_write_reg(uart, UART_DLL, uart->dll);
+        serial_write_reg(uart, UART_DLM, uart->dlh);
+        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(uart, UART_IER, uart->ier);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
+        serial_write_reg(uart, UART_MCR, uart->mcr);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+        serial_write_reg(uart, UART_EFR, efr);
+        serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
+        serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
+        serial_write_reg(uart, UART_OMAP_WER, uart->wer);
+        serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
+
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
+                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
         else
-                serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+                /* UART 16x mode */
+                serial_write_reg(uart, UART_OMAP_MDR1,
+                                UART_OMAP_MDR1_16X_MODE);
 }
 #else
 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
@@ -295,8 +283,7 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
         if (uart->clocked)
                 return;
 
-        clk_enable(uart->ick);
-        clk_enable(uart->fck);
+        omap_device_enable(uart->pdev);
         uart->clocked = 1;
         omap_uart_restore_context(uart);
 }
@@ -310,8 +297,7 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 
         omap_uart_save_context(uart);
         uart->clocked = 0;
-        clk_disable(uart->ick);
-        clk_disable(uart->fck);
+        omap_device_idle(uart->pdev);
 }
 
 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
@@ -349,18 +335,24 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 }
 
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
-                                          int enable)
+                                               int enable)
 {
-        struct plat_serial8250_port *p = uart->p;
-        u16 sysc;
+        u8 idlemode;
 
-        sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
-        if (enable)
-                sysc |= 0x2 << 3;
-        else
-                sysc |= 0x1 << 3;
+        if (enable) {
+                /**
+                 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
+                 * in Smartidle Mode When Configured for DMA Operations.
+                 */
+                if (uart->dma_enabled)
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = HWMOD_IDLEMODE_SMART;
+        } else {
+                idlemode = HWMOD_IDLEMODE_NO;
+        }
 
-        serial_write_reg(p, UART_OMAP_SYSC, sysc);
+        omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 }
 
 static void omap_uart_block_sleep(struct omap_uart_state *uart)
@@ -377,7 +369,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
-        if (device_may_wakeup(&uart->pdev.dev))
+        if (device_may_wakeup(&uart->pdev->dev))
                 omap_uart_enable_wakeup(uart);
         else
                 omap_uart_disable_wakeup(uart);
@@ -414,7 +406,7 @@ void omap_uart_resume_idle(int num)
         struct omap_uart_state *uart;
 
         list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num) {
+                if (num == uart->num && uart->can_sleep) {
                         omap_uart_enable_clocks(uart);
 
                         /* Check for IO pad wakeup */
@@ -472,6 +464,7 @@ int omap_uart_can_sleep(void)
  * UART will not idle or sleep for its timeout period.
  *
  **/
+/* static int first_interrupt; */
 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 {
         struct omap_uart_state *uart = dev_id;
@@ -483,7 +476,6 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
@@ -494,11 +486,12 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 mod_timer(&uart->timer, jiffies + uart->timeout);
         omap_uart_smart_idle_enable(uart, 0);
 
-        if (cpu_is_omap34xx()) {
-                u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
+        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+                u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
                 u32 wk_mask = 0;
                 u32 padconf = 0;
 
+                /* XXX These PRM accesses do not belong here */
                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
                 switch (uart->num) {
@@ -514,19 +507,17 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                         wk_mask = OMAP3430_ST_UART3_MASK;
                         padconf = 0x19e;
                         break;
+                case 3:
+                        wk_mask = OMAP3630_ST_UART4_MASK;
+                        padconf = 0x0d2;
+                        break;
                 }
                 uart->wk_mask = wk_mask;
                 uart->padconf = padconf;
         } else if (cpu_is_omap24xx()) {
                 u32 wk_mask = 0;
+                u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 
-                if (cpu_is_omap2430()) {
-                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
-                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
-                } else if (cpu_is_omap2420()) {
-                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
-                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
-                }
                 switch (uart->num) {
                 case 0:
                         wk_mask = OMAP24XX_ST_UART1_MASK;
@@ -535,10 +526,19 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                         wk_mask = OMAP24XX_ST_UART2_MASK;
                         break;
                 case 2:
+                        wk_en = OMAP24XX_PM_WKEN2;
+                        wk_st = OMAP24XX_PM_WKST2;
                         wk_mask = OMAP24XX_ST_UART3_MASK;
                         break;
                 }
                 uart->wk_mask = wk_mask;
+                if (cpu_is_omap2430()) {
+                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
+                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
+                } else if (cpu_is_omap2420()) {
+                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
+                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
+                }
         } else {
                 uart->wk_en = NULL;
                 uart->wk_st = NULL;
@@ -546,9 +546,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        p->irqflags |= IRQF_SHARED;
-        ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
-                          "serial idle", (void *)uart);
+        uart->irqflags |= IRQF_SHARED;
+        ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
+                                   IRQF_SHARED, "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
@@ -558,11 +558,17 @@ void omap_uart_enable_irqs(int enable)
         struct omap_uart_state *uart;
 
         list_for_each_entry(uart, &uart_list, node) {
-                if (enable)
-                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
-                                IRQF_SHARED, "serial idle", (void *)uart);
-                else
-                        free_irq(uart->p->irq, (void *)uart);
+                if (enable) {
+                        pm_runtime_put_sync(&uart->pdev->dev);
+                        ret = request_threaded_irq(uart->irq, NULL,
+                                                   omap_uart_interrupt,
+                                                   IRQF_SHARED,
+                                                   "serial idle",
+                                                   (void *)uart);
+                } else {
+                        pm_runtime_get_noresume(&uart->pdev->dev);
+                        free_irq(uart->irq, (void *)uart);
+                }
         }
 }
 
@@ -570,10 +576,9 @@ static ssize_t sleep_timeout_show(struct device *dev,
                                   struct device_attribute *attr,
                                   char *buf)
 {
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        struct omap_uart_state *uart = container_of(pdev,
-                                        struct omap_uart_state, pdev);
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *odev = to_omap_device(pdev);
+        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 
         return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
@@ -582,10 +587,9 @@ static ssize_t sleep_timeout_store(struct device *dev,
                                    struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        struct omap_uart_state *uart = container_of(pdev,
-                                        struct omap_uart_state, pdev);
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *odev = to_omap_device(pdev);
+        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
@@ -608,48 +612,15 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+static void omap_uart_block_sleep(struct omap_uart_state *uart)
+{
+        /* Needed to enable UART clocks when built without CONFIG_PM */
+        omap_uart_enable_clocks(uart);
+}
 #define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct omap_uart_state omap_uart[] = {
-        {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data0,
-                        },
-                },
-        }, {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM1,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data1,
-                        },
-                },
-        }, {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM2,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data2,
-                        },
-                },
-        },
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = 3,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data3,
-                        },
-                },
-        },
-#endif
-};
-
+#ifndef CONFIG_SERIAL_OMAP
 /*
  * Override the default 8250 read handler: mem_serial_in()
  * Empty RX fifo read causes an abort on omap3630 and omap4
@@ -682,143 +653,209 @@ static void serial_out_override(struct uart_port *up, int offset, int value)
         }
         __serial_write_reg(up, offset, value);
 }
-void __init omap_serial_early_init(void)
+#endif
+
+static int __init omap_serial_early_init(void)
 {
-        int i, nr_ports;
-        char name[16];
+        int i = 0;
 
-        if (!(cpu_is_omap3630() || cpu_is_omap4430()))
-                nr_ports = 3;
-        else
-                nr_ports = ARRAY_SIZE(omap_uart);
+        do {
+                char oh_name[MAX_UART_HWMOD_NAME_LEN];
+                struct omap_hwmod *oh;
+                struct omap_uart_state *uart;
 
-        /*
-         * Make sure the serial ports are muxed on at this point.
-         * You have to mux them off in device drivers later on
-         * if not needed.
-         */
+                snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
+                         "uart%d", i + 1);
+                oh = omap_hwmod_lookup(oh_name);
+                if (!oh)
+                        break;
 
-        for (i = 0; i < nr_ports; i++) {
-                struct omap_uart_state *uart = &omap_uart[i];
-                struct platform_device *pdev = &uart->pdev;
-                struct device *dev = &pdev->dev;
-                struct plat_serial8250_port *p = dev->platform_data;
+                uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
+                if (WARN_ON(!uart))
+                        return -ENODEV;
+
+                uart->oh = oh;
+                uart->num = i++;
+                list_add_tail(&uart->node, &uart_list);
+                num_uarts++;
 
-                /* Don't map zero-based physical address */
-                if (p->mapbase == 0) {
-                        dev_warn(dev, "no physical address for uart#%d,"
-                                 " so skipping early_init...\n", i);
-                        continue;
-                }
                 /*
-                 * Module 4KB + L4 interconnect 4KB
-                 * Static mapping, never released
+                 * NOTE: omap_hwmod_setup*() has not yet been called,
+                 *       so no hwmod functions will work yet.
                  */
-                p->membase = ioremap(p->mapbase, SZ_8K);
-                if (!p->membase) {
-                        dev_err(dev, "ioremap failed for uart%i\n", i + 1);
-                        continue;
-                }
-
-                sprintf(name, "uart%d_ick", i + 1);
-                uart->ick = clk_get(NULL, name);
-                if (IS_ERR(uart->ick)) {
-                        dev_err(dev, "Could not get uart%d_ick\n", i + 1);
-                        uart->ick = NULL;
-                }
-
-                sprintf(name, "uart%d_fck", i+1);
-                uart->fck = clk_get(NULL, name);
-                if (IS_ERR(uart->fck)) {
-                        dev_err(dev, "Could not get uart%d_fck\n", i + 1);
-                        uart->fck = NULL;
-                }
-
-                /* FIXME: Remove this once the clkdev is ready */
-                if (!cpu_is_omap44xx()) {
-                        if (!uart->ick || !uart->fck)
-                                continue;
-                }
 
-                uart->num = i;
-                p->private_data = uart;
-                uart->p = p;
+                /*
+                 * During UART early init, device need to be probed
+                 * to determine SoC specific init before omap_device
+                 * is ready.  Therefore, don't allow idle here
+                 */
+                uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+        } while (1);
 
-                if (cpu_is_omap44xx())
-                        p->irq += 32;
-        }
+        return 0;
 }
+core_initcall(omap_serial_early_init);
 
 /**
  * omap_serial_init_port() - initialize single serial port
- * @port: serial port number (0-3)
+ * @bdata: port specific board data pointer
  *
- * This function initialies serial driver for given @port only.
+ * This function initialies serial driver for given port only.
  * Platforms can call this function instead of omap_serial_init()
  * if they don't plan to use all available UARTs as serial ports.
  *
  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
  * use only one of the two.
  */
-void __init omap_serial_init_port(int port)
+void __init omap_serial_init_port(struct omap_board_data *bdata)
 {
         struct omap_uart_state *uart;
-        struct platform_device *pdev;
-        struct device *dev;
-
-        BUG_ON(port < 0);
-        BUG_ON(port >= ARRAY_SIZE(omap_uart));
-
-        uart = &omap_uart[port];
-        pdev = &uart->pdev;
-        dev = &pdev->dev;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        void *pdata = NULL;
+        u32 pdata_size = 0;
+        char *name;
+#ifndef CONFIG_SERIAL_OMAP
+        struct plat_serial8250_port ports[2] = {
+                {},
+                {.flags = 0},
+        };
+        struct plat_serial8250_port *p = &ports[0];
+#else
+        struct omap_uart_port_info omap_up;
+#endif
 
-        /* Don't proceed if there's no clocks available */
-        if (unlikely(!uart->ick || !uart->fck)) {
-                WARN(1, "%s: can't init uart%d, no clocks available\n",
-                     kobject_name(&dev->kobj), port);
+        if (WARN_ON(!bdata))
+                return;
+        if (WARN_ON(bdata->id < 0))
+                return;
+        if (WARN_ON(bdata->id >= num_uarts))
                 return;
-        }
-
-        omap_uart_enable_clocks(uart);
-
-        omap_uart_reset(uart);
-        omap_uart_idle_init(uart);
 
-        list_add_tail(&uart->node, &uart_list);
+        list_for_each_entry(uart, &uart_list, node)
+                if (bdata->id == uart->num)
+                        break;
 
-        if (WARN_ON(platform_device_register(pdev)))
-                return;
+        oh = uart->oh;
+        uart->dma_enabled = 0;
+#ifndef CONFIG_SERIAL_OMAP
+        name = "serial8250";
 
-        if ((cpu_is_omap34xx() && uart->padconf) ||
-            (uart->wk_en && uart->wk_mask)) {
-                device_init_wakeup(dev, true);
-                DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
-        }
+        /*
+         * !! 8250 driver does not use standard IORESOURCE* It
+         * has it's own custom pdata that can be taken from
+         * the hwmod resource data.  But, this needs to be
+         * done after the build.
+         *
+         * ?? does it have to be done before the register ??
+         * YES, because platform_device_data_add() copies
+         * pdata, it does not use a pointer.
+         */
+        p->flags = UPF_BOOT_AUTOCONF;
+        p->iotype = UPIO_MEM;
+        p->regshift = 2;
+        p->uartclk = OMAP24XX_BASE_BAUD * 16;
+        p->irq = oh->mpu_irqs[0].irq;
+        p->mapbase = oh->slaves[0]->addr->pa_start;
+        p->membase = omap_hwmod_get_mpu_rt_va(oh);
+        p->irqflags = IRQF_SHARED;
+        p->private_data = uart;
 
         /*
-         * omap44xx: Never read empty UART fifo
+         * omap44xx, ti816x: Never read empty UART fifo
          * omap3xxx: Never read empty UART fifo on UARTs
          * with IP rev >=0x52
          */
-        if (cpu_is_omap44xx())
+        uart->regshift = p->regshift;
+        uart->membase = p->membase;
+        if (cpu_is_omap44xx() || cpu_is_ti816x())
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+        else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 
         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
-                uart->p->serial_in = serial_in_override;
-                uart->p->serial_out = serial_out_override;
+                p->serial_in = serial_in_override;
+                p->serial_out = serial_out_override;
+        }
+
+        pdata = &ports[0];
+        pdata_size = 2 * sizeof(struct plat_serial8250_port);
+#else
+
+        name = DRIVER_NAME;
+
+        omap_up.dma_enabled = uart->dma_enabled;
+        omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
+        omap_up.mapbase = oh->slaves[0]->addr->pa_start;
+        omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
+        omap_up.irqflags = IRQF_SHARED;
+        omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+
+        pdata = &omap_up;
+        pdata_size = sizeof(struct omap_uart_port_info);
+#endif
+
+        if (WARN_ON(!oh))
+                return;
+
+        od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+                               omap_uart_latency,
+                               ARRAY_SIZE(omap_uart_latency), false);
+        WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
+             name, oh->name);
+
+        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
+
+        uart->irq = oh->mpu_irqs[0].irq;
+        uart->regshift = 2;
+        uart->mapbase = oh->slaves[0]->addr->pa_start;
+        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
+        uart->pdev = &od->pdev;
+
+        oh->dev_attr = uart;
+
+        console_lock(); /* in case the earlycon is on the UART */
+
+        /*
+         * Because of early UART probing, UART did not get idled
+         * on init.  Now that omap_device is ready, ensure full idle
+         * before doing omap_device_enable().
+         */
+        omap_hwmod_idle(uart->oh);
+
+        omap_device_enable(uart->pdev);
+        omap_uart_idle_init(uart);
+        omap_uart_reset(uart);
+        omap_hwmod_enable_wakeup(uart->oh);
+        omap_device_idle(uart->pdev);
+
+        /*
+         * Need to block sleep long enough for interrupt driven
+         * driver to start.  Console driver is in polling mode
+         * so device needs to be kept enabled while polling driver
+         * is in use.
+         */
+        if (uart->timeout)
+                uart->timeout = (30 * HZ);
+        omap_uart_block_sleep(uart);
+        uart->timeout = DEFAULT_TIMEOUT;
+
+        console_unlock();
+
+        if ((cpu_is_omap34xx() && uart->padconf) ||
+            (uart->wk_en && uart->wk_mask)) {
+                device_init_wakeup(&od->pdev.dev, true);
+                DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
         }
 
         /* Enable the MDR1 errata for OMAP3 */
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx() && !cpu_is_ti816x())
                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 
 /**
- * omap_serial_init() - intialize all supported serial ports
+ * omap_serial_init() - initialize all supported serial ports
  *
  * Initializes all available UARTs as serial ports. Platforms
  * can call this function when they want to have default behaviour
@@ -826,13 +863,15 @@ void __init omap_serial_init_port(int port)
  */
 void __init omap_serial_init(void)
 {
-        int i, nr_ports;
+        struct omap_uart_state *uart;
+        struct omap_board_data bdata;
 
-        if (!(cpu_is_omap3630() || cpu_is_omap4430()))
-                nr_ports = 3;
-        else
-                nr_ports = ARRAY_SIZE(omap_uart);
+        list_for_each_entry(uart, &uart_list, node) {
+                bdata.id = uart->num;
+                bdata.flags = 0;
+                bdata.pads = NULL;
+                bdata.pads_cnt = 0;
+                omap_serial_init_port(&bdata);
 
-        for (i = 0; i < nr_ports; i++)
-                omap_serial_init_port(i);
+        }
 }
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index c7780cc8d919..b5071a47ec39 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -47,6 +47,7 @@
  * Note: This code get's copied to internal SRAM at boot. When the OMAP
  *       wakes up it continues execution at the point it went to sleep.
  */
+        .align  3
 ENTRY(omap24xx_idle_loop_suspend)
         stmfd   sp!, {r0, lr}           @ save registers on stack
         mov     r0, #0                  @ clear for mcr setup
@@ -82,6 +83,7 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
  * The DLL load value is not kept in RETENTION or OFF.  It needs to be restored
  * at wake
  */
+        .align  3
 ENTRY(omap24xx_cpu_suspend)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
         mov     r3, #0x0                @ clear for mcr call
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ba53191ae4c5..63f10669571a 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -1,6 +1,4 @@
 /*
- * linux/arch/arm/mach-omap2/sleep.S
- *
  * (C) Copyright 2007
  * Texas Instruments
  * Karthik Dasu <karthik-dp@ti.com>
@@ -26,28 +24,35 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <plat/sram.h>
 #include <mach/io.h>
-#include <plat/control.h>
 
-#include "cm.h"
-#include "prm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "sdrc.h"
+#include "control.h"
 
-#define SDRC_SCRATCHPAD_SEM_V   0xfa00291c
-
-#define PM_PREPWSTST_CORE_V     OMAP34XX_PRM_REGADDR(CORE_MOD, \
-                                OMAP3430_PM_PREPWSTST)
-#define PM_PREPWSTST_CORE_P     0x48306AE8
-#define PM_PREPWSTST_MPU_V      OMAP34XX_PRM_REGADDR(MPU_MOD, \
-                                OMAP3430_PM_PREPWSTST)
+/*
+ * Registers access definitions
+ */
+#define SDRC_SCRATCHPAD_SEM_OFFS        0xc
+#define SDRC_SCRATCHPAD_SEM_V   OMAP343X_SCRATCHPAD_REGADDR\
+                                        (SDRC_SCRATCHPAD_SEM_OFFS)
+#define PM_PREPWSTST_CORE_P     OMAP3430_PRM_BASE + CORE_MOD +\
+                                        OMAP3430_PM_PREPWSTST
 #define PM_PWSTCTRL_MPU_P       OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
 #define CM_IDLEST1_CORE_V       OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
-#define SRAM_BASE_P             0x40200000
-#define CONTROL_STAT            0x480022F0
-#define SCRATCHPAD_MEM_OFFS     0x310 /* Move this as correct place is
-                                       * available */
-#define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
-                                                + SCRATCHPAD_MEM_OFFS)
+#define CM_IDLEST_CKGEN_V       OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
+#define SRAM_BASE_P             OMAP3_SRAM_PA
+#define CONTROL_STAT            OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
+#define CONTROL_MEM_RTA_CTRL    (OMAP343X_CTRL_BASE +\
+                                        OMAP36XX_CONTROL_MEM_RTA_CTRL)
+
+/* Move this as correct place is available */
+#define SCRATCHPAD_MEM_OFFS     0x310
+#define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE +\
+                                        OMAP343X_CONTROL_MEM_WKUP +\
+                                        SCRATCHPAD_MEM_OFFS)
 #define SDRC_POWER_V            OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 #define SDRC_SYSCONFIG_P        (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
 #define SDRC_MR_0_P             (OMAP343X_SDRC_BASE + SDRC_MR_0)
@@ -59,103 +64,76 @@
 #define SDRC_DLLA_STATUS_V      OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V        OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
-        .text
-/* Function to acquire the semaphore in scratchpad */
-ENTRY(lock_scratchpad_sem)
-        stmfd   sp!, {lr}       @ save registers on stack
-wait_sem:
-        mov     r0,#1
-        ldr     r1, sdrc_scratchpad_sem
-wait_loop:
-        ldr     r2, [r1]        @ load the lock value
-        cmp     r2, r0          @ is the lock free ?
-        beq     wait_loop       @ not free...
-        swp     r2, r0, [r1]    @ semaphore free so lock it and proceed
-        cmp     r2, r0          @ did we succeed ?
-        beq     wait_sem        @ no - try again
-        ldmfd   sp!, {pc}       @ restore regs and return
-sdrc_scratchpad_sem:
-        .word SDRC_SCRATCHPAD_SEM_V
-ENTRY(lock_scratchpad_sem_sz)
-        .word   . - lock_scratchpad_sem
-
-        .text
-/* Function to release the scratchpad semaphore */
-ENTRY(unlock_scratchpad_sem)
-        stmfd   sp!, {lr}       @ save registers on stack
-        ldr     r3, sdrc_scratchpad_sem
-        mov     r2,#0
-        str     r2,[r3]
-        ldmfd   sp!, {pc}       @ restore regs and return
-ENTRY(unlock_scratchpad_sem_sz)
-        .word   . - unlock_scratchpad_sem
+/*
+ * This file needs be built unconditionally as ARM to interoperate correctly
+ * with non-Thumb-2-capable firmware.
+ */
+        .arm
+
+/*
+ * API functions
+ */
+
+/*
+ * The "get_*restore_pointer" functions are used to provide a
+ * physical restore address where the ROM code jumps while waking
+ * up from MPU OFF/OSWR state.
+ * The restore pointer is stored into the scratchpad.
+ */
 
         .text
 /* Function call to get the restore pointer for resume from OFF */
 ENTRY(get_restore_pointer)
-        stmfd   sp!, {lr}     @ save registers on stack
+        stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore
-        ldmfd   sp!, {pc}     @ restore regs and return
+        ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(get_restore_pointer)
+        .align
 ENTRY(get_restore_pointer_sz)
-        .word   . - get_restore_pointer
+        .word   . - get_restore_pointer
+
+        .text
+/* Function call to get the restore pointer for 3630 resume from OFF */
+ENTRY(get_omap3630_restore_pointer)
+        stmfd   sp!, {lr}       @ save registers on stack
+        adr     r0, restore_3630
+        ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(get_omap3630_restore_pointer)
+        .align
+ENTRY(get_omap3630_restore_pointer_sz)
+        .word   . - get_omap3630_restore_pointer
 
         .text
-/* Function call to get the restore pointer for for ES3 to resume from OFF */
+/* Function call to get the restore pointer for ES3 to resume from OFF */
 ENTRY(get_es3_restore_pointer)
         stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore_es3
         ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(get_es3_restore_pointer)
+        .align
 ENTRY(get_es3_restore_pointer_sz)
         .word   . - get_es3_restore_pointer
 
-ENTRY(es3_sdrc_fix)
-        ldr     r4, sdrc_syscfg         @ get config addr
-        ldr     r5, [r4]                @ get value
-        tst     r5, #0x100              @ is part access blocked
-        it      eq
-        biceq   r5, r5, #0x100          @ clear bit if set
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_mr_0           @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_emr2_0         @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_manual_0       @ get config addr
-        mov     r5, #0x2                @ autorefresh command
-        str     r5, [r4]                @ kick off refreshes
-        ldr     r4, sdrc_mr_1           @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_emr2_1         @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_manual_1       @ get config addr
-        mov     r5, #0x2                @ autorefresh command
-        str     r5, [r4]                @ kick off refreshes
-        bx      lr
-sdrc_syscfg:
-        .word   SDRC_SYSCONFIG_P
-sdrc_mr_0:
-        .word   SDRC_MR_0_P
-sdrc_emr2_0:
-        .word   SDRC_EMR2_0_P
-sdrc_manual_0:
-        .word   SDRC_MANUAL_0_P
-sdrc_mr_1:
-        .word   SDRC_MR_1_P
-sdrc_emr2_1:
-        .word   SDRC_EMR2_1_P
-sdrc_manual_1:
-        .word   SDRC_MANUAL_1_P
-ENTRY(es3_sdrc_fix_sz)
-        .word   . - es3_sdrc_fix
+        .text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a flag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future may not need this.
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+        stmfd   sp!, {lr}       @ save registers on stack
+        /* Setup so that we will disable and enable l2 */
+        mov     r1, #0x1
+        adrl    r2, l2dis_3630  @ may be too distant for plain adr
+        str     r1, [r2]
+        ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(enable_omap3630_toggle_l2_on_restore)
 
+        .text
 /* Function to call rom code to save secure ram context */
+        .align  3
 ENTRY(save_secure_ram_context)
         stmfd   sp!, {r1-r12, lr}       @ save registers on stack
-save_secure_ram_debug:
-        /* b save_secure_ram_debug */   @ enable to debug save code
         adr     r3, api_params          @ r3 points to parameters
         str     r0, [r3,#0x4]           @ r0 has sdram address
         ldr     r12, high_mask
@@ -167,53 +145,167 @@ save_secure_ram_debug:
         mov     r1, #0                  @ set task id for ROM code in r1
         mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
         nop
         nop
         nop
         nop
         ldmfd   sp!, {r1-r12, pc}
+        .align
 sram_phy_addr_mask:
         .word   SRAM_BASE_P
 high_mask:
         .word   0xffff
 api_params:
         .word   0x4, 0x0, 0x0, 0x1, 0x1
+ENDPROC(save_secure_ram_context)
 ENTRY(save_secure_ram_context_sz)
         .word   . - save_secure_ram_context
 
 /*
+ * ======================
+ * == Idle entry point ==
+ * ======================
+ */
+
+/*
  * Forces OMAP into idle state
  *
- * omap34xx_suspend() - This bit of code just executes the WFI
- * for normal idles.
+ * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
+ * and executes the WFI instruction. Calling WFI effectively changes the
+ * power domains states to the desired target power states.
+ *
  *
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- *       wakes up it continues execution at the point it went to sleep.
+ * Notes:
+ * - this code gets copied to internal SRAM at boot and after wake-up
+ *   from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
+ * - when the OMAP wakes up it continues at different execution points
+ *   depending on the low power mode (non-OFF vs OFF modes),
+ *   cf. 'Resume path for xxx mode' comments.
  */
+        .align  3
 ENTRY(omap34xx_cpu_suspend)
-        stmfd   sp!, {r0-r12, lr}               @ save registers on stack
-loop:
-        /*b     loop*/  @Enable to debug by stepping through code
-        /* r0 contains restore pointer in sdram */
-        /* r1 contains information about saving context */
-        ldr     r4, sdrc_power          @ read the SDRC_POWER register
-        ldr     r5, [r4]                @ read the contents of SDRC_POWER
-        orr     r5, r5, #0x40           @ enable self refresh on idle req
-        str     r5, [r4]                @ write back to SDRC_POWER register
+        stmfd   sp!, {r0-r12, lr}       @ save registers on stack
 
+        /*
+         * r0 contains CPU context save/restore pointer in sdram
+         * r1 contains information about saving context:
+         *   0 - No context lost
+         *   1 - Only L1 and logic lost
+         *   2 - Only L2 lost (Even L1 is retained we clean it along with L2)
+         *   3 - Both L1 and L2 lost and logic lost
+         */
+
+        /* Directly jump to WFI is the context save is not required */
         cmp     r1, #0x0
-        /* If context save is required, do that and execute wfi */
-        bne     save_context_wfi
+        beq     omap3_do_wfi
+
+        /* Otherwise fall through to the save context code */
+save_context_wfi:
+        mov     r8, r0                  @ Store SDRAM address in r8
+        mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
+        mov     r4, #0x1                @ Number of parameters for restore call
+        stmia   r8!, {r4-r5}            @ Push parameters for restore call
+        mrc     p15, 1, r5, c9, c0, 2   @ Read L2 AUX ctrl register
+        stmia   r8!, {r4-r5}            @ Push parameters for restore call
+
+        /* Check what that target sleep state is from r1 */
+        cmp     r1, #0x2                @ Only L2 lost, no need to save context
+        beq     clean_caches
+
+l1_logic_lost:
+        mov     r4, sp                  @ Store sp
+        mrs     r5, spsr                @ Store spsr
+        mov     r6, lr                  @ Store lr
+        stmia   r8!, {r4-r6}
+
+        mrc     p15, 0, r4, c1, c0, 2   @ Coprocessor access control register
+        mrc     p15, 0, r5, c2, c0, 0   @ TTBR0
+        mrc     p15, 0, r6, c2, c0, 1   @ TTBR1
+        mrc     p15, 0, r7, c2, c0, 2   @ TTBCR
+        stmia   r8!, {r4-r7}
+
+        mrc     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+        mrc     p15, 0, r5, c10, c2, 0  @ PRRR
+        mrc     p15, 0, r6, c10, c2, 1  @ NMRR
+        stmia   r8!,{r4-r6}
+
+        mrc     p15, 0, r4, c13, c0, 1  @ Context ID
+        mrc     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+        mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+        mrs     r7, cpsr                @ Store current cpsr
+        stmia   r8!, {r4-r7}
+
+        mrc     p15, 0, r4, c1, c0, 0   @ save control register
+        stmia   r8!, {r4}
+
+clean_caches:
+        /*
+         * jump out to kernel flush routine
+         *  - reuse that code is better
+         *  - it executes in a cached space so is faster than refetch per-block
+         *  - should be faster and will change with kernel
+         *  - 'might' have to copy address, load and jump to it
+         * Flush all data from the L1 data cache before disabling
+         * SCTLR.C bit.
+         */
+        ldr     r1, kernel_flush
+        mov     lr, pc
+        bx      r1
+
+        /*
+         * Clear the SCTLR.C bit to prevent further data cache
+         * allocation. Clearing SCTLR.C would make all the data accesses
+         * strongly ordered and would not hit the cache.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        bic     r0, r0, #(1 << 2)       @ Disable the C bit
+        mcr     p15, 0, r0, c1, c0, 0
+        isb
+
+        /*
+         * Invalidate L1 data cache. Even though only invalidate is
+         * necessary exported flush API is used here. Doing clean
+         * on already clean cache would be almost NOP.
+         */
+        ldr     r1, kernel_flush
+        blx     r1
+        /*
+         * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+         * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+         * This sequence switches back to ARM.  Note that .align may insert a
+         * nop: bx pc needs to be word-aligned in order to work.
+         */
+ THUMB( .thumb          )
+ THUMB( .align          )
+ THUMB( bx      pc      )
+ THUMB( nop             )
+        .arm
+
+omap3_do_wfi:
+        ldr     r4, sdrc_power          @ read the SDRC_POWER register
+        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        str     r5, [r4]                @ write back to SDRC_POWER register
+
         /* Data memory barrier and Data sync barrier */
-        mov     r1, #0
-        mcr     p15, 0, r1, c7, c10, 4
-        mcr     p15, 0, r1, c7, c10, 5
+        dsb
+        dmb
 
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
         wfi                             @ wait for interrupt
 
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
         nop
         nop
         nop
@@ -226,9 +318,36 @@ loop:
         nop
         bl wait_sdrc_ok
 
-        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
+        mrc     p15, 0, r0, c1, c0, 0
+        tst     r0, #(1 << 2)           @ Check C bit enabled?
+        orreq   r0, r0, #(1 << 2)       @ Enable the C bit if cleared
+        mcreq   p15, 0, r0, c1, c0, 0
+        isb
+
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+
+/*
+ * ==============================
+ * == Resume path for OFF mode ==
+ * ==============================
+ */
+
+/*
+ * The restore_* functions are called by the ROM code
+ *  when back from WFI in OFF mode.
+ * Cf. the get_*restore_pointer functions.
+ *
+ *  restore_es3: applies to 34xx >= ES3.0
+ *  restore_3630: applies to 36xx
+ *  restore: common code for 3xxx
+ */
 restore_es3:
-        /*b restore_es3*/               @ Enable to debug restore code
         ldr     r5, pm_prepwstst_core_p
         ldr     r4, [r5]
         and     r4, r4, #0x3
@@ -245,160 +364,158 @@ copy_to_sram:
         bne     copy_to_sram
         ldr     r1, sram_base
         blx     r1
+        b       restore
+
+restore_3630:
+        ldr     r1, pm_prepwstst_core_p
+        ldr     r2, [r1]
+        and     r2, r2, #0x3
+        cmp     r2, #0x0        @ Check if previous power state of CORE is OFF
+        bne     restore
+        /* Disable RTA before giving control */
+        ldr     r1, control_mem_rta
+        mov     r2, #OMAP36XX_RTA_DISABLE
+        str     r2, [r1]
+
+        /* Fall through to common code for the remaining logic */
+
 restore:
-        /* b restore*/  @ Enable to debug restore code
-        /* Check what was the reason for mpu reset and store the reason in r9*/
-        /* 1 - Only L1 and logic lost */
-        /* 2 - Only L2 lost - In this case, we wont be here */
-        /* 3 - Both L1 and L2 lost */
-        ldr     r1, pm_pwstctrl_mpu
+        /*
+         * Check what was the reason for mpu reset and store the reason in r9:
+         *  0 - No context lost
+         *  1 - Only L1 and logic lost
+         *  2 - Only L2 lost - In this case, we wont be here
+         *  3 - Both L1 and L2 lost
+         */
+        ldr     r1, pm_pwstctrl_mpu
         ldr     r2, [r1]
-        and     r2, r2, #0x3
-        cmp     r2, #0x0        @ Check if target power state was OFF or RET
-        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
+        and     r2, r2, #0x3
+        cmp     r2, #0x0        @ Check if target power state was OFF or RET
+        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
         movne   r9, #0x1        @ Only L1 and L2 lost => avoid L2 invalidation
         bne     logic_l1_restore
+
+        ldr     r0, l2dis_3630
+        cmp     r0, #0x1        @ should we disable L2 on 3630?
+        bne     skipl2dis
+        mrc     p15, 0, r0, c1, c0, 1
+        bic     r0, r0, #2      @ disable L2 cache
+        mcr     p15, 0, r0, c1, c0, 1
+skipl2dis:
         ldr     r0, control_stat
         ldr     r1, [r0]
         and     r1, #0x700
         cmp     r1, #0x300
         beq     l2_inv_gp
-        mov     r0, #40         @ set service ID for PPA
-        mov     r12, r0         @ copy secure Service ID in r12
-        mov     r1, #0          @ set task id for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r0, #40                 @ set service ID for PPA
+        mov     r12, r0                 @ copy secure Service ID in r12
+        mov     r1, #0                  @ set task id for ROM code in r1
+        mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         adr     r3, l2_inv_api_params   @ r3 points to dummy parameters
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
         /* Write to Aux control register to set some bits */
-        mov     r0, #42         @ set service ID for PPA
-        mov     r12, r0         @ copy secure Service ID in r12
-        mov     r1, #0          @ set task id for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r0, #42                 @ set service ID for PPA
+        mov     r12, r0                 @ copy secure Service ID in r12
+        mov     r1, #0                  @ set task id for ROM code in r1
+        mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         ldr     r4, scratchpad_base
-        ldr     r3, [r4, #0xBC] @ r3 points to parameters
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        ldr     r3, [r4, #0xBC]         @ r3 points to parameters
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
 
 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         /* Restore L2 aux control register */
-        @ set service ID for PPA
+                                        @ set service ID for PPA
         mov     r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
-        mov     r12, r0         @ copy service ID in r12
-        mov     r1, #0          @ set task ID for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r12, r0                 @ copy service ID in r12
+        mov     r1, #0                  @ set task ID for ROM code in r1
+        mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         ldr     r4, scratchpad_base
         ldr     r3, [r4, #0xBC]
-        adds    r3, r3, #8      @ r3 points to parameters
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        adds    r3, r3, #8              @ r3 points to parameters
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
 #endif
         b       logic_l1_restore
+
+        .align
 l2_inv_api_params:
-        .word   0x1, 0x00
+        .word   0x1, 0x00
 l2_inv_gp:
         /* Execute smi to invalidate L2 cache */
-        mov r12, #0x1                         @ set up to invalide L2
-smi:    .word 0xE1600070                @ Call SMI monitor (smieq)
+        mov r12, #0x1                   @ set up to invalidate L2
+        smc     #0                      @ Call SMI monitor (smieq)
         /* Write to Aux control register to set some bits */
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         ldr     r0, [r3,#4]
         mov     r12, #0x3
-        .word 0xE1600070        @ Call SMI monitor (smieq)
+        smc     #0                      @ Call SMI monitor (smieq)
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         ldr     r0, [r3,#12]
         mov     r12, #0x2
-        .word 0xE1600070        @ Call SMI monitor (smieq)
+        smc     #0                      @ Call SMI monitor (smieq)
 logic_l1_restore:
+        ldr     r1, l2dis_3630
+        cmp     r1, #0x1                @ Test if L2 re-enable needed on 3630
+        bne     skipl2reen
+        mrc     p15, 0, r1, c1, c0, 1
+        orr     r1, r1, #2              @ re-enable L2 cache
+        mcr     p15, 0, r1, c1, c0, 1
+skipl2reen:
         mov     r1, #0
-        /* Invalidate all instruction caches to PoU
-         * and flush branch target cache */
+        /*
+         * Invalidate all instruction caches to PoU
+         * and flush branch target cache
+         */
         mcr     p15, 0, r1, c7, c5, 0
 
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         adds    r3, r3, #16
+
         ldmia   r3!, {r4-r6}
-        mov     sp, r4
-        msr     spsr_cxsf, r5
-        mov     lr, r6
-
-        ldmia   r3!, {r4-r9}
-        /* Coprocessor access Control Register */
-        mcr p15, 0, r4, c1, c0, 2
-
-        /* TTBR0 */
-        MCR p15, 0, r5, c2, c0, 0
-        /* TTBR1 */
-        MCR p15, 0, r6, c2, c0, 1
-        /* Translation table base control register */
-        MCR p15, 0, r7, c2, c0, 2
-        /*domain access Control Register */
-        MCR p15, 0, r8, c3, c0, 0
-        /* data fault status Register */
-        MCR p15, 0, r9, c5, c0, 0
-
-        ldmia  r3!,{r4-r8}
-        /* instruction fault status Register */
-        MCR p15, 0, r4, c5, c0, 1
-        /*Data Auxiliary Fault Status Register */
-        MCR p15, 0, r5, c5, c1, 0
-        /*Instruction Auxiliary Fault Status Register*/
-        MCR p15, 0, r6, c5, c1, 1
-        /*Data Fault Address Register */
-        MCR p15, 0, r7, c6, c0, 0
-        /*Instruction Fault Address Register*/
-        MCR p15, 0, r8, c6, c0, 2
-        ldmia  r3!,{r4-r7}
-
-        /* user r/w thread and process ID */
-        MCR p15, 0, r4, c13, c0, 2
-        /* user ro thread and process ID */
-        MCR p15, 0, r5, c13, c0, 3
-        /*Privileged only thread and process ID */
-        MCR p15, 0, r6, c13, c0, 4
-        /* cache size selection */
-        MCR p15, 2, r7, c0, c0, 0
-        ldmia  r3!,{r4-r8}
-        /* Data TLB lockdown registers */
-        MCR p15, 0, r4, c10, c0, 0
-        /* Instruction TLB lockdown registers */
-        MCR p15, 0, r5, c10, c0, 1
-        /* Secure or Nonsecure Vector Base Address */
-        MCR p15, 0, r6, c12, c0, 0
-        /* FCSE PID */
-        MCR p15, 0, r7, c13, c0, 0
-        /* Context PID */
-        MCR p15, 0, r8, c13, c0, 1
-
-        ldmia  r3!,{r4-r5}
-        /* primary memory remap register */
-        MCR p15, 0, r4, c10, c2, 0
-        /*normal memory remap register */
-        MCR p15, 0, r5, c10, c2, 1
-
-        /* Restore cpsr */
-        ldmia   r3!,{r4}        /*load CPSR from SDRAM*/
-        msr     cpsr, r4        /*store cpsr */
+        mov     sp, r4                  @ Restore sp
+        msr     spsr_cxsf, r5           @ Restore spsr
+        mov     lr, r6                  @ Restore lr
+
+        ldmia   r3!, {r4-r7}
+        mcr     p15, 0, r4, c1, c0, 2   @ Coprocessor access Control Register
+        mcr     p15, 0, r5, c2, c0, 0   @ TTBR0
+        mcr     p15, 0, r6, c2, c0, 1   @ TTBR1
+        mcr     p15, 0, r7, c2, c0, 2   @ TTBCR
+
+        ldmia   r3!,{r4-r6}
+        mcr     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+        mcr     p15, 0, r5, c10, c2, 0  @ PRRR
+        mcr     p15, 0, r6, c10, c2, 1  @ NMRR
+
+
+        ldmia   r3!,{r4-r7}
+        mcr     p15, 0, r4, c13, c0, 1  @ Context ID
+        mcr     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+        mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+        msr     cpsr, r7                @ store cpsr
 
         /* Enabling MMU here */
-        mrc     p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
-        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
+        mrc     p15, 0, r7, c2, c0, 2   @ Read TTBRControl
+        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
         and     r7, #0x7
         cmp     r7, #0x0
         beq     usettbr0
 ttbr_error:
-        /* More work needs to be done to support N[0:2] value other than 0
-        * So looping here so that the error can be detected
-        */
+        /*
+         * More work needs to be done to support N[0:2] value other than 0
+         * So looping here so that the error can be detected
+         */
         b       ttbr_error
 usettbr0:
         mrc     p15, 0, r2, c2, c0, 0
@@ -406,21 +523,25 @@ usettbr0:
         and     r2, r5
         mov     r4, pc
         ldr     r5, table_index_mask
-        and     r4, r5 /* r4 = 31 to 20 bits of pc */
+        and     r4, r5                  @ r4 = 31 to 20 bits of pc
         /* Extract the value to be written to table entry */
         ldr     r1, table_entry
-        add     r1, r1, r4 /* r1 has value to be written to table entry*/
+        /* r1 has the value to be written to table entry*/
+        add     r1, r1, r4
         /* Getting the address of table entry to modify */
         lsr     r4, #18
-        add     r2, r4 /* r2 has the location which needs to be modified */
+        /* r2 has the location which needs to be modified */
+        add     r2, r4
         /* Storing previous entry of location being modified */
         ldr     r5, scratchpad_base
         ldr     r4, [r2]
         str     r4, [r5, #0xC0]
         /* Modify the table entry */
         str     r1, [r2]
-        /* Storing address of entry being modified
-         * - will be restored after enabling MMU */
+        /*
+         * Storing address of entry being modified
+         * - will be restored after enabling MMU
+         */
         ldr     r5, scratchpad_base
         str     r2, [r5, #0xC4]
 
@@ -429,221 +550,172 @@ usettbr0:
         mcr     p15, 0, r0, c7, c5, 6   @ Invalidate branch predictor array
         mcr     p15, 0, r0, c8, c5, 0   @ Invalidate instruction TLB
         mcr     p15, 0, r0, c8, c6, 0   @ Invalidate data TLB
-        /* Restore control register  but dont enable caches here*/
-        /* Caches will be enabled after restoring MMU table entry */
+        /*
+         * Restore control register. This enables the MMU.
+         * The caches and prediction are not enabled here, they
+         * will be enabled after restoring the MMU table entry.
+         */
         ldmia   r3!, {r4}
         /* Store previous value of control register in scratchpad */
         str     r4, [r5, #0xC8]
         ldr     r2, cache_pred_disable_mask
         and     r4, r2
         mcr     p15, 0, r4, c1, c0, 0
+        dsb
+        isb
+        ldr     r0, =restoremmu_on
+        bx      r0
 
-        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
-save_context_wfi:
-        /*b     save_context_wfi*/      @ enable to debug save code
-        mov     r8, r0 /* Store SDRAM address in r8 */
-        mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
-        mov     r4, #0x1                @ Number of parameters for restore call
-        stmia   r8!, {r4-r5}            @ Push parameters for restore call
-        mrc     p15, 1, r5, c9, c0, 2   @ Read L2 AUX ctrl register
-        stmia   r8!, {r4-r5}            @ Push parameters for restore call
-        /* Check what that target sleep state is:stored in r1*/
-        /* 1 - Only L1 and logic lost */
-        /* 2 - Only L2 lost */
-        /* 3 - Both L1 and L2 lost */
-        cmp     r1, #0x2 /* Only L2 lost */
-        beq     clean_l2
-        cmp     r1, #0x1 /* L2 retained */
-        /* r9 stores whether to clean L2 or not*/
-        moveq   r9, #0x0 /* Dont Clean L2 */
-        movne   r9, #0x1 /* Clean L2 */
-l1_logic_lost:
-        /* Store sp and spsr to SDRAM */
-        mov     r4, sp
-        mrs     r5, spsr
-        mov     r6, lr
-        stmia   r8!, {r4-r6}
-        /* Save all ARM registers */
-        /* Coprocessor access control register */
-        mrc     p15, 0, r6, c1, c0, 2
-        stmia   r8!, {r6}
-        /* TTBR0, TTBR1 and Translation table base control */
-        mrc     p15, 0, r4, c2, c0, 0
-        mrc     p15, 0, r5, c2, c0, 1
-        mrc     p15, 0, r6, c2, c0, 2
-        stmia   r8!, {r4-r6}
-        /* Domain access control register, data fault status register,
-        and instruction fault status register */
-        mrc     p15, 0, r4, c3, c0, 0
-        mrc     p15, 0, r5, c5, c0, 0
-        mrc     p15, 0, r6, c5, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Data aux fault status register, instruction aux fault status,
-        datat fault address register and instruction fault address register*/
-        mrc     p15, 0, r4, c5, c1, 0
-        mrc     p15, 0, r5, c5, c1, 1
-        mrc     p15, 0, r6, c6, c0, 0
-        mrc     p15, 0, r7, c6, c0, 2
-        stmia   r8!, {r4-r7}
-        /* user r/w thread and process ID, user r/o thread and process ID,
-        priv only thread and process ID, cache size selection */
-        mrc     p15, 0, r4, c13, c0, 2
-        mrc     p15, 0, r5, c13, c0, 3
-        mrc     p15, 0, r6, c13, c0, 4
-        mrc     p15, 2, r7, c0, c0, 0
-        stmia   r8!, {r4-r7}
-        /* Data TLB lockdown, instruction TLB lockdown registers */
-        mrc     p15, 0, r5, c10, c0, 0
-        mrc     p15, 0, r6, c10, c0, 1
-        stmia   r8!, {r5-r6}
-        /* Secure or non secure vector base address, FCSE PID, Context PID*/
-        mrc     p15, 0, r4, c12, c0, 0
-        mrc     p15, 0, r5, c13, c0, 0
-        mrc     p15, 0, r6, c13, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Primary remap, normal remap registers */
-        mrc     p15, 0, r4, c10, c2, 0
-        mrc     p15, 0, r5, c10, c2, 1
-        stmia   r8!,{r4-r5}
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
+restoremmu_on:
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
-        /* Store current cpsr*/
-        mrs     r2, cpsr
-        stmia   r8!, {r2}
 
-        mrc     p15, 0, r4, c1, c0, 0
-        /* save control register */
-        stmia   r8!, {r4}
-clean_caches:
-        /* Clean Data or unified cache to POU*/
-        /* How to invalidate only L1 cache???? - #FIX_ME# */
-        /* mcr  p15, 0, r11, c7, c11, 1 */
-        cmp     r9, #1 /* Check whether L2 inval is required or not*/
-        bne     skip_l2_inval
-clean_l2:
-        /* read clidr */
-        mrc     p15, 1, r0, c0, c0, 1
-        /* extract loc from clidr */
-        ands    r3, r0, #0x7000000
-        /* left align loc bit field */
-        mov     r3, r3, lsr #23
-        /* if loc is 0, then no need to clean */
-        beq     finished
-        /* start clean at cache level 0 */
-        mov     r10, #0
-loop1:
-        /* work out 3x current cache level */
-        add     r2, r10, r10, lsr #1
-        /* extract cache type bits from clidr*/
-        mov     r1, r0, lsr r2
-        /* mask of the bits for current cache only */
-        and     r1, r1, #7
-        /* see what cache we have at this level */
-        cmp     r1, #2
-        /* skip if no cache, or just i-cache */
-        blt     skip
-        /* select current cache level in cssr */
-        mcr     p15, 2, r10, c0, c0, 0
-        /* isb to sych the new cssr&csidr */
-        isb
-        /* read the new csidr */
-        mrc     p15, 1, r1, c0, c0, 0
-        /* extract the length of the cache lines */
-        and     r2, r1, #7
-        /* add 4 (line length offset) */
-        add     r2, r2, #4
-        ldr     r4, assoc_mask
-        /* find maximum number on the way size */
-        ands    r4, r4, r1, lsr #3
-        /* find bit position of way size increment */
-        clz     r5, r4
-        ldr     r7, numset_mask
-        /* extract max number of the index size*/
-        ands    r7, r7, r1, lsr #13
-loop2:
-        mov     r9, r4
-        /* create working copy of max way size*/
-loop3:
-        /* factor way and cache number into r11 */
-        orr     r11, r10, r9, lsl r5
-        /* factor index number into r11 */
-        orr     r11, r11, r7, lsl r2
-        /*clean & invalidate by set/way */
-        mcr     p15, 0, r11, c7, c10, 2
-        /* decrement the way*/
-        subs    r9, r9, #1
-        bge     loop3
-        /*decrement the index */
-        subs    r7, r7, #1
-        bge     loop2
-skip:
-        add     r10, r10, #2
-        /* increment cache number */
-        cmp     r3, r10
-        bgt     loop1
-finished:
-        /*swith back to cache level 0 */
-        mov     r10, #0
-        /* select current cache level in cssr */
-        mcr     p15, 2, r10, c0, c0, 0
-        isb
-skip_l2_inval:
-        /* Data memory barrier and Data sync barrier */
-        mov     r1, #0
-        mcr     p15, 0, r1, c7, c10, 4
-        mcr     p15, 0, r1, c7, c10, 5
+/*
+ * Internal functions
+ */
 
-        wfi                             @ wait for interrupt
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        bl wait_sdrc_ok
-        /* restore regs and return */
-        ldmfd   sp!, {r0-r12, pc}
+/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
+        .text
+        .align  3
+ENTRY(es3_sdrc_fix)
+        ldr     r4, sdrc_syscfg         @ get config addr
+        ldr     r5, [r4]                @ get value
+        tst     r5, #0x100              @ is part access blocked
+        it      eq
+        biceq   r5, r5, #0x100          @ clear bit if set
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_mr_0           @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_emr2_0         @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_manual_0       @ get config addr
+        mov     r5, #0x2                @ autorefresh command
+        str     r5, [r4]                @ kick off refreshes
+        ldr     r4, sdrc_mr_1           @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_emr2_1         @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_manual_1       @ get config addr
+        mov     r5, #0x2                @ autorefresh command
+        str     r5, [r4]                @ kick off refreshes
+        bx      lr
+
+        .align
+sdrc_syscfg:
+        .word   SDRC_SYSCONFIG_P
+sdrc_mr_0:
+        .word   SDRC_MR_0_P
+sdrc_emr2_0:
+        .word   SDRC_EMR2_0_P
+sdrc_manual_0:
+        .word   SDRC_MANUAL_0_P
+sdrc_mr_1:
+        .word   SDRC_MR_1_P
+sdrc_emr2_1:
+        .word   SDRC_EMR2_1_P
+sdrc_manual_1:
+        .word   SDRC_MANUAL_1_P
+ENDPROC(es3_sdrc_fix)
+ENTRY(es3_sdrc_fix_sz)
+        .word   . - es3_sdrc_fix
+
+/*
+ * This function implements the erratum ID i581 WA:
+ *  SDRC state restore before accessing the SDRAM
+ *
+ * Only used at return from non-OFF mode. For OFF
+ * mode the ROM code configures the SDRC and
+ * the DPLL before calling the restore code directly
+ * from DDR.
+ */
 
 /* Make sure SDRC accesses are ok */
 wait_sdrc_ok:
-        ldr     r4, cm_idlest1_core
-        ldr     r5, [r4]
-        and     r5, r5, #0x2
-        cmp     r5, #0
-        bne     wait_sdrc_ok
-        ldr     r4, sdrc_power
-        ldr     r5, [r4]
-        bic     r5, r5, #0x40
-        str     r5, [r4]
+
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
+        ldr     r4, cm_idlest_ckgen
+wait_dpll3_lock:
+        ldr     r5, [r4]
+        tst     r5, #1
+        beq     wait_dpll3_lock
+
+        ldr     r4, cm_idlest1_core
+wait_sdrc_ready:
+        ldr     r5, [r4]
+        tst     r5, #0x2
+        bne     wait_sdrc_ready
+        /* allow DLL powerdown upon hw idle req */
+        ldr     r4, sdrc_power
+        ldr     r5, [r4]
+        bic     r5, r5, #0x40
+        str     r5, [r4]
+
+/*
+ * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
+ * base instead.
+ * Be careful not to clobber r7 when maintaing this code.
+ */
+
+is_dll_in_lock_mode:
+        /* Is dll in lock mode? */
+        ldr     r4, sdrc_dlla_ctrl
+        ldr     r5, [r4]
+        tst     r5, #0x4
+        bxne    lr                      @ Return if locked
+        /* wait till dll locks */
+        adr     r7, kick_counter
+wait_dll_lock_timed:
+        ldr     r4, wait_dll_lock_counter
+        add     r4, r4, #1
+        str     r4, [r7, #wait_dll_lock_counter - kick_counter]
+        ldr     r4, sdrc_dlla_status
+        /* Wait 20uS for lock */
+        mov     r6, #8
 wait_dll_lock:
-        /* Is dll in lock mode? */
-        ldr     r4, sdrc_dlla_ctrl
-        ldr     r5, [r4]
-        tst     r5, #0x4
-        bxne    lr
-        /* wait till dll locks */
-        ldr     r4, sdrc_dlla_status
-        ldr     r5, [r4]
-        and     r5, r5, #0x4
-        cmp     r5, #0x4
-        bne     wait_dll_lock
-        bx      lr
+        subs    r6, r6, #0x1
+        beq     kick_dll
+        ldr     r5, [r4]
+        and     r5, r5, #0x4
+        cmp     r5, #0x4
+        bne     wait_dll_lock
+        bx      lr                      @ Return when locked
+
+        /* disable/reenable DLL if not locked */
+kick_dll:
+        ldr     r4, sdrc_dlla_ctrl
+        ldr     r5, [r4]
+        mov     r6, r5
+        bic     r6, #(1<<3)             @ disable dll
+        str     r6, [r4]
+        dsb
+        orr     r6, r6, #(1<<3)         @ enable dll
+        str     r6, [r4]
+        dsb
+        ldr     r4, kick_counter
+        add     r4, r4, #1
+        str     r4, [r7]                @ kick_counter
+        b       wait_dll_lock_timed
 
+        .align
 cm_idlest1_core:
         .word   CM_IDLEST1_CORE_V
+cm_idlest_ckgen:
+        .word   CM_IDLEST_CKGEN_V
 sdrc_dlla_status:
         .word   SDRC_DLLA_STATUS_V
 sdrc_dlla_ctrl:
         .word   SDRC_DLLA_CTRL_V
-pm_prepwstst_core:
-        .word   PM_PREPWSTST_CORE_V
 pm_prepwstst_core_p:
         .word   PM_PREPWSTST_CORE_P
-pm_prepwstst_mpu:
-        .word   PM_PREPWSTST_MPU_V
 pm_pwstctrl_mpu:
         .word   PM_PWSTCTRL_MPU_P
 scratchpad_base:
@@ -651,13 +723,7 @@ scratchpad_base:
 sram_base:
         .word   SRAM_BASE_P + 0x8000
 sdrc_power:
-        .word SDRC_POWER_V
-clk_stabilize_delay:
-        .word 0x000001FF
-assoc_mask:
-        .word   0x3ff
-numset_mask:
-        .word   0x7fff
+        .word   SDRC_POWER_V
 ttbrbit_mask:
         .word   0xFFFFC000
 table_index_mask:
@@ -668,5 +734,21 @@ cache_pred_disable_mask:
         .word   0xFFFFE7FB
 control_stat:
         .word   CONTROL_STAT
+control_mem_rta:
+        .word   CONTROL_MEM_RTA_CTRL
+kernel_flush:
+        .word   v7_flush_dcache_all
+l2dis_3630:
+        .word   0
+        /*
+         * When exporting to userspace while the counters are in SRAM,
+         * these 2 words need to be at the end to facilitate retrival!
+         */
+kick_counter:
+        .word   0
+wait_dll_lock_counter:
+        .word   0
+ENDPROC(omap34xx_cpu_suspend)
+
 ENTRY(omap34xx_cpu_suspend_sz)
         .word   . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
new file mode 100644
index 000000000000..f438cf4d847b
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -0,0 +1,59 @@
+/*
+ * Smart reflex Class 3 specific implementations
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "smartreflex.h"
+
+static int sr_class3_enable(struct voltagedomain *voltdm)
+{
+        unsigned long volt = omap_voltage_get_nom_volt(voltdm);
+
+        if (!volt) {
+                pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
+                                __func__, voltdm->name);
+                return -ENODATA;
+        }
+
+        omap_vp_enable(voltdm);
+        return sr_enable(voltdm, volt);
+}
+
+static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+{
+        omap_vp_disable(voltdm);
+        sr_disable(voltdm);
+        if (is_volt_reset)
+                omap_voltage_reset(voltdm);
+
+        return 0;
+}
+
+static int sr_class3_configure(struct voltagedomain *voltdm)
+{
+        return sr_configure_errgen(voltdm);
+}
+
+/* SR class3 structure */
+static struct omap_sr_class_data class3_data = {
+        .enable = sr_class3_enable,
+        .disable = sr_class3_disable,
+        .configure = sr_class3_configure,
+        .class_type = SR_CLASS3,
+};
+
+/* Smartreflex Class3 init API to be called from board file */
+static int __init sr_class3_init(void)
+{
+        pr_info("SmartReflex Class3 initialized\n");
+        return sr_register_class(&class3_data);
+}
+late_initcall(sr_class3_init);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 000000000000..fb7dc52394a8
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,1043 @@
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+
+#include <plat/common.h>
+
+#include "pm.h"
+#include "smartreflex.h"
+
+#define SMARTREFLEX_NAME_LEN    16
+#define NVALUE_NAME_LEN         40
+#define SR_DISABLE_TIMEOUT      200
+
+struct omap_sr {
+        int                             srid;
+        int                             ip_type;
+        int                             nvalue_count;
+        bool                            autocomp_active;
+        u32                             clk_length;
+        u32                             err_weight;
+        u32                             err_minlimit;
+        u32                             err_maxlimit;
+        u32                             accum_data;
+        u32                             senn_avgweight;
+        u32                             senp_avgweight;
+        u32                             senp_mod;
+        u32                             senn_mod;
+        unsigned int                    irq;
+        void __iomem                    *base;
+        struct platform_device          *pdev;
+        struct list_head                node;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+        struct dentry                   *dbg_dir;
+};
+
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+
+static struct omap_sr_class_data *sr_class;
+static struct omap_sr_pmic_data *sr_pmic_data;
+
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+        __raw_writel(value, (sr->base + offset));
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
+                                        u32 value)
+{
+        u32 reg_val;
+        u32 errconfig_offs = 0, errconfig_mask = 0;
+
+        reg_val = __raw_readl(sr->base + offset);
+        reg_val &= ~mask;
+
+        /*
+         * Smartreflex error config register is special as it contains
+         * certain status bits which if written a 1 into means a clear
+         * of those bits. So in order to make sure no accidental write of
+         * 1 happens to those status bits, do a clear of them in the read
+         * value. This mean this API doesn't rewrite values in these bits
+         * if they are currently set, but does allow the caller to write
+         * those bits.
+         */
+        if (sr->ip_type == SR_TYPE_V1) {
+                errconfig_offs = ERRCONFIG_V1;
+                errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                errconfig_offs = ERRCONFIG_V2;
+                errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
+        }
+
+        if (offset == errconfig_offs)
+                reg_val &= ~errconfig_mask;
+
+        reg_val |= value;
+
+        __raw_writel(reg_val, (sr->base + offset));
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
+{
+        return __raw_readl(sr->base + offset);
+}
+
+static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr_info;
+
+        if (!voltdm) {
+                pr_err("%s: Null voltage domain passed!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        list_for_each_entry(sr_info, &sr_list, node) {
+                if (voltdm == sr_info->voltdm)
+                        return sr_info;
+        }
+
+        return ERR_PTR(-ENODATA);
+}
+
+static irqreturn_t sr_interrupt(int irq, void *data)
+{
+        struct omap_sr *sr_info = (struct omap_sr *)data;
+        u32 status = 0;
+
+        if (sr_info->ip_type == SR_TYPE_V1) {
+                /* Read the status bits */
+                status = sr_read_reg(sr_info, ERRCONFIG_V1);
+
+                /* Clear them by writing back */
+                sr_write_reg(sr_info, ERRCONFIG_V1, status);
+        } else if (sr_info->ip_type == SR_TYPE_V2) {
+                /* Read the status bits */
+                sr_read_reg(sr_info, IRQSTATUS);
+
+                /* Clear them by writing back */
+                sr_write_reg(sr_info, IRQSTATUS, status);
+        }
+
+        if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
+                sr_class->notify(sr_info->voltdm, status);
+
+        return IRQ_HANDLED;
+}
+
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+        struct clk *sys_ck;
+        u32 sys_clk_speed;
+
+        if (cpu_is_omap34xx())
+                sys_ck = clk_get(NULL, "sys_ck");
+        else
+                sys_ck = clk_get(NULL, "sys_clkin_ck");
+
+        if (IS_ERR(sys_ck)) {
+                dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
+                        __func__);
+                return;
+        }
+        sys_clk_speed = clk_get_rate(sys_ck);
+        clk_put(sys_ck);
+
+        switch (sys_clk_speed) {
+        case 12000000:
+                sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+                break;
+        case 13000000:
+                sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+                break;
+        case 19200000:
+                sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+                break;
+        case 26000000:
+                sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+                break;
+        case 38400000:
+                sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
+                        __func__, sys_clk_speed);
+                break;
+        }
+}
+
+static void sr_set_regfields(struct omap_sr *sr)
+{
+        /*
+         * For time being these values are defined in smartreflex.h
+         * and populated during init. May be they can be moved to board
+         * file or pmic specific data structure. In that case these structure
+         * fields will have to be populated using the pdata or pmic structure.
+         */
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                sr->err_weight = OMAP3430_SR_ERRWEIGHT;
+                sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+                sr->accum_data = OMAP3430_SR_ACCUMDATA;
+                if (!(strcmp(sr->voltdm->name, "mpu"))) {
+                        sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+                        sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+                } else {
+                        sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+                        sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+                }
+        }
+}
+
+static void sr_start_vddautocomp(struct omap_sr *sr)
+{
+        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+                dev_warn(&sr->pdev->dev,
+                        "%s: smartreflex class driver not registered\n",
+                        __func__);
+                return;
+        }
+
+        if (!sr_class->enable(sr->voltdm))
+                sr->autocomp_active = true;
+}
+
+static void sr_stop_vddautocomp(struct omap_sr *sr)
+{
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev,
+                        "%s: smartreflex class driver not registered\n",
+                        __func__);
+                return;
+        }
+
+        if (sr->autocomp_active) {
+                sr_class->disable(sr->voltdm, 1);
+                sr->autocomp_active = false;
+        }
+}
+
+/*
+ * This function handles the intializations which have to be done
+ * only when both sr device and class driver regiter has
+ * completed. This will be attempted to be called from both sr class
+ * driver register and sr device intializtion API's. Only one call
+ * will ultimately succeed.
+ *
+ * Currently this function registers interrrupt handler for a particular SR
+ * if smartreflex class driver is already registered and has
+ * requested for interrupts and the SR interrupt line in present.
+ */
+static int sr_late_init(struct omap_sr *sr_info)
+{
+        char *name;
+        struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
+        struct resource *mem;
+        int ret = 0;
+
+        if (sr_class->class_type == SR_CLASS2 &&
+                sr_class->notify_flags && sr_info->irq) {
+
+                name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
+                if (name == NULL) {
+                        ret = -ENOMEM;
+                        goto error;
+                }
+                ret = request_irq(sr_info->irq, sr_interrupt,
+                                0, name, (void *)sr_info);
+                if (ret)
+                        goto error;
+        }
+
+        if (pdata && pdata->enable_on_init)
+                sr_start_vddautocomp(sr_info);
+
+        return ret;
+
+error:
+                iounmap(sr_info->base);
+                mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+                release_mem_region(mem->start, resource_size(mem));
+                list_del(&sr_info->node);
+                dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+                        "interrupt handler. Smartreflex will"
+                        "not function as desired\n", __func__);
+                kfree(name);
+                kfree(sr_info);
+                return ret;
+}
+
+static void sr_v1_disable(struct omap_sr *sr)
+{
+        int timeout = 0;
+
+        /* Enable MCUDisableAcknowledge interrupt */
+        sr_modify_reg(sr, ERRCONFIG_V1,
+                        ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+        /* SRCONFIG - disable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+        /* Disable all other SR interrupts and clear the status */
+        sr_modify_reg(sr, ERRCONFIG_V1,
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+                        ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+                        (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+                        ERRCONFIG_MCUBOUNDINTST |
+                        ERRCONFIG_VPBOUNDINTST_V1));
+
+        /*
+         * Wait for SR to be disabled.
+         * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+         */
+        omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+                        ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+                        timeout);
+
+        if (timeout >= SR_DISABLE_TIMEOUT)
+                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+                        __func__);
+
+        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+        sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+                        ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+        int timeout = 0;
+
+        /* Enable MCUDisableAcknowledge interrupt */
+        sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+        /* SRCONFIG - disable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+        /* Disable all other SR interrupts and clear the status */
+        sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+                        ERRCONFIG_VPBOUNDINTST_V2);
+        sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+                        IRQENABLE_MCUVALIDINT |
+                        IRQENABLE_MCUBOUNDSINT));
+        sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+                        IRQSTATUS_MCVALIDINT |
+                        IRQSTATUS_MCBOUNDSINT));
+
+        /*
+         * Wait for SR to be disabled.
+         * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+         */
+        omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
+                        IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+                        timeout);
+
+        if (timeout >= SR_DISABLE_TIMEOUT)
+                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+                        __func__);
+
+        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+        sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+        sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
+static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
+{
+        int i;
+
+        if (!sr->nvalue_table) {
+                dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
+                        __func__);
+                return 0;
+        }
+
+        for (i = 0; i < sr->nvalue_count; i++) {
+                if (sr->nvalue_table[i].efuse_offs == efuse_offs)
+                        return sr->nvalue_table[i].nvalue;
+        }
+
+        return 0;
+}
+
+/* Public Functions */
+
+/**
+ * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
+ *                       error generator module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the error generator module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_errgen(struct voltagedomain *voltdm)
+{
+        u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
+        u32 vpboundint_st, senp_en = 0, senn_en = 0;
+        u8 senp_shift, senn_shift;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+
+        if (!sr->clk_length)
+                sr_set_clk_length(sr);
+
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+
+        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_config |= SRCONFIG_DELAYCTRL;
+                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+                errconfig_offs = ERRCONFIG_V1;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+                errconfig_offs = ERRCONFIG_V2;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+        } else {
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+
+        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+        sr_write_reg(sr, SRCONFIG, sr_config);
+        sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
+                (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+                (sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
+        sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
+                SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+                sr_errconfig);
+
+        /* Enabling the interrupts if the ERROR module is used */
+        sr_modify_reg(sr, errconfig_offs,
+                vpboundint_en, (vpboundint_en | vpboundint_st));
+
+        return 0;
+}
+
+/**
+ * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
+ *                       minmaxavg module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the minmaxavg module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_minmax(struct voltagedomain *voltdm)
+{
+        u32 sr_config, sr_avgwt;
+        u32 senp_en = 0, senn_en = 0;
+        u8 senp_shift, senn_shift;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+
+        if (!sr->clk_length)
+                sr_set_clk_length(sr);
+
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+
+        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                SRCONFIG_SENENABLE |
+                (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_config |= SRCONFIG_DELAYCTRL;
+                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+        } else {
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+
+        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+        sr_write_reg(sr, SRCONFIG, sr_config);
+        sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
+                (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
+        sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
+
+        /*
+         * Enabling the interrupts if MINMAXAVG module is used.
+         * TODO: check if all the interrupts are mandatory
+         */
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_modify_reg(sr, ERRCONFIG_V1,
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+                        ERRCONFIG_MCUBOUNDINTEN),
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+                         ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+                         ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                sr_write_reg(sr, IRQSTATUS,
+                        IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+                        IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+                sr_write_reg(sr, IRQENABLE_SET,
+                        IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+                        IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+        }
+
+        return 0;
+}
+
+/**
+ * sr_enable() - Enables the smartreflex module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ * @volt:       The voltage at which the Voltage domain associated with
+ *              the smartreflex module is operating at.
+ *              This is required only to program the correct Ntarget value.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * enable a smartreflex module. Returns 0 on success. Returns error
+ * value if the voltage passed is wrong or if ntarget value is wrong.
+ */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+{
+        u32 nvalue_reciprocal;
+        struct omap_volt_data *volt_data;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        int ret;
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+
+        volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
+
+        if (IS_ERR(volt_data)) {
+                dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
+                        "for nominal voltage %ld\n", __func__, volt);
+                return -ENODATA;
+        }
+
+        nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
+
+        if (!nvalue_reciprocal) {
+                dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
+                        __func__, volt);
+                return -ENODATA;
+        }
+
+        /* errminlimit is opp dependent and hence linked to voltage */
+        sr->err_minlimit = volt_data->sr_errminlimit;
+
+        pm_runtime_get_sync(&sr->pdev->dev);
+
+        /* Check if SR is already enabled. If yes do nothing */
+        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+                return 0;
+
+        /* Configure SR */
+        ret = sr_class->configure(voltdm);
+        if (ret)
+                return ret;
+
+        sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+
+        /* SRCONFIG - enable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+        return 0;
+}
+
+/**
+ * sr_disable() - Disables the smartreflex module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable a smartreflex module.
+ */
+void sr_disable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        /* Check if SR clocks are already disabled. If yes do nothing */
+        if (pm_runtime_suspended(&sr->pdev->dev))
+                return;
+
+        /*
+         * Disable SR if only it is indeed enabled. Else just
+         * disable the clocks.
+         */
+        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
+                if (sr->ip_type == SR_TYPE_V1)
+                        sr_v1_disable(sr);
+                else if (sr->ip_type == SR_TYPE_V2)
+                        sr_v2_disable(sr);
+        }
+
+        pm_runtime_put_sync(&sr->pdev->dev);
+}
+
+/**
+ * sr_register_class() - API to register a smartreflex class parameters.
+ * @class_data: The structure containing various sr class specific data.
+ *
+ * This API is to be called by the smartreflex class driver to register itself
+ * with the smartreflex driver during init. Returns 0 on success else the
+ * error value.
+ */
+int sr_register_class(struct omap_sr_class_data *class_data)
+{
+        struct omap_sr *sr_info;
+
+        if (!class_data) {
+                pr_warning("%s:, Smartreflex class data passed is NULL\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        if (sr_class) {
+                pr_warning("%s: Smartreflex class driver already registered\n",
+                        __func__);
+                return -EBUSY;
+        }
+
+        sr_class = class_data;
+
+        /*
+         * Call into late init to do intializations that require
+         * both sr driver and sr class driver to be initiallized.
+         */
+        list_for_each_entry(sr_info, &sr_list, node)
+                sr_late_init(sr_info);
+
+        return 0;
+}
+
+/**
+ * omap_sr_enable() -  API to enable SR clocks and to call into the
+ *                      registered smartreflex class enable API.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to enable
+ * a particular smartreflex module. This API will do the initial
+ * configurations to turn on the smartreflex module and in turn call
+ * into the registered smartreflex class enable API.
+ */
+void omap_sr_enable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        if (!sr->autocomp_active)
+                return;
+
+        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+
+        sr_class->enable(voltdm);
+}
+
+/**
+ * omap_sr_disable() - API to disable SR without resetting the voltage
+ *                      processor voltage
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable not to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        if (!sr->autocomp_active)
+                return;
+
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+
+        sr_class->disable(voltdm, 0);
+}
+
+/**
+ * omap_sr_disable_reset_volt() - API to disable SR and reset the
+ *                              voltage processor voltage
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        if (!sr->autocomp_active)
+                return;
+
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+
+        sr_class->disable(voltdm, 1);
+}
+
+/**
+ * omap_sr_register_pmic() - API to register pmic specific info.
+ * @pmic_data:  The structure containing pmic specific data.
+ *
+ * This API is to be called from the PMIC specific code to register with
+ * smartreflex driver pmic specific info. Currently the only info required
+ * is the smartreflex init on the PMIC side.
+ */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
+{
+        if (!pmic_data) {
+                pr_warning("%s: Trying to register NULL PMIC data structure"
+                        "with smartreflex\n", __func__);
+                return;
+        }
+
+        sr_pmic_data = pmic_data;
+}
+
+/* PM Debug Fs enteries to enable disable smartreflex. */
+static int omap_sr_autocomp_show(void *data, u64 *val)
+{
+        struct omap_sr *sr_info = (struct omap_sr *) data;
+
+        if (!sr_info) {
+                pr_warning("%s: omap_sr struct not found\n", __func__);
+                return -EINVAL;
+        }
+
+        *val = sr_info->autocomp_active;
+
+        return 0;
+}
+
+static int omap_sr_autocomp_store(void *data, u64 val)
+{
+        struct omap_sr *sr_info = (struct omap_sr *) data;
+
+        if (!sr_info) {
+                pr_warning("%s: omap_sr struct not found\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Sanity check */
+        if (val && (val != 1)) {
+                pr_warning("%s: Invalid argument %lld\n", __func__, val);
+                return -EINVAL;
+        }
+
+        if (!val)
+                sr_stop_vddautocomp(sr_info);
+        else
+                sr_start_vddautocomp(sr_info);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
+                omap_sr_autocomp_store, "%llu\n");
+
+static int __init omap_sr_probe(struct platform_device *pdev)
+{
+        struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct resource *mem, *irq;
+        struct dentry *vdd_dbg_dir, *nvalue_dir;
+        struct omap_volt_data *volt_data;
+        int i, ret = 0;
+
+        if (!sr_info) {
+                dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                ret = -EINVAL;
+                goto err_free_devinfo;
+        }
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+                ret = -ENODEV;
+                goto err_free_devinfo;
+        }
+
+        mem = request_mem_region(mem->start, resource_size(mem),
+                                        dev_name(&pdev->dev));
+        if (!mem) {
+                dev_err(&pdev->dev, "%s: no mem region\n", __func__);
+                ret = -EBUSY;
+                goto err_free_devinfo;
+        }
+
+        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+        pm_runtime_enable(&pdev->dev);
+
+        sr_info->pdev = pdev;
+        sr_info->srid = pdev->id;
+        sr_info->voltdm = pdata->voltdm;
+        sr_info->nvalue_table = pdata->nvalue_table;
+        sr_info->nvalue_count = pdata->nvalue_count;
+        sr_info->senn_mod = pdata->senn_mod;
+        sr_info->senp_mod = pdata->senp_mod;
+        sr_info->autocomp_active = false;
+        sr_info->ip_type = pdata->ip_type;
+        sr_info->base = ioremap(mem->start, resource_size(mem));
+        if (!sr_info->base) {
+                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+                ret = -ENOMEM;
+                goto err_release_region;
+        }
+
+        if (irq)
+                sr_info->irq = irq->start;
+
+        sr_set_clk_length(sr_info);
+        sr_set_regfields(sr_info);
+
+        list_add(&sr_info->node, &sr_list);
+
+        /*
+         * Call into late init to do intializations that require
+         * both sr driver and sr class driver to be initiallized.
+         */
+        if (sr_class) {
+                ret = sr_late_init(sr_info);
+                if (ret) {
+                        pr_warning("%s: Error in SR late init\n", __func__);
+                        return ret;
+                }
+        }
+
+        dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+
+        /*
+         * If the voltage domain debugfs directory is not created, do
+         * not try to create rest of the debugfs entries.
+         */
+        vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
+        if (!vdd_dbg_dir) {
+                ret = -EINVAL;
+                goto err_iounmap;
+        }
+
+        sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
+        if (IS_ERR(sr_info->dbg_dir)) {
+                dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+                        __func__);
+                ret = PTR_ERR(sr_info->dbg_dir);
+                goto err_iounmap;
+        }
+
+        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
+                        sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
+        (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
+                        &sr_info->err_weight);
+        (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
+                        &sr_info->err_maxlimit);
+        (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
+                        &sr_info->err_minlimit);
+
+        nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
+        if (IS_ERR(nvalue_dir)) {
+                dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+                        "for n-values\n", __func__);
+                ret = PTR_ERR(nvalue_dir);
+                goto err_debugfs;
+        }
+
+        omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
+        if (!volt_data) {
+                dev_warn(&pdev->dev, "%s: No Voltage table for the"
+                        " corresponding vdd vdd_%s. Cannot create debugfs"
+                        "entries for n-values\n",
+                        __func__, sr_info->voltdm->name);
+                ret = -ENODATA;
+                goto err_debugfs;
+        }
+
+        for (i = 0; i < sr_info->nvalue_count; i++) {
+                char name[NVALUE_NAME_LEN + 1];
+
+                snprintf(name, sizeof(name), "volt_%d",
+                         volt_data[i].volt_nominal);
+                (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+                                &(sr_info->nvalue_table[i].nvalue));
+        }
+
+        return ret;
+
+err_debugfs:
+        debugfs_remove_recursive(sr_info->dbg_dir);
+err_iounmap:
+        list_del(&sr_info->node);
+        iounmap(sr_info->base);
+err_release_region:
+        release_mem_region(mem->start, resource_size(mem));
+err_free_devinfo:
+        kfree(sr_info);
+
+        return ret;
+}
+
+static int __devexit omap_sr_remove(struct platform_device *pdev)
+{
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct omap_sr *sr_info;
+        struct resource *mem;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                return -EINVAL;
+        }
+
+        sr_info = _sr_lookup(pdata->voltdm);
+        if (IS_ERR(sr_info)) {
+                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        if (sr_info->autocomp_active)
+                sr_stop_vddautocomp(sr_info);
+        if (sr_info->dbg_dir)
+                debugfs_remove_recursive(sr_info->dbg_dir);
+
+        list_del(&sr_info->node);
+        iounmap(sr_info->base);
+        kfree(sr_info);
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(mem->start, resource_size(mem));
+
+        return 0;
+}
+
+static struct platform_driver smartreflex_driver = {
+        .remove         = omap_sr_remove,
+        .driver         = {
+                .name   = "smartreflex",
+        },
+};
+
+static int __init sr_init(void)
+{
+        int ret = 0;
+
+        /*
+         * sr_init is a late init. If by then a pmic specific API is not
+         * registered either there is no need for anything to be done on
+         * the PMIC side or somebody has forgotten to register a PMIC
+         * handler. Warn for the second condition.
+         */
+        if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
+                sr_pmic_data->sr_pmic_init();
+        else
+                pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
+
+        ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
+        if (ret) {
+                pr_err("%s: platform driver register failed for SR\n",
+                        __func__);
+                return ret;
+        }
+
+        return 0;
+}
+
+static void __exit sr_exit(void)
+{
+        platform_driver_unregister(&smartreflex_driver);
+}
+late_initcall(sr_init);
+module_exit(sr_exit);
+
+MODULE_DESCRIPTION("OMAP Smartreflex Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
new file mode 100644
index 000000000000..5f35b9e25556
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -0,0 +1,246 @@
+/*
+ * OMAP Smartreflex Defines and Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
+#define __ASM_ARM_OMAP_SMARTREFLEX_H
+
+#include <linux/platform_device.h>
+
+#include "voltage.h"
+
+/*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ * OMAP3430. The v2 is the update for the 45nm version of the IP
+ * used in OMAP3630 and OMAP4430
+ */
+#define SR_TYPE_V1      1
+#define SR_TYPE_V2      2
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG                0x00
+#define SRSTATUS                0x04
+#define SENVAL                  0x08
+#define SENMIN                  0x0C
+#define SENMAX                  0x10
+#define SENAVG                  0x14
+#define AVGWEIGHT               0x18
+#define NVALUERECIPROCAL        0x1c
+#define SENERROR_V1             0x20
+#define ERRCONFIG_V1            0x24
+#define IRQ_EOI                 0x20
+#define IRQSTATUS_RAW           0x24
+#define IRQSTATUS               0x28
+#define IRQENABLE_SET           0x2C
+#define IRQENABLE_CLR           0x30
+#define SENERROR_V2             0x34
+#define ERRCONFIG_V2            0x38
+
+/* Bit/Shift Positions */
+
+/* SRCONFIG */
+#define SRCONFIG_ACCUMDATA_SHIFT        22
+#define SRCONFIG_SRCLKLENGTH_SHIFT      12
+#define SRCONFIG_SENNENABLE_V1_SHIFT    5
+#define SRCONFIG_SENPENABLE_V1_SHIFT    3
+#define SRCONFIG_SENNENABLE_V2_SHIFT    1
+#define SRCONFIG_SENPENABLE_V2_SHIFT    0
+#define SRCONFIG_CLKCTRL_SHIFT          0
+
+#define SRCONFIG_ACCUMDATA_MASK         (0x3ff << 22)
+
+#define SRCONFIG_SRENABLE               BIT(11)
+#define SRCONFIG_SENENABLE              BIT(10)
+#define SRCONFIG_ERRGEN_EN              BIT(9)
+#define SRCONFIG_MINMAXAVG_EN           BIT(8)
+#define SRCONFIG_DELAYCTRL              BIT(2)
+
+/* AVGWEIGHT */
+#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT   2
+#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT   0
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
+#define NVALUERECIPROCAL_RNSENP_SHIFT   8
+#define NVALUERECIPROCAL_RNSENN_SHIFT   0
+
+/* ERRCONFIG */
+#define ERRCONFIG_ERRWEIGHT_SHIFT       16
+#define ERRCONFIG_ERRMAXLIMIT_SHIFT     8
+#define ERRCONFIG_ERRMINLIMIT_SHIFT     0
+
+#define SR_ERRWEIGHT_MASK               (0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK             (0xff << 8)
+#define SR_ERRMINLIMIT_MASK             (0xff << 0)
+
+#define ERRCONFIG_VPBOUNDINTEN_V1       BIT(31)
+#define ERRCONFIG_VPBOUNDINTST_V1       BIT(30)
+#define ERRCONFIG_MCUACCUMINTEN         BIT(29)
+#define ERRCONFIG_MCUACCUMINTST         BIT(28)
+#define ERRCONFIG_MCUVALIDINTEN         BIT(27)
+#define ERRCONFIG_MCUVALIDINTST         BIT(26)
+#define ERRCONFIG_MCUBOUNDINTEN         BIT(25)
+#define ERRCONFIG_MCUBOUNDINTST         BIT(24)
+#define ERRCONFIG_MCUDISACKINTEN        BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_V2       BIT(23)
+#define ERRCONFIG_MCUDISACKINTST        BIT(22)
+#define ERRCONFIG_VPBOUNDINTEN_V2       BIT(22)
+
+#define ERRCONFIG_STATUS_V1_MASK        (ERRCONFIG_VPBOUNDINTST_V1 | \
+                                        ERRCONFIG_MCUACCUMINTST | \
+                                        ERRCONFIG_MCUVALIDINTST | \
+                                        ERRCONFIG_MCUBOUNDINTST | \
+                                        ERRCONFIG_MCUDISACKINTST)
+/* IRQSTATUS */
+#define IRQSTATUS_MCUACCUMINT           BIT(3)
+#define IRQSTATUS_MCVALIDINT            BIT(2)
+#define IRQSTATUS_MCBOUNDSINT           BIT(1)
+#define IRQSTATUS_MCUDISABLEACKINT      BIT(0)
+
+/* IRQENABLE_SET and IRQENABLE_CLEAR */
+#define IRQENABLE_MCUACCUMINT           BIT(3)
+#define IRQENABLE_MCUVALIDINT           BIT(2)
+#define IRQENABLE_MCUBOUNDSINT          BIT(1)
+#define IRQENABLE_MCUDISABLEACKINT      BIT(0)
+
+/* Common Bit values */
+
+#define SRCLKLENGTH_12MHZ_SYSCLK        0x3c
+#define SRCLKLENGTH_13MHZ_SYSCLK        0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK        0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK        0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK        0xC0
+
+/*
+ * 3430 specific values. Maybe these should be passed from board file or
+ * pmic structures.
+ */
+#define OMAP3430_SR_ACCUMDATA           0x1f4
+
+#define OMAP3430_SR1_SENPAVGWEIGHT      0x03
+#define OMAP3430_SR1_SENNAVGWEIGHT      0x03
+
+#define OMAP3430_SR2_SENPAVGWEIGHT      0x01
+#define OMAP3430_SR2_SENNAVGWEIGHT      0x01
+
+#define OMAP3430_SR_ERRWEIGHT           0x04
+#define OMAP3430_SR_ERRMAXLIMIT         0x02
+
+/**
+ * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ *                              pmic specific info to smartreflex driver
+ *
+ * @sr_pmic_init:       API to initialize smartreflex on the PMIC side.
+ */
+struct omap_sr_pmic_data {
+        void (*sr_pmic_init) (void);
+};
+
+#ifdef CONFIG_OMAP_SMARTREFLEX
+/*
+ * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ * The smartreflex class driver should pass the class type.
+ * Should be used to populate the class_type field of the
+ * omap_smartreflex_class_data structure.
+ */
+#define SR_CLASS1       0x1
+#define SR_CLASS2       0x2
+#define SR_CLASS3       0x3
+
+/**
+ * struct omap_sr_class_data - Smartreflex class driver info
+ *
+ * @enable:             API to enable a particular class smaartreflex.
+ * @disable:            API to disable a particular class smartreflex.
+ * @configure:          API to configure a particular class smartreflex.
+ * @notify:             API to notify the class driver about an event in SR.
+ *                      Not needed for class3.
+ * @notify_flags:       specify the events to be notified to the class driver
+ * @class_type:         specify which smartreflex class.
+ *                      Can be used by the SR driver to take any class
+ *                      based decisions.
+ */
+struct omap_sr_class_data {
+        int (*enable)(struct voltagedomain *voltdm);
+        int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+        int (*configure)(struct voltagedomain *voltdm);
+        int (*notify)(struct voltagedomain *voltdm, u32 status);
+        u8 notify_flags;
+        u8 class_type;
+};
+
+/**
+ * struct omap_sr_nvalue_table  - Smartreflex n-target value info
+ *
+ * @efuse_offs: The offset of the efuse where n-target values are stored.
+ * @nvalue:     The n-target value.
+ */
+struct omap_sr_nvalue_table {
+        u32 efuse_offs;
+        u32 nvalue;
+};
+
+/**
+ * struct omap_sr_data - Smartreflex platform data.
+ *
+ * @ip_type:            Smartreflex IP type.
+ * @senp_mod:           SENPENABLE value for the sr
+ * @senn_mod:           SENNENABLE value for sr
+ * @nvalue_count:       Number of distinct nvalues in the nvalue table
+ * @enable_on_init:     whether this sr module needs to enabled at
+ *                      boot up or not.
+ * @nvalue_table:       table containing the  efuse offsets and nvalues
+ *                      corresponding to them.
+ * @voltdm:             Pointer to the voltage domain associated with the SR
+ */
+struct omap_sr_data {
+        int                             ip_type;
+        u32                             senp_mod;
+        u32                             senn_mod;
+        int                             nvalue_count;
+        bool                            enable_on_init;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+};
+
+/* Smartreflex module enable/disable interface */
+void omap_sr_enable(struct voltagedomain *voltdm);
+void omap_sr_disable(struct voltagedomain *voltdm);
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+
+/* API to register the pmic specific data with the smartreflex driver. */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+
+/* Smartreflex driver hooks to be called from Smartreflex class driver */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+void sr_disable(struct voltagedomain *voltdm);
+int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_configure_minmax(struct voltagedomain *voltdm);
+
+/* API to register the smartreflex class driver with the smartreflex driver */
+int sr_register_class(struct omap_sr_class_data *class_data);
+#else
+static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable_reset_volt(
+                struct voltagedomain *voltdm) {}
+static inline void omap_sr_register_pmic(
+                struct omap_sr_pmic_data *pmic_data) {}
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
new file mode 100644
index 000000000000..10d3c5ee8018
--- /dev/null
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -0,0 +1,147 @@
+/*
+ * OMAP3/OMAP4 smartreflex device file
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Based originally on code from smartreflex.c
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#include <plat/omap_device.h>
+
+#include "smartreflex.h"
+#include "voltage.h"
+#include "control.h"
+#include "pm.h"
+
+static bool sr_enable_on_init;
+
+static struct omap_device_pm_latency omap_sr_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
+        },
+};
+
+/* Read EFUSE values from control registers for OMAP3430 */
+static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
+                                struct omap_sr_data *sr_data)
+{
+        struct omap_sr_nvalue_table *nvalue_table;
+        int i, count = 0;
+
+        while (volt_data[count].volt_nominal)
+                count++;
+
+        nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
+                        GFP_KERNEL);
+
+        for (i = 0; i < count; i++) {
+                u32 v;
+                /*
+                 * In OMAP4 the efuse registers are 24 bit aligned.
+                 * A __raw_readl will fail for non-32 bit aligned address
+                 * and hence the 8-bit read and shift.
+                 */
+                if (cpu_is_omap44xx()) {
+                        u16 offset = volt_data[i].sr_efuse_offs;
+
+                        v = omap_ctrl_readb(offset) |
+                                omap_ctrl_readb(offset + 1) << 8 |
+                                omap_ctrl_readb(offset + 2) << 16;
+                } else {
+                         v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+                }
+
+                nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
+                nvalue_table[i].nvalue = v;
+        }
+
+        sr_data->nvalue_table = nvalue_table;
+        sr_data->nvalue_count = count;
+}
+
+static int sr_dev_init(struct omap_hwmod *oh, void *user)
+{
+        struct omap_sr_data *sr_data;
+        struct omap_device *od;
+        struct omap_volt_data *volt_data;
+        char *name = "smartreflex";
+        static int i;
+
+        sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
+        if (!sr_data) {
+                pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
+                        __func__, oh->name);
+                return -ENOMEM;
+        }
+
+        if (!oh->vdd_name) {
+                pr_err("%s: No voltage domain specified for %s."
+                        "Cannot initialize\n", __func__, oh->name);
+                goto exit;
+        }
+
+        sr_data->ip_type = oh->class->rev;
+        sr_data->senn_mod = 0x1;
+        sr_data->senp_mod = 0x1;
+
+        sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name);
+        if (IS_ERR(sr_data->voltdm)) {
+                pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
+                        __func__, oh->vdd_name);
+                goto exit;
+        }
+
+        omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
+        if (!volt_data) {
+                pr_warning("%s: No Voltage table registerd fo VDD%d."
+                        "Something really wrong\n\n", __func__, i + 1);
+                goto exit;
+        }
+
+        sr_set_nvalues(volt_data, sr_data);
+
+        sr_data->enable_on_init = sr_enable_on_init;
+
+        od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
+                               omap_sr_latency,
+                               ARRAY_SIZE(omap_sr_latency), 0);
+        if (IS_ERR(od))
+                pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
+                        __func__, name, oh->name);
+exit:
+        i++;
+        kfree(sr_data);
+        return 0;
+}
+
+/*
+ * API to be called from board files to enable smartreflex
+ * autocompensation at init.
+ */
+void __init omap_enable_smartreflex_on_init(void)
+{
+        sr_enable_on_init = true;
+}
+
+int __init omap_devinit_smartreflex(void)
+{
+        return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
+}
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 92e6e1a12af8..ff9b9dbcb30e 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -21,18 +21,25 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
 #include <mach/hardware.h>
 
-#include "prm.h"
-#include "cm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "sdrc.h"
 
         .text
 
+        .align  3
 ENTRY(omap242x_sram_ddr_init)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
 
@@ -137,6 +144,7 @@ ENTRY(omap242x_sram_ddr_init_sz)
  * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
  * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
  */
+        .align  3
 ENTRY(omap242x_sram_reprogram_sdrc)
         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
         mov     r3, #0x0                @ clear for mrc call
@@ -232,6 +240,7 @@ ENTRY(omap242x_sram_reprogram_sdrc_sz)
 /*
  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  */
+        .align  3
 ENTRY(omap242x_sram_set_prcm)
         stmfd   sp!, {r0-r12, lr}       @ regs to stack
         adr     r4, pbegin              @ addr of preload start
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index ab4973695c71..76730209fa0e 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -21,18 +21,25 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
 #include <mach/hardware.h>
 
-#include "prm.h"
-#include "cm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "sdrc.h"
 
         .text
 
+        .align  3
 ENTRY(omap243x_sram_ddr_init)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
 
@@ -137,6 +144,7 @@ ENTRY(omap243x_sram_ddr_init_sz)
  * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
  * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
  */
+        .align  3
 ENTRY(omap243x_sram_reprogram_sdrc)
         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
         mov     r3, #0x0                @ clear for mrc call
@@ -232,6 +240,7 @@ ENTRY(omap243x_sram_reprogram_sdrc_sz)
 /*
  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  */
+        .align  3
 ENTRY(omap243x_sram_set_prcm)
         stmfd   sp!, {r0-r12, lr}       @ regs to stack
         adr     r4, pbegin              @ addr of preload start
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index de99ba2a57ab..6f5849aaa7c0 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -32,7 +32,13 @@
 #include <mach/io.h>
 
 #include "sdrc.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+
+/*
+ * This file needs be built unconditionally as ARM to interoperate correctly
+ * with non-Thumb-2-capable firmware.
+ */
+        .arm
 
         .text
 
@@ -104,33 +110,55 @@
  * touching the SDRAM.  Until that time, users who know that their use case
  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
  * option.
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
+        .align  3
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
 
                                         @ pull the extra args off the stack
                                         @  and store them in SRAM
+
+/*
+ * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
+ * in Thumb-2: use a r7 as a base instead.
+ * Be careful not to clobber r7 when maintaing this file.
+ */
+ THUMB( adr     r7, omap3_sram_configure_core_dpll                      )
+        .macro strtext Rt:req, label:req
+ ARM(   str     \Rt, \label                                             )
+ THUMB( str     \Rt, [r7, \label - omap3_sram_configure_core_dpll]      )
+        .endm
+
         ldr     r4, [sp, #52]
-        str     r4, omap_sdrc_rfr_ctrl_0_val
+        strtext r4, omap_sdrc_rfr_ctrl_0_val
         ldr     r4, [sp, #56]
-        str     r4, omap_sdrc_actim_ctrl_a_0_val
+        strtext r4, omap_sdrc_actim_ctrl_a_0_val
         ldr     r4, [sp, #60]
-        str     r4, omap_sdrc_actim_ctrl_b_0_val
+        strtext r4, omap_sdrc_actim_ctrl_b_0_val
         ldr     r4, [sp, #64]
-        str     r4, omap_sdrc_mr_0_val
+        strtext r4, omap_sdrc_mr_0_val
         ldr     r4, [sp, #68]
-        str     r4, omap_sdrc_rfr_ctrl_1_val
+        strtext r4, omap_sdrc_rfr_ctrl_1_val
         cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
         beq     skip_cs1_params         @  do not use cs1 params
         ldr     r4, [sp, #72]
-        str     r4, omap_sdrc_actim_ctrl_a_1_val
+        strtext r4, omap_sdrc_actim_ctrl_a_1_val
         ldr     r4, [sp, #76]
-        str     r4, omap_sdrc_actim_ctrl_b_1_val
+        strtext r4, omap_sdrc_actim_ctrl_b_1_val
         ldr     r4, [sp, #80]
-        str     r4, omap_sdrc_mr_1_val
+        strtext r4, omap_sdrc_mr_1_val
 skip_cs1_params:
+        mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
+        bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
+        mcr     p15, 0, r10, c1, c0, 0  @ write ctrl register
         dsb                             @ flush buffered writes to interconnect
-
+        isb                             @ prevent speculative exec past here
         cmp     r3, #1                  @ if increasing SDRC clk rate,
         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
         cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
@@ -148,6 +176,7 @@ skip_cs1_params:
         beq     return_to_sdram         @ return to SDRAM code, otherwise,
         bl      configure_sdrc          @ reprogram SDRC regs now
 return_to_sdram:
+        mcr     p15, 0, r8, c1, c0, 0   @ restore ctrl register
         isb                             @ prevent speculative exec past here
         mov     r0, #0                  @ return value
         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
@@ -261,6 +290,7 @@ skip_cs1_prog:
         ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
 
+        .align
 omap3_sdrc_power:
         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 omap3_cm_clksel1_pll:
@@ -309,6 +339,7 @@ omap3_sdrc_dlla_ctrl:
         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 core_m2_mask_val:
         .word 0x07FFFFFF
+ENDPROC(omap3_sram_configure_core_dpll)
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
         .word   . - omap3_sram_configure_core_dpll
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8491f2..3b9cf85f4bb9 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -39,6 +39,12 @@
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
+#include <asm/sched_clock.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
+
+#include "timer-gp.h"
+
 
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
@@ -128,9 +134,13 @@ static void __init omap2_gp_clockevent_init(void)
 {
         u32 tick_rate;
         int src;
+        char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
 
         inited = 1;
 
+        sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
+        omap_hwmod_setup_one(clockevent_hwmod_name);
+
         gptimer = omap_dm_timer_request_specific(gptimer_id);
         BUG_ON(gptimer == NULL);
         gptimer_wakeup = gptimer;
@@ -174,14 +184,19 @@ static void __init omap2_gp_clockevent_init(void)
 /* 
  * When 32k-timer is enabled, don't use GPTimer for clocksource
  * instead, just leave default clocksource which uses the 32k
- * sync counter.  See clocksource setup in see plat-omap/common.c. 
+ * sync counter.  See clocksource setup in plat-omap/counter_32k.c
  */
 
-static inline void __init omap2_gp_clocksource_init(void) {}
+static void __init omap2_gp_clocksource_init(void)
+{
+        omap_init_clocksource_32k();
+}
+
 #else
 /*
  * clocksource
  */
+static DEFINE_CLOCK_DATA(cd);
 static struct omap_dm_timer *gpt_clocksource;
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
@@ -193,15 +208,23 @@ static struct clocksource clocksource_gpt = {
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static void notrace dmtimer_update_sched_clock(void)
+{
+        u32 cyc;
+
+        cyc = omap_dm_timer_read_counter(gpt_clocksource);
+
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
 /* Setup free-running counter for clocksource */
 static void __init omap2_gp_clocksource_init(void)
 {
         static struct omap_dm_timer *gpt;
-        u32 tick_rate, tick_period;
+        u32 tick_rate;
         static char err1[] __initdata = KERN_ERR
                 "%s: failed to request dm-timer\n";
         static char err2[] __initdata = KERN_ERR
@@ -214,13 +237,12 @@ static void __init omap2_gp_clocksource_init(void)
 
         omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
-        tick_period = (tick_rate / HZ) - 1;
 
         omap_dm_timer_set_load_start(gpt, 1, 0);
 
-        clocksource_gpt.mult =
-                clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
-        if (clocksource_register(&clocksource_gpt))
+        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
+
+        if (clocksource_register_hz(&clocksource_gpt, tick_rate))
                 printk(err2, clocksource_gpt.name);
 }
 #endif
@@ -228,8 +250,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-        BUG_ON(!twd_base);
+        if (cpu_is_omap44xx()) {
+                twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+                BUG_ON(!twd_base);
+        }
 #endif
         omap_dm_timer_init();
 
diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
new file mode 100644
index 000000000000..5c1072c6783b
--- /dev/null
+++ b/arch/arm/mach-omap2/timer-gp.h
@@ -0,0 +1,16 @@
+/*
+ * OMAP2/3 GPTIMER support.headers
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
+
+extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
+
+#endif
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 954682e64399..31c0ac4cd66a 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -26,9 +26,14 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+        /* Local timers are not supprted on OMAP4430 ES1.0 */
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+
         evt->irq = OMAP44XX_IRQ_LOCALTIMER;
         twd_timer_setup(evt);
+        return 0;
 }
 
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
deleted file mode 100644
index b11bf385d360..000000000000
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/usb-ehci.c
- *
- * This file will contain the board specific details for the
- * Synopsys EHCI host controller on OMAP3430
- *
- * Copyright (C) 2007 Texas Instruments
- * Author: Vikram Pandita <vikram.pandita@ti.com>
- *
- * Generalization by:
- * Felipe Balbi <felipe.balbi@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/io.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <plat/usb.h>
-
-#include "mux.h"
-
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
-
-static struct resource ehci_resources[] = {
-        {
-                .start  = OMAP34XX_EHCI_BASE,
-                .end    = OMAP34XX_EHCI_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP34XX_UHH_CONFIG_BASE,
-                .end    = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP34XX_USBTLL_BASE,
-                .end    = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {         /* general IRQ */
-                .start   = INT_34XX_EHCI_IRQ,
-                .flags   = IORESOURCE_IRQ,
-        }
-};
-
-static u64 ehci_dmamask = ~(u32)0;
-static struct platform_device ehci_device = {
-        .name           = "ehci-omap",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = NULL,
-        },
-        .num_resources  = ARRAY_SIZE(ehci_resources),
-        .resource       = ehci_resources,
-};
-
-/* MUX settings for EHCI pins */
-/*
- * setup_ehci_io_mux - initialize IO pad mux for USBHOST
- */
-static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode)
-{
-        switch (port_mode[0]) {
-        case EHCI_HCD_OMAP_MODE_PHY:
-                omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case EHCI_HCD_OMAP_MODE_TLL:
-                omap_mux_init_signal("hsusb1_tll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("hsusb1_tll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb1_tll_data7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case EHCI_HCD_OMAP_MODE_UNKNOWN:
-                /* FALLTHROUGH */
-        default:
-                break;
-        }
-
-        switch (port_mode[1]) {
-        case EHCI_HCD_OMAP_MODE_PHY:
-                omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_data7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case EHCI_HCD_OMAP_MODE_TLL:
-                omap_mux_init_signal("hsusb2_tll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("hsusb2_tll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb2_tll_data7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case EHCI_HCD_OMAP_MODE_UNKNOWN:
-                /* FALLTHROUGH */
-        default:
-                break;
-        }
-
-        switch (port_mode[2]) {
-        case EHCI_HCD_OMAP_MODE_PHY:
-                printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
-                break;
-        case EHCI_HCD_OMAP_MODE_TLL:
-                omap_mux_init_signal("hsusb3_tll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("hsusb3_tll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("hsusb3_tll_data7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case EHCI_HCD_OMAP_MODE_UNKNOWN:
-                /* FALLTHROUGH */
-        default:
-                break;
-        }
-
-        return;
-}
-
-void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata)
-{
-        platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
-
-        /* Setup Pin IO MUX for EHCI */
-        if (cpu_is_omap34xx())
-                setup_ehci_io_mux(pdata->port_mode);
-
-        if (platform_device_register(&ehci_device) < 0) {
-                printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
-                return;
-        }
-}
-
-#else
-
-void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata)
-
-{
-}
-
-#endif /* CONFIG_USB_EHCI_HCD */
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
-static struct resource ohci_resources[] = {
-        {
-                .start  = OMAP34XX_OHCI_BASE,
-                .end    = OMAP34XX_OHCI_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP34XX_UHH_CONFIG_BASE,
-                .end    = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP34XX_USBTLL_BASE,
-                .end    = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {       /* general IRQ */
-                .start  = INT_34XX_OHCI_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device ohci_device = {
-        .name           = "ohci-omap3",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &ohci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(ohci_resources),
-        .resource       = ohci_resources,
-};
-
-static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode)
-{
-        switch (port_mode[0]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("mm1_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("mm1_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("mm1_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("mm1_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("mm1_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case OMAP_OHCI_PORT_MODE_UNUSED:
-                /* FALLTHROUGH */
-        default:
-                break;
-        }
-        switch (port_mode[1]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("mm2_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("mm2_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("mm2_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("mm2_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("mm2_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case OMAP_OHCI_PORT_MODE_UNUSED:
-                /* FALLTHROUGH */
-        default:
-                break;
-        }
-        switch (port_mode[2]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("mm3_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("mm3_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("mm3_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
-                /* FALLTHROUGH */
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("mm3_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("mm3_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case OMAP_OHCI_PORT_MODE_UNUSED:
-                /* FALLTHROUGH */
-        default:
-                break;
-        }
-}
-
-void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata)
-{
-        platform_device_add_data(&ohci_device, pdata, sizeof(*pdata));
-
-        /* Setup Pin IO MUX for OHCI */
-        if (cpu_is_omap34xx())
-                setup_ohci_io_mux(pdata->port_mode);
-
-        if (platform_device_register(&ohci_device) < 0) {
-                pr_err("Unable to register FS-USB (OHCI) device\n");
-                return;
-        }
-}
-
-#else
-
-void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata)
-{
-}
-
-#endif /* CONFIG_USB_OHCI_HCD */
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index a216d88b04b5..1481078763b8 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -29,18 +29,18 @@
 
 #include <asm/irq.h>
 
-#include <plat/control.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 
+#include "control.h"
+#include "mux.h"
+
 #define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
 #define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
 #define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
 #define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
 #define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
 
-#include "mux.h"
-
 #if defined(CONFIG_ARCH_OMAP2)
 
 #ifdef  CONFIG_USB_GADGET_OMAP
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
new file mode 100644
index 000000000000..89ae29847c59
--- /dev/null
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -0,0 +1,574 @@
+/*
+ * usb-host.c - OMAP USB Host
+ *
+ * This file will contain the board specific details for the
+ * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
+ *
+ * Copyright (C) 2007-2011 Texas Instruments
+ * Author: Vikram Pandita <vikram.pandita@ti.com>
+ * Author: Keshava Munegowda <keshava_mgowda@ti.com>
+ *
+ * Generalization by:
+ * Felipe Balbi <balbi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <plat/usb.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_MFD_OMAP_USB_HOST
+
+#define OMAP_USBHS_DEVICE       "usbhs-omap"
+
+static struct resource usbhs_resources[] = {
+        {
+                .name   = "uhh",
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "tll",
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ehci",
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ehci-irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "ohci",
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ohci-irq",
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device usbhs_device = {
+        .name           = OMAP_USBHS_DEVICE,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(usbhs_resources),
+        .resource       = usbhs_resources,
+};
+
+static struct usbhs_omap_platform_data          usbhs_data;
+static struct ehci_hcd_omap_platform_data       ehci_data;
+static struct ohci_hcd_omap_platform_data       ohci_data;
+
+/* MUX settings for EHCI pins */
+/*
+ * setup_ehci_io_mux - initialize IO pad mux for USBHOST
+ */
+static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+{
+        switch (port_mode[0]) {
+        case OMAP_EHCI_PORT_MODE_PHY:
+                omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_EHCI_PORT_MODE_TLL:
+                omap_mux_init_signal("hsusb1_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb1_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+                /* FALLTHROUGH */
+        default:
+                break;
+        }
+
+        switch (port_mode[1]) {
+        case OMAP_EHCI_PORT_MODE_PHY:
+                omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_EHCI_PORT_MODE_TLL:
+                omap_mux_init_signal("hsusb2_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb2_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+                /* FALLTHROUGH */
+        default:
+                break;
+        }
+
+        switch (port_mode[2]) {
+        case OMAP_EHCI_PORT_MODE_PHY:
+                printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
+                break;
+        case OMAP_EHCI_PORT_MODE_TLL:
+                omap_mux_init_signal("hsusb3_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb3_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+                /* FALLTHROUGH */
+        default:
+                break;
+        }
+
+        return;
+}
+
+static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+{
+        switch (port_mode[0]) {
+        case OMAP_EHCI_PORT_MODE_PHY:
+                omap_mux_init_signal("usbb1_ulpiphy_stp",
+                        OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("usbb1_ulpiphy_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case OMAP_EHCI_PORT_MODE_TLL:
+                omap_mux_init_signal("usbb1_ulpitll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("usbb1_ulpitll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+        default:
+                        break;
+        }
+        switch (port_mode[1]) {
+        case OMAP_EHCI_PORT_MODE_PHY:
+                omap_mux_init_signal("usbb2_ulpiphy_stp",
+                        OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("usbb2_ulpiphy_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case OMAP_EHCI_PORT_MODE_TLL:
+                omap_mux_init_signal("usbb2_ulpitll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("usbb2_ulpitll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+        default:
+                        break;
+        }
+}
+
+static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+{
+        switch (port_mode[0]) {
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+                omap_mux_init_signal("mm1_rxdp",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("mm1_rxdm",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+                omap_mux_init_signal("mm1_rxrcv",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+                omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+                omap_mux_init_signal("mm1_txse0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("mm1_txdat",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+                /* FALLTHROUGH */
+        default:
+                break;
+        }
+        switch (port_mode[1]) {
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+                omap_mux_init_signal("mm2_rxdp",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("mm2_rxdm",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+                omap_mux_init_signal("mm2_rxrcv",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+                omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+                omap_mux_init_signal("mm2_txse0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("mm2_txdat",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+                /* FALLTHROUGH */
+        default:
+                break;
+        }
+        switch (port_mode[2]) {
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+                omap_mux_init_signal("mm3_rxdp",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("mm3_rxdm",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+                omap_mux_init_signal("mm3_rxrcv",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+                omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
+                /* FALLTHROUGH */
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+                omap_mux_init_signal("mm3_txse0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("mm3_txdat",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+                /* FALLTHROUGH */
+        default:
+                break;
+        }
+}
+
+static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+{
+        switch (port_mode[0]) {
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+                omap_mux_init_signal("usbb1_mm_rxdp",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_mm_rxdm",
+                        OMAP_PIN_INPUT_PULLDOWN);
+
+        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+                omap_mux_init_signal("usbb1_mm_rxrcv",
+                        OMAP_PIN_INPUT_PULLDOWN);
+
+        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+                omap_mux_init_signal("usbb1_mm_txen",
+                        OMAP_PIN_INPUT_PULLDOWN);
+
+
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+                omap_mux_init_signal("usbb1_mm_txdat",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_mm_txse0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+        default:
+                break;
+        }
+
+        switch (port_mode[1]) {
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+                omap_mux_init_signal("usbb2_mm_rxdp",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_mm_rxdm",
+                        OMAP_PIN_INPUT_PULLDOWN);
+
+        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+                omap_mux_init_signal("usbb2_mm_rxrcv",
+                        OMAP_PIN_INPUT_PULLDOWN);
+
+        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+                omap_mux_init_signal("usbb2_mm_txen",
+                        OMAP_PIN_INPUT_PULLDOWN);
+
+
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+                omap_mux_init_signal("usbb2_mm_txdat",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_mm_txse0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                break;
+
+        case OMAP_USBHS_PORT_MODE_UNUSED:
+        default:
+                break;
+        }
+}
+
+void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
+{
+        int     i;
+
+        for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
+                usbhs_data.port_mode[i] = pdata->port_mode[i];
+                ohci_data.port_mode[i] = pdata->port_mode[i];
+                ehci_data.port_mode[i] = pdata->port_mode[i];
+                ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
+                ehci_data.regulator[i] = pdata->regulator[i];
+        }
+        ehci_data.phy_reset = pdata->phy_reset;
+        ohci_data.es2_compatibility = pdata->es2_compatibility;
+        usbhs_data.ehci_data = &ehci_data;
+        usbhs_data.ohci_data = &ohci_data;
+
+        if (cpu_is_omap34xx()) {
+                usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE;
+                usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1;
+                usbhs_resources[1].start = OMAP34XX_USBTLL_BASE;
+                usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1;
+                usbhs_resources[2].start        = OMAP34XX_EHCI_BASE;
+                usbhs_resources[2].end  = OMAP34XX_EHCI_BASE + SZ_1K - 1;
+                usbhs_resources[3].start = INT_34XX_EHCI_IRQ;
+                usbhs_resources[4].start        = OMAP34XX_OHCI_BASE;
+                usbhs_resources[4].end  = OMAP34XX_OHCI_BASE + SZ_1K - 1;
+                usbhs_resources[5].start = INT_34XX_OHCI_IRQ;
+                setup_ehci_io_mux(pdata->port_mode);
+                setup_ohci_io_mux(pdata->port_mode);
+        } else if (cpu_is_omap44xx()) {
+                usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE;
+                usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1;
+                usbhs_resources[1].start = OMAP44XX_USBTLL_BASE;
+                usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1;
+                usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE;
+                usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1;
+                usbhs_resources[3].start = OMAP44XX_IRQ_EHCI;
+                usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE;
+                usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1;
+                usbhs_resources[5].start = OMAP44XX_IRQ_OHCI;
+                setup_4430ehci_io_mux(pdata->port_mode);
+                setup_4430ohci_io_mux(pdata->port_mode);
+        }
+
+        if (platform_device_add_data(&usbhs_device,
+                                &usbhs_data, sizeof(usbhs_data)) < 0) {
+                printk(KERN_ERR "USBHS platform_device_add_data failed\n");
+                goto init_end;
+        }
+
+        if (platform_device_register(&usbhs_device) < 0)
+                printk(KERN_ERR "USBHS platform_device_register failed\n");
+
+init_end:
+        return;
+}
+
+#else
+
+void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
+{
+}
+
+#endif
+
+
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 33a5cde1c227..c7ed540d868d 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,23 +28,12 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/am35xx.h>
 #include <plat/usb.h>
+#include <plat/omap_device.h>
+#include "mux.h"
 
-#ifdef CONFIG_USB_MUSB_SOC
-
-static struct resource musb_resources[] = {
-        [0] = { /* start and end set dynamically */
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = { /* general IRQ */
-                .start  = INT_243X_HS_USB_MC,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = { /* DMA IRQ */
-                .start  = INT_243X_HS_USB_DMA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
+#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
 
 static struct musb_hdrc_config musb_config = {
         .multipoint     = 1,
@@ -73,30 +62,72 @@ static struct musb_hdrc_platform_data musb_plat = {
 
 static u64 musb_dmamask = DMA_BIT_MASK(32);
 
-static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
-        .id             = -1,
-        .dev = {
-                .dma_mask               = &musb_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &musb_plat,
+static struct omap_device_pm_latency omap_musb_latency[] = {
+        {
+                .deactivate_func        = omap_device_idle_hwmods,
+                .activate_func          = omap_device_enable_hwmods,
+                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
-        .num_resources  = ARRAY_SIZE(musb_resources),
-        .resource       = musb_resources,
 };
 
-void __init usb_musb_init(struct omap_musb_board_data *board_data)
+static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
 {
-        if (cpu_is_omap243x()) {
-                musb_resources[0].start = OMAP243X_HS_BASE;
-        } else if (cpu_is_omap34xx()) {
-                musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
-        } else if (cpu_is_omap44xx()) {
-                musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
-                musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
-                musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
+        switch (board_data->interface_type) {
+        case MUSB_INTERFACE_UTMI:
+                omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT);
+                omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT);
+                break;
+        case MUSB_INTERFACE_ULPI:
+                omap_mux_init_signal("usba0_ulpiphy_clk",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_stp",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dir",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_nxt",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat0",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat1",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat2",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat3",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat4",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat5",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat6",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat7",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        default:
+                break;
         }
-        musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
+}
+
+static struct omap_musb_board_data musb_default_board_data = {
+        .interface_type         = MUSB_INTERFACE_ULPI,
+        .mode                   = MUSB_OTG,
+        .power                  = 100,
+};
+
+void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
+{
+        struct omap_hwmod               *oh;
+        struct omap_device              *od;
+        struct platform_device          *pdev;
+        struct device                   *dev;
+        int                             bus_id = -1;
+        const char                      *oh_name, *name;
+        struct omap_musb_board_data     *board_data;
+
+        if (musb_board_data)
+                board_data = musb_board_data;
+        else
+                board_data = &musb_default_board_data;
 
         /*
          * REVISIT: This line can be removed once all the platforms using
@@ -108,12 +139,47 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
         musb_plat.mode = board_data->mode;
         musb_plat.extvbus = board_data->extvbus;
 
-        if (platform_device_register(&musb_device) < 0)
-                printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
+        if (cpu_is_omap44xx())
+                omap4430_phy_init(dev);
+
+        if (cpu_is_omap3517() || cpu_is_omap3505()) {
+                oh_name = "am35x_otg_hs";
+                name = "musb-am35x";
+        } else {
+                oh_name = "usb_otg_hs";
+                name = "musb-omap2430";
+        }
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return;
+        }
+
+        od = omap_device_build(name, bus_id, oh, &musb_plat,
+                               sizeof(musb_plat), omap_musb_latency,
+                               ARRAY_SIZE(omap_musb_latency), false);
+        if (IS_ERR(od)) {
+                pr_err("Could not build omap_device for %s %s\n",
+                                                name, oh_name);
+                return;
+        }
+
+        pdev = &od->pdev;
+        dev = &pdev->dev;
+        get_device(dev);
+        dev->dma_mask = &musb_dmamask;
+        dev->coherent_dma_mask = musb_dmamask;
+        put_device(dev);
+
+        if (cpu_is_omap44xx())
+                omap4430_phy_init(dev);
 }
 
 #else
 void __init usb_musb_init(struct omap_musb_board_data *board_data)
 {
+        if (cpu_is_omap44xx())
+                omap4430_phy_init(NULL);
 }
 #endif /* CONFIG_USB_MUSB_SOC */
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 64a0112b70a5..8dd26b765b7d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -120,8 +120,8 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
         t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps);
 
         /* GPMC_CLK rate = fclk rate / div */
-        t.sync_clk = 12 /* 11.1 nsec */;
-        tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps;
+        t.sync_clk = 11100 /* 11.1 nsec */;
+        tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
         if (tmp > 4)
                 return -ERANGE;
         if (tmp <= 0)
@@ -216,6 +216,7 @@ static struct resource tusb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         { /* IRQ */
+                .name   = "mc",
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -223,7 +224,7 @@ static struct resource tusb_resources[] = {
 static u64 tusb_dmamask = ~(u32)0;
 
 static struct platform_device tusb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-tusb",
         .id             = -1,
         .dev = {
                 .dma_mask               = &tusb_dmamask,
@@ -292,12 +293,11 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                         );
 
         /* IRQ */
-        status = gpio_request(irq, "TUSB6010 irq");
+        status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
         if (status < 0) {
                 printk(error, 3, status);
                 return status;
         }
-        gpio_direction_input(irq);
         tusb_resources[2].start = irq + IH_GPIO_BASE;
 
         /* set up memory timings ... can speed them up later */
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
new file mode 100644
index 000000000000..e7767771de49
--- /dev/null
+++ b/arch/arm/mach-omap2/vc.h
@@ -0,0 +1,83 @@
+/*
+ * OMAP3/4 Voltage Controller (VC) structure and macro definitions
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_VC_H
+#define __ARCH_ARM_MACH_OMAP2_VC_H
+
+#include <linux/kernel.h>
+
+/**
+ * struct omap_vc_common_data - per-VC register/bitfield data
+ * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
+ * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
+ * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
+ * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
+ * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
+ * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
+ * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
+ * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
+ * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
+ * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
+ * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
+ * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
+ *
+ * XXX One of cmd_on_mask and cmd_on_shift are not needed
+ * XXX VALID should probably be a shift, not a mask
+ */
+struct omap_vc_common_data {
+        u32 cmd_on_mask;
+        u32 valid;
+        u8 smps_sa_reg;
+        u8 smps_volra_reg;
+        u8 bypass_val_reg;
+        u8 data_shift;
+        u8 slaveaddr_shift;
+        u8 regaddr_shift;
+        u8 cmd_on_shift;
+        u8 cmd_onlp_shift;
+        u8 cmd_ret_shift;
+        u8 cmd_off_shift;
+};
+
+/**
+ * struct omap_vc_instance_data - VC per-instance data
+ * @vc_common: pointer to VC common data for this platform
+ * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register
+ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+ * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register
+ * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register
+ *
+ * XXX It is not necessary to have both a *_mask and a *_shift -
+ *     remove one
+ */
+struct omap_vc_instance_data {
+        const struct omap_vc_common_data *vc_common;
+        u32 smps_sa_mask;
+        u32 smps_volra_mask;
+        u8 cmdval_reg;
+        u8 smps_sa_shift;
+        u8 smps_volra_shift;
+};
+
+extern struct omap_vc_instance_data omap3_vc1_data;
+extern struct omap_vc_instance_data omap3_vc2_data;
+
+extern struct omap_vc_instance_data omap4_vc_mpu_data;
+extern struct omap_vc_instance_data omap4_vc_iva_data;
+extern struct omap_vc_instance_data omap4_vc_core_data;
+
+#endif
+
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
new file mode 100644
index 000000000000..f37dc4bc379a
--- /dev/null
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -0,0 +1,63 @@
+/*
+ * OMAP3 Voltage Controller (VC) data
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <plat/common.h>
+
+#include "prm-regbits-34xx.h"
+#include "voltage.h"
+
+#include "vc.h"
+
+/*
+ * VC data common to 34xx/36xx chips
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+static struct omap_vc_common_data omap3_vc_common = {
+        .smps_sa_reg     = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg  = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+        .bypass_val_reg  = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
+        .data_shift      = OMAP3430_DATA_SHIFT,
+        .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
+        .regaddr_shift   = OMAP3430_REGADDR_SHIFT,
+        .valid           = OMAP3430_VALID_MASK,
+        .cmd_on_shift    = OMAP3430_VC_CMD_ON_SHIFT,
+        .cmd_on_mask     = OMAP3430_VC_CMD_ON_MASK,
+        .cmd_onlp_shift  = OMAP3430_VC_CMD_ONLP_SHIFT,
+        .cmd_ret_shift   = OMAP3430_VC_CMD_RET_SHIFT,
+        .cmd_off_shift   = OMAP3430_VC_CMD_OFF_SHIFT,
+};
+
+struct omap_vc_instance_data omap3_vc1_data = {
+        .vc_common = &omap3_vc_common,
+        .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
+        .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
+        .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
+        .smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
+        .smps_volra_mask = OMAP3430_VOLRA0_MASK,
+};
+
+struct omap_vc_instance_data omap3_vc2_data = {
+        .vc_common = &omap3_vc_common,
+        .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
+        .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
+        .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
+        .smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
+        .smps_volra_mask = OMAP3430_VOLRA1_MASK,
+};
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
new file mode 100644
index 000000000000..a98da8ddec52
--- /dev/null
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -0,0 +1,75 @@
+/*
+ * OMAP4 Voltage Controller (VC) data
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <plat/common.h>
+
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#include "voltage.h"
+
+#include "vc.h"
+
+/*
+ * VC data common to 44xx chips
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+static const struct omap_vc_common_data omap4_vc_common = {
+        .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+        .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+        .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
+        .data_shift = OMAP4430_DATA_SHIFT,
+        .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
+        .regaddr_shift = OMAP4430_REGADDR_SHIFT,
+        .valid = OMAP4430_VALID_MASK,
+        .cmd_on_shift = OMAP4430_ON_SHIFT,
+        .cmd_on_mask = OMAP4430_ON_MASK,
+        .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
+        .cmd_ret_shift = OMAP4430_RET_SHIFT,
+        .cmd_off_shift = OMAP4430_OFF_SHIFT,
+};
+
+/* VC instance data for each controllable voltage line */
+struct omap_vc_instance_data omap4_vc_mpu_data = {
+        .vc_common = &omap4_vc_common,
+        .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
+        .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT,
+        .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
+        .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT,
+        .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
+};
+
+struct omap_vc_instance_data omap4_vc_iva_data = {
+        .vc_common = &omap4_vc_common,
+        .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
+        .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT,
+        .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
+        .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT,
+        .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
+};
+
+struct omap_vc_instance_data omap4_vc_core_data = {
+        .vc_common = &omap4_vc_common,
+        .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
+        .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
+        .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
+        .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
+        .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
+};
+
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
new file mode 100644
index 000000000000..9ef3789ded4b
--- /dev/null
+++ b/arch/arm/mach-omap2/voltage.c
@@ -0,0 +1,1106 @@
+/*
+ * OMAP3/OMAP4 Voltage Management Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+
+#include <plat/common.h>
+
+#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm44xx.h"
+#include "prminst44xx.h"
+#include "control.h"
+
+#include "voltage.h"
+
+#include "vc.h"
+#include "vp.h"
+
+#define VOLTAGE_DIR_SIZE        16
+
+
+static struct omap_vdd_info **vdd_info;
+
+/*
+ * Number of scalable voltage domains.
+ */
+static int nr_scalable_vdd;
+
+/* XXX document */
+static s16 prm_mod_offs;
+static s16 prm_irqst_ocp_mod_offs;
+
+static struct dentry *voltage_dir;
+
+/* Init function pointers */
+static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+                                        unsigned long target_volt);
+
+static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
+{
+        return omap2_prm_read_mod_reg(mod, offset);
+}
+
+static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset)
+{
+        omap2_prm_write_mod_reg(val, mod, offset);
+}
+
+static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
+{
+        return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                        mod, offset);
+}
+
+static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
+{
+        omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
+}
+
+static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
+{
+        char *sys_ck_name;
+        struct clk *sys_ck;
+        u32 sys_clk_speed, timeout_val, waittime;
+
+        /*
+         * XXX Clockfw should handle this, or this should be in a
+         * struct record
+         */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                sys_ck_name = "sys_ck";
+        else if (cpu_is_omap44xx())
+                sys_ck_name = "sys_clkin_ck";
+        else
+                return -EINVAL;
+
+        /*
+         * Sys clk rate is require to calculate vp timeout value and
+         * smpswaittimemin and smpswaittimemax.
+         */
+        sys_ck = clk_get(NULL, sys_ck_name);
+        if (IS_ERR(sys_ck)) {
+                pr_warning("%s: Could not get the sys clk to calculate"
+                        "various vdd_%s params\n", __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+        sys_clk_speed = clk_get_rate(sys_ck);
+        clk_put(sys_ck);
+        /* Divide to avoid overflow */
+        sys_clk_speed /= 1000;
+
+        /* Generic voltage parameters */
+        vdd->volt_scale = vp_forceupdate_scale_voltage;
+        vdd->vp_enabled = false;
+
+        vdd->vp_rt_data.vpconfig_erroroffset =
+                (vdd->pmic_info->vp_erroroffset <<
+                 vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
+
+        timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
+        vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+        vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+        vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
+
+        waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
+                                sys_clk_speed) / 1000;
+        vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
+        vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
+        vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+        vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
+
+        return 0;
+}
+
+/* Voltage debugfs support */
+static int vp_volt_debug_get(void *data, u64 *val)
+{
+        struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+        u8 vsel;
+
+        if (!vdd) {
+                pr_warning("Wrong paramater passed\n");
+                return -EINVAL;
+        }
+
+        vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
+
+        if (!vdd->pmic_info->vsel_to_uv) {
+                pr_warning("PMIC function to convert vsel to voltage"
+                        "in uV not registerd\n");
+                return -EINVAL;
+        }
+
+        *val = vdd->pmic_info->vsel_to_uv(vsel);
+        return 0;
+}
+
+static int nom_volt_debug_get(void *data, u64 *val)
+{
+        struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+
+        if (!vdd) {
+                pr_warning("Wrong paramater passed\n");
+                return -EINVAL;
+        }
+
+        *val = omap_voltage_get_nom_volt(&vdd->voltdm);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
+                                                                "%llu\n");
+static void vp_latch_vsel(struct omap_vdd_info *vdd)
+{
+        u32 vpconfig;
+        unsigned long uvdc;
+        char vsel;
+
+        uvdc = omap_voltage_get_nom_volt(&vdd->voltdm);
+        if (!uvdc) {
+                pr_warning("%s: unable to find current voltage for vdd_%s\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+                pr_warning("%s: PMIC function to convert voltage in uV to"
+                        " vsel not registered\n", __func__);
+                return;
+        }
+
+        vsel = vdd->pmic_info->uv_to_vsel(uvdc);
+
+        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
+        vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
+                        vdd->vp_data->vp_common->vpconfig_initvdd);
+        vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
+
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        /* Trigger initVDD value copy to voltage processor */
+        vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
+                       prm_mod_offs, vdd->vp_data->vpconfig);
+
+        /* Clear initVDD copy trigger bit */
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+}
+
+/* Generic voltage init functions */
+static void __init vp_init(struct omap_vdd_info *vdd)
+{
+        u32 vp_val;
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
+                (vdd->vp_rt_data.vpconfig_errorgain <<
+                vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
+                vdd->vp_data->vp_common->vpconfig_timeouten;
+        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+                vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
+                (vdd->vp_rt_data.vstepmin_stepmin <<
+                vdd->vp_data->vp_common->vstepmin_stepmin_shift));
+        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin);
+
+        vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+                vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
+                (vdd->vp_rt_data.vstepmax_stepmax <<
+                vdd->vp_data->vp_common->vstepmax_stepmax_shift));
+        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax);
+
+        vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+                vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
+                (vdd->vp_rt_data.vlimitto_vddmin <<
+                vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
+                (vdd->vp_rt_data.vlimitto_timeout <<
+                vdd->vp_data->vp_common->vlimitto_timeout_shift));
+        vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto);
+}
+
+static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+{
+        char *name;
+
+        name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL);
+        if (!name) {
+                pr_warning("%s: Unable to allocate memory for debugfs"
+                        " directory name for vdd_%s",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+        strcpy(name, "vdd_");
+        strcat(name, vdd->voltdm.name);
+
+        vdd->debug_dir = debugfs_create_dir(name, voltage_dir);
+        kfree(name);
+        if (IS_ERR(vdd->debug_dir)) {
+                pr_warning("%s: Unable to create debugfs directory for"
+                        " vdd_%s\n", __func__, vdd->voltdm.name);
+                vdd->debug_dir = NULL;
+                return;
+        }
+
+        (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_rt_data.vpconfig_errorgain));
+        (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
+                                vdd->debug_dir,
+                                &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
+        (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_rt_data.vstepmin_stepmin));
+        (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
+                                vdd->debug_dir,
+                                &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
+        (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_rt_data.vstepmax_stepmax));
+        (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_rt_data.vlimitto_vddmax));
+        (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_rt_data.vlimitto_vddmin));
+        (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_rt_data.vlimitto_timeout));
+        (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
+                                (void *) vdd, &vp_volt_debug_fops);
+        (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
+                                vdd->debug_dir, (void *) vdd,
+                                &nom_volt_debug_fops);
+}
+
+/* Voltage scale and accessory APIs */
+static int _pre_volt_scale(struct omap_vdd_info *vdd,
+                unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
+{
+        struct omap_volt_data *volt_data;
+        const struct omap_vc_common_data *vc_common;
+        const struct omap_vp_common_data *vp_common;
+        u32 vc_cmdval, vp_errgain_val;
+
+        vc_common = vdd->vc_data->vc_common;
+        vp_common = vdd->vp_data->vp_common;
+
+        /* Check if suffiecient pmic info is available for this vdd */
+        if (!vdd->pmic_info) {
+                pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+                        __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        if (!vdd->pmic_info->uv_to_vsel) {
+                pr_err("%s: PMIC function to convert voltage in uV to"
+                        "vsel not registered. Hence unable to scale voltage"
+                        "for vdd_%s\n", __func__, vdd->voltdm.name);
+                return -ENODATA;
+        }
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        /* Get volt_data corresponding to target_volt */
+        volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
+        if (IS_ERR(volt_data))
+                volt_data = NULL;
+
+        *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
+        *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
+
+        /* Setting the ON voltage to the new target voltage */
+        vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg);
+        vc_cmdval &= ~vc_common->cmd_on_mask;
+        vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
+        vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg);
+
+        /* Setting vp errorgain based on the voltage */
+        if (volt_data) {
+                vp_errgain_val = vdd->read_reg(prm_mod_offs,
+                                               vdd->vp_data->vpconfig);
+                vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+                vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
+                vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+                        vp_common->vpconfig_errorgain_shift;
+                vdd->write_reg(vp_errgain_val, prm_mod_offs,
+                               vdd->vp_data->vpconfig);
+        }
+
+        return 0;
+}
+
+static void _post_volt_scale(struct omap_vdd_info *vdd,
+                unsigned long target_volt, u8 target_vsel, u8 current_vsel)
+{
+        u32 smps_steps = 0, smps_delay = 0;
+
+        smps_steps = abs(target_vsel - current_vsel);
+        /* SMPS slew rate / step size. 2us added as buffer. */
+        smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
+                        vdd->pmic_info->slew_rate) + 2;
+        udelay(smps_delay);
+
+        vdd->curr_volt = target_volt;
+}
+
+/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
+static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+                unsigned long target_volt)
+{
+        u32 loop_cnt = 0, retries_cnt = 0;
+        u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+        u8 target_vsel, current_vsel;
+        int ret;
+
+        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
+        if (ret)
+                return ret;
+
+        vc_valid = vdd->vc_data->vc_common->valid;
+        vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg;
+        vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) |
+                        (vdd->pmic_info->pmic_reg <<
+                        vdd->vc_data->vc_common->regaddr_shift) |
+                        (vdd->pmic_info->i2c_slave_addr <<
+                        vdd->vc_data->vc_common->slaveaddr_shift);
+
+        vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg);
+        vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs,
+                       vc_bypass_val_reg);
+
+        vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg);
+        /*
+         * Loop till the bypass command is acknowledged from the SMPS.
+         * NOTE: This is legacy code. The loop count and retry count needs
+         * to be revisited.
+         */
+        while (!(vc_bypass_value & vc_valid)) {
+                loop_cnt++;
+
+                if (retries_cnt > 10) {
+                        pr_warning("%s: Retry count exceeded\n", __func__);
+                        return -ETIMEDOUT;
+                }
+
+                if (loop_cnt > 50) {
+                        retries_cnt++;
+                        loop_cnt = 0;
+                        udelay(10);
+                }
+                vc_bypass_value = vdd->read_reg(prm_mod_offs,
+                                                vc_bypass_val_reg);
+        }
+
+        _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
+        return 0;
+}
+
+/* VP force update method of voltage scaling */
+static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+                unsigned long target_volt)
+{
+        u32 vpconfig;
+        u8 target_vsel, current_vsel, prm_irqst_reg;
+        int ret, timeout = 0;
+
+        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
+        if (ret)
+                return ret;
+
+        prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
+
+        /*
+         * Clear all pending TransactionDone interrupt/status. Typical latency
+         * is <3us
+         */
+        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+                vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+                               prm_irqst_ocp_mod_offs, prm_irqst_reg);
+                if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
+                      vdd->vp_data->prm_irqst_data->tranxdone_status))
+                        break;
+                udelay(1);
+        }
+        if (timeout >= VP_TRANXDONE_TIMEOUT) {
+                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+                        "Voltage change aborted", __func__, vdd->voltdm.name);
+                return -ETIMEDOUT;
+        }
+
+        /* Configure for VP-Force Update */
+        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
+        vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
+                        vdd->vp_data->vp_common->vpconfig_forceupdate |
+                        vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
+        vpconfig |= ((target_vsel <<
+                        vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        /* Trigger initVDD value copy to voltage processor */
+        vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        /* Force update of voltage */
+        vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        /*
+         * Wait for TransactionDone. Typical latency is <200us.
+         * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+         */
+        timeout = 0;
+        omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
+                           vdd->vp_data->prm_irqst_data->tranxdone_status),
+                          VP_TRANXDONE_TIMEOUT, timeout);
+        if (timeout >= VP_TRANXDONE_TIMEOUT)
+                pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+                        "TRANXDONE never got set after the voltage update\n",
+                        __func__, vdd->voltdm.name);
+
+        _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
+
+        /*
+         * Disable TransactionDone interrupt , clear all status, clear
+         * control registers
+         */
+        timeout = 0;
+        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+                vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+                               prm_irqst_ocp_mod_offs, prm_irqst_reg);
+                if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
+                      vdd->vp_data->prm_irqst_data->tranxdone_status))
+                        break;
+                udelay(1);
+        }
+
+        if (timeout >= VP_TRANXDONE_TIMEOUT)
+                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+                        "to clear the TRANXDONE status\n",
+                        __func__, vdd->voltdm.name);
+
+        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
+        /* Clear initVDD copy trigger bit */
+        vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+        /* Clear force bit */
+        vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        return 0;
+}
+
+static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
+{
+        /*
+         * Voltage Manager FSM parameters init
+         * XXX This data should be passed in from the board file
+         */
+        vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET);
+        vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs,
+                       OMAP3_PRM_VOLTOFFSET_OFFSET);
+        vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs,
+                       OMAP3_PRM_VOLTSETUP2_OFFSET);
+}
+
+static void __init omap3_vc_init(struct omap_vdd_info *vdd)
+{
+        static bool is_initialized;
+        u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+        u32 vc_val;
+
+        if (is_initialized)
+                return;
+
+        /* Set up the on, inactive, retention and off voltage */
+        on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+        onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+        ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+        off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
+        vc_val  = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) |
+                (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
+                (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
+                (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
+        vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg);
+
+        /*
+         * Generic VC parameters init
+         * XXX This data should be abstracted out
+         */
+        vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs,
+                        OMAP3_PRM_VC_CH_CONF_OFFSET);
+        vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs,
+                        OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+        omap3_vfsm_init(vdd);
+
+        is_initialized = true;
+}
+
+
+/* OMAP4 specific voltage init functions */
+static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+{
+        static bool is_initialized;
+        u32 vc_val;
+
+        if (is_initialized)
+                return;
+
+        /* TODO: Configure setup times and CMD_VAL values*/
+
+        /*
+         * Generic VC parameters init
+         * XXX This data should be abstracted out
+         */
+        vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+                  OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+                  OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+        vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+        /* XXX These are magic numbers and do not belong! */
+        vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+        vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+        is_initialized = true;
+}
+
+static void __init omap_vc_init(struct omap_vdd_info *vdd)
+{
+        u32 vc_val;
+
+        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+                pr_err("%s: PMIC info requried to configure vc for"
+                        "vdd_%s not populated.Hence cannot initialize vc\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        /* Set up the SMPS_SA(i2c slave address in VC */
+        vc_val = vdd->read_reg(prm_mod_offs,
+                               vdd->vc_data->vc_common->smps_sa_reg);
+        vc_val &= ~vdd->vc_data->smps_sa_mask;
+        vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
+        vdd->write_reg(vc_val, prm_mod_offs,
+                       vdd->vc_data->vc_common->smps_sa_reg);
+
+        /* Setup the VOLRA(pmic reg addr) in VC */
+        vc_val = vdd->read_reg(prm_mod_offs,
+                               vdd->vc_data->vc_common->smps_volra_reg);
+        vc_val &= ~vdd->vc_data->smps_volra_mask;
+        vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
+        vdd->write_reg(vc_val, prm_mod_offs,
+                       vdd->vc_data->vc_common->smps_volra_reg);
+
+        /* Configure the setup times */
+        vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg);
+        vc_val &= ~vdd->vfsm->voltsetup_mask;
+        vc_val |= vdd->pmic_info->volt_setup_time <<
+                        vdd->vfsm->voltsetup_shift;
+        vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg);
+
+        if (cpu_is_omap34xx())
+                omap3_vc_init(vdd);
+        else if (cpu_is_omap44xx())
+                omap4_vc_init(vdd);
+}
+
+static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd)
+{
+        int ret = -EINVAL;
+
+        if (!vdd->pmic_info) {
+                pr_err("%s: PMIC info requried to configure vdd_%s not"
+                        "populated.Hence cannot initialize vdd_%s\n",
+                        __func__, vdd->voltdm.name, vdd->voltdm.name);
+                goto ovdc_out;
+        }
+
+        if (IS_ERR_VALUE(_config_common_vdd_data(vdd)))
+                goto ovdc_out;
+
+        if (cpu_is_omap34xx()) {
+                vdd->read_reg = omap3_voltage_read_reg;
+                vdd->write_reg = omap3_voltage_write_reg;
+                ret = 0;
+        } else if (cpu_is_omap44xx()) {
+                vdd->read_reg = omap4_voltage_read_reg;
+                vdd->write_reg = omap4_voltage_write_reg;
+                ret = 0;
+        }
+
+ovdc_out:
+        return ret;
+}
+
+/* Public functions */
+/**
+ * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
+ * @voltdm:     pointer to the VDD for which current voltage info is needed
+ *
+ * API to get the current non-auto-compensated voltage for a VDD.
+ * Returns 0 in case of error else returns the current voltage for the VDD.
+ */
+unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return 0;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        return vdd->curr_volt;
+}
+
+/**
+ * omap_vp_get_curr_volt() - API to get the current vp voltage.
+ * @voltdm:     pointer to the VDD.
+ *
+ * This API returns the current voltage for the specified voltage processor
+ */
+unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+        u8 curr_vsel;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return 0;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!vdd->read_reg) {
+                pr_err("%s: No read API for reading vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return 0;
+        }
+
+        curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
+
+        if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
+                pr_warning("%s: PMIC function to convert vsel to voltage"
+                        "in uV not registerd\n", __func__);
+                return 0;
+        }
+
+        return vdd->pmic_info->vsel_to_uv(curr_vsel);
+}
+
+/**
+ * omap_vp_enable() - API to enable a particular VP
+ * @voltdm:     pointer to the VDD whose VP is to be enabled.
+ *
+ * This API enables a particular voltage processor. Needed by the smartreflex
+ * class drivers.
+ */
+void omap_vp_enable(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+        u32 vpconfig;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        /* If VP is already enabled, do nothing. Return */
+        if (vdd->vp_enabled)
+                return;
+
+        vp_latch_vsel(vdd);
+
+        /* Enable VP */
+        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
+        vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+        vdd->vp_enabled = true;
+}
+
+/**
+ * omap_vp_disable() - API to disable a particular VP
+ * @voltdm:     pointer to the VDD whose VP is to be disabled.
+ *
+ * This API disables a particular voltage processor. Needed by the smartreflex
+ * class drivers.
+ */
+void omap_vp_disable(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+        u32 vpconfig;
+        int timeout;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        /* If VP is already disabled, do nothing. Return */
+        if (!vdd->vp_enabled) {
+                pr_warning("%s: Trying to disable VP for vdd_%s when"
+                        "it is already disabled\n", __func__, voltdm->name);
+                return;
+        }
+
+        /* Disable VP */
+        vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
+        vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
+        vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+        /*
+         * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+         */
+        omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)),
+                                VP_IDLE_TIMEOUT, timeout);
+
+        if (timeout >= VP_IDLE_TIMEOUT)
+                pr_warning("%s: vdd_%s idle timedout\n",
+                        __func__, voltdm->name);
+
+        vdd->vp_enabled = false;
+
+        return;
+}
+
+/**
+ * omap_voltage_scale_vdd() - API to scale voltage of a particular
+ *                              voltage domain.
+ * @voltdm:     pointer to the VDD which is to be scaled.
+ * @target_volt:        The target voltage of the voltage domain
+ *
+ * This API should be called by the kernel to do the voltage scaling
+ * for a particular voltage domain during dvfs or any other situation.
+ */
+int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+                unsigned long target_volt)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return -EINVAL;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        if (!vdd->volt_scale) {
+                pr_err("%s: No voltage scale API registered for vdd_%s\n",
+                        __func__, voltdm->name);
+                return -ENODATA;
+        }
+
+        return vdd->volt_scale(vdd, target_volt);
+}
+
+/**
+ * omap_voltage_reset() - Resets the voltage of a particular voltage domain
+ *                      to that of the current OPP.
+ * @voltdm:     pointer to the VDD whose voltage is to be reset.
+ *
+ * This API finds out the correct voltage the voltage domain is supposed
+ * to be at and resets the voltage to that level. Should be used especially
+ * while disabling any voltage compensation modules.
+ */
+void omap_voltage_reset(struct voltagedomain *voltdm)
+{
+        unsigned long target_uvdc;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        target_uvdc = omap_voltage_get_nom_volt(voltdm);
+        if (!target_uvdc) {
+                pr_err("%s: unable to find current voltage for vdd_%s\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        omap_voltage_scale_vdd(voltdm, target_uvdc);
+}
+
+/**
+ * omap_voltage_get_volttable() - API to get the voltage table associated with a
+ *                              particular voltage domain.
+ * @voltdm:     pointer to the VDD for which the voltage table is required
+ * @volt_data:  the voltage table for the particular vdd which is to be
+ *              populated by this API
+ *
+ * This API populates the voltage table associated with a VDD into the
+ * passed parameter pointer. Returns the count of distinct voltages
+ * supported by this vdd.
+ *
+ */
+void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+                struct omap_volt_data **volt_data)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        *volt_data = vdd->volt_data;
+}
+
+/**
+ * omap_voltage_get_voltdata() - API to get the voltage table entry for a
+ *                              particular voltage
+ * @voltdm:     pointer to the VDD whose voltage table has to be searched
+ * @volt:       the voltage to be searched in the voltage table
+ *
+ * This API searches through the voltage table for the required voltage
+ * domain and tries to find a matching entry for the passed voltage volt.
+ * If a matching entry is found volt_data is populated with that entry.
+ * This API searches only through the non-compensated voltages int the
+ * voltage table.
+ * Returns pointer to the voltage table entry corresponding to volt on
+ * success. Returns -ENODATA if no voltage table exisits for the passed voltage
+ * domain or if there is no matching entry.
+ */
+struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+                unsigned long volt)
+{
+        struct omap_vdd_info *vdd;
+        int i;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        if (!vdd->volt_data) {
+                pr_warning("%s: voltage table does not exist for vdd_%s\n",
+                        __func__, voltdm->name);
+                return ERR_PTR(-ENODATA);
+        }
+
+        for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) {
+                if (vdd->volt_data[i].volt_nominal == volt)
+                        return &vdd->volt_data[i];
+        }
+
+        pr_notice("%s: Unable to match the current voltage with the voltage"
+                "table for vdd_%s\n", __func__, voltdm->name);
+
+        return ERR_PTR(-ENODATA);
+}
+
+/**
+ * omap_voltage_register_pmic() - API to register PMIC specific data
+ * @voltdm:     pointer to the VDD for which the PMIC specific data is
+ *              to be registered
+ * @pmic_info:  the structure containing pmic info
+ *
+ * This API is to be called by the SOC/PMIC file to specify the
+ * pmic specific info as present in omap_volt_pmic_info structure.
+ */
+int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+                struct omap_volt_pmic_info *pmic_info)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return -EINVAL;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        vdd->pmic_info = pmic_info;
+
+        return 0;
+}
+
+/**
+ * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory
+ *                              corresponding to a voltage domain.
+ *
+ * @voltdm:     pointer to the VDD whose debug directory is required.
+ *
+ * This API returns pointer to the debugfs directory corresponding
+ * to the voltage domain. Should be used by drivers requiring to
+ * add any debug entry for a particular voltage domain. Returns NULL
+ * in case of error.
+ */
+struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return NULL;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        return vdd->debug_dir;
+}
+
+/**
+ * omap_change_voltscale_method() - API to change the voltage scaling method.
+ * @voltdm:     pointer to the VDD whose voltage scaling method
+ *              has to be changed.
+ * @voltscale_method:   the method to be used for voltage scaling.
+ *
+ * This API can be used by the board files to change the method of voltage
+ * scaling between vpforceupdate and vcbypass. The parameter values are
+ * defined in voltage.h
+ */
+void omap_change_voltscale_method(struct voltagedomain *voltdm,
+                int voltscale_method)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        switch (voltscale_method) {
+        case VOLTSCALE_VPFORCEUPDATE:
+                vdd->volt_scale = vp_forceupdate_scale_voltage;
+                return;
+        case VOLTSCALE_VCBYPASS:
+                vdd->volt_scale = vc_bypass_scale_voltage;
+                return;
+        default:
+                pr_warning("%s: Trying to change the method of voltage scaling"
+                        "to an unsupported one!\n", __func__);
+        }
+}
+
+/**
+ * omap_voltage_domain_lookup() - API to get the voltage domain pointer
+ * @name:       Name of the voltage domain
+ *
+ * This API looks up in the global vdd_info struct for the
+ * existence of voltage domain <name>. If it exists, the API returns
+ * a pointer to the voltage domain structure corresponding to the
+ * VDD<name>. Else retuns error pointer.
+ */
+struct voltagedomain *omap_voltage_domain_lookup(char *name)
+{
+        int i;
+
+        if (!vdd_info) {
+                pr_err("%s: Voltage driver init not yet happened.Faulting!\n",
+                        __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        if (!name) {
+                pr_err("%s: No name to get the votage domain!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        for (i = 0; i < nr_scalable_vdd; i++) {
+                if (!(strcmp(name, vdd_info[i]->voltdm.name)))
+                        return &vdd_info[i]->voltdm;
+        }
+
+        return ERR_PTR(-EINVAL);
+}
+
+/**
+ * omap_voltage_late_init() - Init the various voltage parameters
+ *
+ * This API is to be called in the later stages of the
+ * system boot to init the voltage controller and
+ * voltage processors.
+ */
+int __init omap_voltage_late_init(void)
+{
+        int i;
+
+        if (!vdd_info) {
+                pr_err("%s: Voltage driver support not added\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        voltage_dir = debugfs_create_dir("voltage", NULL);
+        if (IS_ERR(voltage_dir))
+                pr_err("%s: Unable to create voltage debugfs main dir\n",
+                        __func__);
+        for (i = 0; i < nr_scalable_vdd; i++) {
+                if (omap_vdd_data_configure(vdd_info[i]))
+                        continue;
+                omap_vc_init(vdd_info[i]);
+                vp_init(vdd_info[i]);
+                vdd_debugfs_init(vdd_info[i]);
+        }
+
+        return 0;
+}
+
+/* XXX document */
+int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod,
+                                   struct omap_vdd_info *omap_vdd_array[],
+                                   u8 omap_vdd_count)
+{
+        prm_mod_offs = prm_mod;
+        prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod;
+        vdd_info = omap_vdd_array;
+        nr_scalable_vdd = omap_vdd_count;
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
new file mode 100644
index 000000000000..e9f5408244e0
--- /dev/null
+++ b/arch/arm/mach-omap2/voltage.h
@@ -0,0 +1,184 @@
+/*
+ * OMAP Voltage Management Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+
+#include <linux/err.h>
+
+#include "vc.h"
+#include "vp.h"
+
+/* XXX document */
+#define VOLTSCALE_VPFORCEUPDATE         1
+#define VOLTSCALE_VCBYPASS              2
+
+/*
+ * OMAP3 GENERIC setup times. Revisit to see if these needs to be
+ * passed from board or PMIC file
+ */
+#define OMAP3_CLKSETUP          0xff
+#define OMAP3_VOLTOFFSET        0xff
+#define OMAP3_VOLTSETUP2        0xff
+
+/**
+ * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield
+ * data
+ * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
+ * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
+ * @voltsetup_shift: SETUP_TIME* field shift in the PRM_VOLTSETUP* register
+ *
+ * XXX What about VOLTOFFSET/VOLTCTRL?
+ * XXX It is not necessary to have both a _mask and a _shift for the same
+ *     bitfield - remove one!
+ */
+struct omap_vfsm_instance_data {
+        u32 voltsetup_mask;
+        u8 voltsetup_reg;
+        u8 voltsetup_shift;
+};
+
+/**
+ * struct voltagedomain - omap voltage domain global structure.
+ * @name:       Name of the voltage domain which can be used as a unique
+ *              identifier.
+ */
+struct voltagedomain {
+        char *name;
+};
+
+/**
+ * struct omap_volt_data - Omap voltage specific data.
+ * @voltage_nominal:    The possible voltage value in uV
+ * @sr_efuse_offs:      The offset of the efuse register(from system
+ *                      control module base address) from where to read
+ *                      the n-target value for the smartreflex module.
+ * @sr_errminlimit:     Error min limit value for smartreflex. This value
+ *                      differs at differnet opp and thus is linked
+ *                      with voltage.
+ * @vp_errorgain:       Error gain value for the voltage processor. This
+ *                      field also differs according to the voltage/opp.
+ */
+struct omap_volt_data {
+        u32     volt_nominal;
+        u32     sr_efuse_offs;
+        u8      sr_errminlimit;
+        u8      vp_errgain;
+};
+
+/**
+ * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
+ * @slew_rate:  PMIC slew rate (in uv/us)
+ * @step_size:  PMIC voltage step size (in uv)
+ * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
+ * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
+ */
+struct omap_volt_pmic_info {
+        int slew_rate;
+        int step_size;
+        u32 on_volt;
+        u32 onlp_volt;
+        u32 ret_volt;
+        u32 off_volt;
+        u16 volt_setup_time;
+        u8 vp_erroroffset;
+        u8 vp_vstepmin;
+        u8 vp_vstepmax;
+        u8 vp_vddmin;
+        u8 vp_vddmax;
+        u8 vp_timeout_us;
+        u8 i2c_slave_addr;
+        u8 pmic_reg;
+        unsigned long (*vsel_to_uv) (const u8 vsel);
+        u8 (*uv_to_vsel) (unsigned long uV);
+};
+
+/**
+ * omap_vdd_info - Per Voltage Domain info
+ *
+ * @volt_data           : voltage table having the distinct voltages supported
+ *                        by the domain and other associated per voltage data.
+ * @pmic_info           : pmic specific parameters which should be populted by
+ *                        the pmic drivers.
+ * @vp_data             : the register values, shifts, masks for various
+ *                        vp registers
+ * @vp_rt_data          : VP data derived at runtime, not predefined
+ * @vc_data             : structure containing various various vc registers,
+ *                        shifts, masks etc.
+ * @vfsm                : voltage manager FSM data
+ * @voltdm              : pointer to the voltage domain structure
+ * @debug_dir           : debug directory for this voltage domain.
+ * @curr_volt           : current voltage for this vdd.
+ * @vp_enabled          : flag to keep track of whether vp is enabled or not
+ * @volt_scale          : API to scale the voltage of the vdd.
+ */
+struct omap_vdd_info {
+        struct omap_volt_data *volt_data;
+        struct omap_volt_pmic_info *pmic_info;
+        struct omap_vp_instance_data *vp_data;
+        struct omap_vp_runtime_data vp_rt_data;
+        struct omap_vc_instance_data *vc_data;
+        const struct omap_vfsm_instance_data *vfsm;
+        struct voltagedomain voltdm;
+        struct dentry *debug_dir;
+        u32 curr_volt;
+        bool vp_enabled;
+        u32 (*read_reg) (u16 mod, u8 offset);
+        void (*write_reg) (u32 val, u16 mod, u8 offset);
+        int (*volt_scale) (struct omap_vdd_info *vdd,
+                unsigned long target_volt);
+};
+
+unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+void omap_vp_enable(struct voltagedomain *voltdm);
+void omap_vp_disable(struct voltagedomain *voltdm);
+int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+                unsigned long target_volt);
+void omap_voltage_reset(struct voltagedomain *voltdm);
+void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+                struct omap_volt_data **volt_data);
+struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+                unsigned long volt);
+unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_mod,
+                                   struct omap_vdd_info *omap_vdd_array[],
+                                   u8 omap_vdd_count);
+#ifdef CONFIG_PM
+int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+                struct omap_volt_pmic_info *pmic_info);
+void omap_change_voltscale_method(struct voltagedomain *voltdm,
+                int voltscale_method);
+/* API to get the voltagedomain pointer */
+struct voltagedomain *omap_voltage_domain_lookup(char *name);
+
+int omap_voltage_late_init(void);
+#else
+static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+                struct omap_volt_pmic_info *pmic_info)
+{
+        return -EINVAL;
+}
+static inline  void omap_change_voltscale_method(struct voltagedomain *voltdm,
+                int voltscale_method) {}
+static inline int omap_voltage_late_init(void)
+{
+        return -EINVAL;
+}
+static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
+{
+        return ERR_PTR(-EINVAL);
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
new file mode 100644
index 000000000000..def230fd2fde
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -0,0 +1,95 @@
+/*
+ * OMAP3 voltage domain data
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+
+#include "prm-regbits-34xx.h"
+#include "omap_opp_data.h"
+#include "voltage.h"
+#include "vc.h"
+#include "vp.h"
+
+/*
+ * VDD data
+ */
+
+static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
+        .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
+        .voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT,
+        .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
+};
+
+static struct omap_vdd_info omap3_vdd1_info = {
+        .vp_data = &omap3_vp1_data,
+        .vc_data = &omap3_vc1_data,
+        .vfsm = &omap3_vdd1_vfsm_data,
+        .voltdm = {
+                .name = "mpu",
+        },
+};
+
+static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
+        .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
+        .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT,
+        .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
+};
+
+static struct omap_vdd_info omap3_vdd2_info = {
+        .vp_data = &omap3_vp2_data,
+        .vc_data = &omap3_vc2_data,
+        .vfsm = &omap3_vdd2_vfsm_data,
+        .voltdm = {
+                .name = "core",
+        },
+};
+
+/* OMAP3 VDD structures */
+static struct omap_vdd_info *omap3_vdd_info[] = {
+        &omap3_vdd1_info,
+        &omap3_vdd2_info,
+};
+
+/* OMAP3 specific voltage init functions */
+static int __init omap3xxx_voltage_early_init(void)
+{
+        s16 prm_mod = OMAP3430_GR_MOD;
+        s16 prm_irqst_ocp_mod = OCP_MOD;
+
+        if (!cpu_is_omap34xx())
+                return 0;
+
+        /*
+         * XXX Will depend on the process, validation, and binning
+         * for the currently-running IC
+         */
+        if (cpu_is_omap3630()) {
+                omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data;
+                omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data;
+        } else {
+                omap3_vdd1_info.volt_data = omap34xx_vddmpu_volt_data;
+                omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
+        }
+
+        return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+                                       omap3_vdd_info,
+                                       ARRAY_SIZE(omap3_vdd_info));
+};
+core_initcall(omap3xxx_voltage_early_init);
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
new file mode 100644
index 000000000000..cb64996de0e1
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -0,0 +1,102 @@
+/*
+ * OMAP3/OMAP4 Voltage Management Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <plat/common.h>
+
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm44xx.h"
+#include "prminst44xx.h"
+#include "voltage.h"
+#include "omap_opp_data.h"
+#include "vc.h"
+#include "vp.h"
+
+static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
+        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+};
+
+static struct omap_vdd_info omap4_vdd_mpu_info = {
+        .vp_data = &omap4_vp_mpu_data,
+        .vc_data = &omap4_vc_mpu_data,
+        .vfsm = &omap4_vdd_mpu_vfsm_data,
+        .voltdm = {
+                .name = "mpu",
+        },
+};
+
+static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
+        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
+};
+
+static struct omap_vdd_info omap4_vdd_iva_info = {
+        .vp_data = &omap4_vp_iva_data,
+        .vc_data = &omap4_vc_iva_data,
+        .vfsm = &omap4_vdd_iva_vfsm_data,
+        .voltdm = {
+                .name = "iva",
+        },
+};
+
+static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
+        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+};
+
+static struct omap_vdd_info omap4_vdd_core_info = {
+        .vp_data = &omap4_vp_core_data,
+        .vc_data = &omap4_vc_core_data,
+        .vfsm = &omap4_vdd_core_vfsm_data,
+        .voltdm = {
+                .name = "core",
+        },
+};
+
+/* OMAP4 VDD structures */
+static struct omap_vdd_info *omap4_vdd_info[] = {
+        &omap4_vdd_mpu_info,
+        &omap4_vdd_iva_info,
+        &omap4_vdd_core_info,
+};
+
+/* OMAP4 specific voltage init functions */
+static int __init omap44xx_voltage_early_init(void)
+{
+        s16 prm_mod = OMAP4430_PRM_DEVICE_INST;
+        s16 prm_irqst_ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
+
+        if (!cpu_is_omap44xx())
+                return 0;
+
+        /*
+         * XXX Will depend on the process, validation, and binning
+         * for the currently-running IC
+         */
+        omap4_vdd_mpu_info.volt_data = omap44xx_vdd_mpu_volt_data;
+        omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
+        omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
+
+        return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+                                       omap4_vdd_info,
+                                       ARRAY_SIZE(omap4_vdd_info));
+};
+core_initcall(omap44xx_voltage_early_init);
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
new file mode 100644
index 000000000000..7ce134f7de79
--- /dev/null
+++ b/arch/arm/mach-omap2/vp.h
@@ -0,0 +1,143 @@
+/*
+ * OMAP3/4 Voltage Processor (VP) structure and macro definitions
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_VP_H
+#define __ARCH_ARM_MACH_OMAP2_VP_H
+
+#include <linux/kernel.h>
+
+/* XXX document */
+#define VP_IDLE_TIMEOUT         200
+#define VP_TRANXDONE_TIMEOUT    300
+
+
+/**
+ * struct omap_vp_common_data - register data common to all VDDs
+ * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
+ * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
+ * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
+ * @vpconfig_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
+ * @vpconfig_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
+ * @vpconfig_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
+ * @vpconfig_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
+ * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+ * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+ * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
+ *
+ * XXX It it not necessary to have both a mask and a shift for the same
+ *     bitfield - remove one
+ * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix!
+ */
+struct omap_vp_common_data {
+        u32 vpconfig_errorgain_mask;
+        u32 vpconfig_initvoltage_mask;
+        u32 vpconfig_timeouten;
+        u32 vpconfig_initvdd;
+        u32 vpconfig_forceupdate;
+        u32 vpconfig_vpenable;
+        u8 vpconfig_erroroffset_shift;
+        u8 vpconfig_errorgain_shift;
+        u8 vpconfig_initvoltage_shift;
+        u8 vstepmin_stepmin_shift;
+        u8 vstepmin_smpswaittimemin_shift;
+        u8 vstepmax_stepmax_shift;
+        u8 vstepmax_smpswaittimemax_shift;
+        u8 vlimitto_vddmin_shift;
+        u8 vlimitto_vddmax_shift;
+        u8 vlimitto_timeout_shift;
+};
+
+/**
+ * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
+ * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ *
+ * XXX prm_irqst_reg does not belong here
+ * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
+ *     hardware bug
+ * XXX This structure is probably not needed
+ */
+struct omap_vp_prm_irqst_data {
+        u8 prm_irqst_reg;
+        u32 tranxdone_status;
+};
+
+/**
+ * struct omap_vp_instance_data - VP register offsets (per-VDD)
+ * @vp_common: pointer to struct omap_vp_common_data * for this SoC
+ * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD
+ * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
+ * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
+ * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
+ * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
+ * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
+ *
+ * XXX vp_common is probably not needed since it is per-SoC
+ */
+struct omap_vp_instance_data {
+        const struct omap_vp_common_data *vp_common;
+        const struct omap_vp_prm_irqst_data *prm_irqst_data;
+        u8 vpconfig;
+        u8 vstepmin;
+        u8 vstepmax;
+        u8 vlimitto;
+        u8 vstatus;
+        u8 voltage;
+};
+
+/**
+ * struct omap_vp_runtime_data - VP data populated at runtime by code
+ * @vpconfig_erroroffset: value of ERROROFFSET bitfield in PRM_VP*_CONFIG
+ * @vpconfig_errorgain: value of ERRORGAIN bitfield in PRM_VP*_CONFIG
+ * @vstepmin_smpswaittimemin: value of SMPSWAITTIMEMIN bitfield in PRM_VP*_VSTEPMIN
+ * @vstepmax_smpswaittimemax: value of SMPSWAITTIMEMAX bitfield in PRM_VP*_VSTEPMAX
+ * @vlimitto_timeout: value of TIMEOUT bitfield in PRM_VP*_VLIMITTO
+ * @vstepmin_stepmin: value of VSTEPMIN bitfield in PRM_VP*_VSTEPMIN
+ * @vstepmax_stepmax: value of VSTEPMAX bitfield in PRM_VP*_VSTEPMAX
+ * @vlimitto_vddmin: value of VDDMIN bitfield in PRM_VP*_VLIMITTO
+ * @vlimitto_vddmax: value of VDDMAX bitfield in PRM_VP*_VLIMITTO
+ *
+ * XXX Is this structure really needed?  Why not just program the
+ * device directly?  They are in PRM space, therefore in the WKUP
+ * powerdomain, so register contents should not be lost in off-mode.
+ * XXX Some of these fields are incorrectly named, e.g., vstep*
+ */
+struct omap_vp_runtime_data {
+        u32 vpconfig_erroroffset;
+        u16 vpconfig_errorgain;
+        u16 vstepmin_smpswaittimemin;
+        u16 vstepmax_smpswaittimemax;
+        u16 vlimitto_timeout;
+        u8 vstepmin_stepmin;
+        u8 vstepmax_stepmax;
+        u8 vlimitto_vddmin;
+        u8 vlimitto_vddmax;
+};
+
+extern struct omap_vp_instance_data omap3_vp1_data;
+extern struct omap_vp_instance_data omap3_vp2_data;
+
+extern struct omap_vp_instance_data omap4_vp_mpu_data;
+extern struct omap_vp_instance_data omap4_vp_iva_data;
+extern struct omap_vp_instance_data omap4_vp_core_data;
+
+#endif
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
new file mode 100644
index 000000000000..645217094e51
--- /dev/null
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -0,0 +1,82 @@
+/*
+ * OMAP3 Voltage Processor (VP) data
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <plat/common.h>
+
+#include "prm-regbits-34xx.h"
+#include "voltage.h"
+
+#include "vp.h"
+
+/*
+ * VP data common to 34xx/36xx chips
+ * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
+ */
+static const struct omap_vp_common_data omap3_vp_common = {
+        .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
+        .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
+        .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
+        .vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT,
+        .vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
+        .vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
+        .vpconfig_initvdd = OMAP3430_INITVDD_MASK,
+        .vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK,
+        .vpconfig_vpenable = OMAP3430_VPENABLE_MASK,
+        .vstepmin_smpswaittimemin_shift = OMAP3430_SMPSWAITTIMEMIN_SHIFT,
+        .vstepmax_smpswaittimemax_shift = OMAP3430_SMPSWAITTIMEMAX_SHIFT,
+        .vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT,
+        .vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT,
+        .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
+        .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
+        .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
+};
+
+static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
+        .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+};
+
+struct omap_vp_instance_data omap3_vp1_data = {
+        .vp_common = &omap3_vp_common,
+        .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+        .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+        .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
+        .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
+        .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
+        .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
+        .prm_irqst_data = &omap3_vp1_prm_irqst_data,
+};
+
+static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
+        .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+};
+
+struct omap_vp_instance_data omap3_vp2_data = {
+        .vp_common = &omap3_vp_common,
+        .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+        .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+        .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
+        .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
+        .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
+        .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
+        .prm_irqst_data = &omap3_vp2_prm_irqst_data,
+};
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
new file mode 100644
index 000000000000..65d1ad63800a
--- /dev/null
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -0,0 +1,100 @@
+/*
+ * OMAP3 Voltage Processor (VP) data
+ *
+ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <plat/common.h>
+
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#include "voltage.h"
+
+#include "vp.h"
+
+/*
+ * VP data common to 44xx chips
+ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
+ */
+static const struct omap_vp_common_data omap4_vp_common = {
+        .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
+        .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
+        .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
+        .vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT,
+        .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK,
+        .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK,
+        .vpconfig_initvdd = OMAP4430_INITVDD_MASK,
+        .vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK,
+        .vpconfig_vpenable = OMAP4430_VPENABLE_MASK,
+        .vstepmin_smpswaittimemin_shift = OMAP4430_SMPSWAITTIMEMIN_SHIFT,
+        .vstepmax_smpswaittimemax_shift = OMAP4430_SMPSWAITTIMEMAX_SHIFT,
+        .vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT,
+        .vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT,
+        .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT,
+        .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT,
+        .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT,
+};
+
+static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
+        .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+        .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
+};
+
+struct omap_vp_instance_data omap4_vp_mpu_data = {
+        .vp_common = &omap4_vp_common,
+        .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+        .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+        .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+        .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+        .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+        .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+        .prm_irqst_data = &omap4_vp_mpu_prm_irqst_data,
+};
+
+static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
+        .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+        .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+};
+
+struct omap_vp_instance_data omap4_vp_iva_data = {
+        .vp_common = &omap4_vp_common,
+        .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+        .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+        .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+        .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+        .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+        .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+        .prm_irqst_data = &omap4_vp_iva_prm_irqst_data,
+};
+
+static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
+        .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+        .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
+};
+
+struct omap_vp_instance_data omap4_vp_core_data = {
+        .vp_common = &omap4_vp_common,
+        .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+        .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+        .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+        .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+        .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+        .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+        .prm_irqst_data = &omap4_vp_core_prm_irqst_data,
+};
+
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
new file mode 100644
index 000000000000..4067669d96c4
--- /dev/null
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -0,0 +1,56 @@
+/*
+ * OMAP2+ MPU WD_TIMER-specific code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <plat/omap_hwmod.h>
+
+#include "wd_timer.h"
+
+/*
+ * In order to avoid any assumptions from bootloader regarding WDT
+ * settings, WDT module is reset during init. This enables the watchdog
+ * timer. Hence it is required to disable the watchdog after the WDT reset
+ * during init. Otherwise the system would reboot as per the default
+ * watchdog timer registers settings.
+ */
+#define OMAP_WDT_WPS            0x34
+#define OMAP_WDT_SPR            0x48
+
+
+int omap2_wd_timer_disable(struct omap_hwmod *oh)
+{
+        void __iomem *base;
+
+        if (!oh) {
+                pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
+                return -EINVAL;
+        }
+
+        base = omap_hwmod_get_mpu_rt_va(oh);
+        if (!base) {
+                pr_err("%s: Could not get the base address for %s\n",
+                                oh->name, __func__);
+                return -EINVAL;
+        }
+
+        /* sequence required to disable watchdog */
+        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        __raw_writel(0x5555, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
new file mode 100644
index 000000000000..e0054a2d5505
--- /dev/null
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -0,0 +1,17 @@
+/*
+ * OMAP2+ MPU WD_TIMER-specific function prototypes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
+#define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
+
+#include <plat/omap_hwmod.h>
+
+extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
+
+#endif