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Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c1939
1 files changed, 1269 insertions, 670 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index e10db7a90cb2..8c965671b4d4 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -17,21 +17,30 @@
17 * This program is free software; you can redistribute it and/or modify 17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
20 */ 24 */
21 25
22#include <linux/kernel.h> 26#include <linux/kernel.h>
23#include <linux/list.h> 27#include <linux/list.h>
24#include <linux/clk.h> 28#include <linux/clk.h>
25
26#include <plat/control.h>
27#include <plat/clkdev_omap.h> 29#include <plat/clkdev_omap.h>
28 30
29#include "clock.h" 31#include "clock.h"
30#include "clock44xx.h" 32#include "clock44xx.h"
31#include "cm.h" 33#include "cm1_44xx.h"
34#include "cm2_44xx.h"
32#include "cm-regbits-44xx.h" 35#include "cm-regbits-44xx.h"
33#include "prm.h" 36#include "prm44xx.h"
34#include "prm-regbits-44xx.h" 37#include "prm-regbits-44xx.h"
38#include "control.h"
39#include "scrm44xx.h"
40
41/* OMAP4 modulemode control */
42#define OMAP4430_MODULEMODE_HWCTRL 0
43#define OMAP4430_MODULEMODE_SWCTRL 1
35 44
36/* Root clocks */ 45/* Root clocks */
37 46
@@ -44,7 +53,9 @@ static struct clk extalt_clkin_ck = {
44static struct clk pad_clks_ck = { 53static struct clk pad_clks_ck = {
45 .name = "pad_clks_ck", 54 .name = "pad_clks_ck",
46 .rate = 12000000, 55 .rate = 12000000,
47 .ops = &clkops_null, 56 .ops = &clkops_omap2_dflt,
57 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
48}; 59};
49 60
50static struct clk pad_slimbus_core_clks_ck = { 61static struct clk pad_slimbus_core_clks_ck = {
@@ -62,7 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
62static struct clk slimbus_clk = { 73static struct clk slimbus_clk = {
63 .name = "slimbus_clk", 74 .name = "slimbus_clk",
64 .rate = 12000000, 75 .rate = 12000000,
65 .ops = &clkops_null, 76 .ops = &clkops_omap2_dflt,
77 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
66}; 79};
67 80
68static struct clk sys_32k_ck = { 81static struct clk sys_32k_ck = {
@@ -175,21 +188,27 @@ static struct clk sys_clkin_ck = {
175 .recalc = &omap2_clksel_recalc, 188 .recalc = &omap2_clksel_recalc,
176}; 189};
177 190
191static struct clk tie_low_clock_ck = {
192 .name = "tie_low_clock_ck",
193 .rate = 0,
194 .ops = &clkops_null,
195};
196
178static struct clk utmi_phy_clkout_ck = { 197static struct clk utmi_phy_clkout_ck = {
179 .name = "utmi_phy_clkout_ck", 198 .name = "utmi_phy_clkout_ck",
180 .rate = 12000000, 199 .rate = 60000000,
181 .ops = &clkops_null, 200 .ops = &clkops_null,
182}; 201};
183 202
184static struct clk xclk60mhsp1_ck = { 203static struct clk xclk60mhsp1_ck = {
185 .name = "xclk60mhsp1_ck", 204 .name = "xclk60mhsp1_ck",
186 .rate = 12000000, 205 .rate = 60000000,
187 .ops = &clkops_null, 206 .ops = &clkops_null,
188}; 207};
189 208
190static struct clk xclk60mhsp2_ck = { 209static struct clk xclk60mhsp2_ck = {
191 .name = "xclk60mhsp2_ck", 210 .name = "xclk60mhsp2_ck",
192 .rate = 12000000, 211 .rate = 60000000,
193 .ops = &clkops_null, 212 .ops = &clkops_null,
194}; 213};
195 214
@@ -201,39 +220,23 @@ static struct clk xclk60motg_ck = {
201 220
202/* Module clocks and DPLL outputs */ 221/* Module clocks and DPLL outputs */
203 222
204static const struct clksel_rate div2_1to2_rates[] = { 223static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
205 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 224 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
206 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 225 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
207 { .div = 0 },
208};
209
210static const struct clksel dpll_sys_ref_clk_div[] = {
211 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
212 { .parent = NULL }, 226 { .parent = NULL },
213}; 227};
214 228
215static struct clk dpll_sys_ref_clk = { 229static struct clk abe_dpll_bypass_clk_mux_ck = {
216 .name = "dpll_sys_ref_clk", 230 .name = "abe_dpll_bypass_clk_mux_ck",
217 .parent = &sys_clkin_ck, 231 .parent = &sys_clkin_ck,
218 .clksel = dpll_sys_ref_clk_div,
219 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
220 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
221 .ops = &clkops_null, 232 .ops = &clkops_null,
222 .recalc = &omap2_clksel_recalc, 233 .recalc = &followparent_recalc,
223 .round_rate = &omap2_clksel_round_rate,
224 .set_rate = &omap2_clksel_set_rate,
225};
226
227static const struct clksel abe_dpll_refclk_mux_sel[] = {
228 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
229 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
230 { .parent = NULL },
231}; 234};
232 235
233static struct clk abe_dpll_refclk_mux_ck = { 236static struct clk abe_dpll_refclk_mux_ck = {
234 .name = "abe_dpll_refclk_mux_ck", 237 .name = "abe_dpll_refclk_mux_ck",
235 .parent = &dpll_sys_ref_clk, 238 .parent = &sys_clkin_ck,
236 .clksel = abe_dpll_refclk_mux_sel, 239 .clksel = abe_dpll_bypass_clk_mux_sel,
237 .init = &omap2_init_clksel_parent, 240 .init = &omap2_init_clksel_parent,
238 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, 241 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
239 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 242 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
@@ -244,7 +247,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
244/* DPLL_ABE */ 247/* DPLL_ABE */
245static struct dpll_data dpll_abe_dd = { 248static struct dpll_data dpll_abe_dd = {
246 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, 249 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
247 .clk_bypass = &sys_clkin_ck, 250 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
248 .clk_ref = &abe_dpll_refclk_mux_ck, 251 .clk_ref = &abe_dpll_refclk_mux_ck,
249 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, 252 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
250 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 253 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -272,18 +275,73 @@ static struct clk dpll_abe_ck = {
272 .set_rate = &omap3_noncore_dpll_set_rate, 275 .set_rate = &omap3_noncore_dpll_set_rate,
273}; 276};
274 277
278static struct clk dpll_abe_x2_ck = {
279 .name = "dpll_abe_x2_ck",
280 .parent = &dpll_abe_ck,
281 .flags = CLOCK_CLKOUTX2,
282 .ops = &clkops_omap4_dpllmx_ops,
283 .recalc = &omap3_clkoutx2_recalc,
284 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
285};
286
287static const struct clksel_rate div31_1to31_rates[] = {
288 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
289 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
290 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
291 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
292 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
293 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
294 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
295 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
296 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
297 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
298 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
299 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
300 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
301 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
302 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
303 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
304 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
305 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
306 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
307 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
308 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
309 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
310 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
311 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
312 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
313 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
314 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
315 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
316 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
317 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
318 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
319 { .div = 0 },
320};
321
322static const struct clksel dpll_abe_m2x2_div[] = {
323 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
324 { .parent = NULL },
325};
326
275static struct clk dpll_abe_m2x2_ck = { 327static struct clk dpll_abe_m2x2_ck = {
276 .name = "dpll_abe_m2x2_ck", 328 .name = "dpll_abe_m2x2_ck",
277 .parent = &dpll_abe_ck, 329 .parent = &dpll_abe_x2_ck,
278 .ops = &clkops_null, 330 .clksel = dpll_abe_m2x2_div,
279 .recalc = &followparent_recalc, 331 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
332 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
333 .ops = &clkops_omap4_dpllmx_ops,
334 .recalc = &omap2_clksel_recalc,
335 .round_rate = &omap2_clksel_round_rate,
336 .set_rate = &omap2_clksel_set_rate,
280}; 337};
281 338
282static struct clk abe_24m_fclk = { 339static struct clk abe_24m_fclk = {
283 .name = "abe_24m_fclk", 340 .name = "abe_24m_fclk",
284 .parent = &dpll_abe_m2x2_ck, 341 .parent = &dpll_abe_m2x2_ck,
285 .ops = &clkops_null, 342 .ops = &clkops_null,
286 .recalc = &followparent_recalc, 343 .fixed_div = 8,
344 .recalc = &omap_fixed_divisor_recalc,
287}; 345};
288 346
289static const struct clksel_rate div3_1to4_rates[] = { 347static const struct clksel_rate div3_1to4_rates[] = {
@@ -310,6 +368,12 @@ static struct clk abe_clk = {
310 .set_rate = &omap2_clksel_set_rate, 368 .set_rate = &omap2_clksel_set_rate,
311}; 369};
312 370
371static const struct clksel_rate div2_1to2_rates[] = {
372 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
373 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
374 { .div = 0 },
375};
376
313static const struct clksel aess_fclk_div[] = { 377static const struct clksel aess_fclk_div[] = {
314 { .parent = &abe_clk, .rates = div2_1to2_rates }, 378 { .parent = &abe_clk, .rates = div2_1to2_rates },
315 { .parent = NULL }, 379 { .parent = NULL },
@@ -327,67 +391,27 @@ static struct clk aess_fclk = {
327 .set_rate = &omap2_clksel_set_rate, 391 .set_rate = &omap2_clksel_set_rate,
328}; 392};
329 393
330static const struct clksel_rate div31_1to31_rates[] = { 394static struct clk dpll_abe_m3x2_ck = {
331 { .div = 1, .val = 1, .flags = RATE_IN_4430 }, 395 .name = "dpll_abe_m3x2_ck",
332 { .div = 2, .val = 2, .flags = RATE_IN_4430 }, 396 .parent = &dpll_abe_x2_ck,
333 { .div = 3, .val = 3, .flags = RATE_IN_4430 }, 397 .clksel = dpll_abe_m2x2_div,
334 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
335 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
336 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
337 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
338 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
339 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
340 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
341 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
342 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
343 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
344 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
345 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
346 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
347 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
348 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
349 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
350 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
351 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
352 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
353 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
354 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
355 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
356 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
357 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
358 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
359 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
360 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
361 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
362 { .div = 0 },
363};
364
365static const struct clksel dpll_abe_m3_div[] = {
366 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
367 { .parent = NULL },
368};
369
370static struct clk dpll_abe_m3_ck = {
371 .name = "dpll_abe_m3_ck",
372 .parent = &dpll_abe_ck,
373 .clksel = dpll_abe_m3_div,
374 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, 398 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
375 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 399 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
376 .ops = &clkops_null, 400 .ops = &clkops_omap4_dpllmx_ops,
377 .recalc = &omap2_clksel_recalc, 401 .recalc = &omap2_clksel_recalc,
378 .round_rate = &omap2_clksel_round_rate, 402 .round_rate = &omap2_clksel_round_rate,
379 .set_rate = &omap2_clksel_set_rate, 403 .set_rate = &omap2_clksel_set_rate,
380}; 404};
381 405
382static const struct clksel core_hsd_byp_clk_mux_sel[] = { 406static const struct clksel core_hsd_byp_clk_mux_sel[] = {
383 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 407 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
384 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, 408 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
385 { .parent = NULL }, 409 { .parent = NULL },
386}; 410};
387 411
388static struct clk core_hsd_byp_clk_mux_ck = { 412static struct clk core_hsd_byp_clk_mux_ck = {
389 .name = "core_hsd_byp_clk_mux_ck", 413 .name = "core_hsd_byp_clk_mux_ck",
390 .parent = &dpll_sys_ref_clk, 414 .parent = &sys_clkin_ck,
391 .clksel = core_hsd_byp_clk_mux_sel, 415 .clksel = core_hsd_byp_clk_mux_sel,
392 .init = &omap2_init_clksel_parent, 416 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, 417 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
@@ -400,7 +424,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
400static struct dpll_data dpll_core_dd = { 424static struct dpll_data dpll_core_dd = {
401 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, 425 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
402 .clk_bypass = &core_hsd_byp_clk_mux_ck, 426 .clk_bypass = &core_hsd_byp_clk_mux_ck,
403 .clk_ref = &dpll_sys_ref_clk, 427 .clk_ref = &sys_clkin_ck,
404 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, 428 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 429 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
406 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, 430 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
@@ -418,25 +442,33 @@ static struct dpll_data dpll_core_dd = {
418 442
419static struct clk dpll_core_ck = { 443static struct clk dpll_core_ck = {
420 .name = "dpll_core_ck", 444 .name = "dpll_core_ck",
421 .parent = &dpll_sys_ref_clk, 445 .parent = &sys_clkin_ck,
422 .dpll_data = &dpll_core_dd, 446 .dpll_data = &dpll_core_dd,
423 .init = &omap2_init_dpll_parent, 447 .init = &omap2_init_dpll_parent,
424 .ops = &clkops_null, 448 .ops = &clkops_omap3_core_dpll_ops,
425 .recalc = &omap3_dpll_recalc, 449 .recalc = &omap3_dpll_recalc,
426}; 450};
427 451
428static const struct clksel dpll_core_m6_div[] = { 452static struct clk dpll_core_x2_ck = {
429 { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, 453 .name = "dpll_core_x2_ck",
454 .parent = &dpll_core_ck,
455 .flags = CLOCK_CLKOUTX2,
456 .ops = &clkops_null,
457 .recalc = &omap3_clkoutx2_recalc,
458};
459
460static const struct clksel dpll_core_m6x2_div[] = {
461 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
430 { .parent = NULL }, 462 { .parent = NULL },
431}; 463};
432 464
433static struct clk dpll_core_m6_ck = { 465static struct clk dpll_core_m6x2_ck = {
434 .name = "dpll_core_m6_ck", 466 .name = "dpll_core_m6x2_ck",
435 .parent = &dpll_core_ck, 467 .parent = &dpll_core_x2_ck,
436 .clksel = dpll_core_m6_div, 468 .clksel = dpll_core_m6x2_div,
437 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, 469 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
438 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, 470 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
439 .ops = &clkops_null, 471 .ops = &clkops_omap4_dpllmx_ops,
440 .recalc = &omap2_clksel_recalc, 472 .recalc = &omap2_clksel_recalc,
441 .round_rate = &omap2_clksel_round_rate, 473 .round_rate = &omap2_clksel_round_rate,
442 .set_rate = &omap2_clksel_set_rate, 474 .set_rate = &omap2_clksel_set_rate,
@@ -444,7 +476,7 @@ static struct clk dpll_core_m6_ck = {
444 476
445static const struct clksel dbgclk_mux_sel[] = { 477static const struct clksel dbgclk_mux_sel[] = {
446 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 478 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
447 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, 479 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
448 { .parent = NULL }, 480 { .parent = NULL },
449}; 481};
450 482
@@ -455,13 +487,18 @@ static struct clk dbgclk_mux_ck = {
455 .recalc = &followparent_recalc, 487 .recalc = &followparent_recalc,
456}; 488};
457 489
490static const struct clksel dpll_core_m2_div[] = {
491 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
492 { .parent = NULL },
493};
494
458static struct clk dpll_core_m2_ck = { 495static struct clk dpll_core_m2_ck = {
459 .name = "dpll_core_m2_ck", 496 .name = "dpll_core_m2_ck",
460 .parent = &dpll_core_ck, 497 .parent = &dpll_core_ck,
461 .clksel = dpll_core_m6_div, 498 .clksel = dpll_core_m2_div,
462 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, 499 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
463 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 500 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
464 .ops = &clkops_null, 501 .ops = &clkops_omap4_dpllmx_ops,
465 .recalc = &omap2_clksel_recalc, 502 .recalc = &omap2_clksel_recalc,
466 .round_rate = &omap2_clksel_round_rate, 503 .round_rate = &omap2_clksel_round_rate,
467 .set_rate = &omap2_clksel_set_rate, 504 .set_rate = &omap2_clksel_set_rate,
@@ -471,29 +508,30 @@ static struct clk ddrphy_ck = {
471 .name = "ddrphy_ck", 508 .name = "ddrphy_ck",
472 .parent = &dpll_core_m2_ck, 509 .parent = &dpll_core_m2_ck,
473 .ops = &clkops_null, 510 .ops = &clkops_null,
474 .recalc = &followparent_recalc, 511 .fixed_div = 2,
512 .recalc = &omap_fixed_divisor_recalc,
475}; 513};
476 514
477static struct clk dpll_core_m5_ck = { 515static struct clk dpll_core_m5x2_ck = {
478 .name = "dpll_core_m5_ck", 516 .name = "dpll_core_m5x2_ck",
479 .parent = &dpll_core_ck, 517 .parent = &dpll_core_x2_ck,
480 .clksel = dpll_core_m6_div, 518 .clksel = dpll_core_m6x2_div,
481 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, 519 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
482 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 520 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
483 .ops = &clkops_null, 521 .ops = &clkops_omap4_dpllmx_ops,
484 .recalc = &omap2_clksel_recalc, 522 .recalc = &omap2_clksel_recalc,
485 .round_rate = &omap2_clksel_round_rate, 523 .round_rate = &omap2_clksel_round_rate,
486 .set_rate = &omap2_clksel_set_rate, 524 .set_rate = &omap2_clksel_set_rate,
487}; 525};
488 526
489static const struct clksel div_core_div[] = { 527static const struct clksel div_core_div[] = {
490 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates }, 528 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
491 { .parent = NULL }, 529 { .parent = NULL },
492}; 530};
493 531
494static struct clk div_core_ck = { 532static struct clk div_core_ck = {
495 .name = "div_core_ck", 533 .name = "div_core_ck",
496 .parent = &dpll_core_m5_ck, 534 .parent = &dpll_core_m5x2_ck,
497 .clksel = div_core_div, 535 .clksel = div_core_div,
498 .clksel_reg = OMAP4430_CM_CLKSEL_CORE, 536 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
499 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, 537 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
@@ -512,13 +550,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
512}; 550};
513 551
514static const struct clksel div_iva_hs_clk_div[] = { 552static const struct clksel div_iva_hs_clk_div[] = {
515 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates }, 553 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
516 { .parent = NULL }, 554 { .parent = NULL },
517}; 555};
518 556
519static struct clk div_iva_hs_clk = { 557static struct clk div_iva_hs_clk = {
520 .name = "div_iva_hs_clk", 558 .name = "div_iva_hs_clk",
521 .parent = &dpll_core_m5_ck, 559 .parent = &dpll_core_m5x2_ck,
522 .clksel = div_iva_hs_clk_div, 560 .clksel = div_iva_hs_clk_div,
523 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, 561 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
524 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, 562 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -530,7 +568,7 @@ static struct clk div_iva_hs_clk = {
530 568
531static struct clk div_mpu_hs_clk = { 569static struct clk div_mpu_hs_clk = {
532 .name = "div_mpu_hs_clk", 570 .name = "div_mpu_hs_clk",
533 .parent = &dpll_core_m5_ck, 571 .parent = &dpll_core_m5x2_ck,
534 .clksel = div_iva_hs_clk_div, 572 .clksel = div_iva_hs_clk_div,
535 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, 573 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
536 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, 574 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -540,13 +578,13 @@ static struct clk div_mpu_hs_clk = {
540 .set_rate = &omap2_clksel_set_rate, 578 .set_rate = &omap2_clksel_set_rate,
541}; 579};
542 580
543static struct clk dpll_core_m4_ck = { 581static struct clk dpll_core_m4x2_ck = {
544 .name = "dpll_core_m4_ck", 582 .name = "dpll_core_m4x2_ck",
545 .parent = &dpll_core_ck, 583 .parent = &dpll_core_x2_ck,
546 .clksel = dpll_core_m6_div, 584 .clksel = dpll_core_m6x2_div,
547 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, 585 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
548 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 586 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
549 .ops = &clkops_null, 587 .ops = &clkops_omap4_dpllmx_ops,
550 .recalc = &omap2_clksel_recalc, 588 .recalc = &omap2_clksel_recalc,
551 .round_rate = &omap2_clksel_round_rate, 589 .round_rate = &omap2_clksel_round_rate,
552 .set_rate = &omap2_clksel_set_rate, 590 .set_rate = &omap2_clksel_set_rate,
@@ -554,65 +592,77 @@ static struct clk dpll_core_m4_ck = {
554 592
555static struct clk dll_clk_div_ck = { 593static struct clk dll_clk_div_ck = {
556 .name = "dll_clk_div_ck", 594 .name = "dll_clk_div_ck",
557 .parent = &dpll_core_m4_ck, 595 .parent = &dpll_core_m4x2_ck,
558 .ops = &clkops_null, 596 .ops = &clkops_null,
559 .recalc = &followparent_recalc, 597 .fixed_div = 2,
598 .recalc = &omap_fixed_divisor_recalc,
599};
600
601static const struct clksel dpll_abe_m2_div[] = {
602 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
603 { .parent = NULL },
560}; 604};
561 605
562static struct clk dpll_abe_m2_ck = { 606static struct clk dpll_abe_m2_ck = {
563 .name = "dpll_abe_m2_ck", 607 .name = "dpll_abe_m2_ck",
564 .parent = &dpll_abe_ck, 608 .parent = &dpll_abe_ck,
565 .clksel = dpll_abe_m3_div, 609 .clksel = dpll_abe_m2_div,
566 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, 610 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
567 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 611 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
568 .ops = &clkops_null, 612 .ops = &clkops_omap4_dpllmx_ops,
569 .recalc = &omap2_clksel_recalc, 613 .recalc = &omap2_clksel_recalc,
570 .round_rate = &omap2_clksel_round_rate, 614 .round_rate = &omap2_clksel_round_rate,
571 .set_rate = &omap2_clksel_set_rate, 615 .set_rate = &omap2_clksel_set_rate,
572}; 616};
573 617
574static struct clk dpll_core_m3_ck = { 618static struct clk dpll_core_m3x2_ck = {
575 .name = "dpll_core_m3_ck", 619 .name = "dpll_core_m3x2_ck",
576 .parent = &dpll_core_ck, 620 .parent = &dpll_core_x2_ck,
577 .clksel = dpll_core_m6_div, 621 .clksel = dpll_core_m6x2_div,
578 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, 622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
579 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
580 .ops = &clkops_null, 624 .ops = &clkops_omap2_dflt,
625 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
626 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
581 .recalc = &omap2_clksel_recalc, 627 .recalc = &omap2_clksel_recalc,
582 .round_rate = &omap2_clksel_round_rate, 628 .round_rate = &omap2_clksel_round_rate,
583 .set_rate = &omap2_clksel_set_rate, 629 .set_rate = &omap2_clksel_set_rate,
584}; 630};
585 631
586static struct clk dpll_core_m7_ck = { 632static struct clk dpll_core_m7x2_ck = {
587 .name = "dpll_core_m7_ck", 633 .name = "dpll_core_m7x2_ck",
588 .parent = &dpll_core_ck, 634 .parent = &dpll_core_x2_ck,
589 .clksel = dpll_core_m6_div, 635 .clksel = dpll_core_m6x2_div,
590 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, 636 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
591 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, 637 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
592 .ops = &clkops_null, 638 .ops = &clkops_omap4_dpllmx_ops,
593 .recalc = &omap2_clksel_recalc, 639 .recalc = &omap2_clksel_recalc,
594 .round_rate = &omap2_clksel_round_rate, 640 .round_rate = &omap2_clksel_round_rate,
595 .set_rate = &omap2_clksel_set_rate, 641 .set_rate = &omap2_clksel_set_rate,
596}; 642};
597 643
598static const struct clksel iva_hsd_byp_clk_mux_sel[] = { 644static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
599 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 645 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
600 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, 646 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
601 { .parent = NULL }, 647 { .parent = NULL },
602}; 648};
603 649
604static struct clk iva_hsd_byp_clk_mux_ck = { 650static struct clk iva_hsd_byp_clk_mux_ck = {
605 .name = "iva_hsd_byp_clk_mux_ck", 651 .name = "iva_hsd_byp_clk_mux_ck",
606 .parent = &dpll_sys_ref_clk, 652 .parent = &sys_clkin_ck,
653 .clksel = iva_hsd_byp_clk_mux_sel,
654 .init = &omap2_init_clksel_parent,
655 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
656 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
607 .ops = &clkops_null, 657 .ops = &clkops_null,
608 .recalc = &followparent_recalc, 658 .recalc = &omap2_clksel_recalc,
609}; 659};
610 660
611/* DPLL_IVA */ 661/* DPLL_IVA */
612static struct dpll_data dpll_iva_dd = { 662static struct dpll_data dpll_iva_dd = {
613 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, 663 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
614 .clk_bypass = &iva_hsd_byp_clk_mux_ck, 664 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
615 .clk_ref = &dpll_sys_ref_clk, 665 .clk_ref = &sys_clkin_ck,
616 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, 666 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
617 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 667 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, 668 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
@@ -630,7 +680,7 @@ static struct dpll_data dpll_iva_dd = {
630 680
631static struct clk dpll_iva_ck = { 681static struct clk dpll_iva_ck = {
632 .name = "dpll_iva_ck", 682 .name = "dpll_iva_ck",
633 .parent = &dpll_sys_ref_clk, 683 .parent = &sys_clkin_ck,
634 .dpll_data = &dpll_iva_dd, 684 .dpll_data = &dpll_iva_dd,
635 .init = &omap2_init_dpll_parent, 685 .init = &omap2_init_dpll_parent,
636 .ops = &clkops_omap3_noncore_dpll_ops, 686 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -639,30 +689,38 @@ static struct clk dpll_iva_ck = {
639 .set_rate = &omap3_noncore_dpll_set_rate, 689 .set_rate = &omap3_noncore_dpll_set_rate,
640}; 690};
641 691
642static const struct clksel dpll_iva_m4_div[] = { 692static struct clk dpll_iva_x2_ck = {
643 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates }, 693 .name = "dpll_iva_x2_ck",
694 .parent = &dpll_iva_ck,
695 .flags = CLOCK_CLKOUTX2,
696 .ops = &clkops_null,
697 .recalc = &omap3_clkoutx2_recalc,
698};
699
700static const struct clksel dpll_iva_m4x2_div[] = {
701 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
644 { .parent = NULL }, 702 { .parent = NULL },
645}; 703};
646 704
647static struct clk dpll_iva_m4_ck = { 705static struct clk dpll_iva_m4x2_ck = {
648 .name = "dpll_iva_m4_ck", 706 .name = "dpll_iva_m4x2_ck",
649 .parent = &dpll_iva_ck, 707 .parent = &dpll_iva_x2_ck,
650 .clksel = dpll_iva_m4_div, 708 .clksel = dpll_iva_m4x2_div,
651 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, 709 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
652 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 710 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
653 .ops = &clkops_null, 711 .ops = &clkops_omap4_dpllmx_ops,
654 .recalc = &omap2_clksel_recalc, 712 .recalc = &omap2_clksel_recalc,
655 .round_rate = &omap2_clksel_round_rate, 713 .round_rate = &omap2_clksel_round_rate,
656 .set_rate = &omap2_clksel_set_rate, 714 .set_rate = &omap2_clksel_set_rate,
657}; 715};
658 716
659static struct clk dpll_iva_m5_ck = { 717static struct clk dpll_iva_m5x2_ck = {
660 .name = "dpll_iva_m5_ck", 718 .name = "dpll_iva_m5x2_ck",
661 .parent = &dpll_iva_ck, 719 .parent = &dpll_iva_x2_ck,
662 .clksel = dpll_iva_m4_div, 720 .clksel = dpll_iva_m4x2_div,
663 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, 721 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
664 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 722 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
665 .ops = &clkops_null, 723 .ops = &clkops_omap4_dpllmx_ops,
666 .recalc = &omap2_clksel_recalc, 724 .recalc = &omap2_clksel_recalc,
667 .round_rate = &omap2_clksel_round_rate, 725 .round_rate = &omap2_clksel_round_rate,
668 .set_rate = &omap2_clksel_set_rate, 726 .set_rate = &omap2_clksel_set_rate,
@@ -672,7 +730,7 @@ static struct clk dpll_iva_m5_ck = {
672static struct dpll_data dpll_mpu_dd = { 730static struct dpll_data dpll_mpu_dd = {
673 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, 731 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
674 .clk_bypass = &div_mpu_hs_clk, 732 .clk_bypass = &div_mpu_hs_clk,
675 .clk_ref = &dpll_sys_ref_clk, 733 .clk_ref = &sys_clkin_ck,
676 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, 734 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
677 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 735 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
678 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, 736 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
@@ -690,7 +748,7 @@ static struct dpll_data dpll_mpu_dd = {
690 748
691static struct clk dpll_mpu_ck = { 749static struct clk dpll_mpu_ck = {
692 .name = "dpll_mpu_ck", 750 .name = "dpll_mpu_ck",
693 .parent = &dpll_sys_ref_clk, 751 .parent = &sys_clkin_ck,
694 .dpll_data = &dpll_mpu_dd, 752 .dpll_data = &dpll_mpu_dd,
695 .init = &omap2_init_dpll_parent, 753 .init = &omap2_init_dpll_parent,
696 .ops = &clkops_omap3_noncore_dpll_ops, 754 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -710,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
710 .clksel = dpll_mpu_m2_div, 768 .clksel = dpll_mpu_m2_div,
711 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, 769 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
712 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 770 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
713 .ops = &clkops_null, 771 .ops = &clkops_omap4_dpllmx_ops,
714 .recalc = &omap2_clksel_recalc, 772 .recalc = &omap2_clksel_recalc,
715 .round_rate = &omap2_clksel_round_rate, 773 .round_rate = &omap2_clksel_round_rate,
716 .set_rate = &omap2_clksel_set_rate, 774 .set_rate = &omap2_clksel_set_rate,
@@ -718,20 +776,21 @@ static struct clk dpll_mpu_m2_ck = {
718 776
719static struct clk per_hs_clk_div_ck = { 777static struct clk per_hs_clk_div_ck = {
720 .name = "per_hs_clk_div_ck", 778 .name = "per_hs_clk_div_ck",
721 .parent = &dpll_abe_m3_ck, 779 .parent = &dpll_abe_m3x2_ck,
722 .ops = &clkops_null, 780 .ops = &clkops_null,
723 .recalc = &followparent_recalc, 781 .fixed_div = 2,
782 .recalc = &omap_fixed_divisor_recalc,
724}; 783};
725 784
726static const struct clksel per_hsd_byp_clk_mux_sel[] = { 785static const struct clksel per_hsd_byp_clk_mux_sel[] = {
727 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 786 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
728 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, 787 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
729 { .parent = NULL }, 788 { .parent = NULL },
730}; 789};
731 790
732static struct clk per_hsd_byp_clk_mux_ck = { 791static struct clk per_hsd_byp_clk_mux_ck = {
733 .name = "per_hsd_byp_clk_mux_ck", 792 .name = "per_hsd_byp_clk_mux_ck",
734 .parent = &dpll_sys_ref_clk, 793 .parent = &sys_clkin_ck,
735 .clksel = per_hsd_byp_clk_mux_sel, 794 .clksel = per_hsd_byp_clk_mux_sel,
736 .init = &omap2_init_clksel_parent, 795 .init = &omap2_init_clksel_parent,
737 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, 796 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
@@ -744,7 +803,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
744static struct dpll_data dpll_per_dd = { 803static struct dpll_data dpll_per_dd = {
745 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, 804 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
746 .clk_bypass = &per_hsd_byp_clk_mux_ck, 805 .clk_bypass = &per_hsd_byp_clk_mux_ck,
747 .clk_ref = &dpll_sys_ref_clk, 806 .clk_ref = &sys_clkin_ck,
748 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, 807 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
749 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 808 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
750 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, 809 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
@@ -762,7 +821,7 @@ static struct dpll_data dpll_per_dd = {
762 821
763static struct clk dpll_per_ck = { 822static struct clk dpll_per_ck = {
764 .name = "dpll_per_ck", 823 .name = "dpll_per_ck",
765 .parent = &dpll_sys_ref_clk, 824 .parent = &sys_clkin_ck,
766 .dpll_data = &dpll_per_dd, 825 .dpll_data = &dpll_per_dd,
767 .init = &omap2_init_dpll_parent, 826 .init = &omap2_init_dpll_parent,
768 .ops = &clkops_omap3_noncore_dpll_ops, 827 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -782,74 +841,95 @@ static struct clk dpll_per_m2_ck = {
782 .clksel = dpll_per_m2_div, 841 .clksel = dpll_per_m2_div,
783 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, 842 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
784 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 843 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
785 .ops = &clkops_null, 844 .ops = &clkops_omap4_dpllmx_ops,
786 .recalc = &omap2_clksel_recalc, 845 .recalc = &omap2_clksel_recalc,
787 .round_rate = &omap2_clksel_round_rate, 846 .round_rate = &omap2_clksel_round_rate,
788 .set_rate = &omap2_clksel_set_rate, 847 .set_rate = &omap2_clksel_set_rate,
789}; 848};
790 849
850static struct clk dpll_per_x2_ck = {
851 .name = "dpll_per_x2_ck",
852 .parent = &dpll_per_ck,
853 .flags = CLOCK_CLKOUTX2,
854 .ops = &clkops_omap4_dpllmx_ops,
855 .recalc = &omap3_clkoutx2_recalc,
856 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
857};
858
859static const struct clksel dpll_per_m2x2_div[] = {
860 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
861 { .parent = NULL },
862};
863
791static struct clk dpll_per_m2x2_ck = { 864static struct clk dpll_per_m2x2_ck = {
792 .name = "dpll_per_m2x2_ck", 865 .name = "dpll_per_m2x2_ck",
793 .parent = &dpll_per_ck, 866 .parent = &dpll_per_x2_ck,
794 .ops = &clkops_null, 867 .clksel = dpll_per_m2x2_div,
795 .recalc = &followparent_recalc, 868 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
869 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
870 .ops = &clkops_omap4_dpllmx_ops,
871 .recalc = &omap2_clksel_recalc,
872 .round_rate = &omap2_clksel_round_rate,
873 .set_rate = &omap2_clksel_set_rate,
796}; 874};
797 875
798static struct clk dpll_per_m3_ck = { 876static struct clk dpll_per_m3x2_ck = {
799 .name = "dpll_per_m3_ck", 877 .name = "dpll_per_m3x2_ck",
800 .parent = &dpll_per_ck, 878 .parent = &dpll_per_x2_ck,
801 .clksel = dpll_per_m2_div, 879 .clksel = dpll_per_m2x2_div,
802 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, 880 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
803 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 881 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
804 .ops = &clkops_null, 882 .ops = &clkops_omap2_dflt,
883 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
884 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
805 .recalc = &omap2_clksel_recalc, 885 .recalc = &omap2_clksel_recalc,
806 .round_rate = &omap2_clksel_round_rate, 886 .round_rate = &omap2_clksel_round_rate,
807 .set_rate = &omap2_clksel_set_rate, 887 .set_rate = &omap2_clksel_set_rate,
808}; 888};
809 889
810static struct clk dpll_per_m4_ck = { 890static struct clk dpll_per_m4x2_ck = {
811 .name = "dpll_per_m4_ck", 891 .name = "dpll_per_m4x2_ck",
812 .parent = &dpll_per_ck, 892 .parent = &dpll_per_x2_ck,
813 .clksel = dpll_per_m2_div, 893 .clksel = dpll_per_m2x2_div,
814 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, 894 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
815 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 895 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
816 .ops = &clkops_null, 896 .ops = &clkops_omap4_dpllmx_ops,
817 .recalc = &omap2_clksel_recalc, 897 .recalc = &omap2_clksel_recalc,
818 .round_rate = &omap2_clksel_round_rate, 898 .round_rate = &omap2_clksel_round_rate,
819 .set_rate = &omap2_clksel_set_rate, 899 .set_rate = &omap2_clksel_set_rate,
820}; 900};
821 901
822static struct clk dpll_per_m5_ck = { 902static struct clk dpll_per_m5x2_ck = {
823 .name = "dpll_per_m5_ck", 903 .name = "dpll_per_m5x2_ck",
824 .parent = &dpll_per_ck, 904 .parent = &dpll_per_x2_ck,
825 .clksel = dpll_per_m2_div, 905 .clksel = dpll_per_m2x2_div,
826 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, 906 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
827 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 907 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
828 .ops = &clkops_null, 908 .ops = &clkops_omap4_dpllmx_ops,
829 .recalc = &omap2_clksel_recalc, 909 .recalc = &omap2_clksel_recalc,
830 .round_rate = &omap2_clksel_round_rate, 910 .round_rate = &omap2_clksel_round_rate,
831 .set_rate = &omap2_clksel_set_rate, 911 .set_rate = &omap2_clksel_set_rate,
832}; 912};
833 913
834static struct clk dpll_per_m6_ck = { 914static struct clk dpll_per_m6x2_ck = {
835 .name = "dpll_per_m6_ck", 915 .name = "dpll_per_m6x2_ck",
836 .parent = &dpll_per_ck, 916 .parent = &dpll_per_x2_ck,
837 .clksel = dpll_per_m2_div, 917 .clksel = dpll_per_m2x2_div,
838 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, 918 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
839 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, 919 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
840 .ops = &clkops_null, 920 .ops = &clkops_omap4_dpllmx_ops,
841 .recalc = &omap2_clksel_recalc, 921 .recalc = &omap2_clksel_recalc,
842 .round_rate = &omap2_clksel_round_rate, 922 .round_rate = &omap2_clksel_round_rate,
843 .set_rate = &omap2_clksel_set_rate, 923 .set_rate = &omap2_clksel_set_rate,
844}; 924};
845 925
846static struct clk dpll_per_m7_ck = { 926static struct clk dpll_per_m7x2_ck = {
847 .name = "dpll_per_m7_ck", 927 .name = "dpll_per_m7x2_ck",
848 .parent = &dpll_per_ck, 928 .parent = &dpll_per_x2_ck,
849 .clksel = dpll_per_m2_div, 929 .clksel = dpll_per_m2x2_div,
850 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, 930 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
851 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, 931 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
852 .ops = &clkops_null, 932 .ops = &clkops_omap4_dpllmx_ops,
853 .recalc = &omap2_clksel_recalc, 933 .recalc = &omap2_clksel_recalc,
854 .round_rate = &omap2_clksel_round_rate, 934 .round_rate = &omap2_clksel_round_rate,
855 .set_rate = &omap2_clksel_set_rate, 935 .set_rate = &omap2_clksel_set_rate,
@@ -858,8 +938,8 @@ static struct clk dpll_per_m7_ck = {
858/* DPLL_UNIPRO */ 938/* DPLL_UNIPRO */
859static struct dpll_data dpll_unipro_dd = { 939static struct dpll_data dpll_unipro_dd = {
860 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, 940 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
861 .clk_bypass = &dpll_sys_ref_clk, 941 .clk_bypass = &sys_clkin_ck,
862 .clk_ref = &dpll_sys_ref_clk, 942 .clk_ref = &sys_clkin_ck,
863 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, 943 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
864 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 944 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
865 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, 945 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
@@ -869,6 +949,7 @@ static struct dpll_data dpll_unipro_dd = {
869 .enable_mask = OMAP4430_DPLL_EN_MASK, 949 .enable_mask = OMAP4430_DPLL_EN_MASK,
870 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 950 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
871 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 951 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
952 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
872 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 953 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
873 .max_divider = OMAP4430_MAX_DPLL_DIV, 954 .max_divider = OMAP4430_MAX_DPLL_DIV,
874 .min_divider = 1, 955 .min_divider = 1,
@@ -877,7 +958,7 @@ static struct dpll_data dpll_unipro_dd = {
877 958
878static struct clk dpll_unipro_ck = { 959static struct clk dpll_unipro_ck = {
879 .name = "dpll_unipro_ck", 960 .name = "dpll_unipro_ck",
880 .parent = &dpll_sys_ref_clk, 961 .parent = &sys_clkin_ck,
881 .dpll_data = &dpll_unipro_dd, 962 .dpll_data = &dpll_unipro_dd,
882 .init = &omap2_init_dpll_parent, 963 .init = &omap2_init_dpll_parent,
883 .ops = &clkops_omap3_noncore_dpll_ops, 964 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -886,18 +967,26 @@ static struct clk dpll_unipro_ck = {
886 .set_rate = &omap3_noncore_dpll_set_rate, 967 .set_rate = &omap3_noncore_dpll_set_rate,
887}; 968};
888 969
970static struct clk dpll_unipro_x2_ck = {
971 .name = "dpll_unipro_x2_ck",
972 .parent = &dpll_unipro_ck,
973 .flags = CLOCK_CLKOUTX2,
974 .ops = &clkops_null,
975 .recalc = &omap3_clkoutx2_recalc,
976};
977
889static const struct clksel dpll_unipro_m2x2_div[] = { 978static const struct clksel dpll_unipro_m2x2_div[] = {
890 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates }, 979 { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
891 { .parent = NULL }, 980 { .parent = NULL },
892}; 981};
893 982
894static struct clk dpll_unipro_m2x2_ck = { 983static struct clk dpll_unipro_m2x2_ck = {
895 .name = "dpll_unipro_m2x2_ck", 984 .name = "dpll_unipro_m2x2_ck",
896 .parent = &dpll_unipro_ck, 985 .parent = &dpll_unipro_x2_ck,
897 .clksel = dpll_unipro_m2x2_div, 986 .clksel = dpll_unipro_m2x2_div,
898 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, 987 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
899 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 988 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
900 .ops = &clkops_null, 989 .ops = &clkops_omap4_dpllmx_ops,
901 .recalc = &omap2_clksel_recalc, 990 .recalc = &omap2_clksel_recalc,
902 .round_rate = &omap2_clksel_round_rate, 991 .round_rate = &omap2_clksel_round_rate,
903 .set_rate = &omap2_clksel_set_rate, 992 .set_rate = &omap2_clksel_set_rate,
@@ -905,16 +994,18 @@ static struct clk dpll_unipro_m2x2_ck = {
905 994
906static struct clk usb_hs_clk_div_ck = { 995static struct clk usb_hs_clk_div_ck = {
907 .name = "usb_hs_clk_div_ck", 996 .name = "usb_hs_clk_div_ck",
908 .parent = &dpll_abe_m3_ck, 997 .parent = &dpll_abe_m3x2_ck,
909 .ops = &clkops_null, 998 .ops = &clkops_null,
910 .recalc = &followparent_recalc, 999 .fixed_div = 3,
1000 .recalc = &omap_fixed_divisor_recalc,
911}; 1001};
912 1002
913/* DPLL_USB */ 1003/* DPLL_USB */
914static struct dpll_data dpll_usb_dd = { 1004static struct dpll_data dpll_usb_dd = {
915 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, 1005 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
916 .clk_bypass = &usb_hs_clk_div_ck, 1006 .clk_bypass = &usb_hs_clk_div_ck,
917 .clk_ref = &dpll_sys_ref_clk, 1007 .flags = DPLL_J_TYPE,
1008 .clk_ref = &sys_clkin_ck,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, 1009 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 1010 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, 1011 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
@@ -927,13 +1018,12 @@ static struct dpll_data dpll_usb_dd = {
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 1018 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV, 1019 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1, 1020 .min_divider = 1,
930 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
931}; 1021};
932 1022
933 1023
934static struct clk dpll_usb_ck = { 1024static struct clk dpll_usb_ck = {
935 .name = "dpll_usb_ck", 1025 .name = "dpll_usb_ck",
936 .parent = &dpll_sys_ref_clk, 1026 .parent = &sys_clkin_ck,
937 .dpll_data = &dpll_usb_dd, 1027 .dpll_data = &dpll_usb_dd,
938 .init = &omap2_init_dpll_parent, 1028 .init = &omap2_init_dpll_parent,
939 .ops = &clkops_omap3_noncore_dpll_ops, 1029 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -945,7 +1035,8 @@ static struct clk dpll_usb_ck = {
945static struct clk dpll_usb_clkdcoldo_ck = { 1035static struct clk dpll_usb_clkdcoldo_ck = {
946 .name = "dpll_usb_clkdcoldo_ck", 1036 .name = "dpll_usb_clkdcoldo_ck",
947 .parent = &dpll_usb_ck, 1037 .parent = &dpll_usb_ck,
948 .ops = &clkops_null, 1038 .ops = &clkops_omap4_dpllmx_ops,
1039 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
949 .recalc = &followparent_recalc, 1040 .recalc = &followparent_recalc,
950}; 1041};
951 1042
@@ -960,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
960 .clksel = dpll_usb_m2_div, 1051 .clksel = dpll_usb_m2_div,
961 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, 1052 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
962 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, 1053 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
963 .ops = &clkops_null, 1054 .ops = &clkops_omap4_dpllmx_ops,
964 .recalc = &omap2_clksel_recalc, 1055 .recalc = &omap2_clksel_recalc,
965 .round_rate = &omap2_clksel_round_rate, 1056 .round_rate = &omap2_clksel_round_rate,
966 .set_rate = &omap2_clksel_set_rate, 1057 .set_rate = &omap2_clksel_set_rate,
@@ -968,7 +1059,7 @@ static struct clk dpll_usb_m2_ck = {
968 1059
969static const struct clksel ducati_clk_mux_sel[] = { 1060static const struct clksel ducati_clk_mux_sel[] = {
970 { .parent = &div_core_ck, .rates = div_1_0_rates }, 1061 { .parent = &div_core_ck, .rates = div_1_0_rates },
971 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates }, 1062 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
972 { .parent = NULL }, 1063 { .parent = NULL },
973}; 1064};
974 1065
@@ -987,21 +1078,24 @@ static struct clk func_12m_fclk = {
987 .name = "func_12m_fclk", 1078 .name = "func_12m_fclk",
988 .parent = &dpll_per_m2x2_ck, 1079 .parent = &dpll_per_m2x2_ck,
989 .ops = &clkops_null, 1080 .ops = &clkops_null,
990 .recalc = &followparent_recalc, 1081 .fixed_div = 16,
1082 .recalc = &omap_fixed_divisor_recalc,
991}; 1083};
992 1084
993static struct clk func_24m_clk = { 1085static struct clk func_24m_clk = {
994 .name = "func_24m_clk", 1086 .name = "func_24m_clk",
995 .parent = &dpll_per_m2_ck, 1087 .parent = &dpll_per_m2_ck,
996 .ops = &clkops_null, 1088 .ops = &clkops_null,
997 .recalc = &followparent_recalc, 1089 .fixed_div = 4,
1090 .recalc = &omap_fixed_divisor_recalc,
998}; 1091};
999 1092
1000static struct clk func_24mc_fclk = { 1093static struct clk func_24mc_fclk = {
1001 .name = "func_24mc_fclk", 1094 .name = "func_24mc_fclk",
1002 .parent = &dpll_per_m2x2_ck, 1095 .parent = &dpll_per_m2x2_ck,
1003 .ops = &clkops_null, 1096 .ops = &clkops_null,
1004 .recalc = &followparent_recalc, 1097 .fixed_div = 8,
1098 .recalc = &omap_fixed_divisor_recalc,
1005}; 1099};
1006 1100
1007static const struct clksel_rate div2_4to8_rates[] = { 1101static const struct clksel_rate div2_4to8_rates[] = {
@@ -1031,7 +1125,8 @@ static struct clk func_48mc_fclk = {
1031 .name = "func_48mc_fclk", 1125 .name = "func_48mc_fclk",
1032 .parent = &dpll_per_m2x2_ck, 1126 .parent = &dpll_per_m2x2_ck,
1033 .ops = &clkops_null, 1127 .ops = &clkops_null,
1034 .recalc = &followparent_recalc, 1128 .fixed_div = 4,
1129 .recalc = &omap_fixed_divisor_recalc,
1035}; 1130};
1036 1131
1037static const struct clksel_rate div2_2to4_rates[] = { 1132static const struct clksel_rate div2_2to4_rates[] = {
@@ -1041,13 +1136,13 @@ static const struct clksel_rate div2_2to4_rates[] = {
1041}; 1136};
1042 1137
1043static const struct clksel func_64m_fclk_div[] = { 1138static const struct clksel func_64m_fclk_div[] = {
1044 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates }, 1139 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1045 { .parent = NULL }, 1140 { .parent = NULL },
1046}; 1141};
1047 1142
1048static struct clk func_64m_fclk = { 1143static struct clk func_64m_fclk = {
1049 .name = "func_64m_fclk", 1144 .name = "func_64m_fclk",
1050 .parent = &dpll_per_m4_ck, 1145 .parent = &dpll_per_m4x2_ck,
1051 .clksel = func_64m_fclk_div, 1146 .clksel = func_64m_fclk_div,
1052 .clksel_reg = OMAP4430_CM_SCALE_FCLK, 1147 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1053 .clksel_mask = OMAP4430_SCALE_FCLK_MASK, 1148 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
@@ -1148,7 +1243,8 @@ static struct clk lp_clk_div_ck = {
1148 .name = "lp_clk_div_ck", 1243 .name = "lp_clk_div_ck",
1149 .parent = &dpll_abe_m2x2_ck, 1244 .parent = &dpll_abe_m2x2_ck,
1150 .ops = &clkops_null, 1245 .ops = &clkops_null,
1151 .recalc = &followparent_recalc, 1246 .fixed_div = 16,
1247 .recalc = &omap_fixed_divisor_recalc,
1152}; 1248};
1153 1249
1154static const struct clksel l4_wkup_clk_mux_sel[] = { 1250static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1216,13 +1312,14 @@ static struct clk per_abe_24m_fclk = {
1216 .name = "per_abe_24m_fclk", 1312 .name = "per_abe_24m_fclk",
1217 .parent = &dpll_abe_m2_ck, 1313 .parent = &dpll_abe_m2_ck,
1218 .ops = &clkops_null, 1314 .ops = &clkops_null,
1219 .recalc = &followparent_recalc, 1315 .fixed_div = 4,
1316 .recalc = &omap_fixed_divisor_recalc,
1220}; 1317};
1221 1318
1222static const struct clksel pmd_stm_clock_mux_sel[] = { 1319static const struct clksel pmd_stm_clock_mux_sel[] = {
1223 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1320 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1224 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, 1321 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1225 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, 1322 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1226 { .parent = NULL }, 1323 { .parent = NULL },
1227}; 1324};
1228 1325
@@ -1240,10 +1337,15 @@ static struct clk pmd_trace_clk_mux_ck = {
1240 .recalc = &followparent_recalc, 1337 .recalc = &followparent_recalc,
1241}; 1338};
1242 1339
1340static const struct clksel syc_clk_div_div[] = {
1341 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1342 { .parent = NULL },
1343};
1344
1243static struct clk syc_clk_div_ck = { 1345static struct clk syc_clk_div_ck = {
1244 .name = "syc_clk_div_ck", 1346 .name = "syc_clk_div_ck",
1245 .parent = &sys_clkin_ck, 1347 .parent = &sys_clkin_ck,
1246 .clksel = dpll_sys_ref_clk_div, 1348 .clksel = syc_clk_div_div,
1247 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, 1349 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1248 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 1350 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1249 .ops = &clkops_null, 1351 .ops = &clkops_null,
@@ -1284,13 +1386,13 @@ static struct clk aess_fck = {
1284 .recalc = &followparent_recalc, 1386 .recalc = &followparent_recalc,
1285}; 1387};
1286 1388
1287static struct clk cust_efuse_fck = { 1389static struct clk bandgap_fclk = {
1288 .name = "cust_efuse_fck", 1390 .name = "bandgap_fclk",
1289 .ops = &clkops_omap2_dflt, 1391 .ops = &clkops_omap2_dflt,
1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, 1392 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1393 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1292 .clkdm_name = "l4_cefuse_clkdm", 1394 .clkdm_name = "l4_wkup_clkdm",
1293 .parent = &sys_clkin_ck, 1395 .parent = &sys_32k_ck,
1294 .recalc = &followparent_recalc, 1396 .recalc = &followparent_recalc,
1295}; 1397};
1296 1398
@@ -1344,6 +1446,56 @@ static struct clk dmic_fck = {
1344 .clkdm_name = "abe_clkdm", 1446 .clkdm_name = "abe_clkdm",
1345}; 1447};
1346 1448
1449static struct clk dsp_fck = {
1450 .name = "dsp_fck",
1451 .ops = &clkops_omap2_dflt,
1452 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1453 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1454 .clkdm_name = "tesla_clkdm",
1455 .parent = &dpll_iva_m4x2_ck,
1456 .recalc = &followparent_recalc,
1457};
1458
1459static struct clk dss_sys_clk = {
1460 .name = "dss_sys_clk",
1461 .ops = &clkops_omap2_dflt,
1462 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1463 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1464 .clkdm_name = "l3_dss_clkdm",
1465 .parent = &syc_clk_div_ck,
1466 .recalc = &followparent_recalc,
1467};
1468
1469static struct clk dss_tv_clk = {
1470 .name = "dss_tv_clk",
1471 .ops = &clkops_omap2_dflt,
1472 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1473 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1474 .clkdm_name = "l3_dss_clkdm",
1475 .parent = &extalt_clkin_ck,
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk dss_dss_clk = {
1480 .name = "dss_dss_clk",
1481 .ops = &clkops_omap2_dflt,
1482 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1483 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1484 .clkdm_name = "l3_dss_clkdm",
1485 .parent = &dpll_per_m5x2_ck,
1486 .recalc = &followparent_recalc,
1487};
1488
1489static struct clk dss_48mhz_clk = {
1490 .name = "dss_48mhz_clk",
1491 .ops = &clkops_omap2_dflt,
1492 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1493 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1494 .clkdm_name = "l3_dss_clkdm",
1495 .parent = &func_48mc_fclk,
1496 .recalc = &followparent_recalc,
1497};
1498
1347static struct clk dss_fck = { 1499static struct clk dss_fck = {
1348 .name = "dss_fck", 1500 .name = "dss_fck",
1349 .ops = &clkops_omap2_dflt, 1501 .ops = &clkops_omap2_dflt,
@@ -1354,18 +1506,18 @@ static struct clk dss_fck = {
1354 .recalc = &followparent_recalc, 1506 .recalc = &followparent_recalc,
1355}; 1507};
1356 1508
1357static struct clk ducati_ick = { 1509static struct clk efuse_ctrl_cust_fck = {
1358 .name = "ducati_ick", 1510 .name = "efuse_ctrl_cust_fck",
1359 .ops = &clkops_omap2_dflt, 1511 .ops = &clkops_omap2_dflt,
1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 1512 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1513 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1362 .clkdm_name = "ducati_clkdm", 1514 .clkdm_name = "l4_cefuse_clkdm",
1363 .parent = &ducati_clk_mux_ck, 1515 .parent = &sys_clkin_ck,
1364 .recalc = &followparent_recalc, 1516 .recalc = &followparent_recalc,
1365}; 1517};
1366 1518
1367static struct clk emif1_ick = { 1519static struct clk emif1_fck = {
1368 .name = "emif1_ick", 1520 .name = "emif1_fck",
1369 .ops = &clkops_omap2_dflt, 1521 .ops = &clkops_omap2_dflt,
1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, 1522 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1523 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1375,8 +1527,8 @@ static struct clk emif1_ick = {
1375 .recalc = &followparent_recalc, 1527 .recalc = &followparent_recalc,
1376}; 1528};
1377 1529
1378static struct clk emif2_ick = { 1530static struct clk emif2_fck = {
1379 .name = "emif2_ick", 1531 .name = "emif2_fck",
1380 .ops = &clkops_omap2_dflt, 1532 .ops = &clkops_omap2_dflt,
1381 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, 1533 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1382 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1534 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1387,14 +1539,14 @@ static struct clk emif2_ick = {
1387}; 1539};
1388 1540
1389static const struct clksel fdif_fclk_div[] = { 1541static const struct clksel fdif_fclk_div[] = {
1390 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates }, 1542 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1391 { .parent = NULL }, 1543 { .parent = NULL },
1392}; 1544};
1393 1545
1394/* Merged fdif_fclk into fdif */ 1546/* Merged fdif_fclk into fdif */
1395static struct clk fdif_fck = { 1547static struct clk fdif_fck = {
1396 .name = "fdif_fck", 1548 .name = "fdif_fck",
1397 .parent = &dpll_per_m4_ck, 1549 .parent = &dpll_per_m4x2_ck,
1398 .clksel = fdif_fclk_div, 1550 .clksel = fdif_fclk_div,
1399 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, 1551 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1400 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, 1552 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
@@ -1407,42 +1559,24 @@ static struct clk fdif_fck = {
1407 .clkdm_name = "iss_clkdm", 1559 .clkdm_name = "iss_clkdm",
1408}; 1560};
1409 1561
1410static const struct clksel per_sgx_fclk_div[] = { 1562static struct clk fpka_fck = {
1411 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, 1563 .name = "fpka_fck",
1412 { .parent = NULL }, 1564 .ops = &clkops_omap2_dflt,
1413}; 1565 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1414 1566 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1415static struct clk per_sgx_fclk = { 1567 .clkdm_name = "l4_secure_clkdm",
1416 .name = "per_sgx_fclk", 1568 .parent = &l4_div_ck,
1417 .parent = &dpll_per_m2x2_ck, 1569 .recalc = &followparent_recalc,
1418 .clksel = per_sgx_fclk_div,
1419 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1420 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1421 .ops = &clkops_null,
1422 .recalc = &omap2_clksel_recalc,
1423 .round_rate = &omap2_clksel_round_rate,
1424 .set_rate = &omap2_clksel_set_rate,
1425};
1426
1427static const struct clksel sgx_clk_mux_sel[] = {
1428 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1429 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1430 { .parent = NULL },
1431}; 1570};
1432 1571
1433/* Merged sgx_clk_mux into gfx */ 1572static struct clk gpio1_dbclk = {
1434static struct clk gfx_fck = { 1573 .name = "gpio1_dbclk",
1435 .name = "gfx_fck",
1436 .parent = &dpll_core_m7_ck,
1437 .clksel = sgx_clk_mux_sel,
1438 .init = &omap2_init_clksel_parent,
1439 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1440 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1441 .ops = &clkops_omap2_dflt, 1574 .ops = &clkops_omap2_dflt,
1442 .recalc = &omap2_clksel_recalc, 1575 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1443 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1576 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1444 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1577 .clkdm_name = "l4_wkup_clkdm",
1445 .clkdm_name = "l3_gfx_clkdm", 1578 .parent = &sys_32k_ck,
1579 .recalc = &followparent_recalc,
1446}; 1580};
1447 1581
1448static struct clk gpio1_ick = { 1582static struct clk gpio1_ick = {
@@ -1455,6 +1589,16 @@ static struct clk gpio1_ick = {
1455 .recalc = &followparent_recalc, 1589 .recalc = &followparent_recalc,
1456}; 1590};
1457 1591
1592static struct clk gpio2_dbclk = {
1593 .name = "gpio2_dbclk",
1594 .ops = &clkops_omap2_dflt,
1595 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1596 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1597 .clkdm_name = "l4_per_clkdm",
1598 .parent = &sys_32k_ck,
1599 .recalc = &followparent_recalc,
1600};
1601
1458static struct clk gpio2_ick = { 1602static struct clk gpio2_ick = {
1459 .name = "gpio2_ick", 1603 .name = "gpio2_ick",
1460 .ops = &clkops_omap2_dflt, 1604 .ops = &clkops_omap2_dflt,
@@ -1465,6 +1609,16 @@ static struct clk gpio2_ick = {
1465 .recalc = &followparent_recalc, 1609 .recalc = &followparent_recalc,
1466}; 1610};
1467 1611
1612static struct clk gpio3_dbclk = {
1613 .name = "gpio3_dbclk",
1614 .ops = &clkops_omap2_dflt,
1615 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1616 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1617 .clkdm_name = "l4_per_clkdm",
1618 .parent = &sys_32k_ck,
1619 .recalc = &followparent_recalc,
1620};
1621
1468static struct clk gpio3_ick = { 1622static struct clk gpio3_ick = {
1469 .name = "gpio3_ick", 1623 .name = "gpio3_ick",
1470 .ops = &clkops_omap2_dflt, 1624 .ops = &clkops_omap2_dflt,
@@ -1475,6 +1629,16 @@ static struct clk gpio3_ick = {
1475 .recalc = &followparent_recalc, 1629 .recalc = &followparent_recalc,
1476}; 1630};
1477 1631
1632static struct clk gpio4_dbclk = {
1633 .name = "gpio4_dbclk",
1634 .ops = &clkops_omap2_dflt,
1635 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1636 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1637 .clkdm_name = "l4_per_clkdm",
1638 .parent = &sys_32k_ck,
1639 .recalc = &followparent_recalc,
1640};
1641
1478static struct clk gpio4_ick = { 1642static struct clk gpio4_ick = {
1479 .name = "gpio4_ick", 1643 .name = "gpio4_ick",
1480 .ops = &clkops_omap2_dflt, 1644 .ops = &clkops_omap2_dflt,
@@ -1485,6 +1649,16 @@ static struct clk gpio4_ick = {
1485 .recalc = &followparent_recalc, 1649 .recalc = &followparent_recalc,
1486}; 1650};
1487 1651
1652static struct clk gpio5_dbclk = {
1653 .name = "gpio5_dbclk",
1654 .ops = &clkops_omap2_dflt,
1655 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1656 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1657 .clkdm_name = "l4_per_clkdm",
1658 .parent = &sys_32k_ck,
1659 .recalc = &followparent_recalc,
1660};
1661
1488static struct clk gpio5_ick = { 1662static struct clk gpio5_ick = {
1489 .name = "gpio5_ick", 1663 .name = "gpio5_ick",
1490 .ops = &clkops_omap2_dflt, 1664 .ops = &clkops_omap2_dflt,
@@ -1495,6 +1669,16 @@ static struct clk gpio5_ick = {
1495 .recalc = &followparent_recalc, 1669 .recalc = &followparent_recalc,
1496}; 1670};
1497 1671
1672static struct clk gpio6_dbclk = {
1673 .name = "gpio6_dbclk",
1674 .ops = &clkops_omap2_dflt,
1675 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1676 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1677 .clkdm_name = "l4_per_clkdm",
1678 .parent = &sys_32k_ck,
1679 .recalc = &followparent_recalc,
1680};
1681
1498static struct clk gpio6_ick = { 1682static struct clk gpio6_ick = {
1499 .name = "gpio6_ick", 1683 .name = "gpio6_ick",
1500 .ops = &clkops_omap2_dflt, 1684 .ops = &clkops_omap2_dflt,
@@ -1515,214 +1699,25 @@ static struct clk gpmc_ick = {
1515 .recalc = &followparent_recalc, 1699 .recalc = &followparent_recalc,
1516}; 1700};
1517 1701
1518static const struct clksel dmt1_clk_mux_sel[] = { 1702static const struct clksel sgx_clk_mux_sel[] = {
1519 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1703 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1520 { .parent = &sys_32k_ck, .rates = div_1_1_rates }, 1704 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1521 { .parent = NULL },
1522};
1523
1524/*
1525 * Merged dmt1_clk_mux into gptimer1
1526 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
1527 */
1528static struct clk gpt1_fck = {
1529 .name = "gpt1_fck",
1530 .parent = &sys_clkin_ck,
1531 .clksel = dmt1_clk_mux_sel,
1532 .init = &omap2_init_clksel_parent,
1533 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1534 .clksel_mask = OMAP4430_CLKSEL_MASK,
1535 .ops = &clkops_omap2_dflt,
1536 .recalc = &omap2_clksel_recalc,
1537 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1538 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1539 .clkdm_name = "l4_wkup_clkdm",
1540};
1541
1542/*
1543 * Merged cm2_dm10_mux into gptimer10
1544 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1545 */
1546static struct clk gpt10_fck = {
1547 .name = "gpt10_fck",
1548 .parent = &sys_clkin_ck,
1549 .clksel = dmt1_clk_mux_sel,
1550 .init = &omap2_init_clksel_parent,
1551 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1552 .clksel_mask = OMAP4430_CLKSEL_MASK,
1553 .ops = &clkops_omap2_dflt,
1554 .recalc = &omap2_clksel_recalc,
1555 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1556 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1557 .clkdm_name = "l4_per_clkdm",
1558};
1559
1560/*
1561 * Merged cm2_dm11_mux into gptimer11
1562 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1563 */
1564static struct clk gpt11_fck = {
1565 .name = "gpt11_fck",
1566 .parent = &sys_clkin_ck,
1567 .clksel = dmt1_clk_mux_sel,
1568 .init = &omap2_init_clksel_parent,
1569 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1571 .ops = &clkops_omap2_dflt,
1572 .recalc = &omap2_clksel_recalc,
1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1575 .clkdm_name = "l4_per_clkdm",
1576};
1577
1578/*
1579 * Merged cm2_dm2_mux into gptimer2
1580 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1581 */
1582static struct clk gpt2_fck = {
1583 .name = "gpt2_fck",
1584 .parent = &sys_clkin_ck,
1585 .clksel = dmt1_clk_mux_sel,
1586 .init = &omap2_init_clksel_parent,
1587 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1588 .clksel_mask = OMAP4430_CLKSEL_MASK,
1589 .ops = &clkops_omap2_dflt,
1590 .recalc = &omap2_clksel_recalc,
1591 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1593 .clkdm_name = "l4_per_clkdm",
1594};
1595
1596/*
1597 * Merged cm2_dm3_mux into gptimer3
1598 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1599 */
1600static struct clk gpt3_fck = {
1601 .name = "gpt3_fck",
1602 .parent = &sys_clkin_ck,
1603 .clksel = dmt1_clk_mux_sel,
1604 .init = &omap2_init_clksel_parent,
1605 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1606 .clksel_mask = OMAP4430_CLKSEL_MASK,
1607 .ops = &clkops_omap2_dflt,
1608 .recalc = &omap2_clksel_recalc,
1609 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1610 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1611 .clkdm_name = "l4_per_clkdm",
1612};
1613
1614/*
1615 * Merged cm2_dm4_mux into gptimer4
1616 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1617 */
1618static struct clk gpt4_fck = {
1619 .name = "gpt4_fck",
1620 .parent = &sys_clkin_ck,
1621 .clksel = dmt1_clk_mux_sel,
1622 .init = &omap2_init_clksel_parent,
1623 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1624 .clksel_mask = OMAP4430_CLKSEL_MASK,
1625 .ops = &clkops_omap2_dflt,
1626 .recalc = &omap2_clksel_recalc,
1627 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1628 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1629 .clkdm_name = "l4_per_clkdm",
1630};
1631
1632static const struct clksel timer5_sync_mux_sel[] = {
1633 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1634 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1635 { .parent = NULL }, 1705 { .parent = NULL },
1636}; 1706};
1637 1707
1638/* 1708/* Merged sgx_clk_mux into gpu */
1639 * Merged timer5_sync_mux into gptimer5 1709static struct clk gpu_fck = {
1640 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention 1710 .name = "gpu_fck",
1641 */ 1711 .parent = &dpll_core_m7x2_ck,
1642static struct clk gpt5_fck = { 1712 .clksel = sgx_clk_mux_sel,
1643 .name = "gpt5_fck",
1644 .parent = &syc_clk_div_ck,
1645 .clksel = timer5_sync_mux_sel,
1646 .init = &omap2_init_clksel_parent,
1647 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1648 .clksel_mask = OMAP4430_CLKSEL_MASK,
1649 .ops = &clkops_omap2_dflt,
1650 .recalc = &omap2_clksel_recalc,
1651 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1653 .clkdm_name = "abe_clkdm",
1654};
1655
1656/*
1657 * Merged timer6_sync_mux into gptimer6
1658 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1659 */
1660static struct clk gpt6_fck = {
1661 .name = "gpt6_fck",
1662 .parent = &syc_clk_div_ck,
1663 .clksel = timer5_sync_mux_sel,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1667 .ops = &clkops_omap2_dflt,
1668 .recalc = &omap2_clksel_recalc,
1669 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "abe_clkdm",
1672};
1673
1674/*
1675 * Merged timer7_sync_mux into gptimer7
1676 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1677 */
1678static struct clk gpt7_fck = {
1679 .name = "gpt7_fck",
1680 .parent = &syc_clk_div_ck,
1681 .clksel = timer5_sync_mux_sel,
1682 .init = &omap2_init_clksel_parent,
1683 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1684 .clksel_mask = OMAP4430_CLKSEL_MASK,
1685 .ops = &clkops_omap2_dflt,
1686 .recalc = &omap2_clksel_recalc,
1687 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1688 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1689 .clkdm_name = "abe_clkdm",
1690};
1691
1692/*
1693 * Merged timer8_sync_mux into gptimer8
1694 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1695 */
1696static struct clk gpt8_fck = {
1697 .name = "gpt8_fck",
1698 .parent = &syc_clk_div_ck,
1699 .clksel = timer5_sync_mux_sel,
1700 .init = &omap2_init_clksel_parent,
1701 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1702 .clksel_mask = OMAP4430_CLKSEL_MASK,
1703 .ops = &clkops_omap2_dflt,
1704 .recalc = &omap2_clksel_recalc,
1705 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1706 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1707 .clkdm_name = "abe_clkdm",
1708};
1709
1710/*
1711 * Merged cm2_dm9_mux into gptimer9
1712 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1713 */
1714static struct clk gpt9_fck = {
1715 .name = "gpt9_fck",
1716 .parent = &sys_clkin_ck,
1717 .clksel = dmt1_clk_mux_sel,
1718 .init = &omap2_init_clksel_parent, 1713 .init = &omap2_init_clksel_parent,
1719 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1714 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1720 .clksel_mask = OMAP4430_CLKSEL_MASK, 1715 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1721 .ops = &clkops_omap2_dflt, 1716 .ops = &clkops_omap2_dflt,
1722 .recalc = &omap2_clksel_recalc, 1717 .recalc = &omap2_clksel_recalc,
1723 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1718 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1724 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1719 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1725 .clkdm_name = "l4_per_clkdm", 1720 .clkdm_name = "l3_gfx_clkdm",
1726}; 1721};
1727 1722
1728static struct clk hdq1w_fck = { 1723static struct clk hdq1w_fck = {
@@ -1735,11 +1730,16 @@ static struct clk hdq1w_fck = {
1735 .recalc = &followparent_recalc, 1730 .recalc = &followparent_recalc,
1736}; 1731};
1737 1732
1733static const struct clksel hsi_fclk_div[] = {
1734 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1735 { .parent = NULL },
1736};
1737
1738/* Merged hsi_fclk into hsi */ 1738/* Merged hsi_fclk into hsi */
1739static struct clk hsi_ick = { 1739static struct clk hsi_fck = {
1740 .name = "hsi_ick", 1740 .name = "hsi_fck",
1741 .parent = &dpll_per_m2x2_ck, 1741 .parent = &dpll_per_m2x2_ck,
1742 .clksel = per_sgx_fclk_div, 1742 .clksel = hsi_fclk_div,
1743 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1743 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1744 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, 1744 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1745 .ops = &clkops_omap2_dflt, 1745 .ops = &clkops_omap2_dflt,
@@ -1791,6 +1791,26 @@ static struct clk i2c4_fck = {
1791 .recalc = &followparent_recalc, 1791 .recalc = &followparent_recalc,
1792}; 1792};
1793 1793
1794static struct clk ipu_fck = {
1795 .name = "ipu_fck",
1796 .ops = &clkops_omap2_dflt,
1797 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1798 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1799 .clkdm_name = "ducati_clkdm",
1800 .parent = &ducati_clk_mux_ck,
1801 .recalc = &followparent_recalc,
1802};
1803
1804static struct clk iss_ctrlclk = {
1805 .name = "iss_ctrlclk",
1806 .ops = &clkops_omap2_dflt,
1807 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1808 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1809 .clkdm_name = "iss_clkdm",
1810 .parent = &func_96m_fclk,
1811 .recalc = &followparent_recalc,
1812};
1813
1794static struct clk iss_fck = { 1814static struct clk iss_fck = {
1795 .name = "iss_fck", 1815 .name = "iss_fck",
1796 .ops = &clkops_omap2_dflt, 1816 .ops = &clkops_omap2_dflt,
@@ -1801,18 +1821,18 @@ static struct clk iss_fck = {
1801 .recalc = &followparent_recalc, 1821 .recalc = &followparent_recalc,
1802}; 1822};
1803 1823
1804static struct clk ivahd_ick = { 1824static struct clk iva_fck = {
1805 .name = "ivahd_ick", 1825 .name = "iva_fck",
1806 .ops = &clkops_omap2_dflt, 1826 .ops = &clkops_omap2_dflt,
1807 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1827 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1808 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1828 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1809 .clkdm_name = "ivahd_clkdm", 1829 .clkdm_name = "ivahd_clkdm",
1810 .parent = &dpll_iva_m5_ck, 1830 .parent = &dpll_iva_m5x2_ck,
1811 .recalc = &followparent_recalc, 1831 .recalc = &followparent_recalc,
1812}; 1832};
1813 1833
1814static struct clk keyboard_fck = { 1834static struct clk kbd_fck = {
1815 .name = "keyboard_fck", 1835 .name = "kbd_fck",
1816 .ops = &clkops_omap2_dflt, 1836 .ops = &clkops_omap2_dflt,
1817 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 1837 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1818 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1838 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1821,22 +1841,24 @@ static struct clk keyboard_fck = {
1821 .recalc = &followparent_recalc, 1841 .recalc = &followparent_recalc,
1822}; 1842};
1823 1843
1824static struct clk l3_instr_interconnect_ick = { 1844static struct clk l3_instr_ick = {
1825 .name = "l3_instr_interconnect_ick", 1845 .name = "l3_instr_ick",
1826 .ops = &clkops_omap2_dflt, 1846 .ops = &clkops_omap2_dflt,
1827 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1847 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1828 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1848 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1829 .clkdm_name = "l3_instr_clkdm", 1849 .clkdm_name = "l3_instr_clkdm",
1850 .flags = ENABLE_ON_INIT,
1830 .parent = &l3_div_ck, 1851 .parent = &l3_div_ck,
1831 .recalc = &followparent_recalc, 1852 .recalc = &followparent_recalc,
1832}; 1853};
1833 1854
1834static struct clk l3_interconnect_3_ick = { 1855static struct clk l3_main_3_ick = {
1835 .name = "l3_interconnect_3_ick", 1856 .name = "l3_main_3_ick",
1836 .ops = &clkops_omap2_dflt, 1857 .ops = &clkops_omap2_dflt,
1837 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1858 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1838 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1859 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1839 .clkdm_name = "l3_instr_clkdm", 1860 .clkdm_name = "l3_instr_clkdm",
1861 .flags = ENABLE_ON_INIT,
1840 .parent = &l3_div_ck, 1862 .parent = &l3_div_ck,
1841 .recalc = &followparent_recalc, 1863 .recalc = &followparent_recalc,
1842}; 1864};
@@ -2005,6 +2027,16 @@ static struct clk mcbsp4_fck = {
2005 .clkdm_name = "l4_per_clkdm", 2027 .clkdm_name = "l4_per_clkdm",
2006}; 2028};
2007 2029
2030static struct clk mcpdm_fck = {
2031 .name = "mcpdm_fck",
2032 .ops = &clkops_omap2_dflt,
2033 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2034 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2035 .clkdm_name = "abe_clkdm",
2036 .parent = &pad_clks_ck,
2037 .recalc = &followparent_recalc,
2038};
2039
2008static struct clk mcspi1_fck = { 2040static struct clk mcspi1_fck = {
2009 .name = "mcspi1_fck", 2041 .name = "mcspi1_fck",
2010 .ops = &clkops_omap2_dflt, 2042 .ops = &clkops_omap2_dflt,
@@ -2105,33 +2137,34 @@ static struct clk mmc5_fck = {
2105 .recalc = &followparent_recalc, 2137 .recalc = &followparent_recalc,
2106}; 2138};
2107 2139
2108static struct clk ocp_wp1_ick = { 2140static struct clk ocp2scp_usb_phy_phy_48m = {
2109 .name = "ocp_wp1_ick", 2141 .name = "ocp2scp_usb_phy_phy_48m",
2110 .ops = &clkops_omap2_dflt, 2142 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2143 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2112 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2144 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2113 .clkdm_name = "l3_instr_clkdm", 2145 .clkdm_name = "l3_init_clkdm",
2114 .parent = &l3_div_ck, 2146 .parent = &func_48m_fclk,
2115 .recalc = &followparent_recalc, 2147 .recalc = &followparent_recalc,
2116}; 2148};
2117 2149
2118static struct clk pdm_fck = { 2150static struct clk ocp2scp_usb_phy_ick = {
2119 .name = "pdm_fck", 2151 .name = "ocp2scp_usb_phy_ick",
2120 .ops = &clkops_omap2_dflt, 2152 .ops = &clkops_omap2_dflt,
2121 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 2153 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2122 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2154 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2123 .clkdm_name = "abe_clkdm", 2155 .clkdm_name = "l3_init_clkdm",
2124 .parent = &pad_clks_ck, 2156 .parent = &l4_div_ck,
2125 .recalc = &followparent_recalc, 2157 .recalc = &followparent_recalc,
2126}; 2158};
2127 2159
2128static struct clk pkaeip29_fck = { 2160static struct clk ocp_wp_noc_ick = {
2129 .name = "pkaeip29_fck", 2161 .name = "ocp_wp_noc_ick",
2130 .ops = &clkops_omap2_dflt, 2162 .ops = &clkops_omap2_dflt,
2131 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, 2163 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2164 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2133 .clkdm_name = "l4_secure_clkdm", 2165 .clkdm_name = "l3_instr_clkdm",
2134 .parent = &l4_div_ck, 2166 .flags = ENABLE_ON_INIT,
2167 .parent = &l3_div_ck,
2135 .recalc = &followparent_recalc, 2168 .recalc = &followparent_recalc,
2136}; 2169};
2137 2170
@@ -2145,8 +2178,8 @@ static struct clk rng_ick = {
2145 .recalc = &followparent_recalc, 2178 .recalc = &followparent_recalc,
2146}; 2179};
2147 2180
2148static struct clk sha2md51_fck = { 2181static struct clk sha2md5_fck = {
2149 .name = "sha2md51_fck", 2182 .name = "sha2md5_fck",
2150 .ops = &clkops_omap2_dflt, 2183 .ops = &clkops_omap2_dflt,
2151 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 2184 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2152 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2185 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2155,13 +2188,53 @@ static struct clk sha2md51_fck = {
2155 .recalc = &followparent_recalc, 2188 .recalc = &followparent_recalc,
2156}; 2189};
2157 2190
2158static struct clk sl2_ick = { 2191static struct clk sl2if_ick = {
2159 .name = "sl2_ick", 2192 .name = "sl2if_ick",
2160 .ops = &clkops_omap2_dflt, 2193 .ops = &clkops_omap2_dflt,
2161 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 2194 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2162 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2195 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2163 .clkdm_name = "ivahd_clkdm", 2196 .clkdm_name = "ivahd_clkdm",
2164 .parent = &dpll_iva_m5_ck, 2197 .parent = &dpll_iva_m5x2_ck,
2198 .recalc = &followparent_recalc,
2199};
2200
2201static struct clk slimbus1_fclk_1 = {
2202 .name = "slimbus1_fclk_1",
2203 .ops = &clkops_omap2_dflt,
2204 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2205 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2206 .clkdm_name = "abe_clkdm",
2207 .parent = &func_24m_clk,
2208 .recalc = &followparent_recalc,
2209};
2210
2211static struct clk slimbus1_fclk_0 = {
2212 .name = "slimbus1_fclk_0",
2213 .ops = &clkops_omap2_dflt,
2214 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2215 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2216 .clkdm_name = "abe_clkdm",
2217 .parent = &abe_24m_fclk,
2218 .recalc = &followparent_recalc,
2219};
2220
2221static struct clk slimbus1_fclk_2 = {
2222 .name = "slimbus1_fclk_2",
2223 .ops = &clkops_omap2_dflt,
2224 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2225 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2226 .clkdm_name = "abe_clkdm",
2227 .parent = &pad_clks_ck,
2228 .recalc = &followparent_recalc,
2229};
2230
2231static struct clk slimbus1_slimbus_clk = {
2232 .name = "slimbus1_slimbus_clk",
2233 .ops = &clkops_omap2_dflt,
2234 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2235 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2236 .clkdm_name = "abe_clkdm",
2237 .parent = &slimbus_clk,
2165 .recalc = &followparent_recalc, 2238 .recalc = &followparent_recalc,
2166}; 2239};
2167 2240
@@ -2175,6 +2248,36 @@ static struct clk slimbus1_fck = {
2175 .recalc = &followparent_recalc, 2248 .recalc = &followparent_recalc,
2176}; 2249};
2177 2250
2251static struct clk slimbus2_fclk_1 = {
2252 .name = "slimbus2_fclk_1",
2253 .ops = &clkops_omap2_dflt,
2254 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2255 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2256 .clkdm_name = "l4_per_clkdm",
2257 .parent = &per_abe_24m_fclk,
2258 .recalc = &followparent_recalc,
2259};
2260
2261static struct clk slimbus2_fclk_0 = {
2262 .name = "slimbus2_fclk_0",
2263 .ops = &clkops_omap2_dflt,
2264 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2265 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2266 .clkdm_name = "l4_per_clkdm",
2267 .parent = &func_24mc_fclk,
2268 .recalc = &followparent_recalc,
2269};
2270
2271static struct clk slimbus2_slimbus_clk = {
2272 .name = "slimbus2_slimbus_clk",
2273 .ops = &clkops_omap2_dflt,
2274 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2275 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2276 .clkdm_name = "l4_per_clkdm",
2277 .parent = &pad_slimbus_core_clks_ck,
2278 .recalc = &followparent_recalc,
2279};
2280
2178static struct clk slimbus2_fck = { 2281static struct clk slimbus2_fck = {
2179 .name = "slimbus2_fck", 2282 .name = "slimbus2_fck",
2180 .ops = &clkops_omap2_dflt, 2283 .ops = &clkops_omap2_dflt,
@@ -2185,8 +2288,8 @@ static struct clk slimbus2_fck = {
2185 .recalc = &followparent_recalc, 2288 .recalc = &followparent_recalc,
2186}; 2289};
2187 2290
2188static struct clk sr_core_fck = { 2291static struct clk smartreflex_core_fck = {
2189 .name = "sr_core_fck", 2292 .name = "smartreflex_core_fck",
2190 .ops = &clkops_omap2_dflt, 2293 .ops = &clkops_omap2_dflt,
2191 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 2294 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2192 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2295 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2195,8 +2298,8 @@ static struct clk sr_core_fck = {
2195 .recalc = &followparent_recalc, 2298 .recalc = &followparent_recalc,
2196}; 2299};
2197 2300
2198static struct clk sr_iva_fck = { 2301static struct clk smartreflex_iva_fck = {
2199 .name = "sr_iva_fck", 2302 .name = "smartreflex_iva_fck",
2200 .ops = &clkops_omap2_dflt, 2303 .ops = &clkops_omap2_dflt,
2201 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 2304 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2202 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2305 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2205,8 +2308,8 @@ static struct clk sr_iva_fck = {
2205 .recalc = &followparent_recalc, 2308 .recalc = &followparent_recalc,
2206}; 2309};
2207 2310
2208static struct clk sr_mpu_fck = { 2311static struct clk smartreflex_mpu_fck = {
2209 .name = "sr_mpu_fck", 2312 .name = "smartreflex_mpu_fck",
2210 .ops = &clkops_omap2_dflt, 2313 .ops = &clkops_omap2_dflt,
2211 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 2314 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2212 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2315 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2215,14 +2318,175 @@ static struct clk sr_mpu_fck = {
2215 .recalc = &followparent_recalc, 2318 .recalc = &followparent_recalc,
2216}; 2319};
2217 2320
2218static struct clk tesla_ick = { 2321/* Merged dmt1_clk_mux into timer1 */
2219 .name = "tesla_ick", 2322static struct clk timer1_fck = {
2323 .name = "timer1_fck",
2324 .parent = &sys_clkin_ck,
2325 .clksel = abe_dpll_bypass_clk_mux_sel,
2326 .init = &omap2_init_clksel_parent,
2327 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2328 .clksel_mask = OMAP4430_CLKSEL_MASK,
2220 .ops = &clkops_omap2_dflt, 2329 .ops = &clkops_omap2_dflt,
2221 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 2330 .recalc = &omap2_clksel_recalc,
2222 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2331 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2223 .clkdm_name = "tesla_clkdm", 2332 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2224 .parent = &dpll_iva_m4_ck, 2333 .clkdm_name = "l4_wkup_clkdm",
2225 .recalc = &followparent_recalc, 2334};
2335
2336/* Merged cm2_dm10_mux into timer10 */
2337static struct clk timer10_fck = {
2338 .name = "timer10_fck",
2339 .parent = &sys_clkin_ck,
2340 .clksel = abe_dpll_bypass_clk_mux_sel,
2341 .init = &omap2_init_clksel_parent,
2342 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2343 .clksel_mask = OMAP4430_CLKSEL_MASK,
2344 .ops = &clkops_omap2_dflt,
2345 .recalc = &omap2_clksel_recalc,
2346 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2347 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2348 .clkdm_name = "l4_per_clkdm",
2349};
2350
2351/* Merged cm2_dm11_mux into timer11 */
2352static struct clk timer11_fck = {
2353 .name = "timer11_fck",
2354 .parent = &sys_clkin_ck,
2355 .clksel = abe_dpll_bypass_clk_mux_sel,
2356 .init = &omap2_init_clksel_parent,
2357 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2358 .clksel_mask = OMAP4430_CLKSEL_MASK,
2359 .ops = &clkops_omap2_dflt,
2360 .recalc = &omap2_clksel_recalc,
2361 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2362 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2363 .clkdm_name = "l4_per_clkdm",
2364};
2365
2366/* Merged cm2_dm2_mux into timer2 */
2367static struct clk timer2_fck = {
2368 .name = "timer2_fck",
2369 .parent = &sys_clkin_ck,
2370 .clksel = abe_dpll_bypass_clk_mux_sel,
2371 .init = &omap2_init_clksel_parent,
2372 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2373 .clksel_mask = OMAP4430_CLKSEL_MASK,
2374 .ops = &clkops_omap2_dflt,
2375 .recalc = &omap2_clksel_recalc,
2376 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2377 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2378 .clkdm_name = "l4_per_clkdm",
2379};
2380
2381/* Merged cm2_dm3_mux into timer3 */
2382static struct clk timer3_fck = {
2383 .name = "timer3_fck",
2384 .parent = &sys_clkin_ck,
2385 .clksel = abe_dpll_bypass_clk_mux_sel,
2386 .init = &omap2_init_clksel_parent,
2387 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2388 .clksel_mask = OMAP4430_CLKSEL_MASK,
2389 .ops = &clkops_omap2_dflt,
2390 .recalc = &omap2_clksel_recalc,
2391 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2392 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2393 .clkdm_name = "l4_per_clkdm",
2394};
2395
2396/* Merged cm2_dm4_mux into timer4 */
2397static struct clk timer4_fck = {
2398 .name = "timer4_fck",
2399 .parent = &sys_clkin_ck,
2400 .clksel = abe_dpll_bypass_clk_mux_sel,
2401 .init = &omap2_init_clksel_parent,
2402 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2403 .clksel_mask = OMAP4430_CLKSEL_MASK,
2404 .ops = &clkops_omap2_dflt,
2405 .recalc = &omap2_clksel_recalc,
2406 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2407 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2408 .clkdm_name = "l4_per_clkdm",
2409};
2410
2411static const struct clksel timer5_sync_mux_sel[] = {
2412 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2413 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2414 { .parent = NULL },
2415};
2416
2417/* Merged timer5_sync_mux into timer5 */
2418static struct clk timer5_fck = {
2419 .name = "timer5_fck",
2420 .parent = &syc_clk_div_ck,
2421 .clksel = timer5_sync_mux_sel,
2422 .init = &omap2_init_clksel_parent,
2423 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2424 .clksel_mask = OMAP4430_CLKSEL_MASK,
2425 .ops = &clkops_omap2_dflt,
2426 .recalc = &omap2_clksel_recalc,
2427 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2428 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2429 .clkdm_name = "abe_clkdm",
2430};
2431
2432/* Merged timer6_sync_mux into timer6 */
2433static struct clk timer6_fck = {
2434 .name = "timer6_fck",
2435 .parent = &syc_clk_div_ck,
2436 .clksel = timer5_sync_mux_sel,
2437 .init = &omap2_init_clksel_parent,
2438 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2439 .clksel_mask = OMAP4430_CLKSEL_MASK,
2440 .ops = &clkops_omap2_dflt,
2441 .recalc = &omap2_clksel_recalc,
2442 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2443 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2444 .clkdm_name = "abe_clkdm",
2445};
2446
2447/* Merged timer7_sync_mux into timer7 */
2448static struct clk timer7_fck = {
2449 .name = "timer7_fck",
2450 .parent = &syc_clk_div_ck,
2451 .clksel = timer5_sync_mux_sel,
2452 .init = &omap2_init_clksel_parent,
2453 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2454 .clksel_mask = OMAP4430_CLKSEL_MASK,
2455 .ops = &clkops_omap2_dflt,
2456 .recalc = &omap2_clksel_recalc,
2457 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2458 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2459 .clkdm_name = "abe_clkdm",
2460};
2461
2462/* Merged timer8_sync_mux into timer8 */
2463static struct clk timer8_fck = {
2464 .name = "timer8_fck",
2465 .parent = &syc_clk_div_ck,
2466 .clksel = timer5_sync_mux_sel,
2467 .init = &omap2_init_clksel_parent,
2468 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2469 .clksel_mask = OMAP4430_CLKSEL_MASK,
2470 .ops = &clkops_omap2_dflt,
2471 .recalc = &omap2_clksel_recalc,
2472 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2473 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2474 .clkdm_name = "abe_clkdm",
2475};
2476
2477/* Merged cm2_dm9_mux into timer9 */
2478static struct clk timer9_fck = {
2479 .name = "timer9_fck",
2480 .parent = &sys_clkin_ck,
2481 .clksel = abe_dpll_bypass_clk_mux_sel,
2482 .init = &omap2_init_clksel_parent,
2483 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2484 .clksel_mask = OMAP4430_CLKSEL_MASK,
2485 .ops = &clkops_omap2_dflt,
2486 .recalc = &omap2_clksel_recalc,
2487 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2488 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2489 .clkdm_name = "l4_per_clkdm",
2226}; 2490};
2227 2491
2228static struct clk uart1_fck = { 2492static struct clk uart1_fck = {
@@ -2265,38 +2529,169 @@ static struct clk uart4_fck = {
2265 .recalc = &followparent_recalc, 2529 .recalc = &followparent_recalc,
2266}; 2530};
2267 2531
2268static struct clk unipro1_fck = { 2532static struct clk usb_host_fs_fck = {
2269 .name = "unipro1_fck", 2533 .name = "usb_host_fs_fck",
2270 .ops = &clkops_omap2_dflt, 2534 .ops = &clkops_omap2_dflt,
2271 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, 2535 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2272 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2536 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2273 .clkdm_name = "l3_init_clkdm", 2537 .clkdm_name = "l3_init_clkdm",
2274 .parent = &func_96m_fclk, 2538 .parent = &func_48mc_fclk,
2539 .recalc = &followparent_recalc,
2540};
2541
2542static const struct clksel utmi_p1_gfclk_sel[] = {
2543 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2544 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2545 { .parent = NULL },
2546};
2547
2548static struct clk utmi_p1_gfclk = {
2549 .name = "utmi_p1_gfclk",
2550 .parent = &init_60m_fclk,
2551 .clksel = utmi_p1_gfclk_sel,
2552 .init = &omap2_init_clksel_parent,
2553 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2554 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2555 .ops = &clkops_null,
2556 .recalc = &omap2_clksel_recalc,
2557};
2558
2559static struct clk usb_host_hs_utmi_p1_clk = {
2560 .name = "usb_host_hs_utmi_p1_clk",
2561 .ops = &clkops_omap2_dflt,
2562 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2563 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2564 .clkdm_name = "l3_init_clkdm",
2565 .parent = &utmi_p1_gfclk,
2275 .recalc = &followparent_recalc, 2566 .recalc = &followparent_recalc,
2276}; 2567};
2277 2568
2278static struct clk usb_host_fck = { 2569static const struct clksel utmi_p2_gfclk_sel[] = {
2279 .name = "usb_host_fck", 2570 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2571 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2572 { .parent = NULL },
2573};
2574
2575static struct clk utmi_p2_gfclk = {
2576 .name = "utmi_p2_gfclk",
2577 .parent = &init_60m_fclk,
2578 .clksel = utmi_p2_gfclk_sel,
2579 .init = &omap2_init_clksel_parent,
2580 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2581 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2582 .ops = &clkops_null,
2583 .recalc = &omap2_clksel_recalc,
2584};
2585
2586static struct clk usb_host_hs_utmi_p2_clk = {
2587 .name = "usb_host_hs_utmi_p2_clk",
2280 .ops = &clkops_omap2_dflt, 2588 .ops = &clkops_omap2_dflt,
2281 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2589 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2282 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2590 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2591 .clkdm_name = "l3_init_clkdm",
2592 .parent = &utmi_p2_gfclk,
2593 .recalc = &followparent_recalc,
2594};
2595
2596static struct clk usb_host_hs_utmi_p3_clk = {
2597 .name = "usb_host_hs_utmi_p3_clk",
2598 .ops = &clkops_omap2_dflt,
2599 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2600 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2283 .clkdm_name = "l3_init_clkdm", 2601 .clkdm_name = "l3_init_clkdm",
2284 .parent = &init_60m_fclk, 2602 .parent = &init_60m_fclk,
2285 .recalc = &followparent_recalc, 2603 .recalc = &followparent_recalc,
2286}; 2604};
2287 2605
2288static struct clk usb_host_fs_fck = { 2606static struct clk usb_host_hs_hsic480m_p1_clk = {
2289 .name = "usb_host_fs_fck", 2607 .name = "usb_host_hs_hsic480m_p1_clk",
2290 .ops = &clkops_omap2_dflt, 2608 .ops = &clkops_omap2_dflt,
2291 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, 2609 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2292 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2610 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2611 .clkdm_name = "l3_init_clkdm",
2612 .parent = &dpll_usb_m2_ck,
2613 .recalc = &followparent_recalc,
2614};
2615
2616static struct clk usb_host_hs_hsic60m_p1_clk = {
2617 .name = "usb_host_hs_hsic60m_p1_clk",
2618 .ops = &clkops_omap2_dflt,
2619 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2620 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2621 .clkdm_name = "l3_init_clkdm",
2622 .parent = &init_60m_fclk,
2623 .recalc = &followparent_recalc,
2624};
2625
2626static struct clk usb_host_hs_hsic60m_p2_clk = {
2627 .name = "usb_host_hs_hsic60m_p2_clk",
2628 .ops = &clkops_omap2_dflt,
2629 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2630 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2631 .clkdm_name = "l3_init_clkdm",
2632 .parent = &init_60m_fclk,
2633 .recalc = &followparent_recalc,
2634};
2635
2636static struct clk usb_host_hs_hsic480m_p2_clk = {
2637 .name = "usb_host_hs_hsic480m_p2_clk",
2638 .ops = &clkops_omap2_dflt,
2639 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2640 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2641 .clkdm_name = "l3_init_clkdm",
2642 .parent = &dpll_usb_m2_ck,
2643 .recalc = &followparent_recalc,
2644};
2645
2646static struct clk usb_host_hs_func48mclk = {
2647 .name = "usb_host_hs_func48mclk",
2648 .ops = &clkops_omap2_dflt,
2649 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2650 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2293 .clkdm_name = "l3_init_clkdm", 2651 .clkdm_name = "l3_init_clkdm",
2294 .parent = &func_48mc_fclk, 2652 .parent = &func_48mc_fclk,
2295 .recalc = &followparent_recalc, 2653 .recalc = &followparent_recalc,
2296}; 2654};
2297 2655
2298static struct clk usb_otg_ick = { 2656static struct clk usb_host_hs_fck = {
2299 .name = "usb_otg_ick", 2657 .name = "usb_host_hs_fck",
2658 .ops = &clkops_omap2_dflt,
2659 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2660 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2661 .clkdm_name = "l3_init_clkdm",
2662 .parent = &init_60m_fclk,
2663 .recalc = &followparent_recalc,
2664};
2665
2666static const struct clksel otg_60m_gfclk_sel[] = {
2667 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2668 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2669 { .parent = NULL },
2670};
2671
2672static struct clk otg_60m_gfclk = {
2673 .name = "otg_60m_gfclk",
2674 .parent = &utmi_phy_clkout_ck,
2675 .clksel = otg_60m_gfclk_sel,
2676 .init = &omap2_init_clksel_parent,
2677 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2678 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2679 .ops = &clkops_null,
2680 .recalc = &omap2_clksel_recalc,
2681};
2682
2683static struct clk usb_otg_hs_xclk = {
2684 .name = "usb_otg_hs_xclk",
2685 .ops = &clkops_omap2_dflt,
2686 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2687 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2688 .clkdm_name = "l3_init_clkdm",
2689 .parent = &otg_60m_gfclk,
2690 .recalc = &followparent_recalc,
2691};
2692
2693static struct clk usb_otg_hs_ick = {
2694 .name = "usb_otg_hs_ick",
2300 .ops = &clkops_omap2_dflt, 2695 .ops = &clkops_omap2_dflt,
2301 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2696 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2302 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2697 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2305,38 +2700,101 @@ static struct clk usb_otg_ick = {
2305 .recalc = &followparent_recalc, 2700 .recalc = &followparent_recalc,
2306}; 2701};
2307 2702
2308static struct clk usb_tll_ick = { 2703static struct clk usb_phy_cm_clk32k = {
2309 .name = "usb_tll_ick", 2704 .name = "usb_phy_cm_clk32k",
2705 .ops = &clkops_omap2_dflt,
2706 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2707 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2708 .clkdm_name = "l4_ao_clkdm",
2709 .parent = &sys_32k_ck,
2710 .recalc = &followparent_recalc,
2711};
2712
2713static struct clk usb_tll_hs_usb_ch2_clk = {
2714 .name = "usb_tll_hs_usb_ch2_clk",
2310 .ops = &clkops_omap2_dflt, 2715 .ops = &clkops_omap2_dflt,
2311 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2716 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2312 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2717 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2313 .clkdm_name = "l3_init_clkdm", 2718 .clkdm_name = "l3_init_clkdm",
2314 .parent = &l4_div_ck, 2719 .parent = &init_60m_fclk,
2315 .recalc = &followparent_recalc, 2720 .recalc = &followparent_recalc,
2316}; 2721};
2317 2722
2318static struct clk usbphyocp2scp_ick = { 2723static struct clk usb_tll_hs_usb_ch0_clk = {
2319 .name = "usbphyocp2scp_ick", 2724 .name = "usb_tll_hs_usb_ch0_clk",
2320 .ops = &clkops_omap2_dflt, 2725 .ops = &clkops_omap2_dflt,
2321 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, 2726 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2727 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2728 .clkdm_name = "l3_init_clkdm",
2729 .parent = &init_60m_fclk,
2730 .recalc = &followparent_recalc,
2731};
2732
2733static struct clk usb_tll_hs_usb_ch1_clk = {
2734 .name = "usb_tll_hs_usb_ch1_clk",
2735 .ops = &clkops_omap2_dflt,
2736 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2737 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2738 .clkdm_name = "l3_init_clkdm",
2739 .parent = &init_60m_fclk,
2740 .recalc = &followparent_recalc,
2741};
2742
2743static struct clk usb_tll_hs_ick = {
2744 .name = "usb_tll_hs_ick",
2745 .ops = &clkops_omap2_dflt,
2746 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2322 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2747 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2323 .clkdm_name = "l3_init_clkdm", 2748 .clkdm_name = "l3_init_clkdm",
2324 .parent = &l4_div_ck, 2749 .parent = &l4_div_ck,
2325 .recalc = &followparent_recalc, 2750 .recalc = &followparent_recalc,
2326}; 2751};
2327 2752
2753static const struct clksel_rate div2_14to18_rates[] = {
2754 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2755 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2756 { .div = 0 },
2757};
2758
2759static const struct clksel usim_fclk_div[] = {
2760 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2761 { .parent = NULL },
2762};
2763
2764static struct clk usim_ck = {
2765 .name = "usim_ck",
2766 .parent = &dpll_per_m4x2_ck,
2767 .clksel = usim_fclk_div,
2768 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2769 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2770 .ops = &clkops_null,
2771 .recalc = &omap2_clksel_recalc,
2772 .round_rate = &omap2_clksel_round_rate,
2773 .set_rate = &omap2_clksel_set_rate,
2774};
2775
2776static struct clk usim_fclk = {
2777 .name = "usim_fclk",
2778 .ops = &clkops_omap2_dflt,
2779 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2780 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2781 .clkdm_name = "l4_wkup_clkdm",
2782 .parent = &usim_ck,
2783 .recalc = &followparent_recalc,
2784};
2785
2328static struct clk usim_fck = { 2786static struct clk usim_fck = {
2329 .name = "usim_fck", 2787 .name = "usim_fck",
2330 .ops = &clkops_omap2_dflt, 2788 .ops = &clkops_omap2_dflt,
2331 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2789 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2332 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2790 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2333 .clkdm_name = "l4_wkup_clkdm", 2791 .clkdm_name = "l4_wkup_clkdm",
2334 .parent = &sys_32k_ck, 2792 .parent = &sys_32k_ck,
2335 .recalc = &followparent_recalc, 2793 .recalc = &followparent_recalc,
2336}; 2794};
2337 2795
2338static struct clk wdt2_fck = { 2796static struct clk wd_timer2_fck = {
2339 .name = "wdt2_fck", 2797 .name = "wd_timer2_fck",
2340 .ops = &clkops_omap2_dflt, 2798 .ops = &clkops_omap2_dflt,
2341 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 2799 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2800 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2345,8 +2803,8 @@ static struct clk wdt2_fck = {
2345 .recalc = &followparent_recalc, 2803 .recalc = &followparent_recalc,
2346}; 2804};
2347 2805
2348static struct clk wdt3_fck = { 2806static struct clk wd_timer3_fck = {
2349 .name = "wdt3_fck", 2807 .name = "wd_timer3_fck",
2350 .ops = &clkops_omap2_dflt, 2808 .ops = &clkops_omap2_dflt,
2351 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 2809 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2352 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2810 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2356,23 +2814,6 @@ static struct clk wdt3_fck = {
2356}; 2814};
2357 2815
2358/* Remaining optional clocks */ 2816/* Remaining optional clocks */
2359static const struct clksel otg_60m_gfclk_sel[] = {
2360 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2361 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2362 { .parent = NULL },
2363};
2364
2365static struct clk otg_60m_gfclk_ck = {
2366 .name = "otg_60m_gfclk_ck",
2367 .parent = &utmi_phy_clkout_ck,
2368 .clksel = otg_60m_gfclk_sel,
2369 .init = &omap2_init_clksel_parent,
2370 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2371 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2372 .ops = &clkops_null,
2373 .recalc = &omap2_clksel_recalc,
2374};
2375
2376static const struct clksel stm_clk_div_div[] = { 2817static const struct clksel stm_clk_div_div[] = {
2377 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, 2818 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2378 { .parent = NULL }, 2819 { .parent = NULL },
@@ -2407,60 +2848,165 @@ static struct clk trace_clk_div_ck = {
2407 .set_rate = &omap2_clksel_set_rate, 2848 .set_rate = &omap2_clksel_set_rate,
2408}; 2849};
2409 2850
2410static const struct clksel_rate div2_14to18_rates[] = { 2851/* SCRM aux clk nodes */
2411 { .div = 14, .val = 0, .flags = RATE_IN_4430 }, 2852
2412 { .div = 18, .val = 1, .flags = RATE_IN_4430 }, 2853static const struct clksel auxclk_sel[] = {
2413 { .div = 0 }, 2854 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2855 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2856 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2857 { .parent = NULL },
2414}; 2858};
2415 2859
2416static const struct clksel usim_fclk_div[] = { 2860static struct clk auxclk0_ck = {
2417 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, 2861 .name = "auxclk0_ck",
2862 .parent = &sys_clkin_ck,
2863 .init = &omap2_init_clksel_parent,
2864 .ops = &clkops_omap2_dflt,
2865 .clksel = auxclk_sel,
2866 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2867 .clksel_mask = OMAP4_SRCSELECT_MASK,
2868 .recalc = &omap2_clksel_recalc,
2869 .enable_reg = OMAP4_SCRM_AUXCLK0,
2870 .enable_bit = OMAP4_ENABLE_SHIFT,
2871};
2872
2873static struct clk auxclk1_ck = {
2874 .name = "auxclk1_ck",
2875 .parent = &sys_clkin_ck,
2876 .init = &omap2_init_clksel_parent,
2877 .ops = &clkops_omap2_dflt,
2878 .clksel = auxclk_sel,
2879 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2880 .clksel_mask = OMAP4_SRCSELECT_MASK,
2881 .recalc = &omap2_clksel_recalc,
2882 .enable_reg = OMAP4_SCRM_AUXCLK1,
2883 .enable_bit = OMAP4_ENABLE_SHIFT,
2884};
2885
2886static struct clk auxclk2_ck = {
2887 .name = "auxclk2_ck",
2888 .parent = &sys_clkin_ck,
2889 .init = &omap2_init_clksel_parent,
2890 .ops = &clkops_omap2_dflt,
2891 .clksel = auxclk_sel,
2892 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2893 .clksel_mask = OMAP4_SRCSELECT_MASK,
2894 .recalc = &omap2_clksel_recalc,
2895 .enable_reg = OMAP4_SCRM_AUXCLK2,
2896 .enable_bit = OMAP4_ENABLE_SHIFT,
2897};
2898static struct clk auxclk3_ck = {
2899 .name = "auxclk3_ck",
2900 .parent = &sys_clkin_ck,
2901 .init = &omap2_init_clksel_parent,
2902 .ops = &clkops_omap2_dflt,
2903 .clksel = auxclk_sel,
2904 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2905 .clksel_mask = OMAP4_SRCSELECT_MASK,
2906 .recalc = &omap2_clksel_recalc,
2907 .enable_reg = OMAP4_SCRM_AUXCLK3,
2908 .enable_bit = OMAP4_ENABLE_SHIFT,
2909};
2910
2911static struct clk auxclk4_ck = {
2912 .name = "auxclk4_ck",
2913 .parent = &sys_clkin_ck,
2914 .init = &omap2_init_clksel_parent,
2915 .ops = &clkops_omap2_dflt,
2916 .clksel = auxclk_sel,
2917 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2918 .clksel_mask = OMAP4_SRCSELECT_MASK,
2919 .recalc = &omap2_clksel_recalc,
2920 .enable_reg = OMAP4_SCRM_AUXCLK4,
2921 .enable_bit = OMAP4_ENABLE_SHIFT,
2922};
2923
2924static struct clk auxclk5_ck = {
2925 .name = "auxclk5_ck",
2926 .parent = &sys_clkin_ck,
2927 .init = &omap2_init_clksel_parent,
2928 .ops = &clkops_omap2_dflt,
2929 .clksel = auxclk_sel,
2930 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2931 .clksel_mask = OMAP4_SRCSELECT_MASK,
2932 .recalc = &omap2_clksel_recalc,
2933 .enable_reg = OMAP4_SCRM_AUXCLK5,
2934 .enable_bit = OMAP4_ENABLE_SHIFT,
2935};
2936
2937static const struct clksel auxclkreq_sel[] = {
2938 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2939 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2940 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2941 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2942 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2943 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2418 { .parent = NULL }, 2944 { .parent = NULL },
2419}; 2945};
2420 2946
2421static struct clk usim_fclk = { 2947static struct clk auxclkreq0_ck = {
2422 .name = "usim_fclk", 2948 .name = "auxclkreq0_ck",
2423 .parent = &dpll_per_m4_ck, 2949 .parent = &auxclk0_ck,
2424 .clksel = usim_fclk_div, 2950 .init = &omap2_init_clksel_parent,
2425 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2426 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2427 .ops = &clkops_null, 2951 .ops = &clkops_null,
2952 .clksel = auxclkreq_sel,
2953 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
2954 .clksel_mask = OMAP4_MAPPING_MASK,
2428 .recalc = &omap2_clksel_recalc, 2955 .recalc = &omap2_clksel_recalc,
2429 .round_rate = &omap2_clksel_round_rate,
2430 .set_rate = &omap2_clksel_set_rate,
2431}; 2956};
2432 2957
2433static const struct clksel utmi_p1_gfclk_sel[] = { 2958static struct clk auxclkreq1_ck = {
2434 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2959 .name = "auxclkreq1_ck",
2435 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, 2960 .parent = &auxclk1_ck,
2436 { .parent = NULL }, 2961 .init = &omap2_init_clksel_parent,
2962 .ops = &clkops_null,
2963 .clksel = auxclkreq_sel,
2964 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
2965 .clksel_mask = OMAP4_MAPPING_MASK,
2966 .recalc = &omap2_clksel_recalc,
2437}; 2967};
2438 2968
2439static struct clk utmi_p1_gfclk_ck = { 2969static struct clk auxclkreq2_ck = {
2440 .name = "utmi_p1_gfclk_ck", 2970 .name = "auxclkreq2_ck",
2441 .parent = &init_60m_fclk, 2971 .parent = &auxclk2_ck,
2442 .clksel = utmi_p1_gfclk_sel,
2443 .init = &omap2_init_clksel_parent, 2972 .init = &omap2_init_clksel_parent,
2444 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2445 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2446 .ops = &clkops_null, 2973 .ops = &clkops_null,
2974 .clksel = auxclkreq_sel,
2975 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
2976 .clksel_mask = OMAP4_MAPPING_MASK,
2447 .recalc = &omap2_clksel_recalc, 2977 .recalc = &omap2_clksel_recalc,
2448}; 2978};
2449 2979
2450static const struct clksel utmi_p2_gfclk_sel[] = { 2980static struct clk auxclkreq3_ck = {
2451 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2981 .name = "auxclkreq3_ck",
2452 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, 2982 .parent = &auxclk3_ck,
2453 { .parent = NULL }, 2983 .init = &omap2_init_clksel_parent,
2984 .ops = &clkops_null,
2985 .clksel = auxclkreq_sel,
2986 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
2987 .clksel_mask = OMAP4_MAPPING_MASK,
2988 .recalc = &omap2_clksel_recalc,
2454}; 2989};
2455 2990
2456static struct clk utmi_p2_gfclk_ck = { 2991static struct clk auxclkreq4_ck = {
2457 .name = "utmi_p2_gfclk_ck", 2992 .name = "auxclkreq4_ck",
2458 .parent = &init_60m_fclk, 2993 .parent = &auxclk4_ck,
2459 .clksel = utmi_p2_gfclk_sel,
2460 .init = &omap2_init_clksel_parent, 2994 .init = &omap2_init_clksel_parent,
2461 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2462 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2463 .ops = &clkops_null, 2995 .ops = &clkops_null,
2996 .clksel = auxclkreq_sel,
2997 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
2998 .clksel_mask = OMAP4_MAPPING_MASK,
2999 .recalc = &omap2_clksel_recalc,
3000};
3001
3002static struct clk auxclkreq5_ck = {
3003 .name = "auxclkreq5_ck",
3004 .parent = &auxclk5_ck,
3005 .init = &omap2_init_clksel_parent,
3006 .ops = &clkops_null,
3007 .clksel = auxclkreq_sel,
3008 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3009 .clksel_mask = OMAP4_MAPPING_MASK,
2464 .recalc = &omap2_clksel_recalc, 3010 .recalc = &omap2_clksel_recalc,
2465}; 3011};
2466 3012
@@ -2483,50 +3029,56 @@ static struct omap_clk omap44xx_clks[] = {
2483 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), 3029 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2484 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), 3030 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2485 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), 3031 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
3032 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
2486 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), 3033 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2487 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), 3034 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2488 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), 3035 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2489 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), 3036 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2490 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), 3037 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
2491 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 3038 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2492 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 3039 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3040 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
2493 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 3041 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2494 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), 3042 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2495 CLK(NULL, "abe_clk", &abe_clk, CK_443X), 3043 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2496 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), 3044 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2497 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X), 3045 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
2498 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), 3046 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2499 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), 3047 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2500 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X), 3048 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3049 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
2501 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), 3050 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2502 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), 3051 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2503 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), 3052 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2504 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X), 3053 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
2505 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), 3054 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2506 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), 3055 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2507 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), 3056 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2508 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X), 3057 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
2509 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), 3058 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2510 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), 3059 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2511 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X), 3060 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
2512 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X), 3061 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
2513 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), 3062 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2514 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), 3063 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2515 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X), 3064 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
2516 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X), 3065 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3066 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
2517 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), 3067 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2518 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), 3068 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2519 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), 3069 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2520 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), 3070 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2521 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), 3071 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2522 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), 3072 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3073 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
2523 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), 3074 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2524 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X), 3075 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
2525 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X), 3076 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
2526 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X), 3077 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
2527 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X), 3078 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
2528 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X), 3079 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
2529 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), 3080 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
3081 CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
2530 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), 3082 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2531 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 3083 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2532 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 3084 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
@@ -2557,46 +3109,48 @@ static struct omap_clk omap44xx_clks[] = {
2557 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 3109 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2558 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 3110 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2559 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 3111 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2560 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), 3112 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
2561 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 3113 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2562 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 3114 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2563 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 3115 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2564 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 3116 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
2565 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), 3117 CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
2566 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), 3118 CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
2567 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), 3119 CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
3120 CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
3121 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3122 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3123 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
3124 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
2568 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 3125 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2569 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), 3126 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
2570 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), 3127 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
2571 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 3128 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
3129 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
2572 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 3130 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
3131 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
2573 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 3132 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
3133 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
2574 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), 3134 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
3135 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
2575 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 3136 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
3137 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
2576 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 3138 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2577 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 3139 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2578 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), 3140 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
2579 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2580 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2581 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2582 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2583 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2584 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2585 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2586 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2587 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2588 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2589 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 3141 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2590 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), 3142 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
2591 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), 3143 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X),
2592 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), 3144 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X),
2593 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), 3145 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X),
2594 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), 3146 CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X),
3147 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3148 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
2595 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 3149 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2596 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), 3150 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
2597 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), 3151 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
2598 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), 3152 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
2599 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), 3153 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
2600 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 3154 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2601 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 3155 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2602 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 3156 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
@@ -2607,52 +3161,82 @@ static struct omap_clk omap44xx_clks[] = {
2607 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 3161 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2608 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 3162 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2609 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 3163 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
3164 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
2610 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 3165 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2611 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 3166 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2612 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 3167 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
2613 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), 3168 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
2614 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), 3169 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
2615 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), 3170 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
2616 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 3171 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
2617 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 3172 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
2618 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 3173 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
2619 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), 3174 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
2620 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), 3175 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
2621 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), 3176 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
2622 CLK("omap_rng", "ick", &rng_ick, CK_443X), 3177 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2623 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), 3178 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
2624 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), 3179 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
3180 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
3181 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
3182 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
3183 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
2625 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), 3184 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
3185 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
3186 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
3187 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
2626 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), 3188 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2627 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), 3189 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
2628 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), 3190 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
2629 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), 3191 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
2630 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), 3192 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
3193 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
3194 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
3195 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
3196 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
3197 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
3198 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
3199 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
3200 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
3201 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
3202 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
2631 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), 3203 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2632 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 3204 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2633 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 3205 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2634 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 3206 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2635 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2636 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2637 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 3207 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2638 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), 3208 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
2639 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), 3209 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
2640 CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), 3210 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3211 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
3212 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3213 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
3214 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3215 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3216 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3217 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3218 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3219 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
3220 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
3221 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
3222 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3223 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3224 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3225 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3226 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3227 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3228 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3229 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
3230 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3231 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
3232 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3233 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2641 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3234 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2642 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), 3235 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
2643 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), 3236 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
2644 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), 3237 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
2645 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3238 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2646 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3239 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2647 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2648 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2649 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2650 CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
2651 CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
2652 CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
2653 CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
2654 CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
2655 CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
2656 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3240 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2657 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 3241 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2658 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 3242 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@@ -2665,28 +3249,40 @@ static struct omap_clk omap44xx_clks[] = {
2665 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), 3249 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
2666 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), 3250 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
2667 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), 3251 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
2668 CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X), 3252 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
2669 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), 3253 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
2670 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), 3254 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
2671 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), 3255 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3256 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3257 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3258 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3259 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3260 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
2672 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 3261 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2673 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 3262 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2674 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 3263 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2675 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 3264 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
2676 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 3265 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2677 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 3266 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2678 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 3267 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2679 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 3268 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2680 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2681 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2682 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2683 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2684 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2685 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 3269 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2686 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 3270 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2687 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 3271 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
2688 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 3272 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
2689 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3273 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3274 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3275 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3276 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3277 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3278 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3279 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3280 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3281 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3282 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3283 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3284 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3285 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
2690}; 3286};
2691 3287
2692int __init omap4xxx_clk_init(void) 3288int __init omap4xxx_clk_init(void)
@@ -2713,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
2713 omap2_init_clk_clkdm(c->lk.clk); 3309 omap2_init_clk_clkdm(c->lk.clk);
2714 } 3310 }
2715 3311
3312 /* Disable autoidle on all clocks; let the PM code enable it later */
3313 omap_clk_disable_autoidle_all();
3314
2716 recalculate_root_clocks(); 3315 recalculate_root_clocks();
2717 3316
2718 /* 3317 /*
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 02:43:59 -0400