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-rw-r--r--arch/arm/mach-omap2/devices.c856
1 files changed, 364 insertions, 492 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2dbb265bedd4..5b8ca680ed93 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -9,12 +9,13 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/kernel.h> 12#include <linux/kernel.h>
14#include <linux/init.h> 13#include <linux/init.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
16#include <linux/io.h> 15#include <linux/io.h>
17#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/slab.h>
18 19
19#include <mach/hardware.h> 20#include <mach/hardware.h>
20#include <mach/irqs.h> 21#include <mach/irqs.h>
@@ -22,18 +23,87 @@
22#include <asm/mach/map.h> 23#include <asm/mach/map.h>
23#include <asm/pmu.h> 24#include <asm/pmu.h>
24 25
25#include <plat/control.h>
26#include <plat/tc.h> 26#include <plat/tc.h>
27#include <plat/board.h> 27#include <plat/board.h>
28#include <plat/mcbsp.h>
28#include <mach/gpio.h> 29#include <mach/gpio.h>
29#include <plat/mmc.h> 30#include <plat/mmc.h>
30#include <plat/dma.h> 31#include <plat/dma.h>
32#include <plat/omap_hwmod.h>
33#include <plat/omap_device.h>
34#include <plat/omap4-keypad.h>
31 35
32#include "mux.h" 36#include "mux.h"
37#include "control.h"
38#include "devices.h"
39
40#define L3_MODULES_MAX_LEN 12
41#define L3_MODULES 3
42
43static int __init omap3_l3_init(void)
44{
45 int l;
46 struct omap_hwmod *oh;
47 struct omap_device *od;
48 char oh_name[L3_MODULES_MAX_LEN];
49
50 /*
51 * To avoid code running on other OMAPs in
52 * multi-omap builds
53 */
54 if (!(cpu_is_omap34xx()))
55 return -ENODEV;
56
57 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
58
59 oh = omap_hwmod_lookup(oh_name);
60
61 if (!oh)
62 pr_err("could not look up %s\n", oh_name);
63
64 od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
65 NULL, 0, 0);
66
67 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
68
69 return IS_ERR(od) ? PTR_ERR(od) : 0;
70}
71postcore_initcall(omap3_l3_init);
72
73static int __init omap4_l3_init(void)
74{
75 int l, i;
76 struct omap_hwmod *oh[3];
77 struct omap_device *od;
78 char oh_name[L3_MODULES_MAX_LEN];
79
80 /*
81 * To avoid code running on other OMAPs in
82 * multi-omap builds
83 */
84 if (!(cpu_is_omap44xx()))
85 return -ENODEV;
86
87 for (i = 0; i < L3_MODULES; i++) {
88 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
89
90 oh[i] = omap_hwmod_lookup(oh_name);
91 if (!(oh[i]))
92 pr_err("could not look up %s\n", oh_name);
93 }
94
95 od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
96 0, NULL, 0, 0);
97
98 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
99
100 return IS_ERR(od) ? PTR_ERR(od) : 0;
101}
102postcore_initcall(omap4_l3_init);
33 103
34#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 104#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
35 105
36static struct resource cam_resources[] = { 106static struct resource omap2cam_resources[] = {
37 { 107 {
38 .start = OMAP24XX_CAMERA_BASE, 108 .start = OMAP24XX_CAMERA_BASE,
39 .end = OMAP24XX_CAMERA_BASE + 0xfff, 109 .end = OMAP24XX_CAMERA_BASE + 0xfff,
@@ -45,19 +115,13 @@ static struct resource cam_resources[] = {
45 } 115 }
46}; 116};
47 117
48static struct platform_device omap_cam_device = { 118static struct platform_device omap2cam_device = {
49 .name = "omap24xxcam", 119 .name = "omap24xxcam",
50 .id = -1, 120 .id = -1,
51 .num_resources = ARRAY_SIZE(cam_resources), 121 .num_resources = ARRAY_SIZE(omap2cam_resources),
52 .resource = cam_resources, 122 .resource = omap2cam_resources,
53}; 123};
54 124#endif
55static inline void omap_init_camera(void)
56{
57 platform_device_register(&omap_cam_device);
58}
59
60#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
61 125
62static struct resource omap3isp_resources[] = { 126static struct resource omap3isp_resources[] = {
63 { 127 {
@@ -66,11 +130,6 @@ static struct resource omap3isp_resources[] = {
66 .flags = IORESOURCE_MEM, 130 .flags = IORESOURCE_MEM,
67 }, 131 },
68 { 132 {
69 .start = OMAP3430_ISP_CBUFF_BASE,
70 .end = OMAP3430_ISP_CBUFF_END,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = OMAP3430_ISP_CCP2_BASE, 133 .start = OMAP3430_ISP_CCP2_BASE,
75 .end = OMAP3430_ISP_CCP2_END, 134 .end = OMAP3430_ISP_CCP2_END,
76 .flags = IORESOURCE_MEM, 135 .flags = IORESOURCE_MEM,
@@ -106,13 +165,33 @@ static struct resource omap3isp_resources[] = {
106 .flags = IORESOURCE_MEM, 165 .flags = IORESOURCE_MEM,
107 }, 166 },
108 { 167 {
109 .start = OMAP3430_ISP_CSI2A_BASE, 168 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
110 .end = OMAP3430_ISP_CSI2A_END, 169 .end = OMAP3430_ISP_CSI2A_REGS1_END,
111 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
112 }, 171 },
113 { 172 {
114 .start = OMAP3430_ISP_CSI2PHY_BASE, 173 .start = OMAP3430_ISP_CSIPHY2_BASE,
115 .end = OMAP3430_ISP_CSI2PHY_END, 174 .end = OMAP3430_ISP_CSIPHY2_END,
175 .flags = IORESOURCE_MEM,
176 },
177 {
178 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
179 .end = OMAP3630_ISP_CSI2A_REGS2_END,
180 .flags = IORESOURCE_MEM,
181 },
182 {
183 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
184 .end = OMAP3630_ISP_CSI2C_REGS1_END,
185 .flags = IORESOURCE_MEM,
186 },
187 {
188 .start = OMAP3630_ISP_CSIPHY1_BASE,
189 .end = OMAP3630_ISP_CSIPHY1_END,
190 .flags = IORESOURCE_MEM,
191 },
192 {
193 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
194 .end = OMAP3630_ISP_CSI2C_REGS2_END,
116 .flags = IORESOURCE_MEM, 195 .flags = IORESOURCE_MEM,
117 }, 196 },
118 { 197 {
@@ -128,106 +207,84 @@ static struct platform_device omap3isp_device = {
128 .resource = omap3isp_resources, 207 .resource = omap3isp_resources,
129}; 208};
130 209
131static inline void omap_init_camera(void) 210int omap3_init_camera(struct isp_platform_data *pdata)
132{ 211{
133 platform_device_register(&omap3isp_device); 212 omap3isp_device.dev.platform_data = pdata;
213 return platform_device_register(&omap3isp_device);
134} 214}
135#else 215
136static inline void omap_init_camera(void) 216static inline void omap_init_camera(void)
137{ 217{
138} 218#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
219 if (cpu_is_omap24xx())
220 platform_device_register(&omap2cam_device);
139#endif 221#endif
222}
140 223
141#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 224struct omap_device_pm_latency omap_keyboard_latency[] = {
142
143#define MBOX_REG_SIZE 0x120
144
145#ifdef CONFIG_ARCH_OMAP2
146static struct resource omap2_mbox_resources[] = {
147 { 225 {
148 .start = OMAP24XX_MAILBOX_BASE, 226 .deactivate_func = omap_device_idle_hwmods,
149 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, 227 .activate_func = omap_device_enable_hwmods,
150 .flags = IORESOURCE_MEM, 228 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
151 },
152 {
153 .start = INT_24XX_MAIL_U0_MPU,
154 .flags = IORESOURCE_IRQ,
155 .name = "dsp",
156 },
157 {
158 .start = INT_24XX_MAIL_U3_MPU,
159 .flags = IORESOURCE_IRQ,
160 .name = "iva",
161 }, 229 },
162}; 230};
163static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
164#else
165#define omap2_mbox_resources NULL
166#define omap2_mbox_resources_sz 0
167#endif
168 231
169#ifdef CONFIG_ARCH_OMAP3 232int __init omap4_keyboard_init(struct omap4_keypad_platform_data
170static struct resource omap3_mbox_resources[] = { 233 *sdp4430_keypad_data)
171 { 234{
172 .start = OMAP34XX_MAILBOX_BASE, 235 struct omap_device *od;
173 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, 236 struct omap_hwmod *oh;
174 .flags = IORESOURCE_MEM, 237 struct omap4_keypad_platform_data *keypad_data;
175 }, 238 unsigned int id = -1;
176 { 239 char *oh_name = "kbd";
177 .start = INT_24XX_MAIL_U0_MPU, 240 char *name = "omap4-keypad";
178 .flags = IORESOURCE_IRQ, 241
179 .name = "dsp", 242 oh = omap_hwmod_lookup(oh_name);
180 }, 243 if (!oh) {
181}; 244 pr_err("Could not look up %s\n", oh_name);
182static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); 245 return -ENODEV;
183#else 246 }
184#define omap3_mbox_resources NULL
185#define omap3_mbox_resources_sz 0
186#endif
187 247
188#ifdef CONFIG_ARCH_OMAP4 248 keypad_data = sdp4430_keypad_data;
189 249
190#define OMAP4_MBOX_REG_SIZE 0x130 250 od = omap_device_build(name, id, oh, keypad_data,
191static struct resource omap4_mbox_resources[] = { 251 sizeof(struct omap4_keypad_platform_data),
192 { 252 omap_keyboard_latency,
193 .start = OMAP44XX_MAILBOX_BASE, 253 ARRAY_SIZE(omap_keyboard_latency), 0);
194 .end = OMAP44XX_MAILBOX_BASE +
195 OMAP4_MBOX_REG_SIZE - 1,
196 .flags = IORESOURCE_MEM,
197 },
198 {
199 .start = OMAP44XX_IRQ_MAIL_U0,
200 .flags = IORESOURCE_IRQ,
201 .name = "mbox",
202 },
203};
204static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
205#else
206#define omap4_mbox_resources NULL
207#define omap4_mbox_resources_sz 0
208#endif
209 254
210static struct platform_device mbox_device = { 255 if (IS_ERR(od)) {
211 .name = "omap-mailbox", 256 WARN(1, "Can't build omap_device for %s:%s.\n",
212 .id = -1, 257 name, oh->name);
258 return PTR_ERR(od);
259 }
260
261 return 0;
262}
263
264#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
265static struct omap_device_pm_latency mbox_latencies[] = {
266 [0] = {
267 .activate_func = omap_device_enable_hwmods,
268 .deactivate_func = omap_device_idle_hwmods,
269 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
270 },
213}; 271};
214 272
215static inline void omap_init_mbox(void) 273static inline void omap_init_mbox(void)
216{ 274{
217 if (cpu_is_omap24xx()) { 275 struct omap_hwmod *oh;
218 mbox_device.resource = omap2_mbox_resources; 276 struct omap_device *od;
219 mbox_device.num_resources = omap2_mbox_resources_sz; 277
220 } else if (cpu_is_omap34xx()) { 278 oh = omap_hwmod_lookup("mailbox");
221 mbox_device.resource = omap3_mbox_resources; 279 if (!oh) {
222 mbox_device.num_resources = omap3_mbox_resources_sz; 280 pr_err("%s: unable to find hwmod\n", __func__);
223 } else if (cpu_is_omap44xx()) {
224 mbox_device.resource = omap4_mbox_resources;
225 mbox_device.num_resources = omap4_mbox_resources_sz;
226 } else {
227 pr_err("%s: platform not supported\n", __func__);
228 return; 281 return;
229 } 282 }
230 platform_device_register(&mbox_device); 283
284 od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
285 mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
286 WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
287 __func__, PTR_ERR(od));
231} 288}
232#else 289#else
233static inline void omap_init_mbox(void) { } 290static inline void omap_init_mbox(void) { }
@@ -235,167 +292,96 @@ static inline void omap_init_mbox(void) { }
235 292
236static inline void omap_init_sti(void) {} 293static inline void omap_init_sti(void) {}
237 294
238#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 295#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
239
240#include <plat/mcspi.h>
241
242#define OMAP2_MCSPI1_BASE 0x48098000
243#define OMAP2_MCSPI2_BASE 0x4809a000
244#define OMAP2_MCSPI3_BASE 0x480b8000
245#define OMAP2_MCSPI4_BASE 0x480ba000
246
247#define OMAP4_MCSPI1_BASE 0x48098100
248#define OMAP4_MCSPI2_BASE 0x4809a100
249#define OMAP4_MCSPI3_BASE 0x480b8100
250#define OMAP4_MCSPI4_BASE 0x480ba100
251
252static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
253 .num_cs = 4,
254};
255
256static struct resource omap2_mcspi1_resources[] = {
257 {
258 .start = OMAP2_MCSPI1_BASE,
259 .end = OMAP2_MCSPI1_BASE + 0xff,
260 .flags = IORESOURCE_MEM,
261 },
262};
263
264static struct platform_device omap2_mcspi1 = {
265 .name = "omap2_mcspi",
266 .id = 1,
267 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
268 .resource = omap2_mcspi1_resources,
269 .dev = {
270 .platform_data = &omap2_mcspi1_config,
271 },
272};
273 296
274static struct omap2_mcspi_platform_config omap2_mcspi2_config = { 297static struct platform_device omap_pcm = {
275 .num_cs = 2, 298 .name = "omap-pcm-audio",
299 .id = -1,
276}; 300};
277 301
278static struct resource omap2_mcspi2_resources[] = { 302/*
279 { 303 * OMAP2420 has 2 McBSP ports
280 .start = OMAP2_MCSPI2_BASE, 304 * OMAP2430 has 5 McBSP ports
281 .end = OMAP2_MCSPI2_BASE + 0xff, 305 * OMAP3 has 5 McBSP ports
282 .flags = IORESOURCE_MEM, 306 * OMAP4 has 4 McBSP ports
283 }, 307 */
284}; 308OMAP_MCBSP_PLATFORM_DEVICE(1);
285 309OMAP_MCBSP_PLATFORM_DEVICE(2);
286static struct platform_device omap2_mcspi2 = { 310OMAP_MCBSP_PLATFORM_DEVICE(3);
287 .name = "omap2_mcspi", 311OMAP_MCBSP_PLATFORM_DEVICE(4);
288 .id = 2, 312OMAP_MCBSP_PLATFORM_DEVICE(5);
289 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
290 .resource = omap2_mcspi2_resources,
291 .dev = {
292 .platform_data = &omap2_mcspi2_config,
293 },
294};
295 313
296#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ 314static void omap_init_audio(void)
297 defined(CONFIG_ARCH_OMAP4) 315{
298static struct omap2_mcspi_platform_config omap2_mcspi3_config = { 316 platform_device_register(&omap_mcbsp1);
299 .num_cs = 2, 317 platform_device_register(&omap_mcbsp2);
300}; 318 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
319 platform_device_register(&omap_mcbsp3);
320 platform_device_register(&omap_mcbsp4);
321 }
322 if (cpu_is_omap243x() || cpu_is_omap34xx())
323 platform_device_register(&omap_mcbsp5);
301 324
302static struct resource omap2_mcspi3_resources[] = { 325 platform_device_register(&omap_pcm);
303 { 326}
304 .start = OMAP2_MCSPI3_BASE,
305 .end = OMAP2_MCSPI3_BASE + 0xff,
306 .flags = IORESOURCE_MEM,
307 },
308};
309 327
310static struct platform_device omap2_mcspi3 = { 328#else
311 .name = "omap2_mcspi", 329static inline void omap_init_audio(void) {}
312 .id = 3,
313 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
314 .resource = omap2_mcspi3_resources,
315 .dev = {
316 .platform_data = &omap2_mcspi3_config,
317 },
318};
319#endif 330#endif
320 331
321#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 332#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
322static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
323 .num_cs = 1,
324};
325 333
326static struct resource omap2_mcspi4_resources[] = { 334#include <plat/mcspi.h>
327 {
328 .start = OMAP2_MCSPI4_BASE,
329 .end = OMAP2_MCSPI4_BASE + 0xff,
330 .flags = IORESOURCE_MEM,
331 },
332};
333 335
334static struct platform_device omap2_mcspi4 = { 336struct omap_device_pm_latency omap_mcspi_latency[] = {
335 .name = "omap2_mcspi", 337 [0] = {
336 .id = 4, 338 .deactivate_func = omap_device_idle_hwmods,
337 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), 339 .activate_func = omap_device_enable_hwmods,
338 .resource = omap2_mcspi4_resources, 340 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
339 .dev = {
340 .platform_data = &omap2_mcspi4_config,
341 }, 341 },
342}; 342};
343#endif
344 343
345#ifdef CONFIG_ARCH_OMAP4 344static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
346static inline void omap4_mcspi_fixup(void)
347{ 345{
348 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; 346 struct omap_device *od;
349 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; 347 char *name = "omap2_mcspi";
350 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; 348 struct omap2_mcspi_platform_config *pdata;
351 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; 349 static int spi_num;
352 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; 350 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
353 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; 351
354 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; 352 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
355 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; 353 if (!pdata) {
356} 354 pr_err("Memory allocation for McSPI device failed\n");
357#else 355 return -ENOMEM;
358static inline void omap4_mcspi_fixup(void) 356 }
359{
360}
361#endif
362 357
363#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ 358 pdata->num_cs = mcspi_attrib->num_chipselect;
364 defined(CONFIG_ARCH_OMAP4) 359 switch (oh->class->rev) {
365static inline void omap2_mcspi3_init(void) 360 case OMAP2_MCSPI_REV:
366{ 361 case OMAP3_MCSPI_REV:
367 platform_device_register(&omap2_mcspi3); 362 pdata->regs_offset = 0;
368} 363 break;
369#else 364 case OMAP4_MCSPI_REV:
370static inline void omap2_mcspi3_init(void) 365 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
371{ 366 break;
372} 367 default:
373#endif 368 pr_err("Invalid McSPI Revision value\n");
369 return -EINVAL;
370 }
374 371
375#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 372 spi_num++;
376static inline void omap2_mcspi4_init(void) 373 od = omap_device_build(name, spi_num, oh, pdata,
377{ 374 sizeof(*pdata), omap_mcspi_latency,
378 platform_device_register(&omap2_mcspi4); 375 ARRAY_SIZE(omap_mcspi_latency), 0);
379} 376 WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
380#else 377 name, oh->name);
381static inline void omap2_mcspi4_init(void) 378 kfree(pdata);
382{ 379 return 0;
383} 380}
384#endif
385 381
386static void omap_init_mcspi(void) 382static void omap_init_mcspi(void)
387{ 383{
388 if (cpu_is_omap44xx()) 384 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
389 omap4_mcspi_fixup();
390
391 platform_device_register(&omap2_mcspi1);
392 platform_device_register(&omap2_mcspi2);
393
394 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
395 omap2_mcspi3_init();
396
397 if (cpu_is_omap343x() || cpu_is_omap44xx())
398 omap2_mcspi4_init();
399} 385}
400 386
401#else 387#else
@@ -498,115 +484,82 @@ static void omap_init_sham(void)
498static inline void omap_init_sham(void) { } 484static inline void omap_init_sham(void) { }
499#endif 485#endif
500 486
501/*-------------------------------------------------------------------------*/ 487#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
502
503#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
504 488
505#define MMCHS_SYSCONFIG 0x0010 489#ifdef CONFIG_ARCH_OMAP2
506#define MMCHS_SYSCONFIG_SWRESET (1 << 1) 490static struct resource omap2_aes_resources[] = {
507#define MMCHS_SYSSTATUS 0x0014 491 {
508#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 492 .start = OMAP24XX_SEC_AES_BASE,
493 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .start = OMAP24XX_DMA_AES_TX,
498 .flags = IORESOURCE_DMA,
499 },
500 {
501 .start = OMAP24XX_DMA_AES_RX,
502 .flags = IORESOURCE_DMA,
503 }
504};
505static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
506#else
507#define omap2_aes_resources NULL
508#define omap2_aes_resources_sz 0
509#endif
509 510
510static struct platform_device dummy_pdev = { 511#ifdef CONFIG_ARCH_OMAP3
511 .dev = { 512static struct resource omap3_aes_resources[] = {
512 .bus = &platform_bus_type, 513 {
514 .start = OMAP34XX_SEC_AES_BASE,
515 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
516 .flags = IORESOURCE_MEM,
513 }, 517 },
518 {
519 .start = OMAP34XX_DMA_AES2_TX,
520 .flags = IORESOURCE_DMA,
521 },
522 {
523 .start = OMAP34XX_DMA_AES2_RX,
524 .flags = IORESOURCE_DMA,
525 }
526};
527static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
528#else
529#define omap3_aes_resources NULL
530#define omap3_aes_resources_sz 0
531#endif
532
533static struct platform_device aes_device = {
534 .name = "omap-aes",
535 .id = -1,
514}; 536};
515 537
516/** 538static void omap_init_aes(void)
517 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
518 *
519 * Ensure that each MMC controller is fully reset. Controllers
520 * left in an unknown state (by bootloader) may prevent retention
521 * or OFF-mode. This is especially important in cases where the
522 * MMC driver is not enabled, _or_ built as a module.
523 *
524 * In order for reset to work, interface, functional and debounce
525 * clocks must be enabled. The debounce clock comes from func_32k_clk
526 * and is not under SW control, so we only enable i- and f-clocks.
527 **/
528static void __init omap_hsmmc_reset(void)
529{ 539{
530 u32 i, nr_controllers; 540 if (cpu_is_omap24xx()) {
531 541 aes_device.resource = omap2_aes_resources;
532 if (cpu_is_omap242x()) 542 aes_device.num_resources = omap2_aes_resources_sz;
543 } else if (cpu_is_omap34xx()) {
544 aes_device.resource = omap3_aes_resources;
545 aes_device.num_resources = omap3_aes_resources_sz;
546 } else {
547 pr_err("%s: platform not supported\n", __func__);
533 return; 548 return;
534
535 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
536 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
537
538 for (i = 0; i < nr_controllers; i++) {
539 u32 v, base = 0;
540 struct clk *iclk, *fclk;
541 struct device *dev = &dummy_pdev.dev;
542
543 switch (i) {
544 case 0:
545 base = OMAP2_MMC1_BASE;
546 break;
547 case 1:
548 base = OMAP2_MMC2_BASE;
549 break;
550 case 2:
551 base = OMAP3_MMC3_BASE;
552 break;
553 case 3:
554 if (!cpu_is_omap44xx())
555 return;
556 base = OMAP4_MMC4_BASE;
557 break;
558 case 4:
559 if (!cpu_is_omap44xx())
560 return;
561 base = OMAP4_MMC5_BASE;
562 break;
563 }
564
565 if (cpu_is_omap44xx())
566 base += OMAP4_MMC_REG_OFFSET;
567
568 dummy_pdev.id = i;
569 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
570 iclk = clk_get(dev, "ick");
571 if (iclk && clk_enable(iclk))
572 iclk = NULL;
573
574 fclk = clk_get(dev, "fck");
575 if (fclk && clk_enable(fclk))
576 fclk = NULL;
577
578 if (!iclk || !fclk) {
579 printk(KERN_WARNING
580 "%s: Unable to enable clocks for MMC%d, "
581 "cannot reset.\n", __func__, i);
582 break;
583 }
584
585 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
586 v = omap_readl(base + MMCHS_SYSSTATUS);
587 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
588 MMCHS_SYSSTATUS_RESETDONE))
589 cpu_relax();
590
591 if (fclk) {
592 clk_disable(fclk);
593 clk_put(fclk);
594 }
595 if (iclk) {
596 clk_disable(iclk);
597 clk_put(iclk);
598 }
599 } 549 }
550 platform_device_register(&aes_device);
600} 551}
552
601#else 553#else
602static inline void omap_hsmmc_reset(void) {} 554static inline void omap_init_aes(void) { }
603#endif 555#endif
604 556
605#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ 557/*-------------------------------------------------------------------------*/
606 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 558
559#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
607 560
608static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, 561static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
609 int controller_nr) 562 *mmc_controller)
610{ 563{
611 if ((mmc_controller->slots[0].switch_pin > 0) && \ 564 if ((mmc_controller->slots[0].switch_pin > 0) && \
612 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 565 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
@@ -617,163 +570,44 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
617 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 570 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
618 OMAP_PIN_INPUT_PULLUP); 571 OMAP_PIN_INPUT_PULLUP);
619 572
620 if (cpu_is_omap2420() && controller_nr == 0) { 573 omap_mux_init_signal("sdmmc_cmd", 0);
621 omap_mux_init_signal("sdmmc_cmd", 0); 574 omap_mux_init_signal("sdmmc_clki", 0);
622 omap_mux_init_signal("sdmmc_clki", 0); 575 omap_mux_init_signal("sdmmc_clko", 0);
623 omap_mux_init_signal("sdmmc_clko", 0); 576 omap_mux_init_signal("sdmmc_dat0", 0);
624 omap_mux_init_signal("sdmmc_dat0", 0); 577 omap_mux_init_signal("sdmmc_dat_dir0", 0);
625 omap_mux_init_signal("sdmmc_dat_dir0", 0); 578 omap_mux_init_signal("sdmmc_cmd_dir", 0);
626 omap_mux_init_signal("sdmmc_cmd_dir", 0); 579 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
627 if (mmc_controller->slots[0].wires == 4) { 580 omap_mux_init_signal("sdmmc_dat1", 0);
628 omap_mux_init_signal("sdmmc_dat1", 0); 581 omap_mux_init_signal("sdmmc_dat2", 0);
629 omap_mux_init_signal("sdmmc_dat2", 0); 582 omap_mux_init_signal("sdmmc_dat3", 0);
630 omap_mux_init_signal("sdmmc_dat3", 0); 583 omap_mux_init_signal("sdmmc_dat_dir1", 0);
631 omap_mux_init_signal("sdmmc_dat_dir1", 0); 584 omap_mux_init_signal("sdmmc_dat_dir2", 0);
632 omap_mux_init_signal("sdmmc_dat_dir2", 0); 585 omap_mux_init_signal("sdmmc_dat_dir3", 0);
633 omap_mux_init_signal("sdmmc_dat_dir3", 0);
634 }
635
636 /*
637 * Use internal loop-back in MMC/SDIO Module Input Clock
638 * selection
639 */
640 if (mmc_controller->slots[0].internal_clock) {
641 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
642 v |= (1 << 24);
643 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
644 }
645 } 586 }
646 587
647 if (cpu_is_omap34xx()) { 588 /*
648 if (controller_nr == 0) { 589 * Use internal loop-back in MMC/SDIO Module Input Clock
649 omap_mux_init_signal("sdmmc1_clk", 590 * selection
650 OMAP_PIN_INPUT_PULLUP); 591 */
651 omap_mux_init_signal("sdmmc1_cmd", 592 if (mmc_controller->slots[0].internal_clock) {
652 OMAP_PIN_INPUT_PULLUP); 593 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
653 omap_mux_init_signal("sdmmc1_dat0", 594 v |= (1 << 24);
654 OMAP_PIN_INPUT_PULLUP); 595 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
655 if (mmc_controller->slots[0].wires == 4 ||
656 mmc_controller->slots[0].wires == 8) {
657 omap_mux_init_signal("sdmmc1_dat1",
658 OMAP_PIN_INPUT_PULLUP);
659 omap_mux_init_signal("sdmmc1_dat2",
660 OMAP_PIN_INPUT_PULLUP);
661 omap_mux_init_signal("sdmmc1_dat3",
662 OMAP_PIN_INPUT_PULLUP);
663 }
664 if (mmc_controller->slots[0].wires == 8) {
665 omap_mux_init_signal("sdmmc1_dat4",
666 OMAP_PIN_INPUT_PULLUP);
667 omap_mux_init_signal("sdmmc1_dat5",
668 OMAP_PIN_INPUT_PULLUP);
669 omap_mux_init_signal("sdmmc1_dat6",
670 OMAP_PIN_INPUT_PULLUP);
671 omap_mux_init_signal("sdmmc1_dat7",
672 OMAP_PIN_INPUT_PULLUP);
673 }
674 }
675 if (controller_nr == 1) {
676 /* MMC2 */
677 omap_mux_init_signal("sdmmc2_clk",
678 OMAP_PIN_INPUT_PULLUP);
679 omap_mux_init_signal("sdmmc2_cmd",
680 OMAP_PIN_INPUT_PULLUP);
681 omap_mux_init_signal("sdmmc2_dat0",
682 OMAP_PIN_INPUT_PULLUP);
683
684 /*
685 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
686 * in the board-*.c files
687 */
688 if (mmc_controller->slots[0].wires == 4 ||
689 mmc_controller->slots[0].wires == 8) {
690 omap_mux_init_signal("sdmmc2_dat1",
691 OMAP_PIN_INPUT_PULLUP);
692 omap_mux_init_signal("sdmmc2_dat2",
693 OMAP_PIN_INPUT_PULLUP);
694 omap_mux_init_signal("sdmmc2_dat3",
695 OMAP_PIN_INPUT_PULLUP);
696 }
697 if (mmc_controller->slots[0].wires == 8) {
698 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
699 OMAP_PIN_INPUT_PULLUP);
700 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
701 OMAP_PIN_INPUT_PULLUP);
702 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
703 OMAP_PIN_INPUT_PULLUP);
704 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
705 OMAP_PIN_INPUT_PULLUP);
706 }
707 }
708
709 /*
710 * For MMC3 the pins need to be muxed in the board-*.c files
711 */
712 } 596 }
713} 597}
714 598
715void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 599void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
716 int nr_controllers)
717{ 600{
718 int i; 601 char *name = "mmci-omap";
719 char *name;
720 602
721 for (i = 0; i < nr_controllers; i++) { 603 if (!mmc_data[0]) {
722 unsigned long base, size; 604 pr_err("%s fails: Incomplete platform data\n", __func__);
723 unsigned int irq = 0; 605 return;
724 606 }
725 if (!mmc_data[i])
726 continue;
727
728 omap2_mmc_mux(mmc_data[i], i);
729 607
730 switch (i) { 608 omap242x_mmc_mux(mmc_data[0]);
731 case 0: 609 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
732 base = OMAP2_MMC1_BASE; 610 INT_24XX_MMC_IRQ, mmc_data[0]);
733 irq = INT_24XX_MMC_IRQ;
734 break;
735 case 1:
736 base = OMAP2_MMC2_BASE;
737 irq = INT_24XX_MMC2_IRQ;
738 break;
739 case 2:
740 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
741 return;
742 base = OMAP3_MMC3_BASE;
743 irq = INT_34XX_MMC3_IRQ;
744 break;
745 case 3:
746 if (!cpu_is_omap44xx())
747 return;
748 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
749 irq = OMAP44XX_IRQ_MMC4;
750 break;
751 case 4:
752 if (!cpu_is_omap44xx())
753 return;
754 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
755 irq = OMAP44XX_IRQ_MMC5;
756 break;
757 default:
758 continue;
759 }
760
761 if (cpu_is_omap2420()) {
762 size = OMAP2420_MMC_SIZE;
763 name = "mmci-omap";
764 } else if (cpu_is_omap44xx()) {
765 if (i < 3) {
766 base += OMAP4_MMC_REG_OFFSET;
767 irq += OMAP44XX_IRQ_GIC_START;
768 }
769 size = OMAP4_HSMMC_SIZE;
770 name = "mmci-omap-hs";
771 } else {
772 size = OMAP3_HSMMC_SIZE;
773 name = "mmci-omap-hs";
774 }
775 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
776 };
777} 611}
778 612
779#endif 613#endif
@@ -781,7 +615,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
781/*-------------------------------------------------------------------------*/ 615/*-------------------------------------------------------------------------*/
782 616
783#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) 617#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
784#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 618#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
785#define OMAP_HDQ_BASE 0x480B2000 619#define OMAP_HDQ_BASE 0x480B2000
786#endif 620#endif
787static struct resource omap_hdq_resources[] = { 621static struct resource omap_hdq_resources[] = {
@@ -843,10 +677,11 @@ static inline void omap_init_vout(void) {}
843 677
844static int __init omap2_init_devices(void) 678static int __init omap2_init_devices(void)
845{ 679{
846 /* please keep these calls, and their implementations above, 680 /*
681 * please keep these calls, and their implementations above,
847 * in alphabetical order so they're easier to sort through. 682 * in alphabetical order so they're easier to sort through.
848 */ 683 */
849 omap_hsmmc_reset(); 684 omap_init_audio();
850 omap_init_camera(); 685 omap_init_camera();
851 omap_init_mbox(); 686 omap_init_mbox();
852 omap_init_mcspi(); 687 omap_init_mcspi();
@@ -854,8 +689,45 @@ static int __init omap2_init_devices(void)
854 omap_hdq_init(); 689 omap_hdq_init();
855 omap_init_sti(); 690 omap_init_sti();
856 omap_init_sham(); 691 omap_init_sham();
692 omap_init_aes();
857 omap_init_vout(); 693 omap_init_vout();
858 694
859 return 0; 695 return 0;
860} 696}
861arch_initcall(omap2_init_devices); 697arch_initcall(omap2_init_devices);
698
699#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
700static struct omap_device_pm_latency omap_wdt_latency[] = {
701 [0] = {
702 .deactivate_func = omap_device_idle_hwmods,
703 .activate_func = omap_device_enable_hwmods,
704 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
705 },
706};
707
708static int __init omap_init_wdt(void)
709{
710 int id = -1;
711 struct omap_device *od;
712 struct omap_hwmod *oh;
713 char *oh_name = "wd_timer2";
714 char *dev_name = "omap_wdt";
715
716 if (!cpu_class_is_omap2())
717 return 0;
718
719 oh = omap_hwmod_lookup(oh_name);
720 if (!oh) {
721 pr_err("Could not look up wd_timer%d hwmod\n", id);
722 return -EINVAL;
723 }
724
725 od = omap_device_build(dev_name, id, oh, NULL, 0,
726 omap_wdt_latency,
727 ARRAY_SIZE(omap_wdt_latency), 0);
728 WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
729 dev_name, oh->name);
730 return 0;
731}
732subsys_initcall(omap_init_wdt);
733#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 19:46:05 -0400