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-rw-r--r--arch/arm/mach-omap2/serial.c619
1 files changed, 329 insertions, 290 deletions
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 566e991ede81..1ac361b7b8cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,20 +19,33 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_reg.h> 22#include <linux/serial_reg.h>
24#include <linux/clk.h> 23#include <linux/clk.h>
25#include <linux/io.h> 24#include <linux/io.h>
26#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28#include <linux/serial_8250.h>
29#include <linux/pm_runtime.h>
30#include <linux/console.h>
31
32#ifdef CONFIG_SERIAL_OMAP
33#include <plat/omap-serial.h>
34#endif
27 35
28#include <plat/common.h> 36#include <plat/common.h>
29#include <plat/board.h> 37#include <plat/board.h>
30#include <plat/clock.h> 38#include <plat/clock.h>
31#include <plat/control.h> 39#include <plat/dma.h>
40#include <plat/omap_hwmod.h>
41#include <plat/omap_device.h>
32 42
33#include "prm.h" 43#include "prm2xxx_3xxx.h"
34#include "pm.h" 44#include "pm.h"
45#include "cm2xxx_3xxx.h"
35#include "prm-regbits-34xx.h" 46#include "prm-regbits-34xx.h"
47#include "control.h"
48#include "mux.h"
36 49
37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 50#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
38#define UART_OMAP_WER 0x17 /* Wake-up enable register */ 51#define UART_OMAP_WER 0x17 /* Wake-up enable register */
@@ -48,6 +61,8 @@
48 */ 61 */
49#define DEFAULT_TIMEOUT 0 62#define DEFAULT_TIMEOUT 0
50 63
64#define MAX_UART_HWMOD_NAME_LEN 16
65
51struct omap_uart_state { 66struct omap_uart_state {
52 int num; 67 int num;
53 int can_sleep; 68 int can_sleep;
@@ -58,14 +73,21 @@ struct omap_uart_state {
58 void __iomem *wk_en; 73 void __iomem *wk_en;
59 u32 wk_mask; 74 u32 wk_mask;
60 u32 padconf; 75 u32 padconf;
76 u32 dma_enabled;
61 77
62 struct clk *ick; 78 struct clk *ick;
63 struct clk *fck; 79 struct clk *fck;
64 int clocked; 80 int clocked;
65 81
66 struct plat_serial8250_port *p; 82 int irq;
83 int regshift;
84 int irqflags;
85 void __iomem *membase;
86 resource_size_t mapbase;
87
67 struct list_head node; 88 struct list_head node;
68 struct platform_device pdev; 89 struct omap_hwmod *oh;
90 struct platform_device *pdev;
69 91
70 u32 errata; 92 u32 errata;
71#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 93#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
@@ -83,75 +105,42 @@ struct omap_uart_state {
83}; 105};
84 106
85static LIST_HEAD(uart_list); 107static LIST_HEAD(uart_list);
108static u8 num_uarts;
86 109
87static struct plat_serial8250_port serial_platform_data0[] = { 110static int uart_idle_hwmod(struct omap_device *od)
88 { 111{
89 .irq = 72, 112 omap_hwmod_idle(od->hwmods[0]);
90 .flags = UPF_BOOT_AUTOCONF,
91 .iotype = UPIO_MEM,
92 .regshift = 2,
93 .uartclk = OMAP24XX_BASE_BAUD * 16,
94 }, {
95 .flags = 0
96 }
97};
98 113
99static struct plat_serial8250_port serial_platform_data1[] = { 114 return 0;
100 { 115}
101 .irq = 73,
102 .flags = UPF_BOOT_AUTOCONF,
103 .iotype = UPIO_MEM,
104 .regshift = 2,
105 .uartclk = OMAP24XX_BASE_BAUD * 16,
106 }, {
107 .flags = 0
108 }
109};
110 116
111static struct plat_serial8250_port serial_platform_data2[] = { 117static int uart_enable_hwmod(struct omap_device *od)
112 { 118{
113 .irq = 74, 119 omap_hwmod_enable(od->hwmods[0]);
114 .flags = UPF_BOOT_AUTOCONF,
115 .iotype = UPIO_MEM,
116 .regshift = 2,
117 .uartclk = OMAP24XX_BASE_BAUD * 16,
118 }, {
119 .flags = 0
120 }
121};
122 120
123static struct plat_serial8250_port serial_platform_data3[] = { 121 return 0;
122}
123
124static struct omap_device_pm_latency omap_uart_latency[] = {
124 { 125 {
125 .irq = 70, 126 .deactivate_func = uart_idle_hwmod,
126 .flags = UPF_BOOT_AUTOCONF, 127 .activate_func = uart_enable_hwmod,
127 .iotype = UPIO_MEM, 128 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
128 .regshift = 2, 129 },
129 .uartclk = OMAP24XX_BASE_BAUD * 16,
130 }, {
131 .flags = 0
132 }
133}; 130};
134 131
135void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
136{
137 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
138 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
139 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
140 serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
141}
142
143static inline unsigned int __serial_read_reg(struct uart_port *up, 132static inline unsigned int __serial_read_reg(struct uart_port *up,
144 int offset) 133 int offset)
145{ 134{
146 offset <<= up->regshift; 135 offset <<= up->regshift;
147 return (unsigned int)__raw_readb(up->membase + offset); 136 return (unsigned int)__raw_readb(up->membase + offset);
148} 137}
149 138
150static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, 139static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
151 int offset) 140 int offset)
152{ 141{
153 offset <<= up->regshift; 142 offset <<= uart->regshift;
154 return (unsigned int)__raw_readb(up->membase + offset); 143 return (unsigned int)__raw_readb(uart->membase + offset);
155} 144}
156 145
157static inline void __serial_write_reg(struct uart_port *up, int offset, 146static inline void __serial_write_reg(struct uart_port *up, int offset,
@@ -161,11 +150,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset,
161 __raw_writeb(value, up->membase + offset); 150 __raw_writeb(value, up->membase + offset);
162} 151}
163 152
164static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, 153static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
165 int value) 154 int value)
166{ 155{
167 offset <<= p->regshift; 156 offset <<= uart->regshift;
168 __raw_writeb(value, p->membase + offset); 157 __raw_writeb(value, uart->membase + offset);
169} 158}
170 159
171/* 160/*
@@ -173,14 +162,12 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
173 * properly. Note that the TX watermark initialization may not be needed 162 * properly. Note that the TX watermark initialization may not be needed
174 * once the 8250.c watermark handling code is merged. 163 * once the 8250.c watermark handling code is merged.
175 */ 164 */
165
176static inline void __init omap_uart_reset(struct omap_uart_state *uart) 166static inline void __init omap_uart_reset(struct omap_uart_state *uart)
177{ 167{
178 struct plat_serial8250_port *p = uart->p; 168 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
179 169 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
180 serial_write_reg(p, UART_OMAP_MDR1, 0x07); 170 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
181 serial_write_reg(p, UART_OMAP_SCR, 0x08);
182 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
183 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
184} 171}
185 172
186#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) 173#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
@@ -197,24 +184,23 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
197static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, 184static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
198 u8 fcr_val) 185 u8 fcr_val)
199{ 186{
200 struct plat_serial8250_port *p = uart->p;
201 u8 timeout = 255; 187 u8 timeout = 255;
202 188
203 serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); 189 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
204 udelay(2); 190 udelay(2);
205 serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | 191 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
206 UART_FCR_CLEAR_RCVR); 192 UART_FCR_CLEAR_RCVR);
207 /* 193 /*
208 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 194 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
209 * TX_FIFO_E bit is 1. 195 * TX_FIFO_E bit is 1.
210 */ 196 */
211 while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & 197 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
212 (UART_LSR_THRE | UART_LSR_DR))) { 198 (UART_LSR_THRE | UART_LSR_DR))) {
213 timeout--; 199 timeout--;
214 if (!timeout) { 200 if (!timeout) {
215 /* Should *never* happen. we warn and carry on */ 201 /* Should *never* happen. we warn and carry on */
216 dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", 202 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
217 serial_read_reg(p, UART_LSR)); 203 serial_read_reg(uart, UART_LSR));
218 break; 204 break;
219 } 205 }
220 udelay(1); 206 udelay(1);
@@ -224,23 +210,22 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
224static void omap_uart_save_context(struct omap_uart_state *uart) 210static void omap_uart_save_context(struct omap_uart_state *uart)
225{ 211{
226 u16 lcr = 0; 212 u16 lcr = 0;
227 struct plat_serial8250_port *p = uart->p;
228 213
229 if (!enable_off_mode) 214 if (!enable_off_mode)
230 return; 215 return;
231 216
232 lcr = serial_read_reg(p, UART_LCR); 217 lcr = serial_read_reg(uart, UART_LCR);
233 serial_write_reg(p, UART_LCR, 0xBF); 218 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
234 uart->dll = serial_read_reg(p, UART_DLL); 219 uart->dll = serial_read_reg(uart, UART_DLL);
235 uart->dlh = serial_read_reg(p, UART_DLM); 220 uart->dlh = serial_read_reg(uart, UART_DLM);
236 serial_write_reg(p, UART_LCR, lcr); 221 serial_write_reg(uart, UART_LCR, lcr);
237 uart->ier = serial_read_reg(p, UART_IER); 222 uart->ier = serial_read_reg(uart, UART_IER);
238 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); 223 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
239 uart->scr = serial_read_reg(p, UART_OMAP_SCR); 224 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
240 uart->wer = serial_read_reg(p, UART_OMAP_WER); 225 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
241 serial_write_reg(p, UART_LCR, 0x80); 226 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
242 uart->mcr = serial_read_reg(p, UART_MCR); 227 uart->mcr = serial_read_reg(uart, UART_MCR);
243 serial_write_reg(p, UART_LCR, lcr); 228 serial_write_reg(uart, UART_LCR, lcr);
244 229
245 uart->context_valid = 1; 230 uart->context_valid = 1;
246} 231}
@@ -248,7 +233,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
248static void omap_uart_restore_context(struct omap_uart_state *uart) 233static void omap_uart_restore_context(struct omap_uart_state *uart)
249{ 234{
250 u16 efr = 0; 235 u16 efr = 0;
251 struct plat_serial8250_port *p = uart->p;
252 236
253 if (!enable_off_mode) 237 if (!enable_off_mode)
254 return; 238 return;
@@ -259,31 +243,35 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
259 uart->context_valid = 0; 243 uart->context_valid = 0;
260 244
261 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) 245 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
262 omap_uart_mdr1_errataset(uart, 0x07, 0xA0); 246 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
263 else 247 else
264 serial_write_reg(p, UART_OMAP_MDR1, 0x7); 248 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
265 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ 249
266 efr = serial_read_reg(p, UART_EFR); 250 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
267 serial_write_reg(p, UART_EFR, UART_EFR_ECB); 251 efr = serial_read_reg(uart, UART_EFR);
268 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ 252 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
269 serial_write_reg(p, UART_IER, 0x0); 253 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
270 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ 254 serial_write_reg(uart, UART_IER, 0x0);
271 serial_write_reg(p, UART_DLL, uart->dll); 255 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
272 serial_write_reg(p, UART_DLM, uart->dlh); 256 serial_write_reg(uart, UART_DLL, uart->dll);
273 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ 257 serial_write_reg(uart, UART_DLM, uart->dlh);
274 serial_write_reg(p, UART_IER, uart->ier); 258 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
275 serial_write_reg(p, UART_LCR, 0x80); 259 serial_write_reg(uart, UART_IER, uart->ier);
276 serial_write_reg(p, UART_MCR, uart->mcr); 260 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
277 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ 261 serial_write_reg(uart, UART_MCR, uart->mcr);
278 serial_write_reg(p, UART_EFR, efr); 262 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
279 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); 263 serial_write_reg(uart, UART_EFR, efr);
280 serial_write_reg(p, UART_OMAP_SCR, uart->scr); 264 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
281 serial_write_reg(p, UART_OMAP_WER, uart->wer); 265 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
282 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); 266 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
267 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
268
283 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) 269 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
284 omap_uart_mdr1_errataset(uart, 0x00, 0xA1); 270 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
285 else 271 else
286 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ 272 /* UART 16x mode */
273 serial_write_reg(uart, UART_OMAP_MDR1,
274 UART_OMAP_MDR1_16X_MODE);
287} 275}
288#else 276#else
289static inline void omap_uart_save_context(struct omap_uart_state *uart) {} 277static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
@@ -295,8 +283,7 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
295 if (uart->clocked) 283 if (uart->clocked)
296 return; 284 return;
297 285
298 clk_enable(uart->ick); 286 omap_device_enable(uart->pdev);
299 clk_enable(uart->fck);
300 uart->clocked = 1; 287 uart->clocked = 1;
301 omap_uart_restore_context(uart); 288 omap_uart_restore_context(uart);
302} 289}
@@ -310,8 +297,7 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
310 297
311 omap_uart_save_context(uart); 298 omap_uart_save_context(uart);
312 uart->clocked = 0; 299 uart->clocked = 0;
313 clk_disable(uart->ick); 300 omap_device_idle(uart->pdev);
314 clk_disable(uart->fck);
315} 301}
316 302
317static void omap_uart_enable_wakeup(struct omap_uart_state *uart) 303static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
@@ -349,18 +335,24 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
349} 335}
350 336
351static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, 337static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
352 int enable) 338 int enable)
353{ 339{
354 struct plat_serial8250_port *p = uart->p; 340 u8 idlemode;
355 u16 sysc;
356 341
357 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; 342 if (enable) {
358 if (enable) 343 /**
359 sysc |= 0x2 << 3; 344 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
360 else 345 * in Smartidle Mode When Configured for DMA Operations.
361 sysc |= 0x1 << 3; 346 */
347 if (uart->dma_enabled)
348 idlemode = HWMOD_IDLEMODE_FORCE;
349 else
350 idlemode = HWMOD_IDLEMODE_SMART;
351 } else {
352 idlemode = HWMOD_IDLEMODE_NO;
353 }
362 354
363 serial_write_reg(p, UART_OMAP_SYSC, sysc); 355 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
364} 356}
365 357
366static void omap_uart_block_sleep(struct omap_uart_state *uart) 358static void omap_uart_block_sleep(struct omap_uart_state *uart)
@@ -377,7 +369,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
377 369
378static void omap_uart_allow_sleep(struct omap_uart_state *uart) 370static void omap_uart_allow_sleep(struct omap_uart_state *uart)
379{ 371{
380 if (device_may_wakeup(&uart->pdev.dev)) 372 if (device_may_wakeup(&uart->pdev->dev))
381 omap_uart_enable_wakeup(uart); 373 omap_uart_enable_wakeup(uart);
382 else 374 else
383 omap_uart_disable_wakeup(uart); 375 omap_uart_disable_wakeup(uart);
@@ -414,7 +406,7 @@ void omap_uart_resume_idle(int num)
414 struct omap_uart_state *uart; 406 struct omap_uart_state *uart;
415 407
416 list_for_each_entry(uart, &uart_list, node) { 408 list_for_each_entry(uart, &uart_list, node) {
417 if (num == uart->num) { 409 if (num == uart->num && uart->can_sleep) {
418 omap_uart_enable_clocks(uart); 410 omap_uart_enable_clocks(uart);
419 411
420 /* Check for IO pad wakeup */ 412 /* Check for IO pad wakeup */
@@ -472,6 +464,7 @@ int omap_uart_can_sleep(void)
472 * UART will not idle or sleep for its timeout period. 464 * UART will not idle or sleep for its timeout period.
473 * 465 *
474 **/ 466 **/
467/* static int first_interrupt; */
475static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) 468static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
476{ 469{
477 struct omap_uart_state *uart = dev_id; 470 struct omap_uart_state *uart = dev_id;
@@ -483,7 +476,6 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
483 476
484static void omap_uart_idle_init(struct omap_uart_state *uart) 477static void omap_uart_idle_init(struct omap_uart_state *uart)
485{ 478{
486 struct plat_serial8250_port *p = uart->p;
487 int ret; 479 int ret;
488 480
489 uart->can_sleep = 0; 481 uart->can_sleep = 0;
@@ -494,11 +486,12 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
494 mod_timer(&uart->timer, jiffies + uart->timeout); 486 mod_timer(&uart->timer, jiffies + uart->timeout);
495 omap_uart_smart_idle_enable(uart, 0); 487 omap_uart_smart_idle_enable(uart, 0);
496 488
497 if (cpu_is_omap34xx()) { 489 if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
498 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; 490 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
499 u32 wk_mask = 0; 491 u32 wk_mask = 0;
500 u32 padconf = 0; 492 u32 padconf = 0;
501 493
494 /* XXX These PRM accesses do not belong here */
502 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); 495 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
503 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); 496 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
504 switch (uart->num) { 497 switch (uart->num) {
@@ -514,19 +507,17 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
514 wk_mask = OMAP3430_ST_UART3_MASK; 507 wk_mask = OMAP3430_ST_UART3_MASK;
515 padconf = 0x19e; 508 padconf = 0x19e;
516 break; 509 break;
510 case 3:
511 wk_mask = OMAP3630_ST_UART4_MASK;
512 padconf = 0x0d2;
513 break;
517 } 514 }
518 uart->wk_mask = wk_mask; 515 uart->wk_mask = wk_mask;
519 uart->padconf = padconf; 516 uart->padconf = padconf;
520 } else if (cpu_is_omap24xx()) { 517 } else if (cpu_is_omap24xx()) {
521 u32 wk_mask = 0; 518 u32 wk_mask = 0;
519 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
522 520
523 if (cpu_is_omap2430()) {
524 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
525 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
526 } else if (cpu_is_omap2420()) {
527 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
528 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
529 }
530 switch (uart->num) { 521 switch (uart->num) {
531 case 0: 522 case 0:
532 wk_mask = OMAP24XX_ST_UART1_MASK; 523 wk_mask = OMAP24XX_ST_UART1_MASK;
@@ -535,10 +526,19 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
535 wk_mask = OMAP24XX_ST_UART2_MASK; 526 wk_mask = OMAP24XX_ST_UART2_MASK;
536 break; 527 break;
537 case 2: 528 case 2:
529 wk_en = OMAP24XX_PM_WKEN2;
530 wk_st = OMAP24XX_PM_WKST2;
538 wk_mask = OMAP24XX_ST_UART3_MASK; 531 wk_mask = OMAP24XX_ST_UART3_MASK;
539 break; 532 break;
540 } 533 }
541 uart->wk_mask = wk_mask; 534 uart->wk_mask = wk_mask;
535 if (cpu_is_omap2430()) {
536 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
537 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
538 } else if (cpu_is_omap2420()) {
539 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
540 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
541 }
542 } else { 542 } else {
543 uart->wk_en = NULL; 543 uart->wk_en = NULL;
544 uart->wk_st = NULL; 544 uart->wk_st = NULL;
@@ -546,9 +546,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
546 uart->padconf = 0; 546 uart->padconf = 0;
547 } 547 }
548 548
549 p->irqflags |= IRQF_SHARED; 549 uart->irqflags |= IRQF_SHARED;
550 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, 550 ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
551 "serial idle", (void *)uart); 551 IRQF_SHARED, "serial idle", (void *)uart);
552 WARN_ON(ret); 552 WARN_ON(ret);
553} 553}
554 554
@@ -558,11 +558,17 @@ void omap_uart_enable_irqs(int enable)
558 struct omap_uart_state *uart; 558 struct omap_uart_state *uart;
559 559
560 list_for_each_entry(uart, &uart_list, node) { 560 list_for_each_entry(uart, &uart_list, node) {
561 if (enable) 561 if (enable) {
562 ret = request_irq(uart->p->irq, omap_uart_interrupt, 562 pm_runtime_put_sync(&uart->pdev->dev);
563 IRQF_SHARED, "serial idle", (void *)uart); 563 ret = request_threaded_irq(uart->irq, NULL,
564 else 564 omap_uart_interrupt,
565 free_irq(uart->p->irq, (void *)uart); 565 IRQF_SHARED,
566 "serial idle",
567 (void *)uart);
568 } else {
569 pm_runtime_get_noresume(&uart->pdev->dev);
570 free_irq(uart->irq, (void *)uart);
571 }
566 } 572 }
567} 573}
568 574
@@ -570,10 +576,9 @@ static ssize_t sleep_timeout_show(struct device *dev,
570 struct device_attribute *attr, 576 struct device_attribute *attr,
571 char *buf) 577 char *buf)
572{ 578{
573 struct platform_device *pdev = container_of(dev, 579 struct platform_device *pdev = to_platform_device(dev);
574 struct platform_device, dev); 580 struct omap_device *odev = to_omap_device(pdev);
575 struct omap_uart_state *uart = container_of(pdev, 581 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
576 struct omap_uart_state, pdev);
577 582
578 return sprintf(buf, "%u\n", uart->timeout / HZ); 583 return sprintf(buf, "%u\n", uart->timeout / HZ);
579} 584}
@@ -582,10 +587,9 @@ static ssize_t sleep_timeout_store(struct device *dev,
582 struct device_attribute *attr, 587 struct device_attribute *attr,
583 const char *buf, size_t n) 588 const char *buf, size_t n)
584{ 589{
585 struct platform_device *pdev = container_of(dev, 590 struct platform_device *pdev = to_platform_device(dev);
586 struct platform_device, dev); 591 struct omap_device *odev = to_omap_device(pdev);
587 struct omap_uart_state *uart = container_of(pdev, 592 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
588 struct omap_uart_state, pdev);
589 unsigned int value; 593 unsigned int value;
590 594
591 if (sscanf(buf, "%u", &value) != 1) { 595 if (sscanf(buf, "%u", &value) != 1) {
@@ -608,48 +612,15 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
608#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) 612#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
609#else 613#else
610static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} 614static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
615static void omap_uart_block_sleep(struct omap_uart_state *uart)
616{
617 /* Needed to enable UART clocks when built without CONFIG_PM */
618 omap_uart_enable_clocks(uart);
619}
611#define DEV_CREATE_FILE(dev, attr) 620#define DEV_CREATE_FILE(dev, attr)
612#endif /* CONFIG_PM */ 621#endif /* CONFIG_PM */
613 622
614static struct omap_uart_state omap_uart[] = { 623#ifndef CONFIG_SERIAL_OMAP
615 {
616 .pdev = {
617 .name = "serial8250",
618 .id = PLAT8250_DEV_PLATFORM,
619 .dev = {
620 .platform_data = serial_platform_data0,
621 },
622 },
623 }, {
624 .pdev = {
625 .name = "serial8250",
626 .id = PLAT8250_DEV_PLATFORM1,
627 .dev = {
628 .platform_data = serial_platform_data1,
629 },
630 },
631 }, {
632 .pdev = {
633 .name = "serial8250",
634 .id = PLAT8250_DEV_PLATFORM2,
635 .dev = {
636 .platform_data = serial_platform_data2,
637 },
638 },
639 },
640#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
641 {
642 .pdev = {
643 .name = "serial8250",
644 .id = 3,
645 .dev = {
646 .platform_data = serial_platform_data3,
647 },
648 },
649 },
650#endif
651};
652
653/* 624/*
654 * Override the default 8250 read handler: mem_serial_in() 625 * Override the default 8250 read handler: mem_serial_in()
655 * Empty RX fifo read causes an abort on omap3630 and omap4 626 * Empty RX fifo read causes an abort on omap3630 and omap4
@@ -682,143 +653,209 @@ static void serial_out_override(struct uart_port *up, int offset, int value)
682 } 653 }
683 __serial_write_reg(up, offset, value); 654 __serial_write_reg(up, offset, value);
684} 655}
685void __init omap_serial_early_init(void) 656#endif
657
658static int __init omap_serial_early_init(void)
686{ 659{
687 int i, nr_ports; 660 int i = 0;
688 char name[16];
689 661
690 if (!(cpu_is_omap3630() || cpu_is_omap4430())) 662 do {
691 nr_ports = 3; 663 char oh_name[MAX_UART_HWMOD_NAME_LEN];
692 else 664 struct omap_hwmod *oh;
693 nr_ports = ARRAY_SIZE(omap_uart); 665 struct omap_uart_state *uart;
694 666
695 /* 667 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
696 * Make sure the serial ports are muxed on at this point. 668 "uart%d", i + 1);
697 * You have to mux them off in device drivers later on 669 oh = omap_hwmod_lookup(oh_name);
698 * if not needed. 670 if (!oh)
699 */ 671 break;
700 672
701 for (i = 0; i < nr_ports; i++) { 673 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
702 struct omap_uart_state *uart = &omap_uart[i]; 674 if (WARN_ON(!uart))
703 struct platform_device *pdev = &uart->pdev; 675 return -ENODEV;
704 struct device *dev = &pdev->dev; 676
705 struct plat_serial8250_port *p = dev->platform_data; 677 uart->oh = oh;
678 uart->num = i++;
679 list_add_tail(&uart->node, &uart_list);
680 num_uarts++;
706 681
707 /* Don't map zero-based physical address */
708 if (p->mapbase == 0) {
709 dev_warn(dev, "no physical address for uart#%d,"
710 " so skipping early_init...\n", i);
711 continue;
712 }
713 /* 682 /*
714 * Module 4KB + L4 interconnect 4KB 683 * NOTE: omap_hwmod_setup*() has not yet been called,
715 * Static mapping, never released 684 * so no hwmod functions will work yet.
716 */ 685 */
717 p->membase = ioremap(p->mapbase, SZ_8K);
718 if (!p->membase) {
719 dev_err(dev, "ioremap failed for uart%i\n", i + 1);
720 continue;
721 }
722
723 sprintf(name, "uart%d_ick", i + 1);
724 uart->ick = clk_get(NULL, name);
725 if (IS_ERR(uart->ick)) {
726 dev_err(dev, "Could not get uart%d_ick\n", i + 1);
727 uart->ick = NULL;
728 }
729
730 sprintf(name, "uart%d_fck", i+1);
731 uart->fck = clk_get(NULL, name);
732 if (IS_ERR(uart->fck)) {
733 dev_err(dev, "Could not get uart%d_fck\n", i + 1);
734 uart->fck = NULL;
735 }
736
737 /* FIXME: Remove this once the clkdev is ready */
738 if (!cpu_is_omap44xx()) {
739 if (!uart->ick || !uart->fck)
740 continue;
741 }
742 686
743 uart->num = i; 687 /*
744 p->private_data = uart; 688 * During UART early init, device need to be probed
745 uart->p = p; 689 * to determine SoC specific init before omap_device
690 * is ready. Therefore, don't allow idle here
691 */
692 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
693 } while (1);
746 694
747 if (cpu_is_omap44xx()) 695 return 0;
748 p->irq += 32;
749 }
750} 696}
697core_initcall(omap_serial_early_init);
751 698
752/** 699/**
753 * omap_serial_init_port() - initialize single serial port 700 * omap_serial_init_port() - initialize single serial port
754 * @port: serial port number (0-3) 701 * @bdata: port specific board data pointer
755 * 702 *
756 * This function initialies serial driver for given @port only. 703 * This function initialies serial driver for given port only.
757 * Platforms can call this function instead of omap_serial_init() 704 * Platforms can call this function instead of omap_serial_init()
758 * if they don't plan to use all available UARTs as serial ports. 705 * if they don't plan to use all available UARTs as serial ports.
759 * 706 *
760 * Don't mix calls to omap_serial_init_port() and omap_serial_init(), 707 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
761 * use only one of the two. 708 * use only one of the two.
762 */ 709 */
763void __init omap_serial_init_port(int port) 710void __init omap_serial_init_port(struct omap_board_data *bdata)
764{ 711{
765 struct omap_uart_state *uart; 712 struct omap_uart_state *uart;
766 struct platform_device *pdev; 713 struct omap_hwmod *oh;
767 struct device *dev; 714 struct omap_device *od;
768 715 void *pdata = NULL;
769 BUG_ON(port < 0); 716 u32 pdata_size = 0;
770 BUG_ON(port >= ARRAY_SIZE(omap_uart)); 717 char *name;
771 718#ifndef CONFIG_SERIAL_OMAP
772 uart = &omap_uart[port]; 719 struct plat_serial8250_port ports[2] = {
773 pdev = &uart->pdev; 720 {},
774 dev = &pdev->dev; 721 {.flags = 0},
722 };
723 struct plat_serial8250_port *p = &ports[0];
724#else
725 struct omap_uart_port_info omap_up;
726#endif
775 727
776 /* Don't proceed if there's no clocks available */ 728 if (WARN_ON(!bdata))
777 if (unlikely(!uart->ick || !uart->fck)) { 729 return;
778 WARN(1, "%s: can't init uart%d, no clocks available\n", 730 if (WARN_ON(bdata->id < 0))
779 kobject_name(&dev->kobj), port); 731 return;
732 if (WARN_ON(bdata->id >= num_uarts))
780 return; 733 return;
781 }
782
783 omap_uart_enable_clocks(uart);
784
785 omap_uart_reset(uart);
786 omap_uart_idle_init(uart);
787 734
788 list_add_tail(&uart->node, &uart_list); 735 list_for_each_entry(uart, &uart_list, node)
736 if (bdata->id == uart->num)
737 break;
789 738
790 if (WARN_ON(platform_device_register(pdev))) 739 oh = uart->oh;
791 return; 740 uart->dma_enabled = 0;
741#ifndef CONFIG_SERIAL_OMAP
742 name = "serial8250";
792 743
793 if ((cpu_is_omap34xx() && uart->padconf) || 744 /*
794 (uart->wk_en && uart->wk_mask)) { 745 * !! 8250 driver does not use standard IORESOURCE* It
795 device_init_wakeup(dev, true); 746 * has it's own custom pdata that can be taken from
796 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); 747 * the hwmod resource data. But, this needs to be
797 } 748 * done after the build.
749 *
750 * ?? does it have to be done before the register ??
751 * YES, because platform_device_data_add() copies
752 * pdata, it does not use a pointer.
753 */
754 p->flags = UPF_BOOT_AUTOCONF;
755 p->iotype = UPIO_MEM;
756 p->regshift = 2;
757 p->uartclk = OMAP24XX_BASE_BAUD * 16;
758 p->irq = oh->mpu_irqs[0].irq;
759 p->mapbase = oh->slaves[0]->addr->pa_start;
760 p->membase = omap_hwmod_get_mpu_rt_va(oh);
761 p->irqflags = IRQF_SHARED;
762 p->private_data = uart;
798 763
799 /* 764 /*
800 * omap44xx: Never read empty UART fifo 765 * omap44xx, ti816x: Never read empty UART fifo
801 * omap3xxx: Never read empty UART fifo on UARTs 766 * omap3xxx: Never read empty UART fifo on UARTs
802 * with IP rev >=0x52 767 * with IP rev >=0x52
803 */ 768 */
804 if (cpu_is_omap44xx()) 769 uart->regshift = p->regshift;
770 uart->membase = p->membase;
771 if (cpu_is_omap44xx() || cpu_is_ti816x())
805 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; 772 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
806 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) 773 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
807 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) 774 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
808 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; 775 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
809 776
810 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { 777 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
811 uart->p->serial_in = serial_in_override; 778 p->serial_in = serial_in_override;
812 uart->p->serial_out = serial_out_override; 779 p->serial_out = serial_out_override;
780 }
781
782 pdata = &ports[0];
783 pdata_size = 2 * sizeof(struct plat_serial8250_port);
784#else
785
786 name = DRIVER_NAME;
787
788 omap_up.dma_enabled = uart->dma_enabled;
789 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
790 omap_up.mapbase = oh->slaves[0]->addr->pa_start;
791 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
792 omap_up.irqflags = IRQF_SHARED;
793 omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
794
795 pdata = &omap_up;
796 pdata_size = sizeof(struct omap_uart_port_info);
797#endif
798
799 if (WARN_ON(!oh))
800 return;
801
802 od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
803 omap_uart_latency,
804 ARRAY_SIZE(omap_uart_latency), false);
805 WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
806 name, oh->name);
807
808 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
809
810 uart->irq = oh->mpu_irqs[0].irq;
811 uart->regshift = 2;
812 uart->mapbase = oh->slaves[0]->addr->pa_start;
813 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
814 uart->pdev = &od->pdev;
815
816 oh->dev_attr = uart;
817
818 console_lock(); /* in case the earlycon is on the UART */
819
820 /*
821 * Because of early UART probing, UART did not get idled
822 * on init. Now that omap_device is ready, ensure full idle
823 * before doing omap_device_enable().
824 */
825 omap_hwmod_idle(uart->oh);
826
827 omap_device_enable(uart->pdev);
828 omap_uart_idle_init(uart);
829 omap_uart_reset(uart);
830 omap_hwmod_enable_wakeup(uart->oh);
831 omap_device_idle(uart->pdev);
832
833 /*
834 * Need to block sleep long enough for interrupt driven
835 * driver to start. Console driver is in polling mode
836 * so device needs to be kept enabled while polling driver
837 * is in use.
838 */
839 if (uart->timeout)
840 uart->timeout = (30 * HZ);
841 omap_uart_block_sleep(uart);
842 uart->timeout = DEFAULT_TIMEOUT;
843
844 console_unlock();
845
846 if ((cpu_is_omap34xx() && uart->padconf) ||
847 (uart->wk_en && uart->wk_mask)) {
848 device_init_wakeup(&od->pdev.dev, true);
849 DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
813 } 850 }
814 851
815 /* Enable the MDR1 errata for OMAP3 */ 852 /* Enable the MDR1 errata for OMAP3 */
816 if (cpu_is_omap34xx()) 853 if (cpu_is_omap34xx() && !cpu_is_ti816x())
817 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; 854 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
818} 855}
819 856
820/** 857/**
821 * omap_serial_init() - intialize all supported serial ports 858 * omap_serial_init() - initialize all supported serial ports
822 * 859 *
823 * Initializes all available UARTs as serial ports. Platforms 860 * Initializes all available UARTs as serial ports. Platforms
824 * can call this function when they want to have default behaviour 861 * can call this function when they want to have default behaviour
@@ -826,13 +863,15 @@ void __init omap_serial_init_port(int port)
826 */ 863 */
827void __init omap_serial_init(void) 864void __init omap_serial_init(void)
828{ 865{
829 int i, nr_ports; 866 struct omap_uart_state *uart;
867 struct omap_board_data bdata;
830 868
831 if (!(cpu_is_omap3630() || cpu_is_omap4430())) 869 list_for_each_entry(uart, &uart_list, node) {
832 nr_ports = 3; 870 bdata.id = uart->num;
833 else 871 bdata.flags = 0;
834 nr_ports = ARRAY_SIZE(omap_uart); 872 bdata.pads = NULL;
873 bdata.pads_cnt = 0;
874 omap_serial_init_port(&bdata);
835 875
836 for (i = 0; i < nr_ports; i++) 876 }
837 omap_serial_init_port(i);
838} 877}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 10:14:10 -0400