270 files changed, 10139 insertions, 10616 deletions

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
new file mode 100644
index 000000000000..87a1e8fb6242
--- /dev/null
+++ b/Documentation/arm/sunxi/README
@@ -0,0 +1,19 @@
+ARM Allwinner SoCs
+==================
+
+This document lists all the ARM Allwinner SoCs that are currently
+supported in mainline by the Linux kernel. This document will also
+provide links to documentation and or datasheet for these SoCs.
+
+SunXi family
+------------
+
+  Flavors:
+        Allwinner A10 (sun4i)
+                Datasheet       : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
+
+        Allwinner A13 (sun5i)
+                Datasheet       : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
+
+  Core: Cortex A8
+  Linux kernel mach directory: arch/arm/mach-sunxi
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
new file mode 100644
index 000000000000..fb7b5cd2652f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
@@ -0,0 +1,9 @@
+Broadcom BCM11351 device tree bindings
+-------------------------------------------
+
+Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
+bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
+
+Required root node property:
+
+compatible = "bcm,bcm11351";
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
index 4755caaccba6..25fcf96795ca 100644
--- a/Documentation/devicetree/bindings/arm/calxeda.txt
+++ b/Documentation/devicetree/bindings/arm/calxeda.txt
@@ -1,8 +1,15 @@
-Calxeda Highbank Platforms Device Tree Bindings
+Calxeda Platforms Device Tree Bindings
 -----------------------------------------------
 
-Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
-properties.
+Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
+following properties.
 
 Required root node properties:
     - compatible = "calxeda,highbank";
+
+
+Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,ecx-2000";
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
new file mode 100644
index 000000000000..9cf3f25544c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
@@ -0,0 +1,50 @@
+ARM Versatile Express system registers
+--------------------------------------
+
+This is a system control registers block, providing multiple low level
+platform functions like board detection and identification, software
+interrupt generation, MMC and NOR Flash control etc.
+
+Required node properties:
+- compatible value : = "arm,vexpress,sysreg";
+- reg : physical base address and the size of the registers window
+- gpio-controller : specifies that the node is a GPIO controller
+- #gpio-cells : size of the GPIO specifier, should be 2:
+  - first cell is the pseudo-GPIO line number:
+    0 - MMC CARDIN
+    1 - MMC WPROT
+    2 - NOR FLASH WPn
+  - second cell can take standard GPIO flags (currently ignored).
+
+Example:
+        v2m_sysreg: sysreg@10000000 {
+                compatible = "arm,vexpress-sysreg";
+                reg = <0x10000000 0x1000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+This block also can also act a bridge to the platform's configuration
+bus via "system control" interface, addressing devices with site number,
+position in the board stack, config controller, function and device
+numbers - see motherboard's TRM for more details.
+
+The node describing a config device must refer to the sysreg node via
+"arm,vexpress,config-bridge" phandle (can be also defined in the node's
+parent) and relies on the board topology properties - see main vexpress
+node documentation for more details. It must must also define the
+following property:
+- arm,vexpress-sysreg,func : must contain two cells:
+  - first cell defines function number (eg. 1 for clock generator,
+    2 for voltage regulators etc.)
+  - device number (eg. osc 0, osc 1 etc.)
+
+Example:
+        mcc {
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
index ec8b50cbb2e8..ae49161e478a 100644
--- a/Documentation/devicetree/bindings/arm/vexpress.txt
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -11,6 +11,10 @@ the motherboard file using a /include/ directive. As the motherboard
 can be initialized in one of two different configurations ("memory
 maps"), care must be taken to include the correct one.
 
+
+Root node
+---------
+
 Required properties in the root node:
 - compatible value:
         compatible = "arm,vexpress,<model>", "arm,vexpress";
@@ -45,6 +49,10 @@ Optional properties in the root node:
   - Coretile Express A9x4 (V2P-CA9) HBI-0225:
         arm,hbi = <0x225>;
 
+
+CPU nodes
+---------
+
 Top-level standard "cpus" node is required. It must contain a node
 with device_type = "cpu" property for every available core, eg.:
 
@@ -59,6 +67,52 @@ with device_type = "cpu" property for every available core, eg.:
                 };
         };
 
+
+Configuration infrastructure
+----------------------------
+
+The platform has an elaborated configuration system, consisting of
+microcontrollers residing on the mother- and daughterboards known
+as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
+The controllers are responsible for the platform initialization
+(reset generation, flash programming, FPGA bitfiles loading etc.)
+but also control clock generators, voltage regulators, gather
+environmental data like temperature, power consumption etc. Even
+the video output switch (FPGA) is controlled that way.
+
+Nodes describing devices controlled by this infrastructure should
+point at the bridge device node:
+- bridge phandle:
+        arm,vexpress,config-bridge = <phandle>;
+This property can be also defined in a parent node (eg. for a DCC)
+and is effective for all children.
+
+
+Platform topology
+-----------------
+
+As Versatile Express can be configured in number of physically
+different setups, the device tree should describe platform topology.
+Root node and main motherboard node must define the following
+property, describing physical location of the children nodes:
+- site number:
+        arm,vexpress,site = <number>;
+  where 0 means motherboard, 1 or 2 are daugtherboard sites,
+  0xf means "master" site (site containing main CPU tile)
+- when daughterboards are stacked on one site, their position
+  in the stack be be described with:
+        arm,vexpress,position = <number>;
+- when describing tiles consisting more than one DCC, its number
+  can be described with:
+        arm,vexpress,dcc = <number>;
+
+Any of the numbers above defaults to zero if not defined in
+the node or any of its parent.
+
+
+Motherboard
+-----------
+
 The motherboard description file provides a single "motherboard" node
 using 2 address cells corresponding to the Static Memory Bus used
 between the motherboard and the tile. The first cell defines the Chip
@@ -87,22 +141,30 @@ can be used to obtain required phandle in the tile's "aliases" node:
 - SP804 timers:
         v2m_timer01 and v2m_timer23
 
-Current Linux implementation requires a "arm,v2m_timer" alias
-pointing at one of the motherboard's SP804 timers, if it is to be
-used as the system timer. This alias should be defined in the
-motherboard files.
+The tile description should define a "smb" node, describing the
+Static Memory Bus between the tile and motherboard. It must define
+the following properties:
+- "simple-bus" compatible value (to ensure creation of the children)
+        compatible = "simple-bus";
+- mapping of the SMB CS/offset addresses into main address space:
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <...>;
+- interrupts mapping:
+        #interrupt-cells = <1>;
+        interrupt-map-mask = <0 0 63>;
+        interrupt-map = <...>;
 
-The tile description must define "ranges", "interrupt-map-mask" and
-"interrupt-map" properties to translate the motherboard's address
-and interrupt space into one used by the tile's processor.
 
-Abbreviated example:
+Example of a VE tile description (simplified)
+---------------------------------------------
 
 /dts-v1/;
 
 / {
         model = "V2P-CA5s";
         arm,hbi = <0x225>;
+        arm,vexpress,site = <0xf>;
         compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
         interrupt-parent = <&gic>;
         #address-cells = <1>;
@@ -134,13 +196,29 @@ Abbreviated example:
                       <0x2c000100 0x100>;
         };
 
-        motherboard {
+        dcc {
+                compatible = "simple-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        compatible = "arm,vexpress-osc";
+                };
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
                 /* CS0 is visible at 0x08000000 */
                 ranges = <0 0 0x08000000 0x04000000>;
+
+                #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 63>;
                 /* Active high IRQ 0 is connected to GIC's SPI0 */
                 interrupt-map = <0 0 0 &gic 0 0 4>;
+
+                /include/ "vexpress-v2m-rs1.dtsi"
         };
 };
 
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
new file mode 100644
index 000000000000..04ad47876be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
+* Clock bindings for Freescale i.MX5
+
+Required properties:
+- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX5
+clocks and IDs.
+
+        Clock                   ID
+        ---------------------------
+        dummy                   0
+        ckil                    1
+        osc                     2
+        ckih1                   3
+        ckih2                   4
+        ahb                     5
+        ipg                     6
+        axi_a                   7
+        axi_b                   8
+        uart_pred               9
+        uart_root               10
+        esdhc_a_pred            11
+        esdhc_b_pred            12
+        esdhc_c_s               13
+        esdhc_d_s               14
+        emi_sel                 15
+        emi_slow_podf           16
+        nfc_podf                17
+        ecspi_pred              18
+        ecspi_podf              19
+        usboh3_pred             20
+        usboh3_podf             21
+        usb_phy_pred            22
+        usb_phy_podf            23
+        cpu_podf                24
+        di_pred                 25
+        tve_di                  26
+        tve_s                   27
+        uart1_ipg_gate          28
+        uart1_per_gate          29
+        uart2_ipg_gate          30
+        uart2_per_gate          31
+        uart3_ipg_gate          32
+        uart3_per_gate          33
+        i2c1_gate               34
+        i2c2_gate               35
+        gpt_ipg_gate            36
+        pwm1_ipg_gate           37
+        pwm1_hf_gate            38
+        pwm2_ipg_gate           39
+        pwm2_hf_gate            40
+        gpt_hf_gate             41
+        fec_gate                42
+        usboh3_per_gate         43
+        esdhc1_ipg_gate         44
+        esdhc2_ipg_gate         45
+        esdhc3_ipg_gate         46
+        esdhc4_ipg_gate         47
+        ssi1_ipg_gate           48
+        ssi2_ipg_gate           49
+        ssi3_ipg_gate           50
+        ecspi1_ipg_gate         51
+        ecspi1_per_gate         52
+        ecspi2_ipg_gate         53
+        ecspi2_per_gate         54
+        cspi_ipg_gate           55
+        sdma_gate               56
+        emi_slow_gate           57
+        ipu_s                   58
+        ipu_gate                59
+        nfc_gate                60
+        ipu_di1_gate            61
+        vpu_s                   62
+        vpu_gate                63
+        vpu_reference_gate      64
+        uart4_ipg_gate          65
+        uart4_per_gate          66
+        uart5_ipg_gate          67
+        uart5_per_gate          68
+        tve_gate                69
+        tve_pred                70
+        esdhc1_per_gate         71
+        esdhc2_per_gate         72
+        esdhc3_per_gate         73
+        esdhc4_per_gate         74
+        usb_phy_gate            75
+        hsi2c_gate              76
+        mipi_hsc1_gate          77
+        mipi_hsc2_gate          78
+        mipi_esc_gate           79
+        mipi_hsp_gate           80
+        ldb_di1_div_3_5         81
+        ldb_di1_div             82
+        ldb_di0_div_3_5         83
+        ldb_di0_div             84
+        ldb_di1_gate            85
+        can2_serial_gate        86
+        can2_ipg_gate           87
+        i2c3_gate               88
+        lp_apm                  89
+        periph_apm              90
+        main_bus                91
+        ahb_max                 92
+        aips_tz1                93
+        aips_tz2                94
+        tmax1                   95
+        tmax2                   96
+        tmax3                   97
+        spba                    98
+        uart_sel                99
+        esdhc_a_sel             100
+        esdhc_b_sel             101
+        esdhc_a_podf            102
+        esdhc_b_podf            103
+        ecspi_sel               104
+        usboh3_sel              105
+        usb_phy_sel             106
+        iim_gate                107
+        usboh3_gate             108
+        emi_fast_gate           109
+        ipu_di0_gate            110
+        gpc_dvfs                111
+        pll1_sw                 112
+        pll2_sw                 113
+        pll3_sw                 114
+        ipu_di0_sel             115
+        ipu_di1_sel             116
+        tve_ext_sel             117
+        mx51_mipi               118
+        pll4_sw                 119
+        ldb_di1_sel             120
+        di_pll4_podf            121
+        ldb_di0_sel             122
+        ldb_di0_gate            123
+        usb_phy1_gate           124
+        usb_phy2_gate           125
+        per_lp_apm              126
+        per_pred1               127
+        per_pred2               128
+        per_podf                129
+        per_root                130
+        ssi_apm                 131
+        ssi1_root_sel           132
+        ssi2_root_sel           133
+        ssi3_root_sel           134
+        ssi_ext1_sel            135
+        ssi_ext2_sel            136
+        ssi_ext1_com_sel        137
+        ssi_ext2_com_sel        138
+        ssi1_root_pred          139
+        ssi1_root_podf          140
+        ssi2_root_pred          141
+        ssi2_root_podf          142
+        ssi_ext1_pred           143
+        ssi_ext1_podf           144
+        ssi_ext2_pred           145
+        ssi_ext2_podf           146
+        ssi1_root_gate          147
+        ssi2_root_gate          148
+        ssi3_root_gate          149
+        ssi_ext1_gate           150
+        ssi_ext2_gate           151
+        epit1_ipg_gate          152
+        epit1_hf_gate           153
+        epit2_ipg_gate          154
+        epit2_hf_gate           155
+        can_sel                 156
+        can1_serial_gate        157
+        can1_ipg_gate           158
+
+Examples (for mx53):
+
+clks: ccm@53fd4000{
+        compatible = "fsl,imx53-ccm";
+        reg = <0x53fd4000 0x4000>;
+        interrupts = <0 71 0x04 0 72 0x04>;
+        #clock-cells = <1>;
+};
+
+can1: can@53fc8000 {
+        compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+        reg = <0x53fc8000 0x4000>;
+        interrupts = <82>;
+        clocks = <&clks 158>, <&clks 157>;
+        clock-names = "ipg", "per";
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 492bd991d52a..d77b4e68dc42 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -187,9 +187,9 @@ clocks and IDs.
         pll3_usb_otg            172
         pll4_audio              173
         pll5_video              174
-        pll6_mlb                175
+        pll8_mlb                175
         pll7_usb_host           176
-        pll8_enet               177
+        pll6_enet               177
         ssi1_ipg                178
         ssi2_ipg                179
         ssi3_ipg                180
@@ -198,6 +198,11 @@ clocks and IDs.
         usbphy2                 183
         ldb_di0_div_3_5         184
         ldb_di1_div_3_5         185
+        sata_ref                186
+        sata_ref_100m           187
+        pcie_ref                188
+        pcie_ref_125m           189
+        enet_ref                190
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
new file mode 100644
index 000000000000..7f9fb85f5456
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
@@ -0,0 +1,104 @@
+Allwinner Sunxi Interrupt Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-ic"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+The interrupt sources are as follows:
+
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: SDMC0
+33: SDMC1
+34: SDMC2
+35: SDMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
+
+Example:
+
+intc: interrupt-controller {
+        compatible = "allwinner,sunxi-ic";
+        reg = <0x01c20400 0x400>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 03dee50532f5..e97a27856b21 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -8,13 +8,20 @@ on-chip controllers onto these pads.
 Required Properties:
 - compatible: should be one of the following.
   - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
+  - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
   - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
 
 - reg: Base address of the pin controller hardware module and length of
   the address space it occupies.
 
-- interrupts: interrupt specifier for the controller. The format and value of
-  the interrupt specifier depends on the interrupt parent for the controller.
+- Pin banks as child nodes: Pin banks of the controller are represented by child
+  nodes of the controller node. Bank name is taken from name of the node. Each
+  bank node must contain following properties:
+
+  - gpio-controller: identifies the node as a gpio controller and pin bank.
+  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
+    binding is used, the amount of cells must be specified as 2. See generic
+    GPIO binding documentation for description of particular cells.
 
 - Pin mux/config groups as child nodes: The pin mux (selecting pin function
   mode) and pin config (pull up/down, driver strength) settings are represented
@@ -72,16 +79,24 @@ used as system wakeup events.
 A. External GPIO Interrupts: For supporting external gpio interrupts, the
    following properties should be specified in the pin-controller device node.
 
-- interrupt-controller: identifies the controller node as interrupt-parent.
-- #interrupt-cells: the value of this property should be 2.
-  - First Cell: represents the external gpio interrupt number local to the
-    external gpio interrupt space of the controller.
-  - Second Cell: flags to identify the type of the interrupt
-    - 1 = rising edge triggered
-    - 2 = falling edge triggered
-    - 3 = rising and falling edge triggered
-    - 4 = high level triggered
-    - 8 = low level triggered
+   - interrupt-parent: phandle of the interrupt parent to which the external
+     GPIO interrupts are forwarded to.
+   - interrupts: interrupt specifier for the controller. The format and value of
+     the interrupt specifier depends on the interrupt parent for the controller.
+
+   In addition, following properties must be present in node of every bank
+   of pins supporting GPIO interrupts:
+
+   - interrupt-controller: identifies the controller node as interrupt-parent.
+   - #interrupt-cells: the value of this property should be 2.
+     - First Cell: represents the external gpio interrupt number local to the
+       external gpio interrupt space of the controller.
+     - Second Cell: flags to identify the type of the interrupt
+       - 1 = rising edge triggered
+       - 2 = falling edge triggered
+       - 3 = rising and falling edge triggered
+       - 4 = high level triggered
+       - 8 = low level triggered
 
 B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
    child node representing the external wakeup interrupt controller should be
@@ -94,6 +109,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
        found on Samsung Exynos4210 SoC.
    - interrupt-parent: phandle of the interrupt parent to which the external
      wakeup interrupts are forwarded to.
+   - interrupts: interrupt used by multiplexed wakeup interrupts.
+
+   In addition, following properties must be present in node of every bank
+   of pins supporting wake-up interrupts:
+
    - interrupt-controller: identifies the node as interrupt-parent.
    - #interrupt-cells: the value of this property should be 2
      - First Cell: represents the external wakeup interrupt number local to
@@ -105,11 +125,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
        - 4 = high level triggered
        - 8 = low level triggered
 
+   Node of every bank of pins supporting direct wake-up interrupts (without
+   multiplexing) must contain following properties:
+
+   - interrupt-parent: phandle of the interrupt parent to which the external
+     wakeup interrupts are forwarded to.
+   - interrupts: interrupts of the interrupt parent which are used for external
+     wakeup interrupts from pins of the bank, must contain interrupts for all
+     pins of the bank.
+
 Aliases:
 
 All the pin controller nodes should be represented in the aliases node using
 the following format 'pinctrl{n}' where n is a unique number for the alias.
 
+Example: A pin-controller node with pin banks:
+
+        pinctrl_0: pinctrl@11400000 {
+                compatible = "samsung,pinctrl-exynos4210";
+                reg = <0x11400000 0x1000>;
+                interrupts = <0 47 0>;
+
+                /* ... */
+
+                /* Pin bank without external interrupts */
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                /* ... */
+
+                /* Pin bank with external GPIO or muxed wake-up interrupts */
+                gpj0: gpj0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                /* ... */
+
+                /* Pin bank with external direct wake-up interrupts */
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                        #interrupt-cells = <2>;
+                };
+
+                /* ... */
+        };
+
 Example 1: A pin-controller node with pin groups.
 
         pinctrl_0: pinctrl@11400000 {
@@ -117,6 +189,8 @@ Example 1: A pin-controller node with pin groups.
                 reg = <0x11400000 0x1000>;
                 interrupts = <0 47 0>;
 
+                /* ... */
+
                 uart0_data: uart0-data {
                         samsung,pins = "gpa0-0", "gpa0-1";
                         samsung,pin-function = <2>;
@@ -158,20 +232,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node.
         pinctrl_1: pinctrl@11000000 {
                 compatible = "samsung,pinctrl-exynos4210";
                 reg = <0x11000000 0x1000>;
-                interrupts = <0 46 0>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
+                interrupts = <0 46 0>
 
-                wakup_eint: wakeup-interrupt-controller {
+                /* ... */
+
+                wakeup-interrupt-controller {
                         compatible = "samsung,exynos4210-wakeup-eint";
                         interrupt-parent = <&gic>;
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                        <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                                        <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                                        <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
-                                        <0 32 0>;
+                        interrupts = <0 32 0>;
                 };
         };
 
@@ -190,7 +258,8 @@ Example 4: Set up the default pin state for uart controller.
 
         static int s3c24xx_serial_probe(struct platform_device *pdev) {
                 struct pinctrl *pinctrl;
-                ...
-                ...
+
+                /* ... */
+
                 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
         }
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
new file mode 100644
index 000000000000..0c7b64e95a61
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
@@ -0,0 +1,17 @@
+Allwinner A1X SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
+
+Example:
+
+timer {
+        compatible = "allwinner,sunxi-timer";
+        reg = <0x01c20c00 0x400>;
+        interrupts = <22>;
+        clocks = <&osc>;
+};
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
new file mode 100644
index 000000000000..d209366b4a69
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
@@ -0,0 +1,13 @@
+BCM2835 Watchdog timer
+
+Required properties:
+
+- compatible : should be "brcm,bcm2835-pm-wdt"
+- reg : Specifies base physical address and size of the registers.
+
+Example:
+
+watchdog {
+        compatible = "brcm,bcm2835-pm-wdt";
+        reg = <0x7e100000 0x28>;
+};
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
new file mode 100644
index 000000000000..0b2717775600
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -0,0 +1,13 @@
+Allwinner sunXi Watchdog timer
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-wdt"
+- reg : Specifies base physical address and size of the registers.
+
+Example:
+
+wdt: watchdog@01c20c90 {
+        compatible = "allwinner,sunxi-wdt";
+        reg = <0x01c20c90 0x10>;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index e624aa2fc3da..386fce6715c4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -685,6 +685,12 @@ M:	Lennert Buytenhek <kernel@wantstofly.org>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 
+ARM/Allwinner A1X SoC support
+M:      Maxime Ripard <maxime.ripard@free-electrons.com>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:      Maintained
+F:      arch/arm/mach-sunxi/
+
 ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
 M:      Andrew Victor <linux@maxim.org.za>
 M:      Nicolas Ferre <nicolas.ferre@atmel.com>
@@ -707,6 +713,12 @@ S:	Maintained
 F:      arch/arm/mach-cns3xxx/
 T:      git git://git.infradead.org/users/cbou/linux-cns3xxx.git
 
+ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE
+M:      Alexander Shiyan <shc_work@mail.ru>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:      Odd Fixes
+F:      arch/arm/mach-clps711x/
+
 ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
 M:      Hartley Sweeten <hsweeten@visionengravers.com>
 M:      Ryan Mallon <rmallon@gmail.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 03e0460d5067..29b85e6bd71d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -286,8 +286,8 @@ config ARCH_INTEGRATOR
         select MULTI_IRQ_HANDLER
         select NEED_MACH_MEMORY_H
         select PLAT_VERSATILE
-        select PLAT_VERSATILE_FPGA_IRQ
         select SPARSE_IRQ
+        select VERSATILE_FPGA_IRQ
         help
           Support for ARM's Integrator platform.
 
@@ -320,7 +320,7 @@ config ARCH_VERSATILE
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLCD
         select PLAT_VERSATILE_CLOCK
-        select PLAT_VERSATILE_FPGA_IRQ
+        select VERSATILE_FPGA_IRQ
         help
           This enables support for ARM Ltd Versatile board.
 
@@ -340,7 +340,7 @@ config ARCH_AT91
 
 config ARCH_BCM2835
         bool "Broadcom BCM2835 family"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
         select ARM_ERRATA_411920
         select ARM_TIMER_SP804
@@ -348,7 +348,10 @@ config ARCH_BCM2835
         select COMMON_CLK
         select CPU_V6
         select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
         select MULTI_IRQ_HANDLER
+        select PINCTRL
+        select PINCTRL_BCM2835
         select SPARSE_IRQ
         select USE_OF
         help
@@ -370,10 +373,14 @@ config ARCH_CLPS711X
         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_USES_GETTIMEOFFSET
+        select AUTO_ZRELADDR
         select CLKDEV_LOOKUP
         select COMMON_CLK
         select CPU_ARM720T
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_MEMORY_H
+        select SPARSE_IRQ
         help
           Support for Cirrus Logic 711x/721x/731x based boards.
 
@@ -1015,6 +1022,8 @@ source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
+source "arch/arm/mach-bcm/Kconfig"
+
 source "arch/arm/mach-clps711x/Kconfig"
 
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -1106,6 +1115,8 @@ source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
+source "arch/arm/mach-sunxi/Kconfig"
+
 source "arch/arm/mach-prima2/Kconfig"
 
 source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5566520686a5..04a3f0d1d053 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -338,6 +338,17 @@ choice
                   The uncompressor code port configuration is now handled
                   by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+        config DEBUG_S3C_UART3
+                depends on PLAT_SAMSUNG && ARCH_EXYNOS
+                bool "Use S3C UART 3 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 3. The port must have been initialised
+                  by the boot-loader before use.
+
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
         config DEBUG_SOCFPGA_UART
                 depends on ARCH_SOCFPGA
                 bool "Use SOCFPGA UART for low-level debug"
@@ -345,6 +356,20 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on SOCFPGA based platforms.
 
+        config DEBUG_SUNXI_UART0
+                bool "Kernel low-level debugging messages via sunXi UART0"
+                depends on ARCH_SUNXI
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Allwinner A1X based platforms on the UART0.
+
+        config DEBUG_SUNXI_UART1
+                bool "Kernel low-level debugging messages via sunXi UART1"
+                depends on ARCH_SUNXI
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Allwinner A1X based platforms on the UART1.
+
         config DEBUG_VEXPRESS_UART0_DETECT
                 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                 depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -424,6 +449,7 @@ config DEBUG_LL_INCLUDE
         default "debug/mvebu.S" if DEBUG_MVEBU_UART
         default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
         default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+        default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
                 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
         default "mach/debug-macro.S"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 20d295aca51f..9c60f474a559 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -138,6 +138,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)             += at91
+machine-$(CONFIG_ARCH_BCM)              += bcm
 machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
 machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
@@ -194,6 +195,7 @@ machine-$(CONFIG_ARCH_SPEAR13XX)	+= spear13xx
 machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
 machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
+machine-$(CONFIG_ARCH_SUNXI)            += sunxi
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 537208f22e56..5cad8a6dadb0 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -45,11 +45,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS            += head-shark.o ofw-shark.o
 endif
 
-ifeq ($(CONFIG_ARCH_P720T),y)
-# Borrow this code from SA1100
-OBJS            += head-sa1100.o
-endif
-
 ifeq ($(CONFIG_ARCH_SA1100),y)
 OBJS            += head-sa1100.o
 endif
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5e98094a3e1b..42917866fcde 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -33,14 +33,17 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
 
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
         dove-cubox.dtb \
         dove-dove-db.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
-        exynos5250-smdk5250.dtb
-dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+        exynos5250-smdk5250.dtb \
+        exynos5440-ssdk5440.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
+        ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
@@ -102,6 +105,8 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
         spear310-evb.dtb \
         spear320-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
+        sun5i-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra20-medcom-wide.dtb \
         tegra20-paz00.dtb \
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
new file mode 100644
index 000000000000..248067cf7069
--- /dev/null
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/include/ "bcm11351.dtsi"
+
+/ {
+        model = "BCM11351 BRT board";
+        compatible = "bcm,bcm11351-brt", "bcm,bcm11351";
+
+        memory {
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+
+        uart@3e000000 {
+                status = "okay";
+        };
+
+};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
new file mode 100644
index 000000000000..ad135885bd2a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "BCM11351 SoC";
+        compatible = "bcm,bcm11351";
+        interrupt-parent = <&gic>;
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+
+        gic: interrupt-controller@3ff00100 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x3ff01000 0x1000>,
+                      <0x3ff00100 0x100>;
+        };
+
+        uart@3e000000 {
+                compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
+                status = "disabled";
+                reg = <0x3e000000 0x1000>;
+                clock-frequency = <13000000>;
+                interrupts = <0x0 67 0x4>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+
+        L2: l2-cache {
+                    compatible = "arm,pl310-cache";
+                    reg = <0x3ff20000 0x1000>;
+                    cache-unified;
+                    cache-level = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 7dd860f83f96..9b72054a0bc0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -10,3 +10,18 @@
                 reg = <0 0x10000000>;
         };
 };
+
+&gpio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&alt0 &alt3>;
+
+        alt0: alt0 {
+                brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
+                brcm,function = <4>; /* alt0 */
+        };
+
+        alt3: alt3 {
+                brcm,pins = <48 49 50 51 52 53>;
+                brcm,function = <7>; /* alt3 */
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 0b619398532c..8917550fd1bb 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -29,11 +29,39 @@
                         #interrupt-cells = <2>;
                 };
 
+                watchdog {
+                        compatible = "brcm,bcm2835-pm-wdt";
+                        reg = <0x7e100000 0x28>;
+                };
+
                 uart@20201000 {
                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
                         reg = <0x7e201000 0x1000>;
                         interrupts = <2 25>;
                         clock-frequency = <3000000>;
                 };
+
+                gpio: gpio {
+                        compatible = "brcm,bcm2835-gpio";
+                        reg = <0x7e200000 0xb4>;
+                        /*
+                         * The GPIO IP block is designed for 3 banks of GPIOs.
+                         * Each bank has a GPIO interrupt for itself.
+                         * There is an overall "any bank" interrupt.
+                         * In order, these are GIC interrupts 17, 18, 19, 20.
+                         * Since the BCM2835 only has 2 banks, the 2nd bank
+                         * interrupt output appears to be mirrored onto the
+                         * 3rd bank's interrupt signal.
+                         * So, a bank0 interrupt shows up on 17, 20, and
+                         * a bank1 interrupt shows up on 18, 19, 20!
+                         */
+                        interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
new file mode 100644
index 000000000000..46477ac1de99
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+
+/ {
+        model = "Calxeda ECX-2000";
+        compatible = "calxeda,ecx-2000";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        clock-ranges;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        reg = <2>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        reg = <3>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+        };
+
+        memory@0 {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
+        };
+
+        memory@200000000 {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
+        };
+
+        soc {
+                ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
+
+                timer {
+                        compatible = "arm,cortex-a15-timer", "arm,armv7-timer";                         interrupts = <1 13 0xf08>,
+                                <1 14 0xf08>,
+                                <1 11 0xf08>,
+                                <1 10 0xf08>;
+                };
+
+                intc: interrupt-controller@fff11000 {
+                        compatible = "arm,cortex-a15-gic";
+                        #interrupt-cells = <3>;
+                        #size-cells = <0>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        interrupts = <1 9 0xf04>;
+                        reg = <0xfff11000 0x1000>,
+                              <0xfff12000 0x1000>,
+                              <0xfff14000 0x2000>,
+                              <0xfff16000 0x2000>;
+                };
+
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
+                };
+        };
+};
+
+/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
new file mode 100644
index 000000000000..d61b535f682a
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/ {
+        chosen {
+                bootargs = "console=ttyAMA0";
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+
+                sata@ffe08000 {
+                        compatible = "calxeda,hb-ahci";
+                        reg = <0xffe08000 0x10000>;
+                        interrupts = <0 83 4>;
+                        dma-coherent;
+                        calxeda,port-phys = <&combophy5 0 &combophy0 0
+                                             &combophy0 1 &combophy0 2
+                                             &combophy0 3>;
+                };
+
+                sdhci@ffe0e000 {
+                        compatible = "calxeda,hb-sdhci";
+                        reg = <0xffe0e000 0x1000>;
+                        interrupts = <0 90 4>;
+                        clocks = <&eclk>;
+                        status = "disabled";
+                };
+
+                memory-controller@fff00000 {
+                        compatible = "calxeda,hb-ddr-ctrl";
+                        reg = <0xfff00000 0x1000>;
+                        interrupts = <0 91 4>;
+                };
+
+                ipc@fff20000 {
+                        compatible = "arm,pl320", "arm,primecell";
+                        reg = <0xfff20000 0x1000>;
+                        interrupts = <0 7 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpioe: gpio@fff30000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff30000 0x1000>;
+                        interrupts = <0 14 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                gpiof: gpio@fff31000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff31000 0x1000>;
+                        interrupts = <0 15 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                gpiog: gpio@fff32000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff32000 0x1000>;
+                        interrupts = <0 16 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                gpioh: gpio@fff33000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff33000 0x1000>;
+                        interrupts = <0 17 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                timer@fff34000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0xfff34000 0x1000>;
+                        interrupts = <0 18 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                rtc@fff35000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0xfff35000 0x1000>;
+                        interrupts = <0 19 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                serial@fff36000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xfff36000 0x1000>;
+                        interrupts = <0 20 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                smic@fff3a000 {
+                        compatible = "ipmi-smic";
+                        device_type = "ipmi";
+                        reg = <0xfff3a000 0x1000>;
+                        interrupts = <0 24 4>;
+                        reg-size = <4>;
+                        reg-spacing = <4>;
+                };
+
+                sregs@fff3c000 {
+                        compatible = "calxeda,hb-sregs";
+                        reg = <0xfff3c000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                osc: oscillator {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <33333000>;
+                                };
+
+                                ddrpll: ddrpll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x108>;
+                                };
+
+                                a9pll: a9pll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x100>;
+                                };
+
+                                a9periphclk: a9periphclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-a9periph-clock";
+                                        clocks = <&a9pll>;
+                                        reg = <0x104>;
+                                };
+
+                                a9bclk: a9bclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-a9bus-clock";
+                                        clocks = <&a9pll>;
+                                        reg = <0x104>;
+                                };
+
+                                emmcpll: emmcpll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x10C>;
+                                };
+
+                                eclk: eclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-emmc-clock";
+                                        clocks = <&emmcpll>;
+                                        reg = <0x114>;
+                                };
+
+                                pclk: pclk {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <150000000>;
+                                };
+                        };
+                };
+
+                dma@fff3d000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xfff3d000 0x1000>;
+                        interrupts = <0 92 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                ethernet@fff50000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff50000 0x1000>;
+                        interrupts = <0 77 4  0 78 4  0 79 4>;
+                        dma-coherent;
+                };
+
+                ethernet@fff51000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff51000 0x1000>;
+                        interrupts = <0 80 4  0 81 4  0 82 4>;
+                        dma-coherent;
+                };
+
+                combophy0: combo-phy@fff58000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff58000 0x1000>;
+                        phydev = <5>;
+                };
+
+                combophy5: combo-phy@fff5d000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff5d000 0x1000>;
+                        phydev = <31>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a26c3dd58269..96d4462730fb 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -244,5 +244,11 @@
                         reg = <0x12690000 0x1000>;
                         interrupts = <0 36 0>;
                 };
+
+                mdma1: mdma@12850000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12850000 0x1000>;
+                        interrupts = <0 34 0>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index b12cf272ad0d..6a4a1a04221c 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -16,6 +16,134 @@
 
 / {
         pinctrl@11400000 {
+                gpa0: gpa0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpa1: gpa1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb: gpb {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc0: gpc0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc1: gpc1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpd0: gpd0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpd1: gpd1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe0: gpe0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe1: gpe1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe2: gpe2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe3: gpe3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe4: gpe4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf0: gpf0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf1: gpf1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf2: gpf2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf3: gpf3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
                 uart0_data: uart0-data {
                         samsung,pins = "gpa0-0", "gpa0-1";
                         samsung,pin-function = <0x2>;
@@ -205,6 +333,151 @@
         };
 
         pinctrl@11000000 {
+                gpj0: gpj0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpj1: gpj1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpk0: gpk0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpk1: gpk1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpk2: gpk2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpk3: gpk3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpl0: gpl0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpl1: gpl1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpl2: gpl2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy1: gpy1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy2: gpy2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy3: gpy3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy4: gpy4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy5: gpy5 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy6: gpy6 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx1: gpx1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx2: gpx2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx3: gpx3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
                 sd0_clk: sd0-clk {
                         samsung,pins = "gpk0-0";
                         samsung,pin-function = <2>;
@@ -438,6 +711,11 @@
         };
 
         pinctrl@03860000 {
+                gpz: gpz {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
                 i2s0_bus: i2s0-bus {
                         samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
                                         "gpz-4", "gpz-5", "gpz-6";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 214c557eda7f..d877dbe7ac0e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -46,27 +46,17 @@
                 compatible = "samsung,pinctrl-exynos4210";
                 reg = <0x11400000 0x1000>;
                 interrupts = <0 47 0>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
         };
 
         pinctrl_1: pinctrl@11000000 {
                 compatible = "samsung,pinctrl-exynos4210";
                 reg = <0x11000000 0x1000>;
                 interrupts = <0 46 0>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
 
                 wakup_eint: wakeup-interrupt-controller {
                         compatible = "samsung,exynos4210-wakeup-eint";
                         interrupt-parent = <&gic>;
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                                     <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
-                                     <0 32 0>;
+                        interrupts = <0 32 0>;
                 };
         };
 
@@ -74,233 +64,4 @@
                 compatible = "samsung,pinctrl-exynos4210";
                 reg = <0x03860000 0x1000>;
         };
-
-        gpio-controllers {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                gpio-controller;
-                ranges;
-
-                gpa0: gpio-controller@11400000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400000 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpa1: gpio-controller@11400020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400020 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpb: gpio-controller@11400040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400040 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc0: gpio-controller@11400060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400060 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc1: gpio-controller@11400080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400080 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpd0: gpio-controller@114000A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpd1: gpio-controller@114000C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe0: gpio-controller@114000E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe1: gpio-controller@11400100 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400100 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe2: gpio-controller@11400120 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400120 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe3: gpio-controller@11400140 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400140 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe4: gpio-controller@11400160 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400160 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpf0: gpio-controller@11400180 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400180 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpf1: gpio-controller@114001A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpf2: gpio-controller@114001C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpf3: gpio-controller@114001E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpj0: gpio-controller@11000000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000000 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpj1: gpio-controller@11000020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000020 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpk0: gpio-controller@11000040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000040 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpk1: gpio-controller@11000060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000060 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpk2: gpio-controller@11000080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000080 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpk3: gpio-controller@110000A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110000A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpl0: gpio-controller@110000C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110000C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpl1: gpio-controller@110000E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110000E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpl2: gpio-controller@11000100 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000100 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy0: gpio-controller@11000120 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000120 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy1: gpio-controller@11000140 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000140 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy2: gpio-controller@11000160 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000160 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy3: gpio-controller@11000180 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000180 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy4: gpio-controller@110001A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110001A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy5: gpio-controller@110001C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110001C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy6: gpio-controller@110001E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110001E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx0: gpio-controller@11000C00 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C00 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx1: gpio-controller@11000C20 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C20 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx2: gpio-controller@11000C40 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C40 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx3: gpio-controller@11000C60 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C60 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpz: gpio-controller@03860000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x03860000 0x20>;
-                        #gpio-cells = <4>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
new file mode 100644
index 000000000000..921c83cf694f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -0,0 +1,46 @@
+/*
+ * SAMSUNG SSDK5440 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5440.dtsi"
+
+/ {
+        model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
+        compatible = "samsung,ssdk5440", "samsung,exynos5440";
+
+        memory {
+                reg = <0x80000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
+        };
+
+        spi {
+                status = "disabled";
+        };
+
+        i2c@F0000 {
+                status = "disabled";
+        };
+
+        i2c@100000 {
+                status = "disabled";
+        };
+
+        watchdog {
+                status = "disabled";
+        };
+
+        rtc {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
new file mode 100644
index 000000000000..024269de8ee5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -0,0 +1,159 @@
+/*
+ * SAMSUNG EXYNOS5440 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "samsung,exynos5440";
+
+        interrupt-parent = <&gic>;
+
+        gic:interrupt-controller@2E0000 {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 13 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 14 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 14 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 14 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+        };
+
+        common {
+                compatible = "samsung,exynos5440";
+
+        };
+
+        serial@B0000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0xB0000 0x1000>;
+                interrupts = <0 2 0>;
+        };
+
+        serial@C0000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0xC0000 0x1000>;
+                interrupts = <0 3 0>;
+        };
+
+        spi {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0xD0000 0x1000>;
+                interrupts = <0 4 0>;
+                tx-dma-channel = <&pdma0 5>; /* preliminary */
+                rx-dma-channel = <&pdma0 4>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        pinctrl {
+                compatible = "samsung,pinctrl-exynos5440";
+                reg = <0xE0000 0x1000>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                #gpio-cells = <2>;
+
+                fan: fan {
+                        samsung,exynos5440-pin-function = <1>;
+                };
+
+                hdd_led0: hdd_led0 {
+                        samsung,exynos5440-pin-function = <2>;
+                };
+
+                hdd_led1: hdd_led1 {
+                        samsung,exynos5440-pin-function = <3>;
+                };
+
+                uart1: uart1 {
+                        samsung,exynos5440-pin-function = <4>;
+                };
+        };
+
+        i2c@F0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0xF0000 0x1000>;
+                interrupts = <0 5 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        i2c@100000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x100000 0x1000>;
+                interrupts = <0 6 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        watchdog {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x110000 0x1000>;
+                interrupts = <0 1 0>;
+        };
+
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                pdma0: pdma@121A0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x120000 0x1000>;
+                        interrupts = <0 34 0>;
+                };
+
+                pdma1: pdma@121B0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+        };
+
+        rtc {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x130000 0x1000>;
+                interrupts = <0 16 0>, <0 17 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 0c6fc34821f9..a9ae5d32e80d 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -69,16 +69,8 @@
                 reg = <0x00000000 0xff900000>;
         };
 
-        chosen {
-                bootargs = "console=ttyAMA0";
-        };
-
         soc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
-                ranges;
+                ranges = <0x00000000 0x00000000 0xffffffff>;
 
                 timer@fff10600 {
                         compatible = "arm,cortex-a9-twd-timer";
@@ -117,173 +109,6 @@
                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
                 };
 
-                sata@ffe08000 {
-                        compatible = "calxeda,hb-ahci";
-                        reg = <0xffe08000 0x10000>;
-                        interrupts = <0 83 4>;
-                        calxeda,port-phys = <&combophy5 0 &combophy0 0
-                                             &combophy0 1 &combophy0 2
-                                             &combophy0 3>;
-                        dma-coherent;
-                };
-
-                sdhci@ffe0e000 {
-                        compatible = "calxeda,hb-sdhci";
-                        reg = <0xffe0e000 0x1000>;
-                        interrupts = <0 90 4>;
-                        clocks = <&eclk>;
-                };
-
-                memory-controller@fff00000 {
-                        compatible = "calxeda,hb-ddr-ctrl";
-                        reg = <0xfff00000 0x1000>;
-                        interrupts = <0 91 4>;
-                };
-
-                ipc@fff20000 {
-                        compatible = "arm,pl320", "arm,primecell";
-                        reg = <0xfff20000 0x1000>;
-                        interrupts = <0 7 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                gpioe: gpio@fff30000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff30000 0x1000>;
-                        interrupts = <0 14 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                gpiof: gpio@fff31000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff31000 0x1000>;
-                        interrupts = <0 15 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                gpiog: gpio@fff32000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff32000 0x1000>;
-                        interrupts = <0 16 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                gpioh: gpio@fff33000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff33000 0x1000>;
-                        interrupts = <0 17 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                timer {
-                        compatible = "arm,sp804", "arm,primecell";
-                        reg = <0xfff34000 0x1000>;
-                        interrupts = <0 18 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                rtc@fff35000 {
-                        compatible = "arm,pl031", "arm,primecell";
-                        reg = <0xfff35000 0x1000>;
-                        interrupts = <0 19 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                serial@fff36000 {
-                        compatible = "arm,pl011", "arm,primecell";
-                        reg = <0xfff36000 0x1000>;
-                        interrupts = <0 20 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                smic@fff3a000 {
-                        compatible = "ipmi-smic";
-                        device_type = "ipmi";
-                        reg = <0xfff3a000 0x1000>;
-                        interrupts = <0 24 4>;
-                        reg-size = <4>;
-                        reg-spacing = <4>;
-                };
-
-                sregs@fff3c000 {
-                        compatible = "calxeda,hb-sregs";
-                        reg = <0xfff3c000 0x1000>;
-
-                        clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                osc: oscillator {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        clock-frequency = <33333000>;
-                                };
-
-                                ddrpll: ddrpll {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-pll-clock";
-                                        clocks = <&osc>;
-                                        reg = <0x108>;
-                                };
-
-                                a9pll: a9pll {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-pll-clock";
-                                        clocks = <&osc>;
-                                        reg = <0x100>;
-                                };
-
-                                a9periphclk: a9periphclk {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-a9periph-clock";
-                                        clocks = <&a9pll>;
-                                        reg = <0x104>;
-                                };
-
-                                a9bclk: a9bclk {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-a9bus-clock";
-                                        clocks = <&a9pll>;
-                                        reg = <0x104>;
-                                };
-
-                                emmcpll: emmcpll {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-pll-clock";
-                                        clocks = <&osc>;
-                                        reg = <0x10C>;
-                                };
-
-                                eclk: eclk {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-emmc-clock";
-                                        clocks = <&emmcpll>;
-                                        reg = <0x114>;
-                                };
-
-                                pclk: pclk {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        clock-frequency = <150000000>;
-                                };
-                        };
-                };
 
                 sregs@fff3c200 {
                         compatible = "calxeda,hb-sregs-l2-ecc";
@@ -291,38 +116,7 @@
                         interrupts = <0 71 4  0 72 4>;
                 };
 
-                dma@fff3d000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0xfff3d000 0x1000>;
-                        interrupts = <0 92 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-
-                ethernet@fff50000 {
-                        compatible = "calxeda,hb-xgmac";
-                        reg = <0xfff50000 0x1000>;
-                        interrupts = <0 77 4  0 78 4  0 79 4>;
-                };
-
-                ethernet@fff51000 {
-                        compatible = "calxeda,hb-xgmac";
-                        reg = <0xfff51000 0x1000>;
-                        interrupts = <0 80 4  0 81 4  0 82 4>;
-                };
-
-                combophy0: combo-phy@fff58000 {
-                        compatible = "calxeda,hb-combophy";
-                        #phy-cells = <1>;
-                        reg = <0xfff58000 0x1000>;
-                        phydev = <5>;
-                };
-
-                combophy5: combo-phy@fff5d000 {
-                        compatible = "calxeda,hb-combophy";
-                        #phy-cells = <1>;
-                        reg = <0xfff5d000 0x1000>;
-                        phydev = <31>;
-                };
         };
 };
+
+/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
index 0a8978a40ece..b01c0d745fc5 100644
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -23,10 +23,6 @@
         soc {
                 aipi@10000000 { /* aipi */
 
-                        wdog@10002000 {
-                                status = "okay";
-                        };
-
                         uart1: serial@1000a000 {
                                 fsl,uart-has-rtscts;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cbd2b1c7487b..567e7ee72f91 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -22,6 +22,22 @@
         };
 
         soc {
+                display@di0 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 0>;
+                        interface-pix-fmt = "rgb24";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp1_1>;
+                };
+
+                display@di1 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 1>;
+                        interface-pix-fmt = "rgb565";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+                };
+
                 aips@70000000 { /* aips-1 */
                         spba@70000000 {
                                 esdhc@70004000 { /* ESDHC1 */
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 54aea74769a1..2781e47cff0d 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -62,6 +62,13 @@
                 interrupt-parent = <&tzic>;
                 ranges;
 
+                ipu: ipu@40000000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx51-ipu";
+                        reg = <0x40000000 0x20000000>;
+                        interrupts = <11 10>;
+                };
+
                 aips@70000000 { /* AIPS1 */
                         compatible = "fsl,aips-bus", "simple-bus";
                         #address-cells = <1>;
@@ -80,6 +87,8 @@
                                         compatible = "fsl,imx51-esdhc";
                                         reg = <0x70004000 0x4000>;
                                         interrupts = <1>;
+                                        clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
 
@@ -87,6 +96,8 @@
                                         compatible = "fsl,imx51-esdhc";
                                         reg = <0x70008000 0x4000>;
                                         interrupts = <2>;
+                                        clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
 
@@ -94,6 +105,8 @@
                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                         reg = <0x7000c000 0x4000>;
                                         interrupts = <33>;
+                                        clocks = <&clks 32>, <&clks 33>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -103,6 +116,8 @@
                                         compatible = "fsl,imx51-ecspi";
                                         reg = <0x70010000 0x4000>;
                                         interrupts = <36>;
+                                        clocks = <&clks 51>, <&clks 52>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -110,6 +125,7 @@
                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                         reg = <0x70014000 0x4000>;
                                         interrupts = <30>;
+                                        clocks = <&clks 49>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
                                         status = "disabled";
@@ -119,6 +135,8 @@
                                         compatible = "fsl,imx51-esdhc";
                                         reg = <0x70020000 0x4000>;
                                         interrupts = <3>;
+                                        clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
 
@@ -126,6 +144,8 @@
                                         compatible = "fsl,imx51-esdhc";
                                         reg = <0x70024000 0x4000>;
                                         interrupts = <4>;
+                                        clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
                         };
@@ -202,12 +222,14 @@
                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                 reg = <0x73f98000 0x4000>;
                                 interrupts = <58>;
+                                clocks = <&clks 0>;
                         };
 
                         wdog@73f9c000 { /* WDOG2 */
                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                 reg = <0x73f9c000 0x4000>;
                                 interrupts = <59>;
+                                clocks = <&clks 0>;
                                 status = "disabled";
                         };
 
@@ -295,6 +317,66 @@
                                         };
                                 };
 
+                                ipu_disp1 {
+                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                                                fsl,pins = <
+                                                        528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
+                                                        529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
+                                                        530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
+                                                        531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
+                                                        532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
+                                                        533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
+                                                        535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
+                                                        537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
+                                                        539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
+                                                        541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
+                                                        543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
+                                                        545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
+                                                        547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
+                                                        549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
+                                                        551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
+                                                        553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
+                                                        555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
+                                                        557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
+                                                        559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
+                                                        563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
+                                                        567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
+                                                        571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
+                                                        575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
+                                                        579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
+                                                        584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
+                                                        583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
+                                                >;
+                                        };
+                                };
+
+                                ipu_disp2 {
+                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                                                fsl,pins = <
+                                                        603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
+                                                        608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
+                                                        613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
+                                                        614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
+                                                        615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
+                                                        616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
+                                                        617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
+                                                        622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
+                                                        627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
+                                                        633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
+                                                        637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
+                                                        643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
+                                                        648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
+                                                        652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
+                                                        656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
+                                                        661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
+                                                        593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
+                                                        595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
+                                                        597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
+                                                        599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
+                                                >;
+                                        };
+                                };
+
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
@@ -327,10 +409,30 @@
                                 };
                         };
 
+                        pwm1: pwm@73fb4000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+                                reg = <0x73fb4000 0x4000>;
+                                clocks = <&clks 37>, <&clks 38>;
+                                clock-names = "ipg", "per";
+                                interrupts = <61>;
+                        };
+
+                        pwm2: pwm@73fb8000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+                                reg = <0x73fb8000 0x4000>;
+                                clocks = <&clks 39>, <&clks 40>;
+                                clock-names = "ipg", "per";
+                                interrupts = <94>;
+                        };
+
                         uart1: serial@73fbc000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fbc000 0x4000>;
                                 interrupts = <31>;
+                                clocks = <&clks 28>, <&clks 29>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -338,8 +440,17 @@
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fc0000 0x4000>;
                                 interrupts = <32>;
+                                clocks = <&clks 30>, <&clks 31>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
+
+                        clks: ccm@73fd4000{
+                                compatible = "fsl,imx51-ccm";
+                                reg = <0x73fd4000 0x4000>;
+                                interrupts = <0 71 0x04 0 72 0x04>;
+                                #clock-cells = <1>;
+                        };
                 };
 
                 aips@80000000 { /* AIPS2 */
@@ -355,6 +466,8 @@
                                 compatible = "fsl,imx51-ecspi";
                                 reg = <0x83fac000 0x4000>;
                                 interrupts = <37>;
+                                clocks = <&clks 53>, <&clks 54>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -362,6 +475,8 @@
                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
                                 reg = <0x83fb0000 0x4000>;
                                 interrupts = <6>;
+                                clocks = <&clks 56>, <&clks 56>;
+                                clock-names = "ipg", "ahb";
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                         };
 
@@ -371,6 +486,8 @@
                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
                                 reg = <0x83fc0000 0x4000>;
                                 interrupts = <38>;
+                                clocks = <&clks 55>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -380,6 +497,7 @@
                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
                                 reg = <0x83fc4000 0x4000>;
                                 interrupts = <63>;
+                                clocks = <&clks 35>;
                                 status = "disabled";
                         };
 
@@ -389,6 +507,7 @@
                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
                                 reg = <0x83fc8000 0x4000>;
                                 interrupts = <62>;
+                                clocks = <&clks 34>;
                                 status = "disabled";
                         };
 
@@ -396,6 +515,7 @@
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fcc000 0x4000>;
                                 interrupts = <29>;
+                                clocks = <&clks 48>;
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -411,6 +531,7 @@
                                 compatible = "fsl,imx51-nand";
                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
                                 interrupts = <8>;
+                                clocks = <&clks 60>;
                                 status = "disabled";
                         };
 
@@ -418,6 +539,7 @@
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fe8000 0x4000>;
                                 interrupts = <96>;
+                                clocks = <&clks 50>;
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -427,6 +549,8 @@
                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
                                 reg = <0x83fec000 0x4000>;
                                 interrupts = <87>;
+                                clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                                clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index caf09ff73f10..da9a047ce4cf 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -67,6 +67,13 @@
                 interrupt-parent = <&tzic>;
                 ranges;
 
+                ipu: ipu@18000000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx53-ipu";
+                        reg = <0x18000000 0x080000000>;
+                        interrupts = <11 10>;
+                };
+
                 aips@50000000 { /* AIPS1 */
                         compatible = "fsl,aips-bus", "simple-bus";
                         #address-cells = <1>;
@@ -85,6 +92,8 @@
                                         compatible = "fsl,imx53-esdhc";
                                         reg = <0x50004000 0x4000>;
                                         interrupts = <1>;
+                                        clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
 
@@ -92,6 +101,8 @@
                                         compatible = "fsl,imx53-esdhc";
                                         reg = <0x50008000 0x4000>;
                                         interrupts = <2>;
+                                        clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
 
@@ -99,6 +110,8 @@
                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                         reg = <0x5000c000 0x4000>;
                                         interrupts = <33>;
+                                        clocks = <&clks 32>, <&clks 33>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -108,6 +121,8 @@
                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x50010000 0x4000>;
                                         interrupts = <36>;
+                                        clocks = <&clks 51>, <&clks 52>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -115,6 +130,7 @@
                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                         reg = <0x50014000 0x4000>;
                                         interrupts = <30>;
+                                        clocks = <&clks 49>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
                                         status = "disabled";
@@ -124,6 +140,8 @@
                                         compatible = "fsl,imx53-esdhc";
                                         reg = <0x50020000 0x4000>;
                                         interrupts = <3>;
+                                        clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
 
@@ -131,6 +149,8 @@
                                         compatible = "fsl,imx53-esdhc";
                                         reg = <0x50024000 0x4000>;
                                         interrupts = <4>;
+                                        clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                        clock-names = "ipg", "ahb", "per";
                                         status = "disabled";
                                 };
                         };
@@ -207,12 +227,14 @@
                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                 reg = <0x53f98000 0x4000>;
                                 interrupts = <58>;
+                                clocks = <&clks 0>;
                         };
 
                         wdog@53f9c000 { /* WDOG2 */
                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                 reg = <0x53f9c000 0x4000>;
                                 interrupts = <59>;
+                                clocks = <&clks 0>;
                                 status = "disabled";
                         };
 
@@ -371,10 +393,30 @@
                                 };
                         };
 
+                        pwm1: pwm@53fb4000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fb4000 0x4000>;
+                                clocks = <&clks 37>, <&clks 38>;
+                                clock-names = "ipg", "per";
+                                interrupts = <61>;
+                        };
+
+                        pwm2: pwm@53fb8000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fb8000 0x4000>;
+                                clocks = <&clks 39>, <&clks 40>;
+                                clock-names = "ipg", "per";
+                                interrupts = <94>;
+                        };
+
                         uart1: serial@53fbc000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fbc000 0x4000>;
                                 interrupts = <31>;
+                                clocks = <&clks 28>, <&clks 29>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -382,6 +424,8 @@
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fc0000 0x4000>;
                                 interrupts = <32>;
+                                clocks = <&clks 30>, <&clks 31>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -389,6 +433,8 @@
                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x53fc8000 0x4000>;
                                 interrupts = <82>;
+                                clocks = <&clks 158>, <&clks 157>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -396,9 +442,18 @@
                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x53fcc000 0x4000>;
                                 interrupts = <83>;
+                                clocks = <&clks 158>, <&clks 157>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
+                        clks: ccm@53fd4000{
+                                compatible = "fsl,imx53-ccm";
+                                reg = <0x53fd4000 0x4000>;
+                                interrupts = <0 71 0x04 0 72 0x04>;
+                                #clock-cells = <1>;
+                        };
+
                         gpio5: gpio@53fdc000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53fdc000 0x4000>;
@@ -435,6 +490,7 @@
                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                 reg = <0x53fec000 0x4000>;
                                 interrupts = <64>;
+                                clocks = <&clks 88>;
                                 status = "disabled";
                         };
 
@@ -442,6 +498,8 @@
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53ff0000 0x4000>;
                                 interrupts = <13>;
+                                clocks = <&clks 65>, <&clks 66>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
                 };
@@ -457,6 +515,8 @@
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x63f90000 0x4000>;
                                 interrupts = <86>;
+                                clocks = <&clks 67>, <&clks 68>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -466,6 +526,8 @@
                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
                                 reg = <0x63fac000 0x4000>;
                                 interrupts = <37>;
+                                clocks = <&clks 53>, <&clks 54>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -473,6 +535,8 @@
                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
                                 reg = <0x63fb0000 0x4000>;
                                 interrupts = <6>;
+                                clocks = <&clks 56>, <&clks 56>;
+                                clock-names = "ipg", "ahb";
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                         };
 
@@ -482,6 +546,8 @@
                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
                                 reg = <0x63fc0000 0x4000>;
                                 interrupts = <38>;
+                                clocks = <&clks 55>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -491,6 +557,7 @@
                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                 reg = <0x63fc4000 0x4000>;
                                 interrupts = <63>;
+                                clocks = <&clks 35>;
                                 status = "disabled";
                         };
 
@@ -500,6 +567,7 @@
                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                 reg = <0x63fc8000 0x4000>;
                                 interrupts = <62>;
+                                clocks = <&clks 34>;
                                 status = "disabled";
                         };
 
@@ -507,6 +575,7 @@
                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                 reg = <0x63fcc000 0x4000>;
                                 interrupts = <29>;
+                                clocks = <&clks 48>;
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -522,6 +591,7 @@
                                 compatible = "fsl,imx53-nand";
                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
                                 interrupts = <8>;
+                                clocks = <&clks 60>;
                                 status = "disabled";
                         };
 
@@ -529,6 +599,7 @@
                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                 reg = <0x63fe8000 0x4000>;
                                 interrupts = <96>;
+                                clocks = <&clks 50>;
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -538,6 +609,8 @@
                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
                                 reg = <0x63fec000 0x4000>;
                                 interrupts = <87>;
+                                clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                                clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f604a44a5c66..d907d062e5dd 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -268,23 +268,39 @@
                         };
 
                         pwm@02080000 { /* PWM1 */
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                 reg = <0x02080000 0x4000>;
                                 interrupts = <0 83 0x04>;
+                                clocks = <&clks 62>, <&clks 145>;
+                                clock-names = "ipg", "per";
                         };
 
                         pwm@02084000 { /* PWM2 */
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                 reg = <0x02084000 0x4000>;
                                 interrupts = <0 84 0x04>;
+                                clocks = <&clks 62>, <&clks 146>;
+                                clock-names = "ipg", "per";
                         };
 
                         pwm@02088000 { /* PWM3 */
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                 reg = <0x02088000 0x4000>;
                                 interrupts = <0 85 0x04>;
+                                clocks = <&clks 62>, <&clks 147>;
+                                clock-names = "ipg", "per";
                         };
 
                         pwm@0208c000 { /* PWM4 */
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                 reg = <0x0208c000 0x4000>;
                                 interrupts = <0 86 0x04>;
+                                clocks = <&clks 62>, <&clks 148>;
+                                clock-names = "ipg", "per";
                         };
 
                         flexcan@02090000 { /* CAN1 */
@@ -1001,5 +1017,23 @@
                                 status = "disabled";
                         };
                 };
+
+                ipu1: ipu@02400000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx6q-ipu";
+                        reg = <0x02400000 0x400000>;
+                        interrupts = <0 6 0x4 0 5 0x4>;
+                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
+                        clock-names = "bus", "di0", "di1";
+                };
+
+                ipu2: ipu@02800000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx6q-ipu";
+                        reg = <0x02800000 0x400000>;
+                        interrupts = <0 8 0x4 0 7 0x4>;
+                        clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+                        clock-names = "bus", "di0", "di1";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7377.dtsi
deleted file mode 100644
index 767ee0796daa..000000000000
--- a/arch/arm/boot/dts/sh7377.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Device Tree Source for the sh7377 SoC
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-        compatible = "renesas,sh7377";
-
-        cpus {
-                cpu@0 {
-                        compatible = "arm,cortex-a8";
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/sun4i-cubieboard.dts b/arch/arm/boot/dts/sun4i-cubieboard.dts
new file mode 100644
index 000000000000..f4ca126ad994
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-cubieboard.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012 Stefan Roese
+ * Stefan Roese <sr@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun4i.dtsi"
+
+/ {
+        model = "Cubietech Cubieboard";
+        compatible = "cubietech,cubieboard", "allwinner,sun4i";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+
+        soc {
+                uart0: uart@01c28000 {
+                        status = "okay";
+                };
+
+                uart1: uart@01c28400 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i.dtsi b/arch/arm/boot/dts/sun4i.dtsi
new file mode 100644
index 000000000000..e61fdd47bd01
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2012 Stefan Roese
+ * Stefan Roese <sr@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "sunxi.dtsi"
+
+/ {
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
new file mode 100644
index 000000000000..d6ff889a5d87
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i.dtsi"
+
+/ {
+        model = "Olimex A13-Olinuxino";
+        compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
+
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+
+        soc {
+                uart1: uart@01c28400 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
new file mode 100644
index 000000000000..59a2d265a98e
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "sunxi.dtsi"
+
+/ {
+        memory {
+                reg = <0x40000000 0x20000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
new file mode 100644
index 000000000000..8bbc2bfef221
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc: oscillator {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sunxi-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sunxi-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sunxi-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                uart0: uart@01c28000 {
+                        compatible = "ns8250";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        clock-frequency = <24000000>;
+                        status = "disabled";
+                };
+
+                uart1: uart@01c28400 {
+                        compatible = "ns8250";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        clock-frequency = <24000000>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3a09d0d45bc..f40cfbaa7c7e 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,15 @@
         compatible = "nvidia,tegra20";
         interrupt-parent = <&intc>;
 
+        cache-controller@50043000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x50043000 0x1000>;
+                arm,data-latency = <5 5 2>;
+                arm,tag-latency = <4 4 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
         intc: interrupt-controller {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0x50041000 0x1000
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index df7f2270fc91..fed8dca1692d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,15 @@
         compatible = "nvidia,tegra30";
         interrupt-parent = <&intc>;
 
+        cache-controller@50043000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x50043000 0x1000>;
+                arm,data-latency = <6 6 2>;
+                arm,tag-latency = <5 5 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
         intc: interrupt-controller {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0x50041000 0x1000
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827bd2bf3..ac870fb3fa0d 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -17,17 +17,16 @@
  * CHANGES TO vexpress-v2m.dtsi!
  */
 
-/ {
-        aliases {
-                arm,v2m_timer = &v2m_timer01;
-        };
-
         motherboard {
-                compatible = "simple-bus";
+                model = "V2M-P1";
+                arm,hbi = <0x190>;
+                arm,vexpress,site = <0>;
                 arm,v2m-memory-map = "rs1";
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                 #address-cells = <2>; /* SMB chipselect number and offset */
                 #size-cells = <1>;
                 #interrupt-cells = <1>;
+                ranges;
 
                 flash@0,00000000 {
                         compatible = "arm,vexpress-flash", "cfi-flash";
@@ -72,14 +71,20 @@
                         #size-cells = <1>;
                         ranges = <0 3 0 0x200000>;
 
-                        sysreg@010000 {
+                        v2m_sysreg: sysreg@010000 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x010000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                         };
 
-                        sysctl@020000 {
+                        v2m_sysctl: sysctl@020000 {
                                 compatible = "arm,sp810", "arm,primecell";
                                 reg = <0x020000 0x1000>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+                                clock-names = "refclk", "timclk", "apb_pclk";
+                                #clock-cells = <1>;
+                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
                         };
 
                         /* PCI-E I2C bus */
@@ -100,66 +105,92 @@
                                 compatible = "arm,pl041", "arm,primecell";
                                 reg = <0x040000 0x1000>;
                                 interrupts = <11>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                         };
 
                         mmci@050000 {
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x050000 0x1000>;
                                 interrupts = <9 10>;
+                                cd-gpios = <&v2m_sysreg 0 0>;
+                                wp-gpios = <&v2m_sysreg 1 0>;
+                                max-frequency = <12000000>;
+                                vmmc-supply = <&v2m_fixed_3v3>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
 
                         kmi@060000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x060000 0x1000>;
                                 interrupts = <12>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
                         kmi@070000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x070000 0x1000>;
                                 interrupts = <13>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
                         v2m_serial0: uart@090000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x090000 0x1000>;
                                 interrupts = <5>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial1: uart@0a0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0a0000 0x1000>;
                                 interrupts = <6>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial2: uart@0b0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0b0000 0x1000>;
                                 interrupts = <7>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial3: uart@0c0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0c0000 0x1000>;
                                 interrupts = <8>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         wdt@0f0000 {
                                 compatible = "arm,sp805", "arm,primecell";
                                 reg = <0x0f0000 0x1000>;
                                 interrupts = <0>;
+                                clocks = <&v2m_refclk32khz>, <&smbclk>;
+                                clock-names = "wdogclk", "apb_pclk";
                         };
 
                         v2m_timer01: timer@110000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x110000 0x1000>;
                                 interrupts = <2>;
+                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                         };
 
                         v2m_timer23: timer@120000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x120000 0x1000>;
                                 interrupts = <3>;
+                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                         };
 
                         /* DVI I2C bus */
@@ -185,6 +216,8 @@
                                 compatible = "arm,pl031", "arm,primecell";
                                 reg = <0x170000 0x1000>;
                                 interrupts = <4>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                         };
 
                         compact-flash@1a0000 {
@@ -198,6 +231,8 @@
                                 compatible = "arm,pl111", "arm,primecell";
                                 reg = <0x1f0000 0x1000>;
                                 interrupts = <14>;
+                                clocks = <&v2m_oscclk1>, <&smbclk>;
+                                clock-names = "clcdclk", "apb_pclk";
                         };
                 };
 
@@ -208,5 +243,98 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+
+                mcc {
+                        compatible = "arm,vexpress,config-bus";
+                        arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                        osc@0 {
+                                /* MCC static memory clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 0>;
+                                freq-range = <25000000 60000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk0";
+                        };
+
+                        v2m_oscclk1: osc@1 {
+                                /* CLCD clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 1>;
+                                freq-range = <23750000 63500000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk1";
+                        };
+
+                        v2m_oscclk2: osc@2 {
+                                /* IO FPGA peripheral clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 2>;
+                                freq-range = <24000000 24000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk2";
+                        };
+
+                        volt@0 {
+                                /* Logic level voltage */
+                                compatible = "arm,vexpress-volt";
+                                arm,vexpress-sysreg,func = <2 0>;
+                                regulator-name = "VIO";
+                                regulator-always-on;
+                                label = "VIO";
+                        };
+
+                        temp@0 {
+                                /* MCC internal operating temperature */
+                                compatible = "arm,vexpress-temp";
+                                arm,vexpress-sysreg,func = <4 0>;
+                                label = "MCC";
+                        };
+
+                        reset@0 {
+                                compatible = "arm,vexpress-reset";
+                                arm,vexpress-sysreg,func = <5 0>;
+                        };
+
+                        muxfpga@0 {
+                                compatible = "arm,vexpress-muxfpga";
+                                arm,vexpress-sysreg,func = <7 0>;
+                        };
+
+                        shutdown@0 {
+                                compatible = "arm,vexpress-shutdown";
+                                arm,vexpress-sysreg,func = <8 0>;
+                        };
+
+                        reboot@0 {
+                                compatible = "arm,vexpress-reboot";
+                                arm,vexpress-sysreg,func = <9 0>;
+                        };
+
+                        dvimode@0 {
+                                compatible = "arm,vexpress-dvimode";
+                                arm,vexpress-sysreg,func = <11 0>;
+                        };
+                };
         };
-};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index dba53fd026bb..f1420368355b 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -17,16 +17,15 @@
  * CHANGES TO vexpress-v2m-rs1.dtsi!
  */
 
-/ {
-        aliases {
-                arm,v2m_timer = &v2m_timer01;
-        };
-
         motherboard {
-                compatible = "simple-bus";
+                model = "V2M-P1";
+                arm,hbi = <0x190>;
+                arm,vexpress,site = <0>;
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                 #address-cells = <2>; /* SMB chipselect number and offset */
                 #size-cells = <1>;
                 #interrupt-cells = <1>;
+                ranges;
 
                 flash@0,00000000 {
                         compatible = "arm,vexpress-flash", "cfi-flash";
@@ -71,14 +70,20 @@
                         #size-cells = <1>;
                         ranges = <0 7 0 0x20000>;
 
-                        sysreg@00000 {
+                        v2m_sysreg: sysreg@00000 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x00000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                         };
 
-                        sysctl@01000 {
+                        v2m_sysctl: sysctl@01000 {
                                 compatible = "arm,sp810", "arm,primecell";
                                 reg = <0x01000 0x1000>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+                                clock-names = "refclk", "timclk", "apb_pclk";
+                                #clock-cells = <1>;
+                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
                         };
 
                         /* PCI-E I2C bus */
@@ -99,66 +104,92 @@
                                 compatible = "arm,pl041", "arm,primecell";
                                 reg = <0x04000 0x1000>;
                                 interrupts = <11>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                         };
 
                         mmci@05000 {
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x05000 0x1000>;
                                 interrupts = <9 10>;
+                                cd-gpios = <&v2m_sysreg 0 0>;
+                                wp-gpios = <&v2m_sysreg 1 0>;
+                                max-frequency = <12000000>;
+                                vmmc-supply = <&v2m_fixed_3v3>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
 
                         kmi@06000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x06000 0x1000>;
                                 interrupts = <12>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
                         kmi@07000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x07000 0x1000>;
                                 interrupts = <13>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
                         v2m_serial0: uart@09000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x09000 0x1000>;
                                 interrupts = <5>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial1: uart@0a000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0a000 0x1000>;
                                 interrupts = <6>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial2: uart@0b000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0b000 0x1000>;
                                 interrupts = <7>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial3: uart@0c000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0c000 0x1000>;
                                 interrupts = <8>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         wdt@0f000 {
                                 compatible = "arm,sp805", "arm,primecell";
                                 reg = <0x0f000 0x1000>;
                                 interrupts = <0>;
+                                clocks = <&v2m_refclk32khz>, <&smbclk>;
+                                clock-names = "wdogclk", "apb_pclk";
                         };
 
                         v2m_timer01: timer@11000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x11000 0x1000>;
                                 interrupts = <2>;
+                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                         };
 
                         v2m_timer23: timer@12000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x12000 0x1000>;
                                 interrupts = <3>;
+                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                         };
 
                         /* DVI I2C bus */
@@ -184,6 +215,8 @@
                                 compatible = "arm,pl031", "arm,primecell";
                                 reg = <0x17000 0x1000>;
                                 interrupts = <4>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                         };
 
                         compact-flash@1a000 {
@@ -197,6 +230,8 @@
                                 compatible = "arm,pl111", "arm,primecell";
                                 reg = <0x1f000 0x1000>;
                                 interrupts = <14>;
+                                clocks = <&v2m_oscclk1>, <&smbclk>;
+                                clock-names = "clcdclk", "apb_pclk";
                         };
                 };
 
@@ -207,5 +242,98 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+
+                mcc {
+                        compatible = "arm,vexpress,config-bus";
+                        arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                        osc@0 {
+                                /* MCC static memory clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 0>;
+                                freq-range = <25000000 60000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk0";
+                        };
+
+                        v2m_oscclk1: osc@1 {
+                                /* CLCD clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 1>;
+                                freq-range = <23750000 63500000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk1";
+                        };
+
+                        v2m_oscclk2: osc@2 {
+                                /* IO FPGA peripheral clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 2>;
+                                freq-range = <24000000 24000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk2";
+                        };
+
+                        volt@0 {
+                                /* Logic level voltage */
+                                compatible = "arm,vexpress-volt";
+                                arm,vexpress-sysreg,func = <2 0>;
+                                regulator-name = "VIO";
+                                regulator-always-on;
+                                label = "VIO";
+                        };
+
+                        temp@0 {
+                                /* MCC internal operating temperature */
+                                compatible = "arm,vexpress-temp";
+                                arm,vexpress-sysreg,func = <4 0>;
+                                label = "MCC";
+                        };
+
+                        reset@0 {
+                                compatible = "arm,vexpress-reset";
+                                arm,vexpress-sysreg,func = <5 0>;
+                        };
+
+                        muxfpga@0 {
+                                compatible = "arm,vexpress-muxfpga";
+                                arm,vexpress-sysreg,func = <7 0>;
+                        };
+
+                        shutdown@0 {
+                                compatible = "arm,vexpress-shutdown";
+                                arm,vexpress-sysreg,func = <8 0>;
+                        };
+
+                        reboot@0 {
+                                compatible = "arm,vexpress-reboot";
+                                arm,vexpress-sysreg,func = <9 0>;
+                        };
+
+                        dvimode@0 {
+                                compatible = "arm,vexpress-dvimode";
+                                arm,vexpress-sysreg,func = <11 0>;
+                        };
+                };
         };
-};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34ca0568..a3d37ec2655d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -12,6 +12,7 @@
 / {
         model = "V2P-CA15";
         arm,hbi = <0x237>;
+        arm,vexpress,site = <0xf>;
         compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
         interrupt-parent = <&gic>;
         #address-cells = <2>;
@@ -54,17 +55,24 @@
                 compatible = "arm,hdlcd";
                 reg = <0 0x2b000000 0 0x1000>;
                 interrupts = <0 85 4>;
+                clocks = <&oscclk5>;
+                clock-names = "pxlclk";
         };
 
         memory-controller@2b0a0000 {
                 compatible = "arm,pl341", "arm,primecell";
                 reg = <0 0x2b0a0000 0 0x1000>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
         };
 
         wdt@2b060000 {
                 compatible = "arm,sp805", "arm,primecell";
+                status = "disabled";
                 reg = <0 0x2b060000 0 0x1000>;
                 interrupts = <98>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
         };
 
         gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@
                 reg = <0 0x7ffd0000 0 0x1000>;
                 interrupts = <0 86 4>,
                              <0 87 4>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
         };
 
         dma@7ffb0000 {
@@ -94,6 +104,8 @@
                              <0 89 4>,
                              <0 90 4>,
                              <0 91 4>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
         };
 
         timer {
@@ -110,7 +122,109 @@
                              <0 69 4>;
         };
 
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        /* CPU PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <50000000 60000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk0";
+                };
+
+                osc@4 {
+                        /* Multiplexed AXI master clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 4>;
+                        freq-range = <20000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk4";
+                };
+
+                oscclk5: osc@5 {
+                        /* HDLCD PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 5>;
+                        freq-range = <23750000 165000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk5";
+                };
+
+                smbclk: osc@6 {
+                        /* SMB clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 6>;
+                        freq-range = <20000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk6";
+                };
+
+                oscclk7: osc@7 {
+                        /* SYS PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 7>;
+                        freq-range = <20000000 60000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk7";
+                };
+
+                osc@8 {
+                        /* DDR2 PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 8>;
+                        freq-range = <40000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk8";
+                };
+
+                volt@0 {
+                        /* CPU core voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "Cores";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <1050000>;
+                        regulator-always-on;
+                        label = "Cores";
+                };
+
+                amp@0 {
+                        /* Total current for the two cores */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "Cores";
+                };
+
+                temp@0 {
+                        /* DCC internal temperature */
+                        compatible = "arm,vexpress-temp";
+                        arm,vexpress-sysreg,func = <4 0>;
+                        label = "DCC";
+                };
+
+                power@0 {
+                        /* Total power */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "Cores";
+                };
+
+                energy@0 {
+                        /* Total energy */
+                        compatible = "arm,vexpress-energy";
+                        arm,vexpress-sysreg,func = <13 0>;
+                        label = "Cores";
+                };
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
                 ranges = <0 0 0 0x08000000 0x04000000>,
                          <1 0 0 0x14000000 0x04000000>,
                          <2 0 0 0x18000000 0x04000000>,
@@ -118,6 +232,7 @@
                          <4 0 0 0x0c000000 0x04000000>,
                          <5 0 0 0x10000000 0x04000000>;
 
+                #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
                                 <0 0  1 &gic 0  1 4>,
@@ -162,7 +277,7 @@
                                 <0 0 40 &gic 0 40 4>,
                                 <0 0 41 &gic 0 41 4>,
                                 <0 0 42 &gic 0 42 4>;
+
+                /include/ "vexpress-v2m-rs1.dtsi"
         };
 };
-
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 4890a81c5467..1fc405a9ecfb 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -12,6 +12,7 @@
 / {
         model = "V2P-CA15_CA7";
         arm,hbi = <0x249>;
+        arm,vexpress,site = <0xf>;
         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
         interrupt-parent = <&gic>;
         #address-cells = <2>;
@@ -74,17 +75,23 @@
                 compatible = "arm,sp805", "arm,primecell";
                 reg = <0 0x2a490000 0 0x1000>;
                 interrupts = <98>;
+                clocks = <&oscclk6a>, <&oscclk6a>;
+                clock-names = "wdogclk", "apb_pclk";
         };
 
         hdlcd@2b000000 {
                 compatible = "arm,hdlcd";
                 reg = <0 0x2b000000 0 0x1000>;
                 interrupts = <0 85 4>;
+                clocks = <&oscclk5>;
+                clock-names = "pxlclk";
         };
 
         memory-controller@2b0a0000 {
                 compatible = "arm,pl341", "arm,primecell";
                 reg = <0 0x2b0a0000 0 0x1000>;
+                clocks = <&oscclk6a>;
+                clock-names = "apb_pclk";
         };
 
         gic: interrupt-controller@2c001000 {
@@ -104,6 +111,8 @@
                 reg = <0 0x7ffd0000 0 0x1000>;
                 interrupts = <0 86 4>,
                              <0 87 4>;
+                clocks = <&oscclk6a>;
+                clock-names = "apb_pclk";
         };
 
         dma@7ff00000 {
@@ -114,6 +123,8 @@
                              <0 89 4>,
                              <0 90 4>,
                              <0 91 4>;
+                clocks = <&oscclk6a>;
+                clock-names = "apb_pclk";
         };
 
         timer {
@@ -130,7 +141,175 @@
                              <0 69 4>;
         };
 
-        motherboard {
+        oscclk6a: oscclk6a {
+                /* Reference 24MHz clock */
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+                clock-output-names = "oscclk6a";
+        };
+
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        /* A15 PLL 0 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk0";
+                };
+
+                osc@1 {
+                        /* A15 PLL 1 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk1";
+                };
+
+                osc@2 {
+                        /* A7 PLL 0 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk2";
+                };
+
+                osc@3 {
+                        /* A7 PLL 1 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 3>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk3";
+                };
+
+                osc@4 {
+                        /* External AXI master clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 4>;
+                        freq-range = <20000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk4";
+                };
+
+                oscclk5: osc@5 {
+                        /* HDLCD PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 5>;
+                        freq-range = <23750000 165000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk5";
+                };
+
+                smbclk: osc@6 {
+                        /* Static memory controller clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 6>;
+                        freq-range = <20000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk6";
+                };
+
+                osc@7 {
+                        /* SYS PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 7>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk7";
+                };
+
+                osc@8 {
+                        /* DDR2 PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 8>;
+                        freq-range = <20000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk8";
+                };
+
+                volt@0 {
+                        /* A15 CPU core voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "A15 Vcore";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <1050000>;
+                        regulator-always-on;
+                        label = "A15 Vcore";
+                };
+
+                volt@1 {
+                        /* A7 CPU core voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 1>;
+                        regulator-name = "A7 Vcore";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <1050000>;
+                        regulator-always-on;
+                        label = "A7 Vcore";
+                };
+
+                amp@0 {
+                        /* Total current for the two A15 cores */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "A15 Icore";
+                };
+
+                amp@1 {
+                        /* Total current for the three A7 cores */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 1>;
+                        label = "A7 Icore";
+                };
+
+                temp@0 {
+                        /* DCC internal temperature */
+                        compatible = "arm,vexpress-temp";
+                        arm,vexpress-sysreg,func = <4 0>;
+                        label = "DCC";
+                };
+
+                power@0 {
+                        /* Total power for the two A15 cores */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "A15 Pcore";
+                };
+                power@1 {
+                        /* Total power for the three A7 cores */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 1>;
+                        label = "A7 Pcore";
+                };
+
+                energy@0 {
+                        /* Total energy for the two A15 cores */
+                        compatible = "arm,vexpress-energy";
+                        arm,vexpress-sysreg,func = <13 0>;
+                        label = "A15 Jcore";
+                };
+
+                energy@2 {
+                        /* Total energy for the three A7 cores */
+                        compatible = "arm,vexpress-energy";
+                        arm,vexpress-sysreg,func = <13 2>;
+                        label = "A7 Jcore";
+                };
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
                 ranges = <0 0 0 0x08000000 0x04000000>,
                          <1 0 0 0x14000000 0x04000000>,
                          <2 0 0 0x18000000 0x04000000>,
@@ -138,6 +317,7 @@
                          <4 0 0 0x0c000000 0x04000000>,
                          <5 0 0 0x10000000 0x04000000>;
 
+                #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
                                 <0 0  1 &gic 0  1 4>,
@@ -182,7 +362,7 @@
                                 <0 0 40 &gic 0 40 4>,
                                 <0 0 41 &gic 0 41 4>,
                                 <0 0 42 &gic 0 42 4>;
+
+                /include/ "vexpress-v2m-rs1.dtsi"
         };
 };
-
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0f8604..6328cbc71d30 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -12,6 +12,7 @@
 / {
         model = "V2P-CA5s";
         arm,hbi = <0x225>;
+        arm,vexpress,site = <0xf>;
         compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
         interrupt-parent = <&gic>;
         #address-cells = <1>;
@@ -56,11 +57,15 @@
                 compatible = "arm,hdlcd";
                 reg = <0x2a110000 0x1000>;
                 interrupts = <0 85 4>;
+                clocks = <&oscclk3>;
+                clock-names = "pxlclk";
         };
 
         memory-controller@2a150000 {
                 compatible = "arm,pl341", "arm,primecell";
                 reg = <0x2a150000 0x1000>;
+                clocks = <&oscclk1>;
+                clock-names = "apb_pclk";
         };
 
         memory-controller@2a190000 {
@@ -68,6 +73,8 @@
                 reg = <0x2a190000 0x1000>;
                 interrupts = <0 86 4>,
                              <0 87 4>;
+                clocks = <&oscclk1>;
+                clock-names = "apb_pclk";
         };
 
         scu@2c000000 {
@@ -109,7 +116,77 @@
                              <0 69 4>;
         };
 
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        /* CPU and internal AXI reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <50000000 100000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk0";
+                };
+
+                oscclk1: osc@1 {
+                        /* Multiplexed AXI master clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <5000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk1";
+                };
+
+                osc@2 {
+                        /* DDR2 */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <80000000 120000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk2";
+                };
+
+                oscclk3: osc@3 {
+                        /* HDLCD */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 3>;
+                        freq-range = <23750000 165000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk3";
+                };
+
+                osc@4 {
+                        /* Test chip gate configuration */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 4>;
+                        freq-range = <80000000 80000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk4";
+                };
+
+                smbclk: osc@5 {
+                        /* SMB clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 5>;
+                        freq-range = <25000000 60000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk5";
+                };
+
+                temp@0 {
+                        /* DCC internal operating temperature */
+                        compatible = "arm,vexpress-temp";
+                        arm,vexpress-sysreg,func = <4 0>;
+                        label = "DCC";
+                };
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
                 ranges = <0 0 0x08000000 0x04000000>,
                          <1 0 0x14000000 0x04000000>,
                          <2 0 0x18000000 0x04000000>,
@@ -117,6 +194,7 @@
                          <4 0 0x0c000000 0x04000000>,
                          <5 0 0x10000000 0x04000000>;
 
+                #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
                                 <0 0  1 &gic 0  1 4>,
@@ -161,7 +239,7 @@
                                 <0 0 40 &gic 0 40 4>,
                                 <0 0 41 &gic 0 41 4>,
                                 <0 0 42 &gic 0 42 4>;
+
+                /include/ "vexpress-v2m-rs1.dtsi"
         };
 };
-
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736d31d6..1420bb14d95c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -12,6 +12,7 @@
 / {
         model = "V2P-CA9";
         arm,hbi = <0x191>;
+        arm,vexpress,site = <0xf>;
         compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
         interrupt-parent = <&gic>;
         #address-cells = <1>;
@@ -70,11 +71,15 @@
                 compatible = "arm,pl111", "arm,primecell";
                 reg = <0x10020000 0x1000>;
                 interrupts = <0 44 4>;
+                clocks = <&oscclk1>, <&oscclk2>;
+                clock-names = "clcdclk", "apb_pclk";
         };
 
         memory-controller@100e0000 {
                 compatible = "arm,pl341", "arm,primecell";
                 reg = <0x100e0000 0x1000>;
+                clocks = <&oscclk2>;
+                clock-names = "apb_pclk";
         };
 
         memory-controller@100e1000 {
@@ -82,6 +87,8 @@
                 reg = <0x100e1000 0x1000>;
                 interrupts = <0 45 4>,
                              <0 46 4>;
+                clocks = <&oscclk2>;
+                clock-names = "apb_pclk";
         };
 
         timer@100e4000 {
@@ -89,12 +96,16 @@
                 reg = <0x100e4000 0x1000>;
                 interrupts = <0 48 4>,
                              <0 49 4>;
+                clocks = <&oscclk2>, <&oscclk2>;
+                clock-names = "timclk", "apb_pclk";
         };
 
         watchdog@100e5000 {
                 compatible = "arm,sp805", "arm,primecell";
                 reg = <0x100e5000 0x1000>;
                 interrupts = <0 51 4>;
+                clocks = <&oscclk2>, <&oscclk2>;
+                clock-names = "wdogclk", "apb_pclk";
         };
 
         scu@1e000000 {
@@ -140,13 +151,132 @@
                              <0 63 4>;
         };
 
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        /* ACLK clock to the AXI master port on the test chip */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <30000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "extsaxiclk";
+                };
+
+                oscclk1: osc@1 {
+                        /* Reference clock for the CLCD */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <10000000 80000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "clcdclk";
+                };
+
+                smbclk: oscclk2: osc@2 {
+                        /* Reference clock for the test chip internal PLLs */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <33000000 100000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "tcrefclk";
+                };
+
+                volt@0 {
+                        /* Test Chip internal logic voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "VD10";
+                        regulator-always-on;
+                        label = "VD10";
+                };
+
+                volt@1 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 1>;
+                        regulator-name = "VD10_S2";
+                        regulator-always-on;
+                        label = "VD10_S2";
+                };
+
+                volt@2 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 2>;
+                        regulator-name = "VD10_S3";
+                        regulator-always-on;
+                        label = "VD10_S3";
+                };
+
+                volt@3 {
+                        /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 3>;
+                        regulator-name = "VCC1V8";
+                        regulator-always-on;
+                        label = "VCC1V8";
+                };
+
+                volt@4 {
+                        /* DDR2 SDRAM VTT termination voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 4>;
+                        regulator-name = "DDR2VTT";
+                        regulator-always-on;
+                        label = "DDR2VTT";
+                };
+
+                volt@5 {
+                        /* Local board supply for miscellaneous logic external to the Test Chip */
+                        arm,vexpress-sysreg,func = <2 5>;
+                        compatible = "arm,vexpress-volt";
+                        regulator-name = "VCC3V3";
+                        regulator-always-on;
+                        label = "VCC3V3";
+                };
+
+                amp@0 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "VD10_S2";
+                };
+
+                amp@1 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 1>;
+                        label = "VD10_S3";
+                };
+
+                power@0 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "PVD10_S2";
+                };
+
+                power@1 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 1>;
+                        label = "PVD10_S3";
+                };
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
                 ranges = <0 0 0x40000000 0x04000000>,
                          <1 0 0x44000000 0x04000000>,
                          <2 0 0x48000000 0x04000000>,
                          <3 0 0x4c000000 0x04000000>,
                          <7 0 0x10000000 0x00020000>;
 
+                #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
                                 <0 0  1 &gic 0  1 4>,
@@ -191,7 +321,7 @@
                                 <0 0 40 &gic 0 40 4>,
                                 <0 0 41 &gic 0 41 4>,
                                 <0 0 42 &gic 0 42 4>;
+
+                /include/ "vexpress-v2m.dtsi"
         };
 };
-
-/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f78d259f8d23..3d764072dd54 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -7,6 +7,7 @@ CONFIG_LOG_BUF_SHIFT=16
 # CONFIG_IPC_NS is not set
 # CONFIG_PID_NS is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 7aea70253c63..74e27f0ff6ad 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -66,8 +66,6 @@ CONFIG_TTY_PRINTK=y
 # CONFIG_FILE_LOCKING is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_FS is not set
-# CONFIG_SYSFS is not set
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PRINTK_TIME=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
new file mode 100644
index 000000000000..e3bf2d65618e
--- /dev/null
+++ b/arch/arm/configs/bcm_defconfig
@@ -0,0 +1,114 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_COMPACTION is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M"
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_BLK_DEV is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
+CONFIG_XZ_DEC=y
+CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
new file mode 100644
index 000000000000..1cd94c36321f
--- /dev/null
+++ b/arch/arm/configs/clps711x_defconfig
@@ -0,0 +1,90 @@
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLOB=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_LBDAF is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_CLPS711X=y
+CONFIG_ARCH_AUTCPU12=y
+CONFIG_ARCH_CDB89712=y
+CONFIG_ARCH_CLEP7312=y
+CONFIG_ARCH_EDB7211=y
+CONFIG_ARCH_P720T=y
+CONFIG_ARCH_FORTUNET=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_COREDUMP is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=y
+CONFIG_IRTTY_SIR=y
+CONFIG_EP7211_DONGLE=y
+# CONFIG_WIRELESS is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_AUTCPU12=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+CONFIG_CS89x0=y
+CONFIG_CS89x0_PLATFORM=y
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_CLPS711X_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_CLPS711X=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_PLATFORM=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_MINIX_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/edb7211_defconfig b/arch/arm/configs/edb7211_defconfig
deleted file mode 100644
index d52ded350a12..000000000000
--- a/arch/arm/configs/edb7211_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
-CONFIG_ARCH_EDB7211=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_VT is not set
-CONFIG_SERIAL_CLPS711X=y
-CONFIG_SERIAL_CLPS711X_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_MINIX_FS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/fortunet_defconfig b/arch/arm/configs/fortunet_defconfig
deleted file mode 100644
index 840fced7529f..000000000000
--- a/arch/arm/configs/fortunet_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
-CONFIG_ARCH_FORTUNET=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_FASTFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_CLPS711X=y
-CONFIG_SERIAL_CLPS711X_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 53382b6c8bb4..f79b55c512d0 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -69,6 +69,8 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=6
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index e2184f6c20b3..a7827fd0616f 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -80,6 +80,10 @@ CONFIG_RFKILL_GPIO=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_CMA=y
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_AD525X_DPOT=y
@@ -98,12 +102,12 @@ CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
+CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
-# CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
@@ -116,7 +120,8 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
-CONFIG_SPI_TEGRA=y
+CONFIG_SPI_TEGRA20_SFLASH=y
+CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
@@ -138,6 +143,15 @@ CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
+CONFIG_DRM=y
+CONFIG_DRM_TEGRA=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -205,6 +219,9 @@ CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index afd7e916472f..6636430dd0e6 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -50,12 +50,6 @@
 #define SCPCELLID2              0xFF8
 #define SCPCELLID3              0xFFC
 
-#define SCCTRL_TIMEREN0SEL_REFCLK       (0 << 15)
-#define SCCTRL_TIMEREN0SEL_TIMCLK       (1 << 15)
-
-#define SCCTRL_TIMEREN1SEL_REFCLK       (0 << 17)
-#define SCCTRL_TIMEREN1SEL_TIMCLK       (1 << 17)
-
 #define SCCTRL_TIMERENnSEL_SHIFT(n)     (15 + ((n) * 2))
 
 static inline void sysctl_soft_reset(void __iomem *base)
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 195ac2f9d3d3..2fe141fcc8d6 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -40,6 +40,13 @@ extern void iotable_init(struct map_desc *, int);
 extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
                                   void *caller);
 
+#ifdef CONFIG_DEBUG_LL
+extern void debug_ll_addr(unsigned long *paddr, unsigned long *vaddr);
+extern void debug_ll_io_init(void);
+#else
+static inline void debug_ll_io_init(void) {}
+#endif
+
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
 /*
diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
new file mode 100644
index 000000000000..04eb56d5db2c
--- /dev/null
+++ b/arch/arm/include/debug/sunxi.S
@@ -0,0 +1,27 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#if defined(CONFIG_DEBUG_SUNXI_UART0)
+#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28000
+#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28000
+#elif defined(CONFIG_DEBUG_SUNXI_UART1)
+#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
+#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
+#endif
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =SUNXI_UART_DEBUG_PHYS_BASE
+        ldr     \rv, =SUNXI_UART_DEBUG_VIRT_BASE
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 66f711b2e0e8..6809200c31fb 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -100,6 +100,13 @@ ENTRY(printch)
                 b       1b
 ENDPROC(printch)
 
+ENTRY(debug_ll_addr)
+                addruart r2, r3, ip
+                str     r2, [r0]
+                str     r3, [r1]
+                mov     pc, lr
+ENDPROC(debug_ll_addr)
+
 #else
 
 ENTRY(printascii)
@@ -119,4 +126,11 @@ ENTRY(printch)
                 mov     pc, lr
 ENDPROC(printch)
 
+ENTRY(debug_ll_addr)
+                mov     r2, #0
+                str     r2, [r0]
+                str     r2, [r1]
+                mov     pc, lr
+ENDPROC(debug_ll_addr)
+
 #endif
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index ff07879ad95d..49f335d301ba 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -390,10 +390,8 @@ void __init twd_local_timer_of_register(void)
         int err;
 
         np = of_find_matching_node(NULL, twd_of_match);
-        if (!np) {
-                err = -ENODEV;
-                goto out;
-        }
+        if (!np)
+                return;
 
         twd_ppi = irq_of_parse_and_map(np, 0);
         if (!twd_ppi) {
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
new file mode 100644
index 000000000000..48705c10a0fe
--- /dev/null
+++ b/arch/arm/mach-bcm/Kconfig
@@ -0,0 +1,19 @@
+config ARCH_BCM
+        bool "Broadcom SoC" if ARCH_MULTI_V7
+        depends on MMU
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369 if SMP
+        select ARM_GIC
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select GENERIC_TIME
+        select GPIO_BCM
+        select SPARSE_IRQ
+        select TICK_ONESHOT
+        help
+          This enables support for system based on Broadcom SoCs.
+          It currently supports the 'BCM281XX' family, which includes
+          BCM11130, BCM11140, BCM11351, BCM28145 and
+          BCM28155 variants.
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
new file mode 100644
index 000000000000..bbf412261e5e
--- /dev/null
+++ b/arch/arm/mach-bcm/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2012 Broadcom Corporation
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+obj-$(CONFIG_ARCH_BCM) := board_bcm.o
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
new file mode 100644
index 000000000000..3a62f1b1cabc
--- /dev/null
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <asm/mach/time.h>
+
+static const struct of_device_id irq_match[] = {
+        {.compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+
+static void timer_init(void)
+{
+}
+
+static struct sys_timer timer = {
+        .init = timer_init,
+};
+
+static void __init init_irq(void)
+{
+        of_irq_init(irq_match);
+}
+
+static void __init board_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                &platform_bus);
+}
+
+static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
+
+DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
+        .init_irq = init_irq,
+        .timer = &timer,
+        .init_machine = board_init,
+        .dt_compat = bcm11351_dt_compat,
+        .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 53e3842c9330..f0d739f4b7a3 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -12,8 +12,10 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/irqchip/bcm2835.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/bcm2835_timer.h>
 #include <linux/clk/bcm2835.h>
@@ -23,6 +25,48 @@
 
 #include <mach/bcm2835_soc.h>
 
+#define PM_RSTC                         0x1c
+#define PM_WDOG                         0x24
+
+#define PM_PASSWORD                     0x5a000000
+#define PM_RSTC_WRCFG_MASK              0x00000030
+#define PM_RSTC_WRCFG_FULL_RESET        0x00000020
+
+static void __iomem *wdt_regs;
+
+/*
+ * The machine restart method can be called from an atomic context so we won't
+ * be able to ioremap the regs then.
+ */
+static void bcm2835_setup_restart(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                                "brcm,bcm2835-pm-wdt");
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+
+        wdt_regs = of_iomap(np, 0);
+        WARN(!wdt_regs, "failed to remap watchdog regs");
+}
+
+static void bcm2835_restart(char mode, const char *cmd)
+{
+        u32 val;
+
+        if (!wdt_regs)
+                return;
+
+        /* use a timeout of 10 ticks (~150us) */
+        writel_relaxed(10 | PM_PASSWORD, wdt_regs + PM_WDOG);
+        val = readl_relaxed(wdt_regs + PM_RSTC);
+        val &= ~PM_RSTC_WRCFG_MASK;
+        val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
+        writel_relaxed(val, wdt_regs + PM_RSTC);
+
+        /* No sleeping, possibly atomic. */
+        mdelay(1);
+}
+
 static struct map_desc io_map __initdata = {
         .virtual = BCM2835_PERIPH_VIRT,
         .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
@@ -39,6 +83,7 @@ static void __init bcm2835_init(void)
 {
         int ret;
 
+        bcm2835_setup_restart();
         bcm2835_init_clocks();
 
         ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
@@ -60,5 +105,6 @@ DT_MACHINE_START(BCM2835, "BCM2835")
         .handle_irq = bcm2835_handle_irq,
         .init_machine = bcm2835_init,
         .timer = &bcm2835_timer,
+        .restart = bcm2835_restart,
         .dt_compat = bcm2835_compat
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/include/mach/gpio.h b/arch/arm/mach-bcm2835/include/mach/gpio.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 263242da2cb8..2d00165e85ec 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -10,7 +10,6 @@ config ARCH_AUTCPU12
 
 config ARCH_CDB89712
         bool "CDB89712"
-        select ISA
         help
           This is an evaluation board from Cirrus for the CS89712 processor.
           The board includes 2 serial ports, Ethernet, IRDA, and expansion
@@ -25,7 +24,6 @@ config ARCH_EDB7211
         bool "EDB7211"
         select ARCH_SELECT_MEMORY_MODEL
         select ARCH_SPARSEMEM_ENABLE
-        select ISA
         help
           Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
           evaluation board.
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 6da6940b3656..992995af666a 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -9,9 +9,9 @@ obj-m			:=
 obj-n                   :=
 obj-                    :=
 
-obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
-obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
-obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
-obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
-obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
-obj-$(CONFIG_ARCH_P720T)    += p720t.o
+obj-$(CONFIG_ARCH_AUTCPU12)     += board-autcpu12.o
+obj-$(CONFIG_ARCH_CDB89712)     += board-cdb89712.o
+obj-$(CONFIG_ARCH_CLEP7312)     += board-clep7312.o
+obj-$(CONFIG_ARCH_EDB7211)      += board-edb7211.o
+obj-$(CONFIG_ARCH_FORTUNET)     += board-fortunet.o
+obj-$(CONFIG_ARCH_P720T)        += board-p720t.o
diff --git a/arch/arm/mach-clps711x/Makefile.boot b/arch/arm/mach-clps711x/Makefile.boot
index 9398e859b5af..eba77d35a615 100644
--- a/arch/arm/mach-clps711x/Makefile.boot
+++ b/arch/arm/mach-clps711x/Makefile.boot
@@ -1,5 +1,4 @@
 # The standard locations for stuff on CLPS711x type processors
-   zreladdr-y                           += 0xc0028000
 params_phys-y                           := 0xc0000100
 # Should probably have some agreement on these...
 initrd_phys-$(CONFIG_ARCH_P720T)        := 0xc0400000
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
deleted file mode 100644
index 32871918bb6e..000000000000
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/autcpu12.c
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <mach/hardware.h>
-#include <asm/sizes.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-
-#include <asm/mach/map.h>
-#include <mach/autcpu12.h>
-
-#include "common.h"
-
-/*
- * The on-chip registers are given a size of 1MB so that a section can
- * be used to map them; this saves a page table.  This is the place to
- * add mappings for ROM, expansion memory, PCMCIA, etc.  (if static
- * mappings are chosen for those areas).
- *
-*/
-
-static struct map_desc autcpu12_io_desc[] __initdata = {
-        /* memory-mapped extra io and CS8900A Ethernet chip */
-        /* ethernet chip */
-        {
-                .virtual        = AUTCPU12_VIRT_CS8900A,
-                .pfn            = __phys_to_pfn(AUTCPU12_PHYS_CS8900A),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
-};
-
-void __init autcpu12_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc));
-}
-
-static struct resource autcpu12_nvram_resource[] __initdata = {
-        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-
-static struct platform_device autcpu12_nvram_pdev __initdata = {
-        .name           = "autcpu12_nvram",
-        .id             = -1,
-        .resource       = autcpu12_nvram_resource,
-        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
-};
-
-static void __init autcpu12_init(void)
-{
-        platform_device_register(&autcpu12_nvram_pdev);
-}
-
-MACHINE_START(AUTCPU12, "autronix autcpu12")
-        /* Maintainer: Thomas Gleixner */
-        .atag_offset    = 0x20000,
-        .init_machine   = autcpu12_init,
-        .map_io         = autcpu12_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
new file mode 100644
index 000000000000..3fbf43f72589
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -0,0 +1,179 @@
+/*
+ *  linux/arch/arm/mach-clps711x/autcpu12.c
+ *
+ * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand-gpio.h>
+#include <linux/platform_device.h>
+#include <linux/basic_mmio_gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/sizes.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <mach/autcpu12.h>
+
+#include "common.h"
+
+#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+
+#define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
+#define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
+
+#define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
+#define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
+#define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
+#define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
+#define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
+
+static struct resource autcpu12_cs8900_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
+        DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
+};
+
+static struct resource autcpu12_nvram_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
+};
+
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+        .name           = "autcpu12_nvram",
+        .id             = -1,
+        .resource       = autcpu12_nvram_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
+};
+
+static struct resource autcpu12_nand_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
+};
+
+static struct mtd_partition autcpu12_nand_parts[] __initdata = {
+        {
+                .name   = "Flash partition 1",
+                .offset = 0,
+                .size   = SZ_8M,
+        },
+        {
+                .name   = "Flash partition 2",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
+                                         size_t sz)
+{
+        switch (sz) {
+        case SZ_16M:
+        case SZ_32M:
+                break;
+        case SZ_64M:
+        case SZ_128M:
+                pdata->parts[0].size = SZ_16M;
+                break;
+        default:
+                pr_warn("Unsupported SmartMedia device size %u\n", sz);
+                break;
+        }
+}
+
+static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
+        .gpio_rdy       = AUTCPU12_SMC_RDY,
+        .gpio_nce       = AUTCPU12_SMC_NCE,
+        .gpio_ale       = AUTCPU12_SMC_ALE,
+        .gpio_cle       = AUTCPU12_SMC_CLE,
+        .gpio_nwp       = -1,
+        .chip_delay     = 20,
+        .parts          = autcpu12_nand_parts,
+        .num_parts      = ARRAY_SIZE(autcpu12_nand_parts),
+        .adjust_parts   = autcpu12_adjust_parts,
+};
+
+static struct platform_device autcpu12_nand_pdev __initdata = {
+        .name           = "gpio-nand",
+        .id             = -1,
+        .resource       = autcpu12_nand_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nand_resource),
+        .dev            = {
+                .platform_data = &autcpu12_nand_pdata,
+        },
+};
+
+static struct resource autcpu12_mmgpio_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
+};
+
+static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
+        .base   = AUTCPU12_MMGPIO_BASE,
+        .ngpio  = 8,
+};
+
+static struct platform_device autcpu12_mmgpio_pdev __initdata = {
+        .name           = "basic-mmio-gpio",
+        .id             = -1,
+        .resource       = autcpu12_mmgpio_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_mmgpio_resource),
+        .dev            = {
+                .platform_data = &autcpu12_mmgpio_pdata,
+        },
+};
+
+static void __init autcpu12_init(void)
+{
+        platform_device_register_simple("video-clps711x", 0, NULL, 0);
+        platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
+                                        ARRAY_SIZE(autcpu12_cs8900_resource));
+        platform_device_register(&autcpu12_mmgpio_pdev);
+        platform_device_register(&autcpu12_nvram_pdev);
+}
+
+static void __init autcpu12_init_late(void)
+{
+        if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
+                /* We are need both drivers to handle NAND */
+                platform_device_register(&autcpu12_nand_pdev);
+        }
+}
+
+MACHINE_START(AUTCPU12, "autronix autcpu12")
+        /* Maintainer: Thomas Gleixner */
+        .atag_offset    = 0x20000,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .map_io         = clps711x_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = autcpu12_init,
+        .init_late      = autcpu12_init_late,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
new file mode 100644
index 000000000000..60900ddf97c9
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -0,0 +1,147 @@
+/*
+ *  linux/arch/arm/mach-clps711x/cdb89712.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/partitions.h>
+
+#include <mach/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+
+#define CDB89712_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define CDB89712_CS8900_IRQ     (IRQ_EINT3)
+
+static struct resource cdb89712_cs8900_resource[] __initdata = {
+        DEFINE_RES_MEM(CDB89712_CS8900_BASE, SZ_1K),
+        DEFINE_RES_IRQ(CDB89712_CS8900_IRQ),
+};
+
+static struct mtd_partition cdb89712_flash_partitions[] __initdata = {
+        {
+                .name   = "Flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data cdb89712_flash_pdata __initdata = {
+        .width          = 4,
+        .probe_type     = "map_rom",
+        .parts          = cdb89712_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(cdb89712_flash_partitions),
+};
+
+static struct resource cdb89712_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(CS0_PHYS_BASE, SZ_8M),
+};
+
+static struct platform_device cdb89712_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = cdb89712_flash_resources,
+        .num_resources  = ARRAY_SIZE(cdb89712_flash_resources),
+        .dev    = {
+                .platform_data  = &cdb89712_flash_pdata,
+        },
+};
+
+static struct mtd_partition cdb89712_bootrom_partitions[] __initdata = {
+        {
+                .name   = "BootROM",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = {
+        .width          = 4,
+        .probe_type     = "map_rom",
+        .parts          = cdb89712_bootrom_partitions,
+        .nr_parts       = ARRAY_SIZE(cdb89712_bootrom_partitions),
+};
+
+static struct resource cdb89712_bootrom_resources[] __initdata = {
+        DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM |
+                         IORESOURCE_CACHEABLE | IORESOURCE_READONLY),
+};
+
+static struct platform_device cdb89712_bootrom_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 1,
+        .resource       = cdb89712_bootrom_resources,
+        .num_resources  = ARRAY_SIZE(cdb89712_bootrom_resources),
+        .dev    = {
+                .platform_data  = &cdb89712_bootrom_pdata,
+        },
+};
+
+static struct platdata_mtd_ram cdb89712_sram_pdata __initdata = {
+        .bankwidth      = 4,
+};
+
+static struct resource cdb89712_sram_resources[] __initdata = {
+        DEFINE_RES_MEM(CLPS711X_SRAM_BASE, CLPS711X_SRAM_SIZE),
+};
+
+static struct platform_device cdb89712_sram_pdev __initdata = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = cdb89712_sram_resources,
+        .num_resources  = ARRAY_SIZE(cdb89712_sram_resources),
+        .dev    = {
+                .platform_data  = &cdb89712_sram_pdata,
+        },
+};
+
+static void __init cdb89712_init(void)
+{
+        platform_device_register(&cdb89712_flash_pdev);
+        platform_device_register(&cdb89712_bootrom_pdev);
+        platform_device_register(&cdb89712_sram_pdev);
+        platform_device_register_simple("cs89x0", 0, cdb89712_cs8900_resource,
+                                        ARRAY_SIZE(cdb89712_cs8900_resource));
+}
+
+MACHINE_START(CDB89712, "Cirrus-CDB89712")
+        /* Maintainer: Ray Lehtiniemi */
+        .atag_offset    = 0x100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .map_io         = clps711x_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = cdb89712_init,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index dbc7842639dc..0b32a487183b 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -33,14 +33,14 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
         mi->bank[0].size = 0x01000000;
 }
 
-
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         /* Maintainer: Nobody */
         .atag_offset    = 0x0100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
+        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
-
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
new file mode 100644
index 000000000000..71aa5cf2c0d3
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -0,0 +1,180 @@
+/*
+ *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/memblock.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/backlight.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <mach/hardware.h>
+
+#include "common.h"
+
+#define VIDEORAM_SIZE           SZ_128K
+
+#define EDB7211_LCD_DC_DC_EN    CLPS711X_GPIO(3, 1)
+#define EDB7211_LCDEN           CLPS711X_GPIO(3, 2)
+#define EDB7211_LCDBL           CLPS711X_GPIO(3, 3)
+
+#define EDB7211_FLASH0_BASE     (CS0_PHYS_BASE)
+#define EDB7211_FLASH1_BASE     (CS1_PHYS_BASE)
+#define EDB7211_CS8900_BASE     (CS2_PHYS_BASE + 0x300)
+#define EDB7211_CS8900_IRQ      (IRQ_EINT3)
+
+static struct resource edb7211_cs8900_resource[] __initdata = {
+        DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
+        DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
+};
+
+static struct mtd_partition edb7211_flash_partitions[] __initdata = {
+        {
+                .name   = "Flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data edb7211_flash_pdata __initdata = {
+        .width          = 4,
+        .parts          = edb7211_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(edb7211_flash_partitions),
+};
+
+static struct resource edb7211_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(EDB7211_FLASH0_BASE, SZ_8M),
+        DEFINE_RES_MEM(EDB7211_FLASH1_BASE, SZ_8M),
+};
+
+static struct platform_device edb7211_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = edb7211_flash_resources,
+        .num_resources  = ARRAY_SIZE(edb7211_flash_resources),
+        .dev    = {
+                .platform_data  = &edb7211_flash_pdata,
+        },
+};
+
+static void edb7211_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
+{
+        if (power) {
+                gpio_set_value(EDB7211_LCDEN, 1);
+                udelay(100);
+                gpio_set_value(EDB7211_LCD_DC_DC_EN, 1);
+        } else {
+                gpio_set_value(EDB7211_LCD_DC_DC_EN, 0);
+                udelay(100);
+                gpio_set_value(EDB7211_LCDEN, 0);
+        }
+}
+
+static struct plat_lcd_data edb7211_lcd_power_pdata = {
+        .set_power      = edb7211_lcd_power_set,
+};
+
+static void edb7211_lcd_backlight_set_intensity(int intensity)
+{
+        gpio_set_value(EDB7211_LCDBL, intensity);
+}
+
+static struct generic_bl_info edb7211_lcd_backlight_pdata = {
+        .name                   = "lcd-backlight.0",
+        .default_intensity      = 0x01,
+        .max_intensity          = 0x01,
+        .set_bl_intensity       = edb7211_lcd_backlight_set_intensity,
+};
+
+static struct gpio edb7211_gpios[] __initconst = {
+        { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW,     "LCD DC-DC" },
+        { EDB7211_LCDEN,        GPIOF_OUT_INIT_LOW,     "LCD POWER" },
+        { EDB7211_LCDBL,        GPIOF_OUT_INIT_LOW,     "LCD BACKLIGHT" },
+};
+
+static struct map_desc edb7211_io_desc[] __initdata = {
+        {       /* Memory-mapped extra keyboard row */
+                .virtual        = IO_ADDRESS(EP7211_PHYS_EXTKBD),
+                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init edb7211_map_io(void)
+{
+        clps711x_map_io();
+        iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
+}
+
+/* Reserve screen memory region at the start of main system memory. */
+static void __init edb7211_reserve(void)
+{
+        memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
+}
+
+static void __init
+fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+        /*
+         * Bank start addresses are not present in the information
+         * passed in from the boot loader.  We could potentially
+         * detect them, but instead we hard-code them.
+         *
+         * Banks sizes _are_ present in the param block, but we're
+         * not using that information yet.
+         */
+        mi->bank[0].start = 0xc0000000;
+        mi->bank[0].size = SZ_8M;
+        mi->bank[1].start = 0xc1000000;
+        mi->bank[1].size = SZ_8M;
+        mi->nr_banks = 2;
+}
+
+static void __init edb7211_init(void)
+{
+        gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
+
+        platform_device_register(&edb7211_flash_pdev);
+        platform_device_register_data(&platform_bus, "platform-lcd", 0,
+                                      &edb7211_lcd_power_pdata,
+                                      sizeof(edb7211_lcd_power_pdata));
+        platform_device_register_data(&platform_bus, "generic-bl", 0,
+                                      &edb7211_lcd_backlight_pdata,
+                                      sizeof(edb7211_lcd_backlight_pdata));
+        platform_device_register_simple("video-clps711x", 0, NULL, 0);
+        platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
+                                        ARRAY_SIZE(edb7211_cs8900_resource));
+}
+
+MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
+        /* Maintainer: Jon McClintock */
+        .atag_offset    = VIDEORAM_SIZE + 0x100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .fixup          = fixup_edb7211,
+        .reserve        = edb7211_reserve,
+        .map_io         = edb7211_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = edb7211_init,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index 3a3f0b702cb4..7d0125580366 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -74,9 +74,11 @@ fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
 
 MACHINE_START(FORTUNET, "ARM-FortuNet")
         /* Maintainer: FortuNet Inc. */
+        .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fortunet_fixup,
         .map_io         = clps711x_map_io,
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
+        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
new file mode 100644
index 000000000000..1518fc83babd
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -0,0 +1,232 @@
+/*
+ *  linux/arch/arm/mach-clps711x/p720t.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+#include <linux/sizes.h>
+#include <linux/backlight.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand-gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/syspld.h>
+
+#include <video/platform_lcd.h>
+
+#include "common.h"
+
+#define P720T_USERLED           CLPS711X_GPIO(3, 0)
+#define P720T_NAND_CLE          CLPS711X_GPIO(4, 0)
+#define P720T_NAND_ALE          CLPS711X_GPIO(4, 1)
+#define P720T_NAND_NCE          CLPS711X_GPIO(4, 2)
+
+#define P720T_NAND_BASE         (CLPS711X_SDRAM1_BASE)
+
+static struct resource p720t_nand_resource[] __initdata = {
+        DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
+};
+
+static struct mtd_partition p720t_nand_parts[] __initdata = {
+        {
+                .name   = "Flash partition 1",
+                .offset = 0,
+                .size   = SZ_2M,
+        },
+        {
+                .name   = "Flash partition 2",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct gpio_nand_platdata p720t_nand_pdata __initdata = {
+        .gpio_rdy       = -1,
+        .gpio_nce       = P720T_NAND_NCE,
+        .gpio_ale       = P720T_NAND_ALE,
+        .gpio_cle       = P720T_NAND_CLE,
+        .gpio_nwp       = -1,
+        .chip_delay     = 15,
+        .parts          = p720t_nand_parts,
+        .num_parts      = ARRAY_SIZE(p720t_nand_parts),
+};
+
+static struct platform_device p720t_nand_pdev __initdata = {
+        .name           = "gpio-nand",
+        .id             = -1,
+        .resource       = p720t_nand_resource,
+        .num_resources  = ARRAY_SIZE(p720t_nand_resource),
+        .dev            = {
+                .platform_data = &p720t_nand_pdata,
+        },
+};
+
+static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
+{
+        if (power) {
+                PLD_LCDEN = PLD_LCDEN_EN;
+                PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+        } else {
+                PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
+                PLD_LCDEN = 0;
+        }
+}
+
+static struct plat_lcd_data p720t_lcd_power_pdata = {
+        .set_power      = p720t_lcd_power_set,
+};
+
+static void p720t_lcd_backlight_set_intensity(int intensity)
+{
+        if (intensity)
+                PLD_PWR |= PLD_S3_ON;
+        else
+                PLD_PWR = 0;
+}
+
+static struct generic_bl_info p720t_lcd_backlight_pdata = {
+        .name                   = "lcd-backlight.0",
+        .default_intensity      = 0x01,
+        .max_intensity          = 0x01,
+        .set_bl_intensity       = p720t_lcd_backlight_set_intensity,
+};
+
+/*
+ * Map the P720T system PLD. It occupies two address spaces:
+ * 0x10000000 and 0x10400000. We map both regions as one.
+ */
+static struct map_desc p720t_io_desc[] __initdata = {
+        {
+                .virtual        = SYSPLD_VIRT_BASE,
+                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
+                .length         = SZ_8M,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void __init
+fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
+{
+        /*
+         * Our bootloader doesn't setup any tags (yet).
+         */
+        if (tag->hdr.tag != ATAG_CORE) {
+                tag->hdr.tag = ATAG_CORE;
+                tag->hdr.size = tag_size(tag_core);
+                tag->u.core.flags = 0;
+                tag->u.core.pagesize = PAGE_SIZE;
+                tag->u.core.rootdev = 0x0100;
+
+                tag = tag_next(tag);
+                tag->hdr.tag = ATAG_MEM;
+                tag->hdr.size = tag_size(tag_mem32);
+                tag->u.mem.size = 4096;
+                tag->u.mem.start = PHYS_OFFSET;
+
+                tag = tag_next(tag);
+                tag->hdr.tag = ATAG_NONE;
+                tag->hdr.size = 0;
+        }
+}
+
+static void __init p720t_map_io(void)
+{
+        clps711x_map_io();
+        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
+}
+
+static void __init p720t_init_early(void)
+{
+        /*
+         * Power down as much as possible in case we don't
+         * have the drivers loaded.
+         */
+        PLD_LCDEN = 0;
+        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
+
+        PLD_KBD   = 0;
+        PLD_IO    = 0;
+        PLD_IRDA  = 0;
+        PLD_CODEC = 0;
+        PLD_TCH   = 0;
+        PLD_SPI   = 0;
+        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
+                PLD_COM2 = 0;
+                PLD_COM1 = 0;
+        }
+}
+
+static struct gpio_led p720t_gpio_leds[] = {
+        {
+                .name                   = "User LED",
+                .default_trigger        = "heartbeat",
+                .gpio                   = P720T_USERLED,
+        },
+};
+
+static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
+        .leds           = p720t_gpio_leds,
+        .num_leds       = ARRAY_SIZE(p720t_gpio_leds),
+};
+
+static void __init p720t_init(void)
+{
+        platform_device_register(&p720t_nand_pdev);
+        platform_device_register_data(&platform_bus, "platform-lcd", 0,
+                                      &p720t_lcd_power_pdata,
+                                      sizeof(p720t_lcd_power_pdata));
+        platform_device_register_data(&platform_bus, "generic-bl", 0,
+                                      &p720t_lcd_backlight_pdata,
+                                      sizeof(p720t_lcd_backlight_pdata));
+        platform_device_register_simple("video-clps711x", 0, NULL, 0);
+}
+
+static void __init p720t_init_late(void)
+{
+        platform_device_register_data(&platform_bus, "leds-gpio", 0,
+                                      &p720t_gpio_led_pdata,
+                                      sizeof(p720t_gpio_led_pdata));
+}
+
+MACHINE_START(P720T, "ARM-Prospector720T")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .atag_offset    = 0x100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .fixup          = fixup_p720t,
+        .map_io         = p720t_map_io,
+        .init_early     = p720t_init_early,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = p720t_init,
+        .init_late      = p720t_init_late,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
deleted file mode 100644
index c314f49d6ef6..000000000000
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/cdb89712.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-
-/*
- * Map the CS89712 Ethernet port.  That should be moved to the
- * ethernet driver, perhaps.
- */
-static struct map_desc cdb89712_io_desc[] __initdata = {
-        {
-                .virtual        = ETHER_BASE,
-                .pfn            =__phys_to_pfn(ETHER_START),
-                .length         = ETHER_SIZE,
-                .type           = MT_DEVICE
-        }
-};
-
-static void __init cdb89712_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(cdb89712_io_desc, ARRAY_SIZE(cdb89712_io_desc));
-}
-
-MACHINE_START(CDB89712, "Cirrus-CDB89712")
-        /* Maintainer: Ray Lehtiniemi */
-        .atag_offset    = 0x100,
-        .map_io         = cdb89712_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 509243d89a32..e046439573ee 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -21,13 +21,16 @@
  */
 #include <linux/io.h>
 #include <linux/init.h>
+#include <linux/sizes.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clockchips.h>
 #include <linux/clk-provider.h>
 
-#include <asm/sizes.h>
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
@@ -36,7 +39,6 @@
 
 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
                   *clk_tint, *clk_spi;
-static unsigned long latch;
 
 /*
  * This maps the generic CLPS711x registers
@@ -45,7 +47,7 @@ static struct map_desc clps711x_io_desc[] __initdata = {
         {
                 .virtual        = (unsigned long)CLPS711X_VIRT_BASE,
                 .pfn            = __phys_to_pfn(CLPS711X_PHYS_BASE),
-                .length         = SZ_1M,
+                .length         = SZ_64K,
                 .type           = MT_DEVICE
         }
 };
@@ -64,7 +66,7 @@ static void int1_mask(struct irq_data *d)
         clps_writel(intmr1, INTMR1);
 }
 
-static void int1_ack(struct irq_data *d)
+static void int1_eoi(struct irq_data *d)
 {
         switch (d->irq) {
         case IRQ_CSINT:  clps_writel(0, COEOI);  break;
@@ -86,7 +88,8 @@ static void int1_unmask(struct irq_data *d)
 }
 
 static struct irq_chip int1_chip = {
-        .irq_ack        = int1_ack,
+        .name           = "Interrupt Vector 1",
+        .irq_eoi        = int1_eoi,
         .irq_mask       = int1_mask,
         .irq_unmask     = int1_unmask,
 };
@@ -100,7 +103,7 @@ static void int2_mask(struct irq_data *d)
         clps_writel(intmr2, INTMR2);
 }
 
-static void int2_ack(struct irq_data *d)
+static void int2_eoi(struct irq_data *d)
 {
         switch (d->irq) {
         case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
@@ -117,73 +120,160 @@ static void int2_unmask(struct irq_data *d)
 }
 
 static struct irq_chip int2_chip = {
-        .irq_ack        = int2_ack,
+        .name           = "Interrupt Vector 2",
+        .irq_eoi        = int2_eoi,
         .irq_mask       = int2_mask,
         .irq_unmask     = int2_unmask,
 };
 
+static void int3_mask(struct irq_data *d)
+{
+        u32 intmr3;
+
+        intmr3 = clps_readl(INTMR3);
+        intmr3 &= ~(1 << (d->irq - 32));
+        clps_writel(intmr3, INTMR3);
+}
+
+static void int3_unmask(struct irq_data *d)
+{
+        u32 intmr3;
+
+        intmr3 = clps_readl(INTMR3);
+        intmr3 |= 1 << (d->irq - 32);
+        clps_writel(intmr3, INTMR3);
+}
+
+static struct irq_chip int3_chip = {
+        .name           = "Interrupt Vector 3",
+        .irq_mask       = int3_mask,
+        .irq_unmask     = int3_unmask,
+};
+
+static struct {
+        int                     nr;
+        struct irq_chip         *chip;
+        irq_flow_handler_t      handle;
+} clps711x_irqdescs[] __initdata = {
+        { IRQ_CSINT,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_EINT1,    &int1_chip,     handle_level_irq,       },
+        { IRQ_EINT2,    &int1_chip,     handle_level_irq,       },
+        { IRQ_EINT3,    &int1_chip,     handle_level_irq,       },
+        { IRQ_TC1OI,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_TC2OI,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_RTCMI,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_TINT,     &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_UTXINT1,  &int1_chip,     handle_level_irq,       },
+        { IRQ_URXINT1,  &int1_chip,     handle_level_irq,       },
+        { IRQ_UMSINT,   &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_SSEOTI,   &int1_chip,     handle_level_irq,       },
+        { IRQ_KBDINT,   &int2_chip,     handle_fasteoi_irq,     },
+        { IRQ_SS2RX,    &int2_chip,     handle_level_irq,       },
+        { IRQ_SS2TX,    &int2_chip,     handle_level_irq,       },
+        { IRQ_UTXINT2,  &int2_chip,     handle_level_irq,       },
+        { IRQ_URXINT2,  &int2_chip,     handle_level_irq,       },
+};
+
 void __init clps711x_init_irq(void)
 {
         unsigned int i;
 
-        for (i = 0; i < NR_IRQS; i++) {
-                if (INT1_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int1_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }
-                if (INT2_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int2_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-
-        /*
-         * Disable interrupts
-         */
+        /* Disable interrupts */
         clps_writel(0, INTMR1);
         clps_writel(0, INTMR2);
+        clps_writel(0, INTMR3);
 
-        /*
-         * Clear down any pending interrupts
-         */
+        /* Clear down any pending interrupts */
+        clps_writel(0, BLEOI);
+        clps_writel(0, MCEOI);
         clps_writel(0, COEOI);
         clps_writel(0, TC1EOI);
         clps_writel(0, TC2EOI);
         clps_writel(0, RTCEOI);
         clps_writel(0, TEOI);
         clps_writel(0, UMSEOI);
-        clps_writel(0, SYNCIO);
         clps_writel(0, KBDEOI);
+        clps_writel(0, SRXEOF);
+        clps_writel(0xffffffff, DAISR);
+
+        for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
+                irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
+                                         clps711x_irqdescs[i].chip,
+                                         clps711x_irqdescs[i].handle);
+                set_irq_flags(clps711x_irqdescs[i].nr,
+                              IRQF_VALID | IRQF_PROBE);
+        }
+
+        if (IS_ENABLED(CONFIG_FIQ)) {
+                init_FIQ(0);
+                irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
+                                         handle_bad_irq);
+                set_irq_flags(IRQ_DAIINT,
+                              IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
+        }
 }
 
-/*
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
+inline u32 fls16(u32 x)
 {
-        unsigned long hwticks;
-        hwticks = latch - (clps_readl(TC2D) & 0xffff);
-        return (hwticks * (tick_nsec / 1000)) / latch;
+        u32 r = 15;
+
+        if (!(x & 0xff00)) {
+                x <<= 8;
+                r -= 8;
+        }
+        if (!(x & 0xf000)) {
+                x <<= 4;
+                r -= 4;
+        }
+        if (!(x & 0xc000)) {
+                x <<= 2;
+                r -= 2;
+        }
+        if (!(x & 0x8000))
+                r--;
+
+        return r;
 }
 
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
+asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
 {
-        timer_tick();
+        u32 irqstat;
+        void __iomem *base = CLPS711X_VIRT_BASE;
+
+        irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
+        if (irqstat) {
+                handle_IRQ(fls16(irqstat), regs);
+                return;
+        }
+
+        irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
+        if (likely(irqstat))
+                handle_IRQ(fls16(irqstat) + 16, regs);
+}
+
+static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
+                                         struct clock_event_device *evt)
+{
+}
+
+static struct clock_event_device clockevent_clps711x = {
+        .name           = "CLPS711x Clockevents",
+        .rating         = 300,
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .set_mode       = clps711x_clockevent_set_mode,
+};
+
+static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
+{
+        clockevent_clps711x.event_handler(&clockevent_clps711x);
+
         return IRQ_HANDLED;
 }
 
 static struct irqaction clps711x_timer_irq = {
         .name           = "CLPS711x Timer Tick",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = p720t_timer_interrupt,
+        .handler        = clps711x_timer_interrupt,
 };
 
 static void add_fixed_clk(struct clk *clk, const char *name, int rate)
@@ -244,20 +334,19 @@ static void __init clps711x_timer_init(void)
 
         pr_info("CPU frequency set at %i Hz.\n", cpu);
 
-        latch = (timh + HZ / 2) / HZ;
+        clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
 
         tmp = clps_readl(SYSCON1);
         tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
         clps_writel(tmp, SYSCON1);
 
-        clps_writel(latch - 1, TC2D);
+        clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
 
         setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
 struct sys_timer clps711x_timer = {
         .init           = clps711x_timer_init,
-        .offset         = clps711x_gettimeoffset,
 };
 
 void clps711x_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index fc0f0650dcb5..b7c0c75c90c0 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,9 +4,14 @@
  * Common bits.
  */
 
+#define CLPS711X_NR_IRQS        (33)
+#define CLPS711X_NR_GPIO        (4 * 8 + 3)
+#define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
+
 struct sys_timer;
 
 extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
-extern struct sys_timer clps711x_timer;
+extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(char mode, const char *cmd);
+extern struct sys_timer clps711x_timer;
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
deleted file mode 100644
index 5fad0b4f40ad..000000000000
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/arch-edb7211.c
- *
- *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/memblock.h>
-#include <linux/types.h>
-#include <linux/string.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-extern void edb7211_map_io(void);
-
-/* Reserve screen memory region at the start of main system memory. */
-static void __init edb7211_reserve(void)
-{
-        memblock_reserve(PHYS_OFFSET, 0x00020000);
-}
-
-static void __init
-fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
-{
-        /*
-         * Bank start addresses are not present in the information
-         * passed in from the boot loader.  We could potentially
-         * detect them, but instead we hard-code them.
-         *
-         * Banks sizes _are_ present in the param block, but we're
-         * not using that information yet.
-         */
-        mi->bank[0].start = 0xc0000000;
-        mi->bank[0].size = 8*1024*1024;
-        mi->bank[1].start = 0xc1000000;
-        mi->bank[1].size = 8*1024*1024;
-        mi->nr_banks = 2;
-}
-
-MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
-        /* Maintainer: Jon McClintock */
-        .atag_offset    = 0x20100,      /* 0xc0000000 - 0xc001ffff can be video RAM */
-        .fixup          = fixup_edb7211,
-        .map_io         = edb7211_map_io,
-        .reserve        = edb7211_reserve,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
deleted file mode 100644
index 4372f06c9929..000000000000
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/mm.c
- *
- *  Extra MM routines for the EDB7211 board
- *
- *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bug.h>
-
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
- 
-#include <asm/mach/map.h>
-
-extern void clps711x_map_io(void);
-
-/*
- * The on-chip registers are given a size of 1MB so that a section can
- * be used to map them; this saves a page table.  This is the place to
- * add mappings for ROM, expansion memory, PCMCIA, etc.  (if static
- * mappings are chosen for those areas).
- *
- * Here is a physical memory map (to be fleshed out later):
- *
- * Physical Address  Size  Description
- * ----------------- ----- ---------------------------------
- * c0000000-c001ffff 128KB reserved for video RAM [1]
- * c0020000-c0023fff  16KB parameters (see Documentation/arm/Setup)
- * c0024000-c0027fff  16KB swapper_pg_dir (task 0 page directory)
- * c0028000-...            kernel image (TEXTADDR)
- *
- * [1] Unused pages should be given back to the VM; they are not yet.
- *     The parameter block should also be released (not sure if this
- *     happens).
- */
-static struct map_desc edb7211_io_desc[] __initdata = {
-        {       /* memory-mapped extra keyboard row */
-                .virtual        = EP7211_VIRT_EXTKBD,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        }, {    /* and CS8900A Ethernet chip */
-                .virtual        = EP7211_VIRT_CS8900A,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_CS8900A),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        }, {    /* flash banks */
-                .virtual        = EP7211_VIRT_FLASH1,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_FLASH1),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = EP7211_VIRT_FLASH2,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_FLASH2),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        }
-};
-
-void __init edb7211_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
-}
-
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index 1588a365f610..0452f5f3f034 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -21,24 +21,15 @@
 #define __ASM_ARCH_AUTCPU12_H
 
 /*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2
- * (nCS2). This is the mapping for it.
- */
-#define AUTCPU12_PHYS_CS8900A           CS2_PHYS_BASE           /* physical */
-#define AUTCPU12_VIRT_CS8900A           (0xfe000000)            /* virtual */
-
-/*
  * The flash bank is wired to chip select 0
  */
 #define AUTCPU12_PHYS_FLASH             CS0_PHYS_BASE           /* physical */
 
 /* offset for device specific information structure */
 #define AUTCPU12_LCDINFO_OFFS           (0x00010000)    
-/*
-* Videomemory is the internal SRAM (CS 6)       
-*/
+
+/* Videomemory in the internal SRAM (CS 6) */
 #define AUTCPU12_PHYS_VIDEO             CS6_PHYS_BASE
-#define AUTCPU12_VIRT_VIDEO             (0xfd000000)
 
 /*
 * All special IO's are tied to CS1
@@ -49,8 +40,6 @@
 
 #define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
 
-#define AUTCPU12_PHYS_SMC               CS1_PHYS_BASE +0x06000000  /* physical */
-
 #define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
 
 #define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
@@ -59,14 +48,6 @@
 
 #define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
 
-/* 
-* defines for smartmedia card access 
-*/
-#define AUTCPU12_SMC_RDY                (1<<2)
-#define AUTCPU12_SMC_ALE                (1<<3)
-#define AUTCPU12_SMC_CLE                (1<<4)
-#define AUTCPU12_SMC_PORT_OFFSET        PBDR
-#define AUTCPU12_SMC_SELECT_OFFSET      0x10
 /*
 * defines for lcd contrast 
 */
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index c82e21ca49c7..01d1b9559710 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -257,6 +257,9 @@
 #define MEMCFG_BUS_WIDTH_16     (0)
 #define MEMCFG_BUS_WIDTH_8      (3)
 
+#define MEMCFG_SQAEN            (1 << 6)
+#define MEMCFG_CLKENB           (1 << 7)
+
 #define MEMCFG_WAITSTATE_8_3    (0 << 2)
 #define MEMCFG_WAITSTATE_7_3    (1 << 2)
 #define MEMCFG_WAITSTATE_6_3    (2 << 2)
@@ -274,4 +277,28 @@
 #define MEMCFG_WAITSTATE_2_0    (14 << 2)
 #define MEMCFG_WAITSTATE_1_0    (15 << 2)
 
+/* INTSR1 Interrupts */
+#define IRQ_CSINT               (4)
+#define IRQ_EINT1               (5)
+#define IRQ_EINT2               (6)
+#define IRQ_EINT3               (7)
+#define IRQ_TC1OI               (8)
+#define IRQ_TC2OI               (9)
+#define IRQ_RTCMI               (10)
+#define IRQ_TINT                (11)
+#define IRQ_UTXINT1             (12)
+#define IRQ_URXINT1             (13)
+#define IRQ_UMSINT              (14)
+#define IRQ_SSEOTI              (15)
+
+/* INTSR2 Interrupts */
+#define IRQ_KBDINT              (16 + 0)
+#define IRQ_SS2RX               (16 + 1)
+#define IRQ_SS2TX               (16 + 2)
+#define IRQ_UTXINT2             (16 + 12)
+#define IRQ_URXINT2             (16 + 13)
+
+/* INTSR3 Interrupts */
+#define IRQ_DAIINT              (32 + 0)
+
 #endif /* __MACH_CLPS711X_H */
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
deleted file mode 100644
index 56e5c2c23504..000000000000
--- a/arch/arm/mach-clps711x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * arch/arm/mach-clps711x/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for CLPS711X-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
-#error INTSR stride != INTMR stride
-#endif
-
-                .macro  get_irqnr_and_base, irqnr, stat, base, mask
-                mov     \base, #CLPS711X_VIRT_BASE
-                ldr     \stat, [\base, #INTSR1]
-                ldr     \mask, [\base, #INTMR1]
-                mov     \irqnr, #4
-                mov     \mask, \mask, lsl #16
-                and     \stat, \stat, \mask, lsr #16
-                movs    \stat, \stat, lsr #4
-                bne     1001f
-
-                add     \base, \base, #INTSR2 - INTSR1
-                ldr     \stat, [\base, #INTSR1]
-                ldr     \mask, [\base, #INTMR1]
-                mov     \irqnr, #16
-                mov     \mask, \mask, lsl #16
-                and     \stat, \stat, \mask, lsr #16
-
-1001:           tst     \stat, #255
-                addeq   \irqnr, \irqnr, #8
-                moveq   \stat, \stat, lsr #8
-                tst     \stat, #15
-                addeq   \irqnr, \irqnr, #4
-                moveq   \stat, \stat, lsr #4
-                tst     \stat, #3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \stat, \stat, lsr #2
-                tst     \stat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \stat, \stat, lsr #1
-                tst     \stat, #1                       @ bit 0 should be set
-                .endm
-
-
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 8497775d6ee5..2f23dd5d73e4 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -24,7 +24,10 @@
 
 #include <mach/clps711x.h>
 
-#define CLPS711X_VIRT_BASE      IOMEM(0xff000000)
+#define IO_ADDRESS(x)           (0xdc000000 + (((x) & 0x03ffffff) | \
+                                (((x) >> 2) & 0x3c000000)))
+
+#define CLPS711X_VIRT_BASE      IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
 
 #ifndef __ASSEMBLY__
 #define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
@@ -61,67 +64,17 @@
 #define CS7_PHYS_BASE           (0x00000000)
 #endif
 
-#define SYSPLD_VIRT_BASE        0xfe000000
-#define SYSPLD_BASE             SYSPLD_VIRT_BASE
-
-#if defined (CONFIG_ARCH_CDB89712)
-
-#define ETHER_START      0x20000000
-#define ETHER_SIZE       0x1000
-#define ETHER_BASE       0xfe000000
-
-#endif
+#define CLPS711X_SRAM_BASE      CS6_PHYS_BASE
+#define CLPS711X_SRAM_SIZE      (48 * 1024)
 
+#define CLPS711X_SDRAM0_BASE    (0xc0000000)
+#define CLPS711X_SDRAM1_BASE    (0xd0000000)
 
 #if defined (CONFIG_ARCH_EDB7211)
 
-/*
- * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 
- * and repeat across it. This is the mapping for it.
- *
- * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_EXTKBD              CS3_PHYS_BASE   /* physical */
-
-#define EP7211_VIRT_EXTKBD              (0xfd000000)    /* virtual */
-
-
-/*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2 
- * (nCS2). This is the mapping for it.
- *
- * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_CS8900A             CS2_PHYS_BASE   /* physical */
-
-#define EP7211_VIRT_CS8900A             (0xfc000000)    /* virtual */
-
-
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define EP7211_PHYS_FLASH1              CS0_PHYS_BASE   /* physical */
-#define EP7211_PHYS_FLASH2              CS1_PHYS_BASE   /* physical */
-
-#define EP7211_VIRT_FLASH1              (0xfa000000)    /* virtual */
-#define EP7211_VIRT_FLASH2              (0xfb000000)    /* virtual */
+/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
+#define EP7211_PHYS_EXTKBD      CS3_PHYS_BASE
 
 #endif /* CONFIG_ARCH_EDB7211 */
 
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the EDB7211.
- */
-#define EDB_PD1_LCD_DC_DC_EN    (1<<1)
-#define EDB_PD2_LCDEN           (1<<2)
-#define EDB_PD3_LCDBL           (1<<3)
-
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h
deleted file mode 100644
index 14d215f8ca81..000000000000
--- a/arch/arm/mach-clps711x/include/mach/irqs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/irqs.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Interrupts from INTSR1
- */
-#define IRQ_CSINT                       4
-#define IRQ_EINT1                       5
-#define IRQ_EINT2                       6
-#define IRQ_EINT3                       7
-#define IRQ_TC1OI                       8
-#define IRQ_TC2OI                       9
-#define IRQ_RTCMI                       10
-#define IRQ_TINT                        11
-#define IRQ_UTXINT1                     12
-#define IRQ_URXINT1                     13
-#define IRQ_UMSINT                      14
-#define IRQ_SSEOTI                      15
-
-#define INT1_IRQS                       (0x0000fff0)
-
-/*
- * Interrupts from INTSR2
- */
-#define IRQ_KBDINT                      (16+0)  /* bit 0 */
-#define IRQ_SS2RX                       (16+1)  /* bit 1 */
-#define IRQ_SS2TX                       (16+2)  /* bit 2 */
-#define IRQ_UTXINT2                     (16+12) /* bit 12 */
-#define IRQ_URXINT2                     (16+13) /* bit 13 */
-
-#define INT2_IRQS                       (0x30070000)
-
-#define NR_IRQS                         30
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
index f7f4c1201898..9a433155bf58 100644
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ b/arch/arm/mach-clps711x/include/mach/syspld.h
@@ -23,14 +23,9 @@
 #define __ASM_ARCH_SYSPLD_H
 
 #define SYSPLD_PHYS_BASE        (0x10000000)
+#define SYSPLD_VIRT_BASE        IO_ADDRESS(SYSPLD_PHYS_BASE)
 
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-#define SYSPLD_REG(type,off)    (*(volatile type *)(SYSPLD_BASE + off))
-#else
-#define SYSPLD_REG(type,off)    (off)
-#endif
+#define SYSPLD_REG(type, off)   (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
 
 #define PLD_INT         SYSPLD_REG(u32, 0x000000)
 #define PLD_INT_PENIRQ          (1 << 5)
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
deleted file mode 100644
index b752b586fc2f..000000000000
--- a/arch/arm/mach-clps711x/p720t.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/p720t.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/sizes.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/syspld.h>
-
-#include <asm/hardware/clps7111.h>
-
-#include "common.h"
-
-/*
- * Map the P720T system PLD.  It occupies two address spaces:
- *  SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
- * We map both here.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
-        {
-                .virtual        = SYSPLD_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = 0xfe400000,
-                .pfn            = __phys_to_pfn(0x10400000),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
-};
-
-static void __init
-fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
-{
-        /*
-         * Our bootloader doesn't setup any tags (yet).
-         */
-        if (tag->hdr.tag != ATAG_CORE) {
-                tag->hdr.tag = ATAG_CORE;
-                tag->hdr.size = tag_size(tag_core);
-                tag->u.core.flags = 0;
-                tag->u.core.pagesize = PAGE_SIZE;
-                tag->u.core.rootdev = 0x0100;
-
-                tag = tag_next(tag);
-                tag->hdr.tag = ATAG_MEM;
-                tag->hdr.size = tag_size(tag_mem32);
-                tag->u.mem.size = 4096;
-                tag->u.mem.start = PHYS_OFFSET;
-
-                tag = tag_next(tag);
-                tag->hdr.tag = ATAG_NONE;
-                tag->hdr.size = 0;
-        }
-}
-
-static void __init p720t_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-
-static void __init p720t_init_early(void)
-{
-        /*
-         * Power down as much as possible in case we don't
-         * have the drivers loaded.
-         */
-        PLD_LCDEN = 0;
-        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-
-        PLD_KBD   = 0;
-        PLD_IO    = 0;
-        PLD_IRDA  = 0;
-        PLD_CODEC = 0;
-        PLD_TCH   = 0;
-        PLD_SPI   = 0;
-        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
-                PLD_COM2 = 0;
-                PLD_COM1 = 0;
-        }
-}
-
-/*
- * LED controled by CPLD
- */
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-static void p720t_led_set(struct led_classdev *cdev,
-                              enum led_brightness b)
-{
-        u8 reg = clps_readb(PDDR);
-
-        if (b != LED_OFF)
-                reg |= 0x1;
-        else
-                reg &= ~0x1;
-
-        clps_writeb(reg, PDDR);
-}
-
-static enum led_brightness p720t_led_get(struct led_classdev *cdev)
-{
-        u8 reg = clps_readb(PDDR);
-
-        return (reg & 0x1) ? LED_FULL : LED_OFF;
-}
-
-static int __init p720t_leds_init(void)
-{
-
-        struct led_classdev *cdev;
-        int ret;
-
-        if (!machine_is_p720t())
-                return -ENODEV;
-
-        cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
-        if (!cdev)
-                return -ENOMEM;
-
-        cdev->name = "p720t:0";
-        cdev->brightness_set = p720t_led_set;
-        cdev->brightness_get = p720t_led_get;
-        cdev->default_trigger = "heartbeat";
-
-        ret = led_classdev_register(NULL, cdev);
-        if (ret < 0) {
-                kfree(cdev);
-                return ret;
-        }
-
-        return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(p720t_leds_init);
-#endif
-
-MACHINE_START(P720T, "ARM-Prospector720T")
-        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .atag_offset    = 0x100,
-        .fixup          = fixup_p720t,
-        .init_early     = p720t_init_early,
-        .map_io         = p720t_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 88ebea89abdf..cdf8d0746e79 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
         if (IS_ERR(aemif))
                 WARN("%s: unable to get AEMIF clock\n", __func__);
         else
-                clk_enable(aemif);
+                clk_prepare_enable(aemif);
 
         platform_add_devices(davinci_evm_devices,
                              ARRAY_SIZE(davinci_evm_devices));
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 2f88103c6459..d41954507fc2 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
         if (IS_ERR(aemif))
                 WARN("%s: unable to get AEMIF clock\n", __func__);
         else
-                clk_enable(aemif);
+                clk_prepare_enable(aemif);
 
         platform_add_devices(davinci_leopard_devices,
                              ARRAY_SIZE(davinci_leopard_devices));
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 1b4a8adcfdc9..5d49c75388ca 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -478,7 +478,7 @@ static void __init evm_init_cpld(void)
         aemif_clk = clk_get(NULL, "aemif");
         if (IS_ERR(aemif_clk))
                 return;
-        clk_enable(aemif_clk);
+        clk_prepare_enable(aemif_clk);
 
         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
                         "cpld") == NULL)
@@ -489,7 +489,7 @@ static void __init evm_init_cpld(void)
                                 SECTION_SIZE);
 fail:
                 pr_err("ERROR: can't map CPLD\n");
-                clk_disable(aemif_clk);
+                clk_disable_unprepare(aemif_clk);
                 return;
         }
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index f8a99ee6bffc..f5e018de7fa5 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -777,7 +777,7 @@ static __init void davinci_evm_init(void)
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         aemif_clk = clk_get(NULL, "aemif");
-        clk_enable(aemif_clk);
+        clk_prepare_enable(aemif_clk);
 
         if (HAS_ATA) {
                 if (HAS_NAND || HAS_NOR)
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 144bf31d68dd..3e3e3afebf88 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -188,7 +188,7 @@ static __init void davinci_ntosd2_init(void)
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         aemif_clk = clk_get(NULL, "aemif");
-        clk_enable(aemif_clk);
+        clk_prepare_enable(aemif_clk);
 
         if (HAS_ATA) {
                 if (HAS_NAND)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b90c172d5541..68c5fe01857c 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -212,6 +212,12 @@ static struct clk tptc2_clk = {
         .flags          = ALWAYS_ENABLED,
 };
 
+static struct clk pruss_clk = {
+        .name           = "pruss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_PRUSS,
+};
+
 static struct clk uart0_clk = {
         .name           = "uart0",
         .parent         = &pll0_sysclk2,
@@ -385,6 +391,7 @@ static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "tptc1",        &tptc1_clk),
         CLK(NULL,               "tpcc1",        &tpcc1_clk),
         CLK(NULL,               "tptc2",        &tptc2_clk),
+        CLK("pruss_uio",        "pruss",        &pruss_clk),
         CLK(NULL,               "uart0",        &uart0_clk),
         CLK(NULL,               "uart1",        &uart1_clk),
         CLK(NULL,               "uart2",        &uart2_clk),
@@ -781,12 +788,6 @@ static struct map_desc da850_io_desc[] = {
                 .length         = DA8XX_CP_INTC_SIZE,
                 .type           = MT_DEVICE
         },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
-                .length         = SZ_8K,
-                .type           = MT_DEVICE
-        },
 };
 
 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
@@ -1239,8 +1240,8 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
         .gpio_irq               = IRQ_DA8XX_GPIO0,
         .serial_dev             = &da8xx_serial_device,
         .emac_pdata             = &da8xx_emac_pdata,
-        .sram_dma               = DA8XX_ARM_RAM_BASE,
-        .sram_len               = SZ_8K,
+        .sram_dma               = DA8XX_SHARED_RAM_BASE,
+        .sram_len               = SZ_128K,
 };
 
 void __init da850_init(void)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bd2f72b414bc..46c9a0c09ae5 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -22,6 +22,7 @@
 #include <mach/time.h>
 #include <mach/da8xx.h>
 #include <mach/cpuidle.h>
+#include <mach/sram.h>
 
 #include "clock.h"
 #include "asp.h"
@@ -32,6 +33,7 @@
 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
 #define DA8XX_I2C0_BASE                 0x01c22000
 #define DA8XX_RTC_BASE                  0x01c23000
+#define DA8XX_PRUSS_MEM_BASE            0x01c30000
 #define DA8XX_MMCSD0_BASE               0x01c40000
 #define DA8XX_SPI0_BASE                 0x01c41000
 #define DA830_SPI1_BASE                 0x01e12000
@@ -518,6 +520,75 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
         }
 }
 
+static struct resource da8xx_pruss_resources[] = {
+        {
+                .start  = DA8XX_PRUSS_MEM_BASE,
+                .end    = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT0,
+                .end    = IRQ_DA8XX_EVTOUT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT1,
+                .end    = IRQ_DA8XX_EVTOUT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT2,
+                .end    = IRQ_DA8XX_EVTOUT2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT3,
+                .end    = IRQ_DA8XX_EVTOUT3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT4,
+                .end    = IRQ_DA8XX_EVTOUT4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT5,
+                .end    = IRQ_DA8XX_EVTOUT5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT6,
+                .end    = IRQ_DA8XX_EVTOUT6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT7,
+                .end    = IRQ_DA8XX_EVTOUT7,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
+        .pintc_base     = 0x4000,
+};
+
+static struct platform_device da8xx_uio_pruss_dev = {
+        .name           = "pruss_uio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(da8xx_pruss_resources),
+        .resource       = da8xx_pruss_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &da8xx_uio_pruss_pdata,
+        }
+};
+
+int __init da8xx_register_uio_pruss(void)
+{
+        da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
+        return platform_device_register(&da8xx_uio_pruss_dev);
+}
+
 static const struct display_panel disp_panel = {
         QVGA,
         16,
@@ -900,7 +971,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
         if (IS_ERR(da850_sata_clk))
                 return PTR_ERR(da850_sata_clk);
 
-        ret = clk_enable(da850_sata_clk);
+        ret = clk_prepare_enable(da850_sata_clk);
         if (ret)
                 goto err0;
 
@@ -931,7 +1002,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
         return 0;
 
 err1:
-        clk_disable(da850_sata_clk);
+        clk_disable_unprepare(da850_sata_clk);
 err0:
         clk_put(da850_sata_clk);
         return ret;
@@ -939,7 +1010,7 @@ err0:
 
 static void da850_sata_exit(struct device *dev)
 {
-        clk_disable(da850_sata_clk);
+        clk_disable_unprepare(da850_sata_clk);
         clk_put(da850_sata_clk);
 }
 
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a255434908db..b49c3b77d55e 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -758,12 +758,6 @@ static struct map_desc dm355_io_desc[] = {
                 .length         = IO_SIZE,
                 .type           = MT_DEVICE
         },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00010000),
-                .length         = SZ_32K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b680c832e0ba..6c3980540be0 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -985,12 +985,6 @@ static struct map_desc dm365_io_desc[] = {
                 .length         = IO_SIZE,
                 .type           = MT_DEVICE
         },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00010000),
-                .length         = SZ_32K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 
 static struct resource dm365_ks_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 14e9947bad6e..11c79a3362ef 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -785,12 +785,6 @@ static struct map_desc dm644x_io_desc[] = {
                 .length         = IO_SIZE,
                 .type           = MT_DEVICE
         },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00008000),
-                .length         = SZ_16K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 97c0f8e555bd..ac7b431c4c8e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -756,12 +756,6 @@ static struct map_desc dm646x_io_desc[] = {
                 .length         = IO_SIZE,
                 .type           = MT_DEVICE
         },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00010000),
-                .length         = SZ_32K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index bdc4aa8e672a..046c7238a3d6 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -104,8 +104,6 @@ int davinci_pm_init(void);
 static inline int davinci_pm_init(void) { return 0; }
 #endif
 
-/* standard place to map on-chip SRAMs; they *may* support DMA */
-#define SRAM_VIRT       0xfffe0000
 #define SRAM_SIZE       SZ_128K
 
 #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index aaccdc4528fc..700d311c6854 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -26,6 +26,7 @@
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
 #include <linux/platform_data/spi-davinci.h>
+#include <linux/platform_data/uio_pruss.h>
 
 #include <media/davinci/vpif_types.h>
 
@@ -72,6 +73,7 @@ extern unsigned int da850_max_speed;
 #define DA8XX_AEMIF_CS2_BASE    0x60000000
 #define DA8XX_AEMIF_CS3_BASE    0x62000000
 #define DA8XX_AEMIF_CTL_BASE    0x68000000
+#define DA8XX_SHARED_RAM_BASE   0x80000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 
 void __init da830_init(void);
@@ -86,6 +88,7 @@ int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
 int da8xx_register_emac(void);
+int da8xx_register_uio_pruss(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 int da850_register_mmcsd1(struct davinci_mmc_config *config);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 86a01fa6d3fe..62ad300440f5 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -43,6 +43,7 @@ struct davinci_uart_config {
 };
 
 extern int davinci_serial_init(struct davinci_uart_config *);
+extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
 #endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
index 111f7cc71e07..4e5db56218b8 100644
--- a/arch/arm/mach-davinci/include/mach/sram.h
+++ b/arch/arm/mach-davinci/include/mach/sram.h
@@ -24,4 +24,7 @@
 extern void *sram_alloc(size_t len, dma_addr_t *dma);
 extern void sram_free(void *addr, size_t len);
 
+/* Get the struct gen_pool * for use in platform data */
+extern struct gen_pool *sram_get_gen_pool(void);
+
 #endif /* __MACH_SRAM_H */
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 1875740fe27c..f2625814c3c9 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -70,11 +70,33 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
                                  UART_DM646X_SCR_TX_WATERMARK);
 }
 
-int __init davinci_serial_init(struct davinci_uart_config *info)
+/* Enable UART clock and obtain its rate */
+int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
 {
-        int i;
         char name[16];
-        struct clk *uart_clk;
+        struct clk *clk;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        struct device *dev = &soc_info->serial_dev->dev;
+
+        sprintf(name, "uart%d", instance);
+        clk = clk_get(dev, name);
+        if (IS_ERR(clk)) {
+                pr_err("%s:%d: failed to get UART%d clock\n",
+                                        __func__, __LINE__, instance);
+                return PTR_ERR(clk);
+        }
+
+        clk_prepare_enable(clk);
+
+        if (rate)
+                *rate = clk_get_rate(clk);
+
+        return 0;
+}
+
+int __init davinci_serial_init(struct davinci_uart_config *info)
+{
+        int i, ret;
         struct davinci_soc_info *soc_info = &davinci_soc_info;
         struct device *dev = &soc_info->serial_dev->dev;
         struct plat_serial8250_port *p = dev->platform_data;
@@ -87,16 +109,9 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
                 if (!(info->enabled_uarts & (1 << i)))
                         continue;
 
-                sprintf(name, "uart%d", i);
-                uart_clk = clk_get(dev, name);
-                if (IS_ERR(uart_clk)) {
-                        printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
-                                        __func__, __LINE__, i);
+                ret = davinci_serial_setup_clk(i, &p->uartclk);
+                if (ret)
                         continue;
-                }
-
-                clk_enable(uart_clk);
-                p->uartclk = clk_get_rate(uart_clk);
 
                 if (!p->membase && p->mapbase) {
                         p->membase = ioremap(p->mapbase, SZ_4K);
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index db0f7787faf1..c5f7ee5cc80a 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -10,6 +10,7 @@
  */
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/genalloc.h>
 
 #include <mach/common.h>
@@ -17,6 +18,11 @@
 
 static struct gen_pool *sram_pool;
 
+struct gen_pool *sram_get_gen_pool(void)
+{
+        return sram_pool;
+}
+
 void *sram_alloc(size_t len, dma_addr_t *dma)
 {
         unsigned long vaddr;
@@ -32,7 +38,7 @@ void *sram_alloc(size_t len, dma_addr_t *dma)
                 return NULL;
 
         if (dma)
-                *dma = dma_base + (vaddr - SRAM_VIRT);
+                *dma = gen_pool_virt_to_phys(sram_pool, vaddr);
         return (void *)vaddr;
 
 }
@@ -53,8 +59,10 @@ EXPORT_SYMBOL(sram_free);
  */
 static int __init sram_init(void)
 {
+        phys_addr_t phys = davinci_soc_info.sram_dma;
         unsigned len = davinci_soc_info.sram_len;
         int status = 0;
+        void *addr;
 
         if (len) {
                 len = min_t(unsigned, len, SRAM_SIZE);
@@ -62,8 +70,17 @@ static int __init sram_init(void)
                 if (!sram_pool)
                         status = -ENOMEM;
         }
-        if (sram_pool)
-                status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
+
+        if (sram_pool) {
+                addr = ioremap(phys, len);
+                if (!addr)
+                        return -ENOMEM;
+                status = gen_pool_add_virt(sram_pool, (unsigned)addr,
+                                           phys, len, -1);
+                if (status < 0)
+                        iounmap(addr);
+        }
+
         WARN_ON(status < 0);
         return status;
 }
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 75da315b6587..9847938785ca 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
 
         timer_clk = clk_get(NULL, "timer0");
         BUG_ON(IS_ERR(timer_clk));
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
 
         /* init timer hw */
         timer_init();
@@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
         wd_clk = clk_get(&pdev->dev, NULL);
         if (WARN_ON(IS_ERR(wd_clk)))
                 return;
-        clk_enable(wd_clk);
+        clk_prepare_enable(wd_clk);
 
         /* disable, internal clock source */
         __raw_writel(0, base + TCR);
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 69d10373a410..070c7b6d3d86 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -67,6 +67,15 @@ config SOC_EXYNOS5250
         help
           Enable EXYNOS5250 SoC support
 
+config SOC_EXYNOS5440
+        bool "SAMSUNG EXYNOS5440"
+        default y
+        depends on ARCH_EXYNOS5
+        select ARM_ARCH_TIMER
+        select AUTO_ZRELADDR
+        help
+          Enable EXYNOS5440 SoC support
+
 config EXYNOS4_MCT
         bool
         default y
@@ -412,9 +421,9 @@ config MACH_EXYNOS4_DT
 
 config MACH_EXYNOS5_DT
         bool "SAMSUNG EXYNOS5 Machine using device tree"
+        default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
-        select SOC_EXYNOS5250
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 0c74bdc6b698..66135eedf491 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,9 +14,9 @@ obj-				:=
 
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
 obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_ARCH_EXYNOS5)      += clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
+obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 0dbee7fef9bd..e05f6cca2c9b 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -18,6 +18,7 @@
 #include <linux/sched.h>
 #include <linux/serial_core.h>
 #include <linux/of.h>
+#include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
@@ -58,9 +59,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5440[] = "EXYNOS5440";
 
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
+static void exynos5440_map_io(void);
 static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
@@ -98,6 +101,12 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init_clocks    = exynos5_init_clocks,
                 .init           = exynos_init,
                 .name           = name_exynos5250,
+        }, {
+                .idcode         = EXYNOS5440_SOC_ID,
+                .idmask         = EXYNOS5_SOC_MASK,
+                .map_io         = exynos5440_map_io,
+                .init           = exynos_init,
+                .name           = name_exynos5440,
         },
 };
 
@@ -112,6 +121,17 @@ static struct map_desc exynos_iodesc[] __initdata = {
         },
 };
 
+#ifdef CONFIG_ARCH_EXYNOS5
+static struct map_desc exynos5440_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+#endif
+
 static struct map_desc exynos4_iodesc[] __initdata = {
         {
                 .virtual        = (unsigned long)S3C_VA_SYS,
@@ -263,6 +283,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
         },
 };
 
+static struct map_desc exynos5440_iodesc0[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        },
+};
+
 void exynos4_restart(char mode, const char *cmd)
 {
         __raw_writel(0x1, S5P_SWRESET);
@@ -270,11 +299,29 @@ void exynos4_restart(char mode, const char *cmd)
 
 void exynos5_restart(char mode, const char *cmd)
 {
-        __raw_writel(0x1, EXYNOS_SWRESET);
+        u32 val;
+        void __iomem *addr;
+
+        if (of_machine_is_compatible("samsung,exynos5250")) {
+                val = 0x1;
+                addr = EXYNOS_SWRESET;
+        } else if (of_machine_is_compatible("samsung,exynos5440")) {
+                val = (0x10 << 20) | (0x1 << 16);
+                addr = EXYNOS5440_SWRESET;
+        } else {
+                pr_err("%s: cannot support non-DT\n", __func__);
+                return;
+        }
+
+        __raw_writel(val, addr);
 }
 
 void __init exynos_init_late(void)
 {
+        if (of_machine_is_compatible("samsung,exynos5440"))
+                /* to be supported later */
+                return;
+
         exynos_pm_late_initcall();
 }
 
@@ -286,8 +333,20 @@ void __init exynos_init_late(void)
 
 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 {
+        struct map_desc *iodesc = exynos_iodesc;
+        int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
+#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
+        unsigned long root = of_get_flat_dt_root();
+
         /* initialize the io descriptors we need for initialization */
-        iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+        if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
+                iodesc = exynos5440_iodesc;
+                iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
+        }
+#endif
+
+        iotable_init(iodesc, iodesc_sz);
+
         if (mach_desc)
                 iotable_init(mach_desc, size);
 
@@ -356,6 +415,11 @@ static void __init exynos4_init_clocks(int xtal)
         exynos4_setup_clocks();
 }
 
+static void __init exynos5440_map_io(void)
+{
+        iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
+}
+
 static void __init exynos5_init_clocks(int xtal)
 {
         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -572,8 +636,9 @@ static int __init combiner_of_init(struct device_node *np,
         return 0;
 }
 
-static const struct of_device_id exynos4_dt_irq_match[] = {
+static const struct of_device_id exynos_dt_irq_match[] = {
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
         { .compatible = "samsung,exynos4210-combiner",
                         .data = combiner_of_init, },
         {},
@@ -590,7 +655,7 @@ void __init exynos4_init_irq(void)
                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
         else
-                of_irq_init(exynos4_dt_irq_match);
+                of_irq_init(exynos_dt_irq_match);
 #endif
 
         if (!of_have_populated_dt())
@@ -607,7 +672,7 @@ void __init exynos4_init_irq(void)
 void __init exynos5_init_irq(void)
 {
 #ifdef CONFIG_OF
-        of_irq_init(exynos4_dt_irq_match);
+        of_irq_init(exynos_dt_irq_match);
 #endif
         /*
          * The parameters of s5p_init_irq() are for VIC init.
@@ -637,7 +702,7 @@ static int __init exynos4_l2x0_cache_init(void)
 {
         int ret;
 
-        if (soc_is_exynos5250())
+        if (soc_is_exynos5250() || soc_is_exynos5440())
                 return 0;
 
         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
@@ -968,6 +1033,8 @@ static int __init exynos_init_irq_eint(void)
                 }
         }
 #endif
+        if (soc_is_exynos5440())
+                return 0;
 
         if (soc_is_exynos5250())
                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 6da31152de3a..e0f0ae3e0cf9 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -328,6 +328,11 @@
 #define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
 #define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
 
+/* EXYNOS5440 */
+
+#define EXYNOS5440_IRQ_UART0            IRQ_SPI(2)
+#define EXYNOS5440_IRQ_UART1            IRQ_SPI(3)
+
 #define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
 
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 872840b2ff45..61b74e12d12b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -53,6 +53,7 @@
 #define EXYNOS4_PA_ONENAND_DMA          0x0C600000
 
 #define EXYNOS_PA_CHIPID                0x10000000
+#define EXYNOS5440_PA_CHIPID            0x00160000
 
 #define EXYNOS4_PA_SYSCON               0x10010000
 #define EXYNOS5_PA_SYSCON               0x10050100
@@ -281,6 +282,10 @@
 #define EXYNOS5_PA_UART2                0x12C20000
 #define EXYNOS5_PA_UART3                0x12C30000
 
+#define EXYNOS5440_PA_UART0             0x000B0000
+#define EXYNOS5440_PA_UART1             0x000C0000
+#define EXYNOS5440_SZ_UART              SZ_256
+
 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 70b2795f5283..84428e72cf5e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
 
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
 #define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
+#define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
 
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index eadf4b59e7d2..6df99c06419d 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -77,6 +77,7 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
                                 "exynos4210-spi.2", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
         {},
 };
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8eacf28..f1326be80b91 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -10,6 +10,7 @@
 */
 
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
 
 #include <asm/mach/arch.h>
@@ -75,20 +76,35 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
         {},
 };
 
-static void __init exynos5250_dt_map_io(void)
+static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
+                                "exynos4210-uart.0", NULL),
+        {},
+};
+
+static void __init exynos5_dt_map_io(void)
 {
+        unsigned long root = of_get_flat_dt_root();
+
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+
+        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
+                s3c24xx_init_clocks(24000000);
 }
 
-static void __init exynos5250_dt_machine_init(void)
+static void __init exynos5_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos5250_auxdata_lookup, NULL);
+        if (of_machine_is_compatible("samsung,exynos5250"))
+                of_platform_populate(NULL, of_default_bus_match_table,
+                                     exynos5250_auxdata_lookup, NULL);
+        else if (of_machine_is_compatible("samsung,exynos5440"))
+                of_platform_populate(NULL, of_default_bus_match_table,
+                                     exynos5440_auxdata_lookup, NULL);
 }
 
-static char const *exynos5250_dt_compat[] __initdata = {
+static char const *exynos5_dt_compat[] __initdata = {
         "samsung,exynos5250",
+        "samsung,exynos5440",
         NULL
 };
 
@@ -96,11 +112,11 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         .init_irq       = exynos5_init_irq,
         .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos5250_dt_map_io,
+        .map_io         = exynos5_dt_map_io,
         .handle_irq     = gic_handle_irq,
-        .init_machine   = exynos5250_dt_machine_init,
+        .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
         .timer          = &exynos4_timer,
-        .dt_compat      = exynos5250_dt_compat,
+        .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8a408b..57668eb68e75 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -19,7 +19,9 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/percpu.h>
+#include <linux/of.h>
 
+#include <asm/arch_timer.h>
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 
@@ -476,8 +478,13 @@ static void __init exynos4_timer_resources(void)
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
-static void __init exynos4_timer_init(void)
+static void __init exynos_timer_init(void)
 {
+        if (soc_is_exynos5440()) {
+                arch_timer_of_register();
+                return;
+        }
+
         if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
                 mct_int_type = MCT_INT_SPI;
         else
@@ -489,5 +496,5 @@ static void __init exynos4_timer_init(void)
 }
 
 struct sys_timer exynos4_timer = {
-        .init           = exynos4_timer_init,
+        .init           = exynos_timer_init,
 };
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index f93d820ecab5..4ca8ff14a5bf 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -36,8 +36,22 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-                                S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline void __iomem *cpu_boot_reg_base(void)
+{
+        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+                return S5P_INFORM5;
+        return S5P_VA_SYSRAM;
+}
+
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+        void __iomem *boot_reg;
+
+        boot_reg = cpu_boot_reg_base();
+        if (soc_is_exynos4412())
+                boot_reg += 4*cpu;
+        return boot_reg;
+}
 
 /*
  * Write pen_release in a way that is guaranteed to be visible to all
@@ -84,6 +98,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
 static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
+        unsigned long phys_cpu = cpu_logical_map(cpu);
 
         /*
          * Set synchronisation state between this boot processor
@@ -99,7 +114,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
          * Note that "pen_release" is the hardware CPU ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        write_pen_release(cpu_logical_map(cpu));
+        write_pen_release(phys_cpu);
 
         if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
                 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
@@ -133,7 +148,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
                 smp_rmb();
 
                 __raw_writel(virt_to_phys(exynos4_secondary_startup),
-                        CPU1_BOOT_REG);
+                                                        cpu_boot_reg(phys_cpu));
                 gic_raise_softirq(cpumask_of(cpu), 0);
 
                 if (pen_release == -1)
@@ -181,6 +196,8 @@ static void __init exynos_smp_init_cpus(void)
 
 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
+        int i;
+
         if (!soc_is_exynos5250())
                 scu_enable(scu_base_addr());
 
@@ -190,8 +207,9 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        __raw_writel(virt_to_phys(exynos4_secondary_startup),
-                        CPU1_BOOT_REG);
+        for (i = 1; i < max_cpus; ++i)
+                __raw_writel(virt_to_phys(exynos4_secondary_startup),
+                                        cpu_boot_reg(cpu_logical_map(i)));
 }
 
 struct smp_operations exynos_smp_ops __initdata = {
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index 5700f23629f7..e2d9dfbf102c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -20,7 +20,7 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        if (soc_is_exynos5250())
+        if (soc_is_exynos5250() || soc_is_exynos5440())
                 /* will be implemented with gpio function */
                 return;
 
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0e1d0a42a3ea..551c97e87a78 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_HIGHBANK
-        bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
+        bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_AMBA
         select ARM_GIC
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 3ec8bdd25d09..8a1ef576d79f 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -3,7 +3,6 @@ obj-y					:= highbank.o system.o smc.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
 
-obj-$(CONFIG_DEBUG_HIGHBANK_UART)       += lluart.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_PM_SLEEP)                  += pm.o
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 286ec82a4f63..80235b46cb58 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,12 +1,10 @@
+#ifndef __HIGHBANK_CORE_H
+#define __HIGHBANK_CORE_H
+
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void highbank_clocks_init(void);
 extern void highbank_restart(char, const char *);
 extern void __iomem *scu_base_addr;
-#ifdef CONFIG_DEBUG_HIGHBANK_UART
-extern void highbank_lluart_map_io(void);
-#else
-static inline void highbank_lluart_map_io(void) {}
-#endif
 
 #ifdef CONFIG_PM_SLEEP
 extern void highbank_pm_init(void);
@@ -18,3 +16,5 @@ extern void highbank_smc1(int fn, int arg);
 extern void highbank_cpu_die(unsigned int cpu);
 
 extern struct smp_operations highbank_smp_ops;
+
+#endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 40e36a50304c..dc248167d206 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -26,9 +26,9 @@
 #include <linux/smp.h>
 #include <linux/amba/bus.h>
 
+#include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
@@ -42,16 +42,7 @@
 #include "sysregs.h"
 
 void __iomem *sregs_base;
-
-#define HB_SCU_VIRT_BASE        0xfee00000
-void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
-
-static struct map_desc scu_io_desc __initdata = {
-        .virtual        = HB_SCU_VIRT_BASE,
-        .pfn            = 0, /* run-time */
-        .length         = SZ_4K,
-        .type           = MT_DEVICE,
-};
+void __iomem *scu_base_addr;
 
 static void __init highbank_scu_map_io(void)
 {
@@ -60,14 +51,7 @@ static void __init highbank_scu_map_io(void)
         /* Get SCU base */
         asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
 
-        scu_io_desc.pfn = __phys_to_pfn(base);
-        iotable_init(&scu_io_desc, 1);
-}
-
-static void __init highbank_map_io(void)
-{
-        highbank_scu_map_io();
-        highbank_lluart_map_io();
+        scu_base_addr = ioremap(base, SZ_4K);
 }
 
 #define HB_JUMP_TABLE_PHYS(cpu)         (0x40 + (0x10 * (cpu)))
@@ -83,6 +67,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
 }
 
 const static struct of_device_id irq_match[] = {
+        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
         {}
 };
@@ -99,6 +84,9 @@ static void __init highbank_init_irq(void)
 {
         of_irq_init(irq_match);
 
+        if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
+                highbank_scu_map_io();
+
 #ifdef CONFIG_CACHE_L2X0
         /* Enable PL310 L2 Cache controller */
         highbank_smc1(0x102, 0x1);
@@ -136,6 +124,9 @@ static void __init highbank_timer_init(void)
         sp804_clockevents_init(timer_base, irq, "timer0");
 
         twd_local_timer_of_register();
+
+        arch_timer_of_register();
+        arch_timer_sched_clock_init();
 }
 
 static struct sys_timer highbank_timer = {
@@ -145,7 +136,6 @@ static struct sys_timer highbank_timer = {
 static void highbank_power_off(void)
 {
         hignbank_set_pwr_shutdown();
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
 
         while (1)
                 cpu_do_idle();
@@ -211,12 +201,13 @@ static void __init highbank_init(void)
 
 static const char *highbank_match[] __initconst = {
         "calxeda,highbank",
+        "calxeda,ecx-2000",
         NULL,
 };
 
 DT_MACHINE_START(HIGHBANK, "Highbank")
         .smp            = smp_ops(highbank_smp_ops),
-        .map_io         = highbank_map_io,
+        .map_io         = debug_ll_io_init,
         .init_irq       = highbank_init_irq,
         .timer          = &highbank_timer,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
index 2c1b8c3c8e45..7b60faccd551 100644
--- a/arch/arm/mach-highbank/hotplug.c
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -14,13 +14,11 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
 
-#include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 
 #include "core.h"
+#include "sysregs.h"
 
 extern void secondary_startup(void);
 
@@ -33,7 +31,7 @@ void __ref highbank_cpu_die(unsigned int cpu)
         flush_cache_all();
 
         highbank_set_cpu_jump(cpu, secondary_startup);
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        highbank_set_core_pwr();
 
         cpu_do_idle();
 
diff --git a/arch/arm/mach-highbank/lluart.c b/arch/arm/mach-highbank/lluart.c
deleted file mode 100644
index 371575019f33..000000000000
--- a/arch/arm/mach-highbank/lluart.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2011 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <asm/mach/map.h>
-
-#define HB_DEBUG_LL_PHYS_BASE   0xfff36000
-#define HB_DEBUG_LL_VIRT_BASE   0xfee36000
-
-static struct map_desc lluart_io_desc __initdata = {
-        .virtual        = HB_DEBUG_LL_VIRT_BASE,
-        .pfn            = __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
-        .length         = SZ_4K,
-        .type           = MT_DEVICE,
-};
-
-void __init highbank_lluart_map_io(void)
-{
-        iotable_init(&lluart_io_desc, 1);
-}
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index fa9560ec6e70..1129957f6c1d 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -42,9 +42,7 @@ static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struc
  */
 static void __init highbank_smp_init_cpus(void)
 {
-        unsigned int i, ncores;
-
-        ncores = scu_get_core_count(scu_base_addr);
+        unsigned int i, ncores = 4;
 
         /* sanity check */
         if (ncores > NR_CPUS) {
@@ -65,7 +63,8 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 {
         int i;
 
-        scu_enable(scu_base_addr);
+        if (scu_base_addr)
+                scu_enable(scu_base_addr);
 
         /*
          * Write the address of secondary startup into the jump table
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index de866f21331f..74aa135966f0 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -19,7 +19,6 @@
 #include <linux/suspend.h>
 
 #include <asm/proc-fns.h>
-#include <asm/smp_scu.h>
 #include <asm/suspend.h>
 
 #include "core.h"
@@ -35,8 +34,6 @@ static int highbank_pm_enter(suspend_state_t state)
 {
         hignbank_set_pwr_suspend();
         highbank_set_cpu_jump(0, cpu_resume);
-
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
         cpu_suspend(0, highbank_suspend_finish);
 
         return 0;
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
index 0e913389f445..e13e8ea7c6cb 100644
--- a/arch/arm/mach-highbank/sysregs.h
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -17,6 +17,10 @@
 #define _MACH_HIGHBANK__SYSREGS_H_
 
 #include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include "core.h"
 
 extern void __iomem *sregs_base;
 
@@ -29,24 +33,39 @@ extern void __iomem *sregs_base;
 #define HB_PWR_HARD_RESET               2
 #define HB_PWR_SHUTDOWN                 3
 
+#define SREG_CPU_PWR_CTRL(c)            (0x200 + ((c) * 4))
+
+static inline void highbank_set_core_pwr(void)
+{
+        int cpu = cpu_logical_map(smp_processor_id());
+        if (scu_base_addr)
+                scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        else
+                writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
+}
+
 static inline void hignbank_set_pwr_suspend(void)
 {
         writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 
 static inline void hignbank_set_pwr_shutdown(void)
 {
         writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 
 static inline void hignbank_set_pwr_soft_reset(void)
 {
         writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 
 static inline void hignbank_set_pwr_hard_reset(void)
 {
         writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 
 #endif
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 86e37cd9376c..aed96ad9bd4a 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/io.h>
-#include <asm/smp_scu.h>
 #include <asm/proc-fns.h>
 
 #include "core.h"
@@ -27,7 +26,6 @@ void highbank_restart(char mode, const char *cmd)
         else
                 hignbank_set_pwr_soft_reset();
 
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
         while (1)
                 cpu_do_idle();
 }
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f1bf610e2900..4e24b8c77eb4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -394,6 +394,7 @@ config MACH_IMX27_VISSTRIM_M10
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MX2_CAMERA
+        select IMX_HAVE_PLATFORM_MX2_EMMA
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select LEDS_GPIO_REGISTER
@@ -820,6 +821,7 @@ config	SOC_IMX53
         select ARCH_MX5
         select ARCH_MX53
         select HAVE_CAN_FLEXCAN if CAN
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select PINCTRL
         select PINCTRL_IMX53
         select SOC_IMX5
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 585ab256c58f..4c1d1e4efc74 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -51,8 +51,10 @@
 
 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
+static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
+static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
 static const char *clko_sel_clks[] = {
-        "ckil", "prem", "ckih", "ckih",
+        "ckil", "fpm", "ckih", "ckih",
         "ckih", "mpll", "spll", "cpu_div",
         "ahb", "ipg", "per1_div", "per2_div",
         "per3_div", "per4_div", "ssi1_div", "ssi2_div",
@@ -79,7 +81,8 @@ enum mx27_clks {
         vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
         csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
         uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
-        uart2_ipg_gate, uart1_ipg_gate, clk_max
+        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
+        mpll_sel, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -91,7 +94,15 @@ int __init mx27_clocks_init(unsigned long fref)
         clk[dummy] = imx_clk_fixed("dummy", 0);
         clk[ckih] = imx_clk_fixed("ckih", fref);
         clk[ckil] = imx_clk_fixed("ckil", 32768);
-        clk[mpll] = imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
+        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
+        clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
+
+        clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
+                        mpll_osc_sel_clks,
+                        ARRAY_SIZE(mpll_osc_sel_clks));
+        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
+                        ARRAY_SIZE(mpll_sel_clks));
+        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
         clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
         clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
 
@@ -224,6 +235,7 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
         clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
         clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
+        clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
         clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
         clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
         clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index abb71f6b4d60..e8c0473c7568 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -87,6 +87,7 @@ enum imx5_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
                 unsigned long rate_osc, unsigned long rate_ckih1,
@@ -305,6 +306,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_prepare_enable(clk[spba]);
         clk_prepare_enable(clk[emi_fast_gate]); /* fec */
         clk_prepare_enable(clk[emi_slow_gate]); /* eim */
+        clk_prepare_enable(clk[mipi_hsc1_gate]);
+        clk_prepare_enable(clk[mipi_hsc2_gate]);
+        clk_prepare_enable(clk[mipi_esc_gate]);
+        clk_prepare_enable(clk[mipi_hsp_gate]);
         clk_prepare_enable(clk[tmax1]);
         clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
         clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
@@ -314,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
         int i;
+        struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
@@ -342,16 +348,20 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         pr_err("i.MX51 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
         clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
         clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -365,10 +375,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -392,6 +398,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 {
         int i;
         unsigned long r;
+        struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -436,15 +443,20 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         pr_err("i.MX53 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
         clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
         clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
         clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
+        clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
         clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
@@ -458,14 +470,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
-        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
-        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
-        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
-        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index e5a82bb95b52..448476958e7f 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -105,7 +105,7 @@ static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m"
 static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
 static const char *ipu_sels[]           = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
-static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", };
 static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
 static const char *ipu1_di0_sels[]      = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *ipu1_di1_sels[]      = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
@@ -152,8 +152,9 @@ enum mx6q_clks {
         gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
         ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
         usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-        pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
+        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
         clk_max
 };
 
@@ -164,6 +165,13 @@ static enum mx6q_clks const clks_init_on[] __initconst = {
         mmdc_ch0_axi, rom,
 };
 
+static struct clk_div_table clk_enet_ref_table[] = {
+        { .val = 0, .div = 20, },
+        { .val = 1, .div = 10, },
+        { .val = 2, .div = 5, },
+        { .val = 3, .div = 4, },
+};
+
 int __init mx6q_clocks_init(void)
 {
         struct device_node *np;
@@ -190,19 +198,29 @@ int __init mx6q_clocks_init(void)
         base = of_iomap(np, 0);
         WARN_ON(!base);
 
-        /*                   type                               name         parent_name  base     gate_mask div_mask */
-        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x2000,   0x7f);
-        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x2000,   0x1);
-        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x2000,   0x3);
-        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x2000,   0x7f);
-        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x2000,   0x7f);
-        clk[pll6_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll6_mlb",     "osc", base + 0xd0, 0x2000,   0x0);
-        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);
-        clk[pll8_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll8_enet",    "osc", base + 0xe0, 0x182000, 0x3);
+        /*                   type                               name         parent_name  base     div_mask */
+        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f);
+        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1);
+        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3);
+        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f);
+        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
+        clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
+        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
+        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
 
         clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
         clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
 
+        clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+        clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+
+        clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+        clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+
+        clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+                        base + 0xe0, 0, 2, 0, clk_enet_ref_table,
+                        &imx_ccm_lock);
+
         /*                                name              parent_name        reg       idx */
         clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
         clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
@@ -358,7 +376,7 @@ int __init mx6q_clocks_init(void)
         clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
         clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
         clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "pll6_mlb",          base + 0x74, 18);
+        clk[mlb]          = imx_clk_gate2("mlb",           "pll8_mlb",          base + 0x74, 18);
         clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
         clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
         clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 36aac947bce1..d09bc3df9a7a 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,7 +31,6 @@
  * @clk_hw:      clock source
  * @base:        base address of PLL registers
  * @powerup_set: set POWER bit to power up the PLL
- * @gate_mask:   mask of gate bits
  * @div_mask:    mask of divider bits
  *
  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 {
         struct clk_hw   hw;
         void __iomem    *base;
         bool            powerup_set;
-        u32             gate_mask;
         u32             div_mask;
 };
 
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
         u32 val;
 
         val = readl_relaxed(pll->base);
-        val |= pll->gate_mask;
+        val |= BM_PLL_ENABLE;
         writel_relaxed(val, pll->base);
 
         return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
         u32 val;
 
         val = readl_relaxed(pll->base);
-        val &= ~pll->gate_mask;
+        val &= ~BM_PLL_ENABLE;
         writel_relaxed(val, pll->base);
 }
 
@@ -287,66 +285,7 @@ static const struct clk_ops clk_pllv3_av_ops = {
 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
                                                 unsigned long parent_rate)
 {
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 div = readl_relaxed(pll->base) & pll->div_mask;
-
-        switch (div) {
-        case 0:
-                return 25000000;
-        case 1:
-                return 50000000;
-        case 2:
-                return 100000000;
-        case 3:
-                return 125000000;
-        }
-
-        return 0;
-}
-
-static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
-                                      unsigned long *prate)
-{
-        if (rate >= 125000000)
-                rate = 125000000;
-        else if (rate >= 100000000)
-                rate = 100000000;
-        else if (rate >= 50000000)
-                rate = 50000000;
-        else
-                rate = 25000000;
-        return rate;
-}
-
-static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val, div;
-
-        switch (rate) {
-        case 25000000:
-                div = 0;
-                break;
-        case 50000000:
-                div = 1;
-                break;
-        case 100000000:
-                div = 2;
-                break;
-        case 125000000:
-                div = 3;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        val = readl_relaxed(pll->base);
-        val &= ~pll->div_mask;
-        val |= div;
-        writel_relaxed(val, pll->base);
-
-        return 0;
+        return 500000000;
 }
 
 static const struct clk_ops clk_pllv3_enet_ops = {
@@ -355,8 +294,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
         .enable         = clk_pllv3_enable,
         .disable        = clk_pllv3_disable,
         .recalc_rate    = clk_pllv3_enet_recalc_rate,
-        .round_rate     = clk_pllv3_enet_round_rate,
-        .set_rate       = clk_pllv3_enet_set_rate,
 };
 
 static const struct clk_ops clk_pllv3_mlb_ops = {
@@ -368,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                           const char *parent_name, void __iomem *base,
-                          u32 gate_mask, u32 div_mask)
+                          u32 div_mask)
 {
         struct clk_pllv3 *pll;
         const struct clk_ops *ops;
@@ -400,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                 ops = &clk_pllv3_ops;
         }
         pll->base = base;
-        pll->gate_mask = gate_mask;
         pll->div_mask = div_mask;
 
         init.name = name;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 5f2d8acca25f..9d1f3b99d1d3 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -22,8 +22,7 @@ enum imx_pllv3_type {
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-                const char *parent_name, void __iomem *base, u32 gate_mask,
-                u32 div_mask);
+                const char *parent_name, void __iomem *base, u32 div_mask);
 
 struct clk *clk_register_gate2(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 8a1ad7972d4c..130962519751 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -53,8 +53,10 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
+
+extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data;
 #define imx27_add_mx2_emmaprp() \
-        imx_add_mx2_emmaprp(&imx27_mx2_camera_data)
+        imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data)
 
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
 #define imx27_add_mxc_ehci_otg(pdata)   \
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index a35d9841f494..9a8f1ca7bcb1 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -56,6 +56,9 @@ config IMX_HAVE_PLATFORM_MX1_CAMERA
 config IMX_HAVE_PLATFORM_MX2_CAMERA
         bool
 
+config IMX_HAVE_PLATFORM_MX2_EMMA
+        bool
+
 config IMX_HAVE_PLATFORM_MXC_EHCI
         bool
 
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 2abe2a5144d0..6acf37e0c119 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index e4b790b9e2aa..6277baf1b7be 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -232,8 +232,15 @@ struct imx_mx2_camera_data {
 struct platform_device *__init imx_add_mx2_camera(
                 const struct imx_mx2_camera_data *data,
                 const struct mx2_camera_platform_data *pdata);
+
+
+struct imx_mx2_emma_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
 struct platform_device *__init imx_add_mx2_emmaprp(
-                const struct imx_mx2_camera_data *data);
+                const struct imx_mx2_emma_data *data);
 
 #include <linux/platform_data/usb-ehci-mxc.h>
 struct imx_mxc_ehci_data {
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
index f4910160346b..b53e1f348f51 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c
@@ -65,20 +65,3 @@ struct platform_device *__init imx_add_mx2_camera(
                         pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
 
-struct platform_device *__init imx_add_mx2_emmaprp(
-                const struct imx_mx2_camera_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobaseemmaprp,
-                        .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irqemmaprp,
-                        .end = data->irqemmaprp,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
-                        res, 2, NULL, 0, DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 50742990a136..5ffa40c673f8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -19,35 +19,9 @@
 #include "common.h"
 #include "mx51.h"
 
-/*
- * Lookup table for attaching a specific name and platform_data pointer to
- * devices as they get created by of_platform_populate().  Ideally this table
- * would not exist, but the current clock implementation depends on some devices
- * having a specific name.
- */
-static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
-        { /* sentinel */ }
-};
-
 static void __init imx51_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             imx51_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static void __init imx51_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index e71e62610eba..860284dea0e7 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -23,34 +23,6 @@
 #include "common.h"
 #include "mx53.h"
 
-/*
- * Lookup table for attaching a specific name and platform_data pointer to
- * devices as they get created by of_platform_populate().  Ideally this table
- * would not exist, but the current clock implementation depends on some devices
- * having a specific name.
- */
-static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx21-i2c.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
-        { /* sentinel */ }
-};
-
 static void __init imx53_qsb_init(void)
 {
         struct clk *clk;
@@ -69,8 +41,7 @@ static void __init imx53_dt_init(void)
         if (of_machine_is_compatible("fsl,imx53-qsb"))
                 imx53_qsb_init();
 
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             imx53_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static void __init imx53_timer_init(void)
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index f92caf1b30ba..79d71cf23a1d 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -81,8 +81,28 @@ void __init imx50_init_early(void)
         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
 }
 
+/*
+ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
+ * the Freescale marketing division. However this did not remove the
+ * hardware from the chip which still needs to be configured for proper
+ * IPU support.
+ */
+static void __init imx51_ipu_mipi_setup(void)
+{
+        void __iomem *hsc_addr;
+        hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
+
+        /* setup MIPI module to legacy mode */
+        __raw_writel(0xf00, hsc_addr);
+
+        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
+        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
+                hsc_addr + 0x800);
+}
+
 void __init imx51_init_early(void)
 {
+        imx51_ipu_mipi_setup();
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h
index 7371018455d2..eff0adad9ae3 100644
--- a/arch/arm/mach-integrator/include/mach/irqs.h
+++ b/arch/arm/mach-integrator/include/mach/irqs.h
@@ -19,64 +19,63 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-/* 
- *  Interrupt numbers
+/*
+ * Interrupt numbers, all of the above are just static reservations
+ * used so they can be encoded into device resources. They will finally
+ * be done away with when switching to device tree.
  */
-#define IRQ_PIC_START                   1
-#define IRQ_SOFTINT                     1
-#define IRQ_UARTINT0                    2
-#define IRQ_UARTINT1                    3
-#define IRQ_KMIINT0                     4
-#define IRQ_KMIINT1                     5
-#define IRQ_TIMERINT0                   6
-#define IRQ_TIMERINT1                   7
-#define IRQ_TIMERINT2                   8
-#define IRQ_RTCINT                      9
-#define IRQ_AP_EXPINT0                  10
-#define IRQ_AP_EXPINT1                  11
-#define IRQ_AP_EXPINT2                  12
-#define IRQ_AP_EXPINT3                  13
-#define IRQ_AP_PCIINT0                  14
-#define IRQ_AP_PCIINT1                  15
-#define IRQ_AP_PCIINT2                  16
-#define IRQ_AP_PCIINT3                  17
-#define IRQ_AP_V3INT                    18
-#define IRQ_AP_CPINT0                   19
-#define IRQ_AP_CPINT1                   20
-#define IRQ_AP_LBUSTIMEOUT              21
-#define IRQ_AP_APCINT                   22
-#define IRQ_CP_CLCDCINT                 23
-#define IRQ_CP_MMCIINT0                 24
-#define IRQ_CP_MMCIINT1                 25
-#define IRQ_CP_AACIINT                  26
-#define IRQ_CP_CPPLDINT                 27
-#define IRQ_CP_ETHINT                   28
-#define IRQ_CP_TSPENINT                 29
-#define IRQ_PIC_END                     29
+#define IRQ_PIC_START                   64
+#define IRQ_SOFTINT                     (IRQ_PIC_START+0)
+#define IRQ_UARTINT0                    (IRQ_PIC_START+1)
+#define IRQ_UARTINT1                    (IRQ_PIC_START+2)
+#define IRQ_KMIINT0                     (IRQ_PIC_START+3)
+#define IRQ_KMIINT1                     (IRQ_PIC_START+4)
+#define IRQ_TIMERINT0                   (IRQ_PIC_START+5)
+#define IRQ_TIMERINT1                   (IRQ_PIC_START+6)
+#define IRQ_TIMERINT2                   (IRQ_PIC_START+7)
+#define IRQ_RTCINT                      (IRQ_PIC_START+8)
+#define IRQ_AP_EXPINT0                  (IRQ_PIC_START+9)
+#define IRQ_AP_EXPINT1                  (IRQ_PIC_START+10)
+#define IRQ_AP_EXPINT2                  (IRQ_PIC_START+11)
+#define IRQ_AP_EXPINT3                  (IRQ_PIC_START+12)
+#define IRQ_AP_PCIINT0                  (IRQ_PIC_START+13)
+#define IRQ_AP_PCIINT1                  (IRQ_PIC_START+14)
+#define IRQ_AP_PCIINT2                  (IRQ_PIC_START+15)
+#define IRQ_AP_PCIINT3                  (IRQ_PIC_START+16)
+#define IRQ_AP_V3INT                    (IRQ_PIC_START+17)
+#define IRQ_AP_CPINT0                   (IRQ_PIC_START+18)
+#define IRQ_AP_CPINT1                   (IRQ_PIC_START+19)
+#define IRQ_AP_LBUSTIMEOUT              (IRQ_PIC_START+20)
+#define IRQ_AP_APCINT                   (IRQ_PIC_START+21)
+#define IRQ_CP_CLCDCINT                 (IRQ_PIC_START+22)
+#define IRQ_CP_MMCIINT0                 (IRQ_PIC_START+23)
+#define IRQ_CP_MMCIINT1                 (IRQ_PIC_START+24)
+#define IRQ_CP_AACIINT                  (IRQ_PIC_START+25)
+#define IRQ_CP_CPPLDINT                 (IRQ_PIC_START+26)
+#define IRQ_CP_ETHINT                   (IRQ_PIC_START+27)
+#define IRQ_CP_TSPENINT                 (IRQ_PIC_START+28)
+#define IRQ_PIC_END                     (IRQ_PIC_START+28)
 
-#define IRQ_CIC_START                   32
-#define IRQ_CM_SOFTINT                  32
-#define IRQ_CM_COMMRX                   33
-#define IRQ_CM_COMMTX                   34
-#define IRQ_CIC_END                     34
+#define IRQ_CIC_START                   (IRQ_PIC_END+1)
+#define IRQ_CM_SOFTINT                  (IRQ_CIC_START+0)
+#define IRQ_CM_COMMRX                   (IRQ_CIC_START+1)
+#define IRQ_CM_COMMTX                   (IRQ_CIC_START+2)
+#define IRQ_CIC_END                     (IRQ_CIC_START+2)
 
 /*
  * IntegratorCP only
  */
-#define IRQ_SIC_START                   35
-#define IRQ_SIC_CP_SOFTINT              35
-#define IRQ_SIC_CP_RI0                  36
-#define IRQ_SIC_CP_RI1                  37
-#define IRQ_SIC_CP_CARDIN               38
-#define IRQ_SIC_CP_LMINT0               39
-#define IRQ_SIC_CP_LMINT1               40
-#define IRQ_SIC_CP_LMINT2               41
-#define IRQ_SIC_CP_LMINT3               42
-#define IRQ_SIC_CP_LMINT4               43
-#define IRQ_SIC_CP_LMINT5               44
-#define IRQ_SIC_CP_LMINT6               45
-#define IRQ_SIC_CP_LMINT7               46
-#define IRQ_SIC_END                     46
-
-#define NR_IRQS_INTEGRATOR_AP           34
-#define NR_IRQS_INTEGRATOR_CP           47
+#define IRQ_SIC_START                   (IRQ_CIC_END+1)
+#define IRQ_SIC_CP_SOFTINT              (IRQ_SIC_START+0)
+#define IRQ_SIC_CP_RI0                  (IRQ_SIC_START+1)
+#define IRQ_SIC_CP_RI1                  (IRQ_SIC_START+2)
+#define IRQ_SIC_CP_CARDIN               (IRQ_SIC_START+3)
+#define IRQ_SIC_CP_LMINT0               (IRQ_SIC_START+4)
+#define IRQ_SIC_CP_LMINT1               (IRQ_SIC_START+5)
+#define IRQ_SIC_CP_LMINT2               (IRQ_SIC_START+6)
+#define IRQ_SIC_CP_LMINT3               (IRQ_SIC_START+7)
+#define IRQ_SIC_CP_LMINT4               (IRQ_SIC_START+8)
+#define IRQ_SIC_CP_LMINT5               (IRQ_SIC_START+9)
+#define IRQ_SIC_CP_LMINT6               (IRQ_SIC_START+10)
+#define IRQ_SIC_CP_LMINT7               (IRQ_SIC_START+11)
+#define IRQ_SIC_END                     (IRQ_SIC_START+11)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index a0a7cbbb7a70..11e2a4145807 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,6 +31,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
@@ -59,8 +60,6 @@
 #include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 
-#include <plat/fpga-irq.h>
-
 #include "common.h"
 
 /* Base address to the AP system controller */
@@ -584,7 +583,6 @@ static const char * ap_dt_board_compat[] = {
 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
         .reserve        = integrator_reserve,
         .map_io         = ap_map_io,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
         .init_early     = ap_init_early,
         .init_irq       = ap_init_irq_of,
         .handle_irq     = fpga_handle_irq,
@@ -715,7 +713,6 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
         .atag_offset    = 0x100,
         .reserve        = integrator_reserve,
         .map_io         = ap_map_io_atag,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
         .init_early     = ap_init_early,
         .init_irq       = ap_init_irq,
         .handle_irq     = fpga_handle_irq,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 29df06b35d0d..7322838c0447 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -20,6 +20,7 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
@@ -47,7 +48,6 @@
 #include <asm/hardware/timer-sp.h>
 
 #include <plat/clcd.h>
-#include <plat/fpga-irq.h>
 #include <plat/sched_clock.h>
 
 #include "common.h"
@@ -387,7 +387,6 @@ static const char * intcp_dt_board_compat[] = {
 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
         .reserve        = integrator_reserve,
         .map_io         = intcp_map_io,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
         .init_early     = intcp_init_early,
         .init_irq       = intcp_init_irq_of,
         .handle_irq     = fpga_handle_irq,
@@ -482,7 +481,7 @@ static void __init intcp_init_irq(void)
         u32 pic_mask, cic_mask, sic_mask;
 
         /* These masks are for the HW IRQ registers */
-        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+        pic_mask = ~((~0u) << (11 - 0));
         pic_mask |= (~((~0u) << (29 - 22))) << 22;
         cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
         sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
@@ -563,7 +562,6 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         .atag_offset    = 0x100,
         .reserve        = integrator_reserve,
         .map_io         = intcp_map_io_atag,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
         .init_early     = intcp_init_early,
         .init_irq       = intcp_init_irq,
         .handle_irq     = fpga_handle_irq,
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f48c2e961b84..dd5d6f532e8c 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
         .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
         .get_rate       = local_return_parent_rate,
 };
+static struct clk clk_mpwm = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
+        .get_rate       = local_return_parent_rate,
+};
 static struct clk clk_wdt = {
         .parent         = &clk_pclk,
         .enable         = local_onoff_enable,
@@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
         CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
         CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
+        CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
         CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
         CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
         CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index acc4aabf1c7b..b5612a1d1839 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -515,6 +515,7 @@
 /*
  * clkpwr_timers_pwms_clk_ctrl_1 register definitions
  */
+#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN        0x40
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN      0x20
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN      0x10
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN      0x08
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 3c6332753358..9ecb8f9c4ef5 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -412,7 +412,6 @@ static const struct of_device_id mic_of_match[] __initconst = {
 void __init lpc32xx_init_irq(void)
 {
         unsigned int i;
-        int irq_base;
 
         /* Setup MIC */
         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
@@ -443,15 +442,6 @@ void __init lpc32xx_init_irq(void)
         lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
         lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
 
-        /* mask all interrupts except SUBIRQ */
-        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
-        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
-        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
-
-        /* MIC SUBIRQx interrupts will route handling to the chain handlers */
-        irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
-        irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
-
         /* Initially disable all wake events */
         __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
         __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
@@ -475,16 +465,13 @@ void __init lpc32xx_init_irq(void)
 
         of_irq_init(mic_of_match);
 
-        irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0);
-        if (irq_base < 0) {
-                pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n");
-                irq_base = 0;
-        }
-
         lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
-                                                   irq_base, 0,
-                                                   &irq_domain_simple_ops,
+                                                   0, 0, &irq_domain_simple_ops,
                                                    NULL);
         if (!lpc32xx_mic_domain)
                 panic("Unable to add MIC irq domain\n");
+
+        /* MIC SUBIRQx interrupts will route handling to the chain handlers */
+        irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
+        irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
 }
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d7a13d1771a3..25df14a9e268 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -405,6 +405,7 @@ config MACH_MINI2440
         select NEW_LEDS
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
+        select S3C_SETUP_CAMIF
         help
           Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
           available via various sources. It can come with a 3.5" or 7" touch LCD.
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 4407b1730539..04b87ec92537 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -161,6 +161,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
+        CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
 };
 
 static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8ae100cc655c..546e40a9dcaf 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -2,18 +2,6 @@ if ARCH_SHMOBILE
 
 comment "SH-Mobile System Type"
 
-config ARCH_SH7367
-        bool "SH-Mobile G3 (SH7367)"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select CPU_V6
-        select SH_CLK_CPG
-
-config ARCH_SH7377
-        bool "SH-Mobile G4 (SH7377)"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select CPU_V7
-        select SH_CLK_CPG
-
 config ARCH_SH7372
         bool "SH-Mobile AP4 (SH7372)"
         select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe2c97c179d1..f4fd247bde61 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,8 +6,6 @@
 obj-y                           := timer.o console.o clock.o
 
 # CPU objects
-obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
-obj-$(CONFIG_ARCH_SH7377)       += setup-sh7377.o clock-sh7377.o intc-sh7377.o
 obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o clock-sh7372.o intc-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
@@ -23,16 +21,12 @@ smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o
 
 # Pinmux setup
 pfc-y                           :=
-pfc-$(CONFIG_ARCH_SH7367)       += pfc-sh7367.o
-pfc-$(CONFIG_ARCH_SH7377)       += pfc-sh7377.o
 pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
 pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
 pfc-$(CONFIG_ARCH_R8A7740)      += pfc-r8a7740.o
 pfc-$(CONFIG_ARCH_R8A7779)      += pfc-r8a7779.o
 
 # IRQ objects
-obj-$(CONFIG_ARCH_SH7367)       += entry-intc.o
-obj-$(CONFIG_ARCH_SH7377)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 obj-$(CONFIG_ARCH_R8A7740)      += entry-intc.o
 
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 790dc68c4312..cefdd030361d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -728,7 +728,7 @@ fsia_ick_out:
 static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
 {
         struct clk *fsib_clk;
-        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
         long fsib_rate = 0;
         long fdiv_rate = 0;
         int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 0c27c810cf99..c826d77ab8a6 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
 static int fsi_b_set_rate(struct device *dev, int rate, int enable)
 {
         struct clk *fsib_clk;
-        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
         long fsib_rate = 0;
         long fdiv_rate = 0;
         int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 6729e0032180..eac49d59782f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -65,6 +65,9 @@
 #define SMSTPCR3        IOMEM(0xe615013c)
 #define SMSTPCR4        IOMEM(0xe6150140)
 
+#define FSIDIVA         IOMEM(0xFE1F8000)
+#define FSIDIVB         IOMEM(0xFE1F8008)
+
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
         .rate   = 32768,
@@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = {
 };
 
 /* USB clock */
+/*
+ * USBCKCR is controlling usb24 clock
+ * bit[7] : parent clock
+ * bit[6] : clock divide rate
+ * And this bit[7] is used as a "usb24s" from other devices.
+ * (Video clock / Sub clock / SPU clock)
+ * You can controll this clock as a below.
+ *
+ * struct clk *usb24    = clk_get(dev,  "usb24");
+ * struct clk *usb24s   = clk_get(NULL, "usb24s");
+ * struct clk *system   = clk_get(NULL, "system_clk");
+ * int rate = clk_get_rate(system);
+ *
+ * clk_set_parent(usb24s, system);  // for bit[7]
+ * clk_set_rate(usb24, rate / 2);   // for bit[6]
+ */
 static struct clk *usb24s_parents[] = {
         [0] = &system_clk,
         [1] = &extal2_clk
@@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = {
         &hdmi2_clk,
 };
 
+/* FSI DIV */
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
+
+static struct clk fsidivs[] = {
+        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
+};
+
 /* MSTP */
 enum {
         DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
@@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = {
 
         CLKDEV_ICK_ID("icka", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIA]),
         CLKDEV_ICK_ID("ickb", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIB]),
+        CLKDEV_ICK_ID("diva", "sh_fsi2",        &fsidivs[FSIDIV_A]),
+        CLKDEV_ICK_ID("divb", "sh_fsi2",        &fsidivs[FSIDIV_B]),
+        CLKDEV_ICK_ID("xcka", "sh_fsi2",        &fsiack_clk),
+        CLKDEV_ICK_ID("xckb", "sh_fsi2",        &fsibck_clk),
 };
 
 void __init r8a7740_clock_init(u8 md_ck)
@@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck)
         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
                 ret = clk_register(late_main_clks[k]);
 
+        if (!ret)
+                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 37b2a3133b3b..c019609da660 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,8 +87,11 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+        MSTP101, MSTP100,
+        MSTP030,
+        MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
+        MSTP007,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
@@ -96,6 +99,12 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
+        [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
+        [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
+        [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
+        [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
+        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */
         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -105,6 +114,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
         [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
         [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
+        [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0,  7, 0), /* HSPI */
 };
 
 static unsigned long mul4_recalc(struct clk *clk)
@@ -146,14 +156,25 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+        CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
+        CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+        CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
+        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
deleted file mode 100644
index ef0a95e592c4..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * SH7367 clock framework support
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include <mach/common.h>
-
-/* SH7367 registers */
-#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    IOMEM(0xe615001C)
-#define SCLKACR    IOMEM(0xe6150010)
-#define SCLKBCR    IOMEM(0xe6150014)
-#define SUBUSBCKCR IOMEM(0xe6158080)
-#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   IOMEM(0xe6150090)
-#define VOUCKCR    IOMEM(0xe6150094)
-#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    IOMEM(0xe615009C)
-#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    IOMEM(0xe615002C)
-#define RTMSTPCR0  IOMEM(0xe6158030)
-#define RTMSTPCR2  IOMEM(0xe6158038)
-#define SYMSTPCR0  IOMEM(0xe6158040)
-#define SYMSTPCR2  IOMEM(0xe6158048)
-#define CMMSTPCR0  IOMEM(0xe615804c)
-
-/* Fixed 32 KHz root clock from EXTALR pin */
-static struct clk r_clk = {
-        .rate           = 32768,
-};
-
-/*
- * 26MHz default rate for the EXTALB1 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7367_extalb1_clk = {
-        .rate           = 26666666,
-};
-
-/*
- * 48MHz default rate for the EXTAL2 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7367_extal2_clk = {
-        .rate           = 48000000,
-};
-
-/* A fixed divide-by-2 block */
-static unsigned long div2_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 2;
-}
-
-static struct sh_clk_ops div2_clk_ops = {
-        .recalc         = div2_recalc,
-};
-
-/* Divide extalb1 by two */
-static struct clk extalb1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7367_extalb1_clk,
-};
-
-/* Divide extal2 by two */
-static struct clk extal2_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7367_extal2_clk,
-};
-
-/* PLLC1 */
-static unsigned long pllc1_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-
-        if (__raw_readl(PLLC1CR) & (1 << 14))
-                mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
-
-        return clk->parent->rate * mult;
-}
-
-static struct sh_clk_ops pllc1_clk_ops = {
-        .recalc         = pllc1_recalc,
-};
-
-static struct clk pllc1_clk = {
-        .ops            = &pllc1_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalb1_div2_clk,
-};
-
-/* Divide PLLC1 by two */
-static struct clk pllc1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &pllc1_clk,
-};
-
-/* PLLC2 */
-static unsigned long pllc2_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-
-        if (__raw_readl(PLLC2CR) & (1 << 31))
-                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
-
-        return clk->parent->rate * mult;
-}
-
-static struct sh_clk_ops pllc2_clk_ops = {
-        .recalc         = pllc2_recalc,
-};
-
-static struct clk pllc2_clk = {
-        .ops            = &pllc2_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalb1_div2_clk,
-};
-
-static struct clk *main_clks[] = {
-        &r_clk,
-        &sh7367_extalb1_clk,
-        &sh7367_extal2_clk,
-        &extalb1_div2_clk,
-        &extal2_div2_clk,
-        &pllc1_clk,
-        &pllc1_div2_clk,
-        &pllc2_clk,
-};
-
-static void div4_kick(struct clk *clk)
-{
-        unsigned long value;
-
-        /* set KICK bit in SYFRQCR to update hardware setting */
-        value = __raw_readl(SYFRQCR);
-        value |= (1 << 31);
-        __raw_writel(value, SYFRQCR);
-}
-
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
-                          24, 32, 36, 48, 0, 72, 0, 0 };
-
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = divisors,
-        .nr_divisors = ARRAY_SIZE(divisors),
-};
-
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-        .kick = div4_kick,
-};
-
-enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
-       DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
-       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
-
-#define DIV4(_reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
-
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
-        [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
-        [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
-        [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
-        [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
-        [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
-        [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
-        [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
-        [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
-};
-
-enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
-       DIV6_MVI3, DIV6_MF1, DIV6_MF2,
-       DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
-       DIV6_NR };
-
-static struct clk div6_clks[DIV6_NR] = {
-        [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
-        [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
-        [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
-        [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
-        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
-        [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
-        [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
-        [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
-        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
-        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
-        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
-        [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
-};
-
-enum { RTMSTP001,
-       RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
-       RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
-       SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
-       SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
-       SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
-       SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
-       CMMSTP003,
-       MSTP_NR };
-
-#define MSTP(_parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
-
-static struct clk mstp_clks[MSTP_NR] = {
-        [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
-        [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
-        [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
-        [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
-        [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
-        [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
-        [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
-        [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
-        [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
-        [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
-        [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
-        [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
-        [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
-        [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
-        [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
-        [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
-        [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
-        [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
-        [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
-        [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
-        [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
-        [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
-        [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
-        [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
-        [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
-        [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
-        [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
-        [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
-};
-
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("r_clk", &r_clk),
-        CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
-        CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
-        CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
-        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
-        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
-        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
-        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
-
-        /* DIV4 clocks */
-        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
-        CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
-        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
-        CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
-        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
-        CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
-        CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
-        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
-        CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
-        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
-        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
-        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
-
-        /* DIV6 clocks */
-        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
-        CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
-        CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
-        CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
-        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
-        CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
-        CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
-        CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
-        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
-        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
-        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
-        CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
-
-        /* MSTP32 clocks */
-        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
-        CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
-        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
-        CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
-        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
-        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
-        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
-        CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
-        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
-};
-
-void __init sh7367_clock_init(void)
-{
-        int k, ret = 0;
-
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-
-        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
-
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup sh7367 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 430a90ffa120..4d57e342537b 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 };
 
 /* FSI DIV */
-static unsigned long fsidiv_recalc(struct clk *clk)
-{
-        unsigned long value;
-
-        value = __raw_readl(clk->mapping->base);
-
-        value >>= 16;
-        if (value < 2)
-                return 0;
-
-        return clk->parent->rate / value;
-}
-
-static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk_rate_div_range_round(clk, 2, 0xffff, rate);
-}
-
-static void fsidiv_disable(struct clk *clk)
-{
-        __raw_writel(0, clk->mapping->base);
-}
-
-static int fsidiv_enable(struct clk *clk)
-{
-        unsigned long value;
-
-        value  = __raw_readl(clk->mapping->base) >> 16;
-        if (value < 2)
-                return -EIO;
-
-        __raw_writel((value << 16) | 0x3, clk->mapping->base);
-
-        return 0;
-}
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
 
-static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
-{
-        int idx;
-
-        idx = (clk->parent->rate / rate) & 0xffff;
-        if (idx < 2)
-                return -EINVAL;
-
-        __raw_writel(idx << 16, clk->mapping->base);
-        return 0;
-}
-
-static struct sh_clk_ops fsidiv_clk_ops = {
-        .recalc         = fsidiv_recalc,
-        .round_rate     = fsidiv_round_rate,
-        .set_rate       = fsidiv_set_rate,
-        .enable         = fsidiv_enable,
-        .disable        = fsidiv_disable,
-};
-
-static struct clk_mapping fsidiva_clk_mapping = {
-        .phys   = FSIDIVA,
-        .len    = 8,
-};
-
-struct clk sh7372_fsidiva_clk = {
-        .ops            = &fsidiv_clk_ops,
-        .parent         = &div6_reparent_clks[DIV6_FSIA], /* late install */
-        .mapping        = &fsidiva_clk_mapping,
-};
-
-static struct clk_mapping fsidivb_clk_mapping = {
-        .phys   = FSIDIVB,
-        .len    = 8,
-};
-
-struct clk sh7372_fsidivb_clk = {
-        .ops            = &fsidiv_clk_ops,
-        .parent         = &div6_reparent_clks[DIV6_FSIB],  /* late install */
-        .mapping        = &fsidivb_clk_mapping,
-};
-
-static struct clk *late_main_clks[] = {
-        &sh7372_fsidiva_clk,
-        &sh7372_fsidivb_clk,
+static struct clk fsidivs[] = {
+        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
 };
 
 enum { MSTP001, MSTP000,
@@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
         CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
         CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
+        CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
+        CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),
 
         /* DIV4 clocks */
         CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
         CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
         CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
+        CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
+        CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
+        CLKDEV_ICK_ID("xcka", "sh_fsi2", &sh7372_fsiack_clk),
+        CLKDEV_ICK_ID("xckb", "sh_fsi2", &sh7372_fsibck_clk),
 };
 
 void __init sh7372_clock_init(void)
@@ -706,8 +636,8 @@ void __init sh7372_clock_init(void)
         if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
-        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
-                ret = clk_register(late_main_clks[k]);
+        if (!ret)
+                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
deleted file mode 100644
index b8480d19e1c8..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * SH7377 clock framework support
- *
- * Copyright (C) 2010 Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include <mach/common.h>
-
-/* SH7377 registers */
-#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    IOMEM(0xe615001C)
-#define FMSICKCR   IOMEM(0xe6150010)
-#define FMSOCKCR   IOMEM(0xe6150014)
-#define FSICKCR    IOMEM(0xe6150018)
-#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    IOMEM(0xe615002C)
-#define SUBUSBCKCR IOMEM(0xe6150080)
-#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   IOMEM(0xe6150090)
-#define HDMICKCR   IOMEM(0xe6150094)
-#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    IOMEM(0xe615009C)
-#define DSITCKCR   IOMEM(0xe6150060)
-#define DSIPCKCR   IOMEM(0xe6150064)
-#define SMSTPCR0   IOMEM(0xe6150130)
-#define SMSTPCR1   IOMEM(0xe6150134)
-#define SMSTPCR2   IOMEM(0xe6150138)
-#define SMSTPCR3   IOMEM(0xe615013C)
-#define SMSTPCR4   IOMEM(0xe6150140)
-
-/* Fixed 32 KHz root clock from EXTALR pin */
-static struct clk r_clk = {
-        .rate           = 32768,
-};
-
-/*
- * 26MHz default rate for the EXTALC1 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7377_extalc1_clk = {
-        .rate           = 26666666,
-};
-
-/*
- * 48MHz default rate for the EXTAL2 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7377_extal2_clk = {
-        .rate           = 48000000,
-};
-
-/* A fixed divide-by-2 block */
-static unsigned long div2_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 2;
-}
-
-static struct sh_clk_ops div2_clk_ops = {
-        .recalc         = div2_recalc,
-};
-
-/* Divide extalc1 by two */
-static struct clk extalc1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7377_extalc1_clk,
-};
-
-/* Divide extal2 by two */
-static struct clk extal2_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7377_extal2_clk,
-};
-
-/* Divide extal2 by four */
-static struct clk extal2_div4_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &extal2_div2_clk,
-};
-
-/* PLLC1 */
-static unsigned long pllc1_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-
-        if (__raw_readl(PLLC1CR) & (1 << 14))
-                mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
-
-        return clk->parent->rate * mult;
-}
-
-static struct sh_clk_ops pllc1_clk_ops = {
-        .recalc         = pllc1_recalc,
-};
-
-static struct clk pllc1_clk = {
-        .ops            = &pllc1_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalc1_div2_clk,
-};
-
-/* Divide PLLC1 by two */
-static struct clk pllc1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &pllc1_clk,
-};
-
-/* PLLC2 */
-static unsigned long pllc2_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-
-        if (__raw_readl(PLLC2CR) & (1 << 31))
-                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
-
-        return clk->parent->rate * mult;
-}
-
-static struct sh_clk_ops pllc2_clk_ops = {
-        .recalc         = pllc2_recalc,
-};
-
-static struct clk pllc2_clk = {
-        .ops            = &pllc2_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalc1_div2_clk,
-};
-
-static struct clk *main_clks[] = {
-        &r_clk,
-        &sh7377_extalc1_clk,
-        &sh7377_extal2_clk,
-        &extalc1_div2_clk,
-        &extal2_div2_clk,
-        &extal2_div4_clk,
-        &pllc1_clk,
-        &pllc1_div2_clk,
-        &pllc2_clk,
-};
-
-static void div4_kick(struct clk *clk)
-{
-        unsigned long value;
-
-        /* set KICK bit in SYFRQCR to update hardware setting */
-        value = __raw_readl(SYFRQCR);
-        value |= (1 << 31);
-        __raw_writel(value, SYFRQCR);
-}
-
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
-                          24, 32, 36, 48, 0, 72, 96, 0 };
-
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = divisors,
-        .nr_divisors = ARRAY_SIZE(divisors),
-};
-
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-        .kick = div4_kick,
-};
-
-enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
-       DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
-       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
-
-#define DIV4(_reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
-
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
-        [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
-        [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
-        [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
-        [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
-        [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
-        [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
-        [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
-        [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
-};
-
-enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
-       DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
-       DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
-       DIV6_NR };
-
-static struct clk div6_clks[] = {
-        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
-        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
-        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
-        [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
-        [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
-        [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
-        [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
-        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
-        [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
-        [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
-        [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
-        [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
-        [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
-        [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
-        [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
-};
-
-enum { MSTP001,
-       MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
-       MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-       MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
-       MSTP315, MSTP314, MSTP313,
-       MSTP403,
-       MSTP_NR };
-
-#define MSTP(_parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
-
-static struct clk mstp_clks[] = {
-        [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
-        [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
-        [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
-        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
-        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
-        [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
-        [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
-        [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
-        [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
-        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
-        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
-        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
-        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
-        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
-        [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
-        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
-        [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
-        [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
-        [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
-        [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
-        [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
-        [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
-        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
-};
-
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("r_clk", &r_clk),
-        CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
-        CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
-        CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
-        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
-        CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
-        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
-        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
-        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
-
-        /* DIV4 clocks */
-        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
-        CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
-        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
-        CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
-        CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
-        CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
-        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
-        CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
-        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
-        CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
-        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
-        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
-        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
-
-        /* DIV6 clocks */
-        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
-        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
-        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
-        CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
-        CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
-        CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
-        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
-        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
-        CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
-        CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
-        CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
-        CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
-        CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
-        CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
-        CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
-
-        /* MSTP32 clocks */
-        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
-        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
-        CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
-        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
-        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
-        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
-        CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
-        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
-};
-
-void __init sh7377_clock_init(void)
-{
-        int k, ret = 0;
-
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-
-        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
-
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup sh7377 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index d47e215aca87..dfeca79e9e96 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -18,24 +18,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
                               struct cpuidle_driver *drv, int index);
 extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 
-extern void sh7367_init_irq(void);
-extern void sh7367_map_io(void);
-extern void sh7367_add_early_devices(void);
-extern void sh7367_add_standard_devices(void);
-extern void sh7367_clock_init(void);
-extern void sh7367_pinmux_init(void);
-extern struct clk sh7367_extalb1_clk;
-extern struct clk sh7367_extal2_clk;
-
-extern void sh7377_init_irq(void);
-extern void sh7377_map_io(void);
-extern void sh7377_add_early_devices(void);
-extern void sh7377_add_standard_devices(void);
-extern void sh7377_clock_init(void);
-extern void sh7377_pinmux_init(void);
-extern struct clk sh7377_extalc1_clk;
-extern struct clk sh7377_extal2_clk;
-
 extern void sh7372_init_irq(void);
 extern void sh7372_map_io(void);
 extern void sh7372_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 499f52d2a4a1..8ab0cd6ad6b0 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
         GPIO_FN_A19,
 
         /* IPSR0 */
-        GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+        GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
         GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
         GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
         GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h
deleted file mode 100644
index 52d0de686f68..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7367.h
+++ /dev/null
@@ -1,332 +0,0 @@
-#ifndef __ASM_SH7367_H__
-#define __ASM_SH7367_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* 49-1 -> 49-6 (GPIO) */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
-        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
-
-        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
-        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
-
-        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
-        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
-
-        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
-        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
-
-        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
-        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
-
-        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
-        GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
-
-        GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
-
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
-        GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
-        GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
-        GPIO_FN_PORT58_KEYIN6_PU,
-
-        /* 49-1 (FN) */
-        GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
-        GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
-        GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
-        GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
-        GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
-        GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
-        GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
-        GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
-        GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
-        GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
-        GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
-        GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
-        GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
-        GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
-        GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
-
-        /* 49-2 (FN) */
-        GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
-        GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
-        GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
-        GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
-        GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
-        GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
-        GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
-        GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
-        GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
-        GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
-        GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
-        GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
-        GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
-        GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
-        GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
-        GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
-        GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
-        GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
-        GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
-        GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
-        GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
-        GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
-        GPIO_FN_XTALB1L,
-        GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
-        GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
-        GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
-        GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
-        GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
-        GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
-        GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
-        GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
-        GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
-        GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
-        GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
-        GPIO_FN_NMI, GPIO_FN_TPU4TO0,
-        GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
-        GPIO_FN_IRQ_TMPB,
-        GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
-        GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
-        GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
-
-        /* 49-3 (FN) */
-        GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
-        GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
-        GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
-        GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
-        GPIO_FN_SCIFA5_RXD,
-        GPIO_FN_SCIFA5_TXD,
-        GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
-        GPIO_FN_A0_EA0, GPIO_FN_BS,
-        GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
-        GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
-        GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
-        GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
-        GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
-        GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
-        GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
-        GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
-        GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
-        GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
-        GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
-        GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
-        GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
-        GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
-        GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
-        GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
-        GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
-        GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
-        GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
-        GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
-        GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
-        GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
-        GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
-        GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
-        GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
-        GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
-        GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
-        GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
-
-        /* 49-4 (FN) */
-        GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
-        GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
-        GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
-        GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
-        GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
-        GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
-        GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
-        GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
-        GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
-        GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
-        GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
-        GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
-        GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
-        GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
-        GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
-        GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
-        GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
-        GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
-        GPIO_FN_LCDD6, GPIO_FN_DV_D6,
-        GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
-        GPIO_FN_LCDD7, GPIO_FN_DV_D7,
-        GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
-        GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
-        GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
-        GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
-        GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
-        GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
-        GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
-        GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
-        GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
-        GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
-        GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
-        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
-        GPIO_FN_D26, GPIO_FN_ED26,
-        GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
-        GPIO_FN_D27, GPIO_FN_ED27,
-        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
-        GPIO_FN_D28, GPIO_FN_ED28,
-        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
-        GPIO_FN_D29, GPIO_FN_ED29,
-        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
-        GPIO_FN_D30, GPIO_FN_ED30,
-        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
-        GPIO_FN_D31, GPIO_FN_ED31,
-        GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
-        GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
-
-
-        /* 49-5 (FN) */
-        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
-        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
-        GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
-        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
-        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
-        GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
-        GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
-        GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
-        GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
-        GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
-        GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
-        GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
-        GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
-        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
-        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
-        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
-        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
-        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
-        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
-        GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
-        GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
-        GPIO_FN_MSIOF1_SS2,
-        GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
-        GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
-        GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
-        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
-        GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
-        GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
-        GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
-        GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
-        GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
-        GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
-        GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
-        GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
-        GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
-        GPIO_FN_SDHICD0,
-        GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
-        GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
-        GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
-        GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
-
-        /* 49-6 (FN) */
-        GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
-        GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
-        GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
-        GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
-        GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
-        GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
-        GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
-        GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
-        GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
-        GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
-        GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
-        GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
-        GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
-        GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
-        GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
-        GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SDHICMD2,
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_DIVLOCK,
-};
-
-#endif /* __ASM_SH7367_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index eb98b45c5089..26cd1016fad8 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -452,6 +452,10 @@ enum {
         SHDMA_SLAVE_SCIF5_RX,
         SHDMA_SLAVE_SCIF6_TX,
         SHDMA_SLAVE_SCIF6_RX,
+        SHDMA_SLAVE_FLCTL0_TX,
+        SHDMA_SLAVE_FLCTL0_RX,
+        SHDMA_SLAVE_FLCTL1_TX,
+        SHDMA_SLAVE_FLCTL1_RX,
         SHDMA_SLAVE_SDHI0_RX,
         SHDMA_SLAVE_SDHI0_TX,
         SHDMA_SLAVE_SDHI1_RX,
@@ -475,8 +479,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
 extern struct clk sh7372_pllc2_clk;
 extern struct clk sh7372_fsiack_clk;
 extern struct clk sh7372_fsibck_clk;
-extern struct clk sh7372_fsidiva_clk;
-extern struct clk sh7372_fsidivb_clk;
 
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h
deleted file mode 100644
index f580e227dd1c..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7377.h
+++ /dev/null
@@ -1,360 +0,0 @@
-#ifndef __ASM_SH7377_H__
-#define __ASM_SH7377_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* 55-1 -> 55-5 (GPIO) */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
-
-        GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-
-        GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
-        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
-
-        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
-        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
-
-        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
-        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
-
-        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
-        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
-
-        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
-        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
-
-        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
-
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU,
-        GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU,
-        GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU,
-        GPIO_FN_PORT72_KEYIN6_PU,
-
-        /* 55-1 (FN) */
-        GPIO_FN_VBUS_0,
-        GPIO_FN_CPORT0,
-        GPIO_FN_CPORT1,
-        GPIO_FN_CPORT2,
-        GPIO_FN_CPORT3,
-        GPIO_FN_CPORT4,
-        GPIO_FN_CPORT5,
-        GPIO_FN_CPORT6,
-        GPIO_FN_CPORT7,
-        GPIO_FN_CPORT8,
-        GPIO_FN_CPORT9,
-        GPIO_FN_CPORT10,
-        GPIO_FN_CPORT11, GPIO_FN_SIN2,
-        GPIO_FN_CPORT12, GPIO_FN_XCTS2,
-        GPIO_FN_CPORT13, GPIO_FN_RFSPO4,
-        GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
-        GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2,
-        GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3,
-        GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2,
-        GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2,
-        GPIO_FN_CPORT19_MPORT1,
-        GPIO_FN_CPORT20, GPIO_FN_RFSPO6,
-        GPIO_FN_CPORT21, GPIO_FN_STATUS0,
-        GPIO_FN_CPORT22, GPIO_FN_STATUS1,
-        GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
-        GPIO_FN_B_SYNLD1,
-        GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK,
-        GPIO_FN_XMAINPS,
-        GPIO_FN_XDIVPS,
-        GPIO_FN_XIDRST,
-        GPIO_FN_IDCLK, GPIO_FN_IC_DP,
-        GPIO_FN_IDIO, GPIO_FN_IC_DM,
-        GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT,
-        GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
-        GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
-        GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
-        GPIO_FN_PCMCLKO,
-        GPIO_FN_SYNC8KO,
-
-        /* 55-2 (FN) */
-        GPIO_FN_DNPCM_A,
-        GPIO_FN_UPPCM_A,
-        GPIO_FN_VACK,
-        GPIO_FN_XTALB1L,
-        GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_GPS_IM,
-        GPIO_FN_GPS_IS,
-        GPIO_FN_GPS_QM,
-        GPIO_FN_GPS_QS,
-        GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
-        GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3,
-        GPIO_FN_FMSIOLR,
-        GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1,
-        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2,
-        GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
-        GPIO_FN_OPORT3, GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
-        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0,
-        GPIO_FN_A0_EA0, GPIO_FN_BS,
-        GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2,
-        GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2,
-        GPIO_FN_TPU0TO1,
-        GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5,
-        GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4,
-        GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
-        GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
-        GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD,
-        GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6,
-        GPIO_FN_D0_ED0_NAF0,
-        GPIO_FN_D1_ED1_NAF1,
-        GPIO_FN_D2_ED2_NAF2,
-        GPIO_FN_D3_ED3_NAF3,
-        GPIO_FN_D4_ED4_NAF4,
-        GPIO_FN_D5_ED5_NAF5,
-        GPIO_FN_D6_ED6_NAF6,
-        GPIO_FN_D7_ED7_NAF7,
-        GPIO_FN_D8_ED8_NAF8,
-        GPIO_FN_D9_ED9_NAF9,
-        GPIO_FN_D10_ED10_NAF10,
-        GPIO_FN_D11_ED11_NAF11,
-        GPIO_FN_D12_ED12_NAF12,
-        GPIO_FN_D13_ED13_NAF13,
-        GPIO_FN_D14_ED14_NAF14,
-        GPIO_FN_D15_ED15_NAF15,
-        GPIO_FN_CS4,
-        GPIO_FN_CS5A, GPIO_FN_FMSICK,
-        GPIO_FN_CS5B, GPIO_FN_FCE1,
-
-        /* 55-3 (FN) */
-        GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0,
-        GPIO_FN_FCE0,
-        GPIO_FN_WAIT, GPIO_FN_DREQ0,
-        GPIO_FN_RD_XRD,
-        GPIO_FN_WE0_XWR0_FWE,
-        GPIO_FN_WE1_XWR1,
-        GPIO_FN_FRB,
-        GPIO_FN_CKO,
-        GPIO_FN_NBRSTOUT,
-        GPIO_FN_NBRST,
-        GPIO_FN_GPS_EPPSIN,
-        GPIO_FN_LATCHPULSE,
-        GPIO_FN_LTESIGNAL,
-        GPIO_FN_LEGACYSTATE,
-        GPIO_FN_TCKON,
-        GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0,
-        GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1,
-        GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD,
-        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1,
-        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2,
-        GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC,
-        GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD,
-        GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK,
-        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2,
-        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3,
-        GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC,
-        GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR,
-        GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2,
-        GPIO_FN_PORT140_FSIAOBT,
-        GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3,
-        GPIO_FN_PORT141_FSIAOSLD,
-        GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK,
-        GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR,
-        GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT,
-        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD,
-        GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2,
-        GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5,
-        GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6,
-        GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1,
-        GPIO_FN_MFG0_IN2,
-        GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
-        GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
-        GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
-        GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2,
-        GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD,
-
-        /* 55-4 (FN) */
-        GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
-        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
-        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0,
-        GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0,
-        GPIO_FN_MFG3_IN2,
-        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0,
-        GPIO_FN_MFG3_IN1,
-        GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0,
-        GPIO_FN_MFG3_OUT1,
-        GPIO_FN_TPU3TO0,
-        GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI,
-        GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS,
-        GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS,
-        GPIO_FN_BBIF2_TSCK1,
-        GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD,
-        GPIO_FN_BBIF2_TXD1,
-        GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD,
-        GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK,
-        GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1,
-        GPIO_FN_LCDD6, GPIO_FN_XWR2,
-        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
-        GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16,
-        GPIO_FN_ED16,
-        GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17,
-        GPIO_FN_ED17,
-        GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18,
-        GPIO_FN_ED18,
-        GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19,
-        GPIO_FN_ED19,
-        GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20,
-        GPIO_FN_ED20,
-        GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21,
-        GPIO_FN_ED21,
-        GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22,
-        GPIO_FN_ED22,
-        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0,
-        GPIO_FN_VIO_DR7,
-        GPIO_FN_D23, GPIO_FN_ED23,
-        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1,
-        GPIO_FN_VIO_VDR,
-        GPIO_FN_D24, GPIO_FN_ED24,
-        GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25,
-        GPIO_FN_ED25,
-        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
-        GPIO_FN_ED26,
-        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27,
-        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
-        GPIO_FN_ED28,
-        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
-        GPIO_FN_ED29,
-        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
-        GPIO_FN_ED30,
-        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
-        GPIO_FN_ED31,
-        GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3,
-        GPIO_FN_VIO_CLKR,
-        GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC,
-        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
-        GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4,
-        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK,
-        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5,
-        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD,
-        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN,
-        GPIO_FN_MSIOF0L_TXD,
-        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
-        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM,
-        GPIO_FN_PORT226_VIO_CKO2,
-        GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN,
-        GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1,
-        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC,
-        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR,
-        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT,
-        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG,
-        GPIO_FN_PORT233_FSIACK,
-        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD,
-        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2,
-        GPIO_FN_PORT235_FSIAILR,
-        GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT,
-        GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD,
-        GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
-
-        /* 55-5 (FN) */
-        GPIO_FN_MSIOF1_SS2,
-        GPIO_FN_SCIFA6_TXD,
-        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1,
-        GPIO_FN_TPU4TO0,
-        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
-        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
-        GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS,
-        GPIO_FN_PORT244_MSIOF2_RXD,
-        GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS,
-        GPIO_FN_PORT245_MSIOF2_TXD,
-        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1,
-        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
-        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2,
-        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
-        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1,
-        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0,
-        GPIO_FN_PORT248_MSIOF2_TSCK,
-        GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC,
-        GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0,
-        GPIO_FN_SDHICD0,
-        GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0,
-        GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0,
-        GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
-        GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0,
-        GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
-        GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
-        GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1,
-        GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2,
-        GPIO_FN_TMS3_SWDIO_MC1,
-        GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2,
-        GPIO_FN_TDO3_SWO0_MC1,
-        GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
-        GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2,
-        GPIO_FN_RTCK3_SWO1_MC1,
-        GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
-        GPIO_FN_RESETOUTS,
-};
-
-#endif /* __ASM_SH7377_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
deleted file mode 100644
index 5bf776495b75..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * sh7367 processor support - INTC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sh_intc.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-enum {
-        UNUSED_INTCA = 0,
-        ENABLED,
-        DISABLED,
-
-        /* interrupt sources INTCA */
-        DIRC,
-        CRYPT1_ERR, CRYPT2_STD,
-        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
-        ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
-        ETM11_ACQCMP, ETM11_FULL,
-        MFI_MFIM, MFI_MFIS,
-        BBIF1, BBIF2,
-        USBDMAC_USHDMI,
-        USBHS_USHI0, USBHS_USHI1,
-        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
-        KEYSC_KEY,
-        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
-        MSIOF2, MSIOF1,
-        SCIFA4, SCIFA5, SCIFB,
-        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-        SDHI0,
-        SDHI1,
-        MSU_MSU, MSU_MSU2,
-        IREM,
-        SIU,
-        SPU,
-        IRDA,
-        TPU0, TPU1, TPU2, TPU3, TPU4,
-        LCRC,
-        PINT1, PINT2,
-        TTI20,
-        MISTY,
-        DDM,
-        SDHI2,
-        RWDT0, RWDT1,
-        DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
-        DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
-        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
-        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
-        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
-        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
-
-        /* interrupt groups INTCA */
-        DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
-        ETM11, ARM11, USBHS, FLCTL, IIC1
-};
-
-static struct intc_vect intca_vectors[] __initdata = {
-        INTC_VECT(DIRC, 0x0560),
-        INTC_VECT(CRYPT1_ERR, 0x05e0),
-        INTC_VECT(CRYPT2_STD, 0x0700),
-        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
-        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
-        INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
-        INTC_VECT(ARM11_COMMRX, 0x0860),
-        INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
-        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
-        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
-        INTC_VECT(USBDMAC_USHDMI, 0x0a00),
-        INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
-        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
-        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
-        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
-        INTC_VECT(KEYSC_KEY, 0x0be0),
-        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
-        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
-        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
-        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
-        INTC_VECT(SCIFB, 0x0d60),
-        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
-        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
-        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
-        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
-        INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
-        INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
-        INTC_VECT(IREM, 0x0f60),
-        INTC_VECT(SIU, 0x0fa0),
-        INTC_VECT(SPU, 0x0fc0),
-        INTC_VECT(IRDA, 0x0480),
-        INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
-        INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
-        INTC_VECT(TPU4, 0x0520),
-        INTC_VECT(LCRC, 0x0540),
-        INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
-        INTC_VECT(TTI20, 0x1100),
-        INTC_VECT(MISTY, 0x1120),
-        INTC_VECT(DDM, 0x1140),
-        INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
-        INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
-        INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
-        INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
-        INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
-        INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
-        INTC_VECT(DMAC_2_DADERR, 0x20c0),
-        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
-        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
-        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
-        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
-        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
-        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
-        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
-        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
-};
-
-static struct intc_group intca_groups[] __initdata = {
-        INTC_GROUP(DMAC_1, DMAC_1_DEI0,
-                   DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
-        INTC_GROUP(DMAC_2, DMAC_2_DEI4,
-                   DMAC_2_DEI5, DMAC_2_DADERR),
-        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
-                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
-        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
-                   DMAC2_2_DEI5, DMAC2_2_DADERR),
-        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
-                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
-        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
-                   DMAC3_2_DEI5, DMAC3_2_DADERR),
-        INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
-        INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
-        INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
-        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
-                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
-        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
-};
-
-static struct intc_mask_reg intca_mask_registers[] __initdata = {
-        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
-          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
-            ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
-        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
-          { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
-            DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
-        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
-          { PINT1, PINT2, 0, 0,
-            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
-        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
-          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
-            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
-        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
-          { DDM, 0, 0, 0,
-            0, 0, ETM11_FULL, ETM11_ACQCMP } },
-        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
-          { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
-            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
-        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
-          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
-            0, 0, MSIOF2, 0 } },
-        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
-        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            TTI20, USBDMAC_USHDMI, SPU, SIU } },
-        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
-          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
-            CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
-        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
-          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
-            0, 0, 0, 0 } },
-        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
-          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
-            LCRC, MSU_MSU2, IREM, MSU_MSU } },
-        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
-          { 0, 0, TPU0, TPU1,
-            TPU2, TPU3, TPU4, 0 } },
-        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            MISTY, CMT3, RWDT1, RWDT0 } },
-};
-
-static struct intc_prio_reg intca_prio_registers[] __initdata = {
-        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
-        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
-        { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
-                                              CMT1_CMT11, ARM11 } },
-        { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
-                                              CMT1_CMT12, TPU4 } },
-        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
-                                              MFI_MFIM, USBHS } },
-        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
-                                              0, CMT1_CMT10 } },
-        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
-                                              SCIFA2, SCIFA3 } },
-        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
-                                              FLCTL, SDHI0 } },
-        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
-        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
-        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
-        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
-        { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
-        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
-        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
-};
-
-static struct intc_desc intca_desc __initdata = {
-        .name = "sh7367-intca",
-        .force_enable = ENABLED,
-        .force_disable = DISABLED,
-        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
-                           intca_mask_registers, intca_prio_registers,
-                           NULL, NULL),
-};
-
-INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
-                 INTC_VECT, "sh7367-intca-irq-pins");
-
-enum {
-        UNUSED_INTCS = 0,
-
-        INTCS,
-
-        /* interrupt sources INTCS */
-        VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
-        VIO3_VOU,
-        RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
-        VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
-        VPU,
-        SGX530,
-        _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
-        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
-        IPMMU_IPMMUB, IPMMU_IPMMUS,
-        RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
-        MSIOF,
-        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
-        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
-        CMT,
-        TSIF,
-        IPMMUI,
-        MVI3,
-        ICB,
-        PEP,
-        ASA,
-        BEM,
-        VE2HO,
-        HQE,
-        JPEG,
-        LCDC,
-
-        /* interrupt groups INTCS */
-        _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
-};
-
-static struct intc_vect intcs_vectors[] = {
-        INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
-        INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
-        INTCS_VECT(VIO3_VOU, 0x780),
-        INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
-        INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
-        INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
-        INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
-        INTCS_VECT(VPU, 0x980),
-        INTCS_VECT(SGX530, 0x9e0),
-        INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
-        INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
-        INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
-        INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
-        INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
-        INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
-        INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
-        INTCS_VECT(MSIOF, 0xd20),
-        INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
-        INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
-        INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
-        INTCS_VECT(TMU_TUNI2, 0xec0),
-        INTCS_VECT(CMT, 0xf00),
-        INTCS_VECT(TSIF, 0xf20),
-        INTCS_VECT(IPMMUI, 0xf60),
-        INTCS_VECT(MVI3, 0x420),
-        INTCS_VECT(ICB, 0x480),
-        INTCS_VECT(PEP, 0x4a0),
-        INTCS_VECT(ASA, 0x4c0),
-        INTCS_VECT(BEM, 0x4e0),
-        INTCS_VECT(VE2HO, 0x520),
-        INTCS_VECT(HQE, 0x540),
-        INTCS_VECT(JPEG, 0x560),
-        INTCS_VECT(LCDC, 0x580),
-
-        INTC_VECT(INTCS, 0xf80),
-};
-
-static struct intc_group intcs_groups[] __initdata = {
-        INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
-                   _2DDMAC_2DDM2, _2DDMAC_2DDM3),
-        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
-                   RTDMAC_1_DEI2, RTDMAC_1_DEI3),
-        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
-        INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
-        INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
-        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
-        INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
-        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
-};
-
-static struct intc_mask_reg intcs_mask_registers[] = {
-        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
-          { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
-            VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
-        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
-          { VIO3_VOU, 0, VE2HO, VPU,
-            0, 0, 0, 0 } },
-        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
-          { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
-            BEM, ASA, PEP, ICB } },
-        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
-          { 0, 0, MVI3, 0,
-            JPEG, HQE, 0, LCDC } },
-        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
-          { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
-            RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
-        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
-          { 0, 0, MSIOF, 0,
-            SGX530, 0, 0, 0 } },
-        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
-          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
-            0, 0, 0, 0 } },
-        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
-          { 0, 0, 0, CMT,
-            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
-        { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
-          { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
-            0, 0, 0, 0 } },
-        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
-          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
-            0, 0, IPMMUI, TSIF } },
-        { 0xffd20104, 0, 16, /* INTAMASK */
-          { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, INTCS } },
-};
-
-/* Priority is needed for INTCA to receive the INTCS interrupt */
-static struct intc_prio_reg intcs_prio_registers[] = {
-        { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
-        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
-        { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
-        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
-        { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
-        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
-                                              TMU_TUNI2, 0 } },
-        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
-        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
-        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
-        { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
-        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
-        { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
-};
-
-static struct resource intcs_resources[] __initdata = {
-        [0] = {
-                .start  = 0xffd20000,
-                .end    = 0xffd2ffff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct intc_desc intcs_desc __initdata = {
-        .name = "sh7367-intcs",
-        .resource = intcs_resources,
-        .num_resources = ARRAY_SIZE(intcs_resources),
-        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
-                           intcs_prio_registers, NULL, NULL),
-};
-
-static void intcs_demux(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *reg = (void *)irq_get_handler_data(irq);
-        unsigned int evtcodeas = ioread32(reg);
-
-        generic_handle_irq(intcs_evt2irq(evtcodeas));
-}
-
-void __init sh7367_init_irq(void)
-{
-        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
-
-        register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_desc);
-        register_intc_controller(&intcs_desc);
-
-        /* demux using INTEVTSA */
-        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
-        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
-}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
deleted file mode 100644
index b84a460a3405..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * sh7377 processor support - INTC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sh_intc.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-enum {
-        UNUSED_INTCA = 0,
-        ENABLED,
-        DISABLED,
-
-        /* interrupt sources INTCA */
-        DIRC,
-        _2DG,
-        CRYPT_STD,
-        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
-        AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
-        MFI_MFIM, MFI_MFIS,
-        BBIF1, BBIF2,
-        USBDMAC_USHDMI,
-        USBHS_USHI0, USBHS_USHI1,
-        _3DG_SGX540,
-        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
-        KEYSC_KEY,
-        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
-        MSIOF2, MSIOF1,
-        SCIFA4, SCIFA5, SCIFB,
-        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-        SDHI0,
-        SDHI1,
-        MSU_MSU, MSU_MSU2,
-        IRREM,
-        MSUG,
-        IRDA,
-        TPU0, TPU1, TPU2, TPU3, TPU4,
-        LCRC,
-        PINTCA_PINT1, PINTCA_PINT2,
-        TTI20,
-        MISTY,
-        DDM,
-        RWDT0, RWDT1,
-        DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
-        DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
-        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
-        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
-        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
-        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
-        SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
-        ICUSB_ICUSB0, ICUSB_ICUSB1,
-        ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
-        SPU2_SPU0, SPU2_SPU1,
-        FSI,
-        FMSI,
-        SCUV,
-        IPMMU_IPMMUB,
-        AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
-        MFIS2,
-        CPORTR2S,
-        CMT14, CMT15,
-        SCIFA6,
-
-        /* interrupt groups INTCA */
-        DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
-        AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
-        ICUSB, ICUDMC
-};
-
-static struct intc_vect intca_vectors[] __initdata = {
-        INTC_VECT(DIRC, 0x0560),
-        INTC_VECT(_2DG, 0x05e0),
-        INTC_VECT(CRYPT_STD, 0x0700),
-        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
-        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
-        INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
-        INTC_VECT(AP_ARM_COMMRX, 0x0860),
-        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
-        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
-        INTC_VECT(USBDMAC_USHDMI, 0x0a00),
-        INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
-        INTC_VECT(_3DG_SGX540, 0x0a60),
-        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
-        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
-        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
-        INTC_VECT(KEYSC_KEY, 0x0be0),
-        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
-        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
-        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
-        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
-        INTC_VECT(SCIFB, 0x0d60),
-        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
-        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
-        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
-        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
-        INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
-        INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
-        INTC_VECT(IRREM, 0x0f60),
-        INTC_VECT(MSUG, 0x0fa0),
-        INTC_VECT(IRDA, 0x0480),
-        INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
-        INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
-        INTC_VECT(TPU4, 0x0520),
-        INTC_VECT(LCRC, 0x0540),
-        INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
-        INTC_VECT(TTI20, 0x1100),
-        INTC_VECT(MISTY, 0x1120),
-        INTC_VECT(DDM, 0x1140),
-        INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
-        INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
-        INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
-        INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
-        INTC_VECT(DMAC_2_DADERR, 0x20c0),
-        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
-        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
-        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
-        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
-        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
-        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
-        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
-        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
-        INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
-        INTC_VECT(SHWYSTAT_COM, 0x1340),
-        INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
-        INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
-        INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
-        INTC_VECT(FSI, 0x1840),
-        INTC_VECT(FMSI, 0x1860),
-        INTC_VECT(SCUV, 0x1880),
-        INTC_VECT(IPMMU_IPMMUB, 0x1900),
-        INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
-        INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
-        INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
-        INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
-        INTC_VECT(MFIS2, 0x1a00),
-        INTC_VECT(CPORTR2S, 0x1a20),
-        INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
-        INTC_VECT(SCIFA6, 0x1a80),
-};
-
-static struct intc_group intca_groups[] __initdata = {
-        INTC_GROUP(DMAC_1, DMAC_1_DEI0,
-                   DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
-        INTC_GROUP(DMAC_2, DMAC_2_DEI4,
-                   DMAC_2_DEI5, DMAC_2_DADERR),
-        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
-                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
-        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
-                   DMAC2_2_DEI5, DMAC2_2_DADERR),
-        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
-                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
-        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
-                   DMAC3_2_DEI5, DMAC3_2_DADERR),
-        INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
-        INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
-        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
-        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
-                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
-        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
-        INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
-        INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
-        INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
-};
-
-static struct intc_mask_reg intca_mask_registers[] __initdata = {
-        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
-          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
-            AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
-        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
-          { _2DG, CRYPT_STD, DIRC, 0,
-            DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
-        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
-          { PINTCA_PINT1, PINTCA_PINT2, 0, 0,
-            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
-        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
-          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
-            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
-        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
-          { DDM, 0, 0, 0,
-            0, 0, 0, 0 } },
-        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
-          { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
-            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
-        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
-          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
-            0, 0, MSIOF2, 0 } },
-        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
-        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            TTI20, USBDMAC_USHDMI, 0, MSUG } },
-        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
-          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
-            CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
-        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
-          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
-            0, 0, 0, 0 } },
-        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
-          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
-            LCRC, MSU_MSU2, IRREM, MSU_MSU } },
-        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
-          { 0, 0, TPU0, TPU1,
-            TPU2, TPU3, TPU4, 0 } },
-        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-          { 0, 0, 0, 0,
-            MISTY, CMT3, RWDT1, RWDT0 } },
-        { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
-          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
-            0, 0, 0, 0 } },
-        { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
-          { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
-            ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
-        { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
-          { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
-            SCUV, 0, 0, 0 } },
-        { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
-          { IPMMU_IPMMUB, 0, 0, 0,
-            AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
-            AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
-        { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
-          { MFIS2, CPORTR2S, CMT14, CMT15,
-            SCIFA6, 0, 0, 0 } },
-};
-
-static struct intc_prio_reg intca_prio_registers[] __initdata = {
-        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
-        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
-        { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
-                                              CMT1_CMT11, AP_ARM1 } },
-        { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
-                                              CMT1_CMT12, TPU4 } },
-        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
-                                              MFI_MFIM, USBHS } },
-        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
-                                              _3DG_SGX540, CMT1_CMT10 } },
-        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
-                                              SCIFA2, SCIFA3 } },
-        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
-                                              FLCTL, SDHI0 } },
-        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
-        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
-        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
-        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
-        { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
-        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
-        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
-        { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
-        { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
-        { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
-        { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
-        { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
-        { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
-        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
-        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
-                                               CMT14, CMT15 } },
-        { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
-};
-
-static struct intc_desc intca_desc __initdata = {
-        .name = "sh7377-intca",
-        .force_enable = ENABLED,
-        .force_disable = DISABLED,
-        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
-                           intca_mask_registers, intca_prio_registers,
-                           NULL, NULL),
-};
-
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTC_VECT, "sh7377-intca-irq-pins");
-
-/* this macro ignore entry which is also in INTCA */
-#define __IGNORE(a...)
-#define __IGNORE0(a...) 0
-
-enum {
-        UNUSED_INTCS = 0,
-
-        INTCS,
-
-        /* interrupt sources INTCS */
-        VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
-        RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
-        CEU,
-        BEU_BEU0, BEU_BEU1, BEU_BEU2,
-        __IGNORE(MFI)
-        __IGNORE(BBIF2)
-        VPU,
-        TSIF1,
-        __IGNORE(SGX540)
-        _2DDMAC,
-        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
-        IPMMU_IPMMUR, IPMMU_IPMMUR2,
-        RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
-        __IGNORE(KEYSC)
-        __IGNORE(TTI20)
-        __IGNORE(MSIOF)
-        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
-        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
-        CMT0,
-        TSIF0,
-        __IGNORE(CMT2)
-        LMB,
-        __IGNORE(MSUG)
-        __IGNORE(MSU_MSU, MSU_MSU2)
-        __IGNORE(CTI)
-        MVI3,
-        __IGNORE(RWDT0)
-        __IGNORE(RWDT1)
-        ICB,
-        PEP,
-        ASA,
-        __IGNORE(_2DG)
-        HQE,
-        JPU,
-        LCDC0,
-        __IGNORE(LCRC)
-        RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
-        RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
-        FRC,
-        LCDC1,
-        CSIRX,
-        DSITX_DSITX0, DSITX_DSITX1,
-        __IGNORE(SPU2_SPU0, SPU2_SPU1)
-        __IGNORE(FSI)
-        __IGNORE(FMSI)
-        __IGNORE(SCUV)
-        TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
-        TSIF2,
-        CMT4,
-        __IGNORE(MFIS2)
-        CPORTS2R,
-
-        /* interrupt groups INTCS */
-        RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
-        IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
-};
-
-#define INTCS_INTVECT 0x0F80
-static struct intc_vect intcs_vectors[] __initdata = {
-        INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
-        INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
-        INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
-        INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
-        INTCS_VECT(CEU, 0x0880),
-        INTCS_VECT(BEU_BEU0, 0x08A0),
-        INTCS_VECT(BEU_BEU1, 0x08C0),
-        INTCS_VECT(BEU_BEU2, 0x08E0),
-        __IGNORE(INTCS_VECT(MFI, 0x0900))
-        __IGNORE(INTCS_VECT(BBIF2, 0x0960))
-        INTCS_VECT(VPU, 0x0980),
-        INTCS_VECT(TSIF1, 0x09A0),
-        __IGNORE(INTCS_VECT(SGX540, 0x09E0))
-        INTCS_VECT(_2DDMAC, 0x0A00),
-        INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
-        INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
-        INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
-        INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
-        INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
-        INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
-        __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
-        __IGNORE(INTCS_VECT(TTI20, 0x0C80))
-        __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
-        INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
-        INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
-        INTCS_VECT(TMU_TUNI0, 0x0E80),
-        INTCS_VECT(TMU_TUNI1, 0x0EA0),
-        INTCS_VECT(TMU_TUNI2, 0x0EC0),
-        INTCS_VECT(CMT0, 0x0F00),
-        INTCS_VECT(TSIF0, 0x0F20),
-        __IGNORE(INTCS_VECT(CMT2, 0x0F40))
-        INTCS_VECT(LMB, 0x0F60),
-        __IGNORE(INTCS_VECT(MSUG, 0x0F80))
-        __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
-        __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
-        __IGNORE(INTCS_VECT(CTI, 0x0400))
-        INTCS_VECT(MVI3, 0x0420),
-        __IGNORE(INTCS_VECT(RWDT0, 0x0440))
-        __IGNORE(INTCS_VECT(RWDT1, 0x0460))
-        INTCS_VECT(ICB, 0x0480),
-        INTCS_VECT(PEP, 0x04A0),
-        INTCS_VECT(ASA, 0x04C0),
-        __IGNORE(INTCS_VECT(_2DG, 0x04E0))
-        INTCS_VECT(HQE, 0x0540),
-        INTCS_VECT(JPU, 0x0560),
-        INTCS_VECT(LCDC0, 0x0580),
-        __IGNORE(INTCS_VECT(LCRC, 0x05A0))
-        INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
-        INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
-        INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
-        INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
-        INTCS_VECT(FRC, 0x1700),
-        INTCS_VECT(LCDC1, 0x1780),
-        INTCS_VECT(CSIRX, 0x17A0),
-        INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
-        __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
-        __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
-        __IGNORE(INTCS_VECT(FSI, 0x1840))
-        __IGNORE(INTCS_VECT(FMSI, 0x1860))
-        __IGNORE(INTCS_VECT(SCUV, 0x1880))
-        INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
-        INTCS_VECT(TMU1_TUNI12, 0x1940),
-        INTCS_VECT(TSIF2, 0x1960),
-        INTCS_VECT(CMT4, 0x1980),
-        __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
-        INTCS_VECT(CPORTS2R, 0x1A20),
-
-        INTC_VECT(INTCS, INTCS_INTVECT),
-};
-
-static struct intc_group intcs_groups[] __initdata = {
-        INTC_GROUP(RTDMAC1_1,
-                   RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
-                   RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
-        INTC_GROUP(RTDMAC1_2,
-                   RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
-        INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
-        INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
-        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
-        __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
-        INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
-        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
-        INTC_GROUP(RTDMAC2_1,
-                   RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
-                   RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
-        INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
-        INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
-        __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
-        INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
-};
-
-static struct intc_mask_reg intcs_mask_registers[] __initdata = {
-        { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS  */
-          { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
-            VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
-        { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
-          { 0, 0, 0, VPU,
-            __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
-        { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
-          { 0, 0, 0, _2DDMAC,
-            __IGNORE0(_2DG), ASA, PEP, ICB } },
-        { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
-          { 0, 0, MVI3, __IGNORE0(CTI),
-            JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
-        { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
-          { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
-            RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
-        __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
-          { 0, 0, MSIOF, 0,
-            SGX540, 0, TTI20, 0 } })
-        { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
-          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
-            0, 0, 0, 0 } },
-        __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
-          { 0, 0, 0, 0,
-            0, MSU_MSU, MSU_MSU2, MSUG } })
-        { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
-          { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
-            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
-        { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
-          { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
-            0, 0, 0, 0 } },
-        { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
-          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
-            0, TSIF1, LMB, TSIF0 } },
-        { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
-          { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
-            RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
-        { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
-          { FRC, 0, 0, 0,
-            LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
-        __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
-          {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
-           SCUV, 0, 0, 0 } })
-        { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
-          { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
-            CMT4, 0, 0, 0 } },
-        { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
-          { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
-            0, 0, 0, 0 } },
-        { 0xFFD20104, 0, 16, /* INTAMASK */
-          { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, INTCS } }
-};
-
-static struct intc_prio_reg intcs_prio_registers[] __initdata = {
-        /* IPRAS */
-        { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
-        /* IPRBS */
-        { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
-        /* IPRCS */
-        __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
-        /* IPRES */
-        { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
-        /* IPRFS */
-        { 0xFFD20014, 0, 16, 4,
-          { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
-        /* IPRGS */
-        { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
-        /* IPRHS */
-        { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
-        /* IPRIS */
-        { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
-        /* IPRJS */
-        __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
-        /* IPRKS */
-        { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
-        /* IPRLS */
-        { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
-        /* IPRMS */
-        { 0xFFD20030, 0, 16, 4,
-          { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
-        /* IPRAS3 */
-        { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
-        /* IPRBS3 */
-        { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
-        /* IPRIS3 */
-        { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
-        /* IPRJS3 */
-        { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
-        /* IPRKS3 */
-        __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
-        /* IPRLS3 */
-        __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
-        /* IPRMS3 */
-        { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
-        /* IPRNS3 */
-        { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
-        /* IPROS3 */
-        { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
-};
-
-static struct resource intcs_resources[] __initdata = {
-        [0] = {
-                .start  = 0xffd20000,
-                .end    = 0xffd500ff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct intc_desc intcs_desc __initdata = {
-        .name = "sh7377-intcs",
-        .resource = intcs_resources,
-        .num_resources = ARRAY_SIZE(intcs_resources),
-        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
-                           intcs_mask_registers, intcs_prio_registers,
-                           NULL, NULL),
-};
-
-static void intcs_demux(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *reg = (void *)irq_get_handler_data(irq);
-        unsigned int evtcodeas = ioread32(reg);
-
-        generic_handle_irq(intcs_evt2irq(evtcodeas));
-}
-
-#define INTEVTSA 0xFFD20100
-void __init sh7377_init_irq(void)
-{
-        void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
-
-        register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_desc);
-        register_intc_controller(&intcs_desc);
-
-        /* demux using INTEVTSA */
-        irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
-        irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
-}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index cbc26ba2a0a2..9513234d322b 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -140,7 +140,7 @@ enum {
         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-        FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+        FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 
         /* GPSR5 */
@@ -176,7 +176,7 @@ enum {
         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-        FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+        FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
         FN_SCIF_CLK, FN_TCLK0_C,
 
         /* IPSR1 */
@@ -447,7 +447,7 @@ enum {
         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-        PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+        USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
         SCIF_CLK_MARK, TCLK0_C_MARK,
 
         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(A18_MARK, FN_A18),
         PINMUX_DATA(A19_MARK, FN_A19),
 
-        PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+        PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(A19),
 
         /* IPSR0 */
-        GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+        GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
         GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
         GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
         GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 GP_4_30_FN, FN_IP8_18,
                 GP_4_29_FN, FN_IP8_17_16,
                 GP_4_28_FN, FN_IP0_2_0,
-                GP_4_27_FN, FN_PENC1,
-                GP_4_26_FN, FN_PENC0,
+                GP_4_27_FN, FN_USB_PENC1,
+                GP_4_26_FN, FN_USB_PENC0,
                 GP_4_25_FN, FN_IP8_15_12,
                 GP_4_24_FN, FN_IP8_11_8,
                 GP_4_23_FN, FN_IP8_7_4,
@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
                 /* IP0_2_0 [3] */
-                FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+                FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
         },
         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
deleted file mode 100644
index c0c137f39052..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ /dev/null
@@ -1,1727 +0,0 @@
-/*
- * sh7367 processor support - PFC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/sh7367.h>
-
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx),           \
-        PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx),    \
-        PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),   \
-        PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),   \
-        PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),   \
-        PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx),   \
-        PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
-
-enum {
-        PINMUX_RESERVED = 0,
-
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
-        PINMUX_DATA_END,
-
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
-        PINMUX_INPUT_END,
-
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
-        PINMUX_OUTPUT_END,
-
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
-        PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
-        PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
-        PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
-        PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
-        PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
-        PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
-        PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
-        PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
-        PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
-
-        MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
-        PINMUX_FUNCTION_END,
-
-        PINMUX_MARK_BEGIN,
-        /* Special Pull-up / Pull-down Functions */
-        PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
-        PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
-        PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
-        PORT58_KEYIN6_PU_MARK,
-
-        /* 49-1 */
-        VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
-        CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
-        CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
-        CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
-        CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
-        CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
-        CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
-        RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
-        STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
-        MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
-        XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
-        IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
-        M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
-        XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
-        XCTS1_MARK, SCIFA4_CTS_MARK,
-
-        /* 49-2 */
-        HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
-        HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
-        HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
-        HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
-        HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
-        HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
-        HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
-        HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
-        HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
-        HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
-        HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
-        HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
-        HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
-        HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
-        HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
-        HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
-        B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
-        HSU_SDI_MARK, PORT55_KEYIN3_MARK,
-        HSU_SCO_MARK, PORT56_KEYIN4_MARK,
-        HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
-        HSU_DACK_MARK, PORT58_KEYIN6_MARK,
-        HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
-        HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
-        PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
-        XTALB1L_MARK,
-        GPS_AGC1_MARK, SCIFA0_RTS_MARK,
-        GPS_AGC2_MARK, SCIFA0_SCK_MARK,
-        GPS_AGC3_MARK, SCIFA0_TXD_MARK,
-        GPS_AGC4_MARK, SCIFA0_RXD_MARK,
-        GPS_PWRD_MARK, SCIFA0_CTS_MARK,
-        GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
-        SIUBOMC_MARK, TPU2TO0_MARK,
-        SIUCKB_MARK, TPU2TO1_MARK,
-        SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
-        SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
-        SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
-        SIUBILR_MARK, TPU3TO1_MARK,
-        SIUBIBT_MARK, TPU3TO2_MARK,
-        SIUBISLD_MARK, TPU3TO3_MARK,
-        NMI_MARK, TPU4TO0_MARK,
-        DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
-        IRQ_TMPB_MARK,
-        PWEN_MARK, MFG1_OUT1_MARK,
-        OVCN_MARK, MFG1_IN1_MARK,
-        OVCN2_MARK, MFG1_IN2_MARK,
-
-        /* 49-3 */
-        RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
-        USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
-        SCIFA5_CTS_MARK, MFG0_IN1_MARK,
-        SCIFA5_RTS_MARK, MFG0_IN2_MARK,
-        SCIFA5_RXD_MARK,
-        SCIFA5_TXD_MARK,
-        SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
-        A0_EA0_MARK, BS_MARK,
-        A14_EA14_MARK, PORT102_KEYOUT0_MARK,
-        A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
-        A16_EA16_MARK, PORT104_KEYOUT2_MARK,
-        DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
-        A17_EA17_MARK, PORT105_KEYOUT3_MARK,
-        DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
-        A18_EA18_MARK, PORT106_KEYOUT4_MARK,
-        DV_DL0_MARK, MSIOF0_TSCK_MARK,
-        A19_EA19_MARK, PORT107_KEYOUT5_MARK,
-        DV_DL1_MARK, MSIOF0_TXD_MARK,
-        A20_EA20_MARK, PORT108_KEYIN0_MARK,
-        DV_DL2_MARK, MSIOF0_RSCK_MARK,
-        A21_EA21_MARK, PORT109_KEYIN1_MARK,
-        DV_DL3_MARK, MSIOF0_RSYNC_MARK,
-        A22_EA22_MARK, PORT110_KEYIN2_MARK,
-        DV_DL4_MARK, MSIOF0_MCK0_MARK,
-        A23_EA23_MARK, PORT111_KEYIN3_MARK,
-        DV_DL5_MARK, MSIOF0_MCK1_MARK,
-        A24_EA24_MARK, PORT112_KEYIN4_MARK,
-        DV_DL6_MARK, MSIOF0_RXD_MARK,
-        A25_EA25_MARK, PORT113_KEYIN5_MARK,
-        DV_DL7_MARK, MSIOF0_SS2_MARK,
-        A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
-        D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
-        D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
-        D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
-        D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
-        D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
-        D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
-        CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
-        CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
-        DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
-        A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
-        WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
-        NBRSTOUT_MARK, NBRST_MARK,
-
-        /* 49-4 */
-        RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
-        VIO_VD_MARK, VIO_HD_MARK,
-        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
-        VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
-        VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
-        VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
-        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
-        VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
-        VIO_CKO_MARK,
-        MFG3_IN1_MARK, MFG3_IN2_MARK,
-        M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
-        M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
-        M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
-        M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
-        LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
-        SIUCKA_MARK, MFG0_OUT2_MARK,
-        LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
-        SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
-        LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
-        SIUAOBT_MARK, BBIF2_TSCK1_MARK,
-        LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
-        SIUAOSLD_MARK, BBIF2_TXD1_MARK,
-        LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
-        SIUAISPD_MARK, MFG1_OUT2_MARK,
-        LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
-        SIUAILR_MARK, MFG2_OUT2_MARK,
-        LCDD6_MARK, DV_D6_MARK,
-        SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
-        LCDD7_MARK, DV_D7_MARK,
-        SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
-        LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
-        LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
-        LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
-        LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
-        LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
-        LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
-        LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
-        LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
-        LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
-        LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
-        LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
-        D26_MARK, ED26_MARK,
-        LCDD19_MARK, MSIOF0L_TSYNC_MARK,
-        D27_MARK, ED27_MARK,
-        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
-        D28_MARK, ED28_MARK,
-        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
-        D29_MARK, ED29_MARK,
-        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
-        D30_MARK, ED30_MARK,
-        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
-        D31_MARK, ED31_MARK,
-        LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
-        LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
-
-        /* 49-5 */
-        LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
-        LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
-        LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
-        LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
-        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
-        VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
-        VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
-        VIO_VDR_MARK, VIO_HDR_MARK,
-        VIO_CLKR_MARK, VIO_CKOR_MARK,
-        SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
-        SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
-        SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
-        SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
-        MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
-        MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
-        MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
-        MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
-        MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
-        MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
-        MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
-        MSIOF1_SS1_MARK, EDBGREQ3_MARK,
-        MSIOF1_SS2_MARK,
-        PORT236_IROUT_MARK, IRDA_OUT_MARK,
-        IRDA_IN_MARK, IRDA_FIRSEL_MARK,
-        TPU1TO0_MARK, TS_SPSYNC3_MARK,
-        TPU1TO1_MARK, TS_SDAT3_MARK,
-        TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
-        TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
-        M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
-        M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
-        PORT245_IROUT_MARK, M15_RSW_MARK,
-        SOUT3_MARK, SCIFA2_TXD1_MARK,
-        SIN3_MARK, SCIFA2_RXD1_MARK,
-        XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
-        XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
-        DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-        SDHICLK0_MARK, TCK2_MARK,
-        SDHICD0_MARK,
-        SDHID0_0_MARK, TMS2_MARK,
-        SDHID0_1_MARK, TDO2_MARK,
-        SDHID0_2_MARK, TDI2_MARK,
-        SDHID0_3_MARK, RTCK2_MARK,
-
-        /* 49-6 */
-        SDHICMD0_MARK, TRST2_MARK,
-        SDHIWP0_MARK, EDBGREQ2_MARK,
-        SDHICLK1_MARK, TCK3_MARK,
-        SDHID1_0_MARK, M11_SLCD_SO2_MARK,
-        TS_SPSYNC2_MARK, TMS3_MARK,
-        SDHID1_1_MARK, M9_SLCD_AO2_MARK,
-        TS_SDAT2_MARK, TDO3_MARK,
-        SDHID1_2_MARK, M10_SLCD_CK2_MARK,
-        TS_SDEN2_MARK, TDI3_MARK,
-        SDHID1_3_MARK, M12_SLCD_CE2_MARK,
-        TS_SCK2_MARK, RTCK3_MARK,
-        SDHICMD1_MARK, TRST3_MARK,
-        SDHICLK2_MARK, SCIFB_SCK_MARK,
-        SDHID2_0_MARK, SCIFB_TXD_MARK,
-        SDHID2_1_MARK, SCIFB_CTS_MARK,
-        SDHID2_2_MARK, SCIFB_RXD_MARK,
-        SDHID2_3_MARK, SCIFB_RTS_MARK,
-        SDHICMD2_MARK,
-        RESETOUTS_MARK,
-        DIVLOCK_MARK,
-        PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
-
-        /* specify valid pin states for each pin in GPIO mode */
-
-        /* 49-1 (GPIO) */
-        PORT_DATA_I_PD(0),
-        PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
-        PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
-        PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
-        PORT_DATA_I_PU(13),
-        PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
-        PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
-        PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
-        PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
-        PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
-        PORT_DATA_IO_PU(33),
-        PORT_DATA_O(34),
-        PORT_DATA_I_PU(35),
-        PORT_DATA_O(36),
-        PORT_DATA_I_PU_PD(37),
-
-        /* 49-2 (GPIO) */
-        PORT_DATA_IO_PU_PD(38),
-        PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
-        PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
-        PORT_DATA_O(46), PORT_DATA_O(47),
-        PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
-        PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
-        PORT_DATA_O(53),
-        PORT_DATA_IO_PD(54),
-        PORT_DATA_I_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),
-        PORT_DATA_I_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),
-        PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
-        PORT_DATA_O(63),
-        PORT_DATA_I_PU(64),
-        PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
-        PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
-        PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
-        PORT_DATA_I_PD(74),
-        PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
-        PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
-        PORT_DATA_O(79),
-        PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
-        PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
-        PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
-        PORT_DATA_I_PD(87),
-        PORT_DATA_IO_PU_PD(88),
-        PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
-
-        /* 49-3 (GPIO) */
-        PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
-        PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
-        PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
-        PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
-        PORT_DATA_IO_PD(107),
-        PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
-        PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
-        PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
-        PORT_DATA_IO_PU_PD(114),
-        PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
-        PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
-        PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
-        PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
-        PORT_DATA_IO_PU(130),
-        PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
-        PORT_DATA_IO_PU(134),
-        PORT_DATA_O(135), PORT_DATA_O(136),
-        PORT_DATA_I_PU_PD(137),
-        PORT_DATA_IO(138),
-        PORT_DATA_IO_PU_PD(139),
-        PORT_DATA_IO(140), PORT_DATA_IO(141),
-        PORT_DATA_I_PU(142),
-        PORT_DATA_O(143), PORT_DATA_O(144),
-        PORT_DATA_I_PU(145),
-
-        /* 49-4 (GPIO) */
-        PORT_DATA_O(146),
-        PORT_DATA_I_PU_PD(147),
-        PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
-        PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
-        PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
-        PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
-        PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
-        PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
-        PORT_DATA_IO_PU_PD(167),
-        PORT_DATA_O(168),
-        PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
-        PORT_DATA_O(171),
-        PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
-        PORT_DATA_O(174),
-        PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
-        PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
-        PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
-        PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
-        PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
-        PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
-        PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
-        PORT_DATA_O(199),
-        PORT_DATA_IO_PD(200),
-
-        /* 49-5 (GPIO) */
-        PORT_DATA_O(201),
-        PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
-        PORT_DATA_I(204),
-        PORT_DATA_O(205),
-        PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
-        PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
-        PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
-        PORT_DATA_O(217),
-        PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
-        PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
-        PORT_DATA_I_PD(223),
-        PORT_DATA_I_PU_PD(224),
-        PORT_DATA_O(225),
-        PORT_DATA_IO_PD(226),
-        PORT_DATA_IO_PU_PD(227),
-        PORT_DATA_I_PD(228),
-        PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
-        PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
-        PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_I_PU_PD(235),
-        PORT_DATA_O(236),
-        PORT_DATA_I_PD(237),
-        PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
-        PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
-        PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
-        PORT_DATA_O(244),
-        PORT_DATA_IO_PU_PD(245),
-        PORT_DATA_O(246),
-        PORT_DATA_I_PD(247),
-        PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_I_PU_PD(249),
-        PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
-        PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
-        PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
-        PORT_DATA_IO_PU_PD(256),
-
-        /* 49-6 (GPIO) */
-        PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
-        PORT_DATA_IO_PD(259),
-        PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
-        PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
-        PORT_DATA_O(265),
-        PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
-        PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
-        PORT_DATA_O(271),
-        PORT_DATA_I_PD(272),
-
-        /* Special Pull-up / Pull-down Functions */
-        PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT48_FN2, PORT48_IN_PU),
-        PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT49_FN2, PORT49_IN_PU),
-        PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT50_FN2, PORT50_IN_PU),
-        PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT55_FN2, PORT55_IN_PU),
-        PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT56_FN2, PORT56_IN_PU),
-        PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT57_FN2, PORT57_IN_PU),
-        PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT58_FN2, PORT58_IN_PU),
-
-        /* 49-1 (FN) */
-        PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
-        PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
-        PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
-        PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
-        PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
-        PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
-        PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
-        PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
-        PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
-        PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
-        PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
-        PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
-        PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
-        PINMUX_DATA(SIN2_MARK, PORT12_FN2),
-        PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
-        PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
-        PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
-        PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
-        PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
-        PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
-        PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
-        PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
-        PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
-        PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
-        PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
-        PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
-        PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
-        PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
-        PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
-        PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
-        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-        PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
-        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-        PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
-        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-        PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
-        PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
-        PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
-        PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
-        PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
-        PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
-        PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
-        PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
-        PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
-        PINMUX_DATA(IDIO_MARK, PORT33_FN1),
-        PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
-        PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
-        PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
-        PINMUX_DATA(SIN1_MARK, PORT35_FN1),
-        PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
-        PINMUX_DATA(XWUP_MARK, PORT35_FN3),
-        PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
-        PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
-        PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
-        PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
-        PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
-
-        /* 49-2 (FN) */
-        PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
-        PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
-        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
-        PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
-        PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
-        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
-        PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
-        PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
-        PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
-        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
-        PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
-        PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
-        PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
-        PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
-        PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
-        PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
-        PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
-        PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
-        PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
-        PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
-        PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
-        PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
-        PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
-        PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
-        PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
-        PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
-        PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
-        PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
-        PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
-        PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
-        PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
-        PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
-        PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
-        PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
-        PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
-        PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
-        PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
-        PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
-        PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
-        PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
-        PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
-        PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
-        PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
-        PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
-        PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
-        PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
-        PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
-        PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
-        PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
-        PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
-        PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
-        PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
-        PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
-        PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
-        PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
-        PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
-        PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
-        PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
-        PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
-        PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
-        PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
-        PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
-        PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
-        PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
-        PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
-        PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
-        PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
-        PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
-        PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
-        PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
-        PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
-        PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
-        PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
-        PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
-        PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
-        PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
-        PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
-        PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
-        PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
-        PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
-        PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
-        PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
-        PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
-        PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
-        PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
-        PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
-        PINMUX_DATA(NMI_MARK, PORT83_FN1),
-        PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
-        PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
-        PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
-        PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
-        PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
-        PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
-        PINMUX_DATA(PWEN_MARK, PORT88_FN1),
-        PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
-        PINMUX_DATA(OVCN_MARK, PORT89_FN1),
-        PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
-        PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
-        PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
-
-        /* 49-3 (FN) */
-        PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
-        PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
-        PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
-        PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
-        PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
-        PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
-        PINMUX_DATA(IDIN_MARK, PORT95_FN1),
-        PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
-        PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
-        PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
-        PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
-        PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
-        PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
-        PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
-        PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
-        PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
-        PINMUX_DATA(BS_MARK, PORT101_FN2),
-        PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
-        PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
-        PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
-        PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
-        PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
-        PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
-        PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
-        PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
-        PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
-        PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
-        PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
-        PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
-        PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
-        PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
-        PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
-        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
-        PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
-        PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
-        PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
-        PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
-        PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
-        PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
-        PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
-        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
-        PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
-        PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
-        PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
-        PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
-        PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
-        PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
-        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
-        PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
-        PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
-        PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
-        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
-        PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
-        PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
-        PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
-        PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
-        PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
-        PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
-        PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
-        PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
-        PINMUX_DATA(A26_MARK, PORT114_FN1),
-        PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
-        PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
-        PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
-        PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
-        PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
-        PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
-        PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
-        PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
-        PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
-        PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
-        PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
-        PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
-        PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
-        PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
-        PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
-        PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
-        PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
-        PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
-        PINMUX_DATA(CS4_MARK, PORT131_FN1),
-        PINMUX_DATA(CS5A_MARK, PORT132_FN1),
-        PINMUX_DATA(CS5B_MARK, PORT133_FN1),
-        PINMUX_DATA(FCE1_MARK, PORT133_FN2),
-        PINMUX_DATA(CS6B_MARK, PORT134_FN1),
-        PINMUX_DATA(XCS2_MARK, PORT134_FN2),
-        PINMUX_DATA(FCE0_MARK, PORT135_FN1),
-        PINMUX_DATA(CS6A_MARK, PORT136_FN1),
-        PINMUX_DATA(DACK0_MARK, PORT136_FN2),
-        PINMUX_DATA(WAIT_MARK, PORT137_FN1),
-        PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
-        PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
-        PINMUX_DATA(A27_MARK, PORT139_FN1),
-        PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
-        PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
-        PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
-        PINMUX_DATA(FRB_MARK, PORT142_FN1),
-        PINMUX_DATA(CKO_MARK, PORT143_FN1),
-        PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
-        PINMUX_DATA(NBRST_MARK, PORT145_FN1),
-
-        /* 49-4 (FN) */
-        PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
-        PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
-        PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
-        PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
-        PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
-        PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
-        PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
-        PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
-        PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
-        PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
-        PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
-        PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
-        PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
-        PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
-        PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
-        PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
-        PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
-        PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
-        PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
-        PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
-        PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
-        PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
-        PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
-        PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
-        PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
-        PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
-        PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
-        PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
-        PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
-        PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
-        PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
-        PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
-        PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
-        PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
-        PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
-        PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
-        PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
-        PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
-        PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
-        PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
-        PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
-        PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
-        PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
-        PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
-        PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
-        PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
-        PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
-        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
-        PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
-        PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
-        PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
-        PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
-        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
-        PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
-        PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
-        PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
-        PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
-        PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
-        PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
-        PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
-        PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
-        PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
-        PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
-        PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
-        PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
-        PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
-        PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
-        PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
-        PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
-        PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
-        PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
-        PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
-        PINMUX_DATA(XWR2_MARK, PORT181_FN7),
-        PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
-        PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
-        PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
-        PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
-        PINMUX_DATA(XWR3_MARK, PORT182_FN7),
-        PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
-        PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
-        PINMUX_DATA(D16_MARK, PORT183_FN6),
-        PINMUX_DATA(ED16_MARK, PORT183_FN7),
-        PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
-        PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
-        PINMUX_DATA(D17_MARK, PORT184_FN6),
-        PINMUX_DATA(ED17_MARK, PORT184_FN7),
-        PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
-        PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
-        PINMUX_DATA(D18_MARK, PORT185_FN6),
-        PINMUX_DATA(ED18_MARK, PORT185_FN7),
-        PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
-        PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
-        PINMUX_DATA(D19_MARK, PORT186_FN6),
-        PINMUX_DATA(ED19_MARK, PORT186_FN7),
-        PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
-        PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
-        PINMUX_DATA(D20_MARK, PORT187_FN6),
-        PINMUX_DATA(ED20_MARK, PORT187_FN7),
-        PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
-        PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
-        PINMUX_DATA(D21_MARK, PORT188_FN6),
-        PINMUX_DATA(ED21_MARK, PORT188_FN7),
-        PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
-        PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
-        PINMUX_DATA(D22_MARK, PORT189_FN6),
-        PINMUX_DATA(ED22_MARK, PORT189_FN7),
-        PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
-        PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
-        PINMUX_DATA(D23_MARK, PORT190_FN6),
-        PINMUX_DATA(ED23_MARK, PORT190_FN7),
-        PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
-        PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
-        PINMUX_DATA(D24_MARK, PORT191_FN6),
-        PINMUX_DATA(ED24_MARK, PORT191_FN7),
-        PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
-        PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
-        PINMUX_DATA(D25_MARK, PORT192_FN6),
-        PINMUX_DATA(ED25_MARK, PORT192_FN7),
-        PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
-        PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
-        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
-        PINMUX_DATA(D26_MARK, PORT193_FN6),
-        PINMUX_DATA(ED26_MARK, PORT193_FN7),
-        PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
-        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
-        PINMUX_DATA(D27_MARK, PORT194_FN6),
-        PINMUX_DATA(ED27_MARK, PORT194_FN7),
-        PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
-        PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
-        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
-        PINMUX_DATA(D28_MARK, PORT195_FN6),
-        PINMUX_DATA(ED28_MARK, PORT195_FN7),
-        PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
-        PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
-        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
-        PINMUX_DATA(D29_MARK, PORT196_FN6),
-        PINMUX_DATA(ED29_MARK, PORT196_FN7),
-        PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
-        PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
-        PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
-        PINMUX_DATA(D30_MARK, PORT197_FN6),
-        PINMUX_DATA(ED30_MARK, PORT197_FN7),
-        PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
-        PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
-        PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
-        PINMUX_DATA(D31_MARK, PORT198_FN6),
-        PINMUX_DATA(ED31_MARK, PORT198_FN7),
-        PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
-        PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
-        PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
-        PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
-        PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
-        PINMUX_DATA(DACK2_MARK, PORT200_FN2),
-        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
-
-        /* 49-5 (FN) */
-        PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
-        PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
-        PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
-        PINMUX_DATA(DACK3_MARK, PORT201_FN4),
-        PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
-        PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
-        PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
-        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
-        PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
-        PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
-        PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
-        PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
-        PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
-        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
-        PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
-        PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
-        PINMUX_DATA(DACK1_MARK, PORT205_FN3),
-        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
-        PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
-        PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
-        PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
-        PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
-        PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
-        PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
-        PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
-        PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
-        PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
-        PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
-        PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
-        PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
-        PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
-        PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
-        PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
-        PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
-        PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
-        PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
-        PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
-        PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
-        PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
-        PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
-        PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
-        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
-        PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
-        PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
-        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
-        PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
-        PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
-        PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
-        PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
-        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
-        PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
-        PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
-        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
-        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
-        PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
-        PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
-        PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
-        PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
-        PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
-        PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
-        PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
-        PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
-        PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
-        PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
-        PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
-        PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
-        PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
-        PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
-        PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
-        PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
-        PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
-        PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
-        PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
-        PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
-        PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
-        PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
-        PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
-        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
-        PINMUX_DATA(SIN3_MARK, PORT247_FN1),
-        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
-        PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
-        PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
-        PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
-        PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
-        PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
-        PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
-        PINMUX_DATA(DINT_MARK, PORT250_FN1),
-        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
-        PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
-        PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
-        PINMUX_DATA(TCK2_MARK, PORT251_FN2),
-        PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
-        PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
-        PINMUX_DATA(TMS2_MARK, PORT253_FN2),
-        PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
-        PINMUX_DATA(TDO2_MARK, PORT254_FN2),
-        PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
-        PINMUX_DATA(TDI2_MARK, PORT255_FN2),
-        PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
-        PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
-
-        /* 49-6 (FN) */
-        PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
-        PINMUX_DATA(TRST2_MARK, PORT257_FN2),
-        PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
-        PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
-        PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
-        PINMUX_DATA(TCK3_MARK, PORT259_FN4),
-        PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
-        PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
-        PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
-        PINMUX_DATA(TMS3_MARK, PORT260_FN4),
-        PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
-        PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
-        PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
-        PINMUX_DATA(TDO3_MARK, PORT261_FN4),
-        PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
-        PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
-        PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
-        PINMUX_DATA(TDI3_MARK, PORT262_FN4),
-        PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
-        PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
-        PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
-        PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
-        PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
-        PINMUX_DATA(TRST3_MARK, PORT264_FN4),
-        PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
-        PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
-        PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
-        PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
-        PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
-        PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
-        PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
-        PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
-        PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
-        PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
-        PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
-        PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
-        PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* 49-1 -> 49-6 (GPIO) */
-        GPIO_PORT_ALL(),
-
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
-        GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
-        GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
-        GPIO_FN(PORT58_KEYIN6_PU),
-
-        /* 49-1 (FN) */
-        GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
-        GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
-        GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
-        GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
-        GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
-        GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
-        GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
-        GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
-        GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
-        GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
-        GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
-        GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
-        GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
-        GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
-        GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
-
-        /* 49-2 (FN) */
-        GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
-        GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
-        GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
-        GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
-        GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
-        GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
-        GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
-        GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
-        GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
-        GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
-        GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
-        GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
-        GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
-        GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
-        GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
-        GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
-        GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
-        GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
-        GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
-        GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
-        GPIO_FN(XTALB1L),
-        GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
-        GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
-        GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
-        GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
-        GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
-        GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
-        GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
-        GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
-        GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
-        GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
-        GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
-        GPIO_FN(NMI), GPIO_FN(TPU4TO0),
-        GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
-        GPIO_FN(IRQ_TMPB),
-        GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
-        GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
-        GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
-
-        /* 49-3 (FN) */
-        GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
-        GPIO_FN(PORT93_VIO_CKO2),
-        GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
-        GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
-        GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
-        GPIO_FN(SCIFA5_RXD),
-        GPIO_FN(SCIFA5_TXD),
-        GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
-        GPIO_FN(A0_EA0), GPIO_FN(BS),
-        GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
-        GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
-        GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
-        GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
-        GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
-        GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
-        GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
-        GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
-        GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
-        GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
-        GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
-        GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
-        GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
-        GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
-        GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
-        GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
-        GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
-        GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
-        GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
-        GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
-        GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
-        GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
-        GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
-        GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
-
-        /* 49-4 (FN) */
-        GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
-        GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
-        GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
-        GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
-        GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
-        GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
-        GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
-        GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
-        GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
-        GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
-        GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
-        GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
-        GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
-        GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
-        GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
-        GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
-        GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
-        GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
-        GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
-        GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
-        GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
-        GPIO_FN(LCDD6), GPIO_FN(DV_D6),
-        GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
-        GPIO_FN(LCDD7), GPIO_FN(DV_D7),
-        GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
-        GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
-        GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
-        GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
-        GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
-        GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
-        GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
-        GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
-        GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
-        GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
-        GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
-        GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
-        GPIO_FN(D26), GPIO_FN(ED26),
-        GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
-        GPIO_FN(D27), GPIO_FN(ED27),
-        GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
-        GPIO_FN(D28), GPIO_FN(ED28),
-        GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
-        GPIO_FN(D29), GPIO_FN(ED29),
-        GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
-        GPIO_FN(D30), GPIO_FN(ED30),
-        GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
-        GPIO_FN(D31), GPIO_FN(ED31),
-        GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
-        GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
-
-        /* 49-5 (FN) */
-        GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
-        GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
-        GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
-        GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
-        GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
-        GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
-        GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
-        GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
-        GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
-        GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
-        GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
-        GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
-        GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
-        GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
-        GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
-        GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
-        GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
-        GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
-        GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
-        GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
-        GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
-        GPIO_FN(MSIOF1_SS2),
-        GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
-        GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
-        GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
-        GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
-        GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
-        GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
-        GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
-        GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
-        GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
-        GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
-        GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
-        GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
-        GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
-        GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
-        GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
-        GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
-
-        /* 49-6 (FN) */
-        GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
-        GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
-        GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
-        GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
-        GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
-        GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
-        GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
-        GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
-        GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
-        GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
-        GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
-        GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
-        GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
-        GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
-        GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
-        GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(RESETOUTS),
-        GPIO_FN(DIVLOCK),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0, 0xe6050000), /* PORT0CR */
-        PORTCR(1, 0xe6050001), /* PORT1CR */
-        PORTCR(2, 0xe6050002), /* PORT2CR */
-        PORTCR(3, 0xe6050003), /* PORT3CR */
-        PORTCR(4, 0xe6050004), /* PORT4CR */
-        PORTCR(5, 0xe6050005), /* PORT5CR */
-        PORTCR(6, 0xe6050006), /* PORT6CR */
-        PORTCR(7, 0xe6050007), /* PORT7CR */
-        PORTCR(8, 0xe6050008), /* PORT8CR */
-        PORTCR(9, 0xe6050009), /* PORT9CR */
-
-        PORTCR(10, 0xe605000a), /* PORT10CR */
-        PORTCR(11, 0xe605000b), /* PORT11CR */
-        PORTCR(12, 0xe605000c), /* PORT12CR */
-        PORTCR(13, 0xe605000d), /* PORT13CR */
-        PORTCR(14, 0xe605000e), /* PORT14CR */
-        PORTCR(15, 0xe605000f), /* PORT15CR */
-        PORTCR(16, 0xe6050010), /* PORT16CR */
-        PORTCR(17, 0xe6050011), /* PORT17CR */
-        PORTCR(18, 0xe6050012), /* PORT18CR */
-        PORTCR(19, 0xe6050013), /* PORT19CR */
-
-        PORTCR(20, 0xe6050014), /* PORT20CR */
-        PORTCR(21, 0xe6050015), /* PORT21CR */
-        PORTCR(22, 0xe6050016), /* PORT22CR */
-        PORTCR(23, 0xe6050017), /* PORT23CR */
-        PORTCR(24, 0xe6050018), /* PORT24CR */
-        PORTCR(25, 0xe6050019), /* PORT25CR */
-        PORTCR(26, 0xe605001a), /* PORT26CR */
-        PORTCR(27, 0xe605001b), /* PORT27CR */
-        PORTCR(28, 0xe605001c), /* PORT28CR */
-        PORTCR(29, 0xe605001d), /* PORT29CR */
-
-        PORTCR(30, 0xe605001e), /* PORT30CR */
-        PORTCR(31, 0xe605001f), /* PORT31CR */
-        PORTCR(32, 0xe6050020), /* PORT32CR */
-        PORTCR(33, 0xe6050021), /* PORT33CR */
-        PORTCR(34, 0xe6050022), /* PORT34CR */
-        PORTCR(35, 0xe6050023), /* PORT35CR */
-        PORTCR(36, 0xe6050024), /* PORT36CR */
-        PORTCR(37, 0xe6050025), /* PORT37CR */
-        PORTCR(38, 0xe6050026), /* PORT38CR */
-        PORTCR(39, 0xe6050027), /* PORT39CR */
-
-        PORTCR(40, 0xe6050028), /* PORT40CR */
-        PORTCR(41, 0xe6050029), /* PORT41CR */
-        PORTCR(42, 0xe605002a), /* PORT42CR */
-        PORTCR(43, 0xe605002b), /* PORT43CR */
-        PORTCR(44, 0xe605002c), /* PORT44CR */
-        PORTCR(45, 0xe605002d), /* PORT45CR */
-        PORTCR(46, 0xe605002e), /* PORT46CR */
-        PORTCR(47, 0xe605002f), /* PORT47CR */
-        PORTCR(48, 0xe6050030), /* PORT48CR */
-        PORTCR(49, 0xe6050031), /* PORT49CR */
-
-        PORTCR(50, 0xe6050032), /* PORT50CR */
-        PORTCR(51, 0xe6050033), /* PORT51CR */
-        PORTCR(52, 0xe6050034), /* PORT52CR */
-        PORTCR(53, 0xe6050035), /* PORT53CR */
-        PORTCR(54, 0xe6050036), /* PORT54CR */
-        PORTCR(55, 0xe6050037), /* PORT55CR */
-        PORTCR(56, 0xe6050038), /* PORT56CR */
-        PORTCR(57, 0xe6050039), /* PORT57CR */
-        PORTCR(58, 0xe605003a), /* PORT58CR */
-        PORTCR(59, 0xe605003b), /* PORT59CR */
-
-        PORTCR(60, 0xe605003c), /* PORT60CR */
-        PORTCR(61, 0xe605003d), /* PORT61CR */
-        PORTCR(62, 0xe605003e), /* PORT62CR */
-        PORTCR(63, 0xe605003f), /* PORT63CR */
-        PORTCR(64, 0xe6050040), /* PORT64CR */
-        PORTCR(65, 0xe6050041), /* PORT65CR */
-        PORTCR(66, 0xe6050042), /* PORT66CR */
-        PORTCR(67, 0xe6050043), /* PORT67CR */
-        PORTCR(68, 0xe6050044), /* PORT68CR */
-        PORTCR(69, 0xe6050045), /* PORT69CR */
-
-        PORTCR(70, 0xe6050046), /* PORT70CR */
-        PORTCR(71, 0xe6050047), /* PORT71CR */
-        PORTCR(72, 0xe6050048), /* PORT72CR */
-        PORTCR(73, 0xe6050049), /* PORT73CR */
-        PORTCR(74, 0xe605004a), /* PORT74CR */
-        PORTCR(75, 0xe605004b), /* PORT75CR */
-        PORTCR(76, 0xe605004c), /* PORT76CR */
-        PORTCR(77, 0xe605004d), /* PORT77CR */
-        PORTCR(78, 0xe605004e), /* PORT78CR */
-        PORTCR(79, 0xe605004f), /* PORT79CR */
-
-        PORTCR(80, 0xe6050050), /* PORT80CR */
-        PORTCR(81, 0xe6050051), /* PORT81CR */
-        PORTCR(82, 0xe6050052), /* PORT82CR */
-        PORTCR(83, 0xe6050053), /* PORT83CR */
-        PORTCR(84, 0xe6050054), /* PORT84CR */
-        PORTCR(85, 0xe6050055), /* PORT85CR */
-        PORTCR(86, 0xe6050056), /* PORT86CR */
-        PORTCR(87, 0xe6050057), /* PORT87CR */
-        PORTCR(88, 0xe6051058), /* PORT88CR */
-        PORTCR(89, 0xe6051059), /* PORT89CR */
-
-        PORTCR(90, 0xe605105a), /* PORT90CR */
-        PORTCR(91, 0xe605105b), /* PORT91CR */
-        PORTCR(92, 0xe605105c), /* PORT92CR */
-        PORTCR(93, 0xe605105d), /* PORT93CR */
-        PORTCR(94, 0xe605105e), /* PORT94CR */
-        PORTCR(95, 0xe605105f), /* PORT95CR */
-        PORTCR(96, 0xe6051060), /* PORT96CR */
-        PORTCR(97, 0xe6051061), /* PORT97CR */
-        PORTCR(98, 0xe6051062), /* PORT98CR */
-        PORTCR(99, 0xe6051063), /* PORT99CR */
-
-        PORTCR(100, 0xe6051064), /* PORT100CR */
-        PORTCR(101, 0xe6051065), /* PORT101CR */
-        PORTCR(102, 0xe6051066), /* PORT102CR */
-        PORTCR(103, 0xe6051067), /* PORT103CR */
-        PORTCR(104, 0xe6051068), /* PORT104CR */
-        PORTCR(105, 0xe6051069), /* PORT105CR */
-        PORTCR(106, 0xe605106a), /* PORT106CR */
-        PORTCR(107, 0xe605106b), /* PORT107CR */
-        PORTCR(108, 0xe605106c), /* PORT108CR */
-        PORTCR(109, 0xe605106d), /* PORT109CR */
-
-        PORTCR(110, 0xe605106e), /* PORT110CR */
-        PORTCR(111, 0xe605106f), /* PORT111CR */
-        PORTCR(112, 0xe6051070), /* PORT112CR */
-        PORTCR(113, 0xe6051071), /* PORT113CR */
-        PORTCR(114, 0xe6051072), /* PORT114CR */
-        PORTCR(115, 0xe6051073), /* PORT115CR */
-        PORTCR(116, 0xe6051074), /* PORT116CR */
-        PORTCR(117, 0xe6051075), /* PORT117CR */
-        PORTCR(118, 0xe6051076), /* PORT118CR */
-        PORTCR(119, 0xe6051077), /* PORT119CR */
-
-        PORTCR(120, 0xe6051078), /* PORT120CR */
-        PORTCR(121, 0xe6051079), /* PORT121CR */
-        PORTCR(122, 0xe605107a), /* PORT122CR */
-        PORTCR(123, 0xe605107b), /* PORT123CR */
-        PORTCR(124, 0xe605107c), /* PORT124CR */
-        PORTCR(125, 0xe605107d), /* PORT125CR */
-        PORTCR(126, 0xe605107e), /* PORT126CR */
-        PORTCR(127, 0xe605107f), /* PORT127CR */
-        PORTCR(128, 0xe6051080), /* PORT128CR */
-        PORTCR(129, 0xe6051081), /* PORT129CR */
-
-        PORTCR(130, 0xe6051082), /* PORT130CR */
-        PORTCR(131, 0xe6051083), /* PORT131CR */
-        PORTCR(132, 0xe6051084), /* PORT132CR */
-        PORTCR(133, 0xe6051085), /* PORT133CR */
-        PORTCR(134, 0xe6051086), /* PORT134CR */
-        PORTCR(135, 0xe6051087), /* PORT135CR */
-        PORTCR(136, 0xe6051088), /* PORT136CR */
-        PORTCR(137, 0xe6051089), /* PORT137CR */
-        PORTCR(138, 0xe605108a), /* PORT138CR */
-        PORTCR(139, 0xe605108b), /* PORT139CR */
-
-        PORTCR(140, 0xe605108c), /* PORT140CR */
-        PORTCR(141, 0xe605108d), /* PORT141CR */
-        PORTCR(142, 0xe605108e), /* PORT142CR */
-        PORTCR(143, 0xe605108f), /* PORT143CR */
-        PORTCR(144, 0xe6051090), /* PORT144CR */
-        PORTCR(145, 0xe6051091), /* PORT145CR */
-        PORTCR(146, 0xe6051092), /* PORT146CR */
-        PORTCR(147, 0xe6051093), /* PORT147CR */
-        PORTCR(148, 0xe6051094), /* PORT148CR */
-        PORTCR(149, 0xe6051095), /* PORT149CR */
-
-        PORTCR(150, 0xe6051096), /* PORT150CR */
-        PORTCR(151, 0xe6051097), /* PORT151CR */
-        PORTCR(152, 0xe6051098), /* PORT152CR */
-        PORTCR(153, 0xe6051099), /* PORT153CR */
-        PORTCR(154, 0xe605109a), /* PORT154CR */
-        PORTCR(155, 0xe605109b), /* PORT155CR */
-        PORTCR(156, 0xe605109c), /* PORT156CR */
-        PORTCR(157, 0xe605109d), /* PORT157CR */
-        PORTCR(158, 0xe605109e), /* PORT158CR */
-        PORTCR(159, 0xe605109f), /* PORT159CR */
-
-        PORTCR(160, 0xe60510a0), /* PORT160CR */
-        PORTCR(161, 0xe60510a1), /* PORT161CR */
-        PORTCR(162, 0xe60510a2), /* PORT162CR */
-        PORTCR(163, 0xe60510a3), /* PORT163CR */
-        PORTCR(164, 0xe60510a4), /* PORT164CR */
-        PORTCR(165, 0xe60510a5), /* PORT165CR */
-        PORTCR(166, 0xe60510a6), /* PORT166CR */
-        PORTCR(167, 0xe60510a7), /* PORT167CR */
-        PORTCR(168, 0xe60510a8), /* PORT168CR */
-        PORTCR(169, 0xe60510a9), /* PORT169CR */
-
-        PORTCR(170, 0xe60510aa), /* PORT170CR */
-        PORTCR(171, 0xe60510ab), /* PORT171CR */
-        PORTCR(172, 0xe60510ac), /* PORT172CR */
-        PORTCR(173, 0xe60510ad), /* PORT173CR */
-        PORTCR(174, 0xe60510ae), /* PORT174CR */
-        PORTCR(175, 0xe60520af), /* PORT175CR */
-        PORTCR(176, 0xe60520b0), /* PORT176CR */
-        PORTCR(177, 0xe60520b1), /* PORT177CR */
-        PORTCR(178, 0xe60520b2), /* PORT178CR */
-        PORTCR(179, 0xe60520b3), /* PORT179CR */
-
-        PORTCR(180, 0xe60520b4), /* PORT180CR */
-        PORTCR(181, 0xe60520b5), /* PORT181CR */
-        PORTCR(182, 0xe60520b6), /* PORT182CR */
-        PORTCR(183, 0xe60520b7), /* PORT183CR */
-        PORTCR(184, 0xe60520b8), /* PORT184CR */
-        PORTCR(185, 0xe60520b9), /* PORT185CR */
-        PORTCR(186, 0xe60520ba), /* PORT186CR */
-        PORTCR(187, 0xe60520bb), /* PORT187CR */
-        PORTCR(188, 0xe60520bc), /* PORT188CR */
-        PORTCR(189, 0xe60520bd), /* PORT189CR */
-
-        PORTCR(190, 0xe60520be), /* PORT190CR */
-        PORTCR(191, 0xe60520bf), /* PORT191CR */
-        PORTCR(192, 0xe60520c0), /* PORT192CR */
-        PORTCR(193, 0xe60520c1), /* PORT193CR */
-        PORTCR(194, 0xe60520c2), /* PORT194CR */
-        PORTCR(195, 0xe60520c3), /* PORT195CR */
-        PORTCR(196, 0xe60520c4), /* PORT196CR */
-        PORTCR(197, 0xe60520c5), /* PORT197CR */
-        PORTCR(198, 0xe60520c6), /* PORT198CR */
-        PORTCR(199, 0xe60520c7), /* PORT199CR */
-
-        PORTCR(200, 0xe60520c8), /* PORT200CR */
-        PORTCR(201, 0xe60520c9), /* PORT201CR */
-        PORTCR(202, 0xe60520ca), /* PORT202CR */
-        PORTCR(203, 0xe60520cb), /* PORT203CR */
-        PORTCR(204, 0xe60520cc), /* PORT204CR */
-        PORTCR(205, 0xe60520cd), /* PORT205CR */
-        PORTCR(206, 0xe60520ce), /* PORT206CR */
-        PORTCR(207, 0xe60520cf), /* PORT207CR */
-        PORTCR(208, 0xe60520d0), /* PORT208CR */
-        PORTCR(209, 0xe60520d1), /* PORT209CR */
-
-        PORTCR(210, 0xe60520d2), /* PORT210CR */
-        PORTCR(211, 0xe60520d3), /* PORT211CR */
-        PORTCR(212, 0xe60520d4), /* PORT212CR */
-        PORTCR(213, 0xe60520d5), /* PORT213CR */
-        PORTCR(214, 0xe60520d6), /* PORT214CR */
-        PORTCR(215, 0xe60520d7), /* PORT215CR */
-        PORTCR(216, 0xe60520d8), /* PORT216CR */
-        PORTCR(217, 0xe60520d9), /* PORT217CR */
-        PORTCR(218, 0xe60520da), /* PORT218CR */
-        PORTCR(219, 0xe60520db), /* PORT219CR */
-
-        PORTCR(220, 0xe60520dc), /* PORT220CR */
-        PORTCR(221, 0xe60520dd), /* PORT221CR */
-        PORTCR(222, 0xe60520de), /* PORT222CR */
-        PORTCR(223, 0xe60520df), /* PORT223CR */
-        PORTCR(224, 0xe60520e0), /* PORT224CR */
-        PORTCR(225, 0xe60520e1), /* PORT225CR */
-        PORTCR(226, 0xe60520e2), /* PORT226CR */
-        PORTCR(227, 0xe60520e3), /* PORT227CR */
-        PORTCR(228, 0xe60520e4), /* PORT228CR */
-        PORTCR(229, 0xe60520e5), /* PORT229CR */
-
-        PORTCR(230, 0xe60520e6), /* PORT230CR */
-        PORTCR(231, 0xe60520e7), /* PORT231CR */
-        PORTCR(232, 0xe60520e8), /* PORT232CR */
-        PORTCR(233, 0xe60520e9), /* PORT233CR */
-        PORTCR(234, 0xe60520ea), /* PORT234CR */
-        PORTCR(235, 0xe60520eb), /* PORT235CR */
-        PORTCR(236, 0xe60530ec), /* PORT236CR */
-        PORTCR(237, 0xe60530ed), /* PORT237CR */
-        PORTCR(238, 0xe60530ee), /* PORT238CR */
-        PORTCR(239, 0xe60530ef), /* PORT239CR */
-
-        PORTCR(240, 0xe60530f0), /* PORT240CR */
-        PORTCR(241, 0xe60530f1), /* PORT241CR */
-        PORTCR(242, 0xe60530f2), /* PORT242CR */
-        PORTCR(243, 0xe60530f3), /* PORT243CR */
-        PORTCR(244, 0xe60530f4), /* PORT244CR */
-        PORTCR(245, 0xe60530f5), /* PORT245CR */
-        PORTCR(246, 0xe60530f6), /* PORT246CR */
-        PORTCR(247, 0xe60530f7), /* PORT247CR */
-        PORTCR(248, 0xe60530f8), /* PORT248CR */
-        PORTCR(249, 0xe60530f9), /* PORT249CR */
-
-        PORTCR(250, 0xe60530fa), /* PORT250CR */
-        PORTCR(251, 0xe60530fb), /* PORT251CR */
-        PORTCR(252, 0xe60530fc), /* PORT252CR */
-        PORTCR(253, 0xe60530fd), /* PORT253CR */
-        PORTCR(254, 0xe60530fe), /* PORT254CR */
-        PORTCR(255, 0xe60530ff), /* PORT255CR */
-        PORTCR(256, 0xe6053100), /* PORT256CR */
-        PORTCR(257, 0xe6053101), /* PORT257CR */
-        PORTCR(258, 0xe6053102), /* PORT258CR */
-        PORTCR(259, 0xe6053103), /* PORT259CR */
-
-        PORTCR(260, 0xe6053104), /* PORT260CR */
-        PORTCR(261, 0xe6053105), /* PORT261CR */
-        PORTCR(262, 0xe6053106), /* PORT262CR */
-        PORTCR(263, 0xe6053107), /* PORT263CR */
-        PORTCR(264, 0xe6053108), /* PORT264CR */
-        PORTCR(265, 0xe6053109), /* PORT265CR */
-        PORTCR(266, 0xe605310a), /* PORT266CR */
-        PORTCR(267, 0xe605310b), /* PORT267CR */
-        PORTCR(268, 0xe605310c), /* PORT268CR */
-        PORTCR(269, 0xe605310d), /* PORT269CR */
-
-        PORTCR(270, 0xe605310e), /* PORT270CR */
-        PORTCR(271, 0xe605310f), /* PORT271CR */
-        PORTCR(272, 0xe6053110), /* PORT272CR */
-
-        { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
-                0, 0,
-                0, 0 }
-        },
-        { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
-                PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-                PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-                PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
-                PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-                PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
-                PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
-                PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
-                PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
-                PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
-                PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
-                PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
-                PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
-                PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
-                PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
-                PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
-                PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
-                PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
-                PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
-                PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-                PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-                PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-                PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-                PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-                PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-                PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-                PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
-                PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-                PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-                PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-                PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-                PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-                PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-                PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-                PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, PORT272_DATA,
-                PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
-                PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
-                PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-                PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
-        },
-        { },
-};
-
-static struct pinmux_info sh7367_pinmux_info = {
-        .name = "sh7367_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_DIVLOCK,
-
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void sh7367_pinmux_init(void)
-{
-        register_pinmux(&sh7367_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
deleted file mode 100644
index f3117f67fa25..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ /dev/null
@@ -1,1688 +0,0 @@
-/*
- * sh7377 processor support - PFC hardware block
- *
- * Copyright (C) 2010  NISHIMOTO Hiroki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/sh7377.h>
-
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx),           \
-        PORT_10(fn, pfx##10, sfx),                              \
-        PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),   \
-        PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),   \
-        PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx),   \
-        PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx),   \
-        PORT_1(fn, pfx##118, sfx),                              \
-        PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx),   \
-        PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx),   \
-        PORT_10(fn, pfx##15, sfx),                              \
-        PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx),   \
-        PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx),   \
-        PORT_1(fn, pfx##164, sfx),                              \
-        PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx),   \
-        PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx),   \
-        PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx),   \
-        PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx),   \
-        PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),   \
-        PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),   \
-        PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),   \
-        PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx),   \
-        PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx),   \
-        PORT_1(fn, pfx##264, sfx)
-
-enum {
-        PINMUX_RESERVED = 0,
-
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
-        PINMUX_DATA_END,
-
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
-        PINMUX_INPUT_END,
-
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
-        PINMUX_OUTPUT_END,
-
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
-        PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
-        PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
-        PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
-        PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
-        PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
-        PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
-        PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
-        PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
-        PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
-
-        MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
-        MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
-        PINMUX_FUNCTION_END,
-
-        PINMUX_MARK_BEGIN,
-        /* Special Pull-up / Pull-down Functions */
-        PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK,
-        PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK,
-        PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK,
-        PORT72_KEYIN6_PU_MARK,
-
-        /* 55-1 */
-        VBUS_0_MARK,
-        CPORT0_MARK,
-        CPORT1_MARK,
-        CPORT2_MARK,
-        CPORT3_MARK,
-        CPORT4_MARK,
-        CPORT5_MARK,
-        CPORT6_MARK,
-        CPORT7_MARK,
-        CPORT8_MARK,
-        CPORT9_MARK,
-        CPORT10_MARK,
-        CPORT11_MARK, SIN2_MARK,
-        CPORT12_MARK, XCTS2_MARK,
-        CPORT13_MARK, RFSPO4_MARK,
-        CPORT14_MARK, RFSPO5_MARK,
-        CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK,
-        CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK,
-        CPORT17_IC_OE_MARK, SOUT2_MARK,
-        CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK,
-        CPORT19_MPORT1_MARK,
-        CPORT20_MARK, RFSPO6_MARK,
-        CPORT21_MARK, STATUS0_MARK,
-        CPORT22_MARK, STATUS1_MARK,
-        CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
-        B_SYNLD1_MARK,
-        B_SYNLD2_MARK, SYSENMSK_MARK,
-        XMAINPS_MARK,
-        XDIVPS_MARK,
-        XIDRST_MARK,
-        IDCLK_MARK, IC_DP_MARK,
-        IDIO_MARK, IC_DM_MARK,
-        SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK,
-        SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
-        XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
-        XCTS1_MARK, SCIFA4_CTS_MARK,
-        PCMCLKO_MARK,
-        SYNC8KO_MARK,
-
-        /* 55-2 */
-        DNPCM_A_MARK,
-        UPPCM_A_MARK,
-        VACK_MARK,
-        XTALB1L_MARK,
-        GPS_AGC1_MARK, SCIFA0_RTS_MARK,
-        GPS_AGC4_MARK, SCIFA0_RXD_MARK,
-        GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK,
-        GPS_IM_MARK,
-        GPS_IS_MARK,
-        GPS_QM_MARK,
-        GPS_QS_MARK,
-        FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK,
-        FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK,
-        FMSIOLR_MARK,
-        FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK,
-        FMSIOBT_MARK,
-        FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK,
-        FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK,
-        FMSIILR_MARK,
-        FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK,
-        FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK,
-        A0_EA0_MARK, BS_MARK,
-        A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK,
-        A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK,
-        A14_EA14_MARK, PORT60_KEYOUT5_MARK,
-        A15_EA15_MARK, PORT61_KEYOUT4_MARK,
-        A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK,
-        A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
-        A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK,
-        A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK,
-        A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK,
-        A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK,
-        A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK,
-        A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK,
-        A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK,
-        A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK,
-        A26_MARK, PORT72_KEYIN6_MARK,
-        D0_ED0_NAF0_MARK,
-        D1_ED1_NAF1_MARK,
-        D2_ED2_NAF2_MARK,
-        D3_ED3_NAF3_MARK,
-        D4_ED4_NAF4_MARK,
-        D5_ED5_NAF5_MARK,
-        D6_ED6_NAF6_MARK,
-        D7_ED7_NAF7_MARK,
-        D8_ED8_NAF8_MARK,
-        D9_ED9_NAF9_MARK,
-        D10_ED10_NAF10_MARK,
-        D11_ED11_NAF11_MARK,
-        D12_ED12_NAF12_MARK,
-        D13_ED13_NAF13_MARK,
-        D14_ED14_NAF14_MARK,
-        D15_ED15_NAF15_MARK,
-        CS4_MARK,
-        CS5A_MARK, FMSICK_MARK,
-        CS5B_MARK, FCE1_MARK,
-
-        /* 55-3 */
-        CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK,
-        FCE0_MARK,
-        WAIT_MARK, DREQ0_MARK,
-        RD_XRD_MARK,
-        WE0_XWR0_FWE_MARK,
-        WE1_XWR1_MARK,
-        FRB_MARK,
-        CKO_MARK,
-        NBRSTOUT_MARK,
-        NBRST_MARK,
-        GPS_EPPSIN_MARK,
-        LATCHPULSE_MARK,
-        LTESIGNAL_MARK,
-        LEGACYSTATE_MARK,
-        TCKON_MARK,
-        VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK,
-        VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK,
-        VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK,
-        VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK,
-        VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK,
-        VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK,
-        VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK,
-        VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK,
-        VIO_D6_MARK, PORT136_KEYIN2_MARK,
-        VIO_D7_MARK, PORT137_KEYIN3_MARK,
-        VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK,
-        VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK,
-        VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK,
-        VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK,
-        VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK,
-        VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK,
-        VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK,
-        VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK,
-        VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK,
-        VIO_FIELD_MARK, PORT147_KEYIN5_MARK,
-        VIO_CKO_MARK, PORT148_KEYIN6_MARK,
-        A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK,
-        MFG0_IN2_MARK,
-        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
-        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
-        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
-        SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
-        SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
-        XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK,
-        XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK,
-
-        /* 55-4 */
-        DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
-        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK,
-        PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK,
-        MFG3_IN2_MARK,
-        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK,
-        MFG3_IN1_MARK,
-        PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK,
-        MFG3_OUT1_MARK, TPU3TO0_MARK,
-        LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK,
-        LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK,
-        BBIF2_TSYNC1_MARK,
-        LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK,
-        BBIF2_TSCK1_MARK,
-        LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK,
-        BBIF2_TXD1_MARK,
-        LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK,
-        LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK,
-        MFG2_OUT2_MARK,
-        TPU2TO1_MARK,
-        LCDD6_MARK, XWR2_MARK,
-        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK,
-        LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK,
-        LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK,
-        LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK,
-        LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK,
-        LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK,
-        LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK,
-        LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK,
-        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK,
-        VIO_DR7_MARK, D23_MARK, ED23_MARK,
-        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK,
-        VIO_VDR_MARK, D24_MARK, ED24_MARK,
-        LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK,
-        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK,
-        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK,
-        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK,
-        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK,
-        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK,
-        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK,
-        LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK,
-        LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK,
-        LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
-        PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK,
-        LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK,
-        LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK,
-        LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK,
-        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK,
-        SCIFA1_TXD_MARK, OVCN2_MARK,
-        EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK,
-        SCIFA1_RTS_MARK, IDIN_MARK,
-        SCIFA1_RXD_MARK,
-        SCIFA1_CTS_MARK, MFG1_IN1_MARK,
-        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK,
-        MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK,
-        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK,
-        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK,
-        PORT233_FSIACK_MARK,
-        MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK,
-        MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK,
-        MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK,
-        MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK,
-        MSIOF1_SS1_MARK, EDBGREQ3_MARK,
-
-        /* 55-5 */
-        MSIOF1_SS2_MARK,
-        SCIFA6_TXD_MARK,
-        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK,
-        TPU4TO0_MARK,
-        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
-        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
-        PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK,
-        PORT244_MSIOF2_RXD_MARK,
-        PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK,
-        PORT245_MSIOF2_TXD_MARK,
-        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK,
-        TPU1TO0_MARK,
-        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK,
-        TPU3TO1_MARK,
-        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK,
-        TPU2TO0_MARK,
-        PORT248_MSIOF2_TSCK_MARK,
-        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK,
-        SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK,
-        SDHICD0_MARK,
-        SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK,
-        SDHID0_1_MARK, TDO2_SWO0_MC0_MARK,
-        SDHID0_2_MARK, TDI2_MARK,
-        SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK,
-        SDHICMD0_MARK, TRST2_MARK,
-        SDHIWP0_MARK, EDBGREQ2_MARK,
-        SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK,
-        SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK,
-        TMS3_SWDIO_MC1_MARK,
-        SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK,
-        SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK,
-        SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK,
-        SDHICMD1_MARK, TRST3_MARK,
-        RESETOUTS_MARK,
-        PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* 55-1 (GPIO) */
-        PORT_DATA_I_PD(0), PORT_DATA_I_PU(1),
-        PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4), PORT_DATA_I_PU(5),
-        PORT_DATA_I_PU(6), PORT_DATA_I_PU(7),
-        PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
-        PORT_DATA_I_PU(10), PORT_DATA_I_PU(11),
-        PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13),
-        PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_O(16), PORT_DATA_IO(17),
-        PORT_DATA_O(18), PORT_DATA_O(19),
-        PORT_DATA_O(20), PORT_DATA_O(21),
-        PORT_DATA_O(22), PORT_DATA_O(23),
-        PORT_DATA_O(24), PORT_DATA_I_PD(25),
-        PORT_DATA_I_PD(26), PORT_DATA_O(27),
-        PORT_DATA_O(28), PORT_DATA_O(29),
-        PORT_DATA_IO(30), PORT_DATA_IO_PU(31),
-        PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33),
-        PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35),
-        PORT_DATA_O(36), PORT_DATA_IO(37),
-
-        /* 55-2 (GPIO) */
-        PORT_DATA_O(38), PORT_DATA_I_PU(39),
-        PORT_DATA_I_PU_PD(40), PORT_DATA_O(41),
-        PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43),
-        PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45),
-        PORT_DATA_I_PD(46), PORT_DATA_I_PD(47),
-        PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51),
-        PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53),
-        PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55),
-        PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57),
-        PORT_DATA_IO(58), PORT_DATA_IO(59),
-        PORT_DATA_IO(60), PORT_DATA_IO(61),
-        PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73),
-        PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75),
-        PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77),
-        PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79),
-        PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81),
-        PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83),
-        PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85),
-        PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87),
-        PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89),
-        PORT_DATA_O(90), PORT_DATA_IO_PU(91),
-        PORT_DATA_O(92),
-
-        /* 55-3 (GPIO) */
-        PORT_DATA_IO_PU(93),
-        PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO(96), PORT_DATA_IO(97),
-        PORT_DATA_IO(98), PORT_DATA_I_PU(99),
-        PORT_DATA_O(100), PORT_DATA_O(101),
-        PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103),
-        PORT_DATA_I_PD(104), PORT_DATA_I_PD(105),
-        PORT_DATA_I_PD(106), PORT_DATA_I_PD(107),
-        PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109),
-        PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111),
-        PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115),
-        PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117),
-        PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128),
-        PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130),
-        PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132),
-        PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134),
-        PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136),
-        PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138),
-        PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140),
-        PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142),
-        PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144),
-        PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146),
-        PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148),
-        PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150),
-        PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152),
-        PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154),
-        PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156),
-        PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158),
-
-        /* 55-4 (GPIO) */
-        PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160),
-        PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162),
-        PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164),
-        PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193),
-        PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199),
-        PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
-        PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
-        PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207),
-        PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213),
-        PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215),
-        PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217),
-        PORT_DATA_O(218), PORT_DATA_IO_PD(219),
-        PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221),
-        PORT_DATA_IO_PU_PD(222),
-        PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224),
-        PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226),
-        PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228),
-        PORT_DATA_I_PD(229), PORT_DATA_IO(230),
-        PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232),
-        PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236),
-        PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238),
-
-        /* 55-5 (GPIO) */
-        PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240),
-        PORT_DATA_O(241), PORT_DATA_I_PD(242),
-        PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244),
-        PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246),
-        PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250),
-        PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252),
-        PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254),
-        PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256),
-        PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258),
-        PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260),
-        PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262),
-        PORT_DATA_IO_PU_PD(263),
-
-        /* Special Pull-up / Pull-down Functions */
-        PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT66_FN2, PORT66_IN_PU),
-        PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT67_FN2, PORT67_IN_PU),
-        PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT68_FN2, PORT68_IN_PU),
-        PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT69_FN2, PORT69_IN_PU),
-        PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT70_FN2, PORT70_IN_PU),
-        PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT71_FN2, PORT71_IN_PU),
-        PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT72_FN2, PORT72_IN_PU),
-
-
-        /* 55-1 (FN) */
-        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
-        PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
-        PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
-        PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
-        PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
-        PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
-        PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
-        PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
-        PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
-        PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
-        PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
-        PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
-        PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
-        PINMUX_DATA(SIN2_MARK, PORT12_FN2),
-        PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
-        PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
-        PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
-        PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
-        PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
-        PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
-        PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
-        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2),
-        PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3),
-        PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
-        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
-        PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3),
-        PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1),
-        PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
-        PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
-        PINMUX_DATA(XRTS2_MARK, PORT19_FN2),
-        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
-        PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1),
-        PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
-        PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
-        PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
-        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-        PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
-        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-        PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
-        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-        PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
-        PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1),
-        PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1),
-        PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2),
-        PINMUX_DATA(XMAINPS_MARK, PORT27_FN1),
-        PINMUX_DATA(XDIVPS_MARK, PORT28_FN1),
-        PINMUX_DATA(XIDRST_MARK, PORT29_FN1),
-        PINMUX_DATA(IDCLK_MARK, PORT30_FN1),
-        PINMUX_DATA(IC_DP_MARK, PORT30_FN2),
-        PINMUX_DATA(IDIO_MARK, PORT31_FN1),
-        PINMUX_DATA(IC_DM_MARK, PORT31_FN2),
-        PINMUX_DATA(SOUT1_MARK, PORT32_FN1),
-        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
-        PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3),
-        PINMUX_DATA(SIN1_MARK, PORT33_FN1),
-        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2),
-        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
-        PINMUX_DATA(XRTS1_MARK, PORT34_FN1),
-        PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2),
-        PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3),
-        PINMUX_DATA(XCTS1_MARK, PORT35_FN1),
-        PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2),
-        PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1),
-        PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1),
-
-        /* 55-2 (FN) */
-        PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1),
-        PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1),
-        PINMUX_DATA(VACK_MARK, PORT40_FN1),
-        PINMUX_DATA(XTALB1L_MARK, PORT41_FN1),
-        PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1),
-        PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2),
-        PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1),
-        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
-        PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1),
-        PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2),
-        PINMUX_DATA(GPS_IM_MARK, PORT45_FN1),
-        PINMUX_DATA(GPS_IS_MARK, PORT46_FN1),
-        PINMUX_DATA(GPS_QM_MARK, PORT47_FN1),
-        PINMUX_DATA(GPS_QS_MARK, PORT48_FN1),
-        PINMUX_DATA(FMSOCK_MARK, PORT49_FN1),
-        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2),
-        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3),
-        PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1),
-        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2),
-        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3),
-        PINMUX_DATA(IPORT3_MARK, PORT50_FN4),
-        PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5),
-        PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1),
-        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2),
-        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3),
-        PINMUX_DATA(OPORT1_MARK, PORT51_FN4),
-        PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5),
-        PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1),
-        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
-        PINMUX_DATA(OPORT2_MARK, PORT52_FN3),
-        PINMUX_DATA(FMSOILR_MARK, PORT53_FN1),
-        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2),
-        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3),
-        PINMUX_DATA(OPORT3_MARK, PORT53_FN4),
-        PINMUX_DATA(FMSIILR_MARK, PORT53_FN5),
-        PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1),
-        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2),
-        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3),
-        PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4),
-        PINMUX_DATA(FMSISLD_MARK, PORT55_FN1),
-        PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2),
-        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
-        PINMUX_DATA(A0_EA0_MARK, PORT57_FN1),
-        PINMUX_DATA(BS_MARK, PORT57_FN2),
-        PINMUX_DATA(A12_EA12_MARK, PORT58_FN1),
-        PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2),
-        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3),
-        PINMUX_DATA(A13_EA13_MARK, PORT59_FN1),
-        PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2),
-        PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3),
-        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
-        PINMUX_DATA(A14_EA14_MARK, PORT60_FN1),
-        PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2),
-        PINMUX_DATA(A15_EA15_MARK, PORT61_FN1),
-        PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2),
-        PINMUX_DATA(A16_EA16_MARK, PORT62_FN1),
-        PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2),
-        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3),
-        PINMUX_DATA(A17_EA17_MARK, PORT63_FN1),
-        PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3),
-        PINMUX_DATA(A18_EA18_MARK, PORT64_FN1),
-        PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2),
-        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3),
-        PINMUX_DATA(A19_EA19_MARK, PORT65_FN1),
-        PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2),
-        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3),
-        PINMUX_DATA(A20_EA20_MARK, PORT66_FN1),
-        PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2),
-        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3),
-        PINMUX_DATA(A21_EA21_MARK, PORT67_FN1),
-        PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3),
-        PINMUX_DATA(A22_EA22_MARK, PORT68_FN1),
-        PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2),
-        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3),
-        PINMUX_DATA(A23_EA23_MARK, PORT69_FN1),
-        PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2),
-        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3),
-        PINMUX_DATA(A24_EA24_MARK, PORT70_FN1),
-        PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2),
-        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3),
-        PINMUX_DATA(A25_EA25_MARK, PORT71_FN1),
-        PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2),
-        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3),
-        PINMUX_DATA(A26_MARK, PORT72_FN1),
-        PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2),
-        PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1),
-        PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1),
-        PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1),
-        PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1),
-        PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1),
-        PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1),
-        PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1),
-        PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1),
-        PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1),
-        PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1),
-        PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1),
-        PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1),
-        PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1),
-        PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1),
-        PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1),
-        PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1),
-        PINMUX_DATA(CS4_MARK, PORT90_FN1),
-        PINMUX_DATA(CS5A_MARK, PORT91_FN1),
-        PINMUX_DATA(FMSICK_MARK, PORT91_FN2),
-        PINMUX_DATA(CS5B_MARK, PORT92_FN1),
-        PINMUX_DATA(FCE1_MARK, PORT92_FN2),
-
-        /* 55-3 (FN) */
-        PINMUX_DATA(CS6B_MARK, PORT93_FN1),
-        PINMUX_DATA(XCS2_MARK, PORT93_FN2),
-        PINMUX_DATA(CS6A_MARK, PORT93_FN3),
-        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
-        PINMUX_DATA(FCE0_MARK, PORT94_FN1),
-        PINMUX_DATA(WAIT_MARK, PORT95_FN1),
-        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
-        PINMUX_DATA(RD_XRD_MARK, PORT96_FN1),
-        PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1),
-        PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1),
-        PINMUX_DATA(FRB_MARK, PORT99_FN1),
-        PINMUX_DATA(CKO_MARK, PORT100_FN1),
-        PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1),
-        PINMUX_DATA(NBRST_MARK, PORT102_FN1),
-        PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1),
-        PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1),
-        PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1),
-        PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1),
-        PINMUX_DATA(TCKON_MARK, PORT118_FN1),
-        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1),
-        PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2),
-        PINMUX_DATA(IPORT0_MARK, PORT128_FN3),
-        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1),
-        PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2),
-        PINMUX_DATA(IPORT1_MARK, PORT129_FN3),
-        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1),
-        PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2),
-        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3),
-        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1),
-        PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2),
-        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3),
-        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1),
-        PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2),
-        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3),
-        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1),
-        PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2),
-        PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3),
-        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1),
-        PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2),
-        PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3),
-        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1),
-        PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2),
-        PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3),
-        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1),
-        PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2),
-        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1),
-        PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2),
-        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1),
-        PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2),
-        PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3),
-        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1),
-        PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2),
-        PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3),
-        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1),
-        PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2),
-        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3),
-        PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4),
-        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1),
-        PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2),
-        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3),
-        PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4),
-        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1),
-        PINMUX_DATA(M13_BSW_MARK, PORT142_FN2),
-        PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3),
-        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1),
-        PINMUX_DATA(M14_GSW_MARK, PORT143_FN2),
-        PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3),
-        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1),
-        PINMUX_DATA(M15_RSW_MARK, PORT144_FN2),
-        PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3),
-        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1),
-        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2),
-        PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3),
-        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1),
-        PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2),
-        PINMUX_DATA(IPORT2_MARK, PORT146_FN3),
-        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1),
-        PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2),
-        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
-        PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2),
-        PINMUX_DATA(A27_MARK, PORT149_FN1),
-        PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2),
-        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3),
-        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1),
-        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1),
-        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2),
-        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2),
-        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1),
-        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2),
-        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3),
-        PINMUX_DATA(SOUT3_MARK, PORT154_FN1),
-        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2),
-        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3),
-        PINMUX_DATA(SIN3_MARK, PORT155_FN1),
-        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2),
-        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3),
-        PINMUX_DATA(XRTS3_MARK, PORT156_FN1),
-        PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2),
-        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3),
-        PINMUX_DATA(XCTS3_MARK, PORT157_FN1),
-        PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2),
-        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3),
-
-        /* 55-4 (FN) */
-        PINMUX_DATA(DINT_MARK, PORT158_FN1),
-        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2),
-        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3),
-        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1),
-        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2),
-        PINMUX_DATA(NMI_MARK, PORT159_FN3),
-        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1),
-        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2),
-        PINMUX_DATA(SOUT0_MARK, PORT160_FN3),
-        PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1),
-        PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2),
-        PINMUX_DATA(XCTS0_MARK, PORT161_FN3),
-        PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4),
-        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1),
-        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2),
-        PINMUX_DATA(SIN0_MARK, PORT162_FN3),
-        PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4),
-        PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1),
-        PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2),
-        PINMUX_DATA(XRTS0_MARK, PORT163_FN3),
-        PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4),
-        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
-        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
-        PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2),
-        PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3),
-        PINMUX_DATA(LCDD1_MARK, PORT193_FN1),
-        PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2),
-        PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3),
-        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4),
-        PINMUX_DATA(LCDD2_MARK, PORT194_FN1),
-        PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2),
-        PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3),
-        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4),
-        PINMUX_DATA(LCDD3_MARK, PORT195_FN1),
-        PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2),
-        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3),
-        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4),
-        PINMUX_DATA(LCDD4_MARK, PORT196_FN1),
-        PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2),
-        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3),
-        PINMUX_DATA(LCDD5_MARK, PORT197_FN1),
-        PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2),
-        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3),
-        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4),
-        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
-        PINMUX_DATA(LCDD7_MARK, PORT199_FN1),
-        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2),
-        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3),
-        PINMUX_DATA(LCDD8_MARK, PORT200_FN1),
-        PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2),
-        PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3),
-        PINMUX_DATA(D16_MARK, PORT200_FN4),
-        PINMUX_DATA(LCDD9_MARK, PORT201_FN1),
-        PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2),
-        PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3),
-        PINMUX_DATA(D17_MARK, PORT201_FN4),
-        PINMUX_DATA(LCDD10_MARK, PORT202_FN1),
-        PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2),
-        PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3),
-        PINMUX_DATA(D18_MARK, PORT202_FN4),
-        PINMUX_DATA(LCDD11_MARK, PORT203_FN1),
-        PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2),
-        PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3),
-        PINMUX_DATA(D19_MARK, PORT203_FN4),
-        PINMUX_DATA(LCDD12_MARK, PORT204_FN1),
-        PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2),
-        PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3),
-        PINMUX_DATA(D20_MARK, PORT204_FN4),
-        PINMUX_DATA(LCDD13_MARK, PORT205_FN1),
-        PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2),
-        PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3),
-        PINMUX_DATA(D21_MARK, PORT205_FN4),
-        PINMUX_DATA(LCDD14_MARK, PORT206_FN1),
-        PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2),
-        PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3),
-        PINMUX_DATA(D22_MARK, PORT206_FN4),
-        PINMUX_DATA(LCDD15_MARK, PORT207_FN1),
-        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2),
-        PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3),
-        PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4),
-        PINMUX_DATA(D23_MARK, PORT207_FN5),
-        PINMUX_DATA(LCDD16_MARK, PORT208_FN1),
-        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2),
-        PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3),
-        PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4),
-        PINMUX_DATA(D24_MARK, PORT208_FN5),
-        PINMUX_DATA(LCDD17_MARK, PORT209_FN1),
-        PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2),
-        PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3),
-        PINMUX_DATA(D25_MARK, PORT209_FN4),
-        PINMUX_DATA(LCDD18_MARK, PORT210_FN1),
-        PINMUX_DATA(DREQ2_MARK, PORT210_FN2),
-        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3),
-        PINMUX_DATA(D26_MARK, PORT210_FN4),
-        PINMUX_DATA(LCDD19_MARK, PORT211_FN1),
-        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2),
-        PINMUX_DATA(D27_MARK, PORT211_FN3),
-        PINMUX_DATA(LCDD20_MARK, PORT212_FN1),
-        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2),
-        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3),
-        PINMUX_DATA(D28_MARK, PORT212_FN4),
-        PINMUX_DATA(LCDD21_MARK, PORT213_FN1),
-        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2),
-        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3),
-        PINMUX_DATA(D29_MARK, PORT213_FN4),
-        PINMUX_DATA(LCDD22_MARK, PORT214_FN1),
-        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2),
-        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3),
-        PINMUX_DATA(D30_MARK, PORT214_FN4),
-        PINMUX_DATA(LCDD23_MARK, PORT215_FN1),
-        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2),
-        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3),
-        PINMUX_DATA(D31_MARK, PORT215_FN4),
-        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1),
-        PINMUX_DATA(LCDWR_MARK, PORT216_FN2),
-        PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3),
-        PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4),
-        PINMUX_DATA(LCDRD_MARK, PORT217_FN1),
-        PINMUX_DATA(DACK2_MARK, PORT217_FN2),
-        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3),
-        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1),
-        PINMUX_DATA(LCDCS_MARK, PORT218_FN2),
-        PINMUX_DATA(LCDCS2_MARK, PORT218_FN3),
-        PINMUX_DATA(DACK3_MARK, PORT218_FN4),
-        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
-        PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6),
-        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1),
-        PINMUX_DATA(LCDRS_MARK, PORT219_FN2),
-        PINMUX_DATA(DREQ3_MARK, PORT219_FN3),
-        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4),
-        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1),
-        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
-        PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3),
-        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1),
-        PINMUX_DATA(DREQ1_MARK, PORT221_FN2),
-        PINMUX_DATA(PWEN_MARK, PORT221_FN3),
-        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4),
-        PINMUX_DATA(LCDDON_MARK, PORT222_FN1),
-        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2),
-        PINMUX_DATA(DACK1_MARK, PORT222_FN3),
-        PINMUX_DATA(OVCN_MARK, PORT222_FN4),
-        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5),
-        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1),
-        PINMUX_DATA(OVCN2_MARK, PORT225_FN2),
-        PINMUX_DATA(EXTLP_MARK, PORT226_FN1),
-        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2),
-        PINMUX_DATA(USBTERM_MARK, PORT226_FN3),
-        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4),
-        PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1),
-        PINMUX_DATA(IDIN_MARK, PORT227_FN2),
-        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1),
-        PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1),
-        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2),
-        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1),
-        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2),
-        PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3),
-        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1),
-        PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2),
-        PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3),
-        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1),
-        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2),
-        PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3),
-        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1),
-        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2),
-        PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3),
-        PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4),
-        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1),
-        PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2),
-        PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1),
-        PINMUX_DATA(OPORT0_MARK, PORT235_FN2),
-        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3),
-        PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4),
-        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1),
-        PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2),
-        PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3),
-        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1),
-        PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2),
-        PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3),
-        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1),
-        PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2),
-
-        /* 55-5 (FN) */
-        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1),
-        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
-        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1),
-        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2),
-        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3),
-        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
-        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1),
-        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2),
-        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1),
-        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
-        PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1),
-        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2),
-        PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3),
-        PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1),
-        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2),
-        PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3),
-        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1),
-        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2),
-        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3),
-        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
-        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1),
-        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2),
-        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3),
-        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
-        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1),
-        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2),
-        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3),
-        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4),
-        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1),
-        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2),
-        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
-        PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2),
-        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
-        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
-        PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2),
-        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
-        PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2),
-        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
-        PINMUX_DATA(TDI2_MARK, PORT254_FN2),
-        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
-        PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2),
-        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
-        PINMUX_DATA(TRST2_MARK, PORT256_FN2),
-        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
-        PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2),
-        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
-        PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2),
-        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1),
-        PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2),
-        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
-        PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4),
-        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1),
-        PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2),
-        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
-        PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4),
-        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1),
-        PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2),
-        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
-        PINMUX_DATA(TDI3_MARK, PORT261_FN4),
-        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1),
-        PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2),
-        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
-        PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4),
-        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
-        PINMUX_DATA(TRST3_MARK, PORT263_FN2),
-        PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* 55-1 -> 55-5 (GPIO) */
-        GPIO_PORT_ALL(),
-
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
-        GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU),
-        GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU),
-        GPIO_FN(PORT72_KEYIN6_PU),
-
-        /* 55-1 (FN) */
-        GPIO_FN(VBUS_0),
-        GPIO_FN(CPORT0),
-        GPIO_FN(CPORT1),
-        GPIO_FN(CPORT2),
-        GPIO_FN(CPORT3),
-        GPIO_FN(CPORT4),
-        GPIO_FN(CPORT5),
-        GPIO_FN(CPORT6),
-        GPIO_FN(CPORT7),
-        GPIO_FN(CPORT8),
-        GPIO_FN(CPORT9),
-        GPIO_FN(CPORT10),
-        GPIO_FN(CPORT11), GPIO_FN(SIN2),
-        GPIO_FN(CPORT12), GPIO_FN(XCTS2),
-        GPIO_FN(CPORT13), GPIO_FN(RFSPO4),
-        GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
-        GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2),
-        GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3),
-        GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2),
-        GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(CPORT19_MPORT1),
-        GPIO_FN(CPORT20), GPIO_FN(RFSPO6),
-        GPIO_FN(CPORT21), GPIO_FN(STATUS0),
-        GPIO_FN(CPORT22), GPIO_FN(STATUS1),
-        GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
-        GPIO_FN(B_SYNLD1),
-        GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK),
-        GPIO_FN(XMAINPS),
-        GPIO_FN(XDIVPS),
-        GPIO_FN(XIDRST),
-        GPIO_FN(IDCLK), GPIO_FN(IC_DP),
-        GPIO_FN(IDIO), GPIO_FN(IC_DM),
-        GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT),
-        GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
-        GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
-        GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
-        GPIO_FN(PCMCLKO),
-        GPIO_FN(SYNC8KO),
-
-        /* 55-2 (FN) */
-        GPIO_FN(DNPCM_A),
-        GPIO_FN(UPPCM_A),
-        GPIO_FN(VACK),
-        GPIO_FN(XTALB1L),
-        GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS),
-        GPIO_FN(GPS_IM),
-        GPIO_FN(GPS_IS),
-        GPIO_FN(GPS_QM),
-        GPIO_FN(GPS_QS),
-        GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT),
-        GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2),
-        GPIO_FN(IPORT3), GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3),
-        GPIO_FN(OPORT1), GPIO_FN(FMSIOBT),
-        GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2),
-        GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3),
-        GPIO_FN(OPORT3), GPIO_FN(FMSIILR),
-        GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2),
-        GPIO_FN(FMSIIBT),
-        GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0),
-        GPIO_FN(A0_EA0), GPIO_FN(BS),
-        GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2),
-        GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2),
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5),
-        GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4),
-        GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6),
-        GPIO_FN(D0_ED0_NAF0),
-        GPIO_FN(D1_ED1_NAF1),
-        GPIO_FN(D2_ED2_NAF2),
-        GPIO_FN(D3_ED3_NAF3),
-        GPIO_FN(D4_ED4_NAF4),
-        GPIO_FN(D5_ED5_NAF5),
-        GPIO_FN(D6_ED6_NAF6),
-        GPIO_FN(D7_ED7_NAF7),
-        GPIO_FN(D8_ED8_NAF8),
-        GPIO_FN(D9_ED9_NAF9),
-        GPIO_FN(D10_ED10_NAF10),
-        GPIO_FN(D11_ED11_NAF11),
-        GPIO_FN(D12_ED12_NAF12),
-        GPIO_FN(D13_ED13_NAF13),
-        GPIO_FN(D14_ED14_NAF14),
-        GPIO_FN(D15_ED15_NAF15),
-        GPIO_FN(CS4),
-        GPIO_FN(CS5A), GPIO_FN(FMSICK),
-
-        /* 55-3 (FN) */
-        GPIO_FN(CS5B), GPIO_FN(FCE1),
-        GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0),
-        GPIO_FN(FCE0),
-        GPIO_FN(WAIT), GPIO_FN(DREQ0),
-        GPIO_FN(RD_XRD),
-        GPIO_FN(WE0_XWR0_FWE),
-        GPIO_FN(WE1_XWR1),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT),
-        GPIO_FN(NBRST),
-        GPIO_FN(GPS_EPPSIN),
-        GPIO_FN(LATCHPULSE),
-        GPIO_FN(LTESIGNAL),
-        GPIO_FN(LEGACYSTATE),
-        GPIO_FN(TCKON),
-        GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0),
-        GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1),
-        GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD),
-        GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1),
-        GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2),
-        GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5),
-        GPIO_FN(PORT133_MSIOF2_TSYNC),
-        GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD),
-        GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK),
-        GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2),
-        GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3),
-        GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC),
-        GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR),
-        GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2),
-        GPIO_FN(PORT140_FSIAOBT),
-        GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3),
-        GPIO_FN(PORT141_FSIAOSLD),
-        GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK),
-        GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR),
-        GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT),
-        GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD),
-        GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2),
-        GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5),
-        GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6),
-        GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1),
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD),
-
-        /* 55-4 (FN) */
-        GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
-        GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI),
-        GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0),
-        GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0),
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0),
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0),
-        GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0),
-        GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI),
-        GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS),
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS),
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD),
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD),
-        GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK),
-        GPIO_FN(MFG2_OUT2),
-        GPIO_FN(LCDD6),
-        GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2),
-        GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0),
-        GPIO_FN(D16),
-        GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1),
-        GPIO_FN(D17),
-        GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2),
-        GPIO_FN(D18),
-        GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3),
-        GPIO_FN(D19),
-        GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4),
-        GPIO_FN(D20),
-        GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5),
-        GPIO_FN(D21),
-        GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6),
-        GPIO_FN(D22),
-        GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0),
-        GPIO_FN(VIO_DR7), GPIO_FN(D23),
-        GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1),
-        GPIO_FN(VIO_VDR), GPIO_FN(D24),
-        GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR),
-        GPIO_FN(D25),
-        GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1),
-        GPIO_FN(D26),
-        GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27),
-        GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
-        GPIO_FN(D28),
-        GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
-        GPIO_FN(D29),
-        GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK),
-        GPIO_FN(D30),
-        GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC),
-        GPIO_FN(D31),
-        GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3),
-        GPIO_FN(VIO_CLKR),
-        GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC),
-        GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
-        GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4),
-        GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK),
-        GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5),
-        GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD),
-        GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN),
-        GPIO_FN(MSIOF0L_TXD),
-        GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM),
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN),
-        GPIO_FN(SCIFA1_RXD),
-        GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC),
-        GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR),
-        GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT),
-        GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG),
-        GPIO_FN(PORT233_FSIACK),
-        GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD),
-        GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2),
-        GPIO_FN(PORT235_FSIAILR),
-        GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT),
-        GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD),
-        GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
-
-        /* 55-5 (FN) */
-        GPIO_FN(MSIOF1_SS2),
-        GPIO_FN(SCIFA6_TXD),
-        GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1),
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1),
-        GPIO_FN(PORT244_SCIFB_CTS),
-        GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2),
-        GPIO_FN(PORT245_SCIFB_RTS),
-        GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1),
-        GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0),
-        GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2),
-        GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1),
-        GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1),
-        GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0),
-        GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1),
-        GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0),
-        GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0),
-        GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
-        GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0),
-        GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
-        GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
-        GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1),
-        GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(TMS3_SWDIO_MC1),
-        GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2),
-        GPIO_FN(TDO3_SWO0_MC1),
-        GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2),
-        GPIO_FN(TDI3),
-        GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2),
-        GPIO_FN(RTCK3_SWO1_MC1),
-        GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
-        GPIO_FN(RESETOUTS),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0, 0xe6050000), /* PORT0CR */
-        PORTCR(1, 0xe6050001), /* PORT1CR */
-        PORTCR(2, 0xe6050002), /* PORT2CR */
-        PORTCR(3, 0xe6050003), /* PORT3CR */
-        PORTCR(4, 0xe6050004), /* PORT4CR */
-        PORTCR(5, 0xe6050005), /* PORT5CR */
-        PORTCR(6, 0xe6050006), /* PORT6CR */
-        PORTCR(7, 0xe6050007), /* PORT7CR */
-        PORTCR(8, 0xe6050008), /* PORT8CR */
-        PORTCR(9, 0xe6050009), /* PORT9CR */
-
-        PORTCR(10, 0xe605000a), /* PORT10CR */
-        PORTCR(11, 0xe605000b), /* PORT11CR */
-        PORTCR(12, 0xe605000c), /* PORT12CR */
-        PORTCR(13, 0xe605000d), /* PORT13CR */
-        PORTCR(14, 0xe605000e), /* PORT14CR */
-        PORTCR(15, 0xe605000f), /* PORT15CR */
-        PORTCR(16, 0xe6050010), /* PORT16CR */
-        PORTCR(17, 0xe6050011), /* PORT17CR */
-        PORTCR(18, 0xe6050012), /* PORT18CR */
-        PORTCR(19, 0xe6050013), /* PORT19CR */
-
-        PORTCR(20, 0xe6050014), /* PORT20CR */
-        PORTCR(21, 0xe6050015), /* PORT21CR */
-        PORTCR(22, 0xe6050016), /* PORT22CR */
-        PORTCR(23, 0xe6050017), /* PORT23CR */
-        PORTCR(24, 0xe6050018), /* PORT24CR */
-        PORTCR(25, 0xe6050019), /* PORT25CR */
-        PORTCR(26, 0xe605001a), /* PORT26CR */
-        PORTCR(27, 0xe605001b), /* PORT27CR */
-        PORTCR(28, 0xe605001c), /* PORT28CR */
-        PORTCR(29, 0xe605001d), /* PORT29CR */
-
-        PORTCR(30, 0xe605001e), /* PORT30CR */
-        PORTCR(31, 0xe605001f), /* PORT31CR */
-        PORTCR(32, 0xe6050020), /* PORT32CR */
-        PORTCR(33, 0xe6050021), /* PORT33CR */
-        PORTCR(34, 0xe6050022), /* PORT34CR */
-        PORTCR(35, 0xe6050023), /* PORT35CR */
-        PORTCR(36, 0xe6050024), /* PORT36CR */
-        PORTCR(37, 0xe6050025), /* PORT37CR */
-        PORTCR(38, 0xe6050026), /* PORT38CR */
-        PORTCR(39, 0xe6050027), /* PORT39CR */
-
-        PORTCR(40, 0xe6050028), /* PORT40CR */
-        PORTCR(41, 0xe6050029), /* PORT41CR */
-        PORTCR(42, 0xe605002a), /* PORT42CR */
-        PORTCR(43, 0xe605002b), /* PORT43CR */
-        PORTCR(44, 0xe605002c), /* PORT44CR */
-        PORTCR(45, 0xe605002d), /* PORT45CR */
-        PORTCR(46, 0xe605002e), /* PORT46CR */
-        PORTCR(47, 0xe605002f), /* PORT47CR */
-        PORTCR(48, 0xe6050030), /* PORT48CR */
-        PORTCR(49, 0xe6050031), /* PORT49CR */
-
-        PORTCR(50, 0xe6050032), /* PORT50CR */
-        PORTCR(51, 0xe6050033), /* PORT51CR */
-        PORTCR(52, 0xe6050034), /* PORT52CR */
-        PORTCR(53, 0xe6050035), /* PORT53CR */
-        PORTCR(54, 0xe6050036), /* PORT54CR */
-        PORTCR(55, 0xe6050037), /* PORT55CR */
-        PORTCR(56, 0xe6050038), /* PORT56CR */
-        PORTCR(57, 0xe6050039), /* PORT57CR */
-        PORTCR(58, 0xe605003a), /* PORT58CR */
-        PORTCR(59, 0xe605003b), /* PORT59CR */
-
-        PORTCR(60, 0xe605003c), /* PORT60CR */
-        PORTCR(61, 0xe605003d), /* PORT61CR */
-        PORTCR(62, 0xe605003e), /* PORT62CR */
-        PORTCR(63, 0xe605003f), /* PORT63CR */
-        PORTCR(64, 0xe6050040), /* PORT64CR */
-        PORTCR(65, 0xe6050041), /* PORT65CR */
-        PORTCR(66, 0xe6050042), /* PORT66CR */
-        PORTCR(67, 0xe6050043), /* PORT67CR */
-        PORTCR(68, 0xe6050044), /* PORT68CR */
-        PORTCR(69, 0xe6050045), /* PORT69CR */
-
-        PORTCR(70, 0xe6050046), /* PORT70CR */
-        PORTCR(71, 0xe6050047), /* PORT71CR */
-        PORTCR(72, 0xe6050048), /* PORT72CR */
-        PORTCR(73, 0xe6050049), /* PORT73CR */
-        PORTCR(74, 0xe605004a), /* PORT74CR */
-        PORTCR(75, 0xe605004b), /* PORT75CR */
-        PORTCR(76, 0xe605004c), /* PORT76CR */
-        PORTCR(77, 0xe605004d), /* PORT77CR */
-        PORTCR(78, 0xe605004e), /* PORT78CR */
-        PORTCR(79, 0xe605004f), /* PORT79CR */
-
-        PORTCR(80, 0xe6050050), /* PORT80CR */
-        PORTCR(81, 0xe6050051), /* PORT81CR */
-        PORTCR(82, 0xe6050052), /* PORT82CR */
-        PORTCR(83, 0xe6050053), /* PORT83CR */
-        PORTCR(84, 0xe6050054), /* PORT84CR */
-        PORTCR(85, 0xe6050055), /* PORT85CR */
-        PORTCR(86, 0xe6050056), /* PORT86CR */
-        PORTCR(87, 0xe6050057), /* PORT87CR */
-        PORTCR(88, 0xe6050058), /* PORT88CR */
-        PORTCR(89, 0xe6050059), /* PORT89CR */
-
-        PORTCR(90, 0xe605005a), /* PORT90CR */
-        PORTCR(91, 0xe605005b), /* PORT91CR */
-        PORTCR(92, 0xe605005c), /* PORT92CR */
-        PORTCR(93, 0xe605005d), /* PORT93CR */
-        PORTCR(94, 0xe605005e), /* PORT94CR */
-        PORTCR(95, 0xe605005f), /* PORT95CR */
-        PORTCR(96, 0xe6050060), /* PORT96CR */
-        PORTCR(97, 0xe6050061), /* PORT97CR */
-        PORTCR(98, 0xe6050062), /* PORT98CR */
-        PORTCR(99, 0xe6050063), /* PORT99CR */
-
-        PORTCR(100, 0xe6050064), /* PORT100CR */
-        PORTCR(101, 0xe6050065), /* PORT101CR */
-        PORTCR(102, 0xe6050066), /* PORT102CR */
-        PORTCR(103, 0xe6050067), /* PORT103CR */
-        PORTCR(104, 0xe6050068), /* PORT104CR */
-        PORTCR(105, 0xe6050069), /* PORT105CR */
-        PORTCR(106, 0xe605006a), /* PORT106CR */
-        PORTCR(107, 0xe605006b), /* PORT107CR */
-        PORTCR(108, 0xe605006c), /* PORT108CR */
-        PORTCR(109, 0xe605006d), /* PORT109CR */
-
-        PORTCR(110, 0xe605006e), /* PORT110CR */
-        PORTCR(111, 0xe605006f), /* PORT111CR */
-        PORTCR(112, 0xe6050070), /* PORT112CR */
-        PORTCR(113, 0xe6050071), /* PORT113CR */
-        PORTCR(114, 0xe6050072), /* PORT114CR */
-        PORTCR(115, 0xe6050073), /* PORT115CR */
-        PORTCR(116, 0xe6050074), /* PORT116CR */
-        PORTCR(117, 0xe6050075), /* PORT117CR */
-        PORTCR(118, 0xe6050076), /* PORT118CR */
-
-        PORTCR(128, 0xe6051080), /* PORT128CR */
-        PORTCR(129, 0xe6051081), /* PORT129CR */
-
-        PORTCR(130, 0xe6051082), /* PORT130CR */
-        PORTCR(131, 0xe6051083), /* PORT131CR */
-        PORTCR(132, 0xe6051084), /* PORT132CR */
-        PORTCR(133, 0xe6051085), /* PORT133CR */
-        PORTCR(134, 0xe6051086), /* PORT134CR */
-        PORTCR(135, 0xe6051087), /* PORT135CR */
-        PORTCR(136, 0xe6051088), /* PORT136CR */
-        PORTCR(137, 0xe6051089), /* PORT137CR */
-        PORTCR(138, 0xe605108a), /* PORT138CR */
-        PORTCR(139, 0xe605108b), /* PORT139CR */
-
-        PORTCR(140, 0xe605108c), /* PORT140CR */
-        PORTCR(141, 0xe605108d), /* PORT141CR */
-        PORTCR(142, 0xe605108e), /* PORT142CR */
-        PORTCR(143, 0xe605108f), /* PORT143CR */
-        PORTCR(144, 0xe6051090), /* PORT144CR */
-        PORTCR(145, 0xe6051091), /* PORT145CR */
-        PORTCR(146, 0xe6051092), /* PORT146CR */
-        PORTCR(147, 0xe6051093), /* PORT147CR */
-        PORTCR(148, 0xe6051094), /* PORT148CR */
-        PORTCR(149, 0xe6051095), /* PORT149CR */
-
-        PORTCR(150, 0xe6051096), /* PORT150CR */
-        PORTCR(151, 0xe6051097), /* PORT151CR */
-        PORTCR(152, 0xe6051098), /* PORT152CR */
-        PORTCR(153, 0xe6051099), /* PORT153CR */
-        PORTCR(154, 0xe605109a), /* PORT154CR */
-        PORTCR(155, 0xe605109b), /* PORT155CR */
-        PORTCR(156, 0xe605109c), /* PORT156CR */
-        PORTCR(157, 0xe605109d), /* PORT157CR */
-        PORTCR(158, 0xe605109e), /* PORT158CR */
-        PORTCR(159, 0xe605109f), /* PORT159CR */
-
-        PORTCR(160, 0xe60510a0), /* PORT160CR */
-        PORTCR(161, 0xe60510a1), /* PORT161CR */
-        PORTCR(162, 0xe60510a2), /* PORT162CR */
-        PORTCR(163, 0xe60510a3), /* PORT163CR */
-        PORTCR(164, 0xe60510a4), /* PORT164CR */
-
-        PORTCR(192, 0xe60520c0), /* PORT192CR */
-        PORTCR(193, 0xe60520c1), /* PORT193CR */
-        PORTCR(194, 0xe60520c2), /* PORT194CR */
-        PORTCR(195, 0xe60520c3), /* PORT195CR */
-        PORTCR(196, 0xe60520c4), /* PORT196CR */
-        PORTCR(197, 0xe60520c5), /* PORT197CR */
-        PORTCR(198, 0xe60520c6), /* PORT198CR */
-        PORTCR(199, 0xe60520c7), /* PORT199CR */
-
-        PORTCR(200, 0xe60520c8), /* PORT200CR */
-        PORTCR(201, 0xe60520c9), /* PORT201CR */
-        PORTCR(202, 0xe60520ca), /* PORT202CR */
-        PORTCR(203, 0xe60520cb), /* PORT203CR */
-        PORTCR(204, 0xe60520cc), /* PORT204CR */
-        PORTCR(205, 0xe60520cd), /* PORT205CR */
-        PORTCR(206, 0xe60520ce), /* PORT206CR */
-        PORTCR(207, 0xe60520cf), /* PORT207CR */
-        PORTCR(208, 0xe60520d0), /* PORT208CR */
-        PORTCR(209, 0xe60520d1), /* PORT209CR */
-
-        PORTCR(210, 0xe60520d2), /* PORT210CR */
-        PORTCR(211, 0xe60520d3), /* PORT211CR */
-        PORTCR(212, 0xe60520d4), /* PORT212CR */
-        PORTCR(213, 0xe60520d5), /* PORT213CR */
-        PORTCR(214, 0xe60520d6), /* PORT214CR */
-        PORTCR(215, 0xe60520d7), /* PORT215CR */
-        PORTCR(216, 0xe60520d8), /* PORT216CR */
-        PORTCR(217, 0xe60520d9), /* PORT217CR */
-        PORTCR(218, 0xe60520da), /* PORT218CR */
-        PORTCR(219, 0xe60520db), /* PORT219CR */
-
-        PORTCR(220, 0xe60520dc), /* PORT220CR */
-        PORTCR(221, 0xe60520dd), /* PORT221CR */
-        PORTCR(222, 0xe60520de), /* PORT222CR */
-        PORTCR(223, 0xe60520df), /* PORT223CR */
-        PORTCR(224, 0xe60520e0), /* PORT224CR */
-        PORTCR(225, 0xe60520e1), /* PORT225CR */
-        PORTCR(226, 0xe60520e2), /* PORT226CR */
-        PORTCR(227, 0xe60520e3), /* PORT227CR */
-        PORTCR(228, 0xe60520e4), /* PORT228CR */
-        PORTCR(229, 0xe60520e5), /* PORT229CR */
-
-        PORTCR(230, 0xe60520e6), /* PORT230CR */
-        PORTCR(231, 0xe60520e7), /* PORT231CR */
-        PORTCR(232, 0xe60520e8), /* PORT232CR */
-        PORTCR(233, 0xe60520e9), /* PORT233CR */
-        PORTCR(234, 0xe60520ea), /* PORT234CR */
-        PORTCR(235, 0xe60520eb), /* PORT235CR */
-        PORTCR(236, 0xe60520ec), /* PORT236CR */
-        PORTCR(237, 0xe60520ed), /* PORT237CR */
-        PORTCR(238, 0xe60520ee), /* PORT238CR */
-        PORTCR(239, 0xe60520ef), /* PORT239CR */
-
-        PORTCR(240, 0xe60520f0), /* PORT240CR */
-        PORTCR(241, 0xe60520f1), /* PORT241CR */
-        PORTCR(242, 0xe60520f2), /* PORT242CR */
-        PORTCR(243, 0xe60520f3), /* PORT243CR */
-        PORTCR(244, 0xe60520f4), /* PORT244CR */
-        PORTCR(245, 0xe60520f5), /* PORT245CR */
-        PORTCR(246, 0xe60520f6), /* PORT246CR */
-        PORTCR(247, 0xe60520f7), /* PORT247CR */
-        PORTCR(248, 0xe60520f8), /* PORT248CR */
-        PORTCR(249, 0xe60520f9), /* PORT249CR */
-
-        PORTCR(250, 0xe60520fa), /* PORT250CR */
-        PORTCR(251, 0xe60520fb), /* PORT251CR */
-        PORTCR(252, 0xe60520fc), /* PORT252CR */
-        PORTCR(253, 0xe60520fd), /* PORT253CR */
-        PORTCR(254, 0xe60520fe), /* PORT254CR */
-        PORTCR(255, 0xe60520ff), /* PORT255CR */
-        PORTCR(256, 0xe6052100), /* PORT256CR */
-        PORTCR(257, 0xe6052101), /* PORT257CR */
-        PORTCR(258, 0xe6052102), /* PORT258CR */
-        PORTCR(259, 0xe6052103), /* PORT259CR */
-
-        PORTCR(260, 0xe6052104), /* PORT260CR */
-        PORTCR(261, 0xe6052105), /* PORT261CR */
-        PORTCR(262, 0xe6052106), /* PORT262CR */
-        PORTCR(263, 0xe6052107), /* PORT263CR */
-        PORTCR(264, 0xe6052108), /* PORT264CR */
-
-        { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        MSELBCR_MSEL17_0, MSELBCR_MSEL17_1,
-                        MSELBCR_MSEL16_0, MSELBCR_MSEL16_1,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
-        },
-        { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
-                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
-                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
-                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) {
-                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT164_DATA,
-                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) {
-                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) {
-                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT264_DATA,
-                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
-        },
-        { },
-};
-
-static struct pinmux_info sh7377_pinmux_info = {
-        .name = "sh7377_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_RESETOUTS,
-
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void sh7377_pinmux_init(void)
-{
-        register_pinmux(&sh7377_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 96f11394c7c0..095222469d03 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -584,6 +584,21 @@ static struct platform_device i2c1_device = {
         .num_resources  = ARRAY_SIZE(i2c1_resources),
 };
 
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = evt2irq(0x19a0),
+                .end    = evt2irq(0x19a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pmu_device = {
+        .name   = "arm-pmu",
+        .id     = -1,
+        .num_resources = ARRAY_SIZE(pmu_resources),
+        .resource = pmu_resources,
+};
+
 static struct platform_device *r8a7740_late_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
@@ -591,6 +606,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
         &dma1_device,
         &dma2_device,
         &usb_dma_device,
+        &pmu_device,
 };
 
 /*
@@ -741,7 +757,7 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
         NULL,
 };
 
-DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
+DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
         .map_io         = r8a7740_map_io,
         .init_early     = r8a7740_add_early_devices_dt,
         .init_irq       = r8a7740_init_irq,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index ebbffc25f24f..7a1ad4f38539 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -229,6 +229,79 @@ static struct platform_device tmu01_device = {
         .num_resources  = ARRAY_SIZE(tmu01_resources),
 };
 
+/* I2C */
+static struct resource rcar_i2c0_res[] = {
+        {
+                .start  = 0xffc70000,
+                .end    = 0xffc70fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(79),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c0_device = {
+        .name           = "i2c-rcar",
+        .id             = 0,
+        .resource       = rcar_i2c0_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
+};
+
+static struct resource rcar_i2c1_res[] = {
+        {
+                .start  = 0xffc71000,
+                .end    = 0xffc71fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(82),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c1_device = {
+        .name           = "i2c-rcar",
+        .id             = 1,
+        .resource       = rcar_i2c1_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
+};
+
+static struct resource rcar_i2c2_res[] = {
+        {
+                .start  = 0xffc72000,
+                .end    = 0xffc72fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(80),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c2_device = {
+        .name           = "i2c-rcar",
+        .id             = 2,
+        .resource       = rcar_i2c2_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
+};
+
+static struct resource rcar_i2c3_res[] = {
+        {
+                .start  = 0xffc73000,
+                .end    = 0xffc73fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(81),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c3_device = {
+        .name           = "i2c-rcar",
+        .id             = 3,
+        .resource       = rcar_i2c3_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
+};
+
 static struct platform_device *r8a7779_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -238,6 +311,10 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
         &scif5_device,
         &tmu00_device,
         &tmu01_device,
+        &i2c0_device,
+        &i2c1_device,
+        &i2c2_device,
+        &i2c3_device,
 };
 
 static struct platform_device *r8a7779_late_devices[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
deleted file mode 100644
index e647f5410879..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- * sh7367 processor support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/uio_driver.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_timer.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-static struct map_desc sh7367_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-void __init sh7367_map_io(void)
-{
-        iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
-}
-
-/* SCIFA0 */
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
-                            evt2irq(0xc00), evt2irq(0xc00) },
-};
-
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-
-/* SCIFA1 */
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
-                            evt2irq(0xc20), evt2irq(0xc20) },
-};
-
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-
-/* SCIFA2 */
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
-                            evt2irq(0xc40), evt2irq(0xc40) },
-};
-
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-
-/* SCIFA3 */
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
-                            evt2irq(0xc60), evt2irq(0xc60) },
-};
-
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-
-/* SCIFA4 */
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
-                            evt2irq(0xd20), evt2irq(0xd20) },
-};
-
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-
-/* SCIFA5 */
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
-                            evt2irq(0xd40), evt2irq(0xd40) },
-};
-
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-
-/* SCIFB */
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
-                            evt2irq(0xd60), evt2irq(0xd60) },
-};
-
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
-
-static struct sh_timer_config cmt10_platform_data = {
-        .name = "CMT10",
-        .channel_offset = 0x10,
-        .timer_bit = 0,
-        .clockevent_rating = 125,
-        .clocksource_rating = 125,
-};
-
-static struct resource cmt10_resources[] = {
-        [0] = {
-                .name   = "CMT10",
-                .start  = 0xe6138010,
-                .end    = 0xe613801b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0xb00), /* CMT1_CMT10 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device cmt10_device = {
-        .name           = "sh_cmt",
-        .id             = 10,
-        .dev = {
-                .platform_data  = &cmt10_platform_data,
-        },
-        .resource       = cmt10_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
-};
-
-/* VPU */
-static struct uio_info vpu_platform_data = {
-        .name = "VPU5",
-        .version = "0",
-        .irq = intcs_evt2irq(0x980),
-};
-
-static struct resource vpu_resources[] = {
-        [0] = {
-                .name   = "VPU",
-                .start  = 0xfe900000,
-                .end    = 0xfe902807,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device vpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &vpu_platform_data,
-        },
-        .resource       = vpu_resources,
-        .num_resources  = ARRAY_SIZE(vpu_resources),
-};
-
-/* VEU0 */
-static struct uio_info veu0_platform_data = {
-        .name = "VEU0",
-        .version = "0",
-        .irq = intcs_evt2irq(0x700),
-};
-
-static struct resource veu0_resources[] = {
-        [0] = {
-                .name   = "VEU0",
-                .start  = 0xfe920000,
-                .end    = 0xfe9200b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &veu0_platform_data,
-        },
-        .resource       = veu0_resources,
-        .num_resources  = ARRAY_SIZE(veu0_resources),
-};
-
-/* VEU1 */
-static struct uio_info veu1_platform_data = {
-        .name = "VEU1",
-        .version = "0",
-        .irq = intcs_evt2irq(0x720),
-};
-
-static struct resource veu1_resources[] = {
-        [0] = {
-                .name   = "VEU1",
-                .start  = 0xfe924000,
-                .end    = 0xfe9240b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &veu1_platform_data,
-        },
-        .resource       = veu1_resources,
-        .num_resources  = ARRAY_SIZE(veu1_resources),
-};
-
-/* VEU2 */
-static struct uio_info veu2_platform_data = {
-        .name = "VEU2",
-        .version = "0",
-        .irq = intcs_evt2irq(0x740),
-};
-
-static struct resource veu2_resources[] = {
-        [0] = {
-                .name   = "VEU2",
-                .start  = 0xfe928000,
-                .end    = 0xfe9280b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu2_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 3,
-        .dev = {
-                .platform_data  = &veu2_platform_data,
-        },
-        .resource       = veu2_resources,
-        .num_resources  = ARRAY_SIZE(veu2_resources),
-};
-
-/* VEU3 */
-static struct uio_info veu3_platform_data = {
-        .name = "VEU3",
-        .version = "0",
-        .irq = intcs_evt2irq(0x760),
-};
-
-static struct resource veu3_resources[] = {
-        [0] = {
-                .name   = "VEU3",
-                .start  = 0xfe92c000,
-                .end    = 0xfe92c0b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu3_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 4,
-        .dev = {
-                .platform_data  = &veu3_platform_data,
-        },
-        .resource       = veu3_resources,
-        .num_resources  = ARRAY_SIZE(veu3_resources),
-};
-
-/* VEU2H */
-static struct uio_info veu2h_platform_data = {
-        .name = "VEU2H",
-        .version = "0",
-        .irq = intcs_evt2irq(0x520),
-};
-
-static struct resource veu2h_resources[] = {
-        [0] = {
-                .name   = "VEU2H",
-                .start  = 0xfe93c000,
-                .end    = 0xfe93c27b,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu2h_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 5,
-        .dev = {
-                .platform_data  = &veu2h_platform_data,
-        },
-        .resource       = veu2h_resources,
-        .num_resources  = ARRAY_SIZE(veu2h_resources),
-};
-
-/* JPU */
-static struct uio_info jpu_platform_data = {
-        .name = "JPU",
-        .version = "0",
-        .irq = intcs_evt2irq(0x560),
-};
-
-static struct resource jpu_resources[] = {
-        [0] = {
-                .name   = "JPU",
-                .start  = 0xfe980000,
-                .end    = 0xfe9902d3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device jpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 6,
-        .dev = {
-                .platform_data  = &jpu_platform_data,
-        },
-        .resource       = jpu_resources,
-        .num_resources  = ARRAY_SIZE(jpu_resources),
-};
-
-/* SPU1 */
-static struct uio_info spu1_platform_data = {
-        .name = "SPU1",
-        .version = "0",
-        .irq = evt2irq(0xfc0),
-};
-
-static struct resource spu1_resources[] = {
-        [0] = {
-                .name   = "SPU1",
-                .start  = 0xfe300000,
-                .end    = 0xfe3fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device spu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 7,
-        .dev = {
-                .platform_data  = &spu1_platform_data,
-        },
-        .resource       = spu1_resources,
-        .num_resources  = ARRAY_SIZE(spu1_resources),
-};
-
-static struct platform_device *sh7367_early_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
-        &scif2_device,
-        &scif3_device,
-        &scif4_device,
-        &scif5_device,
-        &scif6_device,
-        &cmt10_device,
-};
-
-static struct platform_device *sh7367_devices[] __initdata = {
-        &vpu_device,
-        &veu0_device,
-        &veu1_device,
-        &veu2_device,
-        &veu3_device,
-        &veu2h_device,
-        &jpu_device,
-        &spu1_device,
-};
-
-void __init sh7367_add_standard_devices(void)
-{
-        platform_add_devices(sh7367_early_devices,
-                             ARRAY_SIZE(sh7367_early_devices));
-
-        platform_add_devices(sh7367_devices,
-                            ARRAY_SIZE(sh7367_devices));
-}
-
-static void __init sh7367_earlytimer_init(void)
-{
-        sh7367_clock_init();
-        shmobile_earlytimer_init();
-}
-
-#define SYMSTPCR2 IOMEM(0xe6158048)
-#define SYMSTPCR2_CMT1 (1 << 29)
-
-void __init sh7367_add_early_devices(void)
-{
-        /* enable clock to CMT1 */
-        __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
-
-        early_platform_add_devices(sh7367_early_devices,
-                                   ARRAY_SIZE(sh7367_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = sh7367_earlytimer_init;
-}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index be6f746c97fa..c917882424a7 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -402,6 +402,26 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x3e,
         }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
+                .addr           = 0xe6a30050,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x83,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
+                .addr           = 0xe6a30050,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x83,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
+                .addr           = 0xe6a30060,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x87,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
+                .addr           = 0xe6a30060,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x87,
+        }, {
                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
                 .addr           = 0xe6850030,
                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
deleted file mode 100644
index edcf98bb7012..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/*
- * sh7377 processor support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/of_platform.h>
-#include <linux/uio_driver.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_intc.h>
-#include <linux/sh_timer.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/mach/map.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-static struct map_desc sh7377_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-void __init sh7377_map_io(void)
-{
-        iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
-}
-
-/* SCIFA0 */
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
-                            evt2irq(0xc00), evt2irq(0xc00) },
-};
-
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-
-/* SCIFA1 */
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
-                            evt2irq(0xc20), evt2irq(0xc20) },
-};
-
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-
-/* SCIFA2 */
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
-                            evt2irq(0xc40), evt2irq(0xc40) },
-};
-
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-
-/* SCIFA3 */
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
-                            evt2irq(0xc60), evt2irq(0xc60) },
-};
-
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-
-/* SCIFA4 */
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
-                            evt2irq(0xd20), evt2irq(0xd20) },
-};
-
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-
-/* SCIFA5 */
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
-                            evt2irq(0xd40), evt2irq(0xd40) },
-};
-
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-
-/* SCIFA6 */
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6cc0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
-                            intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
-};
-
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
-
-/* SCIFB */
-static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
-                            evt2irq(0xd60), evt2irq(0xd60) },
-};
-
-static struct platform_device scif7_device = {
-        .name           = "sh-sci",
-        .id             = 7,
-        .dev            = {
-                .platform_data  = &scif7_platform_data,
-        },
-};
-
-static struct sh_timer_config cmt10_platform_data = {
-        .name = "CMT10",
-        .channel_offset = 0x10,
-        .timer_bit = 0,
-        .clockevent_rating = 125,
-        .clocksource_rating = 125,
-};
-
-static struct resource cmt10_resources[] = {
-        [0] = {
-                .name   = "CMT10",
-                .start  = 0xe6138010,
-                .end    = 0xe613801b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0xb00), /* CMT1_CMT10 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device cmt10_device = {
-        .name           = "sh_cmt",
-        .id             = 10,
-        .dev = {
-                .platform_data  = &cmt10_platform_data,
-        },
-        .resource       = cmt10_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
-};
-
-/* VPU */
-static struct uio_info vpu_platform_data = {
-        .name = "VPU5HG",
-        .version = "0",
-        .irq = intcs_evt2irq(0x980),
-};
-
-static struct resource vpu_resources[] = {
-        [0] = {
-                .name   = "VPU",
-                .start  = 0xfe900000,
-                .end    = 0xfe900157,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device vpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &vpu_platform_data,
-        },
-        .resource       = vpu_resources,
-        .num_resources  = ARRAY_SIZE(vpu_resources),
-};
-
-/* VEU0 */
-static struct uio_info veu0_platform_data = {
-        .name = "VEU0",
-        .version = "0",
-        .irq = intcs_evt2irq(0x700),
-};
-
-static struct resource veu0_resources[] = {
-        [0] = {
-                .name   = "VEU0",
-                .start  = 0xfe920000,
-                .end    = 0xfe9200cb,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &veu0_platform_data,
-        },
-        .resource       = veu0_resources,
-        .num_resources  = ARRAY_SIZE(veu0_resources),
-};
-
-/* VEU1 */
-static struct uio_info veu1_platform_data = {
-        .name = "VEU1",
-        .version = "0",
-        .irq = intcs_evt2irq(0x720),
-};
-
-static struct resource veu1_resources[] = {
-        [0] = {
-                .name   = "VEU1",
-                .start  = 0xfe924000,
-                .end    = 0xfe9240cb,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &veu1_platform_data,
-        },
-        .resource       = veu1_resources,
-        .num_resources  = ARRAY_SIZE(veu1_resources),
-};
-
-/* VEU2 */
-static struct uio_info veu2_platform_data = {
-        .name = "VEU2",
-        .version = "0",
-        .irq = intcs_evt2irq(0x740),
-};
-
-static struct resource veu2_resources[] = {
-        [0] = {
-                .name   = "VEU2",
-                .start  = 0xfe928000,
-                .end    = 0xfe928307,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu2_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 3,
-        .dev = {
-                .platform_data  = &veu2_platform_data,
-        },
-        .resource       = veu2_resources,
-        .num_resources  = ARRAY_SIZE(veu2_resources),
-};
-
-/* VEU3 */
-static struct uio_info veu3_platform_data = {
-        .name = "VEU3",
-        .version = "0",
-        .irq = intcs_evt2irq(0x760),
-};
-
-static struct resource veu3_resources[] = {
-        [0] = {
-                .name   = "VEU3",
-                .start  = 0xfe92c000,
-                .end    = 0xfe92c307,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device veu3_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 4,
-        .dev = {
-                .platform_data  = &veu3_platform_data,
-        },
-        .resource       = veu3_resources,
-        .num_resources  = ARRAY_SIZE(veu3_resources),
-};
-
-/* JPU */
-static struct uio_info jpu_platform_data = {
-        .name = "JPU",
-        .version = "0",
-        .irq = intcs_evt2irq(0x560),
-};
-
-static struct resource jpu_resources[] = {
-        [0] = {
-                .name   = "JPU",
-                .start  = 0xfe980000,
-                .end    = 0xfe9902d3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device jpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 5,
-        .dev = {
-                .platform_data  = &jpu_platform_data,
-        },
-        .resource       = jpu_resources,
-        .num_resources  = ARRAY_SIZE(jpu_resources),
-};
-
-/* SPU2DSP0 */
-static struct uio_info spu0_platform_data = {
-        .name = "SPU2DSP0",
-        .version = "0",
-        .irq = evt2irq(0x1800),
-};
-
-static struct resource spu0_resources[] = {
-        [0] = {
-                .name   = "SPU2DSP0",
-                .start  = 0xfe200000,
-                .end    = 0xfe2fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device spu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 6,
-        .dev = {
-                .platform_data  = &spu0_platform_data,
-        },
-        .resource       = spu0_resources,
-        .num_resources  = ARRAY_SIZE(spu0_resources),
-};
-
-/* SPU2DSP1 */
-static struct uio_info spu1_platform_data = {
-        .name = "SPU2DSP1",
-        .version = "0",
-        .irq = evt2irq(0x1820),
-};
-
-static struct resource spu1_resources[] = {
-        [0] = {
-                .name   = "SPU2DSP1",
-                .start  = 0xfe300000,
-                .end    = 0xfe3fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device spu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 7,
-        .dev = {
-                .platform_data  = &spu1_platform_data,
-        },
-        .resource       = spu1_resources,
-        .num_resources  = ARRAY_SIZE(spu1_resources),
-};
-
-static struct platform_device *sh7377_early_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
-        &scif2_device,
-        &scif3_device,
-        &scif4_device,
-        &scif5_device,
-        &scif6_device,
-        &scif7_device,
-        &cmt10_device,
-};
-
-static struct platform_device *sh7377_devices[] __initdata = {
-        &vpu_device,
-        &veu0_device,
-        &veu1_device,
-        &veu2_device,
-        &veu3_device,
-        &jpu_device,
-        &spu0_device,
-        &spu1_device,
-};
-
-void __init sh7377_add_standard_devices(void)
-{
-        platform_add_devices(sh7377_early_devices,
-                            ARRAY_SIZE(sh7377_early_devices));
-
-        platform_add_devices(sh7377_devices,
-                            ARRAY_SIZE(sh7377_devices));
-}
-
-static void __init sh7377_earlytimer_init(void)
-{
-        sh7377_clock_init();
-        shmobile_earlytimer_init();
-}
-
-#define SMSTPCR3 IOMEM(0xe615013c)
-#define SMSTPCR3_CMT1 (1 << 29)
-
-void __init sh7377_add_early_devices(void)
-{
-        /* enable clock to CMT1 */
-        __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
-
-        early_platform_add_devices(sh7377_early_devices,
-                                   ARRAY_SIZE(sh7377_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = sh7377_earlytimer_init;
-}
-
-#ifdef CONFIG_USE_OF
-
-void __init sh7377_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
-
-        early_platform_add_devices(sh7377_early_devices,
-                                   ARRAY_SIZE(sh7377_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-
-static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
-        { }
-};
-
-void __init sh7377_add_standard_devices_dt(void)
-{
-        /* clocks are setup late during boot in the case of DT */
-        sh7377_clock_init();
-
-        platform_add_devices(sh7377_early_devices,
-                            ARRAY_SIZE(sh7377_early_devices));
-
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             sh7377_auxdata_lookup, NULL);
-}
-
-static const char *sh7377_boards_compat_dt[] __initdata = {
-        "renesas,sh7377",
-        NULL,
-};
-
-DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
-        .map_io         = sh7377_map_io,
-        .init_early     = sh7377_add_early_devices_dt,
-        .init_irq       = sh7377_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = sh7377_add_standard_devices_dt,
-        .timer          = &shmobile_timer,
-        .dt_compat      = sh7377_boards_compat_dt,
-MACHINE_END
-
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f67456286280..535426c306bd 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -32,24 +32,8 @@
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
 static void __iomem *scu_base;
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        unsigned long tmp;
-
-        /* we assume this code is running on a different cpu
-         * than the one that is changing coherency setting */
-        spin_lock(&scu_lock);
-        tmp = readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        writel(tmp, scu_base + 8);
-        spin_unlock(&scu_lock);
-
-}
-
 static unsigned int __init emev2_get_core_count(void)
 {
         if (!scu_base) {
@@ -95,7 +79,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
         cpu = cpu_logical_map(cpu);
 
         /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base, 0);
 
         /* Tell ROM loader about our vector (in headsmp.S) */
         emev2_set_boot_vector(__pa(shmobile_secondary_vector));
@@ -106,12 +90,10 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
-
         scu_enable(scu_base);
 
         /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base, 0);
 }
 
 static void __init emev2_smp_init_cpus(void)
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 2ce6af9a6a37..9def0f22bf22 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -61,9 +61,6 @@ static void __iomem *scu_base_addr(void)
         return (void __iomem *)0xf0000000;
 }
 
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
 
@@ -73,20 +70,6 @@ void __init r8a7779_register_twd(void)
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
-
 static unsigned int __init r8a7779_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
@@ -102,7 +85,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
         cpu = cpu_logical_map(cpu);
 
         /* disable cache coherency */
-        modify_scu_cpu_psr(3 << (cpu * 8), 0);
+        scu_power_mode(scu_base_addr(), 3);
 
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
@@ -145,7 +128,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
         cpu = cpu_logical_map(cpu);
 
         /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base_addr(), 0);
 
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
@@ -158,15 +141,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
-
         scu_enable(scu_base_addr());
 
         /* Map the reset vector (in headsmp.S) */
         __raw_writel(__pa(shmobile_secondary_vector), AVECR);
 
         /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base_addr(), 0);
 
         r8a7779_pm_init();
 
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 624f00f70abf..96ddb97babbe 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,9 +41,6 @@ static void __iomem *scu_base_addr(void)
         return (void __iomem *)0xf0000000;
 }
 
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
 void __init sh73a0_register_twd(void)
@@ -52,20 +49,6 @@ void __init sh73a0_register_twd(void)
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
-
 static unsigned int __init sh73a0_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
@@ -83,7 +66,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
         cpu = cpu_logical_map(cpu);
 
         /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base_addr(), 0);
 
         if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
                 __raw_writel(1 << cpu, WUPCR);  /* wake up */
@@ -95,8 +78,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
-
         scu_enable(scu_base_addr());
 
         /* Map the reset vector (in headsmp.S) */
@@ -104,7 +85,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
         __raw_writel(__pa(shmobile_secondary_vector), SBAR);
 
         /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base_addr(), 0);
 }
 
 static void __init sh73a0_smp_init_cpus(void)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
new file mode 100644
index 000000000000..3fdd0085e306
--- /dev/null
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -0,0 +1,9 @@
+config ARCH_SUNXI
+        bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select PINCTRL
+        select SPARSE_IRQ
+        select SUNXI_TIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
new file mode 100644
index 000000000000..93bebfc3ff9f
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot
new file mode 100644
index 000000000000..46d4cf0841c0
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-$(CONFIG_ARCH_SUNXI)   += 0x40008000
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
new file mode 100644
index 000000000000..9be910f7920b
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -0,0 +1,96 @@
+/*
+ * Device Tree support for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/sunxi_timer.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#include <asm/hardware/vic.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "sunxi.h"
+
+#define WATCHDOG_CTRL_REG       0x00
+#define WATCHDOG_MODE_REG       0x04
+
+static void __iomem *wdt_base;
+
+static void sunxi_setup_restart(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                                "allwinner,sunxi-wdt");
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+
+        wdt_base = of_iomap(np, 0);
+        WARN(!wdt_base, "failed to map watchdog base address");
+}
+
+static void sunxi_restart(char mode, const char *cmd)
+{
+        if (!wdt_base)
+                return;
+
+        /* Enable timer and set reset bit in the watchdog */
+        writel(3, wdt_base + WATCHDOG_MODE_REG);
+        writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);
+        while(1) {
+                mdelay(5);
+                writel(3, wdt_base + WATCHDOG_MODE_REG);
+        }
+}
+
+static struct map_desc sunxi_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
+                .length         = SUNXI_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init sunxi_map_io(void)
+{
+        iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
+}
+
+static void __init sunxi_dt_init(void)
+{
+        sunxi_setup_restart();
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const sunxi_board_dt_compat[] = {
+        "allwinner,sun4i",
+        "allwinner,sun5i",
+        NULL,
+};
+
+DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+        .init_machine   = sunxi_dt_init,
+        .map_io         = sunxi_map_io,
+        .init_irq       = sunxi_init_irq,
+        .handle_irq     = sunxi_handle_irq,
+        .restart        = sunxi_restart,
+        .timer          = &sunxi_timer,
+        .dt_compat      = sunxi_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
new file mode 100644
index 000000000000..33b58712adea
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.h
@@ -0,0 +1,20 @@
+/*
+ * Generic definitions for Allwinner SunXi SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SUNXI_H
+#define __MACH_SUNXI_H
+
+#define SUNXI_REGS_PHYS_BASE    0x01c00000
+#define SUNXI_REGS_VIRT_BASE    IOMEM(0xf1c00000)
+#define SUNXI_REGS_SIZE         (SZ_2M + SZ_1M)
+
+#endif /* __MACH_SUNXI_H */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 9aa653b3eb32..0979e8bba78a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,15 +8,24 @@ obj-y					+= pmc.o
 obj-y                                   += flowctrl.o
 obj-y                                   += powergate.o
 obj-y                                   += apbio.o
+obj-y                                   += pm.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-t20.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-tegra20.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += cpuidle-tegra20.o
+endif
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks_data.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-t30.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-tegra30.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += cpuidle-tegra30.o
+endif
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 71569c01afd2..734d9cc87f2e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -89,6 +89,17 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
                        &tegra_ehci3_pdata),
         OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
         {}
 };
 
@@ -102,8 +113,20 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         { "pll_a",      "pll_p_out1",   56448000,       true },
         { "pll_a_out0", "pll_a",        11289600,       true },
         { "cdev1",      NULL,           0,              true },
+        { "blink",      "clk_32k",      32768,          true },
         { "i2s1",       "pll_a_out0",   11289600,       false},
         { "i2s2",       "pll_a_out0",   11289600,       false},
+        { "sdmmc1",     "pll_p",        48000000,       false},
+        { "sdmmc3",     "pll_p",        48000000,       false},
+        { "sdmmc4",     "pll_p",        48000000,       false},
+        { "spi",        "pll_p",        20000000,       false },
+        { "sbc1",       "pll_p",        100000000,      false },
+        { "sbc2",       "pll_p",        100000000,      false },
+        { "sbc3",       "pll_p",        100000000,      false },
+        { "sbc4",       "pll_p",        100000000,      false },
+        { "host1x",     "pll_c",        150000000,      false },
+        { "disp1",      "pll_p",        600000000,      false },
+        { "disp2",      "pll_p",        600000000,      false },
         { NULL,         NULL,           0,              0},
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index e56170393a5b..6497d1236b08 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -51,6 +51,18 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
         OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
         OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
         {}
 };
 
@@ -61,11 +73,24 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         { "pll_a_out0", "pll_a",        11289600,       true },
         { "extern1",    "pll_a_out0",   0,              true },
         { "clk_out_1",  "extern1",      0,              true },
+        { "blink",      "clk_32k",      32768,          true },
         { "i2s0",       "pll_a_out0",   11289600,       false},
         { "i2s1",       "pll_a_out0",   11289600,       false},
         { "i2s2",       "pll_a_out0",   11289600,       false},
         { "i2s3",       "pll_a_out0",   11289600,       false},
         { "i2s4",       "pll_a_out0",   11289600,       false},
+        { "sdmmc1",     "pll_p",        48000000,       false},
+        { "sdmmc3",     "pll_p",        48000000,       false},
+        { "sdmmc4",     "pll_p",        48000000,       false},
+        { "sbc1",       "pll_p",        100000000,      false},
+        { "sbc2",       "pll_p",        100000000,      false},
+        { "sbc3",       "pll_p",        100000000,      false},
+        { "sbc4",       "pll_p",        100000000,      false},
+        { "sbc5",       "pll_p",        100000000,      false},
+        { "sbc6",       "pll_p",        100000000,      false},
+        { "host1x",     "pll_c",        150000000,      false},
+        { "disp1",      "pll_p",        600000000,      false},
+        { "disp2",      "pll_p",        600000000,      false},
         { NULL,         NULL,           0,              0},
 };
 
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f688daa74978..11a74db51e5d 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -36,6 +36,7 @@
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
+#include "pm.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -104,25 +105,30 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
         { "clk_m",      NULL,           0,              true },
         { "pll_p",      "clk_m",        408000000,      true },
         { "pll_p_out1", "pll_p",        9600000,        true },
+        { "pll_p_out4", "pll_p",        102000000,      true },
+        { "sclk",       "pll_p_out4",   102000000,      true },
+        { "hclk",       "sclk",         102000000,      true },
+        { "pclk",       "hclk",         51000000,       true },
+        { "csite",      NULL,           0,              true },
         { NULL,         NULL,           0,              0},
 };
 #endif
 
 
-static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
+static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
+        int ret;
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
         u32 aux_ctrl, cache_type;
 
-        writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
-        writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
-
         cache_type = readl(p + L2X0_CACHE_TYPE);
         aux_ctrl = (cache_type & 0x700) << (17-8);
-        aux_ctrl |= 0x6C000001;
+        aux_ctrl |= 0x7C400001;
 
-        l2x0_init(p, aux_ctrl, 0x8200c3fe);
+        ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
+        if (!ret)
+                l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
 #endif
 
 }
@@ -134,7 +140,7 @@ void __init tegra20_init_early(void)
         tegra_init_fuse();
         tegra2_init_clocks();
         tegra_clk_init_from_table(tegra20_clk_init_table);
-        tegra_init_cache(0x331, 0x441);
+        tegra_init_cache();
         tegra_pmc_init();
         tegra_powergate_init();
         tegra20_hotplug_init();
@@ -147,7 +153,7 @@ void __init tegra30_init_early(void)
         tegra_init_fuse();
         tegra30_init_clocks();
         tegra_clk_init_from_table(tegra30_clk_init_table);
-        tegra_init_cache(0x441, 0x551);
+        tegra_init_cache();
         tegra_pmc_init();
         tegra_powergate_init();
         tegra30_hotplug_init();
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
new file mode 100644
index 000000000000..d32e8b0dbd4f
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -0,0 +1,66 @@
+/*
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpuidle.h>
+
+#include <asm/cpuidle.h>
+
+static struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+        .state_count = 1,
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+        },
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+
+int __init tegra20_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
new file mode 100644
index 000000000000..5e8cbf5b799f
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -0,0 +1,188 @@
+/*
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
+
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+
+#include "pm.h"
+#include "sleep.h"
+#include "tegra_cpu_car.h"
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra30_idle_lp2(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv,
+                            int index);
+#endif
+
+static struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+#ifdef CONFIG_PM_SLEEP
+        .state_count = 2,
+#else
+        .state_count = 1,
+#endif
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+                [1] = {
+                        .enter                  = tegra30_idle_lp2,
+                        .exit_latency           = 2000,
+                        .target_residency       = 2200,
+                        .power_usage            = 0,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "powered-down",
+                        .desc                   = "CPU power gated",
+                },
+#endif
+        },
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+
+#ifdef CONFIG_PM_SLEEP
+static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
+                                           struct cpuidle_driver *drv,
+                                           int index)
+{
+        struct cpuidle_state *state = &drv->states[index];
+        u32 cpu_on_time = state->exit_latency;
+        u32 cpu_off_time = state->target_residency - state->exit_latency;
+
+        /* All CPUs entering LP2 is not working.
+         * Don't let CPU0 enter LP2 when any secondary CPU is online.
+         */
+        if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
+                cpu_do_idle();
+                return false;
+        }
+
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+        return true;
+}
+
+#ifdef CONFIG_SMP
+static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
+                                        struct cpuidle_driver *drv,
+                                        int index)
+{
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+        smp_wmb();
+
+        save_cpu_arch_register();
+
+        cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+
+        restore_cpu_arch_register();
+
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+        return true;
+}
+#else
+static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
+                                               struct cpuidle_driver *drv,
+                                               int index)
+{
+        return true;
+}
+#endif
+
+static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
+                                      struct cpuidle_driver *drv,
+                                      int index)
+{
+        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
+        bool entered_lp2 = false;
+        bool last_cpu;
+
+        local_fiq_disable();
+
+        last_cpu = tegra_set_cpu_in_lp2(cpu);
+        cpu_pm_enter();
+
+        if (cpu == 0) {
+                if (last_cpu)
+                        entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
+                                                                     index);
+                else
+                        cpu_do_idle();
+        } else {
+                entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
+        }
+
+        cpu_pm_exit();
+        tegra_clear_cpu_in_lp2(cpu);
+
+        local_fiq_enable();
+
+        smp_rmb();
+
+        return (entered_lp2) ? index : 0;
+}
+#endif
+
+int __init tegra30_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+
+#ifdef CONFIG_PM_SLEEP
+        tegra_tear_down_cpu = tegra30_tear_down_cpu;
+#endif
+
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 9a6f051b382e..d0651397aec7 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -23,83 +23,26 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/cpu.h>
-#include <linux/cpuidle.h>
-#include <linux/hrtimer.h>
 
-#include <asm/proc-fns.h>
-
-static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv, int index);
-
-struct cpuidle_driver tegra_idle_driver = {
-        .name = "tegra_idle",
-        .owner = THIS_MODULE,
-        .state_count = 1,
-        .states = {
-                [0] = {
-                        .enter                  = tegra_idle_enter_lp3,
-                        .exit_latency           = 10,
-                        .target_residency       = 10,
-                        .power_usage            = 600,
-                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                        .name                   = "LP3",
-                        .desc                   = "CPU flow-controlled",
-                },
-        },
-};
-
-static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-
-static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
-        struct cpuidle_driver *drv, int index)
-{
-        ktime_t enter, exit;
-        s64 us;
-
-        local_irq_disable();
-        local_fiq_disable();
-
-        enter = ktime_get();
-
-        cpu_do_idle();
-
-        exit = ktime_sub(ktime_get(), enter);
-        us = ktime_to_us(exit);
-
-        local_fiq_enable();
-        local_irq_enable();
-
-        dev->last_residency = us;
-
-        return index;
-}
+#include "fuse.h"
+#include "cpuidle.h"
 
 static int __init tegra_cpuidle_init(void)
 {
         int ret;
-        unsigned int cpu;
-        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &tegra_idle_driver;
 
-        ret = cpuidle_register_driver(&tegra_idle_driver);
-        if (ret) {
-                pr_err("CPUidle driver registration failed\n");
-                return ret;
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                ret = tegra20_cpuidle_init();
+                break;
+        case TEGRA30:
+                ret = tegra30_cpuidle_init();
+                break;
+        default:
+                ret = -ENODEV;
+                break;
         }
 
-        for_each_possible_cpu(cpu) {
-                dev = &per_cpu(tegra_idle_device, cpu);
-                dev->cpu = cpu;
-
-                dev->state_count = drv->state_count;
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("CPU%u: CPUidle device registration failed\n",
-                                cpu);
-                        return ret;
-                }
-        }
-        return 0;
+        return ret;
 }
 device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
new file mode 100644
index 000000000000..496204d34e55
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPUIDLE_H
+#define __MACH_TEGRA_CPUIDLE_H
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+int tegra20_cpuidle_init(void);
+#else
+static inline int tegra20_cpuidle_init(void) { return -ENODEV; }
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+int tegra30_cpuidle_init(void);
+#else
+static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index ffaa286a71e1..a2250ddae797 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/cpumask.h>
 
 #include "flowctrl.h"
 #include "iomap.h"
@@ -50,6 +51,14 @@ static void flowctrl_update(u8 offset, u32 value)
         readl_relaxed(addr);
 }
 
+u32 flowctrl_read_cpu_csr(unsigned int cpuid)
+{
+        u8 offset = flowctrl_offset_cpu_csr[cpuid];
+        void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
+
+        return readl(addr);
+}
+
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
 {
         return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
@@ -59,3 +68,41 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
 {
         return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
 }
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid)
+{
+        unsigned int reg;
+        int i;
+
+        reg = flowctrl_read_cpu_csr(cpuid);
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
+        reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr flag */
+        reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event flag */
+        reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
+        reg |= FLOW_CTRL_CSR_ENABLE;                    /* pwr gating */
+        flowctrl_write_cpu_csr(cpuid, reg);
+
+        for (i = 0; i < num_possible_cpus(); i++) {
+                if (i == cpuid)
+                        continue;
+                reg = flowctrl_read_cpu_csr(i);
+                reg |= FLOW_CTRL_CSR_EVENT_FLAG;
+                reg |= FLOW_CTRL_CSR_INTR_FLAG;
+                flowctrl_write_cpu_csr(i, reg);
+        }
+}
+
+void flowctrl_cpu_suspend_exit(unsigned int cpuid)
+{
+        unsigned int reg;
+
+        /* Disable powergating via flow controller for CPU0 */
+        reg = flowctrl_read_cpu_csr(cpuid);
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
+        reg &= ~FLOW_CTRL_CSR_ENABLE;                   /* clear enable */
+        reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr */
+        reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event */
+        flowctrl_write_cpu_csr(cpuid, reg);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 19428173855e..0798dec1832d 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,9 +34,17 @@
 #define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
 #define FLOW_CTRL_CPU1_CSR              0x18
 
+#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
+#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
+#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
+
 #ifndef __ASSEMBLY__
+u32 flowctrl_read_cpu_csr(unsigned int cpuid);
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid);
+void flowctrl_cpu_suspend_exit(unsigned int cpuid);
 #endif
 
 #endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 6c752e8f1f06..8121742711fe 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -28,14 +28,21 @@
 #define FUSE_UID_LOW            0x108
 #define FUSE_UID_HIGH           0x10c
 #define FUSE_SKU_INFO           0x110
-#define FUSE_SPARE_BIT          0x200
+
+#define TEGRA20_FUSE_SPARE_BIT          0x200
+#define TEGRA30_FUSE_SPARE_BIT          0x244
 
 int tegra_sku_id;
 int tegra_cpu_process_id;
 int tegra_core_process_id;
 int tegra_chip_id;
+int tegra_cpu_speedo_id;                /* only exist in Tegra30 and later */
+int tegra_soc_speedo_id;
 enum tegra_revision tegra_revision;
 
+static int tegra_fuse_spare_bit;
+static void (*tegra_init_speedo_data)(void);
+
 /* The BCT to use at boot is specified by board straps that can be read
  * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
  */
@@ -56,14 +63,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
         [TEGRA_REVISION_A04]     = "A04",
 };
 
-static inline u32 tegra_fuse_readl(unsigned long offset)
+u32 tegra_fuse_readl(unsigned long offset)
 {
         return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
 }
 
-static inline bool get_spare_fuse(int bit)
+bool tegra_spare_fuse(int bit)
 {
-        return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
+        return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
 }
 
 static enum tegra_revision tegra_get_revision(u32 id)
@@ -77,7 +84,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
                 return TEGRA_REVISION_A02;
         case 3:
                 if (tegra_chip_id == TEGRA20 &&
-                        (get_spare_fuse(18) || get_spare_fuse(19)))
+                        (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
                         return TEGRA_REVISION_A03p;
                 else
                         return TEGRA_REVISION_A03;
@@ -88,6 +95,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
         }
 }
 
+static void tegra_get_process_id(void)
+{
+        u32 reg;
+
+        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
+        tegra_cpu_process_id = (reg >> 6) & 3;
+        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
+        tegra_core_process_id = (reg >> 12) & 3;
+}
+
 void tegra_init_fuse(void)
 {
         u32 id;
@@ -99,19 +116,29 @@ void tegra_init_fuse(void)
         reg = tegra_fuse_readl(FUSE_SKU_INFO);
         tegra_sku_id = reg & 0xFF;
 
-        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
-        tegra_cpu_process_id = (reg >> 6) & 3;
-
-        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
-        tegra_core_process_id = (reg >> 12) & 3;
-
         reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
         tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
 
         id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
         tegra_chip_id = (id >> 8) & 0xff;
 
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
+                tegra_init_speedo_data = &tegra20_init_speedo_data;
+                break;
+        case TEGRA30:
+                tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
+                tegra_init_speedo_data = &tegra30_init_speedo_data;
+                break;
+        default:
+                pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
+                tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
+                tegra_init_speedo_data = &tegra_get_process_id;
+        }
+
         tegra_revision = tegra_get_revision(id);
+        tegra_init_speedo_data();
 
         pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
                 tegra_revision_name[tegra_revision],
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index d2107b2cb85a..ff1383dd61a7 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -42,11 +42,27 @@ extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
 extern int tegra_chip_id;
+extern int tegra_cpu_speedo_id;         /* only exist in Tegra30 and later */
+extern int tegra_soc_speedo_id;
 extern enum tegra_revision tegra_revision;
 
 extern int tegra_bct_strapping;
 
 unsigned long long tegra_chip_uid(void);
 void tegra_init_fuse(void);
+bool tegra_spare_fuse(int bit);
+u32 tegra_fuse_readl(unsigned long offset);
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void tegra20_init_speedo_data(void);
+#else
+static inline void tegra20_init_speedo_data(void) {}
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void tegra30_init_speedo_data(void);
+#else
+static inline void tegra30_init_speedo_data(void) {}
+#endif
 
 #endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 93f0370cc95b..4a317fae6860 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -2,6 +2,8 @@
 #include <linux/init.h>
 
 #include <asm/cache.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include "flowctrl.h"
 #include "iomap.h"
@@ -68,6 +70,64 @@ ENTRY(tegra_secondary_startup)
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
 
+#ifdef CONFIG_PM_SLEEP
+/*
+ *      tegra_resume
+ *
+ *        CPU boot vector when restarting the a CPU following
+ *        an LP2 transition. Also branched to by LP0 and LP1 resume after
+ *        re-enabling sdram.
+ */
+ENTRY(tegra_resume)
+        bl      v7_invalidate_l1
+        /* Enable coresight */
+        mov32   r0, 0xC5ACCE55
+        mcr     p14, 0, r0, c7, c12, 6
+
+        cpu_id  r0
+        cmp     r0, #0                          @ CPU0?
+        bne     cpu_resume                      @ no
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        beq     1f                              @ Yes
+        /* Clear the flow controller flags for this CPU. */
+        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
+        ldr     r1, [r2]
+        /* Clear event & intr flag */
+        orr     r1, r1, \
+                #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
+        bic     r1, r1, r0
+        str     r1, [r2]
+1:
+#endif
+
+#ifdef CONFIG_HAVE_ARM_SCU
+        /* enable SCU */
+        mov32   r0, TEGRA_ARM_PERIF_BASE
+        ldr     r1, [r0]
+        orr     r1, r1, #1
+        str     r1, [r0]
+#endif
+
+        /* L2 cache resume & re-enable */
+        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+
+        b       cpu_resume
+ENDPROC(tegra_resume)
+#endif
+
+#ifdef CONFIG_CACHE_L2X0
+        .globl  l2x0_saved_regs_addr
+l2x0_saved_regs_addr:
+        .long   0
+#endif
+
         .align L1_CACHE_SHIFT
 ENTRY(__tegra_cpu_reset_handler_start)
 
@@ -121,6 +181,17 @@ ENTRY(__tegra_cpu_reset_handler)
 1:
 #endif
 
+        /* Waking up from LP2? */
+        ldr     r9, [r12, #RESET_DATA(MASK_LP2)]
+        tst     r9, r11                         @ if in_lp2
+        beq     __is_not_lp2
+        ldr     lr, [r12, #RESET_DATA(STARTUP_LP2)]
+        cmp     lr, #0
+        bleq    __die                           @ no LP2 startup handler
+        bx      lr
+
+__is_not_lp2:
+
 #ifdef CONFIG_SMP
         /*
          * Can only be secondary boot (initial or hotplug) but CPU 0
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
new file mode 100644
index 000000000000..1b11707eaca0
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.c
@@ -0,0 +1,216 @@
+/*
+ * CPU complex suspend & resume functions for Tegra SoCs
+ *
+ * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/cpu_pm.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
+#include <asm/suspend.h>
+#include <asm/idmap.h>
+#include <asm/proc-fns.h>
+#include <asm/tlbflush.h>
+
+#include "iomap.h"
+#include "reset.h"
+#include "flowctrl.h"
+#include "sleep.h"
+#include "tegra_cpu_car.h"
+
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+
+#define PMC_CTRL                0x0
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+
+#ifdef CONFIG_PM_SLEEP
+static unsigned int g_diag_reg;
+static DEFINE_SPINLOCK(tegra_lp2_lock);
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+static struct clk *tegra_pclk;
+void (*tegra_tear_down_cpu)(void);
+
+void save_cpu_arch_register(void)
+{
+        /* read diagnostic register */
+        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
+        return;
+}
+
+void restore_cpu_arch_register(void)
+{
+        /* write diagnostic register */
+        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
+        return;
+}
+
+static void set_power_timers(unsigned long us_on, unsigned long us_off)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        unsigned long rate;
+        static unsigned long tegra_last_pclk;
+
+        if (tegra_pclk == NULL) {
+                tegra_pclk = clk_get_sys(NULL, "pclk");
+                WARN_ON(IS_ERR(tegra_pclk));
+        }
+
+        rate = clk_get_rate(tegra_pclk);
+
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
+
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+
+/*
+ * restore_cpu_complex
+ *
+ * restores cpu clock setting, clears flow controller
+ *
+ * Always called on CPU 0.
+ */
+static void restore_cpu_complex(void)
+{
+        int cpu = smp_processor_id();
+
+        BUG_ON(cpu != 0);
+
+#ifdef CONFIG_SMP
+        cpu = cpu_logical_map(cpu);
+#endif
+
+        /* Restore the CPU clock settings */
+        tegra_cpu_clock_resume();
+
+        flowctrl_cpu_suspend_exit(cpu);
+
+        restore_cpu_arch_register();
+}
+
+/*
+ * suspend_cpu_complex
+ *
+ * saves pll state for use by restart_plls, prepares flow controller for
+ * transition to suspend state
+ *
+ * Must always be called on cpu 0.
+ */
+static void suspend_cpu_complex(void)
+{
+        int cpu = smp_processor_id();
+
+        BUG_ON(cpu != 0);
+
+#ifdef CONFIG_SMP
+        cpu = cpu_logical_map(cpu);
+#endif
+
+        /* Save the CPU clock settings */
+        tegra_cpu_clock_suspend();
+
+        flowctrl_cpu_suspend_enter(cpu);
+
+        save_cpu_arch_register();
+}
+
+void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
+{
+        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
+
+        spin_lock(&tegra_lp2_lock);
+
+        BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
+        *cpu_in_lp2 &= ~BIT(phy_cpu_id);
+
+        spin_unlock(&tegra_lp2_lock);
+}
+
+bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
+{
+        bool last_cpu = false;
+        cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
+        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
+
+        spin_lock(&tegra_lp2_lock);
+
+        BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
+        *cpu_in_lp2 |= BIT(phy_cpu_id);
+
+        if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
+                last_cpu = true;
+
+        spin_unlock(&tegra_lp2_lock);
+        return last_cpu;
+}
+
+static int tegra_sleep_cpu(unsigned long v2p)
+{
+        /* Switch to the identity mapping. */
+        cpu_switch_mm(idmap_pgd, &init_mm);
+
+        /* Flush the TLB. */
+        local_flush_tlb_all();
+
+        tegra_sleep_cpu_finish(v2p);
+
+        /* should never here */
+        BUG();
+
+        return 0;
+}
+
+void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+{
+        u32 mode;
+
+        /* Only the last cpu down does the final suspend steps */
+        mode = readl(pmc + PMC_CTRL);
+        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
+        writel(mode, pmc + PMC_CTRL);
+
+        set_power_timers(cpu_on_time, cpu_off_time);
+
+        cpu_cluster_pm_enter();
+        suspend_cpu_complex();
+
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+        restore_cpu_complex();
+        cpu_cluster_pm_exit();
+}
+#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
new file mode 100644
index 000000000000..787335cc964c
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MACH_TEGRA_PM_H_
+#define _MACH_TEGRA_PM_H_
+
+extern unsigned long l2x0_saved_regs_addr;
+
+void save_cpu_arch_register(void);
+void restore_cpu_arch_register(void);
+
+void tegra_clear_cpu_in_lp2(int phy_cpu_id);
+bool tegra_set_cpu_in_lp2(int phy_cpu_id);
+
+void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+extern void (*tegra_tear_down_cpu)(void);
+
+#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index e05da7d10c3b..3fd89ecd158e 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -25,6 +25,7 @@
 #include "iomap.h"
 #include "irammap.h"
 #include "reset.h"
+#include "sleep.h"
 #include "fuse.h"
 
 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
@@ -79,5 +80,10 @@ void __init tegra_cpu_reset_handler_init(void)
                 virt_to_phys((void *)tegra_secondary_startup);
 #endif
 
+#ifdef CONFIG_PM_SLEEP
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
+                virt_to_phys((void *)tegra_resume);
+#endif
+
         tegra_cpu_reset_handler_enable();
 }
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index de88bf851dd3..c90d8e9c4ad2 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -29,6 +29,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include "irammap.h"
+
 extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
 
 void __tegra_cpu_reset_handler_start(void);
@@ -36,6 +38,13 @@ void __tegra_cpu_reset_handler(void);
 void __tegra_cpu_reset_handler_end(void);
 void tegra_secondary_startup(void);
 
+#ifdef CONFIG_PM_SLEEP
+#define tegra_cpu_lp2_mask \
+        (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
+        ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
+         (u32)__tegra_cpu_reset_handler_start)))
+#endif
+
 #define tegra_cpu_reset_handler_offset \
                 ((u32)__tegra_cpu_reset_handler - \
                  (u32)__tegra_cpu_reset_handler_start)
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 72ce709799da..72ce709799da 100644
--- a/arch/arm/mach-tegra/sleep-t20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index be7614b7c5cb..562a8e7e413d 100644
--- a/arch/arm/mach-tegra/sleep-t30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -17,6 +17,7 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
+#include <asm/asm-offsets.h>
 
 #include "sleep.h"
 #include "flowctrl.h"
@@ -80,6 +81,7 @@ delay_1:
         ldr     r3, [r1]                        @ read CSR
         str     r3, [r1]                        @ clear CSR
         tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
         movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
         str     r3, [r2]
         ldr     r0, [r2]
@@ -103,3 +105,67 @@ wfe_war:
 
 ENDPROC(tegra30_cpu_shutdown)
 #endif
+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
+ */
+ENTRY(tegra30_sleep_cpu_secondary_finish)
+        mov     r7, lr
+
+        /* Flush and disable the L1 data cache */
+        bl      tegra_disable_clean_inv_dcache
+
+        /* Powergate this CPU. */
+        mov     r0, #0                          @ power mode flags (!hotplug)
+        bl      tegra30_cpu_shutdown
+        mov     r0, #1                          @ never return here
+        mov     pc, r7
+ENDPROC(tegra30_sleep_cpu_secondary_finish)
+
+/*
+ * tegra30_tear_down_cpu
+ *
+ * Switches the CPU to enter sleep.
+ */
+ENTRY(tegra30_tear_down_cpu)
+        mov32   r6, TEGRA_FLOW_CTRL_BASE
+
+        b       tegra30_enter_sleep
+ENDPROC(tegra30_tear_down_cpu)
+
+/*
+ * tegra30_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
+ * executes from SDRAM with target state is LP2
+ * r6 = TEGRA_FLOW_CTRL_BASE
+ */
+tegra30_enter_sleep:
+        cpu_id  r1
+
+        cpu_to_csr_reg  r2, r1
+        ldr     r0, [r6, r2]
+        orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
+        str     r0, [r6, r2]
+
+        mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+        orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+        cpu_to_halt_reg r2, r1
+        str     r0, [r6, r2]
+        dsb
+        ldr     r0, [r6, r2] /* memory barrier */
+
+halted:
+        isb
+        dsb
+        wfi     /* CPU should be power gated here */
+
+        /* !!!FIXME!!! Implement halt failure handler */
+        b       halted
+
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 08e9481c049e..26afa7cbed11 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -25,9 +25,87 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
+#include <asm/cache.h>
+#include <asm/cp15.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include "iomap.h"
 
 #include "flowctrl.h"
 #include "sleep.h"
 
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_disable_clean_inv_dcache
+ *
+ * disable, clean & invalidate the D-cache
+ *
+ * Corrupted registers: r1-r3, r6, r8, r9-r11
+ */
+ENTRY(tegra_disable_clean_inv_dcache)
+        stmfd   sp!, {r0, r4-r5, r7, r9-r11, lr}
+        dmb                                     @ ensure ordering
+
+        /* Disable the D-cache */
+        mrc     p15, 0, r2, c1, c0, 0
+        bic     r2, r2, #CR_C
+        mcr     p15, 0, r2, c1, c0, 0
+        isb
+
+        /* Flush the D-cache */
+        bl      v7_flush_dcache_louis
+
+        /* Trun off coherency */
+        exit_smp r4, r5
+
+        ldmfd   sp!, {r0, r4-r5, r7, r9-r11, pc}
+ENDPROC(tegra_disable_clean_inv_dcache)
+
+/*
+ * tegra_sleep_cpu_finish(unsigned long v2p)
+ *
+ * enters suspend in LP2 by turning off the mmu and jumping to
+ * tegra?_tear_down_cpu
+ */
+ENTRY(tegra_sleep_cpu_finish)
+        /* Flush and disable the L1 data cache */
+        bl      tegra_disable_clean_inv_dcache
+
+        mov32   r6, tegra_tear_down_cpu
+        ldr     r1, [r6]
+        add     r1, r1, r0
+
+        mov32   r3, tegra_shut_off_mmu
+        add     r3, r3, r0
+        mov     r0, r1
+
+        mov     pc, r3
+ENDPROC(tegra_sleep_cpu_finish)
+
+/*
+ * tegra_shut_off_mmu
+ *
+ * r0 = physical address to jump to with mmu off
+ *
+ * called with VA=PA mapping
+ * turns off MMU, icache, dcache and branch prediction
+ */
+        .align  L1_CACHE_SHIFT
+        .pushsection    .idmap.text, "ax"
+ENTRY(tegra_shut_off_mmu)
+        mrc     p15, 0, r3, c1, c0, 0
+        movw    r2, #CR_I | CR_Z | CR_C | CR_M
+        bic     r3, r3, r2
+        dsb
+        mcr     p15, 0, r3, c1, c0, 0
+        isb
+#ifdef CONFIG_CACHE_L2X0
+        /* Disable L2 cache */
+        mov32   r4, TEGRA_ARM_PERIF_BASE + 0x3000
+        mov     r5, #0
+        str     r5, [r4, #L2X0_CTRL]
+#endif
+        mov     pc, r0
+ENDPROC(tegra_shut_off_mmu)
+        .popsection
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4889b281c5f9..9821ee725420 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -71,7 +71,41 @@
         str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
         dsb
 .endm
+
+/* Macro to resume & re-enable L2 cache */
+#ifndef L2X0_CTRL_EN
+#define L2X0_CTRL_EN    1
+#endif
+
+#ifdef CONFIG_CACHE_L2X0
+.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
+        adr     \tmp1, \phys_l2x0_saved_regs
+        ldr     \tmp1, [\tmp1]
+        ldr     \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
+        ldr     \tmp3, [\tmp2, #L2X0_CTRL]
+        tst     \tmp3, #L2X0_CTRL_EN
+        bne     exit_l2_resume
+        ldr     \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
+        str     \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
+        str     \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
+        str     \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
+        str     \tmp3, [\tmp2, #L2X0_POWER_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
+        str     \tmp3, [\tmp2, #L2X0_AUX_CTRL]
+        mov     \tmp3, #L2X0_CTRL_EN
+        str     \tmp3, [\tmp2, #L2X0_CTRL]
+exit_l2_resume:
+.endm
+#else /* CONFIG_CACHE_L2X0 */
+.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
+.endm
+#endif /* CONFIG_CACHE_L2X0 */
 #else
+void tegra_resume(void);
+int tegra_sleep_cpu_finish(unsigned long);
 
 #ifdef CONFIG_HOTPLUG_CPU
 void tegra20_hotplug_init(void);
@@ -81,5 +115,8 @@ static inline void tegra20_hotplug_init(void) {}
 static inline void tegra30_hotplug_init(void) {}
 #endif
 
+int tegra30_sleep_cpu_secondary_finish(unsigned long);
+void tegra30_tear_down_cpu(void);
+
 #endif
 #endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 9615ee39c353..a23a0734e352 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -246,11 +246,16 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
         { 19200000, 216000000, 135, 12, 1, 3},
         { 26000000, 216000000, 216, 26, 1, 4},
 
+        { 12000000, 297000000,  99,  4, 1, 4 },
+        { 12000000, 339000000, 113,  4, 1, 4 },
+
         { 12000000, 594000000, 594, 12, 1, 8},
         { 13000000, 594000000, 594, 13, 1, 8},
         { 19200000, 594000000, 495, 16, 1, 8},
         { 26000000, 594000000, 594, 26, 1, 8},
 
+        { 12000000, 616000000, 616, 12, 1, 8},
+
         { 12000000, 1000000000, 1000, 12, 1, 12},
         { 13000000, 1000000000, 1000, 13, 1, 12},
         { 19200000, 1000000000, 625,  12, 1, 8},
@@ -1036,9 +1041,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("usbd",   "utmip-pad",    NULL),
         CLK_DUPLICATE("usbd",   "tegra-ehci.0", NULL),
         CLK_DUPLICATE("usbd",   "tegra-otg",    NULL),
-        CLK_DUPLICATE("hdmi",   "tegradc.0",    "hdmi"),
-        CLK_DUPLICATE("hdmi",   "tegradc.1",    "hdmi"),
-        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
         CLK_DUPLICATE("2d",     "tegra_grhost", "gr2d"),
         CLK_DUPLICATE("3d",     "tegra_grhost", "gr3d"),
         CLK_DUPLICATE("epp",    "tegra_grhost", "epp"),
@@ -1051,6 +1053,9 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
+        CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
+        CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
+        CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
 };
 
 #define CLK(dev, con, ck)       \
diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/arch/arm/mach-tegra/tegra20_speedo.c
new file mode 100644
index 000000000000..fa6eb570623f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_speedo.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CPU_SPEEDO_LSBIT                20
+#define CPU_SPEEDO_MSBIT                29
+#define CPU_SPEEDO_REDUND_LSBIT         30
+#define CPU_SPEEDO_REDUND_MSBIT         39
+#define CPU_SPEEDO_REDUND_OFFS  (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
+
+#define CORE_SPEEDO_LSBIT               40
+#define CORE_SPEEDO_MSBIT               47
+#define CORE_SPEEDO_REDUND_LSBIT        48
+#define CORE_SPEEDO_REDUND_MSBIT        55
+#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
+
+#define SPEEDO_MULT                     4
+
+#define PROCESS_CORNERS_NUM             4
+
+#define SPEEDO_ID_SELECT_0(rev)         ((rev) <= 2)
+#define SPEEDO_ID_SELECT_1(sku)         \
+        (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
+         ((sku) != 27) && ((sku) != 28))
+
+enum {
+        SPEEDO_ID_0,
+        SPEEDO_ID_1,
+        SPEEDO_ID_2,
+        SPEEDO_ID_COUNT,
+};
+
+static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
+        {315, 366, 420, UINT_MAX},
+        {303, 368, 419, UINT_MAX},
+        {316, 331, 383, UINT_MAX},
+};
+
+static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
+        {165, 195, 224, UINT_MAX},
+        {165, 195, 224, UINT_MAX},
+        {165, 195, 224, UINT_MAX},
+};
+
+void tegra20_init_speedo_data(void)
+{
+        u32 reg;
+        u32 val;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
+
+        if (SPEEDO_ID_SELECT_0(tegra_revision))
+                tegra_soc_speedo_id = SPEEDO_ID_0;
+        else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
+                tegra_soc_speedo_id = SPEEDO_ID_1;
+        else
+                tegra_soc_speedo_id = SPEEDO_ID_2;
+
+        val = 0;
+        for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
+                reg = tegra_spare_fuse(i) |
+                        tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
+                val = (val << 1) | (reg & 0x1);
+        }
+        val = val * SPEEDO_MULT;
+        pr_debug("%s CPU speedo value %u\n", __func__, val);
+
+        for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+                if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
+                        break;
+        }
+        tegra_cpu_process_id = i;
+
+        val = 0;
+        for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
+                reg = tegra_spare_fuse(i) |
+                        tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
+                val = (val << 1) | (reg & 0x1);
+        }
+        val = val * SPEEDO_MULT;
+        pr_debug("%s Core speedo value %u\n", __func__, val);
+
+        for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+                if (val <= core_process_speedos[tegra_soc_speedo_id][i])
+                        break;
+        }
+        tegra_core_process_id = i;
+
+        pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
+}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 000239d68393..efc000e32e1c 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -31,6 +31,8 @@
 
 #include <asm/clkdev.h>
 
+#include <mach/powergate.h>
+
 #include "clock.h"
 #include "fuse.h"
 #include "iomap.h"
@@ -309,6 +311,31 @@
 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
 
+#define CLK_RESET_CCLK_BURST    0x20
+#define CLK_RESET_CCLK_DIVIDER  0x24
+#define CLK_RESET_PLLX_BASE     0xe0
+#define CLK_RESET_PLLX_MISC     0xe4
+
+#define CLK_RESET_SOURCE_CSITE  0x1d4
+
+#define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
+#define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
+#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
+#define CLK_RESET_CCLK_IDLE_POLICY              1
+#define CLK_RESET_CCLK_RUN_POLICY               2
+#define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
+
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+        u32 pllx_misc;
+        u32 pllx_base;
+
+        u32 cpu_burst;
+        u32 clk_csite_src;
+        u32 cclk_divider;
+} tegra30_cpu_clk_sctx;
+#endif
+
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -791,6 +818,112 @@ struct clk_ops tegra30_twd_ops = {
         .recalc_rate = tegra30_twd_clk_recalc_rate,
 };
 
+/* bus clock functions */
+static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+        return c->state;
+}
+
+static int tegra30_bus_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = clk_readl(c->reg);
+        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+static void tegra30_bus_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = clk_readl(c->reg);
+        val |= BUS_CLK_DISABLE << c->reg_shift;
+        clk_writel(val, c->reg);
+}
+
+static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u64 rate = prate;
+
+        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+        c->mul = 1;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int ret = -EINVAL;
+        u32 val;
+        int i;
+
+        val = clk_readl(c->reg);
+        for (i = 1; i <= 4; i++) {
+                if (rate == parent_rate / i) {
+                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+                        val |= (i - 1) << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = i;
+                        c->mul = 1;
+                        ret = 0;
+                        break;
+                }
+        }
+
+        return ret;
+}
+
+static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        s64 divider;
+
+        if (rate >= parent_rate)
+                return parent_rate;
+
+        divider = parent_rate;
+        divider += rate - 1;
+        do_div(divider, rate);
+
+        if (divider < 0)
+                return divider;
+
+        if (divider > 4)
+                divider = 4;
+        do_div(parent_rate, divider);
+
+        return parent_rate;
+}
+
+struct clk_ops tegra30_bus_ops = {
+        .is_enabled = tegra30_bus_clk_is_enabled,
+        .enable = tegra30_bus_clk_enable,
+        .disable = tegra30_bus_clk_disable,
+        .set_rate = tegra30_bus_clk_set_rate,
+        .round_rate = tegra30_bus_clk_round_rate,
+        .recalc_rate = tegra30_bus_clk_recalc_rate,
+};
+
 /* Blink output functions */
 static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
 {
@@ -2280,12 +2413,93 @@ static void tegra30_disable_cpu_clock(u32 cpu)
                reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 }
 
+#ifdef CONFIG_PM_SLEEP
+static bool tegra30_cpu_rail_off_ready(void)
+{
+        unsigned int cpu_rst_status;
+        int cpu_pwr_status;
+
+        cpu_rst_status = readl(reg_clk_base +
+                               TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+        cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
+                         tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
+                         tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
+
+        if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
+                return false;
+
+        return true;
+}
+
+static void tegra30_cpu_clock_suspend(void)
+{
+        /* switch coresite to clk_m, save off original source */
+        tegra30_cpu_clk_sctx.clk_csite_src =
+                                readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
+        writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
+
+        tegra30_cpu_clk_sctx.cpu_burst =
+                                readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+        tegra30_cpu_clk_sctx.pllx_base =
+                                readl(reg_clk_base + CLK_RESET_PLLX_BASE);
+        tegra30_cpu_clk_sctx.pllx_misc =
+                                readl(reg_clk_base + CLK_RESET_PLLX_MISC);
+        tegra30_cpu_clk_sctx.cclk_divider =
+                                readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+}
+
+static void tegra30_cpu_clock_resume(void)
+{
+        unsigned int reg, policy;
+
+        /* Is CPU complex already running on PLLX? */
+        reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+        policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
+
+        if (policy == CLK_RESET_CCLK_IDLE_POLICY)
+                reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
+        else if (policy == CLK_RESET_CCLK_RUN_POLICY)
+                reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
+        else
+                BUG();
+
+        if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
+                /* restore PLLX settings if CPU is on different PLL */
+                writel(tegra30_cpu_clk_sctx.pllx_misc,
+                                        reg_clk_base + CLK_RESET_PLLX_MISC);
+                writel(tegra30_cpu_clk_sctx.pllx_base,
+                                        reg_clk_base + CLK_RESET_PLLX_BASE);
+
+                /* wait for PLL stabilization if PLLX was enabled */
+                if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
+                        udelay(300);
+        }
+
+        /*
+         * Restore original burst policy setting for calls resulting from CPU
+         * LP2 in idle or system suspend.
+         */
+        writel(tegra30_cpu_clk_sctx.cclk_divider,
+                                        reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+        writel(tegra30_cpu_clk_sctx.cpu_burst,
+                                        reg_clk_base + CLK_RESET_CCLK_BURST);
+
+        writel(tegra30_cpu_clk_sctx.clk_csite_src,
+                                        reg_clk_base + CLK_RESET_SOURCE_CSITE);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
         .wait_for_reset = tegra30_wait_cpu_in_reset,
         .put_in_reset   = tegra30_put_cpu_in_reset,
         .out_of_reset   = tegra30_cpu_out_of_reset,
         .enable_clock   = tegra30_enable_cpu_clock,
         .disable_clock  = tegra30_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+        .rail_off_ready = tegra30_cpu_rail_off_ready,
+        .suspend        = tegra30_cpu_clock_suspend,
+        .resume         = tegra30_cpu_clock_resume,
+#endif
 };
 
 void __init tegra30_cpu_car_ops_init(void)
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index f2f88fef6b8b..7a34adb2f72d 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -34,6 +34,7 @@ extern struct clk_ops tegra_clk_out_ops;
 extern struct clk_ops tegra30_super_ops;
 extern struct clk_ops tegra30_blink_clk_ops;
 extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_bus_ops;
 extern struct clk_ops tegra30_periph_clk_ops;
 extern struct clk_ops tegra30_dsib_clk_ops;
 extern struct clk_ops tegra_nand_clk_ops;
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 3d2e5532a9ea..6942c7add3bb 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -711,6 +711,50 @@ static struct clk tegra_clk_sclk = {
         .num_parents = ARRAY_SIZE(mux_sclk),
 };
 
+static const char *tegra_hclk_parent_names[] = {
+        "tegra_sclk",
+};
+
+static struct clk *tegra_hclk_parents[] = {
+        &tegra_clk_sclk,
+};
+
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+        .hw = {
+                .clk = &tegra_hclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 4,
+        .max_rate = 378000000,
+        .min_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
+                tegra_hclk_parents, &tegra_clk_sclk);
+
+static const char *tegra_pclk_parent_names[] = {
+        "tegra_hclk",
+};
+
+static struct clk *tegra_pclk_parents[] = {
+        &tegra_hclk,
+};
+
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+        .hw = {
+                .clk = &tegra_pclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 0,
+        .max_rate = 167000000,
+        .min_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
+                tegra_pclk_parents, &tegra_hclk);
+
 static const char *mux_blink[] = {
         "clk_32k",
 };
@@ -1254,8 +1298,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("usbd", "utmip-pad", NULL),
         CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
         CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
         CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
         CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
         CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
@@ -1293,6 +1335,9 @@ struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
+        CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
+        CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
+        CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
 };
 
 struct clk *tegra_ptr_clks[] = {
@@ -1325,6 +1370,8 @@ struct clk *tegra_ptr_clks[] = {
         &tegra_cml1,
         &tegra_pciex,
         &tegra_clk_sclk,
+        &tegra_hclk,
+        &tegra_pclk,
         &tegra_clk_blink,
         &tegra30_clk_twd,
 };
diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/arch/arm/mach-tegra/tegra30_speedo.c
new file mode 100644
index 000000000000..125cb16424a6
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_speedo.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM        1
+#define CPU_PROCESS_CORNERS_NUM         6
+
+#define FUSE_SPEEDO_CALIB_0     0x114
+#define FUSE_PACKAGE_INFO       0X1FC
+#define FUSE_TEST_PROG_VER      0X128
+
+#define G_SPEEDO_BIT_MINUS1     58
+#define G_SPEEDO_BIT_MINUS1_R   59
+#define G_SPEEDO_BIT_MINUS2     60
+#define G_SPEEDO_BIT_MINUS2_R   61
+#define LP_SPEEDO_BIT_MINUS1    62
+#define LP_SPEEDO_BIT_MINUS1_R  63
+#define LP_SPEEDO_BIT_MINUS2    64
+#define LP_SPEEDO_BIT_MINUS2_R  65
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_2,
+        THRESHOLD_INDEX_3,
+        THRESHOLD_INDEX_4,
+        THRESHOLD_INDEX_5,
+        THRESHOLD_INDEX_6,
+        THRESHOLD_INDEX_7,
+        THRESHOLD_INDEX_8,
+        THRESHOLD_INDEX_9,
+        THRESHOLD_INDEX_10,
+        THRESHOLD_INDEX_11,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {180},
+        {170},
+        {195},
+        {180},
+        {168},
+        {192},
+        {180},
+        {170},
+        {195},
+        {180},
+        {180},
+        {180},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {306, 338, 360, 376, UINT_MAX},
+        {295, 336, 358, 375, UINT_MAX},
+        {325, 325, 358, 375, UINT_MAX},
+        {325, 325, 358, 375, UINT_MAX},
+        {292, 324, 348, 364, UINT_MAX},
+        {324, 324, 348, 364, UINT_MAX},
+        {324, 324, 348, 364, UINT_MAX},
+        {295, 336, 358, 375, UINT_MAX},
+        {358, 358, 358, 358, 397, UINT_MAX},
+        {364, 364, 364, 364, 397, UINT_MAX},
+        {295, 336, 358, 375, 391, UINT_MAX},
+        {295, 336, 358, 375, 391, UINT_MAX},
+};
+
+static int threshold_index;
+static int package_id;
+
+static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
+{
+        u32 reg;
+        int ate_ver;
+        int bit_minus1;
+        int bit_minus2;
+
+        reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
+
+        *speedo_lp = (reg & 0xFFFF) * 4;
+        *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
+
+        ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
+        pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
+
+        if (ate_ver >= 26) {
+                bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
+                bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
+                bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
+                bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
+                *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
+
+                bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
+                bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
+                bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
+                bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
+                *speedo_g |= (bit_minus1 << 1) | bit_minus2;
+        } else {
+                *speedo_lp |= 0x3;
+                *speedo_g |= 0x3;
+        }
+}
+
+static void rev_sku_to_speedo_ids(int rev, int sku)
+{
+        switch (rev) {
+        case TEGRA_REVISION_A01:
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                threshold_index = THRESHOLD_INDEX_0;
+                break;
+        case TEGRA_REVISION_A02:
+        case TEGRA_REVISION_A03:
+                switch (sku) {
+                case 0x87:
+                case 0x82:
+                        tegra_cpu_speedo_id = 1;
+                        tegra_soc_speedo_id = 1;
+                        threshold_index = THRESHOLD_INDEX_1;
+                        break;
+                case 0x81:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 2;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_2;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 4;
+                                tegra_soc_speedo_id = 1;
+                                threshold_index = THRESHOLD_INDEX_7;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                case 0x80:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 5;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_8;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 6;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_9;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                case 0x83:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 7;
+                                tegra_soc_speedo_id = 1;
+                                threshold_index = THRESHOLD_INDEX_10;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 3;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_3;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                case 0x8F:
+                        tegra_cpu_speedo_id = 8;
+                        tegra_soc_speedo_id = 1;
+                        threshold_index = THRESHOLD_INDEX_11;
+                        break;
+                case 0x08:
+                        tegra_cpu_speedo_id = 1;
+                        tegra_soc_speedo_id = 1;
+                        threshold_index = THRESHOLD_INDEX_4;
+                        break;
+                case 0x02:
+                        tegra_cpu_speedo_id = 2;
+                        tegra_soc_speedo_id = 2;
+                        threshold_index = THRESHOLD_INDEX_5;
+                        break;
+                case 0x04:
+                        tegra_cpu_speedo_id = 3;
+                        tegra_soc_speedo_id = 2;
+                        threshold_index = THRESHOLD_INDEX_6;
+                        break;
+                case 0:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 2;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_2;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 3;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_3;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                default:
+                        pr_warn("Tegra30: Unknown SKU %d\n", sku);
+                        tegra_cpu_speedo_id = 0;
+                        tegra_soc_speedo_id = 0;
+                        threshold_index = THRESHOLD_INDEX_0;
+                        break;
+                }
+                break;
+        default:
+                pr_warn("Tegra30: Unknown chip rev %d\n", rev);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                threshold_index = THRESHOLD_INDEX_0;
+                break;
+        }
+}
+
+void tegra30_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
+
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
+        fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
+        pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
+        pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
+
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
+                if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
+                        break;
+        }
+        tegra_cpu_process_id = i - 1;
+
+        if (tegra_cpu_process_id == -1) {
+                pr_warn("Tegra30: CPU speedo value %3d out of range",
+                       cpu_speedo_val);
+                tegra_cpu_process_id = 0;
+                tegra_cpu_speedo_id = 1;
+        }
+
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
+                if (core_speedo_val < core_process_speedos[threshold_index][i])
+                        break;
+        }
+        tegra_core_process_id = i - 1;
+
+        if (tegra_core_process_id == -1) {
+                pr_warn("Tegra30: CORE speedo value %3d out of range",
+                       core_speedo_val);
+                tegra_core_process_id = 0;
+                tegra_soc_speedo_id = 1;
+        }
+
+        pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
+                tegra_cpu_speedo_id, tegra_soc_speedo_id);
+}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
index 30d063ad2bef..9764d31032b7 100644
--- a/arch/arm/mach-tegra/tegra_cpu_car.h
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -30,6 +30,12 @@
  *      CPU clock un-gate
  * disable_clock:
  *      CPU clock gate
+ * rail_off_ready:
+ *      CPU is ready for rail off
+ * suspend:
+ *      save the clock settings when CPU go into low-power state
+ * resume:
+ *      restore the clock settings when CPU exit low-power state
  */
 struct tegra_cpu_car_ops {
         void (*wait_for_reset)(u32 cpu);
@@ -37,6 +43,11 @@ struct tegra_cpu_car_ops {
         void (*out_of_reset)(u32 cpu);
         void (*enable_clock)(u32 cpu);
         void (*disable_clock)(u32 cpu);
+#ifdef CONFIG_PM_SLEEP
+        bool (*rail_off_ready)(void);
+        void (*suspend)(void);
+        void (*resume)(void);
+#endif
 };
 
 extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
@@ -81,6 +92,32 @@ static inline void tegra_disable_cpu_clock(u32 cpu)
         tegra_cpu_car_ops->disable_clock(cpu);
 }
 
+#ifdef CONFIG_PM_SLEEP
+static inline bool tegra_cpu_rail_off_ready(void)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
+                return false;
+
+        return tegra_cpu_car_ops->rail_off_ready();
+}
+
+static inline void tegra_cpu_clock_suspend(void)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->suspend))
+                return;
+
+        tegra_cpu_car_ops->suspend();
+}
+
+static inline void tegra_cpu_clock_resume(void)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->resume))
+                return;
+
+        tegra_cpu_car_ops->resume();
+}
+#endif
+
 void tegra20_cpu_car_ops_init(void);
 void tegra30_cpu_car_ops_init(void);
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 2d16b1dd5fec..e6ad161449da 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,6 +1,5 @@
-
 /*
- * Copyright (C) 2008-2009 ST-Ericsson
+ * Copyright (C) 2008-2012 ST-Ericsson
  *
  * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
  *
@@ -765,6 +764,16 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
         .init_late      = ux500_init_late,
 MACHINE_END
 
+MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
+        .atag_offset    = 0x100,
+        .map_io         = u8500_map_io,
+        .init_irq       = ux500_init_irq,
+        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = mop500_init_machine,
+        .init_late      = ux500_init_late,
+MACHINE_END
+
 MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
         .atag_offset    = 0x100,
         .smp            = smp_ops(ux500_smp_ops),
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 91f028c1264a..5c5ad70e48be 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -19,6 +19,7 @@
 #include <linux/mfd/abx500/ab8500.h>
 #include <linux/platform_data/usb-musb-ux500.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/random.h>
 
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
@@ -187,6 +188,8 @@ static const char *db8500_read_soc_id(void)
 {
         void __iomem *uid = __io_address(U8500_BB_UID_BASE);
 
+        /* Throw these device-specific numbers into the entropy pool */
+        add_device_randomness(uid, 0x14);
         return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
                          readl((u32 *)uid+1),
                          readl((u32 *)uid+1), readl((u32 *)uid+2),
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 5b5c1eeb5b5c..5d5929450366 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -32,6 +32,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/gfp.h>
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
@@ -51,7 +52,6 @@
 #include <asm/hardware/timer-sp.h>
 
 #include <plat/clcd.h>
-#include <plat/fpga-irq.h>
 #include <plat/sched_clock.h>
 
 #include "core.h"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index c95296066203..99e63f5f99d1 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,11 +1,12 @@
 config ARCH_VEXPRESS
         bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
         select ARM_GIC
         select ARM_TIMER_SP804
         select CLKDEV_LOOKUP
         select COMMON_CLK
+        select COMMON_CLK_VERSATILE
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
@@ -17,6 +18,7 @@ config ARCH_VEXPRESS
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLCD
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select VEXPRESS_CONFIG
         help
           This option enables support for systems using Cortex processor based
           ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8b4d3b..80b64971fbdd 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,7 +4,7 @@
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
         -I$(srctree)/arch/arm/plat-versatile/include
 
-obj-y                                   := v2m.o
+obj-y                                   := v2m.o reset.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 4f471fa3e3c5..60838ddb8564 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -9,6 +9,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/clkdev.h>
+#include <linux/vexpress.h>
 
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -64,19 +65,6 @@ static void __init ct_ca9x4_init_irq(void)
         ca9x4_twd_init();
 }
 
-static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
-{
-        u32 site = v2m_get_master_site();
-
-        /*
-         * Old firmware was using the "site" component of the command
-         * to control the DVI muxer (while it should be always 0 ie. MB).
-         * Newer firmware uses the data register. Keep both for compatibility.
-         */
-        v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
-        v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
-}
-
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 {
         unsigned long framesize = 1024 * 768 * 2;
@@ -93,7 +81,6 @@ static struct clcd_board ct_ca9x4_clcd_data = {
         .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
         .check          = clcdfb_check,
         .decode         = clcdfb_decode,
-        .enable         = ct_ca9x4_clcd_enable,
         .setup          = ct_ca9x4_clcd_setup,
         .mmap           = versatile_clcd_mmap_dma,
         .remove         = versatile_clcd_remove_dma,
@@ -111,14 +98,6 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
         &gpio_device,
 };
 
-
-static struct v2m_osc ct_osc1 = {
-        .osc = 1,
-        .rate_min = 10000000,
-        .rate_max = 80000000,
-        .rate_default = 23750000,
-};
-
 static struct resource pmu_resources[] = {
         [0] = {
                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
@@ -149,10 +128,18 @@ static struct platform_device pmu_device = {
         .resource       = pmu_resources,
 };
 
+static struct platform_device osc1_device = {
+        .name           = "vexpress-osc",
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0xf, 1),
+        },
+};
+
 static void __init ct_ca9x4_init(void)
 {
         int i;
-        struct clk *clk;
 
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -164,14 +151,14 @@ static void __init ct_ca9x4_init(void)
         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
-        ct_osc1.site = v2m_get_master_site();
-        clk = v2m_osc_register("ct:osc1", &ct_osc1);
-        clk_register_clkdev(clk, NULL, "ct:clcd");
-
         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 
         platform_device_register(&pmu_device);
+        platform_device_register(&osc1_device);
+
+        WARN_ON(clk_register_clkdev(vexpress_osc_setup(&osc1_device.dev),
+                        NULL, "ct:clcd"));
 }
 
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 1e388c7bf4d7..68abc8b72781 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,8 +1,6 @@
 #ifndef __MACH_MOTHERBOARD_H
 #define __MACH_MOTHERBOARD_H
 
-#include <linux/clk-provider.h>
-
 /*
  * Physical addresses, offset from V2M_PA_CS0-3
  */
@@ -41,31 +39,6 @@
 #define V2M_CF                  (V2M_PA_CS7 + 0x0001a000)
 #define V2M_CLCD                (V2M_PA_CS7 + 0x0001f000)
 
-/*
- * Offsets from SYSREGS base
- */
-#define V2M_SYS_ID              0x000
-#define V2M_SYS_SW              0x004
-#define V2M_SYS_LED             0x008
-#define V2M_SYS_100HZ           0x024
-#define V2M_SYS_FLAGS           0x030
-#define V2M_SYS_FLAGSSET        0x030
-#define V2M_SYS_FLAGSCLR        0x034
-#define V2M_SYS_NVFLAGS         0x038
-#define V2M_SYS_NVFLAGSSET      0x038
-#define V2M_SYS_NVFLAGSCLR      0x03c
-#define V2M_SYS_MCI             0x048
-#define V2M_SYS_FLASH           0x03c
-#define V2M_SYS_CFGSW           0x058
-#define V2M_SYS_24MHZ           0x05c
-#define V2M_SYS_MISC            0x060
-#define V2M_SYS_DMA             0x064
-#define V2M_SYS_PROCID0         0x084
-#define V2M_SYS_PROCID1         0x088
-#define V2M_SYS_CFGDATA         0x0a0
-#define V2M_SYS_CFGCTRL         0x0a4
-#define V2M_SYS_CFGSTAT         0x0a8
-
 
 /*
  * Interrupts.  Those in {} are for AMBA devices
@@ -91,43 +64,6 @@
 
 
 /*
- * Configuration
- */
-#define SYS_CFG_START           (1 << 31)
-#define SYS_CFG_WRITE           (1 << 30)
-#define SYS_CFG_OSC             (1 << 20)
-#define SYS_CFG_VOLT            (2 << 20)
-#define SYS_CFG_AMP             (3 << 20)
-#define SYS_CFG_TEMP            (4 << 20)
-#define SYS_CFG_RESET           (5 << 20)
-#define SYS_CFG_SCC             (6 << 20)
-#define SYS_CFG_MUXFPGA         (7 << 20)
-#define SYS_CFG_SHUTDOWN        (8 << 20)
-#define SYS_CFG_REBOOT          (9 << 20)
-#define SYS_CFG_DVIMODE         (11 << 20)
-#define SYS_CFG_POWER           (12 << 20)
-#define SYS_CFG_SITE(n)         ((n) << 16)
-#define SYS_CFG_SITE_MB         0
-#define SYS_CFG_SITE_DB1        1
-#define SYS_CFG_SITE_DB2        2
-#define SYS_CFG_STACK(n)        ((n) << 12)
-
-#define SYS_CFG_ERR             (1 << 1)
-#define SYS_CFG_COMPLETE        (1 << 0)
-
-int v2m_cfg_write(u32 devfn, u32 data);
-int v2m_cfg_read(u32 devfn, u32 *data);
-void v2m_flags_set(u32 data);
-
-/*
- * Miscellaneous
- */
-#define SYS_MISC_MASTERSITE     (1 << 14)
-#define SYS_PROCIDx_HBI_MASK    0xfff
-
-int v2m_get_master_site(void);
-
-/*
  * Core tile IDs
  */
 #define V2M_CT_ID_CA9           0x0c000191
@@ -149,21 +85,4 @@ struct ct_desc {
 
 extern struct ct_desc *ct_desc;
 
-/*
- * OSC clock provider
- */
-struct v2m_osc {
-        struct clk_hw hw;
-        u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
-        u8 stack; /* board stack position */
-        u16 osc;
-        unsigned long rate_min;
-        unsigned long rate_max;
-        unsigned long rate_default;
-};
-
-#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
-
-struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
-
 #endif
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 7db27c8c05cc..c5d70de9bb4e 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -13,6 +13,7 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <linux/of_fdt.h>
+#include <linux/vexpress.h>
 
 #include <asm/smp_scu.h>
 #include <asm/hardware/gic.h>
@@ -193,7 +194,7 @@ static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        v2m_flags_set(virt_to_phys(versatile_secondary_startup));
+        vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
 }
 
 struct smp_operations __initdata vexpress_smp_ops = {
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 359f782c747d..011661a6c5cb 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,11 +16,10 @@
 #include <linux/smsc911x.h>
 #include <linux/spinlock.h>
 #include <linux/usb/isp1760.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/vexpress.h>
 
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
@@ -33,7 +32,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/timer-sp.h>
-#include <asm/hardware/sp810.h>
 
 #include <mach/ct-ca9x4.h>
 #include <mach/motherboard.h>
@@ -58,22 +56,6 @@ static struct map_desc v2m_io_desc[] __initdata = {
         },
 };
 
-static void __iomem *v2m_sysreg_base;
-
-static void __init v2m_sysctl_init(void __iomem *base)
-{
-        u32 scctrl;
-
-        if (WARN_ON(!base))
-                return;
-
-        /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
-        scctrl = readl(base + SCCTRL);
-        scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
-        scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
-        writel(scctrl, base + SCCTRL);
-}
-
 static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
 {
         if (WARN_ON(!base || irq == NO_IRQ))
@@ -87,69 +69,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
 }
 
 
-static DEFINE_SPINLOCK(v2m_cfg_lock);
-
-int v2m_cfg_write(u32 devfn, u32 data)
-{
-        /* Configuration interface broken? */
-        u32 val;
-
-        printk("%s: writing %08x to %08x\n", __func__, data, devfn);
-
-        devfn |= SYS_CFG_START | SYS_CFG_WRITE;
-
-        spin_lock(&v2m_cfg_lock);
-        val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
-
-        writel(data, v2m_sysreg_base +  V2M_SYS_CFGDATA);
-        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
-
-        do {
-                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        } while (val == 0);
-        spin_unlock(&v2m_cfg_lock);
-
-        return !!(val & SYS_CFG_ERR);
-}
-
-int v2m_cfg_read(u32 devfn, u32 *data)
-{
-        u32 val;
-
-        devfn |= SYS_CFG_START;
-
-        spin_lock(&v2m_cfg_lock);
-        writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
-
-        mb();
-
-        do {
-                cpu_relax();
-                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        } while (val == 0);
-
-        *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
-        spin_unlock(&v2m_cfg_lock);
-
-        return !!(val & SYS_CFG_ERR);
-}
-
-void __init v2m_flags_set(u32 data)
-{
-        writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
-        writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
-}
-
-int v2m_get_master_site(void)
-{
-        u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
-
-        return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
-}
-
-
 static struct resource v2m_pcie_i2c_resource = {
         .start  = V2M_SERIAL_BUS_PCI,
         .end    = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
@@ -237,14 +156,8 @@ static struct platform_device v2m_usb_device = {
         .dev.platform_data = &v2m_usb_config,
 };
 
-static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
-{
-        writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
-}
-
 static struct physmap_flash_data v2m_flash_data = {
         .width          = 4,
-        .set_vpp        = v2m_flash_set_vpp,
 };
 
 static struct resource v2m_flash_resources[] = {
@@ -291,14 +204,61 @@ static struct platform_device v2m_cf_device = {
         .dev.platform_data = &v2m_pata_data,
 };
 
-static unsigned int v2m_mmci_status(struct device *dev)
-{
-        return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
-}
-
 static struct mmci_platform_data v2m_mmci_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .status         = v2m_mmci_status,
+        .gpio_wp        = VEXPRESS_GPIO_MMC_WPROT,
+        .gpio_cd        = VEXPRESS_GPIO_MMC_CARDIN,
+};
+
+static struct resource v2m_sysreg_resources[] = {
+        {
+                .start  = V2M_SYSREGS,
+                .end    = V2M_SYSREGS + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device v2m_sysreg_device = {
+        .name           = "vexpress-sysreg",
+        .id             = -1,
+        .resource       = v2m_sysreg_resources,
+        .num_resources  = ARRAY_SIZE(v2m_sysreg_resources),
+};
+
+static struct platform_device v2m_muxfpga_device = {
+        .name           = "vexpress-muxfpga",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 7),
+        }
+};
+
+static struct platform_device v2m_shutdown_device = {
+        .name           = "vexpress-shutdown",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 8),
+        }
+};
+
+static struct platform_device v2m_reboot_device = {
+        .name           = "vexpress-reboot",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 9),
+        }
+};
+
+static struct platform_device v2m_dvimode_device = {
+        .name           = "vexpress-dvimode",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 11),
+        }
 };
 
 static AMBA_APB_DEVICE(aaci,  "mb:aaci",  0, V2M_AACI, IRQ_V2M_AACI, NULL);
@@ -325,123 +285,9 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
         &rtc_device,
 };
 
-
-static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct v2m_osc *osc = to_v2m_osc(hw);
-
-        return !parent_rate ? osc->rate_default : parent_rate;
-}
-
-static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *parent_rate)
-{
-        struct v2m_osc *osc = to_v2m_osc(hw);
-
-        if (WARN_ON(rate < osc->rate_min))
-                rate = osc->rate_min;
-
-        if (WARN_ON(rate > osc->rate_max))
-                rate = osc->rate_max;
-
-        return rate;
-}
-
-static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct v2m_osc *osc = to_v2m_osc(hw);
-
-        v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
-                        SYS_CFG_STACK(osc->stack) | osc->osc, rate);
-
-        return 0;
-}
-
-static struct clk_ops v2m_osc_ops = {
-        .recalc_rate = v2m_osc_recalc_rate,
-        .round_rate = v2m_osc_round_rate,
-        .set_rate = v2m_osc_set_rate,
-};
-
-struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
-{
-        struct clk_init_data init;
-
-        WARN_ON(osc->site > 2);
-        WARN_ON(osc->stack > 15);
-        WARN_ON(osc->osc > 4095);
-
-        init.name = name;
-        init.ops = &v2m_osc_ops;
-        init.flags = CLK_IS_ROOT;
-        init.num_parents = 0;
-
-        osc->hw.init = &init;
-
-        return clk_register(NULL, &osc->hw);
-}
-
-static struct v2m_osc v2m_mb_osc1 = {
-        .site = SYS_CFG_SITE_MB,
-        .osc = 1,
-        .rate_min = 23750000,
-        .rate_max = 63500000,
-        .rate_default = 23750000,
-};
-
-static const char *v2m_ref_clk_periphs[] __initconst = {
-        "mb:wdt",   "1000f000.wdt",  "1c0f0000.wdt",    /* SP805 WDT */
-};
-
-static const char *v2m_osc1_periphs[] __initconst = {
-        "mb:clcd",  "1001f000.clcd", "1c1f0000.clcd",   /* PL111 CLCD */
-};
-
-static const char *v2m_osc2_periphs[] __initconst = {
-        "mb:mmci",  "10005000.mmci", "1c050000.mmci",   /* PL180 MMCI */
-        "mb:kmi0",  "10006000.kmi",  "1c060000.kmi",    /* PL050 KMI0 */
-        "mb:kmi1",  "10007000.kmi",  "1c070000.kmi",    /* PL050 KMI1 */
-        "mb:uart0", "10009000.uart", "1c090000.uart",   /* PL011 UART0 */
-        "mb:uart1", "1000a000.uart", "1c0a0000.uart",   /* PL011 UART1 */
-        "mb:uart2", "1000b000.uart", "1c0b0000.uart",   /* PL011 UART2 */
-        "mb:uart3", "1000c000.uart", "1c0c0000.uart",   /* PL011 UART3 */
-};
-
-static void __init v2m_clk_init(void)
-{
-        struct clk *clk;
-        int i;
-
-        clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
-                        CLK_IS_ROOT, 0);
-        WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
-
-        clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
-                        CLK_IS_ROOT, 32768);
-        for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
-                WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
-
-        clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
-                        CLK_IS_ROOT, 1000000);
-        WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
-        WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
-
-        clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
-        for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
-                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
-
-        clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
-                        CLK_IS_ROOT, 24000000);
-        for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
-                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
-}
-
 static void __init v2m_timer_init(void)
 {
-        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
-        v2m_clk_init();
+        vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K));
         v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
 }
 
@@ -453,19 +299,7 @@ static void __init v2m_init_early(void)
 {
         if (ct_desc->init_early)
                 ct_desc->init_early();
-        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
-}
-
-static void v2m_power_off(void)
-{
-        if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
-                printk(KERN_EMERG "Unable to shutdown\n");
-}
-
-static void v2m_restart(char str, const char *cmd)
-{
-        if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
-                printk(KERN_EMERG "Unable to reboot\n");
+        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000);
 }
 
 struct ct_desc *ct_desc;
@@ -482,7 +316,7 @@ static void __init v2m_populate_ct_desc(void)
         u32 current_tile_id;
 
         ct_desc = NULL;
-        current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+        current_tile_id = vexpress_get_procid(VEXPRESS_SITE_MASTER)
                                 & V2M_CT_ID_MASK;
 
         for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
@@ -498,7 +332,7 @@ static void __init v2m_populate_ct_desc(void)
 static void __init v2m_map_io(void)
 {
         iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
-        v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
+        vexpress_sysreg_early_init(ioremap(V2M_SYSREGS, SZ_4K));
         v2m_populate_ct_desc();
         ct_desc->map_io();
 }
@@ -515,6 +349,12 @@ static void __init v2m_init(void)
         regulator_register_fixed(0, v2m_eth_supplies,
                         ARRAY_SIZE(v2m_eth_supplies));
 
+        platform_device_register(&v2m_muxfpga_device);
+        platform_device_register(&v2m_shutdown_device);
+        platform_device_register(&v2m_reboot_device);
+        platform_device_register(&v2m_dvimode_device);
+
+        platform_device_register(&v2m_sysreg_device);
         platform_device_register(&v2m_pcie_i2c_device);
         platform_device_register(&v2m_ddc_i2c_device);
         platform_device_register(&v2m_flash_device);
@@ -525,7 +365,7 @@ static void __init v2m_init(void)
         for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
                 amba_device_register(v2m_amba_devs[i], &iomem_resource);
 
-        pm_power_off = v2m_power_off;
+        pm_power_off = vexpress_power_off;
 
         ct_desc->init_tile();
 }
@@ -539,7 +379,7 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .timer          = &v2m_timer,
         .handle_irq     = gic_handle_irq,
         .init_machine   = v2m_init,
-        .restart        = v2m_restart,
+        .restart        = vexpress_restart,
 MACHINE_END
 
 static struct map_desc v2m_rs1_io_desc __initdata = {
@@ -580,20 +420,13 @@ void __init v2m_dt_map_io(void)
 
 void __init v2m_dt_init_early(void)
 {
-        struct device_node *node;
         u32 dt_hbi;
 
-        node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
-        v2m_sysreg_base = of_iomap(node, 0);
-        if (WARN_ON(!v2m_sysreg_base))
-                return;
+        vexpress_sysreg_of_early_init();
 
         /* Confirm board type against DT property, if available */
         if (of_property_read_u32(of_allnodes, "arm,hbi", &dt_hbi) == 0) {
-                int site = v2m_get_master_site();
-                u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
-                                V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
-                u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+                u32 hbi = vexpress_get_hbi(VEXPRESS_SITE_MASTER);
 
                 if (WARN_ON(dt_hbi != hbi))
                         pr_warning("vexpress: DT HBI (%x) is not matching "
@@ -613,51 +446,47 @@ static void __init v2m_dt_init_irq(void)
 
 static void __init v2m_dt_timer_init(void)
 {
-        struct device_node *node;
-        const char *path;
-        int err;
+        struct device_node *node = NULL;
 
-        node = of_find_compatible_node(NULL, NULL, "arm,sp810");
-        v2m_sysctl_init(of_iomap(node, 0));
+        vexpress_clk_of_init();
 
-        v2m_clk_init();
+        do {
+                node = of_find_compatible_node(node, NULL, "arm,sp804");
+        } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
+        if (node) {
+                pr_info("Using SP804 '%s' as a clock & events source\n",
+                                node->full_name);
+                v2m_sp804_init(of_iomap(node, 0),
+                                irq_of_parse_and_map(node, 0));
+        }
 
-        err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
         if (arch_timer_of_register() != 0)
                 twd_local_timer_of_register();
 
         if (arch_timer_sched_clock_init() != 0)
-                versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+                versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
+                                24000000);
 }
 
 static struct sys_timer v2m_dt_timer = {
         .init = v2m_dt_timer_init,
 };
 
-static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
-                        &v2m_flash_data),
-        OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
-        /* RS1 memory map */
-        OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
-                        &v2m_flash_data),
-        OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
+static const struct of_device_id v2m_dt_bus_match[] __initconst = {
+        { .compatible = "simple-bus", },
+        { .compatible = "arm,amba-bus", },
+        { .compatible = "arm,vexpress,config-bus", },
         {}
 };
 
 static void __init v2m_dt_init(void)
 {
         l2x0_of_init(0x00400000, 0xfe0fffff);
-        of_platform_populate(NULL, of_default_bus_match_table,
-                        v2m_dt_auxdata_lookup, NULL);
-        pm_power_off = v2m_power_off;
+        of_platform_populate(NULL, v2m_dt_bus_match, NULL, NULL);
+        pm_power_off = vexpress_power_off;
 }
 
-const static char *v2m_dt_match[] __initconst = {
+static const char * const v2m_dt_match[] __initconst = {
         "arm,vexpress",
         "xen,xenvm",
         NULL,
@@ -672,5 +501,5 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .timer          = &v2m_dt_timer,
         .init_machine   = v2m_dt_init,
         .handle_irq     = gic_handle_irq,
-        .restart        = v2m_restart,
+        .restart        = vexpress_restart,
 MACHINE_END
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 99b47b950efc..9f0610243bd6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -876,6 +876,22 @@ static void __init pci_reserve_io(void)
 #define pci_reserve_io() do { } while (0)
 #endif
 
+#ifdef CONFIG_DEBUG_LL
+void __init debug_ll_io_init(void)
+{
+        struct map_desc map;
+
+        debug_ll_addr(&map.pfn, &map.virtual);
+        if (!map.pfn || !map.virtual)
+                return;
+        map.pfn = __phys_to_pfn(map.pfn);
+        map.virtual &= PAGE_MASK;
+        map.length = PAGE_SIZE;
+        map.type = MT_DEVICE;
+        create_mapping(&map);
+}
+#endif
+
 static void * __initdata vmalloc_min =
         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-emma.c b/arch/arm/plat-mxc/devices/platform-mx2-emma.c
new file mode 100644
index 000000000000..508404ddd4ea
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx2-emma.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mx2_emmaprp_data_entry_single(soc)                          \
+        {                                                               \
+                .iobase = soc ## _EMMAPRP_BASE_ADDR,                    \
+                .iosize = SZ_32,                                        \
+                .irq = soc ## _INT_EMMAPRP,                             \
+        }
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mx2_emma_data imx27_mx2_emmaprp_data __initconst =
+        imx_mx2_emmaprp_data_entry_single(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+struct platform_device *__init imx_add_mx2_emmaprp(
+                const struct imx_mx2_emma_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
+                        res, 2, NULL, 0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 59401e1cc530..a9d52167e16e 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -414,6 +414,11 @@ config S5P_SETUP_MIPIPHY
         help
           Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
 
+config S3C_SETUP_CAMIF
+        bool
+        help
+          Compile in common setup code for S3C CAMIF devices
+
 # DMA
 
 config S3C_DMA
@@ -502,5 +507,6 @@ config DEBUG_S3C_UART
         default "0" if DEBUG_S3C_UART0
         default "1" if DEBUG_S3C_UART1
         default "2" if DEBUG_S3C_UART2
+        default "3" if DEBUG_S3C_UART3
 
 endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 9e40e8d00740..3a7c64d1814a 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_S5P_DEV_UART)	+= s5p-dev-uart.o
 
 obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT)     += dev-backlight.o
 
+obj-$(CONFIG_S3C_SETUP_CAMIF)   += setup-camif.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
 
 # DMA support
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index ace4451b7651..e0072ce8d6e9 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK        0xFFFE0000
 
 #define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5440_SOC_ID       0x54400000
 #define EXYNOS5_SOC_MASK        0xFFFFF000
 
 #define IS_SAMSUNG_CPU(name, id, mask)          \
@@ -62,6 +63,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -130,6 +132,12 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()    0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5440)
+# define soc_is_exynos5440()    is_samsung_exynos5440()
+#else
+# define soc_is_exynos5440()    0
+#endif
+
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef KHZ
diff --git a/arch/arm/plat-samsung/setup-camif.c b/arch/arm/plat-samsung/setup-camif.c
new file mode 100644
index 000000000000..e01bf760af2c
--- /dev/null
+++ b/arch/arm/plat-samsung/setup-camif.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
+ *
+ * Helper functions for S3C24XX/S3C64XX SoC series CAMIF driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+/* Number of camera port pins, without FIELD */
+#define S3C_CAMIF_NUM_GPIOS     13
+
+/* Default camera port configuration helpers. */
+
+static void camif_get_gpios(int *gpio_start, int *gpio_reset)
+{
+#ifdef CONFIG_ARCH_S3C24XX
+        *gpio_start = S3C2410_GPJ(0);
+        *gpio_reset = S3C2410_GPJ(12);
+#else
+        /* s3c64xx */
+        *gpio_start = S3C64XX_GPF(0);
+        *gpio_reset = S3C64XX_GPF(3);
+#endif
+}
+
+int s3c_camif_gpio_get(void)
+{
+        int gpio_start, gpio_reset;
+        int ret, i;
+
+        camif_get_gpios(&gpio_start, &gpio_reset);
+
+        for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) {
+                int gpio = gpio_start + i;
+
+                if (gpio == gpio_reset)
+                        continue;
+
+                ret = gpio_request(gpio, "camif");
+                if (!ret)
+                        ret = s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                if (ret) {
+                        pr_err("failed to configure GPIO %d\n", gpio);
+                        for (--i; i >= 0; i--)
+                                gpio_free(gpio--);
+                        return ret;
+                }
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        return 0;
+}
+
+void s3c_camif_gpio_put(void)
+{
+        int i, gpio_start, gpio_reset;
+
+        camif_get_gpios(&gpio_start, &gpio_reset);
+
+        for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) {
+                int gpio = gpio_start + i;
+                if (gpio != gpio_reset)
+                        gpio_free(gpio);
+        }
+}
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index eb50231c4efd..2c4332b9f948 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -6,15 +6,6 @@ config PLAT_VERSATILE_CLOCK
 config PLAT_VERSATILE_CLCD
         bool
 
-config PLAT_VERSATILE_FPGA_IRQ
-        bool
-        select IRQ_DOMAIN
-
-config PLAT_VERSATILE_FPGA_IRQ_NR
-       int
-       default 4
-       depends on PLAT_VERSATILE_FPGA_IRQ
-
 config PLAT_VERSATILE_LEDS
         def_bool y if NEW_LEDS
         depends on ARCH_REALVIEW || ARCH_VERSATILE
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 74cfd94cbf80..f88d448b629c 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,7 +2,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
-obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
 obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2701235d5757..a96bda3d3b84 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ endif
 obj-$(CONFIG_MACH_LOONGSON1)    += clk-ls1x.o
 obj-$(CONFIG_ARCH_U8500)        += ux500/
 obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
+obj-$(CONFIG_ARCH_SUNXI)        += clk-sunxi.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-sunxi.c b/drivers/clk/clk-sunxi.c
new file mode 100644
index 000000000000..0e831b584ba7
--- /dev/null
+++ b/drivers/clk/clk-sunxi.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/sunxi.h>
+#include <linux/of.h>
+
+static const __initconst struct of_device_id clk_match[] = {
+        { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+        {}
+};
+
+void __init sunxi_init_clocks(void)
+{
+        of_clk_init(clk_match);
+}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6a78073c3808..a0985732f1e2 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,6 +22,9 @@ config DW_APB_TIMER_OF
 config ARMADA_370_XP_TIMER
         bool
 
+config SUNXI_TIMER
+        bool
+
 config CLKSRC_DBX500_PRCMU
         bool "Clocksource PRCMU Timer"
         depends on UX500_SOC_DB8500
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 603be366f762..36f06de4c5ab 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_DW_APB_TIMER_OF)	+= dw_apb_timer_of.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
 obj-$(CONFIG_ARCH_BCM2835)      += bcm2835_timer.o
+obj-$(CONFIG_SUNXI_TIMER)       += sunxi_timer.o
 
 obj-$(CONFIG_CLKSRC_ARM_GENERIC)        += arm_generic.o
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
new file mode 100644
index 000000000000..3cd1bd3d7aee
--- /dev/null
+++ b/drivers/clocksource/sunxi_timer.c
@@ -0,0 +1,171 @@
+/*
+ * Allwinner A1X SoCs timer handling.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sunxi_timer.h>
+#include <linux/clk/sunxi.h>
+
+#define TIMER_CTL_REG           0x00
+#define TIMER_CTL_ENABLE                (1 << 0)
+#define TIMER_IRQ_ST_REG        0x04
+#define TIMER0_CTL_REG          0x10
+#define TIMER0_CTL_ENABLE               (1 << 0)
+#define TIMER0_CTL_AUTORELOAD           (1 << 1)
+#define TIMER0_CTL_ONESHOT              (1 << 7)
+#define TIMER0_INTVAL_REG       0x14
+#define TIMER0_CNTVAL_REG       0x18
+
+#define TIMER_SCAL              16
+
+static void __iomem *timer_base;
+
+static void sunxi_clkevt_mode(enum clock_event_mode mode,
+                              struct clock_event_device *clk)
+{
+        u32 u = readl(timer_base + TIMER0_CTL_REG);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                u &= ~(TIMER0_CTL_ONESHOT);
+                writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
+                break;
+        }
+}
+
+static int sunxi_clkevt_next_event(unsigned long evt,
+                                   struct clock_event_device *unused)
+{
+        u32 u = readl(timer_base + TIMER0_CTL_REG);
+        writel(evt, timer_base + TIMER0_CNTVAL_REG);
+        writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
+               timer_base + TIMER0_CTL_REG);
+
+        return 0;
+}
+
+static struct clock_event_device sunxi_clockevent = {
+        .name = "sunxi_tick",
+        .shift = 32,
+        .rating = 300,
+        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = sunxi_clkevt_mode,
+        .set_next_event = sunxi_clkevt_next_event,
+};
+
+
+static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+        writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction sunxi_timer_irq = {
+        .name = "sunxi_timer0",
+        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler = sunxi_timer_interrupt,
+        .dev_id = &sunxi_clockevent,
+};
+
+static struct of_device_id sunxi_timer_dt_ids[] = {
+        { .compatible = "allwinner,sunxi-timer" },
+        { }
+};
+
+static void __init sunxi_timer_init(void)
+{
+        struct device_node *node;
+        unsigned long rate = 0;
+        struct clk *clk;
+        int ret, irq;
+        u32 val;
+
+        node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
+        if (!node)
+                panic("No sunxi timer node");
+
+        timer_base = of_iomap(node, 0);
+        if (!timer_base)
+                panic("Can't map registers");
+
+        irq = irq_of_parse_and_map(node, 0);
+        if (irq <= 0)
+                panic("Can't parse IRQ");
+
+        sunxi_init_clocks();
+
+        clk = of_clk_get(node, 0);
+        if (IS_ERR(clk))
+                panic("Can't get timer clock");
+
+        rate = clk_get_rate(clk);
+
+        writel(rate / (TIMER_SCAL * HZ),
+               timer_base + TIMER0_INTVAL_REG);
+
+        /* set clock source to HOSC, 16 pre-division */
+        val = readl(timer_base + TIMER0_CTL_REG);
+        val &= ~(0x07 << 4);
+        val &= ~(0x03 << 2);
+        val |= (4 << 4) | (1 << 2);
+        writel(val, timer_base + TIMER0_CTL_REG);
+
+        /* set mode to auto reload */
+        val = readl(timer_base + TIMER0_CTL_REG);
+        writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
+
+        ret = setup_irq(irq, &sunxi_timer_irq);
+        if (ret)
+                pr_warn("failed to setup irq %d\n", irq);
+
+        /* Enable timer0 interrupt */
+        val = readl(timer_base + TIMER_CTL_REG);
+        writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+
+        sunxi_clockevent.mult = div_sc(rate / TIMER_SCAL,
+                                NSEC_PER_SEC,
+                                sunxi_clockevent.shift);
+        sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
+                                                            &sunxi_clockevent);
+        sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
+                                                            &sunxi_clockevent);
+        sunxi_clockevent.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&sunxi_clockevent);
+}
+
+struct sys_timer sunxi_timer = {
+        .init = sunxi_timer_init,
+};
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 234ae651b38f..c4cc27e5c8a5 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -30,3 +30,13 @@ config CPU_IDLE_GOV_MENU
 
 config ARCH_NEEDS_CPU_IDLE_COUPLED
         def_bool n
+
+if CPU_IDLE
+
+config CPU_IDLE_CALXEDA
+        bool "CPU Idle Driver for Calxeda processors"
+        depends on ARCH_HIGHBANK
+        help
+          Select this to enable cpuidle on Calxeda processors.
+
+endif
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 38c8f69f30cf..03ee87482c71 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -4,3 +4,5 @@
 
 obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
 obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
+
+obj-$(CONFIG_CPU_IDLE_CALXEDA) += cpuidle-calxeda.o
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
new file mode 100644
index 000000000000..e1aab38c5a8d
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2012 Calxeda, Inc.
+ *
+ * Based on arch/arm/plat-mxc/cpuidle.c:
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+
+extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
+extern void *scu_base_addr;
+
+static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;
+
+static inline unsigned int get_auxcr(void)
+{
+        unsigned int val;
+        asm("mrc p15, 0, %0, c1, c0, 1  @ get AUXCR" : "=r" (val) : : "cc");
+        return val;
+}
+
+static inline void set_auxcr(unsigned int val)
+{
+        asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+          : : "r" (val) : "cc");
+        isb();
+}
+
+static noinline void calxeda_idle_restore(void)
+{
+        set_cr(get_cr() | CR_C);
+        set_auxcr(get_auxcr() | 0x40);
+        scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
+}
+
+static int calxeda_idle_finish(unsigned long val)
+{
+        /* Already flushed cache, but do it again as the outer cache functions
+         * dirty the cache with spinlocks */
+        flush_cache_all();
+
+        set_auxcr(get_auxcr() & ~0x40);
+        set_cr(get_cr() & ~CR_C);
+
+        scu_power_mode(scu_base_addr, SCU_PM_DORMANT);
+
+        cpu_do_idle();
+
+        /* Restore things if we didn't enter power-gating */
+        calxeda_idle_restore();
+        return 1;
+}
+
+static int calxeda_pwrdown_idle(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index)
+{
+        highbank_set_cpu_jump(smp_processor_id(), cpu_resume);
+        cpu_suspend(0, calxeda_idle_finish);
+        return index;
+}
+
+static void calxeda_idle_cpuidle_devices_uninit(void)
+{
+        int i;
+        struct cpuidle_device *dev;
+
+        for_each_possible_cpu(i) {
+                dev = per_cpu_ptr(calxeda_idle_cpuidle_devices, i);
+                cpuidle_unregister_device(dev);
+        }
+
+        free_percpu(calxeda_idle_cpuidle_devices);
+}
+
+static struct cpuidle_driver calxeda_idle_driver = {
+        .name = "calxeda_idle",
+        .en_core_tk_irqen = 1,
+        .states = {
+                ARM_CPUIDLE_WFI_STATE,
+                {
+                        .name = "PG",
+                        .desc = "Power Gate",
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .exit_latency = 30,
+                        .power_usage = 50,
+                        .target_residency = 200,
+                        .enter = calxeda_pwrdown_idle,
+                },
+        },
+        .state_count = 2,
+};
+
+static int __init calxeda_cpuidle_init(void)
+{
+        int cpu_id;
+        int ret;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &calxeda_idle_driver;
+
+        if (!of_machine_is_compatible("calxeda,highbank"))
+                return -ENODEV;
+
+        ret = cpuidle_register_driver(drv);
+        if (ret)
+                return ret;
+
+        calxeda_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
+        if (calxeda_idle_cpuidle_devices == NULL) {
+                ret = -ENOMEM;
+                goto unregister_drv;
+        }
+
+        /* initialize state data for each cpuidle_device */
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(calxeda_idle_cpuidle_devices, cpu_id);
+                dev->cpu = cpu_id;
+                dev->state_count = drv->state_count;
+
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("Failed to register cpu %u, error: %d\n",
+                               cpu_id, ret);
+                        goto uninit;
+                }
+        }
+
+        return 0;
+
+uninit:
+        calxeda_idle_cpuidle_devices_uninit();
+unregister_drv:
+        cpuidle_unregister_driver(drv);
+        return ret;
+}
+module_init(calxeda_cpuidle_init);
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 1bb8bf6d7fd4..62ca575701d3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -1 +1,8 @@
-# empty
+config VERSATILE_FPGA_IRQ
+        bool
+        select IRQ_DOMAIN
+
+config VERSATILE_FPGA_IRQ_NR
+       int
+       default 4
+       depends on VERSATILE_FPGA_IRQ
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 054321db4350..02bd37a6187f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1 +1,3 @@
 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
+obj-$(CONFIG_ARCH_SUNXI)   += irq-sunxi.o
+obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
new file mode 100644
index 000000000000..10974fa42653
--- /dev/null
+++ b/drivers/irqchip/irq-sunxi.c
@@ -0,0 +1,151 @@
+/*
+ * Allwinner A1X SoCs IRQ chip driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#define SUNXI_IRQ_VECTOR_REG            0x00
+#define SUNXI_IRQ_PROTECTION_REG        0x08
+#define SUNXI_IRQ_NMI_CTRL_REG          0x0c
+#define SUNXI_IRQ_PENDING_REG(x)        (0x10 + 0x4 * x)
+#define SUNXI_IRQ_FIQ_PENDING_REG(x)    (0x20 + 0x4 * x)
+#define SUNXI_IRQ_ENABLE_REG(x)         (0x40 + 0x4 * x)
+#define SUNXI_IRQ_MASK_REG(x)           (0x50 + 0x4 * x)
+
+static void __iomem *sunxi_irq_base;
+static struct irq_domain *sunxi_irq_domain;
+
+void sunxi_irq_ack(struct irq_data *irqd)
+{
+        unsigned int irq = irqd_to_hwirq(irqd);
+        unsigned int irq_off = irq % 32;
+        int reg = irq / 32;
+        u32 val;
+
+        val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+        writel(val | (1 << irq_off),
+               sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+}
+
+static void sunxi_irq_mask(struct irq_data *irqd)
+{
+        unsigned int irq = irqd_to_hwirq(irqd);
+        unsigned int irq_off = irq % 32;
+        int reg = irq / 32;
+        u32 val;
+
+        val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+        writel(val & ~(1 << irq_off),
+               sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+}
+
+static void sunxi_irq_unmask(struct irq_data *irqd)
+{
+        unsigned int irq = irqd_to_hwirq(irqd);
+        unsigned int irq_off = irq % 32;
+        int reg = irq / 32;
+        u32 val;
+
+        val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+        writel(val | (1 << irq_off),
+               sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+}
+
+static struct irq_chip sunxi_irq_chip = {
+        .name           = "sunxi_irq",
+        .irq_ack        = sunxi_irq_ack,
+        .irq_mask       = sunxi_irq_mask,
+        .irq_unmask     = sunxi_irq_unmask,
+};
+
+static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(virq, &sunxi_irq_chip,
+                                 handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops sunxi_irq_ops = {
+        .map = sunxi_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sunxi_of_init(struct device_node *node,
+                                struct device_node *parent)
+{
+        sunxi_irq_base = of_iomap(node, 0);
+        if (!sunxi_irq_base)
+                panic("%s: unable to map IC registers\n",
+                        node->full_name);
+
+        /* Disable all interrupts */
+        writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
+        writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
+        writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
+
+        /* Mask all the interrupts */
+        writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
+        writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
+        writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
+
+        /* Clear all the pending interrupts */
+        writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+        writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
+        writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
+
+        /* Enable protection mode */
+        writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
+
+        /* Configure the external interrupt source type */
+        writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
+
+        sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
+                                                 &sunxi_irq_ops, NULL);
+        if (!sunxi_irq_domain)
+                panic("%s: unable to create IRQ domain\n", node->full_name);
+
+        return 0;
+}
+
+static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
+        { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init },
+        { }
+};
+
+void __init sunxi_init_irq(void)
+{
+        of_irq_init(sunxi_irq_dt_ids);
+}
+
+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
+{
+        u32 irq, hwirq;
+
+        hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
+        while (hwirq != 0) {
+                irq = irq_find_mapping(sunxi_irq_domain, hwirq);
+                handle_IRQ(irq, regs);
+                hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
+        }
+}
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/drivers/irqchip/irq-versatile-fpga.c
index 091ae1030045..9dbd82b716d3 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -1,8 +1,10 @@
 /*
  *  Support for Versatile FPGA-based IRQ controllers
  */
+#include <linux/bitops.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -10,7 +12,6 @@
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
-#include <plat/fpga-irq.h>
 
 #define IRQ_STATUS              0x00
 #define IRQ_RAW_STATUS          0x04
@@ -41,7 +42,7 @@ struct fpga_irq_data {
 };
 
 /* we cannot allocate memory when the controllers are initially registered */
-static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
+static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
 static int fpga_irq_id;
 
 static void fpga_irq_mask(struct irq_data *d)
@@ -117,13 +118,12 @@ static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
         struct fpga_irq_data *f = d->host_data;
 
         /* Skip invalid IRQs, only register handlers for the real ones */
-        if (!(f->valid & (1 << hwirq)))
+        if (!(f->valid & BIT(hwirq)))
                 return -ENOTSUPP;
         irq_set_chip_data(irq, f);
         irq_set_chip_and_handler(irq, &f->chip,
                                 handle_level_irq);
         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        f->used_irqs++;
         return 0;
 }
 
@@ -132,13 +132,15 @@ static struct irq_domain_ops fpga_irqdomain_ops = {
         .xlate = irq_domain_xlate_onetwocell,
 };
 
-static __init struct fpga_irq_data *
-fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
+void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+                          int parent_irq, u32 valid, struct device_node *node)
+{
         struct fpga_irq_data *f;
+        int i;
 
         if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
-                printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
-                return NULL;
+                pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
+                return;
         }
         f = &fpga_irq_devices[fpga_irq_id];
         f->base = base;
@@ -147,36 +149,34 @@ fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
         f->chip.irq_mask = fpga_irq_mask;
         f->chip.irq_unmask = fpga_irq_unmask;
         f->valid = valid;
-        fpga_irq_id++;
-
-        return f;
-}
-
-void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
-                          int parent_irq, u32 valid, struct device_node *node)
-{
-        struct fpga_irq_data *f;
-
-        f = fpga_irq_prep_struct(base, name, valid);
-        if (!f)
-                return;
 
         if (parent_irq != -1) {
                 irq_set_handler_data(parent_irq, f);
                 irq_set_chained_handler(parent_irq, fpga_irq_handle);
         }
 
-        f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0,
+        /* This will also allocate irq descriptors */
+        f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
                                           &fpga_irqdomain_ops, f);
+
+        /* This will allocate all valid descriptors in the linear case */
+        for (i = 0; i < fls(valid); i++)
+                if (valid & BIT(i)) {
+                        if (!irq_start)
+                                irq_create_mapping(f->domain, i);
+                        f->used_irqs++;
+                }
+
         pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
                 fpga_irq_id, name, base, f->used_irqs);
+
+        fpga_irq_id++;
 }
 
 #ifdef CONFIG_OF
 int __init fpga_irq_of_init(struct device_node *node,
                             struct device_node *parent)
 {
-        struct fpga_irq_data *f;
         void __iomem *base;
         u32 clear_mask;
         u32 valid_mask;
@@ -193,18 +193,11 @@ int __init fpga_irq_of_init(struct device_node *node,
         if (of_property_read_u32(node, "valid-mask", &valid_mask))
                 valid_mask = 0;
 
-        f = fpga_irq_prep_struct(base, node->name, valid_mask);
-        if (!f)
-                return -ENOMEM;
+        fpga_irq_init(base, node->name, 0, -1, valid_mask, node);
 
         writel(clear_mask, base + IRQ_ENABLE_CLEAR);
         writel(clear_mask, base + FIQ_ENABLE_CLEAR);
 
-        f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f);
-        f->used_irqs = hweight32(valid_mask);
-
-        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
-                fpga_irq_id, node->name, base, f->used_irqs);
         return 0;
 }
 #endif
diff --git a/drivers/media/platform/soc_camera/mx2_camera.c b/drivers/media/platform/soc_camera/mx2_camera.c
index 8ac9b72b5ec7..791cd1d54a76 100644
--- a/drivers/media/platform/soc_camera/mx2_camera.c
+++ b/drivers/media/platform/soc_camera/mx2_camera.c
@@ -278,7 +278,8 @@ struct mx2_camera_dev {
         struct device           *dev;
         struct soc_camera_host  soc_host;
         struct soc_camera_device *icd;
-        struct clk              *clk_csi, *clk_emma_ahb, *clk_emma_ipg;
+        struct clk              *clk_emma_ahb, *clk_emma_ipg;
+        struct clk              *clk_csi_ahb, *clk_csi_per;
 
         void __iomem            *base_csi, *base_emma;
 
@@ -464,7 +465,8 @@ static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
 {
         unsigned long flags;
 
-        clk_disable_unprepare(pcdev->clk_csi);
+        clk_disable_unprepare(pcdev->clk_csi_ahb);
+        clk_disable_unprepare(pcdev->clk_csi_per);
         writel(0, pcdev->base_csi + CSICR1);
         if (is_imx27_camera(pcdev)) {
                 writel(0, pcdev->base_emma + PRP_CNTL);
@@ -492,10 +494,14 @@ static int mx2_camera_add_device(struct soc_camera_device *icd)
         if (pcdev->icd)
                 return -EBUSY;
 
-        ret = clk_prepare_enable(pcdev->clk_csi);
+        ret = clk_prepare_enable(pcdev->clk_csi_ahb);
         if (ret < 0)
                 return ret;
 
+        ret = clk_prepare_enable(pcdev->clk_csi_per);
+        if (ret < 0)
+                goto exit_csi_ahb;
+
         csicr1 = CSICR1_MCLKEN;
 
         if (is_imx27_camera(pcdev))
@@ -512,6 +518,11 @@ static int mx2_camera_add_device(struct soc_camera_device *icd)
                  icd->devnum);
 
         return 0;
+
+exit_csi_ahb:
+        clk_disable_unprepare(pcdev->clk_csi_ahb);
+
+        return ret;
 }
 
 static void mx2_camera_remove_device(struct soc_camera_device *icd)
@@ -1777,10 +1788,17 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
                 break;
         }
 
-        pcdev->clk_csi = devm_clk_get(&pdev->dev, "ahb");
-        if (IS_ERR(pcdev->clk_csi)) {
-                dev_err(&pdev->dev, "Could not get csi clock\n");
-                err = PTR_ERR(pcdev->clk_csi);
+        pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
+        if (IS_ERR(pcdev->clk_csi_ahb)) {
+                dev_err(&pdev->dev, "Could not get csi ahb clock\n");
+                err = PTR_ERR(pcdev->clk_csi_ahb);
+                goto exit;
+        }
+
+        pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
+        if (IS_ERR(pcdev->clk_csi_per)) {
+                dev_err(&pdev->dev, "Could not get csi per clock\n");
+                err = PTR_ERR(pcdev->clk_csi_per);
                 goto exit;
         }
 
@@ -1790,12 +1808,13 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
 
                 pcdev->platform_flags = pcdev->pdata->flags;
 
-                rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
+                rate = clk_round_rate(pcdev->clk_csi_per,
+                                                pcdev->pdata->clk * 2);
                 if (rate <= 0) {
                         err = -ENODEV;
                         goto exit;
                 }
-                err = clk_set_rate(pcdev->clk_csi, rate);
+                err = clk_set_rate(pcdev->clk_csi_per, rate);
                 if (err < 0)
                         goto exit;
         }
@@ -1853,7 +1872,7 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
                 goto exit_free_emma;
 
         dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
-                        clk_get_rate(pcdev->clk_csi));
+                        clk_get_rate(pcdev->clk_csi_per));
 
         return 0;
 
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2c10938b3567..94bdf83b4bc8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1080,3 +1080,9 @@ config MCP_UCB1200_TS
         depends on MCP_UCB1200 && INPUT
 
 endmenu
+
+config VEXPRESS_CONFIG
+        bool
+        help
+          Platform configuration infrastructure for the ARM Ltd.
+          Versatile Express.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b53db06d1b46..69f260ae0225 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -141,3 +141,4 @@ obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)      += sec-core.o sec-irq.o
 obj-$(CONFIG_MFD_SYSCON)        += syscon.o
 obj-$(CONFIG_MFD_LM3533)        += lm3533-core.o lm3533-ctrlbank.o
+obj-$(CONFIG_VEXPRESS_CONFIG)   += vexpress-config.o vexpress-sysreg.o
diff --git a/drivers/mfd/vexpress-config.c b/drivers/mfd/vexpress-config.c
new file mode 100644
index 000000000000..fae15d880758
--- /dev/null
+++ b/drivers/mfd/vexpress-config.c
@@ -0,0 +1,277 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+#define pr_fmt(fmt) "vexpress-config: " fmt
+
+#include <linux/bitops.h>
+#include <linux/completion.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/vexpress.h>
+
+
+#define VEXPRESS_CONFIG_MAX_BRIDGES 2
+
+struct vexpress_config_bridge {
+        struct device_node *node;
+        struct vexpress_config_bridge_info *info;
+        struct list_head transactions;
+        spinlock_t transactions_lock;
+} vexpress_config_bridges[VEXPRESS_CONFIG_MAX_BRIDGES];
+
+static DECLARE_BITMAP(vexpress_config_bridges_map,
+                ARRAY_SIZE(vexpress_config_bridges));
+static DEFINE_MUTEX(vexpress_config_bridges_mutex);
+
+struct vexpress_config_bridge *vexpress_config_bridge_register(
+                struct device_node *node,
+                struct vexpress_config_bridge_info *info)
+{
+        struct vexpress_config_bridge *bridge;
+        int i;
+
+        pr_debug("Registering bridge '%s'\n", info->name);
+
+        mutex_lock(&vexpress_config_bridges_mutex);
+        i = find_first_zero_bit(vexpress_config_bridges_map,
+                        ARRAY_SIZE(vexpress_config_bridges));
+        if (i >= ARRAY_SIZE(vexpress_config_bridges)) {
+                pr_err("Can't register more bridges!\n");
+                mutex_unlock(&vexpress_config_bridges_mutex);
+                return NULL;
+        }
+        __set_bit(i, vexpress_config_bridges_map);
+        bridge = &vexpress_config_bridges[i];
+
+        bridge->node = node;
+        bridge->info = info;
+        INIT_LIST_HEAD(&bridge->transactions);
+        spin_lock_init(&bridge->transactions_lock);
+
+        mutex_unlock(&vexpress_config_bridges_mutex);
+
+        return bridge;
+}
+
+void vexpress_config_bridge_unregister(struct vexpress_config_bridge *bridge)
+{
+        struct vexpress_config_bridge __bridge = *bridge;
+        int i;
+
+        mutex_lock(&vexpress_config_bridges_mutex);
+        for (i = 0; i < ARRAY_SIZE(vexpress_config_bridges); i++)
+                if (&vexpress_config_bridges[i] == bridge)
+                        __clear_bit(i, vexpress_config_bridges_map);
+        mutex_unlock(&vexpress_config_bridges_mutex);
+
+        WARN_ON(!list_empty(&__bridge.transactions));
+        while (!list_empty(&__bridge.transactions))
+                cpu_relax();
+}
+
+
+struct vexpress_config_func {
+        struct vexpress_config_bridge *bridge;
+        void *func;
+};
+
+struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
+                struct device_node *node)
+{
+        struct device_node *bridge_node;
+        struct vexpress_config_func *func;
+        int i;
+
+        if (WARN_ON(dev && node && dev->of_node != node))
+                return NULL;
+        if (dev && !node)
+                node = dev->of_node;
+
+        func = kzalloc(sizeof(*func), GFP_KERNEL);
+        if (!func)
+                return NULL;
+
+        bridge_node = of_node_get(node);
+        while (bridge_node) {
+                const __be32 *prop = of_get_property(bridge_node,
+                                "arm,vexpress,config-bridge", NULL);
+
+                if (prop) {
+                        bridge_node = of_find_node_by_phandle(
+                                        be32_to_cpup(prop));
+                        break;
+                }
+
+                bridge_node = of_get_next_parent(bridge_node);
+        }
+
+        mutex_lock(&vexpress_config_bridges_mutex);
+        for (i = 0; i < ARRAY_SIZE(vexpress_config_bridges); i++) {
+                struct vexpress_config_bridge *bridge =
+                                &vexpress_config_bridges[i];
+
+                if (test_bit(i, vexpress_config_bridges_map) &&
+                                bridge->node == bridge_node) {
+                        func->bridge = bridge;
+                        func->func = bridge->info->func_get(dev, node);
+                        break;
+                }
+        }
+        mutex_unlock(&vexpress_config_bridges_mutex);
+
+        if (!func->func) {
+                of_node_put(node);
+                kfree(func);
+                return NULL;
+        }
+
+        return func;
+}
+
+void vexpress_config_func_put(struct vexpress_config_func *func)
+{
+        func->bridge->info->func_put(func->func);
+        of_node_put(func->bridge->node);
+        kfree(func);
+}
+
+
+struct vexpress_config_trans {
+        struct vexpress_config_func *func;
+        int offset;
+        bool write;
+        u32 *data;
+        int status;
+        struct completion completion;
+        struct list_head list;
+};
+
+static void vexpress_config_dump_trans(const char *what,
+                struct vexpress_config_trans *trans)
+{
+        pr_debug("%s %s trans %p func 0x%p offset %d data 0x%x status %d\n",
+                        what, trans->write ? "write" : "read", trans,
+                        trans->func->func, trans->offset,
+                        trans->data ? *trans->data : 0, trans->status);
+}
+
+static int vexpress_config_schedule(struct vexpress_config_trans *trans)
+{
+        int status;
+        struct vexpress_config_bridge *bridge = trans->func->bridge;
+        unsigned long flags;
+
+        init_completion(&trans->completion);
+        trans->status = -EFAULT;
+
+        spin_lock_irqsave(&bridge->transactions_lock, flags);
+
+        vexpress_config_dump_trans("Executing", trans);
+
+        if (list_empty(&bridge->transactions))
+                status = bridge->info->func_exec(trans->func->func,
+                                trans->offset, trans->write, trans->data);
+        else
+                status = VEXPRESS_CONFIG_STATUS_WAIT;
+
+        switch (status) {
+        case VEXPRESS_CONFIG_STATUS_DONE:
+                vexpress_config_dump_trans("Finished", trans);
+                trans->status = status;
+                break;
+        case VEXPRESS_CONFIG_STATUS_WAIT:
+                list_add_tail(&trans->list, &bridge->transactions);
+                break;
+        }
+
+        spin_unlock_irqrestore(&bridge->transactions_lock, flags);
+
+        return status;
+}
+
+void vexpress_config_complete(struct vexpress_config_bridge *bridge,
+                int status)
+{
+        struct vexpress_config_trans *trans;
+        unsigned long flags;
+
+        spin_lock_irqsave(&bridge->transactions_lock, flags);
+
+        trans = list_first_entry(&bridge->transactions,
+                        struct vexpress_config_trans, list);
+        vexpress_config_dump_trans("Completed", trans);
+
+        trans->status = status;
+        list_del(&trans->list);
+
+        if (!list_empty(&bridge->transactions)) {
+                vexpress_config_dump_trans("Pending", trans);
+
+                bridge->info->func_exec(trans->func->func, trans->offset,
+                                trans->write, trans->data);
+        }
+        spin_unlock_irqrestore(&bridge->transactions_lock, flags);
+
+        complete(&trans->completion);
+}
+
+int vexpress_config_wait(struct vexpress_config_trans *trans)
+{
+        wait_for_completion(&trans->completion);
+
+        return trans->status;
+}
+
+
+int vexpress_config_read(struct vexpress_config_func *func, int offset,
+                u32 *data)
+{
+        struct vexpress_config_trans trans = {
+                .func = func,
+                .offset = offset,
+                .write = false,
+                .data = data,
+                .status = 0,
+        };
+        int status = vexpress_config_schedule(&trans);
+
+        if (status == VEXPRESS_CONFIG_STATUS_WAIT)
+                status = vexpress_config_wait(&trans);
+
+        return status;
+}
+EXPORT_SYMBOL(vexpress_config_read);
+
+int vexpress_config_write(struct vexpress_config_func *func, int offset,
+                u32 data)
+{
+        struct vexpress_config_trans trans = {
+                .func = func,
+                .offset = offset,
+                .write = true,
+                .data = &data,
+                .status = 0,
+        };
+        int status = vexpress_config_schedule(&trans);
+
+        if (status == VEXPRESS_CONFIG_STATUS_WAIT)
+                status = vexpress_config_wait(&trans);
+
+        return status;
+}
+EXPORT_SYMBOL(vexpress_config_write);
diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c
new file mode 100644
index 000000000000..733c06bd2d17
--- /dev/null
+++ b/drivers/mfd/vexpress-sysreg.c
@@ -0,0 +1,475 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/timer.h>
+#include <linux/vexpress.h>
+
+#define SYS_ID                  0x000
+#define SYS_SW                  0x004
+#define SYS_LED                 0x008
+#define SYS_100HZ               0x024
+#define SYS_FLAGS               0x030
+#define SYS_FLAGSSET            0x030
+#define SYS_FLAGSCLR            0x034
+#define SYS_NVFLAGS             0x038
+#define SYS_NVFLAGSSET          0x038
+#define SYS_NVFLAGSCLR          0x03c
+#define SYS_MCI                 0x048
+#define SYS_FLASH               0x04c
+#define SYS_CFGSW               0x058
+#define SYS_24MHZ               0x05c
+#define SYS_MISC                0x060
+#define SYS_DMA                 0x064
+#define SYS_PROCID0             0x084
+#define SYS_PROCID1             0x088
+#define SYS_CFGDATA             0x0a0
+#define SYS_CFGCTRL             0x0a4
+#define SYS_CFGSTAT             0x0a8
+
+#define SYS_HBI_MASK            0xfff
+#define SYS_ID_HBI_SHIFT        16
+#define SYS_PROCIDx_HBI_SHIFT   0
+
+#define SYS_MCI_CARDIN          (1 << 0)
+#define SYS_MCI_WPROT           (1 << 1)
+
+#define SYS_FLASH_WPn           (1 << 0)
+
+#define SYS_MISC_MASTERSITE     (1 << 14)
+
+#define SYS_CFGCTRL_START       (1 << 31)
+#define SYS_CFGCTRL_WRITE       (1 << 30)
+#define SYS_CFGCTRL_DCC(n)      (((n) & 0xf) << 26)
+#define SYS_CFGCTRL_FUNC(n)     (((n) & 0x3f) << 20)
+#define SYS_CFGCTRL_SITE(n)     (((n) & 0x3) << 16)
+#define SYS_CFGCTRL_POSITION(n) (((n) & 0xf) << 12)
+#define SYS_CFGCTRL_DEVICE(n)   (((n) & 0xfff) << 0)
+
+#define SYS_CFGSTAT_ERR         (1 << 1)
+#define SYS_CFGSTAT_COMPLETE    (1 << 0)
+
+
+static void __iomem *vexpress_sysreg_base;
+static struct device *vexpress_sysreg_dev;
+static int vexpress_master_site;
+
+
+void vexpress_flags_set(u32 data)
+{
+        writel(~0, vexpress_sysreg_base + SYS_FLAGSCLR);
+        writel(data, vexpress_sysreg_base + SYS_FLAGSSET);
+}
+
+u32 vexpress_get_procid(int site)
+{
+        if (site == VEXPRESS_SITE_MASTER)
+                site = vexpress_master_site;
+
+        return readl(vexpress_sysreg_base + (site == VEXPRESS_SITE_DB1 ?
+                        SYS_PROCID0 : SYS_PROCID1));
+}
+
+u32 vexpress_get_hbi(int site)
+{
+        u32 id;
+
+        switch (site) {
+        case VEXPRESS_SITE_MB:
+                id = readl(vexpress_sysreg_base + SYS_ID);
+                return (id >> SYS_ID_HBI_SHIFT) & SYS_HBI_MASK;
+        case VEXPRESS_SITE_MASTER:
+        case VEXPRESS_SITE_DB1:
+        case VEXPRESS_SITE_DB2:
+                id = vexpress_get_procid(site);
+                return (id >> SYS_PROCIDx_HBI_SHIFT) & SYS_HBI_MASK;
+        }
+
+        return ~0;
+}
+
+void __iomem *vexpress_get_24mhz_clock_base(void)
+{
+        return vexpress_sysreg_base + SYS_24MHZ;
+}
+
+
+static void vexpress_sysreg_find_prop(struct device_node *node,
+                const char *name, u32 *val)
+{
+        of_node_get(node);
+        while (node) {
+                if (of_property_read_u32(node, name, val) == 0) {
+                        of_node_put(node);
+                        return;
+                }
+                node = of_get_next_parent(node);
+        }
+}
+
+unsigned __vexpress_get_site(struct device *dev, struct device_node *node)
+{
+        u32 site = 0;
+
+        WARN_ON(dev && node && dev->of_node != node);
+        if (dev && !node)
+                node = dev->of_node;
+
+        if (node) {
+                vexpress_sysreg_find_prop(node, "arm,vexpress,site", &site);
+        } else if (dev && dev->bus == &platform_bus_type) {
+                struct platform_device *pdev = to_platform_device(dev);
+
+                if (pdev->num_resources == 1 &&
+                                pdev->resource[0].flags == IORESOURCE_BUS)
+                        site = pdev->resource[0].start;
+        } else if (dev && strncmp(dev_name(dev), "ct:", 3) == 0) {
+                site = VEXPRESS_SITE_MASTER;
+        }
+
+        if (site == VEXPRESS_SITE_MASTER)
+                site = vexpress_master_site;
+
+        return site;
+}
+
+
+struct vexpress_sysreg_config_func {
+        u32 template;
+        u32 device;
+};
+
+static struct vexpress_config_bridge *vexpress_sysreg_config_bridge;
+static struct timer_list vexpress_sysreg_config_timer;
+static u32 *vexpress_sysreg_config_data;
+static int vexpress_sysreg_config_tries;
+
+static void *vexpress_sysreg_config_func_get(struct device *dev,
+                struct device_node *node)
+{
+        struct vexpress_sysreg_config_func *config_func;
+        u32 site;
+        u32 position = 0;
+        u32 dcc = 0;
+        u32 func_device[2];
+        int err = -EFAULT;
+
+        if (node) {
+                of_node_get(node);
+                vexpress_sysreg_find_prop(node, "arm,vexpress,site", &site);
+                vexpress_sysreg_find_prop(node, "arm,vexpress,position",
+                                &position);
+                vexpress_sysreg_find_prop(node, "arm,vexpress,dcc", &dcc);
+                err = of_property_read_u32_array(node,
+                                "arm,vexpress-sysreg,func", func_device,
+                                ARRAY_SIZE(func_device));
+                of_node_put(node);
+        } else if (dev && dev->bus == &platform_bus_type) {
+                struct platform_device *pdev = to_platform_device(dev);
+
+                if (pdev->num_resources == 1 &&
+                                pdev->resource[0].flags == IORESOURCE_BUS) {
+                        site = pdev->resource[0].start;
+                        func_device[0] = pdev->resource[0].end;
+                        func_device[1] = pdev->id;
+                        err = 0;
+                }
+        }
+        if (err)
+                return NULL;
+
+        config_func = kzalloc(sizeof(*config_func), GFP_KERNEL);
+        if (!config_func)
+                return NULL;
+
+        config_func->template = SYS_CFGCTRL_DCC(dcc);
+        config_func->template |= SYS_CFGCTRL_FUNC(func_device[0]);
+        config_func->template |= SYS_CFGCTRL_SITE(site == VEXPRESS_SITE_MASTER ?
+                        vexpress_master_site : site);
+        config_func->template |= SYS_CFGCTRL_POSITION(position);
+        config_func->device |= func_device[1];
+
+        dev_dbg(vexpress_sysreg_dev, "func 0x%p = 0x%x, %d\n", config_func,
+                        config_func->template, config_func->device);
+
+        return config_func;
+}
+
+static void vexpress_sysreg_config_func_put(void *func)
+{
+        kfree(func);
+}
+
+static int vexpress_sysreg_config_func_exec(void *func, int offset,
+                bool write, u32 *data)
+{
+        int status;
+        struct vexpress_sysreg_config_func *config_func = func;
+        u32 command;
+
+        if (WARN_ON(!vexpress_sysreg_base))
+                return -ENOENT;
+
+        command = readl(vexpress_sysreg_base + SYS_CFGCTRL);
+        if (WARN_ON(command & SYS_CFGCTRL_START))
+                return -EBUSY;
+
+        command = SYS_CFGCTRL_START;
+        command |= write ? SYS_CFGCTRL_WRITE : 0;
+        command |= config_func->template;
+        command |= SYS_CFGCTRL_DEVICE(config_func->device + offset);
+
+        /* Use a canary for reads */
+        if (!write)
+                *data = 0xdeadbeef;
+
+        dev_dbg(vexpress_sysreg_dev, "command %x, data %x\n",
+                        command, *data);
+        writel(*data, vexpress_sysreg_base + SYS_CFGDATA);
+        writel(0, vexpress_sysreg_base + SYS_CFGSTAT);
+        writel(command, vexpress_sysreg_base + SYS_CFGCTRL);
+        mb();
+
+        if (vexpress_sysreg_dev) {
+                /* Schedule completion check */
+                if (!write)
+                        vexpress_sysreg_config_data = data;
+                vexpress_sysreg_config_tries = 100;
+                mod_timer(&vexpress_sysreg_config_timer,
+                                jiffies + usecs_to_jiffies(100));
+                status = VEXPRESS_CONFIG_STATUS_WAIT;
+        } else {
+                /* Early execution, no timer available, have to spin */
+                u32 cfgstat;
+
+                do {
+                        cpu_relax();
+                        cfgstat = readl(vexpress_sysreg_base + SYS_CFGSTAT);
+                } while (!cfgstat);
+
+                if (!write && (cfgstat & SYS_CFGSTAT_COMPLETE))
+                        *data = readl(vexpress_sysreg_base + SYS_CFGDATA);
+                status = VEXPRESS_CONFIG_STATUS_DONE;
+
+                if (cfgstat & SYS_CFGSTAT_ERR)
+                        status = -EINVAL;
+        }
+
+        return status;
+}
+
+struct vexpress_config_bridge_info vexpress_sysreg_config_bridge_info = {
+        .name = "vexpress-sysreg",
+        .func_get = vexpress_sysreg_config_func_get,
+        .func_put = vexpress_sysreg_config_func_put,
+        .func_exec = vexpress_sysreg_config_func_exec,
+};
+
+static void vexpress_sysreg_config_complete(unsigned long data)
+{
+        int status = VEXPRESS_CONFIG_STATUS_DONE;
+        u32 cfgstat = readl(vexpress_sysreg_base + SYS_CFGSTAT);
+
+        if (cfgstat & SYS_CFGSTAT_ERR)
+                status = -EINVAL;
+        if (!vexpress_sysreg_config_tries--)
+                status = -ETIMEDOUT;
+
+        if (status < 0) {
+                dev_err(vexpress_sysreg_dev, "error %d\n", status);
+        } else if (!(cfgstat & SYS_CFGSTAT_COMPLETE)) {
+                mod_timer(&vexpress_sysreg_config_timer,
+                                jiffies + usecs_to_jiffies(50));
+                return;
+        }
+
+        if (vexpress_sysreg_config_data) {
+                *vexpress_sysreg_config_data = readl(vexpress_sysreg_base +
+                                SYS_CFGDATA);
+                dev_dbg(vexpress_sysreg_dev, "read data %x\n",
+                                *vexpress_sysreg_config_data);
+                vexpress_sysreg_config_data = NULL;
+        }
+
+        vexpress_config_complete(vexpress_sysreg_config_bridge, status);
+}
+
+
+void __init vexpress_sysreg_early_init(void __iomem *base)
+{
+        struct device_node *node = of_find_compatible_node(NULL, NULL,
+                        "arm,vexpress-sysreg");
+
+        if (node)
+                base = of_iomap(node, 0);
+
+        if (WARN_ON(!base))
+                return;
+
+        vexpress_sysreg_base = base;
+
+        if (readl(vexpress_sysreg_base + SYS_MISC) & SYS_MISC_MASTERSITE)
+                vexpress_master_site = VEXPRESS_SITE_DB2;
+        else
+                vexpress_master_site = VEXPRESS_SITE_DB1;
+
+        vexpress_sysreg_config_bridge = vexpress_config_bridge_register(
+                        node, &vexpress_sysreg_config_bridge_info);
+        WARN_ON(!vexpress_sysreg_config_bridge);
+}
+
+void __init vexpress_sysreg_of_early_init(void)
+{
+        vexpress_sysreg_early_init(NULL);
+}
+
+
+static struct vexpress_sysreg_gpio {
+        unsigned long reg;
+        u32 value;
+} vexpress_sysreg_gpios[] = {
+        [VEXPRESS_GPIO_MMC_CARDIN] = {
+                .reg = SYS_MCI,
+                .value = SYS_MCI_CARDIN,
+        },
+        [VEXPRESS_GPIO_MMC_WPROT] = {
+                .reg = SYS_MCI,
+                .value = SYS_MCI_WPROT,
+        },
+        [VEXPRESS_GPIO_FLASH_WPn] = {
+                .reg = SYS_FLASH,
+                .value = SYS_FLASH_WPn,
+        },
+};
+
+static int vexpress_sysreg_gpio_direction_input(struct gpio_chip *chip,
+                                       unsigned offset)
+{
+        return 0;
+}
+
+static int vexpress_sysreg_gpio_direction_output(struct gpio_chip *chip,
+                                                unsigned offset, int value)
+{
+        return 0;
+}
+
+static int vexpress_sysreg_gpio_get(struct gpio_chip *chip,
+                                       unsigned offset)
+{
+        struct vexpress_sysreg_gpio *gpio = &vexpress_sysreg_gpios[offset];
+        u32 reg_value = readl(vexpress_sysreg_base + gpio->reg);
+
+        return !!(reg_value & gpio->value);
+}
+
+static void vexpress_sysreg_gpio_set(struct gpio_chip *chip,
+                                       unsigned offset, int value)
+{
+        struct vexpress_sysreg_gpio *gpio = &vexpress_sysreg_gpios[offset];
+        u32 reg_value = readl(vexpress_sysreg_base + gpio->reg);
+
+        if (value)
+                reg_value |= gpio->value;
+        else
+                reg_value &= ~gpio->value;
+
+        writel(reg_value, vexpress_sysreg_base + gpio->reg);
+}
+
+static struct gpio_chip vexpress_sysreg_gpio_chip = {
+        .label = "vexpress-sysreg",
+        .direction_input = vexpress_sysreg_gpio_direction_input,
+        .direction_output = vexpress_sysreg_gpio_direction_output,
+        .get = vexpress_sysreg_gpio_get,
+        .set = vexpress_sysreg_gpio_set,
+        .ngpio = ARRAY_SIZE(vexpress_sysreg_gpios),
+        .base = 0,
+};
+
+
+static ssize_t vexpress_sysreg_sys_id_show(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "0x%08x\n", readl(vexpress_sysreg_base + SYS_ID));
+}
+
+DEVICE_ATTR(sys_id, S_IRUGO, vexpress_sysreg_sys_id_show, NULL);
+
+static int __devinit vexpress_sysreg_probe(struct platform_device *pdev)
+{
+        int err;
+        struct resource *res = platform_get_resource(pdev,
+                        IORESOURCE_MEM, 0);
+
+        if (!devm_request_mem_region(&pdev->dev, res->start,
+                        resource_size(res), pdev->name)) {
+                dev_err(&pdev->dev, "Failed to request memory region!\n");
+                return -EBUSY;
+        }
+
+        if (!vexpress_sysreg_base)
+                vexpress_sysreg_base = devm_ioremap(&pdev->dev, res->start,
+                                resource_size(res));
+
+        if (!vexpress_sysreg_base) {
+                dev_err(&pdev->dev, "Failed to obtain base address!\n");
+                return -EFAULT;
+        }
+
+        setup_timer(&vexpress_sysreg_config_timer,
+                        vexpress_sysreg_config_complete, 0);
+
+        vexpress_sysreg_gpio_chip.dev = &pdev->dev;
+        err = gpiochip_add(&vexpress_sysreg_gpio_chip);
+        if (err) {
+                vexpress_config_bridge_unregister(
+                                vexpress_sysreg_config_bridge);
+                dev_err(&pdev->dev, "Failed to register GPIO chip! (%d)\n",
+                                err);
+                return err;
+        }
+
+        vexpress_sysreg_dev = &pdev->dev;
+
+        device_create_file(vexpress_sysreg_dev, &dev_attr_sys_id);
+
+        return 0;
+}
+
+static const struct of_device_id vexpress_sysreg_match[] = {
+        { .compatible = "arm,vexpress-sysreg", },
+        {},
+};
+
+static struct platform_driver vexpress_sysreg_driver = {
+        .driver = {
+                .name = "vexpress-sysreg",
+                .of_match_table = vexpress_sysreg_match,
+        },
+        .probe = vexpress_sysreg_probe,
+};
+
+static int __init vexpress_sysreg_init(void)
+{
+        return platform_driver_register(&vexpress_sysreg_driver);
+}
+core_initcall(vexpress_sysreg_init);
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 2e47c2ed0a2d..df304868bebb 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -324,13 +324,6 @@ config MTD_SOLUTIONENGINE
           This enables access to the flash chips on the Hitachi SolutionEngine and
           similar boards. Say 'Y' if you are building a kernel for such a board.
 
-config MTD_CDB89712
-        tristate "Cirrus CDB89712 evaluation board mappings"
-        depends on MTD_CFI && ARCH_CDB89712
-        help
-          This enables access to the flash or ROM chips on the CDB89712 board.
-          If you have such a board, say 'Y'.
-
 config MTD_SA1100
         tristate "CFI Flash device mapped on StrongARM SA11x0"
         depends on MTD_CFI && ARCH_SA1100
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index deb43e9a1e7f..a0240edd1961 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_MTD)		+= map_funcs.o
 endif
 
 # Chip mappings
-obj-$(CONFIG_MTD_CDB89712)      += cdb89712.o
 obj-$(CONFIG_MTD_CFI_FLAGADM)   += cfi_flagadm.o
 obj-$(CONFIG_MTD_DC21285)       += dc21285.o
 obj-$(CONFIG_MTD_DILNETPC)      += dilnetpc.o
diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
deleted file mode 100644
index c29cbf87ea0c..000000000000
--- a/drivers/mtd/maps/cdb89712.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * Flash on Cirrus CDB89712
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <asm/io.h>
-#include <mach/hardware.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-
-/* dynamic ioremap() areas */
-#define FLASH_START      0x00000000
-#define FLASH_SIZE       0x800000
-#define FLASH_WIDTH      4
-
-#define SRAM_START       0x60000000
-#define SRAM_SIZE        0xc000
-#define SRAM_WIDTH       4
-
-#define BOOTROM_START    0x70000000
-#define BOOTROM_SIZE     0x80
-#define BOOTROM_WIDTH    4
-
-
-static struct mtd_info *flash_mtd;
-
-struct map_info cdb89712_flash_map = {
-        .name = "flash",
-        .size = FLASH_SIZE,
-        .bankwidth = FLASH_WIDTH,
-        .phys = FLASH_START,
-};
-
-struct resource cdb89712_flash_resource = {
-        .name =   "Flash",
-        .start =  FLASH_START,
-        .end =    FLASH_START + FLASH_SIZE - 1,
-        .flags =  IORESOURCE_IO | IORESOURCE_BUSY,
-};
-
-static int __init init_cdb89712_flash (void)
-{
-        int err;
-
-        if (request_resource (&ioport_resource, &cdb89712_flash_resource)) {
-                printk(KERN_NOTICE "Failed to reserve Cdb89712 FLASH space\n");
-                err = -EBUSY;
-                goto out;
-        }
-
-        cdb89712_flash_map.virt = ioremap(FLASH_START, FLASH_SIZE);
-        if (!cdb89712_flash_map.virt) {
-                printk(KERN_NOTICE "Failed to ioremap Cdb89712 FLASH space\n");
-                err = -EIO;
-                goto out_resource;
-        }
-        simple_map_init(&cdb89712_flash_map);
-        flash_mtd = do_map_probe("cfi_probe", &cdb89712_flash_map);
-        if (!flash_mtd) {
-                flash_mtd = do_map_probe("map_rom", &cdb89712_flash_map);
-                if (flash_mtd)
-                        flash_mtd->erasesize = 0x10000;
-        }
-        if (!flash_mtd) {
-                printk("FLASH probe failed\n");
-                err = -ENXIO;
-                goto out_ioremap;
-        }
-
-        flash_mtd->owner = THIS_MODULE;
-
-        if (mtd_device_register(flash_mtd, NULL, 0)) {
-                printk("FLASH device addition failed\n");
-                err = -ENOMEM;
-                goto out_probe;
-        }
-
-        return 0;
-
-out_probe:
-        map_destroy(flash_mtd);
-        flash_mtd = 0;
-out_ioremap:
-        iounmap((void *)cdb89712_flash_map.virt);
-out_resource:
-        release_resource (&cdb89712_flash_resource);
-out:
-        return err;
-}
-
-
-
-
-
-static struct mtd_info *sram_mtd;
-
-struct map_info cdb89712_sram_map = {
-        .name = "SRAM",
-        .size = SRAM_SIZE,
-        .bankwidth = SRAM_WIDTH,
-        .phys = SRAM_START,
-};
-
-struct resource cdb89712_sram_resource = {
-        .name =   "SRAM",
-        .start =  SRAM_START,
-        .end =    SRAM_START + SRAM_SIZE - 1,
-        .flags =  IORESOURCE_IO | IORESOURCE_BUSY,
-};
-
-static int __init init_cdb89712_sram (void)
-{
-        int err;
-
-        if (request_resource (&ioport_resource, &cdb89712_sram_resource)) {
-                printk(KERN_NOTICE "Failed to reserve Cdb89712 SRAM space\n");
-                err = -EBUSY;
-                goto out;
-        }
-
-        cdb89712_sram_map.virt = ioremap(SRAM_START, SRAM_SIZE);
-        if (!cdb89712_sram_map.virt) {
-                printk(KERN_NOTICE "Failed to ioremap Cdb89712 SRAM space\n");
-                err = -EIO;
-                goto out_resource;
-        }
-        simple_map_init(&cdb89712_sram_map);
-        sram_mtd = do_map_probe("map_ram", &cdb89712_sram_map);
-        if (!sram_mtd) {
-                printk("SRAM probe failed\n");
-                err = -ENXIO;
-                goto out_ioremap;
-        }
-
-        sram_mtd->owner = THIS_MODULE;
-        sram_mtd->erasesize = 16;
-
-        if (mtd_device_register(sram_mtd, NULL, 0)) {
-                printk("SRAM device addition failed\n");
-                err = -ENOMEM;
-                goto out_probe;
-        }
-
-        return 0;
-
-out_probe:
-        map_destroy(sram_mtd);
-        sram_mtd = 0;
-out_ioremap:
-        iounmap((void *)cdb89712_sram_map.virt);
-out_resource:
-        release_resource (&cdb89712_sram_resource);
-out:
-        return err;
-}
-
-
-
-
-
-
-
-static struct mtd_info *bootrom_mtd;
-
-struct map_info cdb89712_bootrom_map = {
-        .name = "BootROM",
-        .size = BOOTROM_SIZE,
-        .bankwidth = BOOTROM_WIDTH,
-        .phys = BOOTROM_START,
-};
-
-struct resource cdb89712_bootrom_resource = {
-        .name =   "BootROM",
-        .start =  BOOTROM_START,
-        .end =    BOOTROM_START + BOOTROM_SIZE - 1,
-        .flags =  IORESOURCE_IO | IORESOURCE_BUSY,
-};
-
-static int __init init_cdb89712_bootrom (void)
-{
-        int err;
-
-        if (request_resource (&ioport_resource, &cdb89712_bootrom_resource)) {
-                printk(KERN_NOTICE "Failed to reserve Cdb89712 BOOTROM space\n");
-                err = -EBUSY;
-                goto out;
-        }
-
-        cdb89712_bootrom_map.virt = ioremap(BOOTROM_START, BOOTROM_SIZE);
-        if (!cdb89712_bootrom_map.virt) {
-                printk(KERN_NOTICE "Failed to ioremap Cdb89712 BootROM space\n");
-                err = -EIO;
-                goto out_resource;
-        }
-        simple_map_init(&cdb89712_bootrom_map);
-        bootrom_mtd = do_map_probe("map_rom", &cdb89712_bootrom_map);
-        if (!bootrom_mtd) {
-                printk("BootROM probe failed\n");
-                err = -ENXIO;
-                goto out_ioremap;
-        }
-
-        bootrom_mtd->owner = THIS_MODULE;
-        bootrom_mtd->erasesize = 0x10000;
-
-        if (mtd_device_register(bootrom_mtd, NULL, 0)) {
-                printk("BootROM device addition failed\n");
-                err = -ENOMEM;
-                goto out_probe;
-        }
-
-        return 0;
-
-out_probe:
-        map_destroy(bootrom_mtd);
-        bootrom_mtd = 0;
-out_ioremap:
-        iounmap((void *)cdb89712_bootrom_map.virt);
-out_resource:
-        release_resource (&cdb89712_bootrom_resource);
-out:
-        return err;
-}
-
-
-
-
-
-static int __init init_cdb89712_maps(void)
-{
-
-        printk(KERN_INFO "Cirrus CDB89712 MTD mappings:\n  Flash 0x%x at 0x%x\n  SRAM 0x%x at 0x%x\n  BootROM 0x%x at 0x%x\n",
-               FLASH_SIZE, FLASH_START, SRAM_SIZE, SRAM_START, BOOTROM_SIZE, BOOTROM_START);
-
-        init_cdb89712_flash();
-        init_cdb89712_sram();
-        init_cdb89712_bootrom();
-
-        return 0;
-}
-
-
-static void __exit cleanup_cdb89712_maps(void)
-{
-        if (sram_mtd) {
-                mtd_device_unregister(sram_mtd);
-                map_destroy(sram_mtd);
-                iounmap((void *)cdb89712_sram_map.virt);
-                release_resource (&cdb89712_sram_resource);
-        }
-
-        if (flash_mtd) {
-                mtd_device_unregister(flash_mtd);
-                map_destroy(flash_mtd);
-                iounmap((void *)cdb89712_flash_map.virt);
-                release_resource (&cdb89712_flash_resource);
-        }
-
-        if (bootrom_mtd) {
-                mtd_device_unregister(bootrom_mtd);
-                map_destroy(bootrom_mtd);
-                iounmap((void *)cdb89712_bootrom_map.virt);
-                release_resource (&cdb89712_bootrom_resource);
-        }
-}
-
-module_init(init_cdb89712_maps);
-module_exit(cleanup_cdb89712_maps);
-
-MODULE_AUTHOR("Ray L");
-MODULE_DESCRIPTION("ARM CDB89712 map driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4883139460be..531807dec6b3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -49,13 +49,6 @@ config MTD_NAND_MUSEUM_IDS
           NAND chips (page size 256 byte, erase size 4-8KiB). The IDs
           of these chips were reused by later, larger chips.
 
-config MTD_NAND_AUTCPU12
-        tristate "SmartMediaCard on autronix autcpu12 board"
-        depends on ARCH_AUTCPU12
-        help
-          This enables the driver for the autronix autcpu12 board to
-          access the SmartMediaCard.
-
 config MTD_NAND_DENALI
        depends on PCI
         tristate "Support Denali NAND controller on Intel Moorestown"
@@ -86,12 +79,6 @@ config MTD_NAND_GPIO
         help
           This enables a GPIO based NAND flash driver.
 
-config MTD_NAND_SPIA
-        tristate "NAND Flash device on SPIA board"
-        depends on ARCH_P720T
-        help
-          If you had to ask, you don't have one. Say 'N'.
-
 config MTD_NAND_AMS_DELTA
         tristate "NAND Flash device on Amstrad E3"
         depends on MACH_AMS_DELTA
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2cbd0916b733..6c7f2b3ca8ae 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -9,9 +9,7 @@ obj-$(CONFIG_MTD_NAND_IDS)		+= nand_ids.o
 obj-$(CONFIG_MTD_SM_COMMON)             += sm_common.o
 
 obj-$(CONFIG_MTD_NAND_CAFE)             += cafe_nand.o
-obj-$(CONFIG_MTD_NAND_SPIA)             += spia.o
 obj-$(CONFIG_MTD_NAND_AMS_DELTA)        += ams-delta.o
-obj-$(CONFIG_MTD_NAND_AUTCPU12)         += autcpu12.o
 obj-$(CONFIG_MTD_NAND_DENALI)           += denali.o
 obj-$(CONFIG_MTD_NAND_AU1550)           += au1550nd.o
 obj-$(CONFIG_MTD_NAND_BF5XX)            += bf5xx_nand.o
diff --git a/drivers/mtd/nand/autcpu12.c b/drivers/mtd/nand/autcpu12.c
deleted file mode 100644
index 04769a49a7cb..000000000000
--- a/drivers/mtd/nand/autcpu12.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- *  drivers/mtd/autcpu12.c
- *
- *  Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
- *
- *  Derived from drivers/mtd/spia.c
- *       Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Overview:
- *   This is a device driver for the NAND flash device found on the
- *   autronix autcpu12 board, which is a SmartMediaCard. It supports
- *   16MiB, 32MiB and 64MiB cards.
- *
- *
- *      02-12-2002 TG   Cleanup of module params
- *
- *      02-20-2002 TG   adjusted for different rd/wr address support
- *                      added support for read device ready/busy line
- *                      added page_cache
- *
- *      10-06-2002 TG   128K card support added
- */
-
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <asm/io.h>
-#include <mach/hardware.h>
-#include <asm/sizes.h>
-#include <mach/autcpu12.h>
-
-/*
- * MTD structure for AUTCPU12 board
- */
-static struct mtd_info *autcpu12_mtd = NULL;
-static void __iomem *autcpu12_fio_base;
-
-/*
- * Define partitions for flash devices
- */
-static struct mtd_partition partition_info16k[] = {
-        { .name         = "AUTCPU12 flash partition 1",
-          .offset       = 0,
-          .size         = 8 * SZ_1M },
-        { .name         = "AUTCPU12 flash partition 2",
-          .offset       = 8 * SZ_1M,
-          .size         = 8 * SZ_1M },
-};
-
-static struct mtd_partition partition_info32k[] = {
-        { .name         = "AUTCPU12 flash partition 1",
-          .offset       = 0,
-          .size         = 8 * SZ_1M },
-        { .name         = "AUTCPU12 flash partition 2",
-          .offset       = 8 * SZ_1M,
-          .size         = 24 * SZ_1M },
-};
-
-static struct mtd_partition partition_info64k[] = {
-        { .name         = "AUTCPU12 flash partition 1",
-          .offset       = 0,
-          .size         = 16 * SZ_1M },
-        { .name         = "AUTCPU12 flash partition 2",
-          .offset       = 16 * SZ_1M,
-          .size         = 48 * SZ_1M },
-};
-
-static struct mtd_partition partition_info128k[] = {
-        { .name         = "AUTCPU12 flash partition 1",
-          .offset       = 0,
-          .size         = 16 * SZ_1M },
-        { .name         = "AUTCPU12 flash partition 2",
-          .offset       = 16 * SZ_1M,
-          .size         = 112 * SZ_1M },
-};
-
-#define NUM_PARTITIONS16K 2
-#define NUM_PARTITIONS32K 2
-#define NUM_PARTITIONS64K 2
-#define NUM_PARTITIONS128K 2
-/*
- *      hardware specific access to control-lines
- *
- *      ALE bit 4 autcpu12_pedr
- *      CLE bit 5 autcpu12_pedr
- *      NCE bit 0 fio_ctrl
- *
- */
-static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd,
-                               unsigned int ctrl)
-{
-        struct nand_chip *chip = mtd->priv;
-
-        if (ctrl & NAND_CTRL_CHANGE) {
-                void __iomem *addr;
-                unsigned char bits;
-
-                bits = clps_readb(AUTCPU12_SMC_PORT_OFFSET) & ~0x30;
-                bits |= (ctrl & NAND_CLE) << 4;
-                bits |= (ctrl & NAND_ALE) << 2;
-                clps_writeb(bits, AUTCPU12_SMC_PORT_OFFSET);
-
-                addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
-                writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
-        }
-
-        if (cmd != NAND_CMD_NONE)
-                writeb(cmd, chip->IO_ADDR_W);
-}
-
-/*
- *      read device ready pin
- */
-int autcpu12_device_ready(struct mtd_info *mtd)
-{
-        return clps_readb(AUTCPU12_SMC_PORT_OFFSET) & AUTCPU12_SMC_RDY;
-}
-
-/*
- * Main initialization routine
- */
-static int __init autcpu12_init(void)
-{
-        struct nand_chip *this;
-        int err = 0;
-
-        /* Allocate memory for MTD device structure and private data */
-        autcpu12_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
-                               GFP_KERNEL);
-        if (!autcpu12_mtd) {
-                printk("Unable to allocate AUTCPU12 NAND MTD device structure.\n");
-                err = -ENOMEM;
-                goto out;
-        }
-
-        /* map physical address */
-        autcpu12_fio_base = ioremap(AUTCPU12_PHYS_SMC, SZ_1K);
-        if (!autcpu12_fio_base) {
-                printk("Ioremap autcpu12 SmartMedia Card failed\n");
-                err = -EIO;
-                goto out_mtd;
-        }
-
-        /* Get pointer to private data */
-        this = (struct nand_chip *)(&autcpu12_mtd[1]);
-
-        /* Initialize structures */
-        memset(autcpu12_mtd, 0, sizeof(struct mtd_info));
-        memset(this, 0, sizeof(struct nand_chip));
-
-        /* Link the private data with the MTD structure */
-        autcpu12_mtd->priv = this;
-        autcpu12_mtd->owner = THIS_MODULE;
-
-        /* Set address of NAND IO lines */
-        this->IO_ADDR_R = autcpu12_fio_base;
-        this->IO_ADDR_W = autcpu12_fio_base;
-        this->cmd_ctrl = autcpu12_hwcontrol;
-        this->dev_ready = autcpu12_device_ready;
-        /* 20 us command delay time */
-        this->chip_delay = 20;
-        this->ecc.mode = NAND_ECC_SOFT;
-
-        /* Enable the following for a flash based bad block table */
-        /*
-           this->bbt_options = NAND_BBT_USE_FLASH;
-         */
-        this->bbt_options = NAND_BBT_USE_FLASH;
-
-        /* Scan to find existence of the device */
-        if (nand_scan(autcpu12_mtd, 1)) {
-                err = -ENXIO;
-                goto out_ior;
-        }
-
-        /* Register the partitions */
-        switch (autcpu12_mtd->size) {
-                case SZ_16M:
-                        mtd_device_register(autcpu12_mtd, partition_info16k,
-                                            NUM_PARTITIONS16K);
-                        break;
-                case SZ_32M:
-                        mtd_device_register(autcpu12_mtd, partition_info32k,
-                                            NUM_PARTITIONS32K);
-                        break;
-                case SZ_64M:
-                        mtd_device_register(autcpu12_mtd, partition_info64k,
-                                            NUM_PARTITIONS64K);
-                        break;
-                case SZ_128M:
-                        mtd_device_register(autcpu12_mtd, partition_info128k,
-                                            NUM_PARTITIONS128K);
-                        break;
-                default:
-                        printk("Unsupported SmartMedia device\n");
-                        err = -ENXIO;
-                        goto out_ior;
-        }
-        goto out;
-
- out_ior:
-        iounmap(autcpu12_fio_base);
- out_mtd:
-        kfree(autcpu12_mtd);
- out:
-        return err;
-}
-
-module_init(autcpu12_init);
-
-/*
- * Clean up routine
- */
-static void __exit autcpu12_cleanup(void)
-{
-        /* Release resources, unregister device */
-        nand_release(autcpu12_mtd);
-
-        /* unmap physical address */
-        iounmap(autcpu12_fio_base);
-
-        /* Free the MTD device structure */
-        kfree(autcpu12_mtd);
-}
-
-module_exit(autcpu12_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
-MODULE_DESCRIPTION("Glue layer for SmartMediaCard on autronix autcpu12");
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c
deleted file mode 100644
index bef76cd7c24c..000000000000
--- a/drivers/mtd/nand/spia.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- *  drivers/mtd/nand/spia.c
- *
- *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- *
- *      10-29-2001 TG   change to support hardwarespecific access
- *                      to controllines (due to change in nand.c)
- *                      page_cache added
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Overview:
- *   This is a device driver for the NAND flash device found on the
- *   SPIA board which utilizes the Toshiba TC58V64AFT part. This is
- *   a 64Mibit (8MiB x 8 bits) NAND flash device.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <asm/io.h>
-
-/*
- * MTD structure for SPIA board
- */
-static struct mtd_info *spia_mtd = NULL;
-
-/*
- * Values specific to the SPIA board (used with EP7212 processor)
- */
-#define SPIA_IO_BASE    0xd0000000      /* Start of EP7212 IO address space */
-#define SPIA_FIO_BASE   0xf0000000      /* Address where flash is mapped */
-#define SPIA_PEDR       0x0080  /*
-                                 * IO offset to Port E data register
-                                 * where the CLE, ALE and NCE pins
-                                 * are wired to.
-                                 */
-#define SPIA_PEDDR      0x00c0  /*
-                                 * IO offset to Port E data direction
-                                 * register so we can control the IO
-                                 * lines.
-                                 */
-
-/*
- * Module stuff
- */
-
-static int spia_io_base = SPIA_IO_BASE;
-static int spia_fio_base = SPIA_FIO_BASE;
-static int spia_pedr = SPIA_PEDR;
-static int spia_peddr = SPIA_PEDDR;
-
-module_param(spia_io_base, int, 0);
-module_param(spia_fio_base, int, 0);
-module_param(spia_pedr, int, 0);
-module_param(spia_peddr, int, 0);
-
-/*
- * Define partitions for flash device
- */
-static const struct mtd_partition partition_info[] = {
-        {
-         .name = "SPIA flash partition 1",
-         .offset = 0,
-         .size = 2 * 1024 * 1024},
-        {
-         .name = "SPIA flash partition 2",
-         .offset = 2 * 1024 * 1024,
-         .size = 6 * 1024 * 1024}
-};
-
-#define NUM_PARTITIONS 2
-
-/*
- *      hardware specific access to control-lines
- *
- *      ctrl:
- *      NAND_CNE: bit 0 -> bit 2
- *      NAND_CLE: bit 1 -> bit 0
- *      NAND_ALE: bit 2 -> bit 1
- */
-static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
-{
-        struct nand_chip *chip = mtd->priv;
-
-        if (ctrl & NAND_CTRL_CHANGE) {
-                void __iomem *addr = spia_io_base + spia_pedr;
-                unsigned char bits;
-
-                bits = (ctrl & NAND_CNE) << 2;
-                bits |= (ctrl & NAND_CLE | NAND_ALE) >> 1;
-                writeb((readb(addr) & ~0x7) | bits, addr);
-        }
-
-        if (cmd != NAND_CMD_NONE)
-                writeb(cmd, chip->IO_ADDR_W);
-}
-
-/*
- * Main initialization routine
- */
-static int __init spia_init(void)
-{
-        struct nand_chip *this;
-
-        /* Allocate memory for MTD device structure and private data */
-        spia_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
-        if (!spia_mtd) {
-                printk("Unable to allocate SPIA NAND MTD device structure.\n");
-                return -ENOMEM;
-        }
-
-        /* Get pointer to private data */
-        this = (struct nand_chip *)(&spia_mtd[1]);
-
-        /* Initialize structures */
-        memset(spia_mtd, 0, sizeof(struct mtd_info));
-        memset(this, 0, sizeof(struct nand_chip));
-
-        /* Link the private data with the MTD structure */
-        spia_mtd->priv = this;
-        spia_mtd->owner = THIS_MODULE;
-
-        /*
-         * Set GPIO Port E control register so that the pins are configured
-         * to be outputs for controlling the NAND flash.
-         */
-        (*(volatile unsigned char *)(spia_io_base + spia_peddr)) = 0x07;
-
-        /* Set address of NAND IO lines */
-        this->IO_ADDR_R = (void __iomem *)spia_fio_base;
-        this->IO_ADDR_W = (void __iomem *)spia_fio_base;
-        /* Set address of hardware control function */
-        this->cmd_ctrl = spia_hwcontrol;
-        /* 15 us command delay time */
-        this->chip_delay = 15;
-
-        /* Scan to find existence of the device */
-        if (nand_scan(spia_mtd, 1)) {
-                kfree(spia_mtd);
-                return -ENXIO;
-        }
-
-        /* Register the partitions */
-        mtd_device_register(spia_mtd, partition_info, NUM_PARTITIONS);
-
-        /* Return happy */
-        return 0;
-}
-
-module_init(spia_init);
-
-/*
- * Clean up routine
- */
-static void __exit spia_cleanup(void)
-{
-        /* Release resources, unregister device */
-        nand_release(spia_mtd);
-
-        /* Free the MTD device structure */
-        kfree(spia_mtd);
-}
-
-module_exit(spia_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com");
-MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on SPIA board");
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 390ab69ea569..c31aeb01bb00 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -190,6 +190,11 @@ config PINCTRL_EXYNOS4
         depends on OF && GPIOLIB
         select PINCTRL_SAMSUNG
 
+config PINCTRL_EXYNOS5440
+        bool "Samsung EXYNOS5440 SoC pinctrl driver"
+        select PINMUX
+        select PINCONF
+
 source "drivers/pinctrl/mvebu/Kconfig"
 
 source "drivers/pinctrl/spear/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f95f5ed923be..fc4606f27dc7 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)    += pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)   += pinctrl-samsung.o
 obj-$(CONFIG_PINCTRL_EXYNOS4)   += pinctrl-exynos.o
+obj-$(CONFIG_PINCTRL_EXYNOS5440)        += pinctrl-exynos5440.o
 obj-$(CONFIG_PINCTRL_XWAY)      += pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)    += pinctrl-lantiq.o
 
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 6ff665209a4c..538b9ddaadf7 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -41,46 +41,46 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
 
 static void exynos_gpio_irq_unmask(struct irq_data *irqd)
 {
-        struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
-        struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
-        unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = bank->drvdata;
+        unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
         unsigned long mask;
 
         mask = readl(d->virt_base + reg_mask);
-        mask &= ~(1 << edata->pin);
+        mask &= ~(1 << irqd->hwirq);
         writel(mask, d->virt_base + reg_mask);
 }
 
 static void exynos_gpio_irq_mask(struct irq_data *irqd)
 {
-        struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
-        struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
-        unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = bank->drvdata;
+        unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
         unsigned long mask;
 
         mask = readl(d->virt_base + reg_mask);
-        mask |= 1 << edata->pin;
+        mask |= 1 << irqd->hwirq;
         writel(mask, d->virt_base + reg_mask);
 }
 
 static void exynos_gpio_irq_ack(struct irq_data *irqd)
 {
-        struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
-        struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
-        unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = bank->drvdata;
+        unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
 
-        writel(1 << edata->pin, d->virt_base + reg_pend);
+        writel(1 << irqd->hwirq, d->virt_base + reg_pend);
 }
 
 static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
 {
-        struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = bank->drvdata;
         struct samsung_pin_ctrl *ctrl = d->ctrl;
-        struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
-        struct samsung_pin_bank *bank = edata->bank;
-        unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
+        unsigned int pin = irqd->hwirq;
+        unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
         unsigned int con, trig_type;
-        unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
+        unsigned long reg_con = ctrl->geint_con + bank->eint_offset;
         unsigned int mask;
 
         switch (type) {
@@ -115,7 +115,7 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
         writel(con, d->virt_base + reg_con);
 
         reg_con = bank->pctl_offset;
-        shift = edata->pin * bank->func_width;
+        shift = pin * bank->func_width;
         mask = (1 << bank->func_width) - 1;
 
         con = readl(d->virt_base + reg_con);
@@ -137,82 +137,23 @@ static struct irq_chip exynos_gpio_irq_chip = {
         .irq_set_type   = exynos_gpio_irq_set_type,
 };
 
-/*
- * given a controller-local external gpio interrupt number, prepare the handler
- * data for it.
- */
-static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
-                                struct samsung_pinctrl_drv_data *d)
-{
-        struct samsung_pin_bank *bank = d->ctrl->pin_banks;
-        struct exynos_geint_data *eint_data;
-        unsigned int nr_banks = d->ctrl->nr_banks, idx;
-        unsigned int irq_base = 0, eint_offset = 0;
-
-        if (hw >= d->ctrl->nr_gint) {
-                dev_err(d->dev, "unsupported ext-gpio interrupt\n");
-                return NULL;
-        }
-
-        for (idx = 0; idx < nr_banks; idx++, bank++) {
-                if (bank->eint_type != EINT_TYPE_GPIO)
-                        continue;
-                if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
-                        break;
-                irq_base += bank->nr_pins;
-                eint_offset += 4;
-        }
-
-        if (idx == nr_banks) {
-                dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
-                return NULL;
-        }
-
-        eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
-        if (!eint_data) {
-                dev_err(d->dev, "no memory for eint-gpio data\n");
-                return NULL;
-        }
-
-        eint_data->bank = bank;
-        eint_data->pin = hw - irq_base;
-        eint_data->eint_offset = eint_offset;
-        return eint_data;
-}
-
 static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
                                         irq_hw_number_t hw)
 {
-        struct samsung_pinctrl_drv_data *d = h->host_data;
-        struct exynos_geint_data *eint_data;
-
-        eint_data = exynos_get_eint_data(hw, d);
-        if (!eint_data)
-                return -EINVAL;
+        struct samsung_pin_bank *b = h->host_data;
 
-        irq_set_handler_data(virq, eint_data);
-        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_data(virq, b);
         irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
                                         handle_level_irq);
         set_irq_flags(virq, IRQF_VALID);
         return 0;
 }
 
-static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
-{
-        struct samsung_pinctrl_drv_data *d = h->host_data;
-        struct exynos_geint_data *eint_data;
-
-        eint_data = irq_get_handler_data(virq);
-        devm_kfree(d->dev, eint_data);
-}
-
 /*
  * irq domain callbacks for external gpio interrupt controller.
  */
 static const struct irq_domain_ops exynos_gpio_irqd_ops = {
         .map    = exynos_gpio_irq_map,
-        .unmap  = exynos_gpio_irq_unmap,
         .xlate  = irq_domain_xlate_twocell,
 };
 
@@ -231,7 +172,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
                 return IRQ_HANDLED;
         bank += (group - 1);
 
-        virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
+        virq = irq_linear_revmap(bank->irq_domain, pin);
         if (!virq)
                 return IRQ_NONE;
         generic_handle_irq(virq);
@@ -244,8 +185,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
  */
 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 {
+        struct samsung_pin_bank *bank;
         struct device *dev = d->dev;
         unsigned int ret;
+        unsigned int i;
 
         if (!d->irq) {
                 dev_err(dev, "irq number not available\n");
@@ -259,11 +202,16 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
                 return -ENXIO;
         }
 
-        d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
-                                &exynos_gpio_irqd_ops, d);
-        if (!d->gpio_irqd) {
-                dev_err(dev, "gpio irq domain allocation failed\n");
-                return -ENXIO;
+        bank = d->ctrl->pin_banks;
+        for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
+                if (bank->eint_type != EINT_TYPE_GPIO)
+                        continue;
+                bank->irq_domain = irq_domain_add_linear(bank->of_node,
+                                bank->nr_pins, &exynos_gpio_irqd_ops, bank);
+                if (!bank->irq_domain) {
+                        dev_err(dev, "gpio irq domain add failed\n");
+                        return -ENXIO;
+                }
         }
 
         return 0;
@@ -271,48 +219,46 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 
 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
 {
-        struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
-        unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
-        unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
-        unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
+        struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = b->drvdata;
+        unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
         unsigned long mask;
 
         mask = readl(d->virt_base + reg_mask);
-        mask &= ~(1 << pin);
+        mask &= ~(1 << irqd->hwirq);
         writel(mask, d->virt_base + reg_mask);
 }
 
 static void exynos_wkup_irq_mask(struct irq_data *irqd)
 {
-        struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
-        unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
-        unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
-        unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
+        struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = b->drvdata;
+        unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
         unsigned long mask;
 
         mask = readl(d->virt_base + reg_mask);
-        mask |= 1 << pin;
+        mask |= 1 << irqd->hwirq;
         writel(mask, d->virt_base + reg_mask);
 }
 
 static void exynos_wkup_irq_ack(struct irq_data *irqd)
 {
-        struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
-        unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
-        unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
-        unsigned long pend = d->ctrl->weint_pend + (bank << 2);
+        struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = b->drvdata;
+        unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
 
-        writel(1 << pin, d->virt_base + pend);
+        writel(1 << irqd->hwirq, d->virt_base + pend);
 }
 
 static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
 {
-        struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
-        unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
-        unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
-        unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        struct samsung_pinctrl_drv_data *d = bank->drvdata;
+        unsigned int pin = irqd->hwirq;
+        unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
         unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
         unsigned long con, trig_type;
+        unsigned int mask;
 
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
@@ -344,6 +290,16 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
         con &= ~(EXYNOS_EINT_CON_MASK << shift);
         con |= trig_type << shift;
         writel(con, d->virt_base + reg_con);
+
+        reg_con = bank->pctl_offset;
+        shift = pin * bank->func_width;
+        mask = (1 << bank->func_width) - 1;
+
+        con = readl(d->virt_base + reg_con);
+        con &= ~(mask << shift);
+        con |= EXYNOS_EINT_FUNC << shift;
+        writel(con, d->virt_base + reg_con);
+
         return 0;
 }
 
@@ -362,6 +318,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
         struct exynos_weint_data *eintd = irq_get_handler_data(irq);
+        struct samsung_pin_bank *bank = eintd->bank;
         struct irq_chip *chip = irq_get_chip(irq);
         int eint_irq;
 
@@ -371,20 +328,20 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
         if (chip->irq_ack)
                 chip->irq_ack(&desc->irq_data);
 
-        eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
+        eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
         generic_handle_irq(eint_irq);
         chip->irq_unmask(&desc->irq_data);
         chained_irq_exit(chip, desc);
 }
 
-static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
-                                        struct irq_domain *domain)
+static inline void exynos_irq_demux_eint(unsigned long pend,
+                                                struct irq_domain *domain)
 {
         unsigned int irq;
 
         while (pend) {
                 irq = fls(pend) - 1;
-                generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
+                generic_handle_irq(irq_find_mapping(domain, irq));
                 pend &= ~(1 << irq);
         }
 }
@@ -393,18 +350,22 @@ static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_chip *chip = irq_get_chip(irq);
-        struct exynos_weint_data *eintd = irq_get_handler_data(irq);
-        struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
+        struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
+        struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
+        struct samsung_pin_ctrl *ctrl = d->ctrl;
         unsigned long pend;
         unsigned long mask;
+        int i;
 
         chained_irq_enter(chip, desc);
-        pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
-        mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8);
-        exynos_irq_demux_eint(16, pend & ~mask, eintd->domain);
-        pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
-        mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC);
-        exynos_irq_demux_eint(24, pend & ~mask, eintd->domain);
+
+        for (i = 0; i < eintd->nr_banks; ++i) {
+                struct samsung_pin_bank *b = eintd->banks[i];
+                pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset);
+                mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset);
+                exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
+        }
+
         chained_irq_exit(chip, desc);
 }
 
@@ -434,7 +395,11 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
         struct device *dev = d->dev;
         struct device_node *wkup_np = NULL;
         struct device_node *np;
+        struct samsung_pin_bank *bank;
         struct exynos_weint_data *weint_data;
+        struct exynos_muxed_weint_data *muxed_data;
+        unsigned int muxed_banks = 0;
+        unsigned int i;
         int idx, irq;
 
         for_each_child_of_node(dev->of_node, np) {
@@ -446,90 +411,124 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
         if (!wkup_np)
                 return -ENODEV;
 
-        d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
-                                &exynos_wkup_irqd_ops, d);
-        if (!d->wkup_irqd) {
-                dev_err(dev, "wakeup irq domain allocation failed\n");
-                return -ENXIO;
-        }
+        bank = d->ctrl->pin_banks;
+        for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
+                if (bank->eint_type != EINT_TYPE_WKUP)
+                        continue;
 
-        weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
-        if (!weint_data) {
-                dev_err(dev, "could not allocate memory for weint_data\n");
-                return -ENOMEM;
-        }
+                bank->irq_domain = irq_domain_add_linear(bank->of_node,
+                                bank->nr_pins, &exynos_wkup_irqd_ops, bank);
+                if (!bank->irq_domain) {
+                        dev_err(dev, "wkup irq domain add failed\n");
+                        return -ENXIO;
+                }
 
-        irq = irq_of_parse_and_map(wkup_np, 16);
-        if (irq) {
-                weint_data[16].domain = d->wkup_irqd;
-                irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
-                irq_set_handler_data(irq, &weint_data[16]);
-        } else {
-                dev_err(dev, "irq number for EINT16-32 not found\n");
-        }
+                if (!of_find_property(bank->of_node, "interrupts", NULL)) {
+                        bank->eint_type = EINT_TYPE_WKUP_MUX;
+                        ++muxed_banks;
+                        continue;
+                }
 
-        for (idx = 0; idx < 16; idx++) {
-                weint_data[idx].domain = d->wkup_irqd;
-                weint_data[idx].irq = idx;
+                weint_data = devm_kzalloc(dev, bank->nr_pins
+                                        * sizeof(*weint_data), GFP_KERNEL);
+                if (!weint_data) {
+                        dev_err(dev, "could not allocate memory for weint_data\n");
+                        return -ENOMEM;
+                }
 
-                irq = irq_of_parse_and_map(wkup_np, idx);
-                if (irq) {
+                for (idx = 0; idx < bank->nr_pins; ++idx) {
+                        irq = irq_of_parse_and_map(bank->of_node, idx);
+                        if (!irq) {
+                                dev_err(dev, "irq number for eint-%s-%d not found\n",
+                                                        bank->name, idx);
+                                continue;
+                        }
+                        weint_data[idx].irq = idx;
+                        weint_data[idx].bank = bank;
                         irq_set_handler_data(irq, &weint_data[idx]);
                         irq_set_chained_handler(irq, exynos_irq_eint0_15);
-                } else {
-                        dev_err(dev, "irq number for eint-%x not found\n", idx);
                 }
         }
+
+        if (!muxed_banks)
+                return 0;
+
+        irq = irq_of_parse_and_map(wkup_np, 0);
+        if (!irq) {
+                dev_err(dev, "irq number for muxed EINTs not found\n");
+                return 0;
+        }
+
+        muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
+                + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
+        if (!muxed_data) {
+                dev_err(dev, "could not allocate memory for muxed_data\n");
+                return -ENOMEM;
+        }
+
+        irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
+        irq_set_handler_data(irq, muxed_data);
+
+        bank = d->ctrl->pin_banks;
+        idx = 0;
+        for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
+                if (bank->eint_type != EINT_TYPE_WKUP_MUX)
+                        continue;
+
+                muxed_data->banks[idx++] = bank;
+        }
+        muxed_data->nr_banks = muxed_banks;
+
         return 0;
 }
 
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
-        EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
-        EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
-        EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
-        EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
-        EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
-        EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
-        EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
-        EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
-        EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
-        EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
-        EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
-        EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
-        EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
-        EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
-        EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
-        EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
+        EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
+        EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
+        EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
+        EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
+        EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
+        EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
+        EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
+        EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 };
 
 /* pin banks of exynos4210 pin-controller 1 */
 static struct samsung_pin_bank exynos4210_pin_banks1[] = {
-        EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
-        EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
-        EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
-        EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
-        EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
-        EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
-        EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
-        EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
-        EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
-        EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
-        EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
-        EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
-        EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
-        EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
-        EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
-        EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
-        EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
-        EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
-        EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
-        EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
+        EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
+        EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
+        EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
+        EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
+        EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
+        EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
+        EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 };
 
 /* pin banks of exynos4210 pin-controller 2 */
 static struct samsung_pin_bank exynos4210_pin_banks2[] = {
-        EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
+        EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 };
 
 /*
@@ -541,9 +540,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 /* pin-controller instance 0 data */
                 .pin_banks      = exynos4210_pin_banks0,
                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks0),
-                .base           = EXYNOS4210_GPIO_A0_START,
-                .nr_pins        = EXYNOS4210_GPIOA_NR_PINS,
-                .nr_gint        = EXYNOS4210_GPIOA_NR_GINT,
                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
@@ -554,10 +550,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 /* pin-controller instance 1 data */
                 .pin_banks      = exynos4210_pin_banks1,
                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks1),
-                .base           = EXYNOS4210_GPIOA_NR_PINS,
-                .nr_pins        = EXYNOS4210_GPIOB_NR_PINS,
-                .nr_gint        = EXYNOS4210_GPIOB_NR_GINT,
-                .nr_wint        = 32,
                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
@@ -572,9 +564,116 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 /* pin-controller instance 2 data */
                 .pin_banks      = exynos4210_pin_banks2,
                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks2),
-                .base           = EXYNOS4210_GPIOA_NR_PINS +
-                                        EXYNOS4210_GPIOB_NR_PINS,
-                .nr_pins        = EXYNOS4210_GPIOC_NR_PINS,
                 .label          = "exynos4210-gpio-ctrl2",
         },
 };
+
+/* pin banks of exynos4x12 pin-controller 0 */
+static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
+        EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
+        EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
+        EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
+        EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
+        EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
+        EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
+};
+
+/* pin banks of exynos4x12 pin-controller 1 */
+static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
+        EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
+        EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
+        EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
+        EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
+        EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
+        EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
+        EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
+        EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
+        EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
+        EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
+        EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
+        EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos4x12 pin-controller 2 */
+static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
+        EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
+};
+
+/* pin banks of exynos4x12 pin-controller 3 */
+static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
+        EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
+        {
+                /* pin-controller instance 0 data */
+                .pin_banks      = exynos4x12_pin_banks0,
+                .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks0),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos4x12-gpio-ctrl0",
+        }, {
+                /* pin-controller instance 1 data */
+                .pin_banks      = exynos4x12_pin_banks1,
+                .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks1),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
+                .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
+                .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .eint_wkup_init = exynos_eint_wkup_init,
+                .label          = "exynos4x12-gpio-ctrl1",
+        }, {
+                /* pin-controller instance 2 data */
+                .pin_banks      = exynos4x12_pin_banks2,
+                .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks2),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos4x12-gpio-ctrl2",
+        }, {
+                /* pin-controller instance 3 data */
+                .pin_banks      = exynos4x12_pin_banks3,
+                .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks3),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos4x12-gpio-ctrl3",
+        },
+};
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 31d0a06174e4..0a708890d8b4 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -17,125 +17,6 @@
  * (at your option) any later version.
  */
 
-#define EXYNOS_GPIO_START(__gpio)       ((__gpio##_START) + (__gpio##_NR))
-
-#define EXYNOS4210_GPIO_A0_NR   (8)
-#define EXYNOS4210_GPIO_A1_NR   (6)
-#define EXYNOS4210_GPIO_B_NR    (8)
-#define EXYNOS4210_GPIO_C0_NR   (5)
-#define EXYNOS4210_GPIO_C1_NR   (5)
-#define EXYNOS4210_GPIO_D0_NR   (4)
-#define EXYNOS4210_GPIO_D1_NR   (4)
-#define EXYNOS4210_GPIO_E0_NR   (5)
-#define EXYNOS4210_GPIO_E1_NR   (8)
-#define EXYNOS4210_GPIO_E2_NR   (6)
-#define EXYNOS4210_GPIO_E3_NR   (8)
-#define EXYNOS4210_GPIO_E4_NR   (8)
-#define EXYNOS4210_GPIO_F0_NR   (8)
-#define EXYNOS4210_GPIO_F1_NR   (8)
-#define EXYNOS4210_GPIO_F2_NR   (8)
-#define EXYNOS4210_GPIO_F3_NR   (6)
-#define EXYNOS4210_GPIO_J0_NR   (8)
-#define EXYNOS4210_GPIO_J1_NR   (5)
-#define EXYNOS4210_GPIO_K0_NR   (7)
-#define EXYNOS4210_GPIO_K1_NR   (7)
-#define EXYNOS4210_GPIO_K2_NR   (7)
-#define EXYNOS4210_GPIO_K3_NR   (7)
-#define EXYNOS4210_GPIO_L0_NR   (8)
-#define EXYNOS4210_GPIO_L1_NR   (3)
-#define EXYNOS4210_GPIO_L2_NR   (8)
-#define EXYNOS4210_GPIO_Y0_NR   (6)
-#define EXYNOS4210_GPIO_Y1_NR   (4)
-#define EXYNOS4210_GPIO_Y2_NR   (6)
-#define EXYNOS4210_GPIO_Y3_NR   (8)
-#define EXYNOS4210_GPIO_Y4_NR   (8)
-#define EXYNOS4210_GPIO_Y5_NR   (8)
-#define EXYNOS4210_GPIO_Y6_NR   (8)
-#define EXYNOS4210_GPIO_X0_NR   (8)
-#define EXYNOS4210_GPIO_X1_NR   (8)
-#define EXYNOS4210_GPIO_X2_NR   (8)
-#define EXYNOS4210_GPIO_X3_NR   (8)
-#define EXYNOS4210_GPIO_Z_NR    (7)
-
-enum exynos4210_gpio_xa_start {
-        EXYNOS4210_GPIO_A0_START        = 0,
-        EXYNOS4210_GPIO_A1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),
-        EXYNOS4210_GPIO_B_START         = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),
-        EXYNOS4210_GPIO_C0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),
-        EXYNOS4210_GPIO_C1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),
-        EXYNOS4210_GPIO_D0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),
-        EXYNOS4210_GPIO_D1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),
-        EXYNOS4210_GPIO_E0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),
-        EXYNOS4210_GPIO_E1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),
-        EXYNOS4210_GPIO_E2_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),
-        EXYNOS4210_GPIO_E3_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),
-        EXYNOS4210_GPIO_E4_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),
-        EXYNOS4210_GPIO_F0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),
-        EXYNOS4210_GPIO_F1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),
-        EXYNOS4210_GPIO_F2_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),
-        EXYNOS4210_GPIO_F3_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),
-};
-
-enum exynos4210_gpio_xb_start {
-        EXYNOS4210_GPIO_J0_START        = 0,
-        EXYNOS4210_GPIO_J1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),
-        EXYNOS4210_GPIO_K0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),
-        EXYNOS4210_GPIO_K1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),
-        EXYNOS4210_GPIO_K2_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),
-        EXYNOS4210_GPIO_K3_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),
-        EXYNOS4210_GPIO_L0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),
-        EXYNOS4210_GPIO_L1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),
-        EXYNOS4210_GPIO_L2_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),
-        EXYNOS4210_GPIO_Y0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),
-        EXYNOS4210_GPIO_Y1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),
-        EXYNOS4210_GPIO_Y2_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),
-        EXYNOS4210_GPIO_Y3_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),
-        EXYNOS4210_GPIO_Y4_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),
-        EXYNOS4210_GPIO_Y5_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),
-        EXYNOS4210_GPIO_Y6_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),
-        EXYNOS4210_GPIO_X0_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),
-        EXYNOS4210_GPIO_X1_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),
-        EXYNOS4210_GPIO_X2_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),
-        EXYNOS4210_GPIO_X3_START        = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),
-};
-
-enum exynos4210_gpio_xc_start {
-        EXYNOS4210_GPIO_Z_START         = 0,
-};
-
-#define EXYNOS4210_GPIO_A0_IRQ          EXYNOS4210_GPIO_A0_START
-#define EXYNOS4210_GPIO_A1_IRQ          EXYNOS4210_GPIO_A1_START
-#define EXYNOS4210_GPIO_B_IRQ           EXYNOS4210_GPIO_B_START
-#define EXYNOS4210_GPIO_C0_IRQ          EXYNOS4210_GPIO_C0_START
-#define EXYNOS4210_GPIO_C1_IRQ          EXYNOS4210_GPIO_C1_START
-#define EXYNOS4210_GPIO_D0_IRQ          EXYNOS4210_GPIO_D0_START
-#define EXYNOS4210_GPIO_D1_IRQ          EXYNOS4210_GPIO_D1_START
-#define EXYNOS4210_GPIO_E0_IRQ          EXYNOS4210_GPIO_E0_START
-#define EXYNOS4210_GPIO_E1_IRQ          EXYNOS4210_GPIO_E1_START
-#define EXYNOS4210_GPIO_E2_IRQ          EXYNOS4210_GPIO_E2_START
-#define EXYNOS4210_GPIO_E3_IRQ          EXYNOS4210_GPIO_E3_START
-#define EXYNOS4210_GPIO_E4_IRQ          EXYNOS4210_GPIO_E4_START
-#define EXYNOS4210_GPIO_F0_IRQ          EXYNOS4210_GPIO_F0_START
-#define EXYNOS4210_GPIO_F1_IRQ          EXYNOS4210_GPIO_F1_START
-#define EXYNOS4210_GPIO_F2_IRQ          EXYNOS4210_GPIO_F2_START
-#define EXYNOS4210_GPIO_F3_IRQ          EXYNOS4210_GPIO_F3_START
-#define EXYNOS4210_GPIO_J0_IRQ          EXYNOS4210_GPIO_J0_START
-#define EXYNOS4210_GPIO_J1_IRQ          EXYNOS4210_GPIO_J1_START
-#define EXYNOS4210_GPIO_K0_IRQ          EXYNOS4210_GPIO_K0_START
-#define EXYNOS4210_GPIO_K1_IRQ          EXYNOS4210_GPIO_K1_START
-#define EXYNOS4210_GPIO_K2_IRQ          EXYNOS4210_GPIO_K2_START
-#define EXYNOS4210_GPIO_K3_IRQ          EXYNOS4210_GPIO_K3_START
-#define EXYNOS4210_GPIO_L0_IRQ          EXYNOS4210_GPIO_L0_START
-#define EXYNOS4210_GPIO_L1_IRQ          EXYNOS4210_GPIO_L1_START
-#define EXYNOS4210_GPIO_L2_IRQ          EXYNOS4210_GPIO_L2_START
-#define EXYNOS4210_GPIO_Z_IRQ           EXYNOS4210_GPIO_Z_START
-
-#define EXYNOS4210_GPIOA_NR_PINS        EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
-#define EXYNOS4210_GPIOA_NR_GINT        EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
-#define EXYNOS4210_GPIOB_NR_PINS        EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)
-#define EXYNOS4210_GPIOB_NR_GINT        EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)
-#define EXYNOS4210_GPIOC_NR_PINS        EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)
-
 /* External GPIO and wakeup interrupt related definitions */
 #define EXYNOS_GPIO_ECON_OFFSET         0x700
 #define EXYNOS_GPIO_EMASK_OFFSET        0x900
@@ -165,11 +46,10 @@ enum exynos4210_gpio_xc_start {
 #define EXYNOS_EINT_MAX_PER_BANK        8
 #define EXYNOS_EINT_NR_WKUP_EINT
 
-#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id)          \
+#define EXYNOS_PIN_BANK_EINTN(pins, reg, id)            \
         {                                               \
                 .pctl_offset    = reg,                  \
-                .pin_base       = (__gpio##_START),     \
-                .nr_pins        = (__gpio##_NR),        \
+                .nr_pins        = pins,                 \
                 .func_width     = 4,                    \
                 .pud_width      = 2,                    \
                 .drv_width      = 2,                    \
@@ -179,40 +59,50 @@ enum exynos4210_gpio_xc_start {
                 .name           = id                    \
         }
 
-#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id)          \
+#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs)      \
         {                                               \
                 .pctl_offset    = reg,                  \
-                .pin_base       = (__gpio##_START),     \
-                .nr_pins        = (__gpio##_NR),        \
+                .nr_pins        = pins,                 \
                 .func_width     = 4,                    \
                 .pud_width      = 2,                    \
                 .drv_width      = 2,                    \
                 .conpdn_width   = 2,                    \
                 .pudpdn_width   = 2,                    \
                 .eint_type      = EINT_TYPE_GPIO,       \
-                .irq_base       = (__gpio##_IRQ),       \
+                .eint_offset    = offs,                 \
                 .name           = id                    \
         }
 
-/**
- * struct exynos_geint_data: gpio eint specific data for irq_chip callbacks.
- * @bank: pin bank from which this gpio interrupt originates.
- * @pin: pin number within the bank.
- * @eint_offset: offset to be added to the con/pend/mask register bank base.
- */
-struct exynos_geint_data {
-        struct samsung_pin_bank *bank;
-        u32                     pin;
-        u32                     eint_offset;
-};
+#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs)      \
+        {                                               \
+                .pctl_offset    = reg,                  \
+                .nr_pins        = pins,                 \
+                .func_width     = 4,                    \
+                .pud_width      = 2,                    \
+                .drv_width      = 2,                    \
+                .eint_type      = EINT_TYPE_WKUP,       \
+                .eint_offset    = offs,                 \
+                .name           = id                    \
+        }
 
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.
- * @domain: irq domain representing the external wakeup interrupts
  * @irq: interrupt number within the domain.
+ * @bank: bank responsible for this interrupt
  */
 struct exynos_weint_data {
-        struct irq_domain       *domain;
-        u32                     irq;
+        unsigned int irq;
+        struct samsung_pin_bank *bank;
+};
+
+/**
+ * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
+ * generated by the external wakeup interrupt controller.
+ * @nr_banks: count of banks being part of the mux
+ * @banks: array of banks being part of the mux
+ */
+struct exynos_muxed_weint_data {
+        unsigned int nr_banks;
+        struct samsung_pin_bank *banks[];
 };
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
new file mode 100644
index 000000000000..b8635f634e91
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -0,0 +1,919 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include "core.h"
+
+/* EXYNOS5440 GPIO and Pinctrl register offsets */
+#define GPIO_MUX                0x00
+#define GPIO_IE                 0x04
+#define GPIO_INT                0x08
+#define GPIO_TYPE               0x0C
+#define GPIO_VAL                0x10
+#define GPIO_OE                 0x14
+#define GPIO_IN                 0x18
+#define GPIO_PE                 0x1C
+#define GPIO_PS                 0x20
+#define GPIO_SR                 0x24
+#define GPIO_DS0                0x28
+#define GPIO_DS1                0x2C
+
+#define EXYNOS5440_MAX_PINS             23
+#define PIN_NAME_LENGTH         10
+
+#define GROUP_SUFFIX            "-grp"
+#define GSUFFIX_LEN             sizeof(GROUP_SUFFIX)
+#define FUNCTION_SUFFIX         "-mux"
+#define FSUFFIX_LEN             sizeof(FUNCTION_SUFFIX)
+
+/*
+ * pin configuration type and its value are packed together into a 16-bits.
+ * The upper 8-bits represent the configuration type and the lower 8-bits
+ * hold the value of the configuration type.
+ */
+#define PINCFG_TYPE_MASK                0xFF
+#define PINCFG_VALUE_SHIFT              8
+#define PINCFG_VALUE_MASK               (0xFF << PINCFG_VALUE_SHIFT)
+#define PINCFG_PACK(type, value)        (((value) << PINCFG_VALUE_SHIFT) | type)
+#define PINCFG_UNPACK_TYPE(cfg)         ((cfg) & PINCFG_TYPE_MASK)
+#define PINCFG_UNPACK_VALUE(cfg)        (((cfg) & PINCFG_VALUE_MASK) >> \
+                                                PINCFG_VALUE_SHIFT)
+
+/**
+ * enum pincfg_type - possible pin configuration types supported.
+ * @PINCFG_TYPE_PUD: Pull up/down configuration.
+ * @PINCFG_TYPE_DRV: Drive strength configuration.
+ * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
+ * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
+ */
+enum pincfg_type {
+        PINCFG_TYPE_PUD,
+        PINCFG_TYPE_DRV,
+        PINCFG_TYPE_SKEW_RATE,
+        PINCFG_TYPE_INPUT_TYPE
+};
+
+/**
+ * struct exynos5440_pin_group: represent group of pins for pincfg setting.
+ * @name: name of the pin group, used to lookup the group.
+ * @pins: the pins included in this group.
+ * @num_pins: number of pins included in this group.
+ */
+struct exynos5440_pin_group {
+        const char              *name;
+        const unsigned int      *pins;
+        u8                      num_pins;
+};
+
+/**
+ * struct exynos5440_pmx_func: represent a pin function.
+ * @name: name of the pin function, used to lookup the function.
+ * @groups: one or more names of pin groups that provide this function.
+ * @num_groups: number of groups included in @groups.
+ * @function: the function number to be programmed when selected.
+ */
+struct exynos5440_pmx_func {
+        const char              *name;
+        const char              **groups;
+        u8                      num_groups;
+        unsigned long           function;
+};
+
+/**
+ * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
+ * @reg_base: ioremapped based address of the register space.
+ * @gc: gpio chip registered with gpiolib.
+ * @pin_groups: list of pin groups parsed from device tree.
+ * @nr_groups: number of pin groups available.
+ * @pmx_functions: list of pin functions parsed from device tree.
+ * @nr_functions: number of pin functions available.
+ */
+struct exynos5440_pinctrl_priv_data {
+        void __iomem                    *reg_base;
+        struct gpio_chip                *gc;
+
+        const struct exynos5440_pin_group       *pin_groups;
+        unsigned int                    nr_groups;
+        const struct exynos5440_pmx_func        *pmx_functions;
+        unsigned int                    nr_functions;
+};
+
+/* list of all possible config options supported */
+struct pin_config {
+        char            *prop_cfg;
+        unsigned int    cfg_type;
+} pcfgs[] = {
+        { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
+        { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
+        { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
+        { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
+};
+
+/* check if the selector is a valid pin group selector */
+static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        return priv->nr_groups;
+}
+
+/* return the name of the group selected by the group selector */
+static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
+                                                unsigned selector)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        return priv->pin_groups[selector].name;
+}
+
+/* return the pin numbers associated with the specified group */
+static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
+                unsigned selector, const unsigned **pins, unsigned *num_pins)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        *pins = priv->pin_groups[selector].pins;
+        *num_pins = priv->pin_groups[selector].num_pins;
+        return 0;
+}
+
+/* create pinctrl_map entries by parsing device tree nodes */
+static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
+                        struct device_node *np, struct pinctrl_map **maps,
+                        unsigned *nmaps)
+{
+        struct device *dev = pctldev->dev;
+        struct pinctrl_map *map;
+        unsigned long *cfg = NULL;
+        char *gname, *fname;
+        int cfg_cnt = 0, map_cnt = 0, idx = 0;
+
+        /* count the number of config options specfied in the node */
+        for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
+                if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
+                        cfg_cnt++;
+
+        /*
+         * Find out the number of map entries to create. All the config options
+         * can be accomadated into a single config map entry.
+         */
+        if (cfg_cnt)
+                map_cnt = 1;
+        if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
+                map_cnt++;
+        if (!map_cnt) {
+                dev_err(dev, "node %s does not have either config or function "
+                                "configurations\n", np->name);
+                return -EINVAL;
+        }
+
+        /* Allocate memory for pin-map entries */
+        map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
+        if (!map) {
+                dev_err(dev, "could not alloc memory for pin-maps\n");
+                return -ENOMEM;
+        }
+        *nmaps = 0;
+
+        /*
+         * Allocate memory for pin group name. The pin group name is derived
+         * from the node name from which these map entries are be created.
+         */
+        gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
+        if (!gname) {
+                dev_err(dev, "failed to alloc memory for group name\n");
+                goto free_map;
+        }
+        sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
+
+        /*
+         * don't have config options? then skip over to creating function
+         * map entries.
+         */
+        if (!cfg_cnt)
+                goto skip_cfgs;
+
+        /* Allocate memory for config entries */
+        cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
+        if (!cfg) {
+                dev_err(dev, "failed to alloc memory for configs\n");
+                goto free_gname;
+        }
+
+        /* Prepare a list of config settings */
+        for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
+                u32 value;
+                if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
+                        cfg[cfg_cnt++] =
+                                PINCFG_PACK(pcfgs[idx].cfg_type, value);
+        }
+
+        /* create the config map entry */
+        map[*nmaps].data.configs.group_or_pin = gname;
+        map[*nmaps].data.configs.configs = cfg;
+        map[*nmaps].data.configs.num_configs = cfg_cnt;
+        map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+        *nmaps += 1;
+
+skip_cfgs:
+        /* create the function map entry */
+        if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
+                fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
+                if (!fname) {
+                        dev_err(dev, "failed to alloc memory for func name\n");
+                        goto free_cfg;
+                }
+                sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
+
+                map[*nmaps].data.mux.group = gname;
+                map[*nmaps].data.mux.function = fname;
+                map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+                *nmaps += 1;
+        }
+
+        *maps = map;
+        return 0;
+
+free_cfg:
+        kfree(cfg);
+free_gname:
+        kfree(gname);
+free_map:
+        kfree(map);
+        return -ENOMEM;
+}
+
+/* free the memory allocated to hold the pin-map table */
+static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
+                             struct pinctrl_map *map, unsigned num_maps)
+{
+        int idx;
+
+        for (idx = 0; idx < num_maps; idx++) {
+                if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
+                        kfree(map[idx].data.mux.function);
+                        if (!idx)
+                                kfree(map[idx].data.mux.group);
+                } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
+                        kfree(map[idx].data.configs.configs);
+                        if (!idx)
+                                kfree(map[idx].data.configs.group_or_pin);
+                }
+        };
+
+        kfree(map);
+}
+
+/* list of pinctrl callbacks for the pinctrl core */
+static struct pinctrl_ops exynos5440_pctrl_ops = {
+        .get_groups_count       = exynos5440_get_group_count,
+        .get_group_name         = exynos5440_get_group_name,
+        .get_group_pins         = exynos5440_get_group_pins,
+        .dt_node_to_map         = exynos5440_dt_node_to_map,
+        .dt_free_map            = exynos5440_dt_free_map,
+};
+
+/* check if the selector is a valid pin function selector */
+static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        return priv->nr_functions;
+}
+
+/* return the name of the pin function specified */
+static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
+                                                unsigned selector)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        return priv->pmx_functions[selector].name;
+}
+
+/* return the groups associated for the specified function selector */
+static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
+                unsigned selector, const char * const **groups,
+                unsigned * const num_groups)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        *groups = priv->pmx_functions[selector].groups;
+        *num_groups = priv->pmx_functions[selector].num_groups;
+        return 0;
+}
+
+/* enable or disable a pinmux function */
+static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+                                        unsigned group, bool enable)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+        void __iomem *base;
+        u32 function;
+        u32 data;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        base = priv->reg_base;
+        function = priv->pmx_functions[selector].function;
+
+        data = readl(base + GPIO_MUX);
+        if (enable)
+                data |= (1 << function);
+        else
+                data &= ~(1 << function);
+        writel(data, base + GPIO_MUX);
+}
+
+/* enable a specified pinmux by writing to registers */
+static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
+                                        unsigned group)
+{
+        exynos5440_pinmux_setup(pctldev, selector, group, true);
+        return 0;
+}
+
+/* disable a specified pinmux by writing to registers */
+static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
+                                        unsigned selector, unsigned group)
+{
+        exynos5440_pinmux_setup(pctldev, selector, group, false);
+}
+
+/*
+ * The calls to gpio_direction_output() and gpio_direction_input()
+ * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
+ * function called from the gpiolib interface).
+ */
+static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+                struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+        return 0;
+}
+
+/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
+static struct pinmux_ops exynos5440_pinmux_ops = {
+        .get_functions_count    = exynos5440_get_functions_count,
+        .get_function_name      = exynos5440_pinmux_get_fname,
+        .get_function_groups    = exynos5440_pinmux_get_groups,
+        .enable                 = exynos5440_pinmux_enable,
+        .disable                = exynos5440_pinmux_disable,
+        .gpio_set_direction     = exynos5440_pinmux_gpio_set_direction,
+};
+
+/* set the pin config settings for a specified pin */
+static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+                                unsigned long config)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+        void __iomem *base;
+        enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
+        u32 cfg_value = PINCFG_UNPACK_VALUE(config);
+        u32 data;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        base = priv->reg_base;
+
+        switch (cfg_type) {
+        case PINCFG_TYPE_PUD:
+                /* first set pull enable/disable bit */
+                data = readl(base + GPIO_PE);
+                data &= ~(1 << pin);
+                if (cfg_value)
+                        data |= (1 << pin);
+                writel(data, base + GPIO_PE);
+
+                /* then set pull up/down bit */
+                data = readl(base + GPIO_PS);
+                data &= ~(1 << pin);
+                if (cfg_value == 2)
+                        data |= (1 << pin);
+                writel(data, base + GPIO_PS);
+                break;
+
+        case PINCFG_TYPE_DRV:
+                /* set the first bit of the drive strength */
+                data = readl(base + GPIO_DS0);
+                data &= ~(1 << pin);
+                data |= ((cfg_value & 1) << pin);
+                writel(data, base + GPIO_DS0);
+                cfg_value >>= 1;
+
+                /* set the second bit of the driver strength */
+                data = readl(base + GPIO_DS1);
+                data &= ~(1 << pin);
+                data |= ((cfg_value & 1) << pin);
+                writel(data, base + GPIO_DS1);
+                break;
+        case PINCFG_TYPE_SKEW_RATE:
+                data = readl(base + GPIO_SR);
+                data &= ~(1 << pin);
+                data |= ((cfg_value & 1) << pin);
+                writel(data, base + GPIO_SR);
+                break;
+        case PINCFG_TYPE_INPUT_TYPE:
+                data = readl(base + GPIO_TYPE);
+                data &= ~(1 << pin);
+                data |= ((cfg_value & 1) << pin);
+                writel(data, base + GPIO_TYPE);
+                break;
+        default:
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/* get the pin config settings for a specified pin */
+static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+                                        unsigned long *config)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+        void __iomem *base;
+        enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
+        u32 data;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        base = priv->reg_base;
+
+        switch (cfg_type) {
+        case PINCFG_TYPE_PUD:
+                data = readl(base + GPIO_PE);
+                data = (data >> pin) & 1;
+                if (!data)
+                        *config = 0;
+                else
+                        *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
+                break;
+        case PINCFG_TYPE_DRV:
+                data = readl(base + GPIO_DS0);
+                data = (data >> pin) & 1;
+                *config = data;
+                data = readl(base + GPIO_DS1);
+                data = (data >> pin) & 1;
+                *config |= (data << 1);
+                break;
+        case PINCFG_TYPE_SKEW_RATE:
+                data = readl(base + GPIO_SR);
+                *config = (data >> pin) & 1;
+                break;
+        case PINCFG_TYPE_INPUT_TYPE:
+                data = readl(base + GPIO_TYPE);
+                *config = (data >> pin) & 1;
+                break;
+        default:
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/* set the pin config settings for a specified pin group */
+static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
+                        unsigned group, unsigned long config)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+        const unsigned int *pins;
+        unsigned int cnt;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        pins = priv->pin_groups[group].pins;
+
+        for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
+                exynos5440_pinconf_set(pctldev, pins[cnt], config);
+
+        return 0;
+}
+
+/* get the pin config settings for a specified pin group */
+static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
+                                unsigned int group, unsigned long *config)
+{
+        struct exynos5440_pinctrl_priv_data *priv;
+        const unsigned int *pins;
+
+        priv = pinctrl_dev_get_drvdata(pctldev);
+        pins = priv->pin_groups[group].pins;
+        exynos5440_pinconf_get(pctldev, pins[0], config);
+        return 0;
+}
+
+/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
+static struct pinconf_ops exynos5440_pinconf_ops = {
+        .pin_config_get         = exynos5440_pinconf_get,
+        .pin_config_set         = exynos5440_pinconf_set,
+        .pin_config_group_get   = exynos5440_pinconf_group_get,
+        .pin_config_group_set   = exynos5440_pinconf_group_set,
+};
+
+/* gpiolib gpio_set callback function */
+static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+        struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+        void __iomem *base = priv->reg_base;
+        u32 data;
+
+        data = readl(base + GPIO_VAL);
+        data &= ~(1 << offset);
+        if (value)
+                data |= 1 << offset;
+        writel(data, base + GPIO_VAL);
+}
+
+/* gpiolib gpio_get callback function */
+static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+        struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+        void __iomem *base = priv->reg_base;
+        u32 data;
+
+        data = readl(base + GPIO_IN);
+        data >>= offset;
+        data &= 1;
+        return data;
+}
+
+/* gpiolib gpio_direction_input callback function */
+static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+        struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+        void __iomem *base = priv->reg_base;
+        u32 data;
+
+        /* first disable the data output enable on this pin */
+        data = readl(base + GPIO_OE);
+        data &= ~(1 << offset);
+        writel(data, base + GPIO_OE);
+
+        /* now enable input on this pin */
+        data =  readl(base + GPIO_IE);
+        data |= 1 << offset;
+        writel(data, base + GPIO_IE);
+        return 0;
+}
+
+/* gpiolib gpio_direction_output callback function */
+static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+                                                        int value)
+{
+        struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+        void __iomem *base = priv->reg_base;
+        u32 data;
+
+        exynos5440_gpio_set(gc, offset, value);
+
+        /* first disable the data input enable on this pin */
+        data = readl(base + GPIO_IE);
+        data &= ~(1 << offset);
+        writel(data, base + GPIO_IE);
+
+        /* now enable output on this pin */
+        data =  readl(base + GPIO_OE);
+        data |= 1 << offset;
+        writel(data, base + GPIO_OE);
+        return 0;
+}
+
+/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
+static int __init exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
+                        struct device_node *cfg_np, unsigned int **pin_list,
+                        unsigned int *npins)
+{
+        struct device *dev = &pdev->dev;
+        struct property *prop;
+
+        prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
+        if (!prop)
+                return -ENOENT;
+
+        *npins = prop->length / sizeof(unsigned long);
+        if (!*npins) {
+                dev_err(dev, "invalid pin list in %s node", cfg_np->name);
+                return -EINVAL;
+        }
+
+        *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
+        if (!*pin_list) {
+                dev_err(dev, "failed to allocate memory for pin list\n");
+                return -ENOMEM;
+        }
+
+        return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
+                        *pin_list, *npins);
+}
+
+/*
+ * Parse the information about all the available pin groups and pin functions
+ * from device node of the pin-controller.
+ */
+static int __init exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
+                                struct exynos5440_pinctrl_priv_data *priv)
+{
+        struct device *dev = &pdev->dev;
+        struct device_node *dev_np = dev->of_node;
+        struct device_node *cfg_np;
+        struct exynos5440_pin_group *groups, *grp;
+        struct exynos5440_pmx_func *functions, *func;
+        unsigned *pin_list;
+        unsigned int npins, grp_cnt, func_idx = 0;
+        char *gname, *fname;
+        int ret;
+
+        grp_cnt = of_get_child_count(dev_np);
+        if (!grp_cnt)
+                return -EINVAL;
+
+        groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
+        if (!groups) {
+                dev_err(dev, "failed allocate memory for ping group list\n");
+                return -EINVAL;
+        }
+        grp = groups;
+
+        functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
+        if (!functions) {
+                dev_err(dev, "failed to allocate memory for function list\n");
+                return -EINVAL;
+        }
+        func = functions;
+
+        /*
+         * Iterate over all the child nodes of the pin controller node
+         * and create pin groups and pin function lists.
+         */
+        for_each_child_of_node(dev_np, cfg_np) {
+                u32 function;
+
+                ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
+                                        &pin_list, &npins);
+                if (ret)
+                        return ret;
+
+                /* derive pin group name from the node name */
+                gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
+                                        GFP_KERNEL);
+                if (!gname) {
+                        dev_err(dev, "failed to alloc memory for group name\n");
+                        return -ENOMEM;
+                }
+                sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
+
+                grp->name = gname;
+                grp->pins = pin_list;
+                grp->num_pins = npins;
+                grp++;
+
+                ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
+                                                &function);
+                if (ret)
+                        continue;
+
+                /* derive function name from the node name */
+                fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
+                                        GFP_KERNEL);
+                if (!fname) {
+                        dev_err(dev, "failed to alloc memory for func name\n");
+                        return -ENOMEM;
+                }
+                sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
+
+                func->name = fname;
+                func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
+                if (!func->groups) {
+                        dev_err(dev, "failed to alloc memory for group list "
+                                        "in pin function");
+                        return -ENOMEM;
+                }
+                func->groups[0] = gname;
+                func->num_groups = 1;
+                func->function = function;
+                func++;
+                func_idx++;
+        }
+
+        priv->pin_groups = groups;
+        priv->nr_groups = grp_cnt;
+        priv->pmx_functions = functions;
+        priv->nr_functions = func_idx;
+        return 0;
+}
+
+/* register the pinctrl interface with the pinctrl subsystem */
+static int __init exynos5440_pinctrl_register(struct platform_device *pdev,
+                                struct exynos5440_pinctrl_priv_data *priv)
+{
+        struct device *dev = &pdev->dev;
+        struct pinctrl_desc *ctrldesc;
+        struct pinctrl_dev *pctl_dev;
+        struct pinctrl_pin_desc *pindesc, *pdesc;
+        struct pinctrl_gpio_range grange;
+        char *pin_names;
+        int pin, ret;
+
+        ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
+        if (!ctrldesc) {
+                dev_err(dev, "could not allocate memory for pinctrl desc\n");
+                return -ENOMEM;
+        }
+
+        ctrldesc->name = "exynos5440-pinctrl";
+        ctrldesc->owner = THIS_MODULE;
+        ctrldesc->pctlops = &exynos5440_pctrl_ops;
+        ctrldesc->pmxops = &exynos5440_pinmux_ops;
+        ctrldesc->confops = &exynos5440_pinconf_ops;
+
+        pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
+                                EXYNOS5440_MAX_PINS, GFP_KERNEL);
+        if (!pindesc) {
+                dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
+                return -ENOMEM;
+        }
+        ctrldesc->pins = pindesc;
+        ctrldesc->npins = EXYNOS5440_MAX_PINS;
+
+        /* dynamically populate the pin number and pin name for pindesc */
+        for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
+                pdesc->number = pin;
+
+        /*
+         * allocate space for storing the dynamically generated names for all
+         * the pins which belong to this pin-controller.
+         */
+        pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
+                                        ctrldesc->npins, GFP_KERNEL);
+        if (!pin_names) {
+                dev_err(&pdev->dev, "mem alloc for pin names failed\n");
+                return -ENOMEM;
+        }
+
+        /* for each pin, set the name of the pin */
+        for (pin = 0; pin < ctrldesc->npins; pin++) {
+                sprintf(pin_names, "gpio%02d", pin);
+                pdesc = pindesc + pin;
+                pdesc->name = pin_names;
+                pin_names += PIN_NAME_LENGTH;
+        }
+
+        ret = exynos5440_pinctrl_parse_dt(pdev, priv);
+        if (ret)
+                return ret;
+
+        pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
+        if (!pctl_dev) {
+                dev_err(&pdev->dev, "could not register pinctrl driver\n");
+                return -EINVAL;
+        }
+
+        grange.name = "exynos5440-pctrl-gpio-range";
+        grange.id = 0;
+        grange.base = 0;
+        grange.npins = EXYNOS5440_MAX_PINS;
+        grange.gc = priv->gc;
+        pinctrl_add_gpio_range(pctl_dev, &grange);
+        return 0;
+}
+
+/* register the gpiolib interface with the gpiolib subsystem */
+static int __init exynos5440_gpiolib_register(struct platform_device *pdev,
+                                struct exynos5440_pinctrl_priv_data *priv)
+{
+        struct gpio_chip *gc;
+        int ret;
+
+        gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
+        if (!gc) {
+                dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
+                return -ENOMEM;
+        }
+
+        priv->gc = gc;
+        gc->base = 0;
+        gc->ngpio = EXYNOS5440_MAX_PINS;
+        gc->dev = &pdev->dev;
+        gc->set = exynos5440_gpio_set;
+        gc->get = exynos5440_gpio_get;
+        gc->direction_input = exynos5440_gpio_direction_input;
+        gc->direction_output = exynos5440_gpio_direction_output;
+        gc->label = "gpiolib-exynos5440";
+        gc->owner = THIS_MODULE;
+        ret = gpiochip_add(gc);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
+                                        "code: %d\n", gc->label, ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+/* unregister the gpiolib interface with the gpiolib subsystem */
+static int __init exynos5440_gpiolib_unregister(struct platform_device *pdev,
+                                struct exynos5440_pinctrl_priv_data *priv)
+{
+        int ret = gpiochip_remove(priv->gc);
+        if (ret) {
+                dev_err(&pdev->dev, "gpio chip remove failed\n");
+                return ret;
+        }
+        return 0;
+}
+
+static int __devinit exynos5440_pinctrl_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct exynos5440_pinctrl_priv_data *priv;
+        struct resource *res;
+        int ret;
+
+        if (!dev->of_node) {
+                dev_err(dev, "device tree node not found\n");
+                return -ENODEV;
+        }
+
+        priv = devm_kzalloc(dev, sizeof(priv), GFP_KERNEL);
+        if (!priv) {
+                dev_err(dev, "could not allocate memory for private data\n");
+                return -ENOMEM;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(dev, "cannot find IO resource\n");
+                return -ENOENT;
+        }
+
+        priv->reg_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!priv->reg_base) {
+                dev_err(dev, "ioremap failed\n");
+                return -ENODEV;
+        }
+
+        ret = exynos5440_gpiolib_register(pdev, priv);
+        if (ret)
+                return ret;
+
+        ret = exynos5440_pinctrl_register(pdev, priv);
+        if (ret) {
+                exynos5440_gpiolib_unregister(pdev, priv);
+                return ret;
+        }
+
+        platform_set_drvdata(pdev, priv);
+        dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
+        return 0;
+}
+
+static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
+        { .compatible = "samsung,exynos5440-pinctrl" },
+        {},
+};
+MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
+
+static struct platform_driver exynos5440_pinctrl_driver = {
+        .probe          = exynos5440_pinctrl_probe,
+        .driver = {
+                .name   = "exynos5440-pinctrl",
+                .owner  = THIS_MODULE,
+                .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
+        },
+};
+
+static int __init exynos5440_pinctrl_drv_register(void)
+{
+        return platform_driver_register(&exynos5440_pinctrl_driver);
+}
+postcore_initcall(exynos5440_pinctrl_drv_register);
+
+static void __exit exynos5440_pinctrl_drv_unregister(void)
+{
+        platform_driver_unregister(&exynos5440_pinctrl_driver);
+}
+module_exit(exynos5440_pinctrl_drv_unregister);
+
+MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
+MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 861cd5f04d5e..8f31b656c4e9 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
+#include <linux/irqdomain.h>
 
 #include "core.h"
 #include "pinctrl-samsung.h"
@@ -46,6 +47,13 @@ struct pin_config {
         { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
 };
 
+static unsigned int pin_base;
+
+static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
+{
+        return container_of(gc, struct samsung_pin_bank, gpio_chip);
+}
+
 /* check if the selector is a valid pin group selector */
 static int samsung_get_group_count(struct pinctrl_dev *pctldev)
 {
@@ -250,14 +258,12 @@ static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev,
  * given a pin number that is local to a pin controller, find out the pin bank
  * and the register base of the pin bank.
  */
-static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin,
-                        void __iomem **reg, u32 *offset,
+static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
+                        unsigned pin, void __iomem **reg, u32 *offset,
                         struct samsung_pin_bank **bank)
 {
-        struct samsung_pinctrl_drv_data *drvdata;
         struct samsung_pin_bank *b;
 
-        drvdata = dev_get_drvdata(gc->dev);
         b = drvdata->ctrl->pin_banks;
 
         while ((pin >= b->pin_base) &&
@@ -292,7 +298,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
          * pin function number in the config register.
          */
         for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
-                pin_to_reg_bank(drvdata->gc, pins[cnt] - drvdata->ctrl->base,
+                pin_to_reg_bank(drvdata, pins[cnt] - drvdata->ctrl->base,
                                 &reg, &pin_offset, &bank);
                 mask = (1 << bank->func_width) - 1;
                 shift = pin_offset * bank->func_width;
@@ -329,10 +335,16 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
                 struct pinctrl_gpio_range *range, unsigned offset, bool input)
 {
         struct samsung_pin_bank *bank;
+        struct samsung_pinctrl_drv_data *drvdata;
         void __iomem *reg;
         u32 data, pin_offset, mask, shift;
 
-        pin_to_reg_bank(range->gc, offset, &reg, &pin_offset, &bank);
+        bank = gc_to_pin_bank(range->gc);
+        drvdata = pinctrl_dev_get_drvdata(pctldev);
+
+        pin_offset = offset - bank->pin_base;
+        reg = drvdata->virt_base + bank->pctl_offset;
+
         mask = (1 << bank->func_width) - 1;
         shift = pin_offset * bank->func_width;
 
@@ -366,7 +378,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
         u32 cfg_value, cfg_reg;
 
         drvdata = pinctrl_dev_get_drvdata(pctldev);
-        pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg_base,
+        pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, &reg_base,
                                         &pin_offset, &bank);
 
         switch (cfg_type) {
@@ -391,6 +403,9 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
                 return -EINVAL;
         }
 
+        if (!width)
+                return -EINVAL;
+
         mask = (1 << width) - 1;
         shift = pin_offset * width;
         data = readl(reg_base + cfg_reg);
@@ -463,14 +478,16 @@ static struct pinconf_ops samsung_pinconf_ops = {
 /* gpiolib gpio_set callback function */
 static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 {
+        struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
         void __iomem *reg;
-        u32 pin_offset, data;
+        u32 data;
+
+        reg = bank->drvdata->virt_base + bank->pctl_offset;
 
-        pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
         data = readl(reg + DAT_REG);
-        data &= ~(1 << pin_offset);
+        data &= ~(1 << offset);
         if (value)
-                data |= 1 << pin_offset;
+                data |= 1 << offset;
         writel(data, reg + DAT_REG);
 }
 
@@ -478,11 +495,13 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
 {
         void __iomem *reg;
-        u32 pin_offset, data;
+        u32 data;
+        struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
+
+        reg = bank->drvdata->virt_base + bank->pctl_offset;
 
-        pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
         data = readl(reg + DAT_REG);
-        data >>= pin_offset;
+        data >>= offset;
         data &= 1;
         return data;
 }
@@ -510,6 +529,23 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
 }
 
 /*
+ * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
+ * and a virtual IRQ, if not already present.
+ */
+static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+        struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
+        unsigned int virq;
+
+        if (!bank->irq_domain)
+                return -ENXIO;
+
+        virq = irq_create_mapping(bank->irq_domain, offset);
+
+        return (virq) ? : -ENXIO;
+}
+
+/*
  * Parse the pin names listed in the 'samsung,pins' property and convert it
  * into a list of gpio numbers are create a pin group from it.
  */
@@ -524,7 +560,7 @@ static int __devinit samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
         const char *pin_name;
 
         *npins = of_property_count_strings(cfg_np, "samsung,pins");
-        if (*npins < 0) {
+        if (IS_ERR_VALUE(*npins)) {
                 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
                 return -EINVAL;
         }
@@ -597,7 +633,7 @@ static int __devinit samsung_pinctrl_parse_dt(struct platform_device *pdev,
          */
         for_each_child_of_node(dev_np, cfg_np) {
                 u32 function;
-                if (of_find_property(cfg_np, "interrupt-controller", NULL))
+                if (!of_find_property(cfg_np, "samsung,pins", NULL))
                         continue;
 
                 ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np,
@@ -712,12 +748,16 @@ static int __devinit samsung_pinctrl_register(struct platform_device *pdev,
                 return -EINVAL;
         }
 
-        drvdata->grange.name = "samsung-pctrl-gpio-range";
-        drvdata->grange.id = 0;
-        drvdata->grange.base = drvdata->ctrl->base;
-        drvdata->grange.npins = drvdata->ctrl->nr_pins;
-        drvdata->grange.gc = drvdata->gc;
-        pinctrl_add_gpio_range(drvdata->pctl_dev, &drvdata->grange);
+        for (bank = 0; bank < drvdata->ctrl->nr_banks; ++bank) {
+                pin_bank = &drvdata->ctrl->pin_banks[bank];
+                pin_bank->grange.name = pin_bank->name;
+                pin_bank->grange.id = bank;
+                pin_bank->grange.pin_base = pin_bank->pin_base;
+                pin_bank->grange.base = pin_bank->gpio_chip.base;
+                pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
+                pin_bank->grange.gc = &pin_bank->gpio_chip;
+                pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
+        }
 
         ret = samsung_pinctrl_parse_dt(pdev, drvdata);
         if (ret) {
@@ -728,68 +768,117 @@ static int __devinit samsung_pinctrl_register(struct platform_device *pdev,
         return 0;
 }
 
+static const struct gpio_chip samsung_gpiolib_chip = {
+        .set = samsung_gpio_set,
+        .get = samsung_gpio_get,
+        .direction_input = samsung_gpio_direction_input,
+        .direction_output = samsung_gpio_direction_output,
+        .to_irq = samsung_gpio_to_irq,
+        .owner = THIS_MODULE,
+};
+
 /* register the gpiolib interface with the gpiolib subsystem */
 static int __devinit samsung_gpiolib_register(struct platform_device *pdev,
                                 struct samsung_pinctrl_drv_data *drvdata)
 {
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        struct samsung_pin_bank *bank = ctrl->pin_banks;
         struct gpio_chip *gc;
         int ret;
-
-        gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
-        if (!gc) {
-                dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
-                return -ENOMEM;
-        }
-
-        drvdata->gc = gc;
-        gc->base = drvdata->ctrl->base;
-        gc->ngpio = drvdata->ctrl->nr_pins;
-        gc->dev = &pdev->dev;
-        gc->set = samsung_gpio_set;
-        gc->get = samsung_gpio_get;
-        gc->direction_input = samsung_gpio_direction_input;
-        gc->direction_output = samsung_gpio_direction_output;
-        gc->label = drvdata->ctrl->label;
-        gc->owner = THIS_MODULE;
-        ret = gpiochip_add(gc);
-        if (ret) {
-                dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
-                                        "code: %d\n", gc->label, ret);
-                return ret;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+                bank->gpio_chip = samsung_gpiolib_chip;
+
+                gc = &bank->gpio_chip;
+                gc->base = ctrl->base + bank->pin_base;
+                gc->ngpio = bank->nr_pins;
+                gc->dev = &pdev->dev;
+                gc->of_node = bank->of_node;
+                gc->label = bank->name;
+
+                ret = gpiochip_add(gc);
+                if (ret) {
+                        dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
+                                                        gc->label, ret);
+                        goto fail;
+                }
         }
 
         return 0;
+
+fail:
+        for (--i, --bank; i >= 0; --i, --bank)
+                if (gpiochip_remove(&bank->gpio_chip))
+                        dev_err(&pdev->dev, "gpio chip %s remove failed\n",
+                                                        bank->gpio_chip.label);
+        return ret;
 }
 
 /* unregister the gpiolib interface with the gpiolib subsystem */
 static int __devinit samsung_gpiolib_unregister(struct platform_device *pdev,
                                 struct samsung_pinctrl_drv_data *drvdata)
 {
-        int ret = gpiochip_remove(drvdata->gc);
-        if (ret) {
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        struct samsung_pin_bank *bank = ctrl->pin_banks;
+        int ret = 0;
+        int i;
+
+        for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank)
+                ret = gpiochip_remove(&bank->gpio_chip);
+
+        if (ret)
                 dev_err(&pdev->dev, "gpio chip remove failed\n");
-                return ret;
-        }
-        return 0;
+
+        return ret;
 }
 
 static const struct of_device_id samsung_pinctrl_dt_match[];
 
 /* retrieve the soc specific data */
 static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
+                                struct samsung_pinctrl_drv_data *d,
                                 struct platform_device *pdev)
 {
         int id;
         const struct of_device_id *match;
-        const struct device_node *node = pdev->dev.of_node;
+        struct device_node *node = pdev->dev.of_node;
+        struct device_node *np;
+        struct samsung_pin_ctrl *ctrl;
+        struct samsung_pin_bank *bank;
+        int i;
 
-        id = of_alias_get_id(pdev->dev.of_node, "pinctrl");
+        id = of_alias_get_id(node, "pinctrl");
         if (id < 0) {
                 dev_err(&pdev->dev, "failed to get alias id\n");
                 return NULL;
         }
         match = of_match_node(samsung_pinctrl_dt_match, node);
-        return (struct samsung_pin_ctrl *)match->data + id;
+        ctrl = (struct samsung_pin_ctrl *)match->data + id;
+
+        bank = ctrl->pin_banks;
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+                bank->drvdata = d;
+                bank->pin_base = ctrl->nr_pins;
+                ctrl->nr_pins += bank->nr_pins;
+        }
+
+        for_each_child_of_node(node, np) {
+                if (!of_find_property(np, "gpio-controller", NULL))
+                        continue;
+                bank = ctrl->pin_banks;
+                for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+                        if (!strcmp(bank->name, np->name)) {
+                                bank->of_node = np;
+                                break;
+                        }
+                }
+        }
+
+        ctrl->base = pin_base;
+        pin_base += ctrl->nr_pins;
+
+        return ctrl;
 }
 
 static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
@@ -805,18 +894,18 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
                 return -ENODEV;
         }
 
-        ctrl = samsung_pinctrl_get_soc_data(pdev);
-        if (!ctrl) {
-                dev_err(&pdev->dev, "driver data not available\n");
-                return -EINVAL;
-        }
-
         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
         if (!drvdata) {
                 dev_err(dev, "failed to allocate memory for driver's "
                                 "private data\n");
                 return -ENOMEM;
         }
+
+        ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev);
+        if (!ctrl) {
+                dev_err(&pdev->dev, "driver data not available\n");
+                return -EINVAL;
+        }
         drvdata->ctrl = ctrl;
         drvdata->dev = dev;
 
@@ -858,6 +947,8 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
 static const struct of_device_id samsung_pinctrl_dt_match[] = {
         { .compatible = "samsung,pinctrl-exynos4210",
                 .data = (void *)exynos4210_pin_ctrl },
+        { .compatible = "samsung,pinctrl-exynos4x12",
+                .data = (void *)exynos4x12_pin_ctrl },
         {},
 };
 MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index b8956934cda6..5addfd16e3cc 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -23,6 +23,8 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/machine.h>
 
+#include <linux/gpio.h>
+
 /* register offsets within a pin bank */
 #define DAT_REG         0x4
 #define PUD_REG         0x8
@@ -64,6 +66,7 @@ enum pincfg_type {
  * @EINT_TYPE_NONE: bank does not support external interrupts
  * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
  * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
+ * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
  *
  * Samsung GPIO controller groups all the available pins into banks. The pins
  * in a pin bank can support external gpio interrupts or external wakeup
@@ -76,6 +79,7 @@ enum eint_type {
         EINT_TYPE_NONE,
         EINT_TYPE_GPIO,
         EINT_TYPE_WKUP,
+        EINT_TYPE_WKUP_MUX,
 };
 
 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
@@ -109,8 +113,12 @@ struct samsung_pinctrl_drv_data;
  * @conpdn_width: width of the sleep mode function selector bin field.
  * @pudpdn_width: width of the sleep mode pull up/down selector bit field.
  * @eint_type: type of the external interrupt supported by the bank.
- * @irq_base: starting controller local irq number of the bank.
  * @name: name to be prefixed for each pin in this pin bank.
+ * @of_node: OF node of the bank.
+ * @drvdata: link to controller driver data
+ * @irq_domain: IRQ domain of the bank.
+ * @gpio_chip: GPIO chip of the bank.
+ * @grange: linux gpio pin range supported by this bank.
  */
 struct samsung_pin_bank {
         u32             pctl_offset;
@@ -122,8 +130,13 @@ struct samsung_pin_bank {
         u8              conpdn_width;
         u8              pudpdn_width;
         enum eint_type  eint_type;
-        u32             irq_base;
+        u32             eint_offset;
         char            *name;
+        struct device_node *of_node;
+        struct samsung_pinctrl_drv_data *drvdata;
+        struct irq_domain *irq_domain;
+        struct gpio_chip gpio_chip;
+        struct pinctrl_gpio_range grange;
 };
 
 /**
@@ -132,8 +145,6 @@ struct samsung_pin_bank {
  * @nr_banks: number of pin banks.
  * @base: starting system wide pin number.
  * @nr_pins: number of pins supported by the controller.
- * @nr_gint: number of external gpio interrupts supported.
- * @nr_wint: number of external wakeup interrupts supported.
  * @geint_con: offset of the ext-gpio controller registers.
  * @geint_mask: offset of the ext-gpio interrupt mask registers.
  * @geint_pend: offset of the ext-gpio interrupt pending registers.
@@ -153,8 +164,6 @@ struct samsung_pin_ctrl {
 
         u32             base;
         u32             nr_pins;
-        u32             nr_gint;
-        u32             nr_wint;
 
         u32             geint_con;
         u32             geint_mask;
@@ -183,8 +192,6 @@ struct samsung_pin_ctrl {
  * @nr_groups: number of such pin groups.
  * @pmx_functions: list of pin functions available to the driver.
  * @nr_function: number of such pin functions.
- * @gc: gpio_chip instance registered with gpiolib.
- * @grange: linux gpio pin range supported by this controller.
  */
 struct samsung_pinctrl_drv_data {
         void __iomem                    *virt_base;
@@ -199,12 +206,6 @@ struct samsung_pinctrl_drv_data {
         unsigned int                    nr_groups;
         const struct samsung_pmx_func   *pmx_functions;
         unsigned int                    nr_functions;
-
-        struct irq_domain               *gpio_irqd;
-        struct irq_domain               *wkup_irqd;
-
-        struct gpio_chip                *gc;
-        struct pinctrl_gpio_range       grange;
 };
 
 /**
@@ -235,5 +236,6 @@ struct samsung_pmx_func {
 
 /* list of all exported SoC specific data */
 extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
+extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 
 #endif /* __PINCTRL_SAMSUNG_H */
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 07e9fb4f8041..b3dc44146ca0 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -361,3 +361,89 @@ int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
         return sh_clk_div_register_ops(clks, nr, table,
                                        &sh_clk_div4_reparent_clk_ops);
 }
+
+/* FSI-DIV */
+static unsigned long fsidiv_recalc(struct clk *clk)
+{
+        u32 value;
+
+        value = __raw_readl(clk->mapping->base);
+
+        value >>= 16;
+        if (value < 2)
+                return clk->parent->rate;
+
+        return clk->parent->rate / value;
+}
+
+static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_rate_div_range_round(clk, 1, 0xffff, rate);
+}
+
+static void fsidiv_disable(struct clk *clk)
+{
+        __raw_writel(0, clk->mapping->base);
+}
+
+static int fsidiv_enable(struct clk *clk)
+{
+        u32 value;
+
+        value  = __raw_readl(clk->mapping->base) >> 16;
+        if (value < 2)
+                return 0;
+
+        __raw_writel((value << 16) | 0x3, clk->mapping->base);
+
+        return 0;
+}
+
+static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val;
+        int idx;
+
+        idx = (clk->parent->rate / rate) & 0xffff;
+        if (idx < 2)
+                __raw_writel(0, clk->mapping->base);
+        else
+                __raw_writel(idx << 16, clk->mapping->base);
+
+        return 0;
+}
+
+static struct sh_clk_ops fsidiv_clk_ops = {
+        .recalc         = fsidiv_recalc,
+        .round_rate     = fsidiv_round_rate,
+        .set_rate       = fsidiv_set_rate,
+        .enable         = fsidiv_enable,
+        .disable        = fsidiv_disable,
+};
+
+int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
+{
+        struct clk_mapping *map;
+        int i;
+
+        for (i = 0; i < nr; i++) {
+
+                map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
+                if (!map) {
+                        pr_err("%s: unable to alloc memory\n", __func__);
+                        return -ENOMEM;
+                }
+
+                /* clks[i].enable_reg came from SH_CLK_FSIDIV() */
+                map->phys               = (phys_addr_t)clks[i].enable_reg;
+                map->len                = 8;
+
+                clks[i].enable_reg      = 0; /* remove .enable_reg */
+                clks[i].ops             = &fsidiv_clk_ops;
+                clks[i].mapping         = map;
+
+                clk_register(&clks[i]);
+        }
+
+        return 0;
+}
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index fb0e0f0bed0e..12e5249d053e 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1654,7 +1654,8 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
 #endif
 
 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
-        defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
+        defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
+        defined(CONFIG_SOC_EXYNOS5440)
 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
         .info = &(struct s3c24xx_uart_info) {
                 .name           = "Samsung Exynos4 UART",
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index 82e2b89d4480..f56d185790ea 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -113,6 +113,7 @@ config UIO_NETX
 config UIO_PRUSS
         tristate "Texas Instruments PRUSS driver"
         depends on ARCH_DAVINCI_DA850
+        select GENERIC_ALLOCATOR
         help
           PRUSS driver for OMAPL138/DA850/AM18XX devices
           PRUSS driver requires user space components, examples and user space
diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
index cce0f78341cc..6e2ab007fe9c 100644
--- a/drivers/uio/uio_pruss.c
+++ b/drivers/uio/uio_pruss.c
@@ -25,7 +25,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
-#include <mach/sram.h>
+#include <linux/genalloc.h>
 
 #define DRV_NAME "pruss_uio"
 #define DRV_VERSION "1.0"
@@ -65,10 +65,11 @@ struct uio_pruss_dev {
         dma_addr_t sram_paddr;
         dma_addr_t ddr_paddr;
         void __iomem *prussio_vaddr;
-        void *sram_vaddr;
+        unsigned long sram_vaddr;
         void *ddr_vaddr;
         unsigned int hostirq_start;
         unsigned int pintc_base;
+        struct gen_pool *sram_pool;
 };
 
 static irqreturn_t pruss_handler(int irq, struct uio_info *info)
@@ -106,7 +107,9 @@ static void pruss_cleanup(struct platform_device *dev,
                         gdev->ddr_paddr);
         }
         if (gdev->sram_vaddr)
-                sram_free(gdev->sram_vaddr, sram_pool_sz);
+                gen_pool_free(gdev->sram_pool,
+                              gdev->sram_vaddr,
+                              sram_pool_sz);
         kfree(gdev->info);
         clk_put(gdev->pruss_clk);
         kfree(gdev);
@@ -152,10 +155,17 @@ static int pruss_probe(struct platform_device *dev)
                 goto out_free;
         }
 
-        gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr));
-        if (!gdev->sram_vaddr) {
-                dev_err(&dev->dev, "Could not allocate SRAM pool\n");
-                goto out_free;
+        if (pdata->sram_pool) {
+                gdev->sram_pool = pdata->sram_pool;
+                gdev->sram_vaddr =
+                        gen_pool_alloc(gdev->sram_pool, sram_pool_sz);
+                if (!gdev->sram_vaddr) {
+                        dev_err(&dev->dev, "Could not allocate SRAM pool\n");
+                        goto out_free;
+                }
+                gdev->sram_paddr =
+                        gen_pool_virt_to_phys(gdev->sram_pool,
+                                              gdev->sram_vaddr);
         }
 
         gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
diff --git a/drivers/video/clps711xfb.c b/drivers/video/clps711xfb.c
index f994c8b8f10a..63ecdf8f7baf 100644
--- a/drivers/video/clps711xfb.c
+++ b/drivers/video/clps711xfb.c
@@ -22,19 +22,15 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/fb.h>
 #include <linux/init.h>
-#include <linux/proc_fs.h>
 #include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <linux/uaccess.h>
 
-#include <mach/syspld.h>
-
 struct fb_info  *cfb;
 
 #define CMAP_MAX_SIZE   16
@@ -162,44 +158,12 @@ clps7111fb_set_par(struct fb_info *info)
 
 static int clps7111fb_blank(int blank, struct fb_info *info)
 {
-        if (blank) {
-                if (machine_is_edb7211()) {
-                        /* Turn off the LCD backlight. */
-                        clps_writeb(clps_readb(PDDR) & ~EDB_PD3_LCDBL, PDDR);
-
-                        /* Power off the LCD DC-DC converter. */
-                        clps_writeb(clps_readb(PDDR) & ~EDB_PD1_LCD_DC_DC_EN, PDDR);
-
-                        /* Delay for a little while (half a second). */
-                        udelay(100);
-
-                        /* Power off the LCD panel. */
-                        clps_writeb(clps_readb(PDDR) & ~EDB_PD2_LCDEN, PDDR);
-
-                        /* Power off the LCD controller. */
-                        clps_writel(clps_readl(SYSCON1) & ~SYSCON1_LCDEN, 
-                                        SYSCON1);
-                }
-        } else {
-                if (machine_is_edb7211()) {
-                        /* Power up the LCD controller. */
-                        clps_writel(clps_readl(SYSCON1) | SYSCON1_LCDEN,
-                                        SYSCON1);
-
-                        /* Power up the LCD panel. */
-                        clps_writeb(clps_readb(PDDR) | EDB_PD2_LCDEN, PDDR);
-
-                        /* Delay for a little while. */
-                        udelay(100);
+        /* Enable/Disable LCD controller. */
+        if (blank)
+                clps_writel(clps_readl(SYSCON1) & ~SYSCON1_LCDEN, SYSCON1);
+        else
+                clps_writel(clps_readl(SYSCON1) | SYSCON1_LCDEN, SYSCON1);
 
-                        /* Power up the LCD DC-DC converter. */
-                        clps_writeb(clps_readb(PDDR) | EDB_PD1_LCD_DC_DC_EN,
-                                        PDDR);
-
-                        /* Turn on the LCD backlight. */
-                        clps_writeb(clps_readb(PDDR) | EDB_PD3_LCDBL, PDDR);
-                }
-        }
         return 0;
 }
 
@@ -214,63 +178,7 @@ static struct fb_ops clps7111fb_ops = {
         .fb_imageblit   = cfb_imageblit,
 };
 
-static int backlight_proc_show(struct seq_file *m, void *v)
-{
-        if (machine_is_edb7211()) {
-                seq_printf(m, "%d\n",
-                                (clps_readb(PDDR) & EDB_PD3_LCDBL) ? 1 : 0);
-        }
-
-        return 0;
-}
-
-static int backlight_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, backlight_proc_show, NULL);
-}
-
-static ssize_t backlight_proc_write(struct file *file, const char *buffer,
-                                    size_t count, loff_t *pos)
-{
-        unsigned char char_value;
-        int value;
-
-        if (count < 1) {
-                return -EINVAL;
-        }
-
-        if (copy_from_user(&char_value, buffer, 1)) 
-                return -EFAULT;
-
-        value = char_value - '0';
-
-        if (machine_is_edb7211()) {
-                unsigned char port_d;
-
-                port_d = clps_readb(PDDR);
-
-                if (value) {
-                        port_d |= EDB_PD3_LCDBL;
-                } else {
-                        port_d &= ~EDB_PD3_LCDBL;
-                }
-
-                clps_writeb(port_d, PDDR);
-        }
-
-        return count;
-}
-
-static const struct file_operations backlight_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = backlight_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .write          = backlight_proc_write,
-};
-
-static void __init clps711x_guess_lcd_params(struct fb_info *info)
+static void __devinit clps711x_guess_lcd_params(struct fb_info *info)
 {
         unsigned int lcdcon, syscon, size;
         unsigned long phys_base = PAGE_OFFSET;
@@ -358,7 +266,7 @@ static void __init clps711x_guess_lcd_params(struct fb_info *info)
         info->fix.type       = FB_TYPE_PACKED_PIXELS;
 }
 
-int __init clps711xfb_init(void)
+static int __devinit clps711x_fb_probe(struct platform_device *pdev)
 {
         int err = -ENOMEM;
 
@@ -378,55 +286,29 @@ int __init clps711xfb_init(void)
 
         fb_alloc_cmap(&cfb->cmap, CMAP_MAX_SIZE, 0);
 
-        if (!proc_create("backlight", 0444, NULL, &backlight_proc_fops)) {
-                printk("Couldn't create the /proc entry for the backlight.\n");
-                return -EINVAL;
-        }
-
-        /*
-         * Power up the LCD
-         */
-        if (machine_is_p720t()) {
-                PLD_LCDEN = PLD_LCDEN_EN;
-                PLD_PWR |= (PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-        }
-
-        if (machine_is_edb7211()) {
-                /* Power up the LCD panel. */
-                clps_writeb(clps_readb(PDDR) | EDB_PD2_LCDEN, PDDR);
-
-                /* Delay for a little while. */
-                udelay(100);
-
-                /* Power up the LCD DC-DC converter. */
-                clps_writeb(clps_readb(PDDR) | EDB_PD1_LCD_DC_DC_EN, PDDR);
-
-                /* Turn on the LCD backlight. */
-                clps_writeb(clps_readb(PDDR) | EDB_PD3_LCDBL, PDDR);
-        }
-
         err = register_framebuffer(cfb);
 
 out:    return err;
 }
 
-static void __exit clps711xfb_exit(void)
+static int __devexit clps711x_fb_remove(struct platform_device *pdev)
 {
         unregister_framebuffer(cfb);
         kfree(cfb);
 
-        /*
-         * Power down the LCD
-         */
-        if (machine_is_p720t()) {
-                PLD_LCDEN = 0;
-                PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-        }
+        return 0;
 }
 
-module_init(clps711xfb_init);
-module_exit(clps711xfb_exit);
+static struct platform_driver clps711x_fb_driver = {
+        .driver = {
+                .name   = "video-clps711x",
+                .owner  = THIS_MODULE,
+        },
+        .probe  = clps711x_fb_probe,
+        .remove = __devexit_p(clps711x_fb_remove),
+};
+module_platform_driver(clps711x_fb_driver);
 
 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
-MODULE_DESCRIPTION("CLPS711x framebuffer driver");
+MODULE_DESCRIPTION("CLPS711X framebuffer driver");
 MODULE_LICENSE("GPL");
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000000000000..e074fdd5a236
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+void __init sunxi_init_clocks(void);
+
+#endif
diff --git a/include/linux/irqchip/sunxi.h b/include/linux/irqchip/sunxi.h
new file mode 100644
index 000000000000..1fe2c2260e2b
--- /dev/null
+++ b/include/linux/irqchip/sunxi.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_IRQCHIP_SUNXI_H
+#define __LINUX_IRQCHIP_SUNXI_H
+
+#include <asm/exception.h>
+
+extern void sunxi_init_irq(void);
+
+extern asmlinkage void __exception_irq_entry sunxi_handle_irq(
+        struct pt_regs *regs);
+
+#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/include/linux/irqchip/versatile-fpga.h
index 1fac9651d3ca..1fac9651d3ca 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/include/linux/irqchip/versatile-fpga.h
diff --git a/include/linux/platform_data/uio_pruss.h b/include/linux/platform_data/uio_pruss.h
index f39140aabc6f..3d47d219827f 100644
--- a/include/linux/platform_data/uio_pruss.h
+++ b/include/linux/platform_data/uio_pruss.h
@@ -20,6 +20,7 @@
 
 /* To configure the PRUSS INTC base offset for UIO driver */
 struct uio_pruss_pdata {
-        u32     pintc_base;
+        u32             pintc_base;
+        struct gen_pool *sram_pool;
 };
 #endif /* _UIO_PRUSS_H_ */
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 50910913b268..60c72395ec6b 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -199,4 +199,13 @@ int sh_clk_div6_reparent_register(struct clk *clks, int nr);
 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
 
+/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
+#define SH_CLK_FSIDIV(_reg, _parent)            \
+{                                               \
+        .enable_reg = (void __iomem *)_reg,     \
+        .parent         = _parent,              \
+}
+
+int sh_clk_fsidiv_register(struct clk *clks, int nr);
+
 #endif /* __SH_CLOCK_H */
diff --git a/include/linux/sunxi_timer.h b/include/linux/sunxi_timer.h
new file mode 100644
index 000000000000..b9165bba6e61
--- /dev/null
+++ b/include/linux/sunxi_timer.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUNXI_TIMER_H
+#define __SUNXI_TIMER_H
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer sunxi_timer;
+
+#endif
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
new file mode 100644
index 000000000000..c52215ff4245
--- /dev/null
+++ b/include/linux/vexpress.h
@@ -0,0 +1,121 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+#ifndef _LINUX_VEXPRESS_H
+#define _LINUX_VEXPRESS_H
+
+#include <linux/device.h>
+
+#define VEXPRESS_SITE_MB                0
+#define VEXPRESS_SITE_DB1               1
+#define VEXPRESS_SITE_DB2               2
+#define VEXPRESS_SITE_MASTER            0xf
+
+#define VEXPRESS_CONFIG_STATUS_DONE     0
+#define VEXPRESS_CONFIG_STATUS_WAIT     1
+
+#define VEXPRESS_GPIO_MMC_CARDIN        0
+#define VEXPRESS_GPIO_MMC_WPROT         1
+#define VEXPRESS_GPIO_FLASH_WPn         2
+
+#define VEXPRESS_RES_FUNC(_site, _func) \
+{                                       \
+        .start = (_site),               \
+        .end = (_func),                 \
+        .flags = IORESOURCE_BUS,        \
+}
+
+/* Config bridge API */
+
+/**
+ * struct vexpress_config_bridge_info - description of the platform
+ * configuration infrastructure bridge.
+ *
+ * @name:       Bridge name
+ *
+ * @func_get:   Obtains pointer to a configuration function for a given
+ *              device or a Device Tree node, to be used with @func_put
+ *              and @func_exec. The node pointer should take precedence
+ *              over device pointer when both are passed.
+ *
+ * @func_put:   Tells the bridge that the function will not be used any
+ *              more, so all allocated resources can be released.
+ *
+ * @func_exec:  Executes a configuration function read or write operation.
+ *              The offset selects a 32 bit word of the value accessed.
+ *              Must return VEXPRESS_CONFIG_STATUS_DONE when operation
+ *              is finished immediately, VEXPRESS_CONFIG_STATUS_WAIT when
+ *              will be completed in some time or negative value in case
+ *              of error.
+ */
+struct vexpress_config_bridge_info {
+        const char *name;
+        void *(*func_get)(struct device *dev, struct device_node *node);
+        void (*func_put)(void *func);
+        int (*func_exec)(void *func, int offset, bool write, u32 *data);
+};
+
+struct vexpress_config_bridge;
+
+struct vexpress_config_bridge *vexpress_config_bridge_register(
+                struct device_node *node,
+                struct vexpress_config_bridge_info *info);
+void vexpress_config_bridge_unregister(struct vexpress_config_bridge *bridge);
+
+void vexpress_config_complete(struct vexpress_config_bridge *bridge,
+                int status);
+
+/* Config function API */
+
+struct vexpress_config_func;
+
+struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
+                struct device_node *node);
+#define vexpress_config_func_get_by_dev(dev) \
+                __vexpress_config_func_get(dev, NULL)
+#define vexpress_config_func_get_by_node(node) \
+                __vexpress_config_func_get(NULL, node)
+void vexpress_config_func_put(struct vexpress_config_func *func);
+
+/* Both may sleep! */
+int vexpress_config_read(struct vexpress_config_func *func, int offset,
+                u32 *data);
+int vexpress_config_write(struct vexpress_config_func *func, int offset,
+                u32 data);
+
+/* Platform control */
+
+u32 vexpress_get_procid(int site);
+u32 vexpress_get_hbi(int site);
+void *vexpress_get_24mhz_clock_base(void);
+void vexpress_flags_set(u32 data);
+
+#define vexpress_get_site_by_node(node) __vexpress_get_site(NULL, node)
+#define vexpress_get_site_by_dev(dev) __vexpress_get_site(dev, NULL)
+unsigned __vexpress_get_site(struct device *dev, struct device_node *node);
+
+void vexpress_sysreg_early_init(void __iomem *base);
+void vexpress_sysreg_of_early_init(void);
+
+void vexpress_power_off(void);
+void vexpress_restart(char str, const char *cmd);
+
+/* Clocks */
+
+struct clk *vexpress_osc_setup(struct device *dev);
+void vexpress_osc_of_setup(struct device_node *node);
+
+void vexpress_clk_init(void __iomem *sp810_base);
+void vexpress_clk_of_init(void);
+
+#endif