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Diffstat (limited to 'arch/arm/mach-clps711x/include/mach/hardware.h')
-rw-r--r--arch/arm/mach-clps711x/include/mach/hardware.h67
1 files changed, 10 insertions, 57 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 8497775d6ee5..2f23dd5d73e4 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -24,7 +24,10 @@
24 24
25#include <mach/clps711x.h> 25#include <mach/clps711x.h>
26 26
27#define CLPS711X_VIRT_BASE IOMEM(0xff000000) 27#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \
28 (((x) >> 2) & 0x3c000000)))
29
30#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
28 31
29#ifndef __ASSEMBLY__ 32#ifndef __ASSEMBLY__
30#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) 33#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
@@ -61,67 +64,17 @@
61#define CS7_PHYS_BASE (0x00000000) 64#define CS7_PHYS_BASE (0x00000000)
62#endif 65#endif
63 66
64#define SYSPLD_VIRT_BASE 0xfe000000 67#define CLPS711X_SRAM_BASE CS6_PHYS_BASE
65#define SYSPLD_BASE SYSPLD_VIRT_BASE 68#define CLPS711X_SRAM_SIZE (48 * 1024)
66
67#if defined (CONFIG_ARCH_CDB89712)
68
69#define ETHER_START 0x20000000
70#define ETHER_SIZE 0x1000
71#define ETHER_BASE 0xfe000000
72
73#endif
74 69
70#define CLPS711X_SDRAM0_BASE (0xc0000000)
71#define CLPS711X_SDRAM1_BASE (0xd0000000)
75 72
76#if defined (CONFIG_ARCH_EDB7211) 73#if defined (CONFIG_ARCH_EDB7211)
77 74
78/* 75/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
79 * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 76#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
80 * and repeat across it. This is the mapping for it.
81 *
82 * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
83 * was cause for much consternation and headscratching. This should probably
84 * be made a compile/run time kernel option.
85 */
86#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
87
88#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
89
90
91/*
92 * The CS8900A ethernet chip has its I/O registers wired to chip select 2
93 * (nCS2). This is the mapping for it.
94 *
95 * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
96 * was cause for much consternation and headscratching. This should probably
97 * be made a compile/run time kernel option.
98 */
99#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
100
101#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
102
103
104/*
105 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
106 * for them.
107 *
108 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
109 * in jumpered boot mode.
110 */
111#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
112#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
113
114#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
115#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
116 77
117#endif /* CONFIG_ARCH_EDB7211 */ 78#endif /* CONFIG_ARCH_EDB7211 */
118 79
119/*
120 * Relevant bits in port D, which controls power to the various parts of
121 * the LCD on the EDB7211.
122 */
123#define EDB_PD1_LCD_DC_DC_EN (1<<1)
124#define EDB_PD2_LCDEN (1<<2)
125#define EDB_PD3_LCDBL (1<<3)
126
127#endif 80#endif