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Diffstat (limited to 'arch/arm/boot/dts/imx51.dtsi')
-rw-r--r--arch/arm/boot/dts/imx51.dtsi124
1 files changed, 124 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 54aea74769a1..2781e47cff0d 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -62,6 +62,13 @@
62 interrupt-parent = <&tzic>; 62 interrupt-parent = <&tzic>;
63 ranges; 63 ranges;
64 64
65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
65 aips@70000000 { /* AIPS1 */ 72 aips@70000000 { /* AIPS1 */
66 compatible = "fsl,aips-bus", "simple-bus"; 73 compatible = "fsl,aips-bus", "simple-bus";
67 #address-cells = <1>; 74 #address-cells = <1>;
@@ -80,6 +87,8 @@
80 compatible = "fsl,imx51-esdhc"; 87 compatible = "fsl,imx51-esdhc";
81 reg = <0x70004000 0x4000>; 88 reg = <0x70004000 0x4000>;
82 interrupts = <1>; 89 interrupts = <1>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
83 status = "disabled"; 92 status = "disabled";
84 }; 93 };
85 94
@@ -87,6 +96,8 @@
87 compatible = "fsl,imx51-esdhc"; 96 compatible = "fsl,imx51-esdhc";
88 reg = <0x70008000 0x4000>; 97 reg = <0x70008000 0x4000>;
89 interrupts = <2>; 98 interrupts = <2>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
90 status = "disabled"; 101 status = "disabled";
91 }; 102 };
92 103
@@ -94,6 +105,8 @@
94 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 105 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
95 reg = <0x7000c000 0x4000>; 106 reg = <0x7000c000 0x4000>;
96 interrupts = <33>; 107 interrupts = <33>;
108 clocks = <&clks 32>, <&clks 33>;
109 clock-names = "ipg", "per";
97 status = "disabled"; 110 status = "disabled";
98 }; 111 };
99 112
@@ -103,6 +116,8 @@
103 compatible = "fsl,imx51-ecspi"; 116 compatible = "fsl,imx51-ecspi";
104 reg = <0x70010000 0x4000>; 117 reg = <0x70010000 0x4000>;
105 interrupts = <36>; 118 interrupts = <36>;
119 clocks = <&clks 51>, <&clks 52>;
120 clock-names = "ipg", "per";
106 status = "disabled"; 121 status = "disabled";
107 }; 122 };
108 123
@@ -110,6 +125,7 @@
110 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 125 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
111 reg = <0x70014000 0x4000>; 126 reg = <0x70014000 0x4000>;
112 interrupts = <30>; 127 interrupts = <30>;
128 clocks = <&clks 49>;
113 fsl,fifo-depth = <15>; 129 fsl,fifo-depth = <15>;
114 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 130 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
115 status = "disabled"; 131 status = "disabled";
@@ -119,6 +135,8 @@
119 compatible = "fsl,imx51-esdhc"; 135 compatible = "fsl,imx51-esdhc";
120 reg = <0x70020000 0x4000>; 136 reg = <0x70020000 0x4000>;
121 interrupts = <3>; 137 interrupts = <3>;
138 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
139 clock-names = "ipg", "ahb", "per";
122 status = "disabled"; 140 status = "disabled";
123 }; 141 };
124 142
@@ -126,6 +144,8 @@
126 compatible = "fsl,imx51-esdhc"; 144 compatible = "fsl,imx51-esdhc";
127 reg = <0x70024000 0x4000>; 145 reg = <0x70024000 0x4000>;
128 interrupts = <4>; 146 interrupts = <4>;
147 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
148 clock-names = "ipg", "ahb", "per";
129 status = "disabled"; 149 status = "disabled";
130 }; 150 };
131 }; 151 };
@@ -202,12 +222,14 @@
202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 222 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
203 reg = <0x73f98000 0x4000>; 223 reg = <0x73f98000 0x4000>;
204 interrupts = <58>; 224 interrupts = <58>;
225 clocks = <&clks 0>;
205 }; 226 };
206 227
207 wdog@73f9c000 { /* WDOG2 */ 228 wdog@73f9c000 { /* WDOG2 */
208 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 229 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
209 reg = <0x73f9c000 0x4000>; 230 reg = <0x73f9c000 0x4000>;
210 interrupts = <59>; 231 interrupts = <59>;
232 clocks = <&clks 0>;
211 status = "disabled"; 233 status = "disabled";
212 }; 234 };
213 235
@@ -295,6 +317,66 @@
295 }; 317 };
296 }; 318 };
297 319
320 ipu_disp1 {
321 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
322 fsl,pins = <
323 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
324 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
325 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
326 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
327 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
328 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
329 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
330 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
331 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
332 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
333 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
334 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
335 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
336 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
337 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
338 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
339 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
340 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
341 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
342 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
343 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
344 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
345 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
346 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
347 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
348 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
349 >;
350 };
351 };
352
353 ipu_disp2 {
354 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
355 fsl,pins = <
356 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
357 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
358 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
359 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
360 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
361 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
362 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
363 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
364 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
365 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
366 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
367 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
368 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
369 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
370 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
371 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
372 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
373 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
374 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
375 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
376 >;
377 };
378 };
379
298 uart1 { 380 uart1 {
299 pinctrl_uart1_1: uart1grp-1 { 381 pinctrl_uart1_1: uart1grp-1 {
300 fsl,pins = < 382 fsl,pins = <
@@ -327,10 +409,30 @@
327 }; 409 };
328 }; 410 };
329 411
412 pwm1: pwm@73fb4000 {
413 #pwm-cells = <2>;
414 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415 reg = <0x73fb4000 0x4000>;
416 clocks = <&clks 37>, <&clks 38>;
417 clock-names = "ipg", "per";
418 interrupts = <61>;
419 };
420
421 pwm2: pwm@73fb8000 {
422 #pwm-cells = <2>;
423 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
424 reg = <0x73fb8000 0x4000>;
425 clocks = <&clks 39>, <&clks 40>;
426 clock-names = "ipg", "per";
427 interrupts = <94>;
428 };
429
330 uart1: serial@73fbc000 { 430 uart1: serial@73fbc000 {
331 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 431 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
332 reg = <0x73fbc000 0x4000>; 432 reg = <0x73fbc000 0x4000>;
333 interrupts = <31>; 433 interrupts = <31>;
434 clocks = <&clks 28>, <&clks 29>;
435 clock-names = "ipg", "per";
334 status = "disabled"; 436 status = "disabled";
335 }; 437 };
336 438
@@ -338,8 +440,17 @@
338 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 440 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
339 reg = <0x73fc0000 0x4000>; 441 reg = <0x73fc0000 0x4000>;
340 interrupts = <32>; 442 interrupts = <32>;
443 clocks = <&clks 30>, <&clks 31>;
444 clock-names = "ipg", "per";
341 status = "disabled"; 445 status = "disabled";
342 }; 446 };
447
448 clks: ccm@73fd4000{
449 compatible = "fsl,imx51-ccm";
450 reg = <0x73fd4000 0x4000>;
451 interrupts = <0 71 0x04 0 72 0x04>;
452 #clock-cells = <1>;
453 };
343 }; 454 };
344 455
345 aips@80000000 { /* AIPS2 */ 456 aips@80000000 { /* AIPS2 */
@@ -355,6 +466,8 @@
355 compatible = "fsl,imx51-ecspi"; 466 compatible = "fsl,imx51-ecspi";
356 reg = <0x83fac000 0x4000>; 467 reg = <0x83fac000 0x4000>;
357 interrupts = <37>; 468 interrupts = <37>;
469 clocks = <&clks 53>, <&clks 54>;
470 clock-names = "ipg", "per";
358 status = "disabled"; 471 status = "disabled";
359 }; 472 };
360 473
@@ -362,6 +475,8 @@
362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 475 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
363 reg = <0x83fb0000 0x4000>; 476 reg = <0x83fb0000 0x4000>;
364 interrupts = <6>; 477 interrupts = <6>;
478 clocks = <&clks 56>, <&clks 56>;
479 clock-names = "ipg", "ahb";
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 480 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
366 }; 481 };
367 482
@@ -371,6 +486,8 @@
371 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 486 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
372 reg = <0x83fc0000 0x4000>; 487 reg = <0x83fc0000 0x4000>;
373 interrupts = <38>; 488 interrupts = <38>;
489 clocks = <&clks 55>, <&clks 0>;
490 clock-names = "ipg", "per";
374 status = "disabled"; 491 status = "disabled";
375 }; 492 };
376 493
@@ -380,6 +497,7 @@
380 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
381 reg = <0x83fc4000 0x4000>; 498 reg = <0x83fc4000 0x4000>;
382 interrupts = <63>; 499 interrupts = <63>;
500 clocks = <&clks 35>;
383 status = "disabled"; 501 status = "disabled";
384 }; 502 };
385 503
@@ -389,6 +507,7 @@
389 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 507 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
390 reg = <0x83fc8000 0x4000>; 508 reg = <0x83fc8000 0x4000>;
391 interrupts = <62>; 509 interrupts = <62>;
510 clocks = <&clks 34>;
392 status = "disabled"; 511 status = "disabled";
393 }; 512 };
394 513
@@ -396,6 +515,7 @@
396 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 515 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
397 reg = <0x83fcc000 0x4000>; 516 reg = <0x83fcc000 0x4000>;
398 interrupts = <29>; 517 interrupts = <29>;
518 clocks = <&clks 48>;
399 fsl,fifo-depth = <15>; 519 fsl,fifo-depth = <15>;
400 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 520 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
401 status = "disabled"; 521 status = "disabled";
@@ -411,6 +531,7 @@
411 compatible = "fsl,imx51-nand"; 531 compatible = "fsl,imx51-nand";
412 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 532 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
413 interrupts = <8>; 533 interrupts = <8>;
534 clocks = <&clks 60>;
414 status = "disabled"; 535 status = "disabled";
415 }; 536 };
416 537
@@ -418,6 +539,7 @@
418 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 539 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
419 reg = <0x83fe8000 0x4000>; 540 reg = <0x83fe8000 0x4000>;
420 interrupts = <96>; 541 interrupts = <96>;
542 clocks = <&clks 50>;
421 fsl,fifo-depth = <15>; 543 fsl,fifo-depth = <15>;
422 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ 544 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
423 status = "disabled"; 545 status = "disabled";
@@ -427,6 +549,8 @@
427 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 549 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
428 reg = <0x83fec000 0x4000>; 550 reg = <0x83fec000 0x4000>;
429 interrupts = <87>; 551 interrupts = <87>;
552 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
553 clock-names = "ipg", "ahb", "ptp";
430 status = "disabled"; 554 status = "disabled";
431 }; 555 };
432 }; 556 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 10:19:27 -0500