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path: root/arch/arm/mach-imx/clk-pllv3.c
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Diffstat (limited to 'arch/arm/mach-imx/clk-pllv3.c')
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c72
1 files changed, 4 insertions, 68 deletions
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 36aac947bce1..d09bc3df9a7a 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,7 +31,6 @@
31 * @clk_hw: clock source 31 * @clk_hw: clock source
32 * @base: base address of PLL registers 32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL 33 * @powerup_set: set POWER bit to power up the PLL
34 * @gate_mask: mask of gate bits
35 * @div_mask: mask of divider bits 34 * @div_mask: mask of divider bits
36 * 35 *
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 {
41 struct clk_hw hw; 40 struct clk_hw hw;
42 void __iomem *base; 41 void __iomem *base;
43 bool powerup_set; 42 bool powerup_set;
44 u32 gate_mask;
45 u32 div_mask; 43 u32 div_mask;
46}; 44};
47 45
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
89 u32 val; 87 u32 val;
90 88
91 val = readl_relaxed(pll->base); 89 val = readl_relaxed(pll->base);
92 val |= pll->gate_mask; 90 val |= BM_PLL_ENABLE;
93 writel_relaxed(val, pll->base); 91 writel_relaxed(val, pll->base);
94 92
95 return 0; 93 return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
101 u32 val; 99 u32 val;
102 100
103 val = readl_relaxed(pll->base); 101 val = readl_relaxed(pll->base);
104 val &= ~pll->gate_mask; 102 val &= ~BM_PLL_ENABLE;
105 writel_relaxed(val, pll->base); 103 writel_relaxed(val, pll->base);
106} 104}
107 105
@@ -287,66 +285,7 @@ static const struct clk_ops clk_pllv3_av_ops = {
287static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 285static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
288 unsigned long parent_rate) 286 unsigned long parent_rate)
289{ 287{
290 struct clk_pllv3 *pll = to_clk_pllv3(hw); 288 return 500000000;
291 u32 div = readl_relaxed(pll->base) & pll->div_mask;
292
293 switch (div) {
294 case 0:
295 return 25000000;
296 case 1:
297 return 50000000;
298 case 2:
299 return 100000000;
300 case 3:
301 return 125000000;
302 }
303
304 return 0;
305}
306
307static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long *prate)
309{
310 if (rate >= 125000000)
311 rate = 125000000;
312 else if (rate >= 100000000)
313 rate = 100000000;
314 else if (rate >= 50000000)
315 rate = 50000000;
316 else
317 rate = 25000000;
318 return rate;
319}
320
321static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
322 unsigned long parent_rate)
323{
324 struct clk_pllv3 *pll = to_clk_pllv3(hw);
325 u32 val, div;
326
327 switch (rate) {
328 case 25000000:
329 div = 0;
330 break;
331 case 50000000:
332 div = 1;
333 break;
334 case 100000000:
335 div = 2;
336 break;
337 case 125000000:
338 div = 3;
339 break;
340 default:
341 return -EINVAL;
342 }
343
344 val = readl_relaxed(pll->base);
345 val &= ~pll->div_mask;
346 val |= div;
347 writel_relaxed(val, pll->base);
348
349 return 0;
350} 289}
351 290
352static const struct clk_ops clk_pllv3_enet_ops = { 291static const struct clk_ops clk_pllv3_enet_ops = {
@@ -355,8 +294,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
355 .enable = clk_pllv3_enable, 294 .enable = clk_pllv3_enable,
356 .disable = clk_pllv3_disable, 295 .disable = clk_pllv3_disable,
357 .recalc_rate = clk_pllv3_enet_recalc_rate, 296 .recalc_rate = clk_pllv3_enet_recalc_rate,
358 .round_rate = clk_pllv3_enet_round_rate,
359 .set_rate = clk_pllv3_enet_set_rate,
360}; 297};
361 298
362static const struct clk_ops clk_pllv3_mlb_ops = { 299static const struct clk_ops clk_pllv3_mlb_ops = {
@@ -368,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
368 305
369struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 306struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
370 const char *parent_name, void __iomem *base, 307 const char *parent_name, void __iomem *base,
371 u32 gate_mask, u32 div_mask) 308 u32 div_mask)
372{ 309{
373 struct clk_pllv3 *pll; 310 struct clk_pllv3 *pll;
374 const struct clk_ops *ops; 311 const struct clk_ops *ops;
@@ -400,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
400 ops = &clk_pllv3_ops; 337 ops = &clk_pllv3_ops;
401 } 338 }
402 pll->base = base; 339 pll->base = base;
403 pll->gate_mask = gate_mask;
404 pll->div_mask = div_mask; 340 pll->div_mask = div_mask;
405 341
406 init.name = name; 342 init.name = name;