Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC updates from Olof Johansson:
 "This contains the bulk of new SoC development for this merge window.

  Two new platforms have been added, the sunxi platforms (Allwinner A1x
  SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
  series of ARMv7 platforms from them, where the hope is that we can
  keep the platform code generic enough to have them all share one mach
  directory.  The new Broadcom platform is contributed by Christian
  Daudt.

  Highbank has grown support for Calxeda's next generation of hardware,
  ECX-2000.

  clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
  also taken on maintainership of the platform.

  Beyond this there has been a bunch of work from a number of people on
  converting more platforms to IRQ domains, pinctrl conversion, cleanup
  and general feature enablement across most of the active platforms."

Fix up trivial conflicts as per Olof.

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
  mfd: vexpress-sysreg: Remove LEDs code
  irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
  clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
  irq: versatile: delete dangling variable
  ARM: sunxi: add missing include for mdelay()
  ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
  ARM: dts: add node for PL330 MDMA1 controller for exynos4
  ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
  ARM: EXYNOS: add UART3 to DEBUG_LL ports
  ARM: S3C24XX: Add clkdev entry for camif-upll clock
  ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
  ARM: sunxi: Add missing sun4i.dtsi file
  pinctrl: samsung: Do not initialise statics to 0
  ARM i.MX6: remove gate_mask from pllv3
  ARM i.MX6: Fix ethernet PLL clocks
  ARM i.MX6: rename PLLs according to datasheet
  ARM i.MX6: Add pwm support
  ARM i.MX51: Add pwm support
  ARM i.MX53: Add pwm support
  ARM: mx5: Replace clk_register_clkdev with clock DT lookup
  ...

1 files changed, 4 insertions, 68 deletions

diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 36aac947bce1..d09bc3df9a7a 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,7 +31,6 @@
  * @clk_hw:      clock source
  * @base:        base address of PLL registers
  * @powerup_set: set POWER bit to power up the PLL
- * @gate_mask:   mask of gate bits
  * @div_mask:    mask of divider bits
  *
  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 {
         struct clk_hw   hw;
         void __iomem    *base;
         bool            powerup_set;
-        u32             gate_mask;
         u32             div_mask;
 };
 
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
         u32 val;
 
         val = readl_relaxed(pll->base);
-        val |= pll->gate_mask;
+        val |= BM_PLL_ENABLE;
         writel_relaxed(val, pll->base);
 
         return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
         u32 val;
 
         val = readl_relaxed(pll->base);
-        val &= ~pll->gate_mask;
+        val &= ~BM_PLL_ENABLE;
         writel_relaxed(val, pll->base);
 }
 
@@ -287,66 +285,7 @@ static const struct clk_ops clk_pllv3_av_ops = {
 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
                                                 unsigned long parent_rate)
 {
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 div = readl_relaxed(pll->base) & pll->div_mask;
-
-        switch (div) {
-        case 0:
-                return 25000000;
-        case 1:
-                return 50000000;
-        case 2:
-                return 100000000;
-        case 3:
-                return 125000000;
-        }
-
-        return 0;
-}
-
-static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
-                                      unsigned long *prate)
-{
-        if (rate >= 125000000)
-                rate = 125000000;
-        else if (rate >= 100000000)
-                rate = 100000000;
-        else if (rate >= 50000000)
-                rate = 50000000;
-        else
-                rate = 25000000;
-        return rate;
-}
-
-static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val, div;
-
-        switch (rate) {
-        case 25000000:
-                div = 0;
-                break;
-        case 50000000:
-                div = 1;
-                break;
-        case 100000000:
-                div = 2;
-                break;
-        case 125000000:
-                div = 3;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        val = readl_relaxed(pll->base);
-        val &= ~pll->div_mask;
-        val |= div;
-        writel_relaxed(val, pll->base);
-
-        return 0;
+        return 500000000;
 }
 
 static const struct clk_ops clk_pllv3_enet_ops = {
@@ -355,8 +294,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
         .enable         = clk_pllv3_enable,
         .disable        = clk_pllv3_disable,
         .recalc_rate    = clk_pllv3_enet_recalc_rate,
-        .round_rate     = clk_pllv3_enet_round_rate,
-        .set_rate       = clk_pllv3_enet_set_rate,
 };
 
 static const struct clk_ops clk_pllv3_mlb_ops = {
@@ -368,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                           const char *parent_name, void __iomem *base,
-                          u32 gate_mask, u32 div_mask)
+                          u32 div_mask)
 {
         struct clk_pllv3 *pll;
         const struct clk_ops *ops;
@@ -400,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                 ops = &clk_pllv3_ops;
         }
         pll->base = base;
-        pll->gate_mask = gate_mask;
         pll->div_mask = div_mask;
 
         init.name = name;